Fawwaz Nadzmy / mbed-STM

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targets/TARGET_NUVOTON/TARGET_M451/device/StdDriver/m451_eadc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

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<> 149:156823d33999 1 /******************************************************************************
<> 149:156823d33999 2 * @file eadc.h
<> 149:156823d33999 3 * @version V0.10
<> 149:156823d33999 4 * $Revision: 18 $
<> 149:156823d33999 5 * $Date: 15/08/11 10:26a $
<> 149:156823d33999 6 * @brief M451 series EADC driver header file
<> 149:156823d33999 7 *
<> 149:156823d33999 8 * @note
<> 149:156823d33999 9 * Copyright (C) 2013~2015 Nuvoton Technology Corp. All rights reserved.
<> 149:156823d33999 10 *****************************************************************************/
<> 149:156823d33999 11 #ifndef __EADC_H__
<> 149:156823d33999 12 #define __EADC_H__
<> 149:156823d33999 13
<> 149:156823d33999 14 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 15 /* Include related headers */
<> 149:156823d33999 16 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 17 #include "M451Series.h"
<> 149:156823d33999 18
<> 149:156823d33999 19
<> 149:156823d33999 20 #ifdef __cplusplus
<> 149:156823d33999 21 extern "C"
<> 149:156823d33999 22 {
<> 149:156823d33999 23 #endif
<> 149:156823d33999 24
<> 149:156823d33999 25
<> 149:156823d33999 26 /** @addtogroup Standard_Driver Standard Driver
<> 149:156823d33999 27 @{
<> 149:156823d33999 28 */
<> 149:156823d33999 29
<> 149:156823d33999 30 /** @addtogroup EADC_Driver EADC Driver
<> 149:156823d33999 31 @{
<> 149:156823d33999 32 */
<> 149:156823d33999 33
<> 149:156823d33999 34 /** @addtogroup EADC_EXPORTED_CONSTANTS EADC Exported Constants
<> 149:156823d33999 35 @{
<> 149:156823d33999 36 */
<> 149:156823d33999 37
<> 149:156823d33999 38 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 39 /* EADC_CTL Constant Definitions */
<> 149:156823d33999 40 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 41 #define EADC_CTL_DIFFEN_SINGLE_END (0UL<<EADC_CTL_DIFFEN_Pos) /*!< Single-end input mode */
<> 149:156823d33999 42 #define EADC_CTL_DIFFEN_DIFFERENTIAL (1UL<<EADC_CTL_DIFFEN_Pos) /*!< Differential input mode */
<> 149:156823d33999 43
<> 149:156823d33999 44 #define EADC_CTL_DMOF_STRAIGHT_BINARY (0UL<<EADC_CTL_DMOF_Pos) /*!< Select the straight binary format as the output format of the conversion result */
<> 149:156823d33999 45 #define EADC_CTL_DMOF_TWOS_COMPLEMENT (1UL<<EADC_CTL_DMOF_Pos) /*!< Select the 2's complement format as the output format of the conversion result */
<> 149:156823d33999 46
<> 149:156823d33999 47 #define EADC_CTL_SMPTSEL1 (0UL<<EADC_CTL_SMPTSEL_Pos) /*!< 1 ADC clock sampling time */
<> 149:156823d33999 48 #define EADC_CTL_SMPTSEL2 (1UL<<EADC_CTL_SMPTSEL_Pos) /*!< 2 ADC clock sampling time */
<> 149:156823d33999 49 #define EADC_CTL_SMPTSEL3 (2UL<<EADC_CTL_SMPTSEL_Pos) /*!< 3 ADC clock sampling time */
<> 149:156823d33999 50 #define EADC_CTL_SMPTSEL4 (3UL<<EADC_CTL_SMPTSEL_Pos) /*!< 4 ADC clock sampling time */
<> 149:156823d33999 51 #define EADC_CTL_SMPTSEL5 (4UL<<EADC_CTL_SMPTSEL_Pos) /*!< 5 ADC clock sampling time */
<> 149:156823d33999 52 #define EADC_CTL_SMPTSEL6 (5UL<<EADC_CTL_SMPTSEL_Pos) /*!< 6 ADC clock sampling time */
<> 149:156823d33999 53 #define EADC_CTL_SMPTSEL7 (6UL<<EADC_CTL_SMPTSEL_Pos) /*!< 7 ADC clock sampling time */
<> 149:156823d33999 54 #define EADC_CTL_SMPTSEL8 (7UL<<EADC_CTL_SMPTSEL_Pos) /*!< 8 ADC clock sampling time */
<> 149:156823d33999 55
<> 149:156823d33999 56 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 57 /* EADC_SCTL Constant Definitions */
<> 149:156823d33999 58 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 59 #define EADC_SCTL_CHSEL(x) ((x) << EADC_SCTL_CHSEL_Pos) /*!< A/D sample module channel selection */
<> 149:156823d33999 60 #define EADC_SCTL_TRGDLYDIV(x) ((x) << EADC_SCTL_TRGDLYDIV_Pos) /*!< A/D sample module start of conversion trigger delay clock divider selection */
<> 149:156823d33999 61 #define EADC_SCTL_TRGDLYCNT(x) ((x) << EADC_SCTL_TRGDLYCNT_Pos) /*!< A/D sample module start of conversion trigger delay time */
<> 149:156823d33999 62
<> 149:156823d33999 63 #define EADC_SOFTWARE_TRIGGER (0UL<<EADC_SCTL_TRGSEL_Pos) /*!< Software trigger */
<> 149:156823d33999 64 #define EADC_FALLING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin falling edge trigger */
<> 149:156823d33999 65 #define EADC_RISING_EDGE_TRIGGER (EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin rising edge trigger */
<> 149:156823d33999 66 #define EADC_FALLING_RISING_EDGE_TRIGGER (EADC_SCTL_EXTFEN_Msk | EADC_SCTL_EXTREN_Msk | (1UL<<EADC_SCTL_TRGSEL_Pos)) /*!< STADC pin both falling and rising edge trigger */
<> 149:156823d33999 67 #define EADC_ADINT0_TRIGGER (2UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT0 interrupt EOC pulse trigger */
<> 149:156823d33999 68 #define EADC_ADINT1_TRIGGER (3UL<<EADC_SCTL_TRGSEL_Pos) /*!< ADC ADINT1 interrupt EOC pulse trigger */
<> 149:156823d33999 69 #define EADC_TIMER0_TRIGGER (4UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer0 overflow pulse trigger */
<> 149:156823d33999 70 #define EADC_TIMER1_TRIGGER (5UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer1 overflow pulse trigger */
<> 149:156823d33999 71 #define EADC_TIMER2_TRIGGER (6UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer2 overflow pulse trigger */
<> 149:156823d33999 72 #define EADC_TIMER3_TRIGGER (7UL<<EADC_SCTL_TRGSEL_Pos) /*!< Timer3 overflow pulse trigger */
<> 149:156823d33999 73 #define EADC_PWM0TG0_TRIGGER (8UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG0 trigger */
<> 149:156823d33999 74 #define EADC_PWM0TG1_TRIGGER (9UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG1 trigger */
<> 149:156823d33999 75 #define EADC_PWM0TG2_TRIGGER (0xAUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG2 trigger */
<> 149:156823d33999 76 #define EADC_PWM0TG3_TRIGGER (0xBUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG3 trigger */
<> 149:156823d33999 77 #define EADC_PWM0TG4_TRIGGER (0xCUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG4 trigger */
<> 149:156823d33999 78 #define EADC_PWM0TG5_TRIGGER (0xDUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM0TG5 trigger */
<> 149:156823d33999 79 #define EADC_PWM1TG0_TRIGGER (0xEUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG0 trigger */
<> 149:156823d33999 80 #define EADC_PWM1TG1_TRIGGER (0xFUL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG1 trigger */
<> 149:156823d33999 81 #define EADC_PWM1TG2_TRIGGER (0x10UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG2 trigger */
<> 149:156823d33999 82 #define EADC_PWM1TG3_TRIGGER (0x11UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG3 trigger */
<> 149:156823d33999 83 #define EADC_PWM1TG4_TRIGGER (0x12UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG4 trigger */
<> 149:156823d33999 84 #define EADC_PWM1TG5_TRIGGER (0x13UL<<EADC_SCTL_TRGSEL_Pos) /*!< PWM1TG5 trigger */
<> 149:156823d33999 85
<> 149:156823d33999 86 #define EADC_SCTL_TRGDLYDIV_DIVIDER_1 (0<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/1 */
<> 149:156823d33999 87 #define EADC_SCTL_TRGDLYDIV_DIVIDER_2 (0x1UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/2 */
<> 149:156823d33999 88 #define EADC_SCTL_TRGDLYDIV_DIVIDER_4 (0x2UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/4 */
<> 149:156823d33999 89 #define EADC_SCTL_TRGDLYDIV_DIVIDER_16 (0x3UL<<EADC_SCTL_TRGDLYDIV_Pos) /*!< Trigger delay clock frequency is ADC_CLK/16 */
<> 149:156823d33999 90
<> 149:156823d33999 91
<> 149:156823d33999 92 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 93 /* EADC_CMP Constant Definitions */
<> 149:156823d33999 94 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 95 #define EADC_CMP_CMPCOND_LESS_THAN (0UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "less than" */
<> 149:156823d33999 96 #define EADC_CMP_CMPCOND_GREATER_OR_EQUAL (1UL<<EADC_CMP_CMPCOND_Pos) /*!< The compare condition is "greater than or equal to" */
<> 149:156823d33999 97 #define EADC_CMP_CMPWEN_ENABLE (EADC_CMP_CMPWEN_Msk) /*!< Compare window mode enable */
<> 149:156823d33999 98 #define EADC_CMP_CMPWEN_DISABLE (~EADC_CMP_CMPWEN_Msk) /*!< Compare window mode disable */
<> 149:156823d33999 99 #define EADC_CMP_ADCMPIE_ENABLE (EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt enable */
<> 149:156823d33999 100 #define EADC_CMP_ADCMPIE_DISABLE (~EADC_CMP_ADCMPIE_Msk) /*!< A/D result compare interrupt disable */
<> 149:156823d33999 101
<> 149:156823d33999 102 /*@}*/ /* end of group EADC_EXPORTED_CONSTANTS */
<> 149:156823d33999 103
<> 149:156823d33999 104 /** @addtogroup EADC_EXPORTED_FUNCTIONS EADC Exported Functions
<> 149:156823d33999 105 @{
<> 149:156823d33999 106 */
<> 149:156823d33999 107 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 108 /* EADC Macro Definitions */
<> 149:156823d33999 109 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 110
<> 149:156823d33999 111 /**
<> 149:156823d33999 112 * @brief A/D Converter Control Circuits Reset.
<> 149:156823d33999 113 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 114 * @return None
<> 149:156823d33999 115 * @details ADCRST bit (EADC_CT[1]) remains 1 during ADC reset, when ADC reset end, the ADCRST bit is automatically cleared to 0.
<> 149:156823d33999 116 */
<> 149:156823d33999 117 #define EADC_CONV_RESET(eadc) ((eadc)->CTL |= EADC_CTL_ADRST_Msk)
<> 149:156823d33999 118
<> 149:156823d33999 119 /**
<> 149:156823d33999 120 * @brief Enable PDMA transfer.
<> 149:156823d33999 121 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 122 * @return None
<> 149:156823d33999 123 * @details When A/D conversion is completed, the converted data is loaded into EADC_DATn (n: 0 ~ 18) register,
<> 149:156823d33999 124 * user can enable this bit to generate a PDMA data transfer request.
<> 149:156823d33999 125 * @note When set PDMAEN bit (EADC_CTL[11]), user must set ADINTENn (EADC_CTL[5:2], n=0~3) = 0 to disable interrupt.
<> 149:156823d33999 126 */
<> 149:156823d33999 127 #define EADC_ENABLE_PDMA(eadc) ((eadc)->CTL |= EADC_CTL_PDMAEN_Msk)
<> 149:156823d33999 128
<> 149:156823d33999 129 /**
<> 149:156823d33999 130 * @brief Disable PDMA transfer.
<> 149:156823d33999 131 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 132 * @return None
<> 149:156823d33999 133 * @details This macro is used to disable PDMA transfer.
<> 149:156823d33999 134 */
<> 149:156823d33999 135 #define EADC_DISABLE_PDMA(eadc) ((eadc)->CTL &= (~EADC_CTL_PDMAEN_Msk))
<> 149:156823d33999 136
<> 149:156823d33999 137 /**
<> 149:156823d33999 138 * @brief Enable double buffer mode.
<> 149:156823d33999 139 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 140 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
<> 149:156823d33999 141 * @return None
<> 149:156823d33999 142 * @details The ADC controller supports a double buffer mode in sample module 0~3.
<> 149:156823d33999 143 * If user enable DBMEN (EADC_SCTLn[23], n=0~3), the double buffer mode will enable.
<> 149:156823d33999 144 */
<> 149:156823d33999 145 #define EADC_ENABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_DBMEN_Msk)
<> 149:156823d33999 146
<> 149:156823d33999 147 /**
<> 149:156823d33999 148 * @brief Disable double buffer mode.
<> 149:156823d33999 149 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 150 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 3.
<> 149:156823d33999 151 * @return None
<> 149:156823d33999 152 * @details Sample has one sample result register.
<> 149:156823d33999 153 */
<> 149:156823d33999 154 #define EADC_DISABLE_DOUBLE_BUFFER(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_DBMEN_Msk)
<> 149:156823d33999 155
<> 149:156823d33999 156 /**
<> 149:156823d33999 157 * @brief Set ADIFn at A/D end of conversion.
<> 149:156823d33999 158 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 159 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
<> 149:156823d33999 160 * @return None
<> 149:156823d33999 161 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the start of conversion.
<> 149:156823d33999 162 */
<> 149:156823d33999 163 #define EADC_ENABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] |= EADC_SCTL_INTPOS_Msk)
<> 149:156823d33999 164
<> 149:156823d33999 165 /**
<> 149:156823d33999 166 * @brief Set ADIFn at A/D start of conversion.
<> 149:156823d33999 167 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 168 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 15.
<> 149:156823d33999 169 * @return None
<> 149:156823d33999 170 * @details The A/D converter generates ADIFn (EADC_STATUS2[3:0], n=0~3) at the end of conversion.
<> 149:156823d33999 171 */
<> 149:156823d33999 172 #define EADC_DISABLE_INT_POSITION(eadc, u32ModuleNum) ((eadc)->SCTL[(u32ModuleNum)] &= ~EADC_SCTL_INTPOS_Msk)
<> 149:156823d33999 173
<> 149:156823d33999 174 /**
<> 149:156823d33999 175 * @brief Enable the interrupt.
<> 149:156823d33999 176 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 177 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
<> 149:156823d33999 178 * This parameter decides which interrupts will be enabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
<> 149:156823d33999 179 * @return None
<> 149:156823d33999 180 * @details The A/D converter generates a conversion end ADIFn (EADC_STATUS2[n]) upon the end of specific sample module A/D conversion.
<> 149:156823d33999 181 * If ADCIENn bit (EADC_CTL[n+2]) is set then conversion end interrupt request ADINTn is generated (n=0~3).
<> 149:156823d33999 182 */
<> 149:156823d33999 183 #define EADC_ENABLE_INT(eadc, u32Mask) ((eadc)->CTL |= ((u32Mask) << EADC_CTL_ADCIEN0_Pos))
<> 149:156823d33999 184
<> 149:156823d33999 185 /**
<> 149:156823d33999 186 * @brief Disable the interrupt.
<> 149:156823d33999 187 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 188 * @param[in] u32Mask Decides the combination of interrupt status bits. Each bit corresponds to a interrupt status.
<> 149:156823d33999 189 * This parameter decides which interrupts will be disabled. Bit 0 is ADCIEN0, bit 1 is ADCIEN1..., bit 3 is ADCIEN3.
<> 149:156823d33999 190 * @return None
<> 149:156823d33999 191 * @details Specific sample module A/D ADINT0 interrupt function Disabled.
<> 149:156823d33999 192 */
<> 149:156823d33999 193 #define EADC_DISABLE_INT(eadc, u32Mask) ((eadc)->CTL &= ~((u32Mask) << EADC_CTL_ADCIEN0_Pos))
<> 149:156823d33999 194
<> 149:156823d33999 195 /**
<> 149:156823d33999 196 * @brief Enable the sample module interrupt.
<> 149:156823d33999 197 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 198 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
<> 149:156823d33999 199 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
<> 149:156823d33999 200 * This parameter decides which sample module interrupts will be enabled, valid range are between 1~0x7FFFF.
<> 149:156823d33999 201 * @return None
<> 149:156823d33999 202 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
<> 149:156823d33999 203 */
<> 149:156823d33999 204 #define EADC_ENABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] |= (u32ModuleMask))
<> 149:156823d33999 205
<> 149:156823d33999 206 /**
<> 149:156823d33999 207 * @brief Disable the sample module interrupt.
<> 149:156823d33999 208 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 209 * @param[in] u32IntSel Decides which interrupt source will be used, valid value are from 0 to 3.
<> 149:156823d33999 210 * @param[in] u32ModuleMask the combination of sample module interrupt status bits. Each bit corresponds to a sample module interrupt status.
<> 149:156823d33999 211 * This parameter decides which sample module interrupts will be disabled, valid range are between 1~0x7FFFF.
<> 149:156823d33999 212 * @return None
<> 149:156823d33999 213 * @details There are 4 ADC interrupts ADINT0~3, and each of these interrupts has its own interrupt vector address.
<> 149:156823d33999 214 */
<> 149:156823d33999 215 #define EADC_DISABLE_SAMPLE_MODULE_INT(eadc, u32IntSel, u32ModuleMask) ((eadc)->INTSRC[(u32IntSel)] &= ~(u32ModuleMask))
<> 149:156823d33999 216
<> 149:156823d33999 217 /**
<> 149:156823d33999 218 * @brief Set the input mode output format.
<> 149:156823d33999 219 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 220 * @param[in] u32Format Decides the output format. Valid values are:
<> 149:156823d33999 221 * - \ref EADC_CTL_DMOF_STRAIGHT_BINARY :Select the straight binary format as the output format of the conversion result.
<> 149:156823d33999 222 * - \ref EADC_CTL_DMOF_TWOS_COMPLEMENT :Select the 2's complement format as the output format of the conversion result.
<> 149:156823d33999 223 * @return None
<> 149:156823d33999 224 * @details The macro is used to set A/D input mode output format.
<> 149:156823d33999 225 */
<> 149:156823d33999 226 #define EADC_SET_DMOF(eadc, u32Format) ((eadc)->CTL = ((eadc)->CTL & ~EADC_CTL_DMOF_Msk) | (u32Format))
<> 149:156823d33999 227
<> 149:156823d33999 228 /**
<> 149:156823d33999 229 * @brief Start the A/D conversion.
<> 149:156823d33999 230 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 231 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
<> 149:156823d33999 232 * This parameter decides which sample module will be conversion, valid range are between 1~0x7FFFF.
<> 149:156823d33999 233 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module 18.
<> 149:156823d33999 234 * @return None
<> 149:156823d33999 235 * @details After write EADC_SWTRG register to start ADC conversion, the EADC_PENDSTS register will show which SAMPLE will conversion.
<> 149:156823d33999 236 */
<> 149:156823d33999 237 #define EADC_START_CONV(eadc, u32ModuleMask) ((eadc)->SWTRG = (u32ModuleMask))
<> 149:156823d33999 238
<> 149:156823d33999 239 /**
<> 149:156823d33999 240 * @brief Cancel the conversion for sample module.
<> 149:156823d33999 241 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 242 * @param[in] u32ModuleMask The combination of sample module. Each bit corresponds to a sample module.
<> 149:156823d33999 243 * This parameter decides which sample module will stop the conversion, valid range are between 1~0x7FFFF.
<> 149:156823d33999 244 * Bit 0 is sample module 0, bit 1 is sample module 1..., bit 18 is sample module18.
<> 149:156823d33999 245 * @return None
<> 149:156823d33999 246 * @details If user want to disable the conversion of the sample module, user can write EADC_PENDSTS register to clear it.
<> 149:156823d33999 247 */
<> 149:156823d33999 248 #define EADC_STOP_CONV(eadc, u32ModuleMask) ((eadc)->PENDSTS = (u32ModuleMask))
<> 149:156823d33999 249
<> 149:156823d33999 250 /**
<> 149:156823d33999 251 * @brief Get the conversion pending flag.
<> 149:156823d33999 252 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 253 * @return Return the conversion pending sample module.
<> 149:156823d33999 254 * @details This STPFn(EADC_PENDSTS[18:0]) bit remains 1 during pending state, when the respective ADC conversion is end,
<> 149:156823d33999 255 * the STPFn (n=0~18) bit is automatically cleared to 0.
<> 149:156823d33999 256 */
<> 149:156823d33999 257 #define EADC_GET_PENDING_CONV(eadc) ((eadc)->PENDSTS)
<> 149:156823d33999 258
<> 149:156823d33999 259 /**
<> 149:156823d33999 260 * @brief Get the conversion data of the user-specified sample module.
<> 149:156823d33999 261 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 262 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
<> 149:156823d33999 263 * @return Return the conversion data of the user-specified sample module.
<> 149:156823d33999 264 * @details This macro is used to read RESULT bit (EADC_DATn[15:0], n=0~18) field to get conversion data.
<> 149:156823d33999 265 */
<> 149:156823d33999 266 #define EADC_GET_CONV_DATA(eadc, u32ModuleNum) ((eadc)->DAT[(u32ModuleNum)] & EADC_DAT_RESULT_Msk)
<> 149:156823d33999 267
<> 149:156823d33999 268 /**
<> 149:156823d33999 269 * @brief Get the data overrun flag of the user-specified sample module.
<> 149:156823d33999 270 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 271 * @param[in] u32ModuleMask The combination of data overrun status bits. Each bit corresponds to a data overrun status, valid range are between 1~0x7FFFF.
<> 149:156823d33999 272 * @return Return the data overrun flag of the user-specified sample module.
<> 149:156823d33999 273 * @details This macro is used to read OV bit (EADC_STATUS0[31:16], EADC_STATUS1[18:16]) field to get data overrun status.
<> 149:156823d33999 274 */
<> 149:156823d33999 275 #define EADC_GET_DATA_OVERRUN_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 >> EADC_STATUS0_OV_Pos) | ((eadc)->STATUS1 & EADC_STATUS1_OV_Msk)) & (u32ModuleMask))
<> 149:156823d33999 276
<> 149:156823d33999 277 /**
<> 149:156823d33999 278 * @brief Get the data valid flag of the user-specified sample module.
<> 149:156823d33999 279 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 280 * @param[in] u32ModuleMask The combination of data valid status bits. Each bit corresponds to a data valid status, valid range are between 1~0x7FFFF.
<> 149:156823d33999 281 * @return Return the data valid flag of the user-specified sample module.
<> 149:156823d33999 282 * @details This macro is used to read VALID bit (EADC_STATUS0[15:0], EADC_STATUS1[1:0]) field to get data overrun status.
<> 149:156823d33999 283 */
<> 149:156823d33999 284 #define EADC_GET_DATA_VALID_FLAG(eadc, u32ModuleMask) ((((eadc)->STATUS0 & EADC_STATUS0_VALID_Msk) | (((eadc)->STATUS1 & EADC_STATUS1_VALID_Msk) << 16)) & (u32ModuleMask))
<> 149:156823d33999 285
<> 149:156823d33999 286 /**
<> 149:156823d33999 287 * @brief Get the double data of the user-specified sample module.
<> 149:156823d33999 288 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 289 * @param[in] u32ModuleNum Decides the sample module number, valid value are from 0 to 18.
<> 149:156823d33999 290 * @return Return the double data of the user-specified sample module.
<> 149:156823d33999 291 * @details This macro is used to read RESULT bit (EADC_DDATn[15:0], n=0~3) field to get conversion data.
<> 149:156823d33999 292 */
<> 149:156823d33999 293 #define EADC_GET_DOUBLE_DATA(eadc, u32ModuleNum) ((eadc)->DDAT[(u32ModuleNum)] & EADC_DDAT_RESULT_Msk)
<> 149:156823d33999 294
<> 149:156823d33999 295 /**
<> 149:156823d33999 296 * @brief Get the user-specified interrupt flags.
<> 149:156823d33999 297 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 298 * @param[in] u32Mask The combination of interrupt status bits. Each bit corresponds to a interrupt status.
<> 149:156823d33999 299 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
<> 149:156823d33999 300 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
<> 149:156823d33999 301 * @return Return the user-specified interrupt flags.
<> 149:156823d33999 302 * @details This macro is used to get the user-specified interrupt flags.
<> 149:156823d33999 303 */
<> 149:156823d33999 304 #define EADC_GET_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 & (u32Mask))
<> 149:156823d33999 305
<> 149:156823d33999 306 /**
<> 149:156823d33999 307 * @brief Get the user-specified sample module overrun flags.
<> 149:156823d33999 308 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 309 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status, valid range are between 1~0x7FFFF.
<> 149:156823d33999 310 * @return Return the user-specified sample module overrun flags.
<> 149:156823d33999 311 * @details This macro is used to get the user-specified sample module overrun flags.
<> 149:156823d33999 312 */
<> 149:156823d33999 313 #define EADC_GET_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS & (u32ModuleMask))
<> 149:156823d33999 314
<> 149:156823d33999 315 /**
<> 149:156823d33999 316 * @brief Clear the selected interrupt status bits.
<> 149:156823d33999 317 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 318 * @param[in] u32Mask The combination of compare interrupt status bits. Each bit corresponds to a compare interrupt status.
<> 149:156823d33999 319 * Bit 0 is ADIF0, bit 1 is ADIF1..., bit 3 is ADIF3.
<> 149:156823d33999 320 * Bit 4 is ADCMPF0, bit 5 is ADCMPF1..., bit 7 is ADCMPF3.
<> 149:156823d33999 321 * @return None
<> 149:156823d33999 322 * @details This macro is used to clear clear the selected interrupt status bits.
<> 149:156823d33999 323 */
<> 149:156823d33999 324 #define EADC_CLR_INT_FLAG(eadc, u32Mask) ((eadc)->STATUS2 = (u32Mask))
<> 149:156823d33999 325
<> 149:156823d33999 326 /**
<> 149:156823d33999 327 * @brief Clear the selected sample module overrun status bits.
<> 149:156823d33999 328 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 329 * @param[in] u32ModuleMask The combination of sample module overrun status bits. Each bit corresponds to a sample module overrun status.
<> 149:156823d33999 330 * Bit 0 is SPOVF0, bit 1 is SPOVF1..., bit 18 is SPOVF18.
<> 149:156823d33999 331 * @return None
<> 149:156823d33999 332 * @details This macro is used to clear the selected sample module overrun status bits.
<> 149:156823d33999 333 */
<> 149:156823d33999 334 #define EADC_CLR_SAMPLE_MODULE_OV_FLAG(eadc, u32ModuleMask) ((eadc)->OVSTS = (u32ModuleMask))
<> 149:156823d33999 335
<> 149:156823d33999 336 /**
<> 149:156823d33999 337 * @brief Check all sample module A/D result data register overrun flags.
<> 149:156823d33999 338 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 339 * @retval 0 None of sample module data register overrun flag is set to 1.
<> 149:156823d33999 340 * @retval 1 Any one of sample module data register overrun flag is set to 1.
<> 149:156823d33999 341 * @details The AOV bit (EADC_STATUS2[27]) will keep 1 when any one of sample module data register overrun flag OVn (EADC_DATn[16]) is set to 1.
<> 149:156823d33999 342 */
<> 149:156823d33999 343 #define EADC_IS_DATA_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AOV_Msk) >> EADC_STATUS2_AOV_Pos)
<> 149:156823d33999 344
<> 149:156823d33999 345 /**
<> 149:156823d33999 346 * @brief Check all sample module A/D result data register valid flags.
<> 149:156823d33999 347 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 348 * @retval 0 None of sample module data register valid flag is set to 1.
<> 149:156823d33999 349 * @retval 1 Any one of sample module data register valid flag is set to 1.
<> 149:156823d33999 350 * @details The AVALID bit (EADC_STATUS2[26]) will keep 1 when any one of sample module data register valid flag VALIDn (EADC_DATn[17]) is set to 1.
<> 149:156823d33999 351 */
<> 149:156823d33999 352 #define EADC_IS_DATA_VALID(eadc) (((eadc)->STATUS2 & EADC_STATUS2_AVALID_Msk) >> EADC_STATUS2_AVALID_Pos)
<> 149:156823d33999 353
<> 149:156823d33999 354 /**
<> 149:156823d33999 355 * @brief Check all A/D sample module start of conversion overrun flags.
<> 149:156823d33999 356 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 357 * @retval 0 None of sample module event overrun flag is set to 1.
<> 149:156823d33999 358 * @retval 1 Any one of sample module event overrun flag is set to 1.
<> 149:156823d33999 359 * @details The STOVF bit (EADC_STATUS2[25]) will keep 1 when any one of sample module event overrun flag SPOVFn (EADC_OVSTS[n]) is set to 1.
<> 149:156823d33999 360 */
<> 149:156823d33999 361 #define EADC_IS_SAMPLE_MODULE_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_STOVF_Msk) >> EADC_STATUS2_STOVF_Pos)
<> 149:156823d33999 362
<> 149:156823d33999 363 /**
<> 149:156823d33999 364 * @brief Check all A/D interrupt flag overrun bits.
<> 149:156823d33999 365 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 366 * @retval 0 None of ADINT interrupt flag is overwritten to 1.
<> 149:156823d33999 367 * @retval 1 Any one of ADINT interrupt flag is overwritten to 1.
<> 149:156823d33999 368 * @details The ADOVIF bit (EADC_STATUS2[24]) will keep 1 when any one of ADINT interrupt flag ADOVIFn (EADC_STATUS2[11:8]) is overwritten to 1.
<> 149:156823d33999 369 */
<> 149:156823d33999 370 #define EADC_IS_INT_FLAG_OV(eadc) (((eadc)->STATUS2 & EADC_STATUS2_ADOVIF_Msk) >> EADC_STATUS2_ADOVIF_Pos)
<> 149:156823d33999 371
<> 149:156823d33999 372 /**
<> 149:156823d33999 373 * @brief Get the busy state of EADC.
<> 149:156823d33999 374 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 375 * @retval 0 Idle state.
<> 149:156823d33999 376 * @retval 1 Busy state.
<> 149:156823d33999 377 * @details This macro is used to read BUSY bit (EADC_STATUS2[23]) to get busy state.
<> 149:156823d33999 378 */
<> 149:156823d33999 379 #define EADC_IS_BUSY(eadc) (((eadc)->STATUS2 & EADC_STATUS2_BUSY_Msk) >> EADC_STATUS2_BUSY_Pos)
<> 149:156823d33999 380
<> 149:156823d33999 381 /**
<> 149:156823d33999 382 * @brief Configure the comparator 0 and enable it.
<> 149:156823d33999 383 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 384 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
<> 149:156823d33999 385 * @param[in] u32Condition specifies the compare condition. Valid values are:
<> 149:156823d33999 386 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
<> 149:156823d33999 387 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
<> 149:156823d33999 388 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
<> 149:156823d33999 389 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
<> 149:156823d33999 390 * @return None
<> 149:156823d33999 391 * @details For example, ADC_ENABLE_CMP0(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
<> 149:156823d33999 392 * Means EADC will assert comparator 0 flag if sample module 5 conversion result is greater or
<> 149:156823d33999 393 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
<> 149:156823d33999 394 */
<> 149:156823d33999 395 #define EADC_ENABLE_CMP0(eadc,\
<> 149:156823d33999 396 u32ModuleNum,\
<> 149:156823d33999 397 u32Condition,\
<> 149:156823d33999 398 u16CMPData,\
<> 149:156823d33999 399 u32MatchCount) ((eadc)->CMP[0] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
<> 149:156823d33999 400 (u32Condition) |\
<> 149:156823d33999 401 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
<> 149:156823d33999 402 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
<> 149:156823d33999 403 EADC_CMP_ADCMPEN_Msk))
<> 149:156823d33999 404
<> 149:156823d33999 405 /**
<> 149:156823d33999 406 * @brief Configure the comparator 1 and enable it.
<> 149:156823d33999 407 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 408 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
<> 149:156823d33999 409 * @param[in] u32Condition specifies the compare condition. Valid values are:
<> 149:156823d33999 410 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
<> 149:156823d33999 411 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
<> 149:156823d33999 412 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
<> 149:156823d33999 413 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
<> 149:156823d33999 414 * @return None
<> 149:156823d33999 415 * @details For example, ADC_ENABLE_CMP1(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
<> 149:156823d33999 416 * Means EADC will assert comparator 1 flag if sample module 5 conversion result is greater or
<> 149:156823d33999 417 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
<> 149:156823d33999 418 */
<> 149:156823d33999 419 #define EADC_ENABLE_CMP1(eadc,\
<> 149:156823d33999 420 u32ModuleNum,\
<> 149:156823d33999 421 u32Condition,\
<> 149:156823d33999 422 u16CMPData,\
<> 149:156823d33999 423 u32MatchCount) ((eadc)->CMP[1] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
<> 149:156823d33999 424 (u32Condition) |\
<> 149:156823d33999 425 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
<> 149:156823d33999 426 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
<> 149:156823d33999 427 EADC_CMP_ADCMPEN_Msk))
<> 149:156823d33999 428
<> 149:156823d33999 429 /**
<> 149:156823d33999 430 * @brief Configure the comparator 2 and enable it.
<> 149:156823d33999 431 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 432 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
<> 149:156823d33999 433 * @param[in] u32Condition specifies the compare condition. Valid values are:
<> 149:156823d33999 434 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
<> 149:156823d33999 435 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
<> 149:156823d33999 436 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
<> 149:156823d33999 437 * @param[in] u32MatchCount specifies the match count setting, valid range are between 0~0xF.
<> 149:156823d33999 438 * @return None
<> 149:156823d33999 439 * @details For example, ADC_ENABLE_CMP2(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_CMPWEN_DISABLE, EADC_CMP_ADCMPIE_ENABLE);
<> 149:156823d33999 440 * Means EADC will assert comparator 2 flag if sample module 5 conversion result is greater or
<> 149:156823d33999 441 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
<> 149:156823d33999 442 */
<> 149:156823d33999 443 #define EADC_ENABLE_CMP2(eadc,\
<> 149:156823d33999 444 u32ModuleNum,\
<> 149:156823d33999 445 u32Condition,\
<> 149:156823d33999 446 u16CMPData,\
<> 149:156823d33999 447 u32MatchCount) ((eadc)->CMP[2] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
<> 149:156823d33999 448 (u32Condition) |\
<> 149:156823d33999 449 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
<> 149:156823d33999 450 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
<> 149:156823d33999 451 EADC_CMP_ADCMPEN_Msk))
<> 149:156823d33999 452
<> 149:156823d33999 453 /**
<> 149:156823d33999 454 * @brief Configure the comparator 3 and enable it.
<> 149:156823d33999 455 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 456 * @param[in] u32ModuleNum specifies the compare sample module, valid value are from 0 to 18.
<> 149:156823d33999 457 * @param[in] u32Condition specifies the compare condition. Valid values are:
<> 149:156823d33999 458 * - \ref EADC_CMP_CMPCOND_LESS_THAN :The compare condition is "less than the compare value"
<> 149:156823d33999 459 * - \ref EADC_CMP_CMPCOND_GREATER_OR_EQUAL :The compare condition is "greater than or equal to the compare value
<> 149:156823d33999 460 * @param[in] u16CMPData specifies the compare value, valid range are between 0~0xFFF.
<> 149:156823d33999 461 * @param[in] u32MatchCount specifies the match count setting, valid range are between 1~0xF.
<> 149:156823d33999 462 * @return None
<> 149:156823d33999 463 * @details For example, ADC_ENABLE_CMP3(EADC, 5, ADC_ADCMPR_CMPCOND_GREATER_OR_EQUAL, 0x800, 10, EADC_CMP_ADCMPIE_ENABLE);
<> 149:156823d33999 464 * Means EADC will assert comparator 3 flag if sample module 5 conversion result is greater or
<> 149:156823d33999 465 * equal to 0x800 for 10 times continuously, and a compare interrupt request is generated.
<> 149:156823d33999 466 */
<> 149:156823d33999 467 #define EADC_ENABLE_CMP3(eadc,\
<> 149:156823d33999 468 u32ModuleNum,\
<> 149:156823d33999 469 u32Condition,\
<> 149:156823d33999 470 u16CMPData,\
<> 149:156823d33999 471 u32MatchCount) ((eadc)->CMP[3] |=(((u32ModuleNum) << EADC_CMP_CMPSPL_Pos)|\
<> 149:156823d33999 472 (u32Condition) |\
<> 149:156823d33999 473 ((u16CMPData) << EADC_CMP_CMPDAT_Pos)| \
<> 149:156823d33999 474 (((u32MatchCount) - 1) << EADC_CMP_CMPMCNT_Pos)|\
<> 149:156823d33999 475 EADC_CMP_ADCMPEN_Msk))
<> 149:156823d33999 476
<> 149:156823d33999 477 /**
<> 149:156823d33999 478 * @brief Enable the compare window mode.
<> 149:156823d33999 479 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 480 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
<> 149:156823d33999 481 * @return None
<> 149:156823d33999 482 * @details ADCMPF0 (EADC_STATUS2[4]) will be set when both EADC_CMP0 and EADC_CMP1 compared condition matched.
<> 149:156823d33999 483 */
<> 149:156823d33999 484 #define EADC_ENABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_CMPWEN_Msk)
<> 149:156823d33999 485
<> 149:156823d33999 486 /**
<> 149:156823d33999 487 * @brief Disable the compare window mode.
<> 149:156823d33999 488 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 489 * @param[in] u32CMP Specifies the compare register, valid value are 0 and 2.
<> 149:156823d33999 490 * @return None
<> 149:156823d33999 491 * @details ADCMPF2 (EADC_STATUS2[6]) will be set when both EADC_CMP2 and EADC_CMP3 compared condition matched.
<> 149:156823d33999 492 */
<> 149:156823d33999 493 #define EADC_DISABLE_CMP_WINDOW_MODE(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_CMPWEN_Msk)
<> 149:156823d33999 494
<> 149:156823d33999 495 /**
<> 149:156823d33999 496 * @brief Enable the compare interrupt.
<> 149:156823d33999 497 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 498 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
<> 149:156823d33999 499 * @return None
<> 149:156823d33999 500 * @details If the compare function is enabled and the compare condition matches the setting of CMPCOND (EADC_CMPn[2], n=0~3)
<> 149:156823d33999 501 * and CMPMCNT (EADC_CMPn[11:8], n=0~3), ADCMPFn (EADC_STATUS2[7:4], n=0~3) will be asserted, in the meanwhile,
<> 149:156823d33999 502 * if ADCMPIE is set to 1, a compare interrupt request is generated.
<> 149:156823d33999 503 */
<> 149:156823d33999 504 #define EADC_ENABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] |= EADC_CMP_ADCMPIE_Msk)
<> 149:156823d33999 505
<> 149:156823d33999 506 /**
<> 149:156823d33999 507 * @brief Disable the compare interrupt.
<> 149:156823d33999 508 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 509 * @param[in] u32CMP Specifies the compare register, valid value are from 0 to 3.
<> 149:156823d33999 510 * @return None
<> 149:156823d33999 511 * @details This macro is used to disable the compare interrupt.
<> 149:156823d33999 512 */
<> 149:156823d33999 513 #define EADC_DISABLE_CMP_INT(eadc, u32CMP) ((eadc)->CMP[(u32CMP)] &= ~EADC_CMP_ADCMPIE_Msk)
<> 149:156823d33999 514
<> 149:156823d33999 515 /**
<> 149:156823d33999 516 * @brief Disable comparator 0.
<> 149:156823d33999 517 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 518 * @return None
<> 149:156823d33999 519 * @details This macro is used to disable comparator 0.
<> 149:156823d33999 520 */
<> 149:156823d33999 521 #define EADC_DISABLE_CMP0(eadc) ((eadc)->CMP[0] = 0)
<> 149:156823d33999 522
<> 149:156823d33999 523 /**
<> 149:156823d33999 524 * @brief Disable comparator 1.
<> 149:156823d33999 525 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 526 * @return None
<> 149:156823d33999 527 * @details This macro is used to disable comparator 1.
<> 149:156823d33999 528 */
<> 149:156823d33999 529 #define EADC_DISABLE_CMP1(eadc) ((eadc)->CMP[1] = 0)
<> 149:156823d33999 530
<> 149:156823d33999 531 /**
<> 149:156823d33999 532 * @brief Disable comparator 2.
<> 149:156823d33999 533 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 534 * @return None
<> 149:156823d33999 535 * @details This macro is used to disable comparator 2.
<> 149:156823d33999 536 */
<> 149:156823d33999 537 #define EADC_DISABLE_CMP2(eadc) ((eadc)->CMP[2] = 0)
<> 149:156823d33999 538
<> 149:156823d33999 539 /**
<> 149:156823d33999 540 * @brief Disable comparator 3.
<> 149:156823d33999 541 * @param[in] eadc The pointer of the specified EADC module.
<> 149:156823d33999 542 * @return None
<> 149:156823d33999 543 * @details This macro is used to disable comparator 3.
<> 149:156823d33999 544 */
<> 149:156823d33999 545 #define EADC_DISABLE_CMP3(eadc) ((eadc)->CMP[3] = 0)
<> 149:156823d33999 546
<> 149:156823d33999 547 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 548 /* Define EADC functions prototype */
<> 149:156823d33999 549 /*---------------------------------------------------------------------------------------------------------*/
<> 149:156823d33999 550 void EADC_Open(EADC_T *eadc, uint32_t u32InputMode);
<> 149:156823d33999 551 void EADC_Close(EADC_T *eadc);
<> 149:156823d33999 552 void EADC_ConfigSampleModule(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerSource, uint32_t u32Channel);
<> 149:156823d33999 553 void EADC_SetTriggerDelayTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32TriggerDelayTime, uint32_t u32DelayClockDivider);
<> 149:156823d33999 554 void EADC_SetInternalSampleTime(EADC_T *eadc, uint32_t u32SampleTime);
<> 149:156823d33999 555 void EADC_SetExtendSampleTime(EADC_T *eadc, uint32_t u32ModuleNum, uint32_t u32ExtendSampleTime);
<> 149:156823d33999 556
<> 149:156823d33999 557 /*@}*/ /* end of group EADC_EXPORTED_FUNCTIONS */
<> 149:156823d33999 558
<> 149:156823d33999 559 /*@}*/ /* end of group EADC_Driver */
<> 149:156823d33999 560
<> 149:156823d33999 561 /*@}*/ /* end of group Standard_Driver */
<> 149:156823d33999 562
<> 149:156823d33999 563 #ifdef __cplusplus
<> 149:156823d33999 564 }
<> 149:156823d33999 565 #endif
<> 149:156823d33999 566
<> 149:156823d33999 567 #endif //__EADC_H__
<> 149:156823d33999 568
<> 149:156823d33999 569 /*** (C) COPYRIGHT 2013~2015 Nuvoton Technology Corp. ***/