mbed library sources. Supersedes mbed-src.
Fork of mbed-dev by
targets/TARGET_NUVOTON/TARGET_NUC472/device/StdDriver/nuc472_pwm.h@150:02e0a0aed4ec, 2016-11-08 (annotated)
- Committer:
- <>
- Date:
- Tue Nov 08 17:45:16 2016 +0000
- Revision:
- 150:02e0a0aed4ec
- Parent:
- 149:156823d33999
This updates the lib to the mbed lib v129
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /**************************************************************************//** |
<> | 144:ef7eb2e8f9f7 | 2 | * @file pwm.h |
<> | 144:ef7eb2e8f9f7 | 3 | * @version V1.00 |
<> | 150:02e0a0aed4ec | 4 | * $Revision: 22 $ |
<> | 150:02e0a0aed4ec | 5 | * $Date: 15/11/16 2:08p $ |
<> | 144:ef7eb2e8f9f7 | 6 | * @brief NUC472/NUC442 PWM driver header file |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * @note |
<> | 144:ef7eb2e8f9f7 | 9 | * Copyright (C) 2013 Nuvoton Technology Corp. All rights reserved. |
<> | 144:ef7eb2e8f9f7 | 10 | *****************************************************************************/ |
<> | 144:ef7eb2e8f9f7 | 11 | #ifndef __PWM_H__ |
<> | 144:ef7eb2e8f9f7 | 12 | #define __PWM_H__ |
<> | 144:ef7eb2e8f9f7 | 13 | |
<> | 144:ef7eb2e8f9f7 | 14 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 15 | extern "C" |
<> | 144:ef7eb2e8f9f7 | 16 | { |
<> | 144:ef7eb2e8f9f7 | 17 | #endif |
<> | 144:ef7eb2e8f9f7 | 18 | |
<> | 144:ef7eb2e8f9f7 | 19 | |
<> | 144:ef7eb2e8f9f7 | 20 | /** @addtogroup NUC472_442_Device_Driver NUC472/NUC442 Device Driver |
<> | 144:ef7eb2e8f9f7 | 21 | @{ |
<> | 144:ef7eb2e8f9f7 | 22 | */ |
<> | 144:ef7eb2e8f9f7 | 23 | |
<> | 144:ef7eb2e8f9f7 | 24 | /** @addtogroup NUC472_442_PWM_Driver PWM Driver |
<> | 144:ef7eb2e8f9f7 | 25 | @{ |
<> | 144:ef7eb2e8f9f7 | 26 | */ |
<> | 144:ef7eb2e8f9f7 | 27 | |
<> | 144:ef7eb2e8f9f7 | 28 | /** @addtogroup NUC472_442_PWM_EXPORTED_CONSTANTS PWM Exported Constants |
<> | 144:ef7eb2e8f9f7 | 29 | @{ |
<> | 144:ef7eb2e8f9f7 | 30 | */ |
<> | 144:ef7eb2e8f9f7 | 31 | #define PWM_CHANNEL_NUM (6) /*!< PWM channel number \hideinitializer */ |
<> | 150:02e0a0aed4ec | 32 | #define PWM_CH0 (0UL) /*!< PWM channel 0 \hideinitializer */ |
<> | 150:02e0a0aed4ec | 33 | #define PWM_CH1 (1UL) /*!< PWM channel 1 \hideinitializer */ |
<> | 150:02e0a0aed4ec | 34 | #define PWM_CH2 (2UL) /*!< PWM channel 2 \hideinitializer */ |
<> | 150:02e0a0aed4ec | 35 | #define PWM_CH3 (3UL) /*!< PWM channel 3 \hideinitializer */ |
<> | 150:02e0a0aed4ec | 36 | #define PWM_CH4 (4UL) /*!< PWM channel 4 \hideinitializer */ |
<> | 150:02e0a0aed4ec | 37 | #define PWM_CH5 (5UL) /*!< PWM channel 5 \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 38 | #define PWM_CH_0_MASK (1UL) /*!< PWM channel 0 mask \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 39 | #define PWM_CH_1_MASK (2UL) /*!< PWM channel 1 mask \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 40 | #define PWM_CH_2_MASK (4UL) /*!< PWM channel 2 mask \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 41 | #define PWM_CH_3_MASK (8UL) /*!< PWM channel 3 mask \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 42 | #define PWM_CH_4_MASK (16UL) /*!< PWM channel 4 mask \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 43 | #define PWM_CH_5_MASK (32UL) /*!< PWM channel 5 mask \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 44 | #define PWM_CLK_DIV_1 (4UL) /*!< PWM clock divide by 1 \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 45 | #define PWM_CLK_DIV_2 (0UL) /*!< PWM clock divide by 2 \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 46 | #define PWM_CLK_DIV_4 (1UL) /*!< PWM clock divide by 4 \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 47 | #define PWM_CLK_DIV_8 (2UL) /*!< PWM clock divide by 8 \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 48 | #define PWM_CLK_DIV_16 (3UL) /*!< PWM clock divide by 16 \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 49 | #define PWM_EDGE_ALIGNED (0UL) /*!< PWM working in edge aligned type \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 50 | #define PWM_CENTER_ALIGNED (1UL) /*!< PWM working in center aligned type \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 51 | #define PWM_TRIGGER_ADC_RISING_EDGE_POINT (0x1000000UL) /*!< PWM trigger ADC while output rising edge is detected \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 52 | #define PWM_TRIGGER_ADC_FALLING_EDGE_POINT (0x10000UL) /*!< PWM trigger ADC while output falling edge is detected \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 53 | #define PWM_TRIGGER_ADC_CENTER_POINT (0x100UL) /*!< PWM trigger ADC while counter matches (CNR + 1) \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 54 | #define PWM_TRIGGER_ADC_PERIOD_POINT (0x1UL) /*!< PWM trigger ADC while counter down count to 0 \hideinitializer */ |
<> | 150:02e0a0aed4ec | 55 | #define PWM_BRK0_BKP0 (PWM_BRKCTL_BRK0EN_Msk) /*!< Brake0 signal source from external pin BKP0 \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 56 | #define PWM_BRK0_CPO0 (PWM_BRKCTL_CPO0BKEN_Msk) /*!< Brake0 signal source from analog comparator 0 output \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 57 | #define PWM_BRK0_CPO1 (PWM_BRKCTL_CPO1BKEN_Msk) /*!< Brake0 signal source from analog comparator 1 output \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 58 | #define PWM_BRK0_CPO2 (PWM_BRKCTL_CPO2BKEN_Msk) /*!< Brake0 signal source from analog comparator 2 output \hideinitializer */ |
<> | 150:02e0a0aed4ec | 59 | #define PWM_BRK1_LVDBK (PWM_BRKCTL_LVDBKEN_Msk) /*!< Brake1 signal source from level detect \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 60 | #define PWM_BK1SEL_BKP1 (0UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from external pin BKP1 \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 61 | #define PWM_BK1SEL_CPO0 (1UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 0 output \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 62 | #define PWM_BK1SEL_CPO1 (2UL << PWM_BRKCTL_BK1SEL_Pos) /*!< Brake1 signal source from analog comparator 1 output \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 63 | #define PWM_PERIOD_INT_UNDERFLOW (0) /*!< PWM period interrupt trigger if counter underflow \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 64 | #define PWM_PERIOD_INT_MATCH_CNR (1UL) /*!< PWM period interrupt trigger if counter match CNR \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 65 | #define PWM_DUTY_INT_MATCH_CMR_DN (0) /*!< PWM duty interrupt if counter match CNR during down counting \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 66 | #define PWM_DUTY_INT_MATCH_CMR_UP (0x100UL) /*!< PWM duty interrupt if counter match CNR during up counting \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 67 | #define PWM_FALLING_LATCH_INT_ENABLE (0x1000000UL) /*!< PWM falling latch interrupt enable \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 68 | #define PWM_RISING_LATCH_INT_ENABLE (0x10000UL) /*!< PWM rising latch interrupt enable \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 69 | #define PWM_RISING_FALLING_LATCH_INT_ENABLE (0x1010000UL) /*!< PWM rising latch interrupt enable \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 70 | #define PWM_FALLING_LATCH_INT_FLAG (PWM_FALLING_LATCH_INT_ENABLE) /*!< PWM falling latch condition happened \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 71 | #define PWM_RISING_LATCH_INT_FLAG (PWM_RISING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 72 | #define PWM_RISING_FALLING_LATCH_INT_FLAG (PWM_RISING_FALLING_LATCH_INT_ENABLE) /*!< PWM rising latch condition happened \hideinitializer */ |
<> | 144:ef7eb2e8f9f7 | 73 | |
<> | 144:ef7eb2e8f9f7 | 74 | /*@}*/ /* end of group NUC472_442_PWM_EXPORTED_CONSTANTS */ |
<> | 144:ef7eb2e8f9f7 | 75 | |
<> | 144:ef7eb2e8f9f7 | 76 | |
<> | 144:ef7eb2e8f9f7 | 77 | /** @addtogroup NUC472_442_PWM_EXPORTED_FUNCTIONS PWM Exported Functions |
<> | 144:ef7eb2e8f9f7 | 78 | @{ |
<> | 144:ef7eb2e8f9f7 | 79 | */ |
<> | 144:ef7eb2e8f9f7 | 80 | |
<> | 144:ef7eb2e8f9f7 | 81 | /** |
<> | 144:ef7eb2e8f9f7 | 82 | * @brief This macro enable complementary mode |
<> | 144:ef7eb2e8f9f7 | 83 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 84 | * @return None |
<> | 144:ef7eb2e8f9f7 | 85 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 86 | */ |
<> | 150:02e0a0aed4ec | 87 | #define PWM_ENABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_OUTMODE_Msk) |
<> | 144:ef7eb2e8f9f7 | 88 | |
<> | 144:ef7eb2e8f9f7 | 89 | /** |
<> | 144:ef7eb2e8f9f7 | 90 | * @brief This macro disable complementary mode, and enable independent mode. |
<> | 144:ef7eb2e8f9f7 | 91 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 92 | * @return None |
<> | 144:ef7eb2e8f9f7 | 93 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 94 | */ |
<> | 150:02e0a0aed4ec | 95 | #define PWM_DISABLE_COMPLEMENTARY_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_OUTMODE_Msk) |
<> | 144:ef7eb2e8f9f7 | 96 | |
<> | 144:ef7eb2e8f9f7 | 97 | /** |
<> | 144:ef7eb2e8f9f7 | 98 | * @brief This macro enable group mode |
<> | 144:ef7eb2e8f9f7 | 99 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 100 | * @return None |
<> | 144:ef7eb2e8f9f7 | 101 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 102 | */ |
<> | 150:02e0a0aed4ec | 103 | #define PWM_ENABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_GROUPEN_Msk) |
<> | 144:ef7eb2e8f9f7 | 104 | |
<> | 144:ef7eb2e8f9f7 | 105 | /** |
<> | 144:ef7eb2e8f9f7 | 106 | * @brief This macro disable group mode |
<> | 144:ef7eb2e8f9f7 | 107 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 108 | * @return None |
<> | 144:ef7eb2e8f9f7 | 109 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 110 | */ |
<> | 150:02e0a0aed4ec | 111 | #define PWM_DISABLE_GROUP_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_GROUPEN_Msk) |
<> | 144:ef7eb2e8f9f7 | 112 | |
<> | 144:ef7eb2e8f9f7 | 113 | /** |
<> | 144:ef7eb2e8f9f7 | 114 | * @brief This macro enable synchronous mode |
<> | 144:ef7eb2e8f9f7 | 115 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 116 | * @return None |
<> | 144:ef7eb2e8f9f7 | 117 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 118 | */ |
<> | 150:02e0a0aed4ec | 119 | #define PWM_ENABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL | PWM_CTL_SYNCEN_Msk) |
<> | 144:ef7eb2e8f9f7 | 120 | |
<> | 144:ef7eb2e8f9f7 | 121 | /** |
<> | 144:ef7eb2e8f9f7 | 122 | * @brief This macro disable synchronous mode, and enable independent mode. |
<> | 144:ef7eb2e8f9f7 | 123 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 124 | * @return None |
<> | 144:ef7eb2e8f9f7 | 125 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 126 | */ |
<> | 150:02e0a0aed4ec | 127 | #define PWM_DISABLE_SYNC_MODE(pwm) ((pwm)->CTL = (pwm)->CTL & ~PWM_CTL_SYNCEN_Msk) |
<> | 144:ef7eb2e8f9f7 | 128 | |
<> | 144:ef7eb2e8f9f7 | 129 | /** |
<> | 144:ef7eb2e8f9f7 | 130 | * @brief This macro enable output inverter of specified channel(s) |
<> | 144:ef7eb2e8f9f7 | 131 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 132 | * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel |
<> | 144:ef7eb2e8f9f7 | 133 | * Bit 0 represents channel 0, bit 1 represents channel 1... |
<> | 144:ef7eb2e8f9f7 | 134 | * @return None |
<> | 144:ef7eb2e8f9f7 | 135 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 136 | */ |
<> | 150:02e0a0aed4ec | 137 | #define PWM_ENABLE_OUTPUT_INVERTER(pwm, u32ChannelMask) ((pwm)->CTL = (((pwm)->CTL & ~PWM_CTL_PINV_Msk) | ((u32ChannelMask) << PWM_CTL_PINV_Pos))) |
<> | 144:ef7eb2e8f9f7 | 138 | |
<> | 144:ef7eb2e8f9f7 | 139 | /** |
<> | 144:ef7eb2e8f9f7 | 140 | * @brief This macro get captured rising data |
<> | 144:ef7eb2e8f9f7 | 141 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 142 | * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 |
<> | 144:ef7eb2e8f9f7 | 143 | * @return None |
<> | 144:ef7eb2e8f9f7 | 144 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 145 | */ |
<> | 150:02e0a0aed4ec | 146 | #define PWM_GET_CAPTURE_RISING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->RCAPDAT0 + 2 * (u32ChannelNum))) |
<> | 144:ef7eb2e8f9f7 | 147 | |
<> | 144:ef7eb2e8f9f7 | 148 | /** |
<> | 144:ef7eb2e8f9f7 | 149 | * @brief This macro get captured falling data |
<> | 144:ef7eb2e8f9f7 | 150 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 151 | * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 |
<> | 144:ef7eb2e8f9f7 | 152 | * @return None |
<> | 144:ef7eb2e8f9f7 | 153 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 154 | */ |
<> | 150:02e0a0aed4ec | 155 | #define PWM_GET_CAPTURE_FALLING_DATA(pwm, u32ChannelNum) (*(__IO uint32_t *) (&(pwm)->FCAPDAT0 + 2 * (u32ChannelNum))) |
<> | 144:ef7eb2e8f9f7 | 156 | |
<> | 144:ef7eb2e8f9f7 | 157 | /** |
<> | 144:ef7eb2e8f9f7 | 158 | * @brief This macro mask output output logic to high or low |
<> | 144:ef7eb2e8f9f7 | 159 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 160 | * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel |
<> | 144:ef7eb2e8f9f7 | 161 | * Bit 0 represents channel 0, bit 1 represents channel 1... |
<> | 144:ef7eb2e8f9f7 | 162 | * @param[in] u32LevelMask Output logic to high or low |
<> | 144:ef7eb2e8f9f7 | 163 | * @return None |
<> | 144:ef7eb2e8f9f7 | 164 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 165 | */ |
<> | 150:02e0a0aed4ec | 166 | #define PWM_MASK_OUTPUT(pwm, u32ChannelMask, u32LevelMask) ((pwm)->MSKEN |= (u32ChannelMask)) |
<> | 144:ef7eb2e8f9f7 | 167 | |
<> | 144:ef7eb2e8f9f7 | 168 | /** |
<> | 144:ef7eb2e8f9f7 | 169 | * @brief This macro set the prescaler of the selected channel |
<> | 144:ef7eb2e8f9f7 | 170 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 171 | * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 |
<> | 144:ef7eb2e8f9f7 | 172 | * @param[in] u32Prescaler Clock prescaler of specified channel. Valid values are between 1 ~ 0xFF |
<> | 144:ef7eb2e8f9f7 | 173 | * @return None |
<> | 144:ef7eb2e8f9f7 | 174 | * @note Every even channel N, and channel (N + 1) share a prescaler. So if channel 0 prescaler changed, |
<> | 144:ef7eb2e8f9f7 | 175 | * channel 1 will also be affected. |
<> | 144:ef7eb2e8f9f7 | 176 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 177 | */ |
<> | 144:ef7eb2e8f9f7 | 178 | #define PWM_SET_PRESCALER(pwm, u32ChannelNum, u32Prescaler) \ |
<> | 150:02e0a0aed4ec | 179 | (pwm->CLKPSC = ((pwm)->CLKPSC & ~(PWM_CLKPSC_CLKPSC01_Msk << (((u32ChannelNum) >> 1) * 8))) | ((u32Prescaler) << (((u32ChannelNum) >> 1) * 8))) |
<> | 144:ef7eb2e8f9f7 | 180 | |
<> | 144:ef7eb2e8f9f7 | 181 | /** |
<> | 144:ef7eb2e8f9f7 | 182 | * @brief This macro set the divider of the selected channel |
<> | 144:ef7eb2e8f9f7 | 183 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 184 | * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 |
<> | 144:ef7eb2e8f9f7 | 185 | * @param[in] u32Divider Clock divider of specified channel. Valid values are |
<> | 144:ef7eb2e8f9f7 | 186 | * - \ref PWM_CLK_DIV_1 |
<> | 144:ef7eb2e8f9f7 | 187 | * - \ref PWM_CLK_DIV_2 |
<> | 144:ef7eb2e8f9f7 | 188 | * - \ref PWM_CLK_DIV_4 |
<> | 144:ef7eb2e8f9f7 | 189 | * - \ref PWM_CLK_DIV_8 |
<> | 144:ef7eb2e8f9f7 | 190 | * - \ref PWM_CLK_DIV_16 |
<> | 144:ef7eb2e8f9f7 | 191 | * @return None |
<> | 144:ef7eb2e8f9f7 | 192 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 193 | */ |
<> | 144:ef7eb2e8f9f7 | 194 | #define PWM_SET_DIVIDER(pwm, u32ChannelNum, u32Divider) \ |
<> | 150:02e0a0aed4ec | 195 | ((pwm)->CLKDIV = ((pwm)->CLKDIV & ~(PWM_CLKDIV_CLKDIV0_Msk << ((u32ChannelNum) * 4))) | ((u32Divider) << ((u32ChannelNum) * 4))) |
<> | 144:ef7eb2e8f9f7 | 196 | |
<> | 144:ef7eb2e8f9f7 | 197 | /** |
<> | 144:ef7eb2e8f9f7 | 198 | * @brief This macro set the duty of the selected channel |
<> | 144:ef7eb2e8f9f7 | 199 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 200 | * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 |
<> | 144:ef7eb2e8f9f7 | 201 | * @param[in] u32CMR Duty of specified channel. Valid values are between 0~0xFFFF |
<> | 144:ef7eb2e8f9f7 | 202 | * @return None |
<> | 144:ef7eb2e8f9f7 | 203 | * @note This new setting will take effect on next PWM period |
<> | 144:ef7eb2e8f9f7 | 204 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 205 | */ |
<> | 150:02e0a0aed4ec | 206 | #define PWM_SET_CMR(pwm, u32ChannelNum, u32CMR) ((pwm)->CMPDAT[(u32ChannelNum)] = (u32CMR)) |
<> | 144:ef7eb2e8f9f7 | 207 | |
<> | 144:ef7eb2e8f9f7 | 208 | /** |
<> | 144:ef7eb2e8f9f7 | 209 | * @brief This macro set the period of the selected channel |
<> | 144:ef7eb2e8f9f7 | 210 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 211 | * @param[in] u32ChannelNum PWM channel number. Valid values are between 0~5 |
<> | 144:ef7eb2e8f9f7 | 212 | * @param[in] u32CNR Period of specified channel. Valid values are between 0~0xFFFF |
<> | 144:ef7eb2e8f9f7 | 213 | * @return None |
<> | 144:ef7eb2e8f9f7 | 214 | * @note This new setting will take effect on next PWM period |
<> | 144:ef7eb2e8f9f7 | 215 | * @note PWM counter will stop if period length set to 0 |
<> | 144:ef7eb2e8f9f7 | 216 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 217 | */ |
<> | 150:02e0a0aed4ec | 218 | #define PWM_SET_CNR(pwm, u32ChannelNum, u32CNR) ((pwm)->PERIOD[(u32ChannelNum)] = (u32CNR)) |
<> | 144:ef7eb2e8f9f7 | 219 | |
<> | 144:ef7eb2e8f9f7 | 220 | /** |
<> | 144:ef7eb2e8f9f7 | 221 | * @brief This macro set the PWM aligned type |
<> | 144:ef7eb2e8f9f7 | 222 | * @param[in] pwm The base address of PWM module |
<> | 144:ef7eb2e8f9f7 | 223 | * @param[in] u32ChannelMask Combination of enabled channels. Each bit corresponds to a channel |
<> | 144:ef7eb2e8f9f7 | 224 | * Bit 0 represents channel 0, bit 1 represents channel 1... |
<> | 144:ef7eb2e8f9f7 | 225 | * @param[in] u32AlignedType PWM aligned type, valid values are: |
<> | 144:ef7eb2e8f9f7 | 226 | * - \ref PWM_EDGE_ALIGNED |
<> | 144:ef7eb2e8f9f7 | 227 | * - \ref PWM_CENTER_ALIGNED |
<> | 144:ef7eb2e8f9f7 | 228 | * @return None |
<> | 144:ef7eb2e8f9f7 | 229 | * \hideinitializer |
<> | 144:ef7eb2e8f9f7 | 230 | */ |
<> | 144:ef7eb2e8f9f7 | 231 | #define PWM_SET_ALIGNED_TYPE(pwm, u32ChannelMask, u32AlignedType) \ |
<> | 150:02e0a0aed4ec | 232 | do { \ |
<> | 150:02e0a0aed4ec | 233 | (pwm)->CTL = ((pwm)->CTL & ~PWM_CTL_CNTTYPE_Msk); \ |
<> | 150:02e0a0aed4ec | 234 | if ((u32AlignedType) == PWM_CENTER_ALIGNED) \ |
<> | 150:02e0a0aed4ec | 235 | (pwm)->CTL = ((pwm)->CTL | ((u32ChannelMask) << PWM_CTL_CNTTYPE_Pos)); \ |
<> | 150:02e0a0aed4ec | 236 | } while(0) |
<> | 144:ef7eb2e8f9f7 | 237 | |
<> | 144:ef7eb2e8f9f7 | 238 | |
<> | 144:ef7eb2e8f9f7 | 239 | uint32_t PWM_ConfigOutputChannel(PWM_T *pwm, |
<> | 144:ef7eb2e8f9f7 | 240 | uint32_t u32ChannelNum, |
<> | 144:ef7eb2e8f9f7 | 241 | uint32_t u32Frequency, |
<> | 144:ef7eb2e8f9f7 | 242 | uint32_t u32DutyCycle); |
<> | 144:ef7eb2e8f9f7 | 243 | uint32_t PWM_ConfigOutputChannel2(PWM_T *pwm, |
<> | 144:ef7eb2e8f9f7 | 244 | uint32_t u32ChannelNum, |
<> | 144:ef7eb2e8f9f7 | 245 | uint32_t u32Frequency, |
<> | 144:ef7eb2e8f9f7 | 246 | uint32_t u32DutyCycle, |
<> | 144:ef7eb2e8f9f7 | 247 | uint32_t u32Frequency2); |
<> | 144:ef7eb2e8f9f7 | 248 | uint32_t PWM_ConfigCaptureChannel (PWM_T *pwm, |
<> | 144:ef7eb2e8f9f7 | 249 | uint32_t u32ChannelNum, |
<> | 144:ef7eb2e8f9f7 | 250 | uint32_t u32UnitTimeNsec, |
<> | 144:ef7eb2e8f9f7 | 251 | uint32_t u32CaptureEdge); |
<> | 144:ef7eb2e8f9f7 | 252 | void PWM_Start(PWM_T *pwm, uint32_t u32ChannelMask); |
<> | 144:ef7eb2e8f9f7 | 253 | void PWM_Stop(PWM_T *pwm, uint32_t u32ChannelMask); |
<> | 144:ef7eb2e8f9f7 | 254 | void PWM_ForceStop(PWM_T *pwm, uint32_t u32ChannelMask); |
<> | 144:ef7eb2e8f9f7 | 255 | void PWM_EnableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition); |
<> | 144:ef7eb2e8f9f7 | 256 | void PWM_DisableADCTrigger(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 257 | void PWM_ClearADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Condition); |
<> | 144:ef7eb2e8f9f7 | 258 | uint32_t PWM_GetADCTriggerFlag(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 259 | void PWM_EnableFaultBrake(PWM_T *pwm, |
<> | 144:ef7eb2e8f9f7 | 260 | uint32_t u32ChannelMask, |
<> | 144:ef7eb2e8f9f7 | 261 | uint32_t u32LevelMask, |
<> | 144:ef7eb2e8f9f7 | 262 | uint32_t u32BrakeSource); |
<> | 144:ef7eb2e8f9f7 | 263 | void PWM_ClearFaultBrakeFlag(PWM_T *pwm, uint32_t u32BrakeSource); |
<> | 144:ef7eb2e8f9f7 | 264 | void PWM_EnableCapture(PWM_T *pwm, uint32_t u32ChannelMask); |
<> | 144:ef7eb2e8f9f7 | 265 | void PWM_DisableCapture(PWM_T *pwm, uint32_t u32ChannelMask); |
<> | 144:ef7eb2e8f9f7 | 266 | void PWM_EnableOutput(PWM_T *pwm, uint32_t u32ChannelMask); |
<> | 144:ef7eb2e8f9f7 | 267 | void PWM_DisableOutput(PWM_T *pwm, uint32_t u32ChannelMask); |
<> | 144:ef7eb2e8f9f7 | 268 | void PWM_EnableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Duration); |
<> | 144:ef7eb2e8f9f7 | 269 | void PWM_DisableDeadZone(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 270 | void PWM_EnableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); |
<> | 144:ef7eb2e8f9f7 | 271 | void PWM_DisableCaptureInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); |
<> | 144:ef7eb2e8f9f7 | 272 | void PWM_ClearCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32Edge); |
<> | 144:ef7eb2e8f9f7 | 273 | uint32_t PWM_GetCaptureIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 274 | void PWM_EnableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntDutyType); |
<> | 144:ef7eb2e8f9f7 | 275 | void PWM_DisableDutyInt(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 276 | void PWM_ClearDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 277 | uint32_t PWM_GetDutyIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 278 | void PWM_EnableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource); |
<> | 144:ef7eb2e8f9f7 | 279 | void PWM_DisableFaultBrakeInt(PWM_T *pwm, uint32_t u32BrakeSource); |
<> | 144:ef7eb2e8f9f7 | 280 | void PWM_ClearFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource); |
<> | 144:ef7eb2e8f9f7 | 281 | uint32_t PWM_GetFaultBrakeIntFlag(PWM_T *pwm, uint32_t u32BrakeSource); |
<> | 144:ef7eb2e8f9f7 | 282 | void PWM_EnablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum, uint32_t u32IntPeriodType); |
<> | 144:ef7eb2e8f9f7 | 283 | void PWM_DisablePeriodInt(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 284 | void PWM_ClearPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 285 | uint32_t PWM_GetPeriodIntFlag(PWM_T *pwm, uint32_t u32ChannelNum); |
<> | 144:ef7eb2e8f9f7 | 286 | |
<> | 144:ef7eb2e8f9f7 | 287 | |
<> | 144:ef7eb2e8f9f7 | 288 | |
<> | 144:ef7eb2e8f9f7 | 289 | /*@}*/ /* end of group NUC472_442_PWM_EXPORTED_FUNCTIONS */ |
<> | 144:ef7eb2e8f9f7 | 290 | |
<> | 144:ef7eb2e8f9f7 | 291 | /*@}*/ /* end of group NUC472_442_PWM_Driver */ |
<> | 144:ef7eb2e8f9f7 | 292 | |
<> | 144:ef7eb2e8f9f7 | 293 | /*@}*/ /* end of group NUC472_442_Device_Driver */ |
<> | 144:ef7eb2e8f9f7 | 294 | |
<> | 144:ef7eb2e8f9f7 | 295 | #ifdef __cplusplus |
<> | 144:ef7eb2e8f9f7 | 296 | } |
<> | 144:ef7eb2e8f9f7 | 297 | #endif |
<> | 144:ef7eb2e8f9f7 | 298 | |
<> | 144:ef7eb2e8f9f7 | 299 | #endif //__PWM_H__ |
<> | 144:ef7eb2e8f9f7 | 300 | |
<> | 144:ef7eb2e8f9f7 | 301 | /*** (C) COPYRIGHT 2013 Nuvoton Technology Corp. ***/ |