Seungchan Lee
/
210714_ads1299_ex2_single_reg_control
This program is for single register control of ADS1299
main.cpp@0:23d6b68e4748, 2021-07-16 (annotated)
- Committer:
- futuremax
- Date:
- Fri Jul 16 04:30:11 2021 +0000
- Revision:
- 0:23d6b68e4748
This program is for single register control of the ADS1299.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
futuremax | 0:23d6b68e4748 | 1 | #include "mbed.h" |
futuremax | 0:23d6b68e4748 | 2 | // Programed by Seungchan Lee, futuremax7@gmail.com |
futuremax | 0:23d6b68e4748 | 3 | // 2021.07.15 |
futuremax | 0:23d6b68e4748 | 4 | |
futuremax | 0:23d6b68e4748 | 5 | //Serial pc(USBTX, USBRX); |
futuremax | 0:23d6b68e4748 | 6 | static UARTSerial pc(USBTX, USBRX, 115200); |
futuremax | 0:23d6b68e4748 | 7 | |
futuremax | 0:23d6b68e4748 | 8 | InterruptIn drdy(D10); |
futuremax | 0:23d6b68e4748 | 9 | SPI ads1299(D11, D12, D13); // mosi, miso, sclk |
futuremax | 0:23d6b68e4748 | 10 | DigitalOut cs(D9); |
futuremax | 0:23d6b68e4748 | 11 | DigitalOut reset(A1); |
futuremax | 0:23d6b68e4748 | 12 | DigitalOut pwdn(A2); |
futuremax | 0:23d6b68e4748 | 13 | DigitalOut start(A0); |
futuremax | 0:23d6b68e4748 | 14 | |
futuremax | 0:23d6b68e4748 | 15 | //SPI Command Definition Byte Assignments (Datasheet, p35) |
futuremax | 0:23d6b68e4748 | 16 | #define _WAKEUP 0x02 // Wake-up from standby mode |
futuremax | 0:23d6b68e4748 | 17 | #define _STANDBY 0x04 // Enter Standby mode |
futuremax | 0:23d6b68e4748 | 18 | #define _RESET 0x06 // Reset the device |
futuremax | 0:23d6b68e4748 | 19 | #define _START 0x08 // Start and restart (synchronize) conversions |
futuremax | 0:23d6b68e4748 | 20 | #define _STOP 0x0A // Stop conversion |
futuremax | 0:23d6b68e4748 | 21 | #define _RDATAC 0x10 // Enable Read Data Continuous mode (default mode at power-up) |
futuremax | 0:23d6b68e4748 | 22 | #define _SDATAC 0x11 // Stop Read Data Continuous mode |
futuremax | 0:23d6b68e4748 | 23 | #define _RDATA 0x12 // Read data by command; supports multiple read back |
futuremax | 0:23d6b68e4748 | 24 | |
futuremax | 0:23d6b68e4748 | 25 | //Register Addresses |
futuremax | 0:23d6b68e4748 | 26 | #define ID 0x00 |
futuremax | 0:23d6b68e4748 | 27 | #define CONFIG1 0x01 |
futuremax | 0:23d6b68e4748 | 28 | #define CONFIG2 0x02 |
futuremax | 0:23d6b68e4748 | 29 | #define CONFIG3 0x03 |
futuremax | 0:23d6b68e4748 | 30 | #define LOFF 0x04 |
futuremax | 0:23d6b68e4748 | 31 | #define CH1SET 0x05 |
futuremax | 0:23d6b68e4748 | 32 | #define CH2SET 0x06 |
futuremax | 0:23d6b68e4748 | 33 | #define CH3SET 0x07 |
futuremax | 0:23d6b68e4748 | 34 | #define CH4SET 0x08 |
futuremax | 0:23d6b68e4748 | 35 | #define CH5SET 0x09 |
futuremax | 0:23d6b68e4748 | 36 | #define CH6SET 0x0A |
futuremax | 0:23d6b68e4748 | 37 | #define CH7SET 0x0B |
futuremax | 0:23d6b68e4748 | 38 | #define CH8SET 0x0C |
futuremax | 0:23d6b68e4748 | 39 | #define BIAS_SENSP 0x0D |
futuremax | 0:23d6b68e4748 | 40 | #define BIAS_SENSN 0x0E |
futuremax | 0:23d6b68e4748 | 41 | #define LOFF_SENSP 0x0F |
futuremax | 0:23d6b68e4748 | 42 | #define LOFF_SENSN 0x10 |
futuremax | 0:23d6b68e4748 | 43 | #define LOFF_FLIP 0x11 |
futuremax | 0:23d6b68e4748 | 44 | #define LOFF_STATP 0x12 |
futuremax | 0:23d6b68e4748 | 45 | #define LOFF_STATN 0x13 |
futuremax | 0:23d6b68e4748 | 46 | #define GPIO 0x14 |
futuremax | 0:23d6b68e4748 | 47 | #define MISC1 0x15 |
futuremax | 0:23d6b68e4748 | 48 | #define MISC2 0x16 |
futuremax | 0:23d6b68e4748 | 49 | #define CONFIG4 0x17 |
futuremax | 0:23d6b68e4748 | 50 | |
futuremax | 0:23d6b68e4748 | 51 | #define REG_LENGTH 0x18 |
futuremax | 0:23d6b68e4748 | 52 | #define REG_UPPER_START 0x01 |
futuremax | 0:23d6b68e4748 | 53 | #define REG_UPPER_LENGTH 0x11 |
futuremax | 0:23d6b68e4748 | 54 | #define REG_LOWER_START 0x14 |
futuremax | 0:23d6b68e4748 | 55 | #define REG_LOWER_LENGTH 0x04 |
futuremax | 0:23d6b68e4748 | 56 | |
futuremax | 0:23d6b68e4748 | 57 | #define BYTE_DATA 28 |
futuremax | 0:23d6b68e4748 | 58 | #define BYTE_HEADER 2 |
futuremax | 0:23d6b68e4748 | 59 | #define BYTE_INFO 1 |
futuremax | 0:23d6b68e4748 | 60 | #define DATA_LENGTH (BYTE_DATA+BYTE_HEADER+BYTE_INFO) |
futuremax | 0:23d6b68e4748 | 61 | |
futuremax | 0:23d6b68e4748 | 62 | char ads1299_reg_data0[REG_LENGTH] = {0x3C, 0x96, 0xC0, 0x60, 0x00, 0x61, 0x61, 0x61, 0x61, 0x00, 0x00, 0x00, 0x00, |
futuremax | 0:23d6b68e4748 | 63 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00}; |
futuremax | 0:23d6b68e4748 | 64 | char ads1299_reg_data1[REG_LENGTH] = {0x3C, 0x96, 0xD0, 0xFC, 0x00, 0x65, 0x65, 0x61, 0x60, 0x00, 0x00, 0x00, 0x00, |
futuremax | 0:23d6b68e4748 | 65 | 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00}; |
futuremax | 0:23d6b68e4748 | 66 | char ads1299_reg_buf[REG_LENGTH] = {0}; |
futuremax | 0:23d6b68e4748 | 67 | |
futuremax | 0:23d6b68e4748 | 68 | void ads1299_command(char command) |
futuremax | 0:23d6b68e4748 | 69 | { |
futuremax | 0:23d6b68e4748 | 70 | cs = 0; |
futuremax | 0:23d6b68e4748 | 71 | ads1299.write(command); |
futuremax | 0:23d6b68e4748 | 72 | cs = 1; |
futuremax | 0:23d6b68e4748 | 73 | wait(0.01); // 100 ms |
futuremax | 0:23d6b68e4748 | 74 | } |
futuremax | 0:23d6b68e4748 | 75 | |
futuremax | 0:23d6b68e4748 | 76 | char ads1299_rreg(char address) |
futuremax | 0:23d6b68e4748 | 77 | { |
futuremax | 0:23d6b68e4748 | 78 | char opcode1 = address + 0x20; // RREG expects 001rrrrr where rrrrr = _address |
futuremax | 0:23d6b68e4748 | 79 | cs = 0; // open SPI |
futuremax | 0:23d6b68e4748 | 80 | ads1299.write(opcode1); // opcode1 |
futuremax | 0:23d6b68e4748 | 81 | ads1299.write(0x00); // opcode2 |
futuremax | 0:23d6b68e4748 | 82 | ads1299_reg_buf[address] = ads1299.write(0x00); // update mirror location with returned byte |
futuremax | 0:23d6b68e4748 | 83 | cs = 1; // close SPI |
futuremax | 0:23d6b68e4748 | 84 | printf("RREG 0x%0X = 0x%0X\n", address, ads1299_reg_buf[address]); |
futuremax | 0:23d6b68e4748 | 85 | |
futuremax | 0:23d6b68e4748 | 86 | return ads1299_reg_buf[address]; // return requested register value |
futuremax | 0:23d6b68e4748 | 87 | } |
futuremax | 0:23d6b68e4748 | 88 | |
futuremax | 0:23d6b68e4748 | 89 | void ads1299_rregs() |
futuremax | 0:23d6b68e4748 | 90 | { |
futuremax | 0:23d6b68e4748 | 91 | const char tx_buf[REG_LENGTH]={0}; |
futuremax | 0:23d6b68e4748 | 92 | |
futuremax | 0:23d6b68e4748 | 93 | cs = 0; // open SPI |
futuremax | 0:23d6b68e4748 | 94 | ads1299.write(0x20); // opcode1 |
futuremax | 0:23d6b68e4748 | 95 | ads1299.write(REG_LENGTH-1); // opcode2 |
futuremax | 0:23d6b68e4748 | 96 | ads1299.write(tx_buf, REG_LENGTH, ads1299_reg_buf, REG_LENGTH); |
futuremax | 0:23d6b68e4748 | 97 | cs = 1; // close SPI |
futuremax | 0:23d6b68e4748 | 98 | for (char n = 0; n<REG_LENGTH; n++) |
futuremax | 0:23d6b68e4748 | 99 | { |
futuremax | 0:23d6b68e4748 | 100 | printf("RREG 0x%0X = 0x%0X\n", n, ads1299_reg_buf[n]); |
futuremax | 0:23d6b68e4748 | 101 | } |
futuremax | 0:23d6b68e4748 | 102 | } |
futuremax | 0:23d6b68e4748 | 103 | |
futuremax | 0:23d6b68e4748 | 104 | void ads1299_wreg(char address, char data) |
futuremax | 0:23d6b68e4748 | 105 | { |
futuremax | 0:23d6b68e4748 | 106 | char opcode1 = address + 0x40; // RREG expects 001rrrrr where rrrrr = _address |
futuremax | 0:23d6b68e4748 | 107 | cs = 0; // open SPI |
futuremax | 0:23d6b68e4748 | 108 | ads1299.write(opcode1); // opcode1 |
futuremax | 0:23d6b68e4748 | 109 | ads1299.write(0x00); // opcode2 |
futuremax | 0:23d6b68e4748 | 110 | ads1299.write(data); // update mirror location with returned byte |
futuremax | 0:23d6b68e4748 | 111 | cs = 1; // close SPI |
futuremax | 0:23d6b68e4748 | 112 | |
futuremax | 0:23d6b68e4748 | 113 | // char check = ads1299_rreg(address); |
futuremax | 0:23d6b68e4748 | 114 | // printf("WREG 0x%X = 0x%X\n", address, check); |
futuremax | 0:23d6b68e4748 | 115 | } |
futuremax | 0:23d6b68e4748 | 116 | |
futuremax | 0:23d6b68e4748 | 117 | void ads1299_wregs_upper(char* data) |
futuremax | 0:23d6b68e4748 | 118 | { |
futuremax | 0:23d6b68e4748 | 119 | char rx_buf[REG_UPPER_LENGTH]={0}; |
futuremax | 0:23d6b68e4748 | 120 | |
futuremax | 0:23d6b68e4748 | 121 | cs = 0; // open SPI |
futuremax | 0:23d6b68e4748 | 122 | ads1299.write(0x40+REG_UPPER_START); // opcode1 |
futuremax | 0:23d6b68e4748 | 123 | ads1299.write(REG_UPPER_LENGTH-1); // opcode2 |
futuremax | 0:23d6b68e4748 | 124 | ads1299.write(data+REG_UPPER_START, REG_UPPER_LENGTH, rx_buf, REG_UPPER_LENGTH); |
futuremax | 0:23d6b68e4748 | 125 | cs = 1; // close SPI |
futuremax | 0:23d6b68e4748 | 126 | |
futuremax | 0:23d6b68e4748 | 127 | // printf("WREG ALL check!\n"); |
futuremax | 0:23d6b68e4748 | 128 | // ads1299_rregs(); |
futuremax | 0:23d6b68e4748 | 129 | } |
futuremax | 0:23d6b68e4748 | 130 | |
futuremax | 0:23d6b68e4748 | 131 | void ads1299_wregs_lower(char* data) |
futuremax | 0:23d6b68e4748 | 132 | { |
futuremax | 0:23d6b68e4748 | 133 | char rx_buf[REG_LOWER_LENGTH]={0}; |
futuremax | 0:23d6b68e4748 | 134 | |
futuremax | 0:23d6b68e4748 | 135 | cs = 0; // open SPI |
futuremax | 0:23d6b68e4748 | 136 | ads1299.write(0x40+REG_LOWER_START); // opcode1 |
futuremax | 0:23d6b68e4748 | 137 | ads1299.write(REG_LOWER_LENGTH-1); // opcode2 |
futuremax | 0:23d6b68e4748 | 138 | ads1299.write(data+REG_LOWER_START, REG_LOWER_LENGTH, rx_buf, REG_LOWER_LENGTH); |
futuremax | 0:23d6b68e4748 | 139 | cs = 1; // close SPI |
futuremax | 0:23d6b68e4748 | 140 | |
futuremax | 0:23d6b68e4748 | 141 | // printf("WREG ALL check!\n"); |
futuremax | 0:23d6b68e4748 | 142 | // ads1299_rregs(); |
futuremax | 0:23d6b68e4748 | 143 | } |
futuremax | 0:23d6b68e4748 | 144 | |
futuremax | 0:23d6b68e4748 | 145 | //------------------------------------------------------------------------------------------------------- |
futuremax | 0:23d6b68e4748 | 146 | |
futuremax | 0:23d6b68e4748 | 147 | int main() { |
futuremax | 0:23d6b68e4748 | 148 | // pc.baud(115200); |
futuremax | 0:23d6b68e4748 | 149 | |
futuremax | 0:23d6b68e4748 | 150 | // GPIO setting |
futuremax | 0:23d6b68e4748 | 151 | reset = 1; |
futuremax | 0:23d6b68e4748 | 152 | pwdn = 1; |
futuremax | 0:23d6b68e4748 | 153 | start = 0; |
futuremax | 0:23d6b68e4748 | 154 | cs = 1; |
futuremax | 0:23d6b68e4748 | 155 | |
futuremax | 0:23d6b68e4748 | 156 | // Setup the ads1299 for 8 bit data, high steady state clock, |
futuremax | 0:23d6b68e4748 | 157 | // second edge capture, with a 1MHz clock rate |
futuremax | 0:23d6b68e4748 | 158 | ads1299.format(8,1); |
futuremax | 0:23d6b68e4748 | 159 | ads1299.frequency(10000000); |
futuremax | 0:23d6b68e4748 | 160 | wait(0.1); |
futuremax | 0:23d6b68e4748 | 161 | |
futuremax | 0:23d6b68e4748 | 162 | cs = 0; |
futuremax | 0:23d6b68e4748 | 163 | ads1299.write(0x06); //RESET |
futuremax | 0:23d6b68e4748 | 164 | cs = 1; |
futuremax | 0:23d6b68e4748 | 165 | wait(0.5); // 100 ms |
futuremax | 0:23d6b68e4748 | 166 | |
futuremax | 0:23d6b68e4748 | 167 | cs = 0; |
futuremax | 0:23d6b68e4748 | 168 | ads1299.write(0x11); //SDATAC |
futuremax | 0:23d6b68e4748 | 169 | cs = 1; |
futuremax | 0:23d6b68e4748 | 170 | wait(0.1); // 100 ms |
futuremax | 0:23d6b68e4748 | 171 | |
futuremax | 0:23d6b68e4748 | 172 | while(1) |
futuremax | 0:23d6b68e4748 | 173 | { |
futuremax | 0:23d6b68e4748 | 174 | ads1299_rreg(0x05); |
futuremax | 0:23d6b68e4748 | 175 | wait(0.1); |
futuremax | 0:23d6b68e4748 | 176 | ads1299_wreg(0x05, 0x62); |
futuremax | 0:23d6b68e4748 | 177 | printf("reg 0x05 modified to 0x62\n"); |
futuremax | 0:23d6b68e4748 | 178 | wait(0.1); |
futuremax | 0:23d6b68e4748 | 179 | |
futuremax | 0:23d6b68e4748 | 180 | ads1299_rreg(0x05); |
futuremax | 0:23d6b68e4748 | 181 | wait(0.1); |
futuremax | 0:23d6b68e4748 | 182 | ads1299_wreg(0x05, 0x61); |
futuremax | 0:23d6b68e4748 | 183 | printf("reg 0x05 modified to 0x61\n"); |
futuremax | 0:23d6b68e4748 | 184 | wait(0.1); |
futuremax | 0:23d6b68e4748 | 185 | } |
futuremax | 0:23d6b68e4748 | 186 | } |