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mbed official
targets/cmsis/TARGET_Atmel/TARGET_SAM_CortexM0P/utils/cmsis/TARGET_SAML21/include/component/comp_supc.h@18:da299f395b9e, 2015-11-09 (annotated)
- Committer:
- mbed_official
- Date:
- Mon Nov 09 13:30:11 2015 +0000
- Revision:
- 18:da299f395b9e
Synchronized with git revision f605825f66bb2e462ff7dbc5fb4ed2dbe979d1c3
Full URL: https://github.com/mbedmicro/mbed/commit/f605825f66bb2e462ff7dbc5fb4ed2dbe979d1c3/
Added support for SAML21
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 18:da299f395b9e | 1 | /** |
| mbed_official | 18:da299f395b9e | 2 | * \file |
| mbed_official | 18:da299f395b9e | 3 | * |
| mbed_official | 18:da299f395b9e | 4 | * \brief Component description for SUPC |
| mbed_official | 18:da299f395b9e | 5 | * |
| mbed_official | 18:da299f395b9e | 6 | * Copyright (c) 2014-2015 Atmel Corporation. All rights reserved. |
| mbed_official | 18:da299f395b9e | 7 | * |
| mbed_official | 18:da299f395b9e | 8 | * \asf_license_start |
| mbed_official | 18:da299f395b9e | 9 | * |
| mbed_official | 18:da299f395b9e | 10 | * \page License |
| mbed_official | 18:da299f395b9e | 11 | * |
| mbed_official | 18:da299f395b9e | 12 | * Redistribution and use in source and binary forms, with or without |
| mbed_official | 18:da299f395b9e | 13 | * modification, are permitted provided that the following conditions are met: |
| mbed_official | 18:da299f395b9e | 14 | * |
| mbed_official | 18:da299f395b9e | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 18:da299f395b9e | 16 | * this list of conditions and the following disclaimer. |
| mbed_official | 18:da299f395b9e | 17 | * |
| mbed_official | 18:da299f395b9e | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 18:da299f395b9e | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 18:da299f395b9e | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 18:da299f395b9e | 21 | * |
| mbed_official | 18:da299f395b9e | 22 | * 3. The name of Atmel may not be used to endorse or promote products derived |
| mbed_official | 18:da299f395b9e | 23 | * from this software without specific prior written permission. |
| mbed_official | 18:da299f395b9e | 24 | * |
| mbed_official | 18:da299f395b9e | 25 | * 4. This software may only be redistributed and used in connection with an |
| mbed_official | 18:da299f395b9e | 26 | * Atmel microcontroller product. |
| mbed_official | 18:da299f395b9e | 27 | * |
| mbed_official | 18:da299f395b9e | 28 | * THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR IMPLIED |
| mbed_official | 18:da299f395b9e | 29 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
| mbed_official | 18:da299f395b9e | 30 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE |
| mbed_official | 18:da299f395b9e | 31 | * EXPRESSLY AND SPECIFICALLY DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR |
| mbed_official | 18:da299f395b9e | 32 | * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 18:da299f395b9e | 33 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS |
| mbed_official | 18:da299f395b9e | 34 | * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
| mbed_official | 18:da299f395b9e | 35 | * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
| mbed_official | 18:da299f395b9e | 36 | * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN |
| mbed_official | 18:da299f395b9e | 37 | * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
| mbed_official | 18:da299f395b9e | 38 | * POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 18:da299f395b9e | 39 | * |
| mbed_official | 18:da299f395b9e | 40 | * \asf_license_stop |
| mbed_official | 18:da299f395b9e | 41 | * |
| mbed_official | 18:da299f395b9e | 42 | */ |
| mbed_official | 18:da299f395b9e | 43 | /* |
| mbed_official | 18:da299f395b9e | 44 | * Support and FAQ: visit <a href="http://www.atmel.com/design-support/">Atmel Support</a> |
| mbed_official | 18:da299f395b9e | 45 | */ |
| mbed_official | 18:da299f395b9e | 46 | |
| mbed_official | 18:da299f395b9e | 47 | #ifndef _SAML21_SUPC_COMPONENT_ |
| mbed_official | 18:da299f395b9e | 48 | #define _SAML21_SUPC_COMPONENT_ |
| mbed_official | 18:da299f395b9e | 49 | |
| mbed_official | 18:da299f395b9e | 50 | /* ========================================================================== */ |
| mbed_official | 18:da299f395b9e | 51 | /** SOFTWARE API DEFINITION FOR SUPC */ |
| mbed_official | 18:da299f395b9e | 52 | /* ========================================================================== */ |
| mbed_official | 18:da299f395b9e | 53 | /** \addtogroup SAML21_SUPC Supply Controller */ |
| mbed_official | 18:da299f395b9e | 54 | /*@{*/ |
| mbed_official | 18:da299f395b9e | 55 | |
| mbed_official | 18:da299f395b9e | 56 | #define SUPC_U2117 |
| mbed_official | 18:da299f395b9e | 57 | #define REV_SUPC 0x110 |
| mbed_official | 18:da299f395b9e | 58 | |
| mbed_official | 18:da299f395b9e | 59 | /* -------- SUPC_INTENCLR : (SUPC Offset: 0x00) (R/W 32) Interrupt Enable Clear -------- */ |
| mbed_official | 18:da299f395b9e | 60 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 61 | typedef union { |
| mbed_official | 18:da299f395b9e | 62 | struct { |
| mbed_official | 18:da299f395b9e | 63 | uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ |
| mbed_official | 18:da299f395b9e | 64 | uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ |
| mbed_official | 18:da299f395b9e | 65 | uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 66 | uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ |
| mbed_official | 18:da299f395b9e | 67 | uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ |
| mbed_official | 18:da299f395b9e | 68 | uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 69 | uint32_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 18:da299f395b9e | 70 | uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ |
| mbed_official | 18:da299f395b9e | 71 | uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ |
| mbed_official | 18:da299f395b9e | 72 | uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ |
| mbed_official | 18:da299f395b9e | 73 | uint32_t :21; /*!< bit: 11..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 74 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 75 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 76 | } SUPC_INTENCLR_Type; |
| mbed_official | 18:da299f395b9e | 77 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 78 | |
| mbed_official | 18:da299f395b9e | 79 | #define SUPC_INTENCLR_OFFSET 0x00 /**< \brief (SUPC_INTENCLR offset) Interrupt Enable Clear */ |
| mbed_official | 18:da299f395b9e | 80 | #define SUPC_INTENCLR_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTENCLR reset_value) Interrupt Enable Clear */ |
| mbed_official | 18:da299f395b9e | 81 | |
| mbed_official | 18:da299f395b9e | 82 | #define SUPC_INTENCLR_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENCLR) BOD33 Ready */ |
| mbed_official | 18:da299f395b9e | 83 | #define SUPC_INTENCLR_BOD33RDY (0x1ul << SUPC_INTENCLR_BOD33RDY_Pos) |
| mbed_official | 18:da299f395b9e | 84 | #define SUPC_INTENCLR_BOD33DET_Pos 1 /**< \brief (SUPC_INTENCLR) BOD33 Detection */ |
| mbed_official | 18:da299f395b9e | 85 | #define SUPC_INTENCLR_BOD33DET (0x1ul << SUPC_INTENCLR_BOD33DET_Pos) |
| mbed_official | 18:da299f395b9e | 86 | #define SUPC_INTENCLR_B33SRDY_Pos 2 /**< \brief (SUPC_INTENCLR) BOD33 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 87 | #define SUPC_INTENCLR_B33SRDY (0x1ul << SUPC_INTENCLR_B33SRDY_Pos) |
| mbed_official | 18:da299f395b9e | 88 | #define SUPC_INTENCLR_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENCLR) BOD12 Ready */ |
| mbed_official | 18:da299f395b9e | 89 | #define SUPC_INTENCLR_BOD12RDY (0x1ul << SUPC_INTENCLR_BOD12RDY_Pos) |
| mbed_official | 18:da299f395b9e | 90 | #define SUPC_INTENCLR_BOD12DET_Pos 4 /**< \brief (SUPC_INTENCLR) BOD12 Detection */ |
| mbed_official | 18:da299f395b9e | 91 | #define SUPC_INTENCLR_BOD12DET (0x1ul << SUPC_INTENCLR_BOD12DET_Pos) |
| mbed_official | 18:da299f395b9e | 92 | #define SUPC_INTENCLR_B12SRDY_Pos 5 /**< \brief (SUPC_INTENCLR) BOD12 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 93 | #define SUPC_INTENCLR_B12SRDY (0x1ul << SUPC_INTENCLR_B12SRDY_Pos) |
| mbed_official | 18:da299f395b9e | 94 | #define SUPC_INTENCLR_VREGRDY_Pos 8 /**< \brief (SUPC_INTENCLR) Voltage Regulator Ready */ |
| mbed_official | 18:da299f395b9e | 95 | #define SUPC_INTENCLR_VREGRDY (0x1ul << SUPC_INTENCLR_VREGRDY_Pos) |
| mbed_official | 18:da299f395b9e | 96 | #define SUPC_INTENCLR_APWSRDY_Pos 9 /**< \brief (SUPC_INTENCLR) Automatic Power Switch Ready */ |
| mbed_official | 18:da299f395b9e | 97 | #define SUPC_INTENCLR_APWSRDY (0x1ul << SUPC_INTENCLR_APWSRDY_Pos) |
| mbed_official | 18:da299f395b9e | 98 | #define SUPC_INTENCLR_VCORERDY_Pos 10 /**< \brief (SUPC_INTENCLR) VDDCORE Ready */ |
| mbed_official | 18:da299f395b9e | 99 | #define SUPC_INTENCLR_VCORERDY (0x1ul << SUPC_INTENCLR_VCORERDY_Pos) |
| mbed_official | 18:da299f395b9e | 100 | #define SUPC_INTENCLR_MASK 0x0000073Ful /**< \brief (SUPC_INTENCLR) MASK Register */ |
| mbed_official | 18:da299f395b9e | 101 | |
| mbed_official | 18:da299f395b9e | 102 | /* -------- SUPC_INTENSET : (SUPC Offset: 0x04) (R/W 32) Interrupt Enable Set -------- */ |
| mbed_official | 18:da299f395b9e | 103 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 104 | typedef union { |
| mbed_official | 18:da299f395b9e | 105 | struct { |
| mbed_official | 18:da299f395b9e | 106 | uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ |
| mbed_official | 18:da299f395b9e | 107 | uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ |
| mbed_official | 18:da299f395b9e | 108 | uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 109 | uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ |
| mbed_official | 18:da299f395b9e | 110 | uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ |
| mbed_official | 18:da299f395b9e | 111 | uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 112 | uint32_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 18:da299f395b9e | 113 | uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ |
| mbed_official | 18:da299f395b9e | 114 | uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ |
| mbed_official | 18:da299f395b9e | 115 | uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ |
| mbed_official | 18:da299f395b9e | 116 | uint32_t :21; /*!< bit: 11..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 117 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 118 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 119 | } SUPC_INTENSET_Type; |
| mbed_official | 18:da299f395b9e | 120 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 121 | |
| mbed_official | 18:da299f395b9e | 122 | #define SUPC_INTENSET_OFFSET 0x04 /**< \brief (SUPC_INTENSET offset) Interrupt Enable Set */ |
| mbed_official | 18:da299f395b9e | 123 | #define SUPC_INTENSET_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTENSET reset_value) Interrupt Enable Set */ |
| mbed_official | 18:da299f395b9e | 124 | |
| mbed_official | 18:da299f395b9e | 125 | #define SUPC_INTENSET_BOD33RDY_Pos 0 /**< \brief (SUPC_INTENSET) BOD33 Ready */ |
| mbed_official | 18:da299f395b9e | 126 | #define SUPC_INTENSET_BOD33RDY (0x1ul << SUPC_INTENSET_BOD33RDY_Pos) |
| mbed_official | 18:da299f395b9e | 127 | #define SUPC_INTENSET_BOD33DET_Pos 1 /**< \brief (SUPC_INTENSET) BOD33 Detection */ |
| mbed_official | 18:da299f395b9e | 128 | #define SUPC_INTENSET_BOD33DET (0x1ul << SUPC_INTENSET_BOD33DET_Pos) |
| mbed_official | 18:da299f395b9e | 129 | #define SUPC_INTENSET_B33SRDY_Pos 2 /**< \brief (SUPC_INTENSET) BOD33 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 130 | #define SUPC_INTENSET_B33SRDY (0x1ul << SUPC_INTENSET_B33SRDY_Pos) |
| mbed_official | 18:da299f395b9e | 131 | #define SUPC_INTENSET_BOD12RDY_Pos 3 /**< \brief (SUPC_INTENSET) BOD12 Ready */ |
| mbed_official | 18:da299f395b9e | 132 | #define SUPC_INTENSET_BOD12RDY (0x1ul << SUPC_INTENSET_BOD12RDY_Pos) |
| mbed_official | 18:da299f395b9e | 133 | #define SUPC_INTENSET_BOD12DET_Pos 4 /**< \brief (SUPC_INTENSET) BOD12 Detection */ |
| mbed_official | 18:da299f395b9e | 134 | #define SUPC_INTENSET_BOD12DET (0x1ul << SUPC_INTENSET_BOD12DET_Pos) |
| mbed_official | 18:da299f395b9e | 135 | #define SUPC_INTENSET_B12SRDY_Pos 5 /**< \brief (SUPC_INTENSET) BOD12 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 136 | #define SUPC_INTENSET_B12SRDY (0x1ul << SUPC_INTENSET_B12SRDY_Pos) |
| mbed_official | 18:da299f395b9e | 137 | #define SUPC_INTENSET_VREGRDY_Pos 8 /**< \brief (SUPC_INTENSET) Voltage Regulator Ready */ |
| mbed_official | 18:da299f395b9e | 138 | #define SUPC_INTENSET_VREGRDY (0x1ul << SUPC_INTENSET_VREGRDY_Pos) |
| mbed_official | 18:da299f395b9e | 139 | #define SUPC_INTENSET_APWSRDY_Pos 9 /**< \brief (SUPC_INTENSET) Automatic Power Switch Ready */ |
| mbed_official | 18:da299f395b9e | 140 | #define SUPC_INTENSET_APWSRDY (0x1ul << SUPC_INTENSET_APWSRDY_Pos) |
| mbed_official | 18:da299f395b9e | 141 | #define SUPC_INTENSET_VCORERDY_Pos 10 /**< \brief (SUPC_INTENSET) VDDCORE Ready */ |
| mbed_official | 18:da299f395b9e | 142 | #define SUPC_INTENSET_VCORERDY (0x1ul << SUPC_INTENSET_VCORERDY_Pos) |
| mbed_official | 18:da299f395b9e | 143 | #define SUPC_INTENSET_MASK 0x0000073Ful /**< \brief (SUPC_INTENSET) MASK Register */ |
| mbed_official | 18:da299f395b9e | 144 | |
| mbed_official | 18:da299f395b9e | 145 | /* -------- SUPC_INTFLAG : (SUPC Offset: 0x08) (R/W 32) Interrupt Flag Status and Clear -------- */ |
| mbed_official | 18:da299f395b9e | 146 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 147 | typedef union { |
| mbed_official | 18:da299f395b9e | 148 | struct { |
| mbed_official | 18:da299f395b9e | 149 | uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ |
| mbed_official | 18:da299f395b9e | 150 | uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ |
| mbed_official | 18:da299f395b9e | 151 | uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 152 | uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ |
| mbed_official | 18:da299f395b9e | 153 | uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ |
| mbed_official | 18:da299f395b9e | 154 | uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 155 | uint32_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 18:da299f395b9e | 156 | uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ |
| mbed_official | 18:da299f395b9e | 157 | uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ |
| mbed_official | 18:da299f395b9e | 158 | uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ |
| mbed_official | 18:da299f395b9e | 159 | uint32_t :21; /*!< bit: 11..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 160 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 161 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 162 | } SUPC_INTFLAG_Type; |
| mbed_official | 18:da299f395b9e | 163 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 164 | |
| mbed_official | 18:da299f395b9e | 165 | #define SUPC_INTFLAG_OFFSET 0x08 /**< \brief (SUPC_INTFLAG offset) Interrupt Flag Status and Clear */ |
| mbed_official | 18:da299f395b9e | 166 | #define SUPC_INTFLAG_RESETVALUE 0x00000000ul /**< \brief (SUPC_INTFLAG reset_value) Interrupt Flag Status and Clear */ |
| mbed_official | 18:da299f395b9e | 167 | |
| mbed_official | 18:da299f395b9e | 168 | #define SUPC_INTFLAG_BOD33RDY_Pos 0 /**< \brief (SUPC_INTFLAG) BOD33 Ready */ |
| mbed_official | 18:da299f395b9e | 169 | #define SUPC_INTFLAG_BOD33RDY (0x1ul << SUPC_INTFLAG_BOD33RDY_Pos) |
| mbed_official | 18:da299f395b9e | 170 | #define SUPC_INTFLAG_BOD33DET_Pos 1 /**< \brief (SUPC_INTFLAG) BOD33 Detection */ |
| mbed_official | 18:da299f395b9e | 171 | #define SUPC_INTFLAG_BOD33DET (0x1ul << SUPC_INTFLAG_BOD33DET_Pos) |
| mbed_official | 18:da299f395b9e | 172 | #define SUPC_INTFLAG_B33SRDY_Pos 2 /**< \brief (SUPC_INTFLAG) BOD33 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 173 | #define SUPC_INTFLAG_B33SRDY (0x1ul << SUPC_INTFLAG_B33SRDY_Pos) |
| mbed_official | 18:da299f395b9e | 174 | #define SUPC_INTFLAG_BOD12RDY_Pos 3 /**< \brief (SUPC_INTFLAG) BOD12 Ready */ |
| mbed_official | 18:da299f395b9e | 175 | #define SUPC_INTFLAG_BOD12RDY (0x1ul << SUPC_INTFLAG_BOD12RDY_Pos) |
| mbed_official | 18:da299f395b9e | 176 | #define SUPC_INTFLAG_BOD12DET_Pos 4 /**< \brief (SUPC_INTFLAG) BOD12 Detection */ |
| mbed_official | 18:da299f395b9e | 177 | #define SUPC_INTFLAG_BOD12DET (0x1ul << SUPC_INTFLAG_BOD12DET_Pos) |
| mbed_official | 18:da299f395b9e | 178 | #define SUPC_INTFLAG_B12SRDY_Pos 5 /**< \brief (SUPC_INTFLAG) BOD12 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 179 | #define SUPC_INTFLAG_B12SRDY (0x1ul << SUPC_INTFLAG_B12SRDY_Pos) |
| mbed_official | 18:da299f395b9e | 180 | #define SUPC_INTFLAG_VREGRDY_Pos 8 /**< \brief (SUPC_INTFLAG) Voltage Regulator Ready */ |
| mbed_official | 18:da299f395b9e | 181 | #define SUPC_INTFLAG_VREGRDY (0x1ul << SUPC_INTFLAG_VREGRDY_Pos) |
| mbed_official | 18:da299f395b9e | 182 | #define SUPC_INTFLAG_APWSRDY_Pos 9 /**< \brief (SUPC_INTFLAG) Automatic Power Switch Ready */ |
| mbed_official | 18:da299f395b9e | 183 | #define SUPC_INTFLAG_APWSRDY (0x1ul << SUPC_INTFLAG_APWSRDY_Pos) |
| mbed_official | 18:da299f395b9e | 184 | #define SUPC_INTFLAG_VCORERDY_Pos 10 /**< \brief (SUPC_INTFLAG) VDDCORE Ready */ |
| mbed_official | 18:da299f395b9e | 185 | #define SUPC_INTFLAG_VCORERDY (0x1ul << SUPC_INTFLAG_VCORERDY_Pos) |
| mbed_official | 18:da299f395b9e | 186 | #define SUPC_INTFLAG_MASK 0x0000073Ful /**< \brief (SUPC_INTFLAG) MASK Register */ |
| mbed_official | 18:da299f395b9e | 187 | |
| mbed_official | 18:da299f395b9e | 188 | /* -------- SUPC_STATUS : (SUPC Offset: 0x0C) (R/ 32) Power and Clocks Status -------- */ |
| mbed_official | 18:da299f395b9e | 189 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 190 | typedef union { |
| mbed_official | 18:da299f395b9e | 191 | struct { |
| mbed_official | 18:da299f395b9e | 192 | uint32_t BOD33RDY:1; /*!< bit: 0 BOD33 Ready */ |
| mbed_official | 18:da299f395b9e | 193 | uint32_t BOD33DET:1; /*!< bit: 1 BOD33 Detection */ |
| mbed_official | 18:da299f395b9e | 194 | uint32_t B33SRDY:1; /*!< bit: 2 BOD33 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 195 | uint32_t BOD12RDY:1; /*!< bit: 3 BOD12 Ready */ |
| mbed_official | 18:da299f395b9e | 196 | uint32_t BOD12DET:1; /*!< bit: 4 BOD12 Detection */ |
| mbed_official | 18:da299f395b9e | 197 | uint32_t B12SRDY:1; /*!< bit: 5 BOD12 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 198 | uint32_t :2; /*!< bit: 6.. 7 Reserved */ |
| mbed_official | 18:da299f395b9e | 199 | uint32_t VREGRDY:1; /*!< bit: 8 Voltage Regulator Ready */ |
| mbed_official | 18:da299f395b9e | 200 | uint32_t APWSRDY:1; /*!< bit: 9 Automatic Power Switch Ready */ |
| mbed_official | 18:da299f395b9e | 201 | uint32_t VCORERDY:1; /*!< bit: 10 VDDCORE Ready */ |
| mbed_official | 18:da299f395b9e | 202 | uint32_t BBPS:1; /*!< bit: 11 Battery Backup Power Switch */ |
| mbed_official | 18:da299f395b9e | 203 | uint32_t :20; /*!< bit: 12..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 204 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 205 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 206 | } SUPC_STATUS_Type; |
| mbed_official | 18:da299f395b9e | 207 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 208 | |
| mbed_official | 18:da299f395b9e | 209 | #define SUPC_STATUS_OFFSET 0x0C /**< \brief (SUPC_STATUS offset) Power and Clocks Status */ |
| mbed_official | 18:da299f395b9e | 210 | #define SUPC_STATUS_RESETVALUE 0x00000000ul /**< \brief (SUPC_STATUS reset_value) Power and Clocks Status */ |
| mbed_official | 18:da299f395b9e | 211 | |
| mbed_official | 18:da299f395b9e | 212 | #define SUPC_STATUS_BOD33RDY_Pos 0 /**< \brief (SUPC_STATUS) BOD33 Ready */ |
| mbed_official | 18:da299f395b9e | 213 | #define SUPC_STATUS_BOD33RDY (0x1ul << SUPC_STATUS_BOD33RDY_Pos) |
| mbed_official | 18:da299f395b9e | 214 | #define SUPC_STATUS_BOD33DET_Pos 1 /**< \brief (SUPC_STATUS) BOD33 Detection */ |
| mbed_official | 18:da299f395b9e | 215 | #define SUPC_STATUS_BOD33DET (0x1ul << SUPC_STATUS_BOD33DET_Pos) |
| mbed_official | 18:da299f395b9e | 216 | #define SUPC_STATUS_B33SRDY_Pos 2 /**< \brief (SUPC_STATUS) BOD33 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 217 | #define SUPC_STATUS_B33SRDY (0x1ul << SUPC_STATUS_B33SRDY_Pos) |
| mbed_official | 18:da299f395b9e | 218 | #define SUPC_STATUS_BOD12RDY_Pos 3 /**< \brief (SUPC_STATUS) BOD12 Ready */ |
| mbed_official | 18:da299f395b9e | 219 | #define SUPC_STATUS_BOD12RDY (0x1ul << SUPC_STATUS_BOD12RDY_Pos) |
| mbed_official | 18:da299f395b9e | 220 | #define SUPC_STATUS_BOD12DET_Pos 4 /**< \brief (SUPC_STATUS) BOD12 Detection */ |
| mbed_official | 18:da299f395b9e | 221 | #define SUPC_STATUS_BOD12DET (0x1ul << SUPC_STATUS_BOD12DET_Pos) |
| mbed_official | 18:da299f395b9e | 222 | #define SUPC_STATUS_B12SRDY_Pos 5 /**< \brief (SUPC_STATUS) BOD12 Synchronization Ready */ |
| mbed_official | 18:da299f395b9e | 223 | #define SUPC_STATUS_B12SRDY (0x1ul << SUPC_STATUS_B12SRDY_Pos) |
| mbed_official | 18:da299f395b9e | 224 | #define SUPC_STATUS_VREGRDY_Pos 8 /**< \brief (SUPC_STATUS) Voltage Regulator Ready */ |
| mbed_official | 18:da299f395b9e | 225 | #define SUPC_STATUS_VREGRDY (0x1ul << SUPC_STATUS_VREGRDY_Pos) |
| mbed_official | 18:da299f395b9e | 226 | #define SUPC_STATUS_APWSRDY_Pos 9 /**< \brief (SUPC_STATUS) Automatic Power Switch Ready */ |
| mbed_official | 18:da299f395b9e | 227 | #define SUPC_STATUS_APWSRDY (0x1ul << SUPC_STATUS_APWSRDY_Pos) |
| mbed_official | 18:da299f395b9e | 228 | #define SUPC_STATUS_VCORERDY_Pos 10 /**< \brief (SUPC_STATUS) VDDCORE Ready */ |
| mbed_official | 18:da299f395b9e | 229 | #define SUPC_STATUS_VCORERDY (0x1ul << SUPC_STATUS_VCORERDY_Pos) |
| mbed_official | 18:da299f395b9e | 230 | #define SUPC_STATUS_BBPS_Pos 11 /**< \brief (SUPC_STATUS) Battery Backup Power Switch */ |
| mbed_official | 18:da299f395b9e | 231 | #define SUPC_STATUS_BBPS (0x1ul << SUPC_STATUS_BBPS_Pos) |
| mbed_official | 18:da299f395b9e | 232 | #define SUPC_STATUS_MASK 0x00000F3Ful /**< \brief (SUPC_STATUS) MASK Register */ |
| mbed_official | 18:da299f395b9e | 233 | |
| mbed_official | 18:da299f395b9e | 234 | /* -------- SUPC_BOD33 : (SUPC Offset: 0x10) (R/W 32) BOD33 Control -------- */ |
| mbed_official | 18:da299f395b9e | 235 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 236 | typedef union { |
| mbed_official | 18:da299f395b9e | 237 | struct { |
| mbed_official | 18:da299f395b9e | 238 | uint32_t :1; /*!< bit: 0 Reserved */ |
| mbed_official | 18:da299f395b9e | 239 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
| mbed_official | 18:da299f395b9e | 240 | uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ |
| mbed_official | 18:da299f395b9e | 241 | uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ |
| mbed_official | 18:da299f395b9e | 242 | uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ |
| mbed_official | 18:da299f395b9e | 243 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ |
| mbed_official | 18:da299f395b9e | 244 | uint32_t RUNBKUP:1; /*!< bit: 7 Configuration in Backup mode */ |
| mbed_official | 18:da299f395b9e | 245 | uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ |
| mbed_official | 18:da299f395b9e | 246 | uint32_t :1; /*!< bit: 9 Reserved */ |
| mbed_official | 18:da299f395b9e | 247 | uint32_t VMON:1; /*!< bit: 10 Voltage Monitored in active and standby mode */ |
| mbed_official | 18:da299f395b9e | 248 | uint32_t :1; /*!< bit: 11 Reserved */ |
| mbed_official | 18:da299f395b9e | 249 | uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ |
| mbed_official | 18:da299f395b9e | 250 | uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level for VDD */ |
| mbed_official | 18:da299f395b9e | 251 | uint32_t :2; /*!< bit: 22..23 Reserved */ |
| mbed_official | 18:da299f395b9e | 252 | uint32_t BKUPLEVEL:6; /*!< bit: 24..29 Threshold Level in backup sleep mode or for VBAT */ |
| mbed_official | 18:da299f395b9e | 253 | uint32_t :2; /*!< bit: 30..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 254 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 255 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 256 | } SUPC_BOD33_Type; |
| mbed_official | 18:da299f395b9e | 257 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 258 | |
| mbed_official | 18:da299f395b9e | 259 | #define SUPC_BOD33_OFFSET 0x10 /**< \brief (SUPC_BOD33 offset) BOD33 Control */ |
| mbed_official | 18:da299f395b9e | 260 | #define SUPC_BOD33_RESETVALUE 0x00000000ul /**< \brief (SUPC_BOD33 reset_value) BOD33 Control */ |
| mbed_official | 18:da299f395b9e | 261 | |
| mbed_official | 18:da299f395b9e | 262 | #define SUPC_BOD33_ENABLE_Pos 1 /**< \brief (SUPC_BOD33) Enable */ |
| mbed_official | 18:da299f395b9e | 263 | #define SUPC_BOD33_ENABLE (0x1ul << SUPC_BOD33_ENABLE_Pos) |
| mbed_official | 18:da299f395b9e | 264 | #define SUPC_BOD33_HYST_Pos 2 /**< \brief (SUPC_BOD33) Hysteresis Enable */ |
| mbed_official | 18:da299f395b9e | 265 | #define SUPC_BOD33_HYST (0x1ul << SUPC_BOD33_HYST_Pos) |
| mbed_official | 18:da299f395b9e | 266 | #define SUPC_BOD33_ACTION_Pos 3 /**< \brief (SUPC_BOD33) Action when Threshold Crossed */ |
| mbed_official | 18:da299f395b9e | 267 | #define SUPC_BOD33_ACTION_Msk (0x3ul << SUPC_BOD33_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 268 | #define SUPC_BOD33_ACTION(value) ((SUPC_BOD33_ACTION_Msk & ((value) << SUPC_BOD33_ACTION_Pos))) |
| mbed_official | 18:da299f395b9e | 269 | #define SUPC_BOD33_ACTION_NONE_Val 0x0ul /**< \brief (SUPC_BOD33) No action */ |
| mbed_official | 18:da299f395b9e | 270 | #define SUPC_BOD33_ACTION_RESET_Val 0x1ul /**< \brief (SUPC_BOD33) The BOD33 generates a reset */ |
| mbed_official | 18:da299f395b9e | 271 | #define SUPC_BOD33_ACTION_INT_Val 0x2ul /**< \brief (SUPC_BOD33) The BOD33 generates an interrupt */ |
| mbed_official | 18:da299f395b9e | 272 | #define SUPC_BOD33_ACTION_BKUP_Val 0x3ul /**< \brief (SUPC_BOD33) The BOD33 puts the device in backup sleep mode if VMON=0 */ |
| mbed_official | 18:da299f395b9e | 273 | #define SUPC_BOD33_ACTION_NONE (SUPC_BOD33_ACTION_NONE_Val << SUPC_BOD33_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 274 | #define SUPC_BOD33_ACTION_RESET (SUPC_BOD33_ACTION_RESET_Val << SUPC_BOD33_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 275 | #define SUPC_BOD33_ACTION_INT (SUPC_BOD33_ACTION_INT_Val << SUPC_BOD33_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 276 | #define SUPC_BOD33_ACTION_BKUP (SUPC_BOD33_ACTION_BKUP_Val << SUPC_BOD33_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 277 | #define SUPC_BOD33_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD33) Configuration in Standby mode */ |
| mbed_official | 18:da299f395b9e | 278 | #define SUPC_BOD33_STDBYCFG (0x1ul << SUPC_BOD33_STDBYCFG_Pos) |
| mbed_official | 18:da299f395b9e | 279 | #define SUPC_BOD33_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD33) Run during Standby */ |
| mbed_official | 18:da299f395b9e | 280 | #define SUPC_BOD33_RUNSTDBY (0x1ul << SUPC_BOD33_RUNSTDBY_Pos) |
| mbed_official | 18:da299f395b9e | 281 | #define SUPC_BOD33_RUNBKUP_Pos 7 /**< \brief (SUPC_BOD33) Configuration in Backup mode */ |
| mbed_official | 18:da299f395b9e | 282 | #define SUPC_BOD33_RUNBKUP (0x1ul << SUPC_BOD33_RUNBKUP_Pos) |
| mbed_official | 18:da299f395b9e | 283 | #define SUPC_BOD33_ACTCFG_Pos 8 /**< \brief (SUPC_BOD33) Configuration in Active mode */ |
| mbed_official | 18:da299f395b9e | 284 | #define SUPC_BOD33_ACTCFG (0x1ul << SUPC_BOD33_ACTCFG_Pos) |
| mbed_official | 18:da299f395b9e | 285 | #define SUPC_BOD33_VMON_Pos 10 /**< \brief (SUPC_BOD33) Voltage Monitored in active and standby mode */ |
| mbed_official | 18:da299f395b9e | 286 | #define SUPC_BOD33_VMON (0x1ul << SUPC_BOD33_VMON_Pos) |
| mbed_official | 18:da299f395b9e | 287 | #define SUPC_BOD33_PSEL_Pos 12 /**< \brief (SUPC_BOD33) Prescaler Select */ |
| mbed_official | 18:da299f395b9e | 288 | #define SUPC_BOD33_PSEL_Msk (0xFul << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 289 | #define SUPC_BOD33_PSEL(value) ((SUPC_BOD33_PSEL_Msk & ((value) << SUPC_BOD33_PSEL_Pos))) |
| mbed_official | 18:da299f395b9e | 290 | #define SUPC_BOD33_PSEL_DIV2_Val 0x0ul /**< \brief (SUPC_BOD33) Divide clock by 2 */ |
| mbed_official | 18:da299f395b9e | 291 | #define SUPC_BOD33_PSEL_DIV4_Val 0x1ul /**< \brief (SUPC_BOD33) Divide clock by 4 */ |
| mbed_official | 18:da299f395b9e | 292 | #define SUPC_BOD33_PSEL_DIV8_Val 0x2ul /**< \brief (SUPC_BOD33) Divide clock by 8 */ |
| mbed_official | 18:da299f395b9e | 293 | #define SUPC_BOD33_PSEL_DIV16_Val 0x3ul /**< \brief (SUPC_BOD33) Divide clock by 16 */ |
| mbed_official | 18:da299f395b9e | 294 | #define SUPC_BOD33_PSEL_DIV32_Val 0x4ul /**< \brief (SUPC_BOD33) Divide clock by 32 */ |
| mbed_official | 18:da299f395b9e | 295 | #define SUPC_BOD33_PSEL_DIV64_Val 0x5ul /**< \brief (SUPC_BOD33) Divide clock by 64 */ |
| mbed_official | 18:da299f395b9e | 296 | #define SUPC_BOD33_PSEL_DIV128_Val 0x6ul /**< \brief (SUPC_BOD33) Divide clock by 128 */ |
| mbed_official | 18:da299f395b9e | 297 | #define SUPC_BOD33_PSEL_DIV256_Val 0x7ul /**< \brief (SUPC_BOD33) Divide clock by 256 */ |
| mbed_official | 18:da299f395b9e | 298 | #define SUPC_BOD33_PSEL_DIV512_Val 0x8ul /**< \brief (SUPC_BOD33) Divide clock by 512 */ |
| mbed_official | 18:da299f395b9e | 299 | #define SUPC_BOD33_PSEL_DIV1024_Val 0x9ul /**< \brief (SUPC_BOD33) Divide clock by 1024 */ |
| mbed_official | 18:da299f395b9e | 300 | #define SUPC_BOD33_PSEL_DIV2048_Val 0xAul /**< \brief (SUPC_BOD33) Divide clock by 2048 */ |
| mbed_official | 18:da299f395b9e | 301 | #define SUPC_BOD33_PSEL_DIV4096_Val 0xBul /**< \brief (SUPC_BOD33) Divide clock by 4096 */ |
| mbed_official | 18:da299f395b9e | 302 | #define SUPC_BOD33_PSEL_DIV8192_Val 0xCul /**< \brief (SUPC_BOD33) Divide clock by 8192 */ |
| mbed_official | 18:da299f395b9e | 303 | #define SUPC_BOD33_PSEL_DIV16384_Val 0xDul /**< \brief (SUPC_BOD33) Divide clock by 16384 */ |
| mbed_official | 18:da299f395b9e | 304 | #define SUPC_BOD33_PSEL_DIV32768_Val 0xEul /**< \brief (SUPC_BOD33) Divide clock by 32768 */ |
| mbed_official | 18:da299f395b9e | 305 | #define SUPC_BOD33_PSEL_DIV65536_Val 0xFul /**< \brief (SUPC_BOD33) Divide clock by 65536 */ |
| mbed_official | 18:da299f395b9e | 306 | #define SUPC_BOD33_PSEL_DIV2 (SUPC_BOD33_PSEL_DIV2_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 307 | #define SUPC_BOD33_PSEL_DIV4 (SUPC_BOD33_PSEL_DIV4_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 308 | #define SUPC_BOD33_PSEL_DIV8 (SUPC_BOD33_PSEL_DIV8_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 309 | #define SUPC_BOD33_PSEL_DIV16 (SUPC_BOD33_PSEL_DIV16_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 310 | #define SUPC_BOD33_PSEL_DIV32 (SUPC_BOD33_PSEL_DIV32_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 311 | #define SUPC_BOD33_PSEL_DIV64 (SUPC_BOD33_PSEL_DIV64_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 312 | #define SUPC_BOD33_PSEL_DIV128 (SUPC_BOD33_PSEL_DIV128_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 313 | #define SUPC_BOD33_PSEL_DIV256 (SUPC_BOD33_PSEL_DIV256_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 314 | #define SUPC_BOD33_PSEL_DIV512 (SUPC_BOD33_PSEL_DIV512_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 315 | #define SUPC_BOD33_PSEL_DIV1024 (SUPC_BOD33_PSEL_DIV1024_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 316 | #define SUPC_BOD33_PSEL_DIV2048 (SUPC_BOD33_PSEL_DIV2048_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 317 | #define SUPC_BOD33_PSEL_DIV4096 (SUPC_BOD33_PSEL_DIV4096_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 318 | #define SUPC_BOD33_PSEL_DIV8192 (SUPC_BOD33_PSEL_DIV8192_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 319 | #define SUPC_BOD33_PSEL_DIV16384 (SUPC_BOD33_PSEL_DIV16384_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 320 | #define SUPC_BOD33_PSEL_DIV32768 (SUPC_BOD33_PSEL_DIV32768_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 321 | #define SUPC_BOD33_PSEL_DIV65536 (SUPC_BOD33_PSEL_DIV65536_Val << SUPC_BOD33_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 322 | #define SUPC_BOD33_LEVEL_Pos 16 /**< \brief (SUPC_BOD33) Threshold Level for VDD */ |
| mbed_official | 18:da299f395b9e | 323 | #define SUPC_BOD33_LEVEL_Msk (0x3Ful << SUPC_BOD33_LEVEL_Pos) |
| mbed_official | 18:da299f395b9e | 324 | #define SUPC_BOD33_LEVEL(value) ((SUPC_BOD33_LEVEL_Msk & ((value) << SUPC_BOD33_LEVEL_Pos))) |
| mbed_official | 18:da299f395b9e | 325 | #define SUPC_BOD33_BKUPLEVEL_Pos 24 /**< \brief (SUPC_BOD33) Threshold Level in backup sleep mode or for VBAT */ |
| mbed_official | 18:da299f395b9e | 326 | #define SUPC_BOD33_BKUPLEVEL_Msk (0x3Ful << SUPC_BOD33_BKUPLEVEL_Pos) |
| mbed_official | 18:da299f395b9e | 327 | #define SUPC_BOD33_BKUPLEVEL(value) ((SUPC_BOD33_BKUPLEVEL_Msk & ((value) << SUPC_BOD33_BKUPLEVEL_Pos))) |
| mbed_official | 18:da299f395b9e | 328 | #define SUPC_BOD33_MASK 0x3F3FF5FEul /**< \brief (SUPC_BOD33) MASK Register */ |
| mbed_official | 18:da299f395b9e | 329 | |
| mbed_official | 18:da299f395b9e | 330 | /* -------- SUPC_BOD12 : (SUPC Offset: 0x14) (R/W 32) BOD12 Control -------- */ |
| mbed_official | 18:da299f395b9e | 331 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 332 | typedef union { |
| mbed_official | 18:da299f395b9e | 333 | struct { |
| mbed_official | 18:da299f395b9e | 334 | uint32_t :1; /*!< bit: 0 Reserved */ |
| mbed_official | 18:da299f395b9e | 335 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
| mbed_official | 18:da299f395b9e | 336 | uint32_t HYST:1; /*!< bit: 2 Hysteresis Enable */ |
| mbed_official | 18:da299f395b9e | 337 | uint32_t ACTION:2; /*!< bit: 3.. 4 Action when Threshold Crossed */ |
| mbed_official | 18:da299f395b9e | 338 | uint32_t STDBYCFG:1; /*!< bit: 5 Configuration in Standby mode */ |
| mbed_official | 18:da299f395b9e | 339 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ |
| mbed_official | 18:da299f395b9e | 340 | uint32_t :1; /*!< bit: 7 Reserved */ |
| mbed_official | 18:da299f395b9e | 341 | uint32_t ACTCFG:1; /*!< bit: 8 Configuration in Active mode */ |
| mbed_official | 18:da299f395b9e | 342 | uint32_t :3; /*!< bit: 9..11 Reserved */ |
| mbed_official | 18:da299f395b9e | 343 | uint32_t PSEL:4; /*!< bit: 12..15 Prescaler Select */ |
| mbed_official | 18:da299f395b9e | 344 | uint32_t LEVEL:6; /*!< bit: 16..21 Threshold Level */ |
| mbed_official | 18:da299f395b9e | 345 | uint32_t :10; /*!< bit: 22..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 346 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 347 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 348 | } SUPC_BOD12_Type; |
| mbed_official | 18:da299f395b9e | 349 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 350 | |
| mbed_official | 18:da299f395b9e | 351 | #define SUPC_BOD12_OFFSET 0x14 /**< \brief (SUPC_BOD12 offset) BOD12 Control */ |
| mbed_official | 18:da299f395b9e | 352 | #define SUPC_BOD12_RESETVALUE 0x00000000ul /**< \brief (SUPC_BOD12 reset_value) BOD12 Control */ |
| mbed_official | 18:da299f395b9e | 353 | |
| mbed_official | 18:da299f395b9e | 354 | #define SUPC_BOD12_ENABLE_Pos 1 /**< \brief (SUPC_BOD12) Enable */ |
| mbed_official | 18:da299f395b9e | 355 | #define SUPC_BOD12_ENABLE (0x1ul << SUPC_BOD12_ENABLE_Pos) |
| mbed_official | 18:da299f395b9e | 356 | #define SUPC_BOD12_HYST_Pos 2 /**< \brief (SUPC_BOD12) Hysteresis Enable */ |
| mbed_official | 18:da299f395b9e | 357 | #define SUPC_BOD12_HYST (0x1ul << SUPC_BOD12_HYST_Pos) |
| mbed_official | 18:da299f395b9e | 358 | #define SUPC_BOD12_ACTION_Pos 3 /**< \brief (SUPC_BOD12) Action when Threshold Crossed */ |
| mbed_official | 18:da299f395b9e | 359 | #define SUPC_BOD12_ACTION_Msk (0x3ul << SUPC_BOD12_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 360 | #define SUPC_BOD12_ACTION(value) ((SUPC_BOD12_ACTION_Msk & ((value) << SUPC_BOD12_ACTION_Pos))) |
| mbed_official | 18:da299f395b9e | 361 | #define SUPC_BOD12_ACTION_NONE_Val 0x0ul /**< \brief (SUPC_BOD12) No action */ |
| mbed_official | 18:da299f395b9e | 362 | #define SUPC_BOD12_ACTION_RESET_Val 0x1ul /**< \brief (SUPC_BOD12) The BOD12 generates a reset */ |
| mbed_official | 18:da299f395b9e | 363 | #define SUPC_BOD12_ACTION_INT_Val 0x2ul /**< \brief (SUPC_BOD12) The BOD12 generates an interrupt */ |
| mbed_official | 18:da299f395b9e | 364 | #define SUPC_BOD12_ACTION_NONE (SUPC_BOD12_ACTION_NONE_Val << SUPC_BOD12_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 365 | #define SUPC_BOD12_ACTION_RESET (SUPC_BOD12_ACTION_RESET_Val << SUPC_BOD12_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 366 | #define SUPC_BOD12_ACTION_INT (SUPC_BOD12_ACTION_INT_Val << SUPC_BOD12_ACTION_Pos) |
| mbed_official | 18:da299f395b9e | 367 | #define SUPC_BOD12_STDBYCFG_Pos 5 /**< \brief (SUPC_BOD12) Configuration in Standby mode */ |
| mbed_official | 18:da299f395b9e | 368 | #define SUPC_BOD12_STDBYCFG (0x1ul << SUPC_BOD12_STDBYCFG_Pos) |
| mbed_official | 18:da299f395b9e | 369 | #define SUPC_BOD12_RUNSTDBY_Pos 6 /**< \brief (SUPC_BOD12) Run during Standby */ |
| mbed_official | 18:da299f395b9e | 370 | #define SUPC_BOD12_RUNSTDBY (0x1ul << SUPC_BOD12_RUNSTDBY_Pos) |
| mbed_official | 18:da299f395b9e | 371 | #define SUPC_BOD12_ACTCFG_Pos 8 /**< \brief (SUPC_BOD12) Configuration in Active mode */ |
| mbed_official | 18:da299f395b9e | 372 | #define SUPC_BOD12_ACTCFG (0x1ul << SUPC_BOD12_ACTCFG_Pos) |
| mbed_official | 18:da299f395b9e | 373 | #define SUPC_BOD12_PSEL_Pos 12 /**< \brief (SUPC_BOD12) Prescaler Select */ |
| mbed_official | 18:da299f395b9e | 374 | #define SUPC_BOD12_PSEL_Msk (0xFul << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 375 | #define SUPC_BOD12_PSEL(value) ((SUPC_BOD12_PSEL_Msk & ((value) << SUPC_BOD12_PSEL_Pos))) |
| mbed_official | 18:da299f395b9e | 376 | #define SUPC_BOD12_PSEL_DIV2_Val 0x0ul /**< \brief (SUPC_BOD12) Divide clock by 2 */ |
| mbed_official | 18:da299f395b9e | 377 | #define SUPC_BOD12_PSEL_DIV4_Val 0x1ul /**< \brief (SUPC_BOD12) Divide clock by 4 */ |
| mbed_official | 18:da299f395b9e | 378 | #define SUPC_BOD12_PSEL_DIV8_Val 0x2ul /**< \brief (SUPC_BOD12) Divide clock by 8 */ |
| mbed_official | 18:da299f395b9e | 379 | #define SUPC_BOD12_PSEL_DIV16_Val 0x3ul /**< \brief (SUPC_BOD12) Divide clock by 16 */ |
| mbed_official | 18:da299f395b9e | 380 | #define SUPC_BOD12_PSEL_DIV32_Val 0x4ul /**< \brief (SUPC_BOD12) Divide clock by 32 */ |
| mbed_official | 18:da299f395b9e | 381 | #define SUPC_BOD12_PSEL_DIV64_Val 0x5ul /**< \brief (SUPC_BOD12) Divide clock by 64 */ |
| mbed_official | 18:da299f395b9e | 382 | #define SUPC_BOD12_PSEL_DIV128_Val 0x6ul /**< \brief (SUPC_BOD12) Divide clock by 128 */ |
| mbed_official | 18:da299f395b9e | 383 | #define SUPC_BOD12_PSEL_DIV256_Val 0x7ul /**< \brief (SUPC_BOD12) Divide clock by 256 */ |
| mbed_official | 18:da299f395b9e | 384 | #define SUPC_BOD12_PSEL_DIV512_Val 0x8ul /**< \brief (SUPC_BOD12) Divide clock by 512 */ |
| mbed_official | 18:da299f395b9e | 385 | #define SUPC_BOD12_PSEL_DIV1024_Val 0x9ul /**< \brief (SUPC_BOD12) Divide clock by 1024 */ |
| mbed_official | 18:da299f395b9e | 386 | #define SUPC_BOD12_PSEL_DIV2048_Val 0xAul /**< \brief (SUPC_BOD12) Divide clock by 2048 */ |
| mbed_official | 18:da299f395b9e | 387 | #define SUPC_BOD12_PSEL_DIV4096_Val 0xBul /**< \brief (SUPC_BOD12) Divide clock by 4096 */ |
| mbed_official | 18:da299f395b9e | 388 | #define SUPC_BOD12_PSEL_DIV8192_Val 0xCul /**< \brief (SUPC_BOD12) Divide clock by 8192 */ |
| mbed_official | 18:da299f395b9e | 389 | #define SUPC_BOD12_PSEL_DIV16384_Val 0xDul /**< \brief (SUPC_BOD12) Divide clock by 16384 */ |
| mbed_official | 18:da299f395b9e | 390 | #define SUPC_BOD12_PSEL_DIV32768_Val 0xEul /**< \brief (SUPC_BOD12) Divide clock by 32768 */ |
| mbed_official | 18:da299f395b9e | 391 | #define SUPC_BOD12_PSEL_DIV65536_Val 0xFul /**< \brief (SUPC_BOD12) Divide clock by 65536 */ |
| mbed_official | 18:da299f395b9e | 392 | #define SUPC_BOD12_PSEL_DIV2 (SUPC_BOD12_PSEL_DIV2_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 393 | #define SUPC_BOD12_PSEL_DIV4 (SUPC_BOD12_PSEL_DIV4_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 394 | #define SUPC_BOD12_PSEL_DIV8 (SUPC_BOD12_PSEL_DIV8_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 395 | #define SUPC_BOD12_PSEL_DIV16 (SUPC_BOD12_PSEL_DIV16_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 396 | #define SUPC_BOD12_PSEL_DIV32 (SUPC_BOD12_PSEL_DIV32_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 397 | #define SUPC_BOD12_PSEL_DIV64 (SUPC_BOD12_PSEL_DIV64_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 398 | #define SUPC_BOD12_PSEL_DIV128 (SUPC_BOD12_PSEL_DIV128_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 399 | #define SUPC_BOD12_PSEL_DIV256 (SUPC_BOD12_PSEL_DIV256_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 400 | #define SUPC_BOD12_PSEL_DIV512 (SUPC_BOD12_PSEL_DIV512_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 401 | #define SUPC_BOD12_PSEL_DIV1024 (SUPC_BOD12_PSEL_DIV1024_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 402 | #define SUPC_BOD12_PSEL_DIV2048 (SUPC_BOD12_PSEL_DIV2048_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 403 | #define SUPC_BOD12_PSEL_DIV4096 (SUPC_BOD12_PSEL_DIV4096_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 404 | #define SUPC_BOD12_PSEL_DIV8192 (SUPC_BOD12_PSEL_DIV8192_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 405 | #define SUPC_BOD12_PSEL_DIV16384 (SUPC_BOD12_PSEL_DIV16384_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 406 | #define SUPC_BOD12_PSEL_DIV32768 (SUPC_BOD12_PSEL_DIV32768_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 407 | #define SUPC_BOD12_PSEL_DIV65536 (SUPC_BOD12_PSEL_DIV65536_Val << SUPC_BOD12_PSEL_Pos) |
| mbed_official | 18:da299f395b9e | 408 | #define SUPC_BOD12_LEVEL_Pos 16 /**< \brief (SUPC_BOD12) Threshold Level */ |
| mbed_official | 18:da299f395b9e | 409 | #define SUPC_BOD12_LEVEL_Msk (0x3Ful << SUPC_BOD12_LEVEL_Pos) |
| mbed_official | 18:da299f395b9e | 410 | #define SUPC_BOD12_LEVEL(value) ((SUPC_BOD12_LEVEL_Msk & ((value) << SUPC_BOD12_LEVEL_Pos))) |
| mbed_official | 18:da299f395b9e | 411 | #define SUPC_BOD12_MASK 0x003FF17Eul /**< \brief (SUPC_BOD12) MASK Register */ |
| mbed_official | 18:da299f395b9e | 412 | |
| mbed_official | 18:da299f395b9e | 413 | /* -------- SUPC_VREG : (SUPC Offset: 0x18) (R/W 32) VREG Control -------- */ |
| mbed_official | 18:da299f395b9e | 414 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 415 | typedef union { |
| mbed_official | 18:da299f395b9e | 416 | struct { |
| mbed_official | 18:da299f395b9e | 417 | uint32_t :1; /*!< bit: 0 Reserved */ |
| mbed_official | 18:da299f395b9e | 418 | uint32_t ENABLE:1; /*!< bit: 1 Enable */ |
| mbed_official | 18:da299f395b9e | 419 | uint32_t SEL:2; /*!< bit: 2.. 3 Voltage Regulator Selection in active mode */ |
| mbed_official | 18:da299f395b9e | 420 | uint32_t :2; /*!< bit: 4.. 5 Reserved */ |
| mbed_official | 18:da299f395b9e | 421 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ |
| mbed_official | 18:da299f395b9e | 422 | uint32_t :1; /*!< bit: 7 Reserved */ |
| mbed_official | 18:da299f395b9e | 423 | uint32_t LPEFF:1; /*!< bit: 8 Low Power Efficiency */ |
| mbed_official | 18:da299f395b9e | 424 | uint32_t :7; /*!< bit: 9..15 Reserved */ |
| mbed_official | 18:da299f395b9e | 425 | uint32_t VSVSTEP:4; /*!< bit: 16..19 Voltage Scaling Voltage Step */ |
| mbed_official | 18:da299f395b9e | 426 | uint32_t :4; /*!< bit: 20..23 Reserved */ |
| mbed_official | 18:da299f395b9e | 427 | uint32_t VSPER:8; /*!< bit: 24..31 Voltage Scaling Period */ |
| mbed_official | 18:da299f395b9e | 428 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 429 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 430 | } SUPC_VREG_Type; |
| mbed_official | 18:da299f395b9e | 431 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 432 | |
| mbed_official | 18:da299f395b9e | 433 | #define SUPC_VREG_OFFSET 0x18 /**< \brief (SUPC_VREG offset) VREG Control */ |
| mbed_official | 18:da299f395b9e | 434 | #define SUPC_VREG_RESETVALUE 0x00000000ul /**< \brief (SUPC_VREG reset_value) VREG Control */ |
| mbed_official | 18:da299f395b9e | 435 | |
| mbed_official | 18:da299f395b9e | 436 | #define SUPC_VREG_ENABLE_Pos 1 /**< \brief (SUPC_VREG) Enable */ |
| mbed_official | 18:da299f395b9e | 437 | #define SUPC_VREG_ENABLE (0x1ul << SUPC_VREG_ENABLE_Pos) |
| mbed_official | 18:da299f395b9e | 438 | #define SUPC_VREG_SEL_Pos 2 /**< \brief (SUPC_VREG) Voltage Regulator Selection in active mode */ |
| mbed_official | 18:da299f395b9e | 439 | #define SUPC_VREG_SEL_Msk (0x3ul << SUPC_VREG_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 440 | #define SUPC_VREG_SEL(value) ((SUPC_VREG_SEL_Msk & ((value) << SUPC_VREG_SEL_Pos))) |
| mbed_official | 18:da299f395b9e | 441 | #define SUPC_VREG_SEL_LDO_Val 0x0ul /**< \brief (SUPC_VREG) LDO selection */ |
| mbed_official | 18:da299f395b9e | 442 | #define SUPC_VREG_SEL_BUCK_Val 0x1ul /**< \brief (SUPC_VREG) Buck selection */ |
| mbed_official | 18:da299f395b9e | 443 | #define SUPC_VREG_SEL_SCVREG_Val 0x2ul /**< \brief (SUPC_VREG) Switched Cap selection */ |
| mbed_official | 18:da299f395b9e | 444 | #define SUPC_VREG_SEL_LDO (SUPC_VREG_SEL_LDO_Val << SUPC_VREG_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 445 | #define SUPC_VREG_SEL_BUCK (SUPC_VREG_SEL_BUCK_Val << SUPC_VREG_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 446 | #define SUPC_VREG_SEL_SCVREG (SUPC_VREG_SEL_SCVREG_Val << SUPC_VREG_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 447 | #define SUPC_VREG_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREG) Run during Standby */ |
| mbed_official | 18:da299f395b9e | 448 | #define SUPC_VREG_RUNSTDBY (0x1ul << SUPC_VREG_RUNSTDBY_Pos) |
| mbed_official | 18:da299f395b9e | 449 | #define SUPC_VREG_LPEFF_Pos 8 /**< \brief (SUPC_VREG) Low Power Efficiency */ |
| mbed_official | 18:da299f395b9e | 450 | #define SUPC_VREG_LPEFF (0x1ul << SUPC_VREG_LPEFF_Pos) |
| mbed_official | 18:da299f395b9e | 451 | #define SUPC_VREG_VSVSTEP_Pos 16 /**< \brief (SUPC_VREG) Voltage Scaling Voltage Step */ |
| mbed_official | 18:da299f395b9e | 452 | #define SUPC_VREG_VSVSTEP_Msk (0xFul << SUPC_VREG_VSVSTEP_Pos) |
| mbed_official | 18:da299f395b9e | 453 | #define SUPC_VREG_VSVSTEP(value) ((SUPC_VREG_VSVSTEP_Msk & ((value) << SUPC_VREG_VSVSTEP_Pos))) |
| mbed_official | 18:da299f395b9e | 454 | #define SUPC_VREG_VSPER_Pos 24 /**< \brief (SUPC_VREG) Voltage Scaling Period */ |
| mbed_official | 18:da299f395b9e | 455 | #define SUPC_VREG_VSPER_Msk (0xFFul << SUPC_VREG_VSPER_Pos) |
| mbed_official | 18:da299f395b9e | 456 | #define SUPC_VREG_VSPER(value) ((SUPC_VREG_VSPER_Msk & ((value) << SUPC_VREG_VSPER_Pos))) |
| mbed_official | 18:da299f395b9e | 457 | #define SUPC_VREG_MASK 0xFF0F014Eul /**< \brief (SUPC_VREG) MASK Register */ |
| mbed_official | 18:da299f395b9e | 458 | |
| mbed_official | 18:da299f395b9e | 459 | /* -------- SUPC_VREF : (SUPC Offset: 0x1C) (R/W 32) VREF Control -------- */ |
| mbed_official | 18:da299f395b9e | 460 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 461 | typedef union { |
| mbed_official | 18:da299f395b9e | 462 | struct { |
| mbed_official | 18:da299f395b9e | 463 | uint32_t :1; /*!< bit: 0 Reserved */ |
| mbed_official | 18:da299f395b9e | 464 | uint32_t TSEN:1; /*!< bit: 1 Temperature Sensor Output Enable */ |
| mbed_official | 18:da299f395b9e | 465 | uint32_t VREFOE:1; /*!< bit: 2 Voltage Reference Output Enable */ |
| mbed_official | 18:da299f395b9e | 466 | uint32_t :3; /*!< bit: 3.. 5 Reserved */ |
| mbed_official | 18:da299f395b9e | 467 | uint32_t RUNSTDBY:1; /*!< bit: 6 Run during Standby */ |
| mbed_official | 18:da299f395b9e | 468 | uint32_t ONDEMAND:1; /*!< bit: 7 On Demand Contrl */ |
| mbed_official | 18:da299f395b9e | 469 | uint32_t :8; /*!< bit: 8..15 Reserved */ |
| mbed_official | 18:da299f395b9e | 470 | uint32_t SEL:4; /*!< bit: 16..19 Voltage Reference Selection */ |
| mbed_official | 18:da299f395b9e | 471 | uint32_t :12; /*!< bit: 20..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 472 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 473 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 474 | } SUPC_VREF_Type; |
| mbed_official | 18:da299f395b9e | 475 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 476 | |
| mbed_official | 18:da299f395b9e | 477 | #define SUPC_VREF_OFFSET 0x1C /**< \brief (SUPC_VREF offset) VREF Control */ |
| mbed_official | 18:da299f395b9e | 478 | #define SUPC_VREF_RESETVALUE 0x00000000ul /**< \brief (SUPC_VREF reset_value) VREF Control */ |
| mbed_official | 18:da299f395b9e | 479 | |
| mbed_official | 18:da299f395b9e | 480 | #define SUPC_VREF_TSEN_Pos 1 /**< \brief (SUPC_VREF) Temperature Sensor Output Enable */ |
| mbed_official | 18:da299f395b9e | 481 | #define SUPC_VREF_TSEN (0x1ul << SUPC_VREF_TSEN_Pos) |
| mbed_official | 18:da299f395b9e | 482 | #define SUPC_VREF_VREFOE_Pos 2 /**< \brief (SUPC_VREF) Voltage Reference Output Enable */ |
| mbed_official | 18:da299f395b9e | 483 | #define SUPC_VREF_VREFOE (0x1ul << SUPC_VREF_VREFOE_Pos) |
| mbed_official | 18:da299f395b9e | 484 | #define SUPC_VREF_RUNSTDBY_Pos 6 /**< \brief (SUPC_VREF) Run during Standby */ |
| mbed_official | 18:da299f395b9e | 485 | #define SUPC_VREF_RUNSTDBY (0x1ul << SUPC_VREF_RUNSTDBY_Pos) |
| mbed_official | 18:da299f395b9e | 486 | #define SUPC_VREF_ONDEMAND_Pos 7 /**< \brief (SUPC_VREF) On Demand Contrl */ |
| mbed_official | 18:da299f395b9e | 487 | #define SUPC_VREF_ONDEMAND (0x1ul << SUPC_VREF_ONDEMAND_Pos) |
| mbed_official | 18:da299f395b9e | 488 | #define SUPC_VREF_SEL_Pos 16 /**< \brief (SUPC_VREF) Voltage Reference Selection */ |
| mbed_official | 18:da299f395b9e | 489 | #define SUPC_VREF_SEL_Msk (0xFul << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 490 | #define SUPC_VREF_SEL(value) ((SUPC_VREF_SEL_Msk & ((value) << SUPC_VREF_SEL_Pos))) |
| mbed_official | 18:da299f395b9e | 491 | #define SUPC_VREF_SEL_1V0_Val 0x0ul /**< \brief (SUPC_VREF) 1.0V voltage reference typical value */ |
| mbed_official | 18:da299f395b9e | 492 | #define SUPC_VREF_SEL_1V1_Val 0x1ul /**< \brief (SUPC_VREF) 1.1V voltage reference typical value */ |
| mbed_official | 18:da299f395b9e | 493 | #define SUPC_VREF_SEL_1V2_Val 0x2ul /**< \brief (SUPC_VREF) 1.2V voltage reference typical value */ |
| mbed_official | 18:da299f395b9e | 494 | #define SUPC_VREF_SEL_1V25_Val 0x3ul /**< \brief (SUPC_VREF) 1.25V voltage reference typical value */ |
| mbed_official | 18:da299f395b9e | 495 | #define SUPC_VREF_SEL_2V0_Val 0x4ul /**< \brief (SUPC_VREF) 2.0V voltage reference typical value */ |
| mbed_official | 18:da299f395b9e | 496 | #define SUPC_VREF_SEL_2V2_Val 0x5ul /**< \brief (SUPC_VREF) 2.2V voltage reference typical value */ |
| mbed_official | 18:da299f395b9e | 497 | #define SUPC_VREF_SEL_2V4_Val 0x6ul /**< \brief (SUPC_VREF) 2.4V voltage reference typical value */ |
| mbed_official | 18:da299f395b9e | 498 | #define SUPC_VREF_SEL_2V5_Val 0x7ul /**< \brief (SUPC_VREF) 2.5V voltage reference typical value */ |
| mbed_official | 18:da299f395b9e | 499 | #define SUPC_VREF_SEL_1V0 (SUPC_VREF_SEL_1V0_Val << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 500 | #define SUPC_VREF_SEL_1V1 (SUPC_VREF_SEL_1V1_Val << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 501 | #define SUPC_VREF_SEL_1V2 (SUPC_VREF_SEL_1V2_Val << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 502 | #define SUPC_VREF_SEL_1V25 (SUPC_VREF_SEL_1V25_Val << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 503 | #define SUPC_VREF_SEL_2V0 (SUPC_VREF_SEL_2V0_Val << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 504 | #define SUPC_VREF_SEL_2V2 (SUPC_VREF_SEL_2V2_Val << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 505 | #define SUPC_VREF_SEL_2V4 (SUPC_VREF_SEL_2V4_Val << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 506 | #define SUPC_VREF_SEL_2V5 (SUPC_VREF_SEL_2V5_Val << SUPC_VREF_SEL_Pos) |
| mbed_official | 18:da299f395b9e | 507 | #define SUPC_VREF_MASK 0x000F00C6ul /**< \brief (SUPC_VREF) MASK Register */ |
| mbed_official | 18:da299f395b9e | 508 | |
| mbed_official | 18:da299f395b9e | 509 | /* -------- SUPC_BBPS : (SUPC Offset: 0x20) (R/W 32) Battery Backup Power Switch -------- */ |
| mbed_official | 18:da299f395b9e | 510 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 511 | typedef union { |
| mbed_official | 18:da299f395b9e | 512 | struct { |
| mbed_official | 18:da299f395b9e | 513 | uint32_t CONF:2; /*!< bit: 0.. 1 Battery Backup Configuration */ |
| mbed_official | 18:da299f395b9e | 514 | uint32_t WAKEEN:1; /*!< bit: 2 Wake Enable */ |
| mbed_official | 18:da299f395b9e | 515 | uint32_t PSOKEN:1; /*!< bit: 3 Power Supply OK Enable */ |
| mbed_official | 18:da299f395b9e | 516 | uint32_t :28; /*!< bit: 4..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 517 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 518 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 519 | } SUPC_BBPS_Type; |
| mbed_official | 18:da299f395b9e | 520 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 521 | |
| mbed_official | 18:da299f395b9e | 522 | #define SUPC_BBPS_OFFSET 0x20 /**< \brief (SUPC_BBPS offset) Battery Backup Power Switch */ |
| mbed_official | 18:da299f395b9e | 523 | #define SUPC_BBPS_RESETVALUE 0x00000000ul /**< \brief (SUPC_BBPS reset_value) Battery Backup Power Switch */ |
| mbed_official | 18:da299f395b9e | 524 | |
| mbed_official | 18:da299f395b9e | 525 | #define SUPC_BBPS_CONF_Pos 0 /**< \brief (SUPC_BBPS) Battery Backup Configuration */ |
| mbed_official | 18:da299f395b9e | 526 | #define SUPC_BBPS_CONF_Msk (0x3ul << SUPC_BBPS_CONF_Pos) |
| mbed_official | 18:da299f395b9e | 527 | #define SUPC_BBPS_CONF(value) ((SUPC_BBPS_CONF_Msk & ((value) << SUPC_BBPS_CONF_Pos))) |
| mbed_official | 18:da299f395b9e | 528 | #define SUPC_BBPS_CONF_NONE_Val 0x0ul /**< \brief (SUPC_BBPS) The backup domain is always supplied by main power */ |
| mbed_official | 18:da299f395b9e | 529 | #define SUPC_BBPS_CONF_APWS_Val 0x1ul /**< \brief (SUPC_BBPS) The power switch is handled by the automatic power switch */ |
| mbed_official | 18:da299f395b9e | 530 | #define SUPC_BBPS_CONF_FORCED_Val 0x2ul /**< \brief (SUPC_BBPS) The backup domain is always supplied by battery backup power */ |
| mbed_official | 18:da299f395b9e | 531 | #define SUPC_BBPS_CONF_BOD33_Val 0x3ul /**< \brief (SUPC_BBPS) The power switch is handled by the BOD33 */ |
| mbed_official | 18:da299f395b9e | 532 | #define SUPC_BBPS_CONF_NONE (SUPC_BBPS_CONF_NONE_Val << SUPC_BBPS_CONF_Pos) |
| mbed_official | 18:da299f395b9e | 533 | #define SUPC_BBPS_CONF_APWS (SUPC_BBPS_CONF_APWS_Val << SUPC_BBPS_CONF_Pos) |
| mbed_official | 18:da299f395b9e | 534 | #define SUPC_BBPS_CONF_FORCED (SUPC_BBPS_CONF_FORCED_Val << SUPC_BBPS_CONF_Pos) |
| mbed_official | 18:da299f395b9e | 535 | #define SUPC_BBPS_CONF_BOD33 (SUPC_BBPS_CONF_BOD33_Val << SUPC_BBPS_CONF_Pos) |
| mbed_official | 18:da299f395b9e | 536 | #define SUPC_BBPS_WAKEEN_Pos 2 /**< \brief (SUPC_BBPS) Wake Enable */ |
| mbed_official | 18:da299f395b9e | 537 | #define SUPC_BBPS_WAKEEN (0x1ul << SUPC_BBPS_WAKEEN_Pos) |
| mbed_official | 18:da299f395b9e | 538 | #define SUPC_BBPS_PSOKEN_Pos 3 /**< \brief (SUPC_BBPS) Power Supply OK Enable */ |
| mbed_official | 18:da299f395b9e | 539 | #define SUPC_BBPS_PSOKEN (0x1ul << SUPC_BBPS_PSOKEN_Pos) |
| mbed_official | 18:da299f395b9e | 540 | #define SUPC_BBPS_MASK 0x0000000Ful /**< \brief (SUPC_BBPS) MASK Register */ |
| mbed_official | 18:da299f395b9e | 541 | |
| mbed_official | 18:da299f395b9e | 542 | /* -------- SUPC_BKOUT : (SUPC Offset: 0x24) (R/W 32) Backup Output Control -------- */ |
| mbed_official | 18:da299f395b9e | 543 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 544 | typedef union { |
| mbed_official | 18:da299f395b9e | 545 | struct { |
| mbed_official | 18:da299f395b9e | 546 | uint32_t EN:2; /*!< bit: 0.. 1 Enable Output */ |
| mbed_official | 18:da299f395b9e | 547 | uint32_t :6; /*!< bit: 2.. 7 Reserved */ |
| mbed_official | 18:da299f395b9e | 548 | uint32_t CLR:2; /*!< bit: 8.. 9 Clear Output */ |
| mbed_official | 18:da299f395b9e | 549 | uint32_t :6; /*!< bit: 10..15 Reserved */ |
| mbed_official | 18:da299f395b9e | 550 | uint32_t SET:2; /*!< bit: 16..17 Set Output */ |
| mbed_official | 18:da299f395b9e | 551 | uint32_t :6; /*!< bit: 18..23 Reserved */ |
| mbed_official | 18:da299f395b9e | 552 | uint32_t RTCTGL:2; /*!< bit: 24..25 RTC Toggle Output */ |
| mbed_official | 18:da299f395b9e | 553 | uint32_t :6; /*!< bit: 26..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 554 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 555 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 556 | } SUPC_BKOUT_Type; |
| mbed_official | 18:da299f395b9e | 557 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 558 | |
| mbed_official | 18:da299f395b9e | 559 | #define SUPC_BKOUT_OFFSET 0x24 /**< \brief (SUPC_BKOUT offset) Backup Output Control */ |
| mbed_official | 18:da299f395b9e | 560 | #define SUPC_BKOUT_RESETVALUE 0x00000000ul /**< \brief (SUPC_BKOUT reset_value) Backup Output Control */ |
| mbed_official | 18:da299f395b9e | 561 | |
| mbed_official | 18:da299f395b9e | 562 | #define SUPC_BKOUT_EN_Pos 0 /**< \brief (SUPC_BKOUT) Enable Output */ |
| mbed_official | 18:da299f395b9e | 563 | #define SUPC_BKOUT_EN_Msk (0x3ul << SUPC_BKOUT_EN_Pos) |
| mbed_official | 18:da299f395b9e | 564 | #define SUPC_BKOUT_EN(value) ((SUPC_BKOUT_EN_Msk & ((value) << SUPC_BKOUT_EN_Pos))) |
| mbed_official | 18:da299f395b9e | 565 | #define SUPC_BKOUT_CLR_Pos 8 /**< \brief (SUPC_BKOUT) Clear Output */ |
| mbed_official | 18:da299f395b9e | 566 | #define SUPC_BKOUT_CLR_Msk (0x3ul << SUPC_BKOUT_CLR_Pos) |
| mbed_official | 18:da299f395b9e | 567 | #define SUPC_BKOUT_CLR(value) ((SUPC_BKOUT_CLR_Msk & ((value) << SUPC_BKOUT_CLR_Pos))) |
| mbed_official | 18:da299f395b9e | 568 | #define SUPC_BKOUT_SET_Pos 16 /**< \brief (SUPC_BKOUT) Set Output */ |
| mbed_official | 18:da299f395b9e | 569 | #define SUPC_BKOUT_SET_Msk (0x3ul << SUPC_BKOUT_SET_Pos) |
| mbed_official | 18:da299f395b9e | 570 | #define SUPC_BKOUT_SET(value) ((SUPC_BKOUT_SET_Msk & ((value) << SUPC_BKOUT_SET_Pos))) |
| mbed_official | 18:da299f395b9e | 571 | #define SUPC_BKOUT_RTCTGL_Pos 24 /**< \brief (SUPC_BKOUT) RTC Toggle Output */ |
| mbed_official | 18:da299f395b9e | 572 | #define SUPC_BKOUT_RTCTGL_Msk (0x3ul << SUPC_BKOUT_RTCTGL_Pos) |
| mbed_official | 18:da299f395b9e | 573 | #define SUPC_BKOUT_RTCTGL(value) ((SUPC_BKOUT_RTCTGL_Msk & ((value) << SUPC_BKOUT_RTCTGL_Pos))) |
| mbed_official | 18:da299f395b9e | 574 | #define SUPC_BKOUT_MASK 0x03030303ul /**< \brief (SUPC_BKOUT) MASK Register */ |
| mbed_official | 18:da299f395b9e | 575 | |
| mbed_official | 18:da299f395b9e | 576 | /* -------- SUPC_BKIN : (SUPC Offset: 0x28) (R/ 32) Backup Input Control -------- */ |
| mbed_official | 18:da299f395b9e | 577 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 578 | typedef union { |
| mbed_official | 18:da299f395b9e | 579 | struct { |
| mbed_official | 18:da299f395b9e | 580 | uint32_t BKIN:8; /*!< bit: 0.. 7 Backup Input Value */ |
| mbed_official | 18:da299f395b9e | 581 | uint32_t :24; /*!< bit: 8..31 Reserved */ |
| mbed_official | 18:da299f395b9e | 582 | } bit; /*!< Structure used for bit access */ |
| mbed_official | 18:da299f395b9e | 583 | uint32_t reg; /*!< Type used for register access */ |
| mbed_official | 18:da299f395b9e | 584 | } SUPC_BKIN_Type; |
| mbed_official | 18:da299f395b9e | 585 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 586 | |
| mbed_official | 18:da299f395b9e | 587 | #define SUPC_BKIN_OFFSET 0x28 /**< \brief (SUPC_BKIN offset) Backup Input Control */ |
| mbed_official | 18:da299f395b9e | 588 | #define SUPC_BKIN_RESETVALUE 0x00000000ul /**< \brief (SUPC_BKIN reset_value) Backup Input Control */ |
| mbed_official | 18:da299f395b9e | 589 | |
| mbed_official | 18:da299f395b9e | 590 | #define SUPC_BKIN_BKIN_Pos 0 /**< \brief (SUPC_BKIN) Backup Input Value */ |
| mbed_official | 18:da299f395b9e | 591 | #define SUPC_BKIN_BKIN_Msk (0xFFul << SUPC_BKIN_BKIN_Pos) |
| mbed_official | 18:da299f395b9e | 592 | #define SUPC_BKIN_BKIN(value) ((SUPC_BKIN_BKIN_Msk & ((value) << SUPC_BKIN_BKIN_Pos))) |
| mbed_official | 18:da299f395b9e | 593 | #define SUPC_BKIN_MASK 0x000000FFul /**< \brief (SUPC_BKIN) MASK Register */ |
| mbed_official | 18:da299f395b9e | 594 | |
| mbed_official | 18:da299f395b9e | 595 | /** \brief SUPC hardware registers */ |
| mbed_official | 18:da299f395b9e | 596 | #if !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) |
| mbed_official | 18:da299f395b9e | 597 | typedef struct { |
| mbed_official | 18:da299f395b9e | 598 | __IO SUPC_INTENCLR_Type INTENCLR; /**< \brief Offset: 0x00 (R/W 32) Interrupt Enable Clear */ |
| mbed_official | 18:da299f395b9e | 599 | __IO SUPC_INTENSET_Type INTENSET; /**< \brief Offset: 0x04 (R/W 32) Interrupt Enable Set */ |
| mbed_official | 18:da299f395b9e | 600 | __IO SUPC_INTFLAG_Type INTFLAG; /**< \brief Offset: 0x08 (R/W 32) Interrupt Flag Status and Clear */ |
| mbed_official | 18:da299f395b9e | 601 | __I SUPC_STATUS_Type STATUS; /**< \brief Offset: 0x0C (R/ 32) Power and Clocks Status */ |
| mbed_official | 18:da299f395b9e | 602 | __IO SUPC_BOD33_Type BOD33; /**< \brief Offset: 0x10 (R/W 32) BOD33 Control */ |
| mbed_official | 18:da299f395b9e | 603 | __IO SUPC_BOD12_Type BOD12; /**< \brief Offset: 0x14 (R/W 32) BOD12 Control */ |
| mbed_official | 18:da299f395b9e | 604 | __IO SUPC_VREG_Type VREG; /**< \brief Offset: 0x18 (R/W 32) VREG Control */ |
| mbed_official | 18:da299f395b9e | 605 | __IO SUPC_VREF_Type VREF; /**< \brief Offset: 0x1C (R/W 32) VREF Control */ |
| mbed_official | 18:da299f395b9e | 606 | __IO SUPC_BBPS_Type BBPS; /**< \brief Offset: 0x20 (R/W 32) Battery Backup Power Switch */ |
| mbed_official | 18:da299f395b9e | 607 | __IO SUPC_BKOUT_Type BKOUT; /**< \brief Offset: 0x24 (R/W 32) Backup Output Control */ |
| mbed_official | 18:da299f395b9e | 608 | __I SUPC_BKIN_Type BKIN; /**< \brief Offset: 0x28 (R/ 32) Backup Input Control */ |
| mbed_official | 18:da299f395b9e | 609 | } Supc; |
| mbed_official | 18:da299f395b9e | 610 | #endif /* !(defined(__ASSEMBLY__) || defined(__IAR_SYSTEMS_ASM__)) */ |
| mbed_official | 18:da299f395b9e | 611 | |
| mbed_official | 18:da299f395b9e | 612 | /*@}*/ |
| mbed_official | 18:da299f395b9e | 613 | |
| mbed_official | 18:da299f395b9e | 614 | #endif /* _SAML21_SUPC_COMPONENT_ */ |