mbed library sources. Supersedes mbed-src.
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targets/TARGET_NXP/TARGET_LPC15XX/us_ticker.c@160:d5399cc887bb, 2017-03-14 (annotated)
- Committer:
- <>
- Date:
- Tue Mar 14 16:40:56 2017 +0000
- Revision:
- 160:d5399cc887bb
- Parent:
- 149:156823d33999
This updates the lib to the mbed lib v138
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
<> | 144:ef7eb2e8f9f7 | 1 | /* mbed Microcontroller Library |
<> | 144:ef7eb2e8f9f7 | 2 | * Copyright (c) 2006-2013 ARM Limited |
<> | 144:ef7eb2e8f9f7 | 3 | * |
<> | 144:ef7eb2e8f9f7 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
<> | 144:ef7eb2e8f9f7 | 5 | * you may not use this file except in compliance with the License. |
<> | 144:ef7eb2e8f9f7 | 6 | * You may obtain a copy of the License at |
<> | 144:ef7eb2e8f9f7 | 7 | * |
<> | 144:ef7eb2e8f9f7 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
<> | 144:ef7eb2e8f9f7 | 9 | * |
<> | 144:ef7eb2e8f9f7 | 10 | * Unless required by applicable law or agreed to in writing, software |
<> | 144:ef7eb2e8f9f7 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
<> | 144:ef7eb2e8f9f7 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
<> | 144:ef7eb2e8f9f7 | 13 | * See the License for the specific language governing permissions and |
<> | 144:ef7eb2e8f9f7 | 14 | * limitations under the License. |
<> | 144:ef7eb2e8f9f7 | 15 | */ |
<> | 144:ef7eb2e8f9f7 | 16 | #include <stddef.h> |
<> | 144:ef7eb2e8f9f7 | 17 | #include "us_ticker_api.h" |
<> | 144:ef7eb2e8f9f7 | 18 | #include "PeripheralNames.h" |
<> | 160:d5399cc887bb | 19 | #include "mbed_critical.h" |
<> | 144:ef7eb2e8f9f7 | 20 | |
<> | 144:ef7eb2e8f9f7 | 21 | #define US_TICKER_TIMER_IRQn SCT3_IRQn |
<> | 144:ef7eb2e8f9f7 | 22 | |
<> | 144:ef7eb2e8f9f7 | 23 | int us_ticker_inited = 0; |
<> | 144:ef7eb2e8f9f7 | 24 | |
<> | 144:ef7eb2e8f9f7 | 25 | void us_ticker_init(void) { |
<> | 144:ef7eb2e8f9f7 | 26 | if (us_ticker_inited) |
<> | 144:ef7eb2e8f9f7 | 27 | return; |
<> | 144:ef7eb2e8f9f7 | 28 | |
<> | 144:ef7eb2e8f9f7 | 29 | us_ticker_inited = 1; |
<> | 144:ef7eb2e8f9f7 | 30 | |
<> | 144:ef7eb2e8f9f7 | 31 | // Enable the SCT3 clock |
<> | 144:ef7eb2e8f9f7 | 32 | LPC_SYSCON->SYSAHBCLKCTRL1 |= (1 << 5); |
<> | 144:ef7eb2e8f9f7 | 33 | |
<> | 144:ef7eb2e8f9f7 | 34 | // Clear peripheral reset the SCT3 |
<> | 144:ef7eb2e8f9f7 | 35 | LPC_SYSCON->PRESETCTRL1 |= (1 << 5); |
<> | 144:ef7eb2e8f9f7 | 36 | LPC_SYSCON->PRESETCTRL1 &= ~(1 << 5); |
<> | 144:ef7eb2e8f9f7 | 37 | |
<> | 144:ef7eb2e8f9f7 | 38 | // Configure SCT3 as a 1MHz 32-bit counter with no auto limiting or match reload |
<> | 144:ef7eb2e8f9f7 | 39 | char sctClkDiv = ((SystemCoreClock + 1000000 - 1) / 1000000) - 1; |
<> | 144:ef7eb2e8f9f7 | 40 | LPC_SCT3->CONFIG = (1 << 7) | (1 << 0); |
<> | 144:ef7eb2e8f9f7 | 41 | LPC_SCT3->CTRL = (sctClkDiv << 5) | (1 << 3) | (1 << 2); |
<> | 144:ef7eb2e8f9f7 | 42 | |
<> | 144:ef7eb2e8f9f7 | 43 | // Configure SCT3 event 0 to fire on match register 0 |
<> | 144:ef7eb2e8f9f7 | 44 | LPC_SCT3->EV0_STATE = (1 << 0); |
<> | 144:ef7eb2e8f9f7 | 45 | LPC_SCT3->EV0_CTRL = (0x1 << 12); |
<> | 144:ef7eb2e8f9f7 | 46 | |
<> | 144:ef7eb2e8f9f7 | 47 | // Start SCT3 |
<> | 144:ef7eb2e8f9f7 | 48 | LPC_SCT3->CTRL &= ~(1 << 2); |
<> | 144:ef7eb2e8f9f7 | 49 | |
<> | 144:ef7eb2e8f9f7 | 50 | // Set SCT3 interrupt vector |
<> | 144:ef7eb2e8f9f7 | 51 | NVIC_SetVector(US_TICKER_TIMER_IRQn, (uint32_t)us_ticker_irq_handler); |
<> | 144:ef7eb2e8f9f7 | 52 | NVIC_EnableIRQ(US_TICKER_TIMER_IRQn); |
<> | 144:ef7eb2e8f9f7 | 53 | } |
<> | 144:ef7eb2e8f9f7 | 54 | |
<> | 144:ef7eb2e8f9f7 | 55 | uint32_t us_ticker_read() { |
<> | 144:ef7eb2e8f9f7 | 56 | if (!us_ticker_inited) |
<> | 144:ef7eb2e8f9f7 | 57 | us_ticker_init(); |
<> | 144:ef7eb2e8f9f7 | 58 | |
<> | 144:ef7eb2e8f9f7 | 59 | // Return SCT3 count value |
<> | 144:ef7eb2e8f9f7 | 60 | return LPC_SCT3->COUNT; |
<> | 144:ef7eb2e8f9f7 | 61 | } |
<> | 144:ef7eb2e8f9f7 | 62 | |
<> | 144:ef7eb2e8f9f7 | 63 | void us_ticker_set_interrupt(timestamp_t timestamp) { |
<> | 144:ef7eb2e8f9f7 | 64 | // Set SCT3 match register 0 (critical section) |
<> | 144:ef7eb2e8f9f7 | 65 | core_util_critical_section_enter(); |
<> | 144:ef7eb2e8f9f7 | 66 | LPC_SCT3->CTRL |= (1 << 2); |
<> | 144:ef7eb2e8f9f7 | 67 | LPC_SCT3->MATCH0 = (uint32_t)timestamp; |
<> | 144:ef7eb2e8f9f7 | 68 | LPC_SCT3->CTRL &= ~(1 << 2); |
<> | 144:ef7eb2e8f9f7 | 69 | core_util_critical_section_exit(); |
<> | 144:ef7eb2e8f9f7 | 70 | |
<> | 144:ef7eb2e8f9f7 | 71 | // Enable interrupt on SCT3 event 0 |
<> | 144:ef7eb2e8f9f7 | 72 | LPC_SCT3->EVEN = (1 << 0); |
<> | 144:ef7eb2e8f9f7 | 73 | } |
<> | 144:ef7eb2e8f9f7 | 74 | |
<> | 144:ef7eb2e8f9f7 | 75 | void us_ticker_disable_interrupt(void) { |
<> | 144:ef7eb2e8f9f7 | 76 | // Disable interrupt on SCT3 event 0 |
<> | 144:ef7eb2e8f9f7 | 77 | LPC_SCT3->EVEN = 0; |
<> | 144:ef7eb2e8f9f7 | 78 | } |
<> | 144:ef7eb2e8f9f7 | 79 | |
<> | 144:ef7eb2e8f9f7 | 80 | void us_ticker_clear_interrupt(void) { |
<> | 144:ef7eb2e8f9f7 | 81 | // Clear SCT3 event 0 interrupt flag |
<> | 144:ef7eb2e8f9f7 | 82 | LPC_SCT3->EVFLAG = (1 << 0); |
<> | 144:ef7eb2e8f9f7 | 83 | } |