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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/TARGET_MTS_GAMBIT/fsl_clock_config.c@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #include "fsl_common.h"
<> 154:37f96f9d4de2 32 #include "fsl_smc.h"
<> 154:37f96f9d4de2 33 #include "fsl_clock_config.h"
<> 154:37f96f9d4de2 34
<> 154:37f96f9d4de2 35 /*******************************************************************************
<> 154:37f96f9d4de2 36 * Definitions
<> 154:37f96f9d4de2 37 ******************************************************************************/
<> 154:37f96f9d4de2 38 /*! @brief Clock configuration structure. */
<> 154:37f96f9d4de2 39 typedef struct _clock_config
<> 154:37f96f9d4de2 40 {
<> 154:37f96f9d4de2 41 mcg_config_t mcgConfig; /*!< MCG configuration. */
<> 154:37f96f9d4de2 42 sim_clock_config_t simConfig; /*!< SIM configuration. */
<> 154:37f96f9d4de2 43 osc_config_t oscConfig; /*!< OSC configuration. */
<> 154:37f96f9d4de2 44 uint32_t coreClock; /*!< core clock frequency. */
<> 154:37f96f9d4de2 45 } clock_config_t;
<> 154:37f96f9d4de2 46
<> 154:37f96f9d4de2 47 /*******************************************************************************
<> 154:37f96f9d4de2 48 * Variables
<> 154:37f96f9d4de2 49 ******************************************************************************/
<> 154:37f96f9d4de2 50 /* System clock frequency. */
<> 154:37f96f9d4de2 51 extern uint32_t SystemCoreClock;
<> 154:37f96f9d4de2 52
<> 154:37f96f9d4de2 53 /* Configuration for enter VLPR mode. Core clock = 4MHz. */
<> 154:37f96f9d4de2 54 const clock_config_t g_defaultClockConfigVlpr = {
<> 154:37f96f9d4de2 55 .mcgConfig =
<> 154:37f96f9d4de2 56 {
<> 154:37f96f9d4de2 57 .mcgMode = kMCG_ModeBLPI, /* Work in BLPI mode. */
<> 154:37f96f9d4de2 58 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
<> 154:37f96f9d4de2 59 .ircs = kMCG_IrcFast, /* Select IRC4M. */
<> 154:37f96f9d4de2 60 .fcrdiv = 0U, /* FCRDIV is 0. */
<> 154:37f96f9d4de2 61
<> 154:37f96f9d4de2 62 .frdiv = 0U,
<> 154:37f96f9d4de2 63 .drs = kMCG_DrsLow, /* Low frequency range. */
<> 154:37f96f9d4de2 64 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
<> 154:37f96f9d4de2 65 .oscsel = kMCG_OscselOsc, /* Select OSC. */
<> 154:37f96f9d4de2 66
<> 154:37f96f9d4de2 67 .pll0Config =
<> 154:37f96f9d4de2 68 {
<> 154:37f96f9d4de2 69 .enableMode = 0U, /* Don't eanble PLL. */
<> 154:37f96f9d4de2 70 .prdiv = 0U,
<> 154:37f96f9d4de2 71 .vdiv = 0U,
<> 154:37f96f9d4de2 72 },
<> 154:37f96f9d4de2 73 },
<> 154:37f96f9d4de2 74 .simConfig =
<> 154:37f96f9d4de2 75 {
<> 154:37f96f9d4de2 76 .pllFllSel = 3U, /* PLLFLLSEL select IRC48MCLK. */
<> 154:37f96f9d4de2 77 .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
<> 154:37f96f9d4de2 78 .clkdiv1 = 0x00040000U, /* SIM_CLKDIV1. */
<> 154:37f96f9d4de2 79 },
<> 154:37f96f9d4de2 80 .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
<> 154:37f96f9d4de2 81 .capLoad = 0,
<> 154:37f96f9d4de2 82 .workMode = kOSC_ModeExt,
<> 154:37f96f9d4de2 83 .oscerConfig =
<> 154:37f96f9d4de2 84 {
<> 154:37f96f9d4de2 85 .enableMode = kOSC_ErClkEnable,
<> 154:37f96f9d4de2 86 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
<> 154:37f96f9d4de2 87 .erclkDiv = 0U,
<> 154:37f96f9d4de2 88 #endif
<> 154:37f96f9d4de2 89 }},
<> 154:37f96f9d4de2 90 .coreClock = 4000000U, /* Core clock frequency */
<> 154:37f96f9d4de2 91 };
<> 154:37f96f9d4de2 92
<> 154:37f96f9d4de2 93 /* Configuration for enter RUN mode. Core clock = 120MHz. */
<> 154:37f96f9d4de2 94 const clock_config_t g_defaultClockConfigRun = {
<> 154:37f96f9d4de2 95 .mcgConfig =
<> 154:37f96f9d4de2 96 {
<> 154:37f96f9d4de2 97 .mcgMode = kMCG_ModePEE, /* Work in PEE mode. */
<> 154:37f96f9d4de2 98 .irclkEnableMode = kMCG_IrclkEnable, /* MCGIRCLK enable. */
<> 154:37f96f9d4de2 99 .ircs = kMCG_IrcSlow, /* Select IRC32k. */
<> 154:37f96f9d4de2 100 .fcrdiv = 0U, /* FCRDIV is 0. */
<> 154:37f96f9d4de2 101
<> 154:37f96f9d4de2 102 .frdiv = 7U,
<> 154:37f96f9d4de2 103 .drs = kMCG_DrsLow, /* Low frequency range. */
<> 154:37f96f9d4de2 104 .dmx32 = kMCG_Dmx32Default, /* DCO has a default range of 25%. */
<> 154:37f96f9d4de2 105 .oscsel = kMCG_OscselOsc, /* Select OSC. */
<> 154:37f96f9d4de2 106
<> 154:37f96f9d4de2 107 .pll0Config =
<> 154:37f96f9d4de2 108 {
<> 154:37f96f9d4de2 109 .enableMode = 0U, .prdiv = 0x13U, .vdiv = 0x18U,
<> 154:37f96f9d4de2 110 },
<> 154:37f96f9d4de2 111 },
<> 154:37f96f9d4de2 112 .simConfig =
<> 154:37f96f9d4de2 113 {
<> 154:37f96f9d4de2 114 .pllFllSel = 1U, /* PLLFLLSEL select PLL. */
<> 154:37f96f9d4de2 115 .er32kSrc = 2U, /* ERCLK32K selection, use RTC. */
<> 154:37f96f9d4de2 116 .clkdiv1 = 0x01140000U, /* SIM_CLKDIV1. */
<> 154:37f96f9d4de2 117 },
<> 154:37f96f9d4de2 118 .oscConfig = {.freq = BOARD_XTAL0_CLK_HZ,
<> 154:37f96f9d4de2 119 .capLoad = 0,
<> 154:37f96f9d4de2 120 .workMode = kOSC_ModeExt,
<> 154:37f96f9d4de2 121 .oscerConfig =
<> 154:37f96f9d4de2 122 {
<> 154:37f96f9d4de2 123 .enableMode = kOSC_ErClkEnable,
<> 154:37f96f9d4de2 124 #if (defined(FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER) && FSL_FEATURE_OSC_HAS_EXT_REF_CLOCK_DIVIDER)
<> 154:37f96f9d4de2 125 .erclkDiv = 0U,
<> 154:37f96f9d4de2 126 #endif
<> 154:37f96f9d4de2 127 }},
<> 154:37f96f9d4de2 128 .coreClock = 120000000U, /* Core clock frequency */
<> 154:37f96f9d4de2 129 };
<> 154:37f96f9d4de2 130
<> 154:37f96f9d4de2 131 /*******************************************************************************
<> 154:37f96f9d4de2 132 * Code
<> 154:37f96f9d4de2 133 ******************************************************************************/
<> 154:37f96f9d4de2 134 /*
<> 154:37f96f9d4de2 135 * How to setup clock using clock driver functions:
<> 154:37f96f9d4de2 136 *
<> 154:37f96f9d4de2 137 * 1. CLOCK_SetSimSafeDivs, to make sure core clock, bus clock, flexbus clock
<> 154:37f96f9d4de2 138 * and flash clock are in allowed range during clock mode switch.
<> 154:37f96f9d4de2 139 *
<> 154:37f96f9d4de2 140 * 2. Call CLOCK_Osc0Init to setup OSC clock, if it is used in target mode.
<> 154:37f96f9d4de2 141 *
<> 154:37f96f9d4de2 142 * 3. Set MCG configuration, MCG includes three parts: FLL clock, PLL clock and
<> 154:37f96f9d4de2 143 * internal reference clock(MCGIRCLK). Follow the steps to setup:
<> 154:37f96f9d4de2 144 *
<> 154:37f96f9d4de2 145 * 1). Call CLOCK_BootToXxxMode to set MCG to target mode.
<> 154:37f96f9d4de2 146 *
<> 154:37f96f9d4de2 147 * 2). If target mode is FBI/BLPI/PBI mode, the MCGIRCLK has been configured
<> 154:37f96f9d4de2 148 * correctly. For other modes, need to call CLOCK_SetInternalRefClkConfig
<> 154:37f96f9d4de2 149 * explicitly to setup MCGIRCLK.
<> 154:37f96f9d4de2 150 *
<> 154:37f96f9d4de2 151 * 3). Don't need to configure FLL explicitly, because if target mode is FLL
<> 154:37f96f9d4de2 152 * mode, then FLL has been configured by the function CLOCK_BootToXxxMode,
<> 154:37f96f9d4de2 153 * if the target mode is not FLL mode, the FLL is disabled.
<> 154:37f96f9d4de2 154 *
<> 154:37f96f9d4de2 155 * 4). If target mode is PEE/PBE/PEI/PBI mode, then the related PLL has been
<> 154:37f96f9d4de2 156 * setup by CLOCK_BootToXxxMode. In FBE/FBI/FEE/FBE mode, the PLL could
<> 154:37f96f9d4de2 157 * be enabled independently, call CLOCK_EnablePll0 explicitly in this case.
<> 154:37f96f9d4de2 158 *
<> 154:37f96f9d4de2 159 * 4. Call CLOCK_SetSimConfig to set the clock configuration in SIM.
<> 154:37f96f9d4de2 160 */
<> 154:37f96f9d4de2 161
<> 154:37f96f9d4de2 162 void BOARD_BootClockVLPR(void)
<> 154:37f96f9d4de2 163 {
<> 154:37f96f9d4de2 164 CLOCK_SetSimSafeDivs();
<> 154:37f96f9d4de2 165
<> 154:37f96f9d4de2 166 CLOCK_BootToBlpiMode(g_defaultClockConfigVlpr.mcgConfig.fcrdiv, g_defaultClockConfigVlpr.mcgConfig.ircs,
<> 154:37f96f9d4de2 167 g_defaultClockConfigVlpr.mcgConfig.irclkEnableMode);
<> 154:37f96f9d4de2 168
<> 154:37f96f9d4de2 169 CLOCK_SetSimConfig(&g_defaultClockConfigVlpr.simConfig);
<> 154:37f96f9d4de2 170
<> 154:37f96f9d4de2 171 SystemCoreClock = g_defaultClockConfigVlpr.coreClock;
<> 154:37f96f9d4de2 172
<> 154:37f96f9d4de2 173 SMC_SetPowerModeProtection(SMC, kSMC_AllowPowerModeAll);
<> 154:37f96f9d4de2 174 SMC_SetPowerModeVlpr(SMC, false);
<> 154:37f96f9d4de2 175 while (SMC_GetPowerModeState(SMC) != kSMC_PowerStateVlpr)
<> 154:37f96f9d4de2 176 {
<> 154:37f96f9d4de2 177 }
<> 154:37f96f9d4de2 178 }
<> 154:37f96f9d4de2 179
<> 154:37f96f9d4de2 180 void BOARD_BootClockRUN(void)
<> 154:37f96f9d4de2 181 {
<> 154:37f96f9d4de2 182 CLOCK_SetSimSafeDivs();
<> 154:37f96f9d4de2 183
<> 154:37f96f9d4de2 184 CLOCK_InitOsc0(&g_defaultClockConfigRun.oscConfig);
<> 154:37f96f9d4de2 185 CLOCK_SetXtal0Freq(BOARD_XTAL0_CLK_HZ);
<> 154:37f96f9d4de2 186
<> 154:37f96f9d4de2 187 CLOCK_BootToPeeMode(g_defaultClockConfigRun.mcgConfig.oscsel, kMCG_PllClkSelPll0,
<> 154:37f96f9d4de2 188 &g_defaultClockConfigRun.mcgConfig.pll0Config);
<> 154:37f96f9d4de2 189
<> 154:37f96f9d4de2 190 CLOCK_SetInternalRefClkConfig(g_defaultClockConfigRun.mcgConfig.irclkEnableMode,
<> 154:37f96f9d4de2 191 g_defaultClockConfigRun.mcgConfig.ircs, g_defaultClockConfigRun.mcgConfig.fcrdiv);
<> 154:37f96f9d4de2 192
<> 154:37f96f9d4de2 193 CLOCK_SetSimConfig(&g_defaultClockConfigRun.simConfig);
<> 154:37f96f9d4de2 194
<> 154:37f96f9d4de2 195 SystemCoreClock = g_defaultClockConfigRun.coreClock;
<> 154:37f96f9d4de2 196 }