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targets/TARGET_NXP/TARGET_LPC82X/device/LPC82x.h@162:16168a1438f3, 2017-04-08 (annotated)

Committer:
funshine
Date:
Sat Apr 08 17:03:55 2017 +0000
Revision:
162:16168a1438f3
Parent:
149:156823d33999 
add code to handle serial port rx error in uart_irq()

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1
<> 144:ef7eb2e8f9f7 2 /****************************************************************************************************//**
<> 144:ef7eb2e8f9f7 3 * @file LPC82x.h
<> 144:ef7eb2e8f9f7 4 *
<> 144:ef7eb2e8f9f7 5 * @brief CMSIS Cortex-M0PLUS Peripheral Access Layer Header File for
<> 144:ef7eb2e8f9f7 6 * LPC82x from .
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * @version V0.4
<> 144:ef7eb2e8f9f7 9 * @date 17. June 2014
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * @note Generated with SVDConv V2.80
<> 144:ef7eb2e8f9f7 12 * from CMSIS SVD File 'LPC82x.svd' Version 0.4,
<> 144:ef7eb2e8f9f7 13 *******************************************************************************************************/
<> 144:ef7eb2e8f9f7 14
<> 144:ef7eb2e8f9f7 15
<> 144:ef7eb2e8f9f7 16
<> 144:ef7eb2e8f9f7 17 /** @addtogroup (null)
<> 144:ef7eb2e8f9f7 18 * @{
<> 144:ef7eb2e8f9f7 19 */
<> 144:ef7eb2e8f9f7 20
<> 144:ef7eb2e8f9f7 21 /** @addtogroup LPC82x
<> 144:ef7eb2e8f9f7 22 * @{
<> 144:ef7eb2e8f9f7 23 */
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 #ifndef LPC82X_H
<> 144:ef7eb2e8f9f7 26 #define LPC82X_H
<> 144:ef7eb2e8f9f7 27
<> 144:ef7eb2e8f9f7 28 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 29 extern "C" {
<> 144:ef7eb2e8f9f7 30 #endif
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /* ------------------------- Interrupt Number Definition ------------------------ */
<> 144:ef7eb2e8f9f7 34
<> 144:ef7eb2e8f9f7 35 typedef enum {
<> 144:ef7eb2e8f9f7 36 /* ----------------- Cortex-M0PLUS Processor Exceptions Numbers ----------------- */
<> 144:ef7eb2e8f9f7 37 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
<> 144:ef7eb2e8f9f7 38 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
<> 144:ef7eb2e8f9f7 39 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
<> 144:ef7eb2e8f9f7 40 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
<> 144:ef7eb2e8f9f7 41 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
<> 144:ef7eb2e8f9f7 42 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
<> 144:ef7eb2e8f9f7 43 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
<> 144:ef7eb2e8f9f7 44 /* ---------------------- LPC82x Specific Interrupt Numbers --------------------- */
<> 144:ef7eb2e8f9f7 45 SPI0_IRQn = 0, /*!< 0 SPI0 */
<> 144:ef7eb2e8f9f7 46 SPI1_IRQn = 1, /*!< 1 SPI1 */
<> 144:ef7eb2e8f9f7 47 UART0_IRQn = 3, /*!< 3 UART0 */
<> 144:ef7eb2e8f9f7 48 UART1_IRQn = 4, /*!< 4 UART1 */
<> 144:ef7eb2e8f9f7 49 UART2_IRQn = 5, /*!< 5 UART2 */
<> 144:ef7eb2e8f9f7 50 I2C1_IRQn = 7, /*!< 7 I2C1 */
<> 144:ef7eb2e8f9f7 51 I2C0_IRQn = 8, /*!< 8 I2C0 */
<> 144:ef7eb2e8f9f7 52 SCT_IRQn = 9, /*!< 9 SCT */
<> 144:ef7eb2e8f9f7 53 MRT_IRQn = 10, /*!< 10 MRT */
<> 144:ef7eb2e8f9f7 54 CMP_IRQn = 11, /*!< 11 CMP */
<> 144:ef7eb2e8f9f7 55 WDT_IRQn = 12, /*!< 12 WDT */
<> 144:ef7eb2e8f9f7 56 BOD_IRQn = 13, /*!< 13 BOD */
<> 144:ef7eb2e8f9f7 57 FLASH_IRQn = 14, /*!< 14 FLASH */
<> 144:ef7eb2e8f9f7 58 WKT_IRQn = 15, /*!< 15 WKT */
<> 144:ef7eb2e8f9f7 59 ADC_SEQA_IRQn = 16, /*!< 16 ADC_SEQA */
<> 144:ef7eb2e8f9f7 60 ADC_SEQB_IRQn = 17, /*!< 17 ADC_SEQB */
<> 144:ef7eb2e8f9f7 61 ADC_THCMP_IRQn = 18, /*!< 18 ADC_THCMP */
<> 144:ef7eb2e8f9f7 62 ADC_OVR_IRQn = 19, /*!< 19 ADC_OVR */
<> 144:ef7eb2e8f9f7 63 DMA_IRQn = 20, /*!< 20 DMA */
<> 144:ef7eb2e8f9f7 64 I2C2_IRQn = 21, /*!< 21 I2C2 */
<> 144:ef7eb2e8f9f7 65 I2C3_IRQn = 22, /*!< 22 I2C3 */
<> 144:ef7eb2e8f9f7 66 PIN_INT0_IRQn = 24, /*!< 24 PIN_INT0 */
<> 144:ef7eb2e8f9f7 67 PIN_INT1_IRQn = 25, /*!< 25 PIN_INT1 */
<> 144:ef7eb2e8f9f7 68 PIN_INT2_IRQn = 26, /*!< 26 PIN_INT2 */
<> 144:ef7eb2e8f9f7 69 PIN_INT3_IRQn = 27, /*!< 27 PIN_INT3 */
<> 144:ef7eb2e8f9f7 70 PIN_INT4_IRQn = 28, /*!< 28 PIN_INT4 */
<> 144:ef7eb2e8f9f7 71 PIN_INT5_IRQn = 29, /*!< 29 PIN_INT5 */
<> 144:ef7eb2e8f9f7 72 PIN_INT6_IRQn = 30, /*!< 30 PIN_INT6 */
<> 144:ef7eb2e8f9f7 73 PIN_INT7_IRQn = 31 /*!< 31 PIN_INT7 */
<> 144:ef7eb2e8f9f7 74 } IRQn_Type;
<> 144:ef7eb2e8f9f7 75
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 /** @addtogroup Configuration_of_CMSIS
<> 144:ef7eb2e8f9f7 78 * @{
<> 144:ef7eb2e8f9f7 79 */
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81
<> 144:ef7eb2e8f9f7 82 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 83 /* ================ Processor and Core Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 84 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 /* ----------------Configuration of the Cortex-M0PLUS Processor and Core Peripherals---------------- */
<> 144:ef7eb2e8f9f7 87 #define __CM0PLUS_REV 0x0001 /*!< Cortex-M0PLUS Core Revision */
<> 144:ef7eb2e8f9f7 88 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 144:ef7eb2e8f9f7 89 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
<> 144:ef7eb2e8f9f7 90 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 144:ef7eb2e8f9f7 91 #define __VTOR_PRESENT 1 /*!< Set to 1 if CPU supports Vector Table Offset Register */
<> 144:ef7eb2e8f9f7 92 /** @} */ /* End of group Configuration_of_CMSIS */
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 #include "core_cm0plus.h" /*!< Cortex-M0PLUS processor and core peripherals */
<> 144:ef7eb2e8f9f7 95 #include "system_LPC82x.h" /*!< LPC82x System */
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 99 /* ================ Device Specific Peripheral Section ================ */
<> 144:ef7eb2e8f9f7 100 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 /** @addtogroup Device_Peripheral_Registers
<> 144:ef7eb2e8f9f7 104 * @{
<> 144:ef7eb2e8f9f7 105 */
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* ------------------- Start of section using anonymous unions ------------------ */
<> 144:ef7eb2e8f9f7 109 #if defined(__CC_ARM)
<> 144:ef7eb2e8f9f7 110 #pragma push
<> 144:ef7eb2e8f9f7 111 #pragma anon_unions
<> 144:ef7eb2e8f9f7 112 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 113 #pragma language=extended
<> 144:ef7eb2e8f9f7 114 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 115 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 116 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 117 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 118 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 119 #pragma warning 586
<> 144:ef7eb2e8f9f7 120 #else
<> 144:ef7eb2e8f9f7 121 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 122 #endif
<> 144:ef7eb2e8f9f7 123
<> 144:ef7eb2e8f9f7 124
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 127 /* ================ WWDT ================ */
<> 144:ef7eb2e8f9f7 128 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 129
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /**
<> 144:ef7eb2e8f9f7 132 * @brief Windowed Watchdog Timer (WWDT) (WWDT)
<> 144:ef7eb2e8f9f7 133 */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 typedef struct { /*!< (@ 0x40000000) WWDT Structure */
<> 144:ef7eb2e8f9f7 136 __IO uint32_t MOD; /*!< (@ 0x40000000) Watchdog mode register. This register contains
<> 144:ef7eb2e8f9f7 137 the basic mode and status of the Watchdog Timer. */
<> 144:ef7eb2e8f9f7 138 __IO uint32_t TC; /*!< (@ 0x40000004) Watchdog timer constant register. This 24-bit
<> 144:ef7eb2e8f9f7 139 register determines the time-out value. */
<> 144:ef7eb2e8f9f7 140 __O uint32_t FEED; /*!< (@ 0x40000008) Watchdog feed sequence register. Writing 0xAA
<> 144:ef7eb2e8f9f7 141 followed by 0x55 to this register reloads the Watchdog timer
<> 144:ef7eb2e8f9f7 142 with the value contained in WDTC. */
<> 144:ef7eb2e8f9f7 143 __I uint32_t TV; /*!< (@ 0x4000000C) Watchdog timer value register. This 24-bit register
<> 144:ef7eb2e8f9f7 144 reads out the current value of the Watchdog timer. */
<> 144:ef7eb2e8f9f7 145 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 146 __IO uint32_t WARNINT; /*!< (@ 0x40000014) Watchdog Warning Interrupt compare value. */
<> 144:ef7eb2e8f9f7 147 __IO uint32_t WINDOW; /*!< (@ 0x40000018) Watchdog Window compare value. */
<> 144:ef7eb2e8f9f7 148 } LPC_WWDT_Type;
<> 144:ef7eb2e8f9f7 149
<> 144:ef7eb2e8f9f7 150
<> 144:ef7eb2e8f9f7 151 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 152 /* ================ MRT ================ */
<> 144:ef7eb2e8f9f7 153 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 154
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 /**
<> 144:ef7eb2e8f9f7 157 * @brief Multi-Rate Timer (MRT) (MRT)
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 typedef struct { /*!< (@ 0x40004000) MRT Structure */
<> 144:ef7eb2e8f9f7 161 __IO uint32_t INTVAL0; /*!< (@ 0x40004000) MRT0 Time interval value register. This value
<> 144:ef7eb2e8f9f7 162 is loaded into the TIMER0 register. */
<> 144:ef7eb2e8f9f7 163 __I uint32_t TIMER0; /*!< (@ 0x40004004) MRT0 Timer register. This register reads the
<> 144:ef7eb2e8f9f7 164 value of the down-counter. */
<> 144:ef7eb2e8f9f7 165 __IO uint32_t CTRL0; /*!< (@ 0x40004008) MRT0 Control register. This register controls
<> 144:ef7eb2e8f9f7 166 the MRT0 modes. */
<> 144:ef7eb2e8f9f7 167 __IO uint32_t STAT0; /*!< (@ 0x4000400C) MRT0 Status register. */
<> 144:ef7eb2e8f9f7 168 __IO uint32_t INTVAL1; /*!< (@ 0x40004010) MRT0 Time interval value register. This value
<> 144:ef7eb2e8f9f7 169 is loaded into the TIMER0 register. */
<> 144:ef7eb2e8f9f7 170 __I uint32_t TIMER1; /*!< (@ 0x40004014) MRT0 Timer register. This register reads the
<> 144:ef7eb2e8f9f7 171 value of the down-counter. */
<> 144:ef7eb2e8f9f7 172 __IO uint32_t CTRL1; /*!< (@ 0x40004018) MRT0 Control register. This register controls
<> 144:ef7eb2e8f9f7 173 the MRT0 modes. */
<> 144:ef7eb2e8f9f7 174 __IO uint32_t STAT1; /*!< (@ 0x4000401C) MRT0 Status register. */
<> 144:ef7eb2e8f9f7 175 __IO uint32_t INTVAL2; /*!< (@ 0x40004020) MRT0 Time interval value register. This value
<> 144:ef7eb2e8f9f7 176 is loaded into the TIMER0 register. */
<> 144:ef7eb2e8f9f7 177 __I uint32_t TIMER2; /*!< (@ 0x40004024) MRT0 Timer register. This register reads the
<> 144:ef7eb2e8f9f7 178 value of the down-counter. */
<> 144:ef7eb2e8f9f7 179 __IO uint32_t CTRL2; /*!< (@ 0x40004028) MRT0 Control register. This register controls
<> 144:ef7eb2e8f9f7 180 the MRT0 modes. */
<> 144:ef7eb2e8f9f7 181 __IO uint32_t STAT2; /*!< (@ 0x4000402C) MRT0 Status register. */
<> 144:ef7eb2e8f9f7 182 __IO uint32_t INTVAL3; /*!< (@ 0x40004030) MRT0 Time interval value register. This value
<> 144:ef7eb2e8f9f7 183 is loaded into the TIMER0 register. */
<> 144:ef7eb2e8f9f7 184 __I uint32_t TIMER3; /*!< (@ 0x40004034) MRT0 Timer register. This register reads the
<> 144:ef7eb2e8f9f7 185 value of the down-counter. */
<> 144:ef7eb2e8f9f7 186 __IO uint32_t CTRL3; /*!< (@ 0x40004038) MRT0 Control register. This register controls
<> 144:ef7eb2e8f9f7 187 the MRT0 modes. */
<> 144:ef7eb2e8f9f7 188 __IO uint32_t STAT3; /*!< (@ 0x4000403C) MRT0 Status register. */
<> 144:ef7eb2e8f9f7 189 __I uint32_t RESERVED0[45];
<> 144:ef7eb2e8f9f7 190 __I uint32_t IDLE_CH; /*!< (@ 0x400040F4) Idle channel register. This register returns
<> 144:ef7eb2e8f9f7 191 the number of the first idle channel. */
<> 144:ef7eb2e8f9f7 192 __IO uint32_t IRQ_FLAG; /*!< (@ 0x400040F8) Global interrupt flag register */
<> 144:ef7eb2e8f9f7 193 } LPC_MRT_Type;
<> 144:ef7eb2e8f9f7 194
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 197 /* ================ WKT ================ */
<> 144:ef7eb2e8f9f7 198 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /**
<> 144:ef7eb2e8f9f7 202 * @brief Self wake-up timer (WKT) (WKT)
<> 144:ef7eb2e8f9f7 203 */
<> 144:ef7eb2e8f9f7 204
<> 144:ef7eb2e8f9f7 205 typedef struct { /*!< (@ 0x40008000) WKT Structure */
<> 144:ef7eb2e8f9f7 206 __IO uint32_t CTRL; /*!< (@ 0x40008000) Self wake-up timer control register. */
<> 144:ef7eb2e8f9f7 207 __I uint32_t RESERVED0[2];
<> 144:ef7eb2e8f9f7 208 __IO uint32_t COUNT; /*!< (@ 0x4000800C) Counter register. */
<> 144:ef7eb2e8f9f7 209 } LPC_WKT_Type;
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211
<> 144:ef7eb2e8f9f7 212 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 213 /* ================ SWM ================ */
<> 144:ef7eb2e8f9f7 214 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 /**
<> 144:ef7eb2e8f9f7 218 * @brief Switch matrix (SWM) (SWM)
<> 144:ef7eb2e8f9f7 219 */
<> 144:ef7eb2e8f9f7 220
<> 144:ef7eb2e8f9f7 221 typedef struct { /*!< (@ 0x4000C000) SWM Structure */
<> 144:ef7eb2e8f9f7 222 union {
<> 144:ef7eb2e8f9f7 223 __IO uint32_t PINASSIGN[12];
<> 144:ef7eb2e8f9f7 224 struct {
<> 144:ef7eb2e8f9f7 225 __IO uint32_t PINASSIGN0; /*!< (@ 0x4000C000) Pin assign register 0. Assign movable functions
<> 144:ef7eb2e8f9f7 226 U0_TXD, U0_RXD, U0_RTS, U0_CTS. */
<> 144:ef7eb2e8f9f7 227 __IO uint32_t PINASSIGN1; /*!< (@ 0x4000C004) Pin assign register 1. Assign movable functions
<> 144:ef7eb2e8f9f7 228 U0_SCLK, U1_TXD, U1_RXD, U1_RTS. */
<> 144:ef7eb2e8f9f7 229 __IO uint32_t PINASSIGN2; /*!< (@ 0x4000C008) Pin assign register 2. Assign movable functions
<> 144:ef7eb2e8f9f7 230 U1_CTS, U1_SCLK, U2_TXD, U2_RXD. */
<> 144:ef7eb2e8f9f7 231 __IO uint32_t PINASSIGN3; /*!< (@ 0x4000C00C) Pin assign register 3. Assign movable function
<> 144:ef7eb2e8f9f7 232 U2_RTS, U2_CTS, U2_SCLK, SPI0_SCK. */
<> 144:ef7eb2e8f9f7 233 __IO uint32_t PINASSIGN4; /*!< (@ 0x4000C010) Pin assign register 4. Assign movable functions
<> 144:ef7eb2e8f9f7 234 SPI0_MOSI, SPI0_MISO, SPI0_SSEL0, SPI0_SSEL1. */
<> 144:ef7eb2e8f9f7 235 __IO uint32_t PINASSIGN5; /*!< (@ 0x4000C014) Pin assign register 5. Assign movable functions
<> 144:ef7eb2e8f9f7 236 SPI0_SSEL2, SPI0_SSEL3, SPI1_SCK, SPI1_MOSI */
<> 144:ef7eb2e8f9f7 237 __IO uint32_t PINASSIGN6; /*!< (@ 0x4000C018) Pin assign register 6. Assign movable functions
<> 144:ef7eb2e8f9f7 238 SPI1_MISO, SPI1_SSEL0, SPI1_SSEL1, SCT0_IN0. */
<> 144:ef7eb2e8f9f7 239 __IO uint32_t PINASSIGN7; /*!< (@ 0x4000C01C) Pin assign register 7. Assign movable functions
<> 144:ef7eb2e8f9f7 240 SCT_IN1, SCT_IN2, SCT_IN3, SCT_OUT0. */
<> 144:ef7eb2e8f9f7 241 __IO uint32_t PINASSIGN8; /*!< (@ 0x4000C020) Pin assign register 8. Assign movable functions
<> 144:ef7eb2e8f9f7 242 SCT_OUT1, SCT_OUT2, SCT_OUT3, SCT_OUT4. */
<> 144:ef7eb2e8f9f7 243 __IO uint32_t PINASSIGN9; /*!< (@ 0x4000C024) Pin assign register 9. Assign movable functions
<> 144:ef7eb2e8f9f7 244 SCT_OUT5, I2C1_SDA, I2C1_SCL, I2C2_SDA. */
<> 144:ef7eb2e8f9f7 245 __IO uint32_t PINASSIGN10; /*!< (@ 0x4000C028) Pin assign register 10. Assign movable functions
<> 144:ef7eb2e8f9f7 246 I2C2_SCL, I2C3_SDA, I2C3_SCL, ADC_PINTRIG0. */
<> 144:ef7eb2e8f9f7 247 __IO uint32_t PINASSIGN11; /*!< (@ 0x4000C02C) Pin assign register 11. Assign movable functions
<> 144:ef7eb2e8f9f7 248 ADC_PINTRIG1, ACMP_O, CLKOUT, GPIO_INT_BMAT */
<> 144:ef7eb2e8f9f7 249 };
<> 144:ef7eb2e8f9f7 250 };
<> 144:ef7eb2e8f9f7 251 __I uint32_t RESERVED0[100];
<> 144:ef7eb2e8f9f7 252 __IO uint32_t PINENABLE0; /*!< (@ 0x4000C1C0) Pin enable register 0. Enables fixed-pin functions
<> 144:ef7eb2e8f9f7 253 ACMP_I0, ACMP_I1, SWCLK, SWDIO, XTALIN, XTALOUT, RESET, CLKIN,
<> 144:ef7eb2e8f9f7 254 VDDCMP. */
<> 144:ef7eb2e8f9f7 255 } LPC_SWM_Type;
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257
<> 144:ef7eb2e8f9f7 258 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 259 /* ================ ADC ================ */
<> 144:ef7eb2e8f9f7 260 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 261
<> 144:ef7eb2e8f9f7 262
<> 144:ef7eb2e8f9f7 263 /**
<> 144:ef7eb2e8f9f7 264 * @brief 12-bit Analog-to-Digital Converter (ADC) (ADC)
<> 144:ef7eb2e8f9f7 265 */
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 typedef struct { /*!< (@ 0x4001C000) ADC Structure */
<> 144:ef7eb2e8f9f7 268 __IO uint32_t CTRL; /*!< (@ 0x4001C000) A/D Control Register. Contains the clock divide
<> 144:ef7eb2e8f9f7 269 value, enable bits for each sequence and the A/D power-down
<> 144:ef7eb2e8f9f7 270 bit. */
<> 144:ef7eb2e8f9f7 271 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 272 __IO uint32_t SEQA_CTRL; /*!< (@ 0x4001C008) A/D Conversion Sequence-A control Register: Controls
<> 144:ef7eb2e8f9f7 273 triggering and channel selection for conversion sequence-A.
<> 144:ef7eb2e8f9f7 274 Also specifies interrupt mode for sequence-A. */
<> 144:ef7eb2e8f9f7 275 __IO uint32_t SEQB_CTRL; /*!< (@ 0x4001C00C) A/D Conversion Sequence-B Control Register: Controls
<> 144:ef7eb2e8f9f7 276 triggering and channel selection for conversion sequence-B.
<> 144:ef7eb2e8f9f7 277 Also specifies interrupt mode for sequence-B. */
<> 144:ef7eb2e8f9f7 278 __IO uint32_t SEQA_GDAT; /*!< (@ 0x4001C010) A/D Sequence-A Global Data Register. This register
<> 144:ef7eb2e8f9f7 279 contains the result of the most recent A/D conversion performed
<> 144:ef7eb2e8f9f7 280 under sequence-A */
<> 144:ef7eb2e8f9f7 281 __IO uint32_t SEQB_GDAT; /*!< (@ 0x4001C014) A/D Sequence-B Global Data Register. This register
<> 144:ef7eb2e8f9f7 282 contains the result of the most recent A/D conversion performed
<> 144:ef7eb2e8f9f7 283 under sequence-B */
<> 144:ef7eb2e8f9f7 284 __I uint32_t RESERVED1[2];
<> 144:ef7eb2e8f9f7 285 __I uint32_t DAT0; /*!< (@ 0x4001C020) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 286 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 287 0. */
<> 144:ef7eb2e8f9f7 288 __I uint32_t DAT1; /*!< (@ 0x4001C024) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 289 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 290 0. */
<> 144:ef7eb2e8f9f7 291 __I uint32_t DAT2; /*!< (@ 0x4001C028) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 292 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 293 0. */
<> 144:ef7eb2e8f9f7 294 __I uint32_t DAT3; /*!< (@ 0x4001C02C) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 295 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 296 0. */
<> 144:ef7eb2e8f9f7 297 __I uint32_t DAT4; /*!< (@ 0x4001C030) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 298 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 299 0. */
<> 144:ef7eb2e8f9f7 300 __I uint32_t DAT5; /*!< (@ 0x4001C034) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 301 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 302 0. */
<> 144:ef7eb2e8f9f7 303 __I uint32_t DAT6; /*!< (@ 0x4001C038) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 304 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 305 0. */
<> 144:ef7eb2e8f9f7 306 __I uint32_t DAT7; /*!< (@ 0x4001C03C) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 307 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 308 0. */
<> 144:ef7eb2e8f9f7 309 __I uint32_t DAT8; /*!< (@ 0x4001C040) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 310 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 311 0. */
<> 144:ef7eb2e8f9f7 312 __I uint32_t DAT9; /*!< (@ 0x4001C044) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 313 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 314 0. */
<> 144:ef7eb2e8f9f7 315 __I uint32_t DAT10; /*!< (@ 0x4001C048) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 316 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 317 0. */
<> 144:ef7eb2e8f9f7 318 __I uint32_t DAT11; /*!< (@ 0x4001C04C) A/D Channel 0 Data Register. This register contains
<> 144:ef7eb2e8f9f7 319 the result of the most recent conversion completed on channel
<> 144:ef7eb2e8f9f7 320 0. */
<> 144:ef7eb2e8f9f7 321 __IO uint32_t THR0_LOW; /*!< (@ 0x4001C050) A/D Low Compare Threshold Register 0 : Contains
<> 144:ef7eb2e8f9f7 322 the lower threshold level for automatic threshold comparison
<> 144:ef7eb2e8f9f7 323 for any channels linked to threshold pair 0. */
<> 144:ef7eb2e8f9f7 324 __IO uint32_t THR1_LOW; /*!< (@ 0x4001C054) A/D Low Compare Threshold Register 1: Contains
<> 144:ef7eb2e8f9f7 325 the lower threshold level for automatic threshold comparison
<> 144:ef7eb2e8f9f7 326 for any channels linked to threshold pair 1. */
<> 144:ef7eb2e8f9f7 327 __IO uint32_t THR0_HIGH; /*!< (@ 0x4001C058) A/D High Compare Threshold Register 0: Contains
<> 144:ef7eb2e8f9f7 328 the upper threshold level for automatic threshold comparison
<> 144:ef7eb2e8f9f7 329 for any channels linked to threshold pair 0. */
<> 144:ef7eb2e8f9f7 330 __IO uint32_t THR1_HIGH; /*!< (@ 0x4001C05C) A/D High Compare Threshold Register 1: Contains
<> 144:ef7eb2e8f9f7 331 the upper threshold level for automatic threshold comparison
<> 144:ef7eb2e8f9f7 332 for any channels linked to threshold pair 1. */
<> 144:ef7eb2e8f9f7 333 __IO uint32_t CHAN_THRSEL; /*!< (@ 0x4001C060) A/D Channel-Threshold Select Register. Specifies
<> 144:ef7eb2e8f9f7 334 which set of threshold compare registers are to be used for
<> 144:ef7eb2e8f9f7 335 each channel */
<> 144:ef7eb2e8f9f7 336 __IO uint32_t INTEN; /*!< (@ 0x4001C064) A/D Interrupt Enable Register. This register
<> 144:ef7eb2e8f9f7 337 contains enable bits that enable the sequence-A, sequence-B,
<> 144:ef7eb2e8f9f7 338 threshold compare and data overrun interrupts to be generated. */
<> 144:ef7eb2e8f9f7 339 __IO uint32_t FLAGS; /*!< (@ 0x4001C068) A/D Flags Register. Contains the four interrupt
<> 144:ef7eb2e8f9f7 340 request flags and the individual component overrun and threshold-compare
<> 144:ef7eb2e8f9f7 341 flags. (The overrun bits replicate information stored in the
<> 144:ef7eb2e8f9f7 342 result registers). */
<> 144:ef7eb2e8f9f7 343 __IO uint32_t TRM; /*!< (@ 0x4001C06C) ADC trim register. */
<> 144:ef7eb2e8f9f7 344 } LPC_ADC_Type;
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346
<> 144:ef7eb2e8f9f7 347 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 348 /* ================ PMU ================ */
<> 144:ef7eb2e8f9f7 349 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 350
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 /**
<> 144:ef7eb2e8f9f7 353 * @brief Power Management Unit (PMU) (PMU)
<> 144:ef7eb2e8f9f7 354 */
<> 144:ef7eb2e8f9f7 355
<> 144:ef7eb2e8f9f7 356 typedef struct { /*!< (@ 0x40020000) PMU Structure */
<> 144:ef7eb2e8f9f7 357 __IO uint32_t PCON; /*!< (@ 0x40020000) Power control register */
<> 144:ef7eb2e8f9f7 358 __IO uint32_t GPREG0; /*!< (@ 0x40020004) General purpose register 0 */
<> 144:ef7eb2e8f9f7 359 __IO uint32_t GPREG1; /*!< (@ 0x40020008) General purpose register 0 */
<> 144:ef7eb2e8f9f7 360 __IO uint32_t GPREG2; /*!< (@ 0x4002000C) General purpose register 0 */
<> 144:ef7eb2e8f9f7 361 __IO uint32_t GPREG3; /*!< (@ 0x40020010) General purpose register 0 */
<> 144:ef7eb2e8f9f7 362 __IO uint32_t DPDCTRL; /*!< (@ 0x40020014) Deep power-down control register. Also includes
<> 144:ef7eb2e8f9f7 363 bits for general purpose storage. */
<> 144:ef7eb2e8f9f7 364 } LPC_PMU_Type;
<> 144:ef7eb2e8f9f7 365
<> 144:ef7eb2e8f9f7 366
<> 144:ef7eb2e8f9f7 367 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 368 /* ================ CMP ================ */
<> 144:ef7eb2e8f9f7 369 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371
<> 144:ef7eb2e8f9f7 372 /**
<> 144:ef7eb2e8f9f7 373 * @brief Analog comparator (CMP)
<> 144:ef7eb2e8f9f7 374 */
<> 144:ef7eb2e8f9f7 375
<> 144:ef7eb2e8f9f7 376 typedef struct { /*!< (@ 0x40024000) CMP Structure */
<> 144:ef7eb2e8f9f7 377 __IO uint32_t CTRL; /*!< (@ 0x40024000) Comparator control register */
<> 144:ef7eb2e8f9f7 378 __IO uint32_t LAD; /*!< (@ 0x40024004) Voltage ladder register */
<> 144:ef7eb2e8f9f7 379 } LPC_CMP_Type;
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381
<> 144:ef7eb2e8f9f7 382 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 383 /* ================ DMATRIGMUX ================ */
<> 144:ef7eb2e8f9f7 384 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 385
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 /**
<> 144:ef7eb2e8f9f7 388 * @brief DMA trigger mux (DMATRIGMUX)
<> 144:ef7eb2e8f9f7 389 */
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 typedef struct { /*!< (@ 0x40028000) DMATRIGMUX Structure */
<> 144:ef7eb2e8f9f7 392 __IO uint32_t DMA_ITRIG_INMUX0; /*!< (@ 0x40028000) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 393 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 394 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 395 __IO uint32_t DMA_ITRIG_INMUX1; /*!< (@ 0x40028004) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 396 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 397 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 398 __IO uint32_t DMA_ITRIG_INMUX2; /*!< (@ 0x40028008) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 399 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 400 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 401 __IO uint32_t DMA_ITRIG_INMUX3; /*!< (@ 0x4002800C) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 402 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 403 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 404 __IO uint32_t DMA_ITRIG_INMUX4; /*!< (@ 0x40028010) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 405 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 406 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 407 __IO uint32_t DMA_ITRIG_INMUX5; /*!< (@ 0x40028014) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 408 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 409 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 410 __IO uint32_t DMA_ITRIG_INMUX6; /*!< (@ 0x40028018) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 411 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 412 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 413 __IO uint32_t DMA_ITRIG_INMUX7; /*!< (@ 0x4002801C) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 414 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 415 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 416 __IO uint32_t DMA_ITRIG_INMUX8; /*!< (@ 0x40028020) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 417 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 418 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 419 __IO uint32_t DMA_ITRIG_INMUX9; /*!< (@ 0x40028024) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 420 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 421 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 422 __IO uint32_t DMA_ITRIG_INMUX10; /*!< (@ 0x40028028) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 423 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 424 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 425 __IO uint32_t DMA_ITRIG_INMUX11; /*!< (@ 0x4002802C) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 426 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 427 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 428 __IO uint32_t DMA_ITRIG_INMUX12; /*!< (@ 0x40028030) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 429 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 430 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 431 __IO uint32_t DMA_ITRIG_INMUX13; /*!< (@ 0x40028034) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 432 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 433 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 434 __IO uint32_t DMA_ITRIG_INMUX14; /*!< (@ 0x40028038) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 435 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 436 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 437 __IO uint32_t DMA_ITRIG_INMUX15; /*!< (@ 0x4002803C) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 438 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 439 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 440 __IO uint32_t DMA_ITRIG_INMUX16; /*!< (@ 0x40028040) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 441 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 442 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 443 __IO uint32_t DMA_ITRIG_INMUX17; /*!< (@ 0x40028044) Input mux register for trigger inputs 0 to 23
<> 144:ef7eb2e8f9f7 444 connected to DMA channel 0. Selects from ADC, SCT, ACMP, pin
<> 144:ef7eb2e8f9f7 445 interrupts, and DMA requests. */
<> 144:ef7eb2e8f9f7 446 } LPC_DMATRIGMUX_Type;
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 450 /* ================ INPUTMUX ================ */
<> 144:ef7eb2e8f9f7 451 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 452
<> 144:ef7eb2e8f9f7 453
<> 144:ef7eb2e8f9f7 454 /**
<> 144:ef7eb2e8f9f7 455 * @brief Input multiplexing (INPUTMUX)
<> 144:ef7eb2e8f9f7 456 */
<> 144:ef7eb2e8f9f7 457
<> 144:ef7eb2e8f9f7 458 typedef struct { /*!< (@ 0x4002C000) INPUTMUX Structure */
<> 144:ef7eb2e8f9f7 459 __IO uint32_t DMA_INMUX_INMUX0; /*!< (@ 0x4002C000) Input mux register for DMA trigger input 20.
<> 144:ef7eb2e8f9f7 460 Selects from 18 DMA trigger outputs. */
<> 144:ef7eb2e8f9f7 461 __IO uint32_t DMA_INMUX_INMUX1; /*!< (@ 0x4002C004) Input mux register for DMA trigger input 20.
<> 144:ef7eb2e8f9f7 462 Selects from 18 DMA trigger outputs. */
<> 144:ef7eb2e8f9f7 463 __I uint32_t RESERVED0[6];
<> 144:ef7eb2e8f9f7 464 __IO uint32_t SCT0_INMUX0; /*!< (@ 0x4002C020) Input mux register for SCT input 0 */
<> 144:ef7eb2e8f9f7 465 __IO uint32_t SCT0_INMUX1; /*!< (@ 0x4002C024) Input mux register for SCT input 0 */
<> 144:ef7eb2e8f9f7 466 __IO uint32_t SCT0_INMUX2; /*!< (@ 0x4002C028) Input mux register for SCT input 0 */
<> 144:ef7eb2e8f9f7 467 __IO uint32_t SCT0_INMUX3; /*!< (@ 0x4002C02C) Input mux register for SCT input 0 */
<> 144:ef7eb2e8f9f7 468 } LPC_INPUTMUX_Type;
<> 144:ef7eb2e8f9f7 469
<> 144:ef7eb2e8f9f7 470
<> 144:ef7eb2e8f9f7 471 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 472 /* ================ FLASHCTRL ================ */
<> 144:ef7eb2e8f9f7 473 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 474
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 /**
<> 144:ef7eb2e8f9f7 477 * @brief Flash controller (FLASHCTRL)
<> 144:ef7eb2e8f9f7 478 */
<> 144:ef7eb2e8f9f7 479
<> 144:ef7eb2e8f9f7 480 typedef struct { /*!< (@ 0x40040000) FLASHCTRL Structure */
<> 144:ef7eb2e8f9f7 481 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 482 __IO uint32_t FLASHCFG; /*!< (@ 0x40040010) Flash configuration register */
<> 144:ef7eb2e8f9f7 483 __I uint32_t RESERVED1[3];
<> 144:ef7eb2e8f9f7 484 __IO uint32_t FMSSTART; /*!< (@ 0x40040020) Signature start address register */
<> 144:ef7eb2e8f9f7 485 __IO uint32_t FMSSTOP; /*!< (@ 0x40040024) Signature stop-address register */
<> 144:ef7eb2e8f9f7 486 __I uint32_t RESERVED2;
<> 144:ef7eb2e8f9f7 487 __I uint32_t FMSW0; /*!< (@ 0x4004002C) Signature Word */
<> 144:ef7eb2e8f9f7 488 } LPC_FLASHCTRL_Type;
<> 144:ef7eb2e8f9f7 489
<> 144:ef7eb2e8f9f7 490
<> 144:ef7eb2e8f9f7 491 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 492 /* ================ IOCON ================ */
<> 144:ef7eb2e8f9f7 493 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495
<> 144:ef7eb2e8f9f7 496 /**
<> 144:ef7eb2e8f9f7 497 * @brief I/O configuration (IOCON) (IOCON)
<> 144:ef7eb2e8f9f7 498 */
<> 144:ef7eb2e8f9f7 499
<> 144:ef7eb2e8f9f7 500 typedef struct { /*!< (@ 0x40044000) IOCON Structure */
<> 144:ef7eb2e8f9f7 501 __IO uint32_t PIO0_17; /*!< (@ 0x40044000) I/O configuration for pin PIO0_17 */
<> 144:ef7eb2e8f9f7 502 __IO uint32_t PIO0_13; /*!< (@ 0x40044004) I/O configuration for pin PIO0_13 */
<> 144:ef7eb2e8f9f7 503 __IO uint32_t PIO0_12; /*!< (@ 0x40044008) I/O configuration for pin PIO0_12 */
<> 144:ef7eb2e8f9f7 504 __IO uint32_t PIO0_5; /*!< (@ 0x4004400C) I/O configuration for pin PIO0_5/RESET */
<> 144:ef7eb2e8f9f7 505 __IO uint32_t PIO0_4; /*!< (@ 0x40044010) I/O configuration for pin PIO0_4 */
<> 144:ef7eb2e8f9f7 506 __IO uint32_t PIO0_3; /*!< (@ 0x40044014) I/O configuration for pin PIO0_3/SWCLK */
<> 144:ef7eb2e8f9f7 507 __IO uint32_t PIO0_2; /*!< (@ 0x40044018) I/O configuration for pin PIO0_2/SWDIO */
<> 144:ef7eb2e8f9f7 508 __IO uint32_t PIO0_11; /*!< (@ 0x4004401C) I/O configuration for pin PIO0_11. This is the
<> 144:ef7eb2e8f9f7 509 pin configuration for the true open-drain pin. */
<> 144:ef7eb2e8f9f7 510 __IO uint32_t PIO0_10; /*!< (@ 0x40044020) I/O configuration for pin PIO0_10. This is the
<> 144:ef7eb2e8f9f7 511 pin configuration for the true open-drain pin. */
<> 144:ef7eb2e8f9f7 512 __IO uint32_t PIO0_16; /*!< (@ 0x40044024) I/O configuration for pin PIO0_16 */
<> 144:ef7eb2e8f9f7 513 __IO uint32_t PIO0_15; /*!< (@ 0x40044028) I/O configuration for pin PIO0_15 */
<> 144:ef7eb2e8f9f7 514 __IO uint32_t PIO0_1; /*!< (@ 0x4004402C) I/O configuration for pin PIO0_17 */
<> 144:ef7eb2e8f9f7 515 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 516 __IO uint32_t PIO0_9; /*!< (@ 0x40044034) I/O configuration for pin PIO0_9/XTALOUT */
<> 144:ef7eb2e8f9f7 517 __IO uint32_t PIO0_8; /*!< (@ 0x40044038) I/O configuration for pin PIO0_8/XTALIN */
<> 144:ef7eb2e8f9f7 518 __IO uint32_t PIO0_7; /*!< (@ 0x4004403C) I/O configuration for pin PIO0_7 */
<> 144:ef7eb2e8f9f7 519 __IO uint32_t PIO0_6; /*!< (@ 0x40044040) I/O configuration for pin PIO0_6/VDDCMP */
<> 144:ef7eb2e8f9f7 520 __IO uint32_t PIO0_0; /*!< (@ 0x40044044) I/O configuration for pin PIO0_0/ACMP_I0 */
<> 144:ef7eb2e8f9f7 521 __IO uint32_t PIO0_14; /*!< (@ 0x40044048) I/O configuration for pin PIO0_14 */
<> 144:ef7eb2e8f9f7 522 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 523 __IO uint32_t PIO0_28; /*!< (@ 0x40044050) I/O configuration for pin PIO0_28 */
<> 144:ef7eb2e8f9f7 524 __IO uint32_t PIO0_27; /*!< (@ 0x40044054) I/O configuration for pin PIO0_27 */
<> 144:ef7eb2e8f9f7 525 __IO uint32_t PIO0_26; /*!< (@ 0x40044058) I/O configuration for pin PIO0_26 */
<> 144:ef7eb2e8f9f7 526 __IO uint32_t PIO0_25; /*!< (@ 0x4004405C) I/O configuration for pin PIO0_25 */
<> 144:ef7eb2e8f9f7 527 __IO uint32_t PIO0_24; /*!< (@ 0x40044060) I/O configuration for pin PIO0_24 */
<> 144:ef7eb2e8f9f7 528 __IO uint32_t PIO0_23; /*!< (@ 0x40044064) I/O configuration for pin PIO0_23/ADC_3 */
<> 144:ef7eb2e8f9f7 529 __IO uint32_t PIO0_22; /*!< (@ 0x40044068) I/O configuration for pin PIO0_22/ADC_4 */
<> 144:ef7eb2e8f9f7 530 __IO uint32_t PIO0_21; /*!< (@ 0x4004406C) I/O configuration for pin PIO0_21/ACMP_I4/ADC_5 */
<> 144:ef7eb2e8f9f7 531 __IO uint32_t PIO0_20; /*!< (@ 0x40044070) I/O configuration for pin PIO0_20/ADC_6 */
<> 144:ef7eb2e8f9f7 532 __IO uint32_t PIO0_19; /*!< (@ 0x40044074) I/O configuration for pin PIO0_19/ADC_7 */
<> 144:ef7eb2e8f9f7 533 __IO uint32_t PIO0_18; /*!< (@ 0x40044078) I/O configuration for pin PIO0_18/ADC_8 */
<> 144:ef7eb2e8f9f7 534 } LPC_IOCON_Type;
<> 144:ef7eb2e8f9f7 535
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 538 /* ================ SYSCON ================ */
<> 144:ef7eb2e8f9f7 539 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 540
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 /**
<> 144:ef7eb2e8f9f7 543 * @brief System configuration (SYSCON) (SYSCON)
<> 144:ef7eb2e8f9f7 544 */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 typedef struct { /*!< (@ 0x40048000) SYSCON Structure */
<> 144:ef7eb2e8f9f7 547 __IO uint32_t SYSMEMREMAP; /*!< (@ 0x40048000) System memory remap */
<> 144:ef7eb2e8f9f7 548 __IO uint32_t PRESETCTRL; /*!< (@ 0x40048004) Peripheral reset control */
<> 144:ef7eb2e8f9f7 549 __IO uint32_t SYSPLLCTRL; /*!< (@ 0x40048008) System PLL control */
<> 144:ef7eb2e8f9f7 550 __I uint32_t SYSPLLSTAT; /*!< (@ 0x4004800C) System PLL status */
<> 144:ef7eb2e8f9f7 551 __I uint32_t RESERVED0[4];
<> 144:ef7eb2e8f9f7 552 __IO uint32_t SYSOSCCTRL; /*!< (@ 0x40048020) System oscillator control */
<> 144:ef7eb2e8f9f7 553 __IO uint32_t WDTOSCCTRL; /*!< (@ 0x40048024) Watchdog oscillator control */
<> 144:ef7eb2e8f9f7 554 __IO uint32_t IRCCTRL; /*!< (@ 0x40048028) IRC control */
<> 144:ef7eb2e8f9f7 555 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 556 __IO uint32_t SYSRSTSTAT; /*!< (@ 0x40048030) System reset status register */
<> 144:ef7eb2e8f9f7 557 __I uint32_t RESERVED2[3];
<> 144:ef7eb2e8f9f7 558 __IO uint32_t SYSPLLCLKSEL; /*!< (@ 0x40048040) System PLL clock source select */
<> 144:ef7eb2e8f9f7 559 __IO uint32_t SYSPLLCLKUEN; /*!< (@ 0x40048044) System PLL clock source update enable */
<> 144:ef7eb2e8f9f7 560 __I uint32_t RESERVED3[10];
<> 144:ef7eb2e8f9f7 561 __IO uint32_t MAINCLKSEL; /*!< (@ 0x40048070) Main clock source select */
<> 144:ef7eb2e8f9f7 562 __IO uint32_t MAINCLKUEN; /*!< (@ 0x40048074) Main clock source update enable */
<> 144:ef7eb2e8f9f7 563 __IO uint32_t SYSAHBCLKDIV; /*!< (@ 0x40048078) System clock divider */
<> 144:ef7eb2e8f9f7 564 __I uint32_t RESERVED4;
<> 144:ef7eb2e8f9f7 565 __IO uint32_t SYSAHBCLKCTRL; /*!< (@ 0x40048080) System clock control */
<> 144:ef7eb2e8f9f7 566 __I uint32_t RESERVED5[4];
<> 144:ef7eb2e8f9f7 567 __IO uint32_t UARTCLKDIV; /*!< (@ 0x40048094) USART clock divider */
<> 144:ef7eb2e8f9f7 568 __I uint32_t RESERVED6[18];
<> 144:ef7eb2e8f9f7 569 __IO uint32_t CLKOUTSEL; /*!< (@ 0x400480E0) CLKOUT clock source select */
<> 144:ef7eb2e8f9f7 570 __IO uint32_t CLKOUTUEN; /*!< (@ 0x400480E4) CLKOUT clock source update enable */
<> 144:ef7eb2e8f9f7 571 __IO uint32_t CLKOUTDIV; /*!< (@ 0x400480E8) CLKOUT clock divider */
<> 144:ef7eb2e8f9f7 572 __I uint32_t RESERVED7;
<> 144:ef7eb2e8f9f7 573 __IO uint32_t UARTFRGDIV; /*!< (@ 0x400480F0) USART1 to USART4 common fractional generator
<> 144:ef7eb2e8f9f7 574 divider value */
<> 144:ef7eb2e8f9f7 575 __IO uint32_t UARTFRGMULT; /*!< (@ 0x400480F4) USART1 to USART4 common fractional generator
<> 144:ef7eb2e8f9f7 576 multiplier value */
<> 144:ef7eb2e8f9f7 577 __I uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 578 __IO uint32_t EXTTRACECMD; /*!< (@ 0x400480FC) External trace buffer command register */
<> 144:ef7eb2e8f9f7 579 __I uint32_t PIOPORCAP0; /*!< (@ 0x40048100) POR captured PIO status 0 */
<> 144:ef7eb2e8f9f7 580 __I uint32_t RESERVED9[12];
<> 144:ef7eb2e8f9f7 581 __IO uint32_t IOCONCLKDIV6; /*!< (@ 0x40048134) Peripheral clock 6 to the IOCON block for programmable
<> 144:ef7eb2e8f9f7 582 glitch filter */
<> 144:ef7eb2e8f9f7 583 __I uint32_t RESERVED10[6];
<> 144:ef7eb2e8f9f7 584 __IO uint32_t BODCTRL; /*!< (@ 0x40048150) Brown-Out Detect */
<> 144:ef7eb2e8f9f7 585 __IO uint32_t SYSTCKCAL; /*!< (@ 0x40048154) System tick counter calibration */
<> 144:ef7eb2e8f9f7 586 __I uint32_t RESERVED11[6];
<> 144:ef7eb2e8f9f7 587 __IO uint32_t IRQLATENCY; /*!< (@ 0x40048170) IQR delay. Allows trade-off between interrupt
<> 144:ef7eb2e8f9f7 588 latency and determinism. */
<> 144:ef7eb2e8f9f7 589 __IO uint32_t NMISRC; /*!< (@ 0x40048174) NMI Source Control */
<> 144:ef7eb2e8f9f7 590 union {
<> 144:ef7eb2e8f9f7 591 __IO uint32_t PINTSEL[8];
<> 144:ef7eb2e8f9f7 592 struct {
<> 144:ef7eb2e8f9f7 593 __IO uint32_t PINTSEL0; /*!< (@ 0x40048178) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 594 __IO uint32_t PINTSEL1; /*!< (@ 0x4004817C) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 595 __IO uint32_t PINTSEL2; /*!< (@ 0x40048180) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 596 __IO uint32_t PINTSEL3; /*!< (@ 0x40048184) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 597 __IO uint32_t PINTSEL4; /*!< (@ 0x40048188) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 598 __IO uint32_t PINTSEL5; /*!< (@ 0x4004818C) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 599 __IO uint32_t PINTSEL6; /*!< (@ 0x40048190) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 600 __IO uint32_t PINTSEL7; /*!< (@ 0x40048194) GPIO Pin Interrupt Select register 0 */
<> 144:ef7eb2e8f9f7 601 };
<> 144:ef7eb2e8f9f7 602 };
<> 144:ef7eb2e8f9f7 603 __I uint32_t RESERVED12[27];
<> 144:ef7eb2e8f9f7 604 __IO uint32_t STARTERP0; /*!< (@ 0x40048204) Start logic 0 pin wake-up enable register */
<> 144:ef7eb2e8f9f7 605 __I uint32_t RESERVED13[3];
<> 144:ef7eb2e8f9f7 606 __IO uint32_t STARTERP1; /*!< (@ 0x40048214) Start logic 1 interrupt wake-up enable register */
<> 144:ef7eb2e8f9f7 607 __I uint32_t RESERVED14[6];
<> 144:ef7eb2e8f9f7 608 __IO uint32_t PDSLEEPCFG; /*!< (@ 0x40048230) Power-down states in deep-sleep mode */
<> 144:ef7eb2e8f9f7 609 __IO uint32_t PDAWAKECFG; /*!< (@ 0x40048234) Power-down states for wake-up from deep-sleep */
<> 144:ef7eb2e8f9f7 610 __IO uint32_t PDRUNCFG; /*!< (@ 0x40048238) Power configuration register */
<> 144:ef7eb2e8f9f7 611 __I uint32_t RESERVED15[111];
<> 144:ef7eb2e8f9f7 612 __I uint32_t DEVICE_ID; /*!< (@ 0x400483F8) Device ID */
<> 144:ef7eb2e8f9f7 613 } LPC_SYSCON_Type;
<> 144:ef7eb2e8f9f7 614
<> 144:ef7eb2e8f9f7 615
<> 144:ef7eb2e8f9f7 616 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 617 /* ================ I2C0 ================ */
<> 144:ef7eb2e8f9f7 618 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /**
<> 144:ef7eb2e8f9f7 622 * @brief I2C0-bus interface (I2C0)
<> 144:ef7eb2e8f9f7 623 */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 typedef struct { /*!< (@ 0x40050000) I2C0 Structure */
<> 144:ef7eb2e8f9f7 626 __IO uint32_t CFG; /*!< (@ 0x40050000) Configuration for shared functions. */
<> 144:ef7eb2e8f9f7 627 __IO uint32_t STAT; /*!< (@ 0x40050004) Status register for Master, Slave, and Monitor
<> 144:ef7eb2e8f9f7 628 functions. */
<> 144:ef7eb2e8f9f7 629 __IO uint32_t INTENSET; /*!< (@ 0x40050008) Interrupt Enable Set and read register. */
<> 144:ef7eb2e8f9f7 630 __O uint32_t INTENCLR; /*!< (@ 0x4005000C) Interrupt Enable Clear register. */
<> 144:ef7eb2e8f9f7 631 __IO uint32_t TIMEOUT; /*!< (@ 0x40050010) Time-out value register. */
<> 144:ef7eb2e8f9f7 632 __IO uint32_t CLKDIV; /*!< (@ 0x40050014) Clock pre-divider for the entire I2C block. This
<> 144:ef7eb2e8f9f7 633 determines what time increments are used for the MSTTIME and
<> 144:ef7eb2e8f9f7 634 SLVTIME registers. */
<> 144:ef7eb2e8f9f7 635 __I uint32_t INTSTAT; /*!< (@ 0x40050018) Interrupt Status register for Master, Slave,
<> 144:ef7eb2e8f9f7 636 and Monitor functions. */
<> 144:ef7eb2e8f9f7 637 __I uint32_t RESERVED0;
<> 144:ef7eb2e8f9f7 638 __IO uint32_t MSTCTL; /*!< (@ 0x40050020) Master control register. */
<> 144:ef7eb2e8f9f7 639 __IO uint32_t MSTTIME; /*!< (@ 0x40050024) Master timing configuration. */
<> 144:ef7eb2e8f9f7 640 __IO uint32_t MSTDAT; /*!< (@ 0x40050028) Combined Master receiver and transmitter data
<> 144:ef7eb2e8f9f7 641 register. */
<> 144:ef7eb2e8f9f7 642 __I uint32_t RESERVED1[5];
<> 144:ef7eb2e8f9f7 643 __IO uint32_t SLVCTL; /*!< (@ 0x40050040) Slave control register. */
<> 144:ef7eb2e8f9f7 644 __IO uint32_t SLVDAT; /*!< (@ 0x40050044) Combined Slave receiver and transmitter data
<> 144:ef7eb2e8f9f7 645 register. */
<> 144:ef7eb2e8f9f7 646 union {
<> 144:ef7eb2e8f9f7 647 __IO uint32_t SLVADR[4];
<> 144:ef7eb2e8f9f7 648 struct {
<> 144:ef7eb2e8f9f7 649 __IO uint32_t SLVADR0; /*!< (@ 0x40050048) Slave address 0. */
<> 144:ef7eb2e8f9f7 650 __IO uint32_t SLVADR1; /*!< (@ 0x4005004C) Slave address 0. */
<> 144:ef7eb2e8f9f7 651 __IO uint32_t SLVADR2; /*!< (@ 0x40050050) Slave address 0. */
<> 144:ef7eb2e8f9f7 652 __IO uint32_t SLVADR3; /*!< (@ 0x40050054) Slave address 0. */
<> 144:ef7eb2e8f9f7 653 };
<> 144:ef7eb2e8f9f7 654 };
<> 144:ef7eb2e8f9f7 655 __IO uint32_t SLVQUAL0; /*!< (@ 0x40050058) Slave Qualification for address 0. */
<> 144:ef7eb2e8f9f7 656 __I uint32_t RESERVED2[9];
<> 144:ef7eb2e8f9f7 657 __I uint32_t MONRXDAT; /*!< (@ 0x40050080) Monitor receiver data register. */
<> 144:ef7eb2e8f9f7 658 } LPC_I2C0_Type;
<> 144:ef7eb2e8f9f7 659
<> 144:ef7eb2e8f9f7 660
<> 144:ef7eb2e8f9f7 661 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 662 /* ================ SPI0 ================ */
<> 144:ef7eb2e8f9f7 663 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 664
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666 /**
<> 144:ef7eb2e8f9f7 667 * @brief SPI0 (SPI0)
<> 144:ef7eb2e8f9f7 668 */
<> 144:ef7eb2e8f9f7 669
<> 144:ef7eb2e8f9f7 670 typedef struct { /*!< (@ 0x40058000) SPI0 Structure */
<> 144:ef7eb2e8f9f7 671 __IO uint32_t CFG; /*!< (@ 0x40058000) SPI Configuration register */
<> 144:ef7eb2e8f9f7 672 __IO uint32_t DLY; /*!< (@ 0x40058004) SPI Delay register */
<> 144:ef7eb2e8f9f7 673 __IO uint32_t STAT; /*!< (@ 0x40058008) SPI Status. Some status flags can be cleared
<> 144:ef7eb2e8f9f7 674 by writing a 1 to that bit position */
<> 144:ef7eb2e8f9f7 675 __IO uint32_t INTENSET; /*!< (@ 0x4005800C) SPI Interrupt Enable read and Set. A complete
<> 144:ef7eb2e8f9f7 676 value may be read from this register. Writing a 1 to any implemented
<> 144:ef7eb2e8f9f7 677 bit position causes that bit to be set. */
<> 144:ef7eb2e8f9f7 678 __O uint32_t INTENCLR; /*!< (@ 0x40058010) SPI Interrupt Enable Clear. Writing a 1 to any
<> 144:ef7eb2e8f9f7 679 implemented bit position causes the corresponding bit in INTENSET
<> 144:ef7eb2e8f9f7 680 to be cleared. */
<> 144:ef7eb2e8f9f7 681 __I uint32_t RXDAT; /*!< (@ 0x40058014) SPI Receive Data */
<> 144:ef7eb2e8f9f7 682 __IO uint32_t TXDATCTL; /*!< (@ 0x40058018) SPI Transmit Data with Control */
<> 144:ef7eb2e8f9f7 683 __IO uint32_t TXDAT; /*!< (@ 0x4005801C) SPI Transmit Data */
<> 144:ef7eb2e8f9f7 684 __IO uint32_t TXCTL; /*!< (@ 0x40058020) SPI Transmit Control */
<> 144:ef7eb2e8f9f7 685 __IO uint32_t DIV; /*!< (@ 0x40058024) SPI clock Divider */
<> 144:ef7eb2e8f9f7 686 __I uint32_t INTSTAT; /*!< (@ 0x40058028) SPI Interrupt Status */
<> 144:ef7eb2e8f9f7 687 } LPC_SPI0_Type;
<> 144:ef7eb2e8f9f7 688
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 691 /* ================ USART0 ================ */
<> 144:ef7eb2e8f9f7 692 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694
<> 144:ef7eb2e8f9f7 695 /**
<> 144:ef7eb2e8f9f7 696 * @brief USART0 (USART0)
<> 144:ef7eb2e8f9f7 697 */
<> 144:ef7eb2e8f9f7 698
<> 144:ef7eb2e8f9f7 699 typedef struct { /*!< (@ 0x40064000) USART0 Structure */
<> 144:ef7eb2e8f9f7 700 __IO uint32_t CFG; /*!< (@ 0x40064000) USART Configuration register. Basic USART configuration
<> 144:ef7eb2e8f9f7 701 settings that typically are not changed during operation. */
<> 144:ef7eb2e8f9f7 702 __IO uint32_t CTL; /*!< (@ 0x40064004) USART Control register. USART control settings
<> 144:ef7eb2e8f9f7 703 that are more likely to change during operation. */
<> 144:ef7eb2e8f9f7 704 __IO uint32_t STAT; /*!< (@ 0x40064008) USART Status register. The complete status value
<> 144:ef7eb2e8f9f7 705 can be read here. Writing ones clears some bits in the register.
<> 144:ef7eb2e8f9f7 706 Some bits can be cleared by writing a 1 to them. */
<> 144:ef7eb2e8f9f7 707 __IO uint32_t INTENSET; /*!< (@ 0x4006400C) Interrupt Enable read and Set register. Contains
<> 144:ef7eb2e8f9f7 708 an individual interrupt enable bit for each potential USART
<> 144:ef7eb2e8f9f7 709 interrupt. A complete value may be read from this register.
<> 144:ef7eb2e8f9f7 710 Writing a 1 to any implemented bit position causes that bit
<> 144:ef7eb2e8f9f7 711 to be set. */
<> 144:ef7eb2e8f9f7 712 __O uint32_t INTENCLR; /*!< (@ 0x40064010) Interrupt Enable Clear register. Allows clearing
<> 144:ef7eb2e8f9f7 713 any combination of bits in the INTENSET register. Writing a
<> 144:ef7eb2e8f9f7 714 1 to any implemented bit position causes the corresponding bit
<> 144:ef7eb2e8f9f7 715 to be cleared. */
<> 144:ef7eb2e8f9f7 716 __I uint32_t RXDAT; /*!< (@ 0x40064014) Receiver Data register. Contains the last character
<> 144:ef7eb2e8f9f7 717 received. */
<> 144:ef7eb2e8f9f7 718 __I uint32_t RXDATSTAT; /*!< (@ 0x40064018) Receiver Data with Status register. Combines
<> 144:ef7eb2e8f9f7 719 the last character received with the current USART receive status.
<> 144:ef7eb2e8f9f7 720 Allows DMA or software to recover incoming data and status together. */
<> 144:ef7eb2e8f9f7 721 __IO uint32_t TXDAT; /*!< (@ 0x4006401C) Transmit Data register. Data to be transmitted
<> 144:ef7eb2e8f9f7 722 is written here. */
<> 144:ef7eb2e8f9f7 723 __IO uint32_t BRG; /*!< (@ 0x40064020) Baud Rate Generator register. 16-bit integer
<> 144:ef7eb2e8f9f7 724 baud rate divisor value. */
<> 144:ef7eb2e8f9f7 725 __I uint32_t INTSTAT; /*!< (@ 0x40064024) Interrupt status register. Reflects interrupts
<> 144:ef7eb2e8f9f7 726 that are currently enabled. */
<> 144:ef7eb2e8f9f7 727 __IO uint32_t OSR; /*!< (@ 0x40064028) Oversample selection register for asynchronous
<> 144:ef7eb2e8f9f7 728 communication. */
<> 144:ef7eb2e8f9f7 729 __IO uint32_t ADDR; /*!< (@ 0x4006402C) Address register for automatic address matching. */
<> 144:ef7eb2e8f9f7 730 } LPC_USART0_Type;
<> 144:ef7eb2e8f9f7 731
<> 144:ef7eb2e8f9f7 732
<> 144:ef7eb2e8f9f7 733 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 734 /* ================ CRC ================ */
<> 144:ef7eb2e8f9f7 735 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737
<> 144:ef7eb2e8f9f7 738 /**
<> 144:ef7eb2e8f9f7 739 * @brief Cyclic Redundancy Check (CRC) engine (CRC)
<> 144:ef7eb2e8f9f7 740 */
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 typedef struct { /*!< (@ 0x50000000) CRC Structure */
<> 144:ef7eb2e8f9f7 743 __IO uint32_t MODE; /*!< (@ 0x50000000) CRC mode register */
<> 144:ef7eb2e8f9f7 744 __IO uint32_t SEED; /*!< (@ 0x50000004) CRC seed register */
<> 144:ef7eb2e8f9f7 745
<> 144:ef7eb2e8f9f7 746 union {
<> 144:ef7eb2e8f9f7 747 __O uint32_t WR_DATA; /*!< (@ 0x50000008) CRC data register */
<> 144:ef7eb2e8f9f7 748 __I uint32_t SUM; /*!< (@ 0x50000008) CRC checksum register */
<> 144:ef7eb2e8f9f7 749 };
<> 144:ef7eb2e8f9f7 750 } LPC_CRC_Type;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752
<> 144:ef7eb2e8f9f7 753 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 754 /* ================ SCT ================ */
<> 144:ef7eb2e8f9f7 755 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 756
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /**
<> 144:ef7eb2e8f9f7 759 * @brief State Configurable Timer (SCT) (SCT)
<> 144:ef7eb2e8f9f7 760 */
<> 144:ef7eb2e8f9f7 761
<> 144:ef7eb2e8f9f7 762 typedef struct { /*!< (@ 0x50004000) SCT Structure */
<> 144:ef7eb2e8f9f7 763 __IO uint32_t CONFIG; /*!< (@ 0x50004000) SCT configuration register */
<> 144:ef7eb2e8f9f7 764 __IO uint32_t CTRL; /*!< (@ 0x50004004) SCT control register */
<> 144:ef7eb2e8f9f7 765 __IO uint32_t LIMIT; /*!< (@ 0x50004008) SCT limit register */
<> 144:ef7eb2e8f9f7 766 __IO uint32_t HALT; /*!< (@ 0x5000400C) SCT halt condition register */
<> 144:ef7eb2e8f9f7 767 __IO uint32_t STOP; /*!< (@ 0x50004010) SCT stop condition register */
<> 144:ef7eb2e8f9f7 768 __IO uint32_t START; /*!< (@ 0x50004014) SCT start condition register */
<> 144:ef7eb2e8f9f7 769 __I uint32_t RESERVED0[10];
<> 144:ef7eb2e8f9f7 770 __IO uint32_t COUNT; /*!< (@ 0x50004040) SCT counter register */
<> 144:ef7eb2e8f9f7 771 __IO uint32_t STATE; /*!< (@ 0x50004044) SCT state register */
<> 144:ef7eb2e8f9f7 772 __I uint32_t INPUT; /*!< (@ 0x50004048) SCT input register */
<> 144:ef7eb2e8f9f7 773 __IO uint32_t REGMODE; /*!< (@ 0x5000404C) SCT match/capture registers mode register */
<> 144:ef7eb2e8f9f7 774 __IO uint32_t OUTPUT; /*!< (@ 0x50004050) SCT output register */
<> 144:ef7eb2e8f9f7 775 __IO uint32_t OUTPUTDIRCTRL; /*!< (@ 0x50004054) SCT output counter direction control register */
<> 144:ef7eb2e8f9f7 776 __IO uint32_t RES; /*!< (@ 0x50004058) SCT conflict resolution register */
<> 144:ef7eb2e8f9f7 777 __IO uint32_t DMAREQ0; /*!< (@ 0x5000405C) SCT DMA request 0 register */
<> 144:ef7eb2e8f9f7 778 __IO uint32_t DMAREQ1; /*!< (@ 0x50004060) SCT DMA request 1 register */
<> 144:ef7eb2e8f9f7 779 __I uint32_t RESERVED1[35];
<> 144:ef7eb2e8f9f7 780 __IO uint32_t EVEN; /*!< (@ 0x500040F0) SCT event enable register */
<> 144:ef7eb2e8f9f7 781 __IO uint32_t EVFLAG; /*!< (@ 0x500040F4) SCT event flag register */
<> 144:ef7eb2e8f9f7 782 __IO uint32_t CONEN; /*!< (@ 0x500040F8) SCT conflict enable register */
<> 144:ef7eb2e8f9f7 783 __IO uint32_t CONFLAG; /*!< (@ 0x500040FC) SCT conflict flag register */
<> 144:ef7eb2e8f9f7 784
<> 144:ef7eb2e8f9f7 785 union {
<> 144:ef7eb2e8f9f7 786 union {
<> 144:ef7eb2e8f9f7 787 __IO uint32_t CAP0; /*!< (@ 0x50004100) SCT capture register of capture channel 0 to
<> 144:ef7eb2e8f9f7 788 7; REGMOD0 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 789 __IO uint32_t MATCH0; /*!< (@ 0x50004100) SCT match value register of match channels 0
<> 144:ef7eb2e8f9f7 790 to 7; REGMOD0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 791 };
<> 144:ef7eb2e8f9f7 792
<> 144:ef7eb2e8f9f7 793 union {
<> 144:ef7eb2e8f9f7 794 __IO uint32_t CAP1; /*!< (@ 0x50004104) SCT capture register of capture channel 0 to
<> 144:ef7eb2e8f9f7 795 7; REGMOD0 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 796 __IO uint32_t MATCH1; /*!< (@ 0x50004104) SCT match value register of match channels 0
<> 144:ef7eb2e8f9f7 797 to 7; REGMOD0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 798 };
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 union {
<> 144:ef7eb2e8f9f7 801 __IO uint32_t CAP2; /*!< (@ 0x50004108) SCT capture register of capture channel 0 to
<> 144:ef7eb2e8f9f7 802 7; REGMOD0 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 803 __IO uint32_t MATCH2; /*!< (@ 0x50004108) SCT match value register of match channels 0
<> 144:ef7eb2e8f9f7 804 to 7; REGMOD0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 805 };
<> 144:ef7eb2e8f9f7 806
<> 144:ef7eb2e8f9f7 807 union {
<> 144:ef7eb2e8f9f7 808 __IO uint32_t MATCH3; /*!< (@ 0x5000410C) SCT match value register of match channels 0
<> 144:ef7eb2e8f9f7 809 to 7; REGMOD0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 810 __IO uint32_t CAP3; /*!< (@ 0x5000410C) SCT capture register of capture channel 0 to
<> 144:ef7eb2e8f9f7 811 7; REGMOD0 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 812 };
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 union {
<> 144:ef7eb2e8f9f7 815 __IO uint32_t CAP4; /*!< (@ 0x50004110) SCT capture register of capture channel 0 to
<> 144:ef7eb2e8f9f7 816 7; REGMOD0 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 817 __IO uint32_t MATCH4; /*!< (@ 0x50004110) SCT match value register of match channels 0
<> 144:ef7eb2e8f9f7 818 to 7; REGMOD0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 819 };
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 union {
<> 144:ef7eb2e8f9f7 822 __IO uint32_t MATCH5; /*!< (@ 0x50004114) SCT match value register of match channels 0
<> 144:ef7eb2e8f9f7 823 to 7; REGMOD0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 824 __IO uint32_t CAP5; /*!< (@ 0x50004114) SCT capture register of capture channel 0 to
<> 144:ef7eb2e8f9f7 825 7; REGMOD0 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 826 };
<> 144:ef7eb2e8f9f7 827
<> 144:ef7eb2e8f9f7 828 union {
<> 144:ef7eb2e8f9f7 829 __IO uint32_t CAP6; /*!< (@ 0x50004118) SCT capture register of capture channel 0 to
<> 144:ef7eb2e8f9f7 830 7; REGMOD0 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 831 __IO uint32_t MATCH6; /*!< (@ 0x50004118) SCT match value register of match channels 0
<> 144:ef7eb2e8f9f7 832 to 7; REGMOD0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 833 };
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 union {
<> 144:ef7eb2e8f9f7 836 __IO uint32_t CAP7; /*!< (@ 0x5000411C) SCT capture register of capture channel 0 to
<> 144:ef7eb2e8f9f7 837 7; REGMOD0 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 838 __IO uint32_t MATCH7; /*!< (@ 0x5000411C) SCT match value register of match channels 0
<> 144:ef7eb2e8f9f7 839 to 7; REGMOD0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 840 };
<> 144:ef7eb2e8f9f7 841 __IO uint32_t CAP[8];
<> 144:ef7eb2e8f9f7 842 __IO uint32_t MATCH[8];
<> 144:ef7eb2e8f9f7 843 };
<> 144:ef7eb2e8f9f7 844 __I uint32_t RESERVED2[56];
<> 144:ef7eb2e8f9f7 845
<> 144:ef7eb2e8f9f7 846 union {
<> 144:ef7eb2e8f9f7 847 struct {
<> 144:ef7eb2e8f9f7 848 union {
<> 144:ef7eb2e8f9f7 849 __IO uint32_t CAPCTRL0; /*!< (@ 0x50004200) SCT capture control register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 850 = 1 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 851 __IO uint32_t MATCHREL0; /*!< (@ 0x50004200) SCT match reload value register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 852 = 0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 853 };
<> 144:ef7eb2e8f9f7 854
<> 144:ef7eb2e8f9f7 855 union {
<> 144:ef7eb2e8f9f7 856 __IO uint32_t CAPCTRL1; /*!< (@ 0x50004204) SCT capture control register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 857 = 1 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 858 __IO uint32_t MATCHREL1; /*!< (@ 0x50004204) SCT match reload value register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 859 = 0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 860 };
<> 144:ef7eb2e8f9f7 861
<> 144:ef7eb2e8f9f7 862 union {
<> 144:ef7eb2e8f9f7 863 __IO uint32_t CAPCTRL2; /*!< (@ 0x50004208) SCT capture control register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 864 = 1 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 865 __IO uint32_t MATCHREL2; /*!< (@ 0x50004208) SCT match reload value register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 866 = 0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 867 };
<> 144:ef7eb2e8f9f7 868
<> 144:ef7eb2e8f9f7 869 union {
<> 144:ef7eb2e8f9f7 870 __IO uint32_t MATCHREL3; /*!< (@ 0x5000420C) SCT match reload value register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 871 = 0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 872 __IO uint32_t CAPCTRL3; /*!< (@ 0x5000420C) SCT capture control register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 873 = 1 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 874 };
<> 144:ef7eb2e8f9f7 875
<> 144:ef7eb2e8f9f7 876 union {
<> 144:ef7eb2e8f9f7 877 __IO uint32_t CAPCTRL4; /*!< (@ 0x50004210) SCT capture control register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 878 = 1 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 879 __IO uint32_t MATCHREL4; /*!< (@ 0x50004210) SCT match reload value register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 880 = 0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 881 };
<> 144:ef7eb2e8f9f7 882
<> 144:ef7eb2e8f9f7 883 union {
<> 144:ef7eb2e8f9f7 884 __IO uint32_t CAPCTRL5; /*!< (@ 0x50004214) SCT capture control register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 885 = 1 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 886 __IO uint32_t MATCHREL5; /*!< (@ 0x50004214) SCT match reload value register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 887 = 0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 888 };
<> 144:ef7eb2e8f9f7 889
<> 144:ef7eb2e8f9f7 890 union {
<> 144:ef7eb2e8f9f7 891 __IO uint32_t CAPCTRL6; /*!< (@ 0x50004218) SCT capture control register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 892 = 1 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 893 __IO uint32_t MATCHREL6; /*!< (@ 0x50004218) SCT match reload value register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 894 = 0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 895 };
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 union {
<> 144:ef7eb2e8f9f7 898 __IO uint32_t CAPCTRL7; /*!< (@ 0x5000421C) SCT capture control register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 899 = 1 to REGMODE7 = 1 */
<> 144:ef7eb2e8f9f7 900 __IO uint32_t MATCHREL7; /*!< (@ 0x5000421C) SCT match reload value register 0 to 7; REGMOD0
<> 144:ef7eb2e8f9f7 901 = 0 to REGMODE7 = 0 */
<> 144:ef7eb2e8f9f7 902 };
<> 144:ef7eb2e8f9f7 903 };
<> 144:ef7eb2e8f9f7 904 __IO uint32_t MATCHREL[8];
<> 144:ef7eb2e8f9f7 905 };
<> 144:ef7eb2e8f9f7 906 __I uint32_t RESERVED3[56];
<> 144:ef7eb2e8f9f7 907
<> 144:ef7eb2e8f9f7 908 union {
<> 144:ef7eb2e8f9f7 909 struct {
<> 144:ef7eb2e8f9f7 910 __IO uint32_t EV0_STATE; /*!< (@ 0x50004300) SCT event state register 0 */
<> 144:ef7eb2e8f9f7 911 __IO uint32_t EV0_CTRL; /*!< (@ 0x50004304) SCT event control register 0 */
<> 144:ef7eb2e8f9f7 912 __IO uint32_t EV1_STATE; /*!< (@ 0x50004308) SCT event state register 0 */
<> 144:ef7eb2e8f9f7 913 __IO uint32_t EV1_CTRL; /*!< (@ 0x5000430C) SCT event control register 0 */
<> 144:ef7eb2e8f9f7 914 __IO uint32_t EV2_STATE; /*!< (@ 0x50004310) SCT event state register 0 */
<> 144:ef7eb2e8f9f7 915 __IO uint32_t EV2_CTRL; /*!< (@ 0x50004314) SCT event control register 0 */
<> 144:ef7eb2e8f9f7 916 __IO uint32_t EV3_STATE; /*!< (@ 0x50004318) SCT event state register 0 */
<> 144:ef7eb2e8f9f7 917 __IO uint32_t EV3_CTRL; /*!< (@ 0x5000431C) SCT event control register 0 */
<> 144:ef7eb2e8f9f7 918 __IO uint32_t EV4_STATE; /*!< (@ 0x50004320) SCT event state register 0 */
<> 144:ef7eb2e8f9f7 919 __IO uint32_t EV4_CTRL; /*!< (@ 0x50004324) SCT event control register 0 */
<> 144:ef7eb2e8f9f7 920 __IO uint32_t EV5_STATE; /*!< (@ 0x50004328) SCT event state register 0 */
<> 144:ef7eb2e8f9f7 921 __IO uint32_t EV5_CTRL; /*!< (@ 0x5000432C) SCT event control register 0 */
<> 144:ef7eb2e8f9f7 922 __IO uint32_t EV6_STATE; /*!< (@ 0x50004330) SCT event state register 0 */
<> 144:ef7eb2e8f9f7 923 __IO uint32_t EV6_CTRL; /*!< (@ 0x50004334) SCT event control register 0 */
<> 144:ef7eb2e8f9f7 924 __IO uint32_t EV7_STATE; /*!< (@ 0x50004338) SCT event state register 0 */
<> 144:ef7eb2e8f9f7 925 __IO uint32_t EV7_CTRL; /*!< (@ 0x5000433C) SCT event control register 0 */
<> 144:ef7eb2e8f9f7 926 };
<> 144:ef7eb2e8f9f7 927 __IO struct {
<> 144:ef7eb2e8f9f7 928 uint32_t STATE;
<> 144:ef7eb2e8f9f7 929 uint32_t CTRL;
<> 144:ef7eb2e8f9f7 930 } EVENT[8];
<> 144:ef7eb2e8f9f7 931 };
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 __I uint32_t RESERVED4[112];
<> 144:ef7eb2e8f9f7 934
<> 144:ef7eb2e8f9f7 935 union {
<> 144:ef7eb2e8f9f7 936 struct {
<> 144:ef7eb2e8f9f7 937 __IO uint32_t OUT0_SET; /*!< (@ 0x50004500) SCT output 0 set register */
<> 144:ef7eb2e8f9f7 938 __IO uint32_t OUT0_CLR; /*!< (@ 0x50004504) SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 939 __IO uint32_t OUT1_SET; /*!< (@ 0x50004508) SCT output 0 set register */
<> 144:ef7eb2e8f9f7 940 __IO uint32_t OUT1_CLR; /*!< (@ 0x5000450C) SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 941 __IO uint32_t OUT2_SET; /*!< (@ 0x50004510) SCT output 0 set register */
<> 144:ef7eb2e8f9f7 942 __IO uint32_t OUT2_CLR; /*!< (@ 0x50004514) SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 943 __IO uint32_t OUT3_SET; /*!< (@ 0x50004518) SCT output 0 set register */
<> 144:ef7eb2e8f9f7 944 __IO uint32_t OUT3_CLR; /*!< (@ 0x5000451C) SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 945 __IO uint32_t OUT4_SET; /*!< (@ 0x50004520) SCT output 0 set register */
<> 144:ef7eb2e8f9f7 946 __IO uint32_t OUT4_CLR; /*!< (@ 0x50004524) SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 947 __IO uint32_t OUT5_SET; /*!< (@ 0x50004528) SCT output 0 set register */
<> 144:ef7eb2e8f9f7 948 __IO uint32_t OUT5_CLR; /*!< (@ 0x5000452C) SCT output 0 clear register */
<> 144:ef7eb2e8f9f7 949 };
<> 144:ef7eb2e8f9f7 950 __IO struct {
<> 144:ef7eb2e8f9f7 951 uint32_t SET;
<> 144:ef7eb2e8f9f7 952 uint32_t CLR;
<> 144:ef7eb2e8f9f7 953 } OUT[6];
<> 144:ef7eb2e8f9f7 954 };
<> 144:ef7eb2e8f9f7 955
<> 144:ef7eb2e8f9f7 956 } LPC_SCT_Type;
<> 144:ef7eb2e8f9f7 957
<> 144:ef7eb2e8f9f7 958
<> 144:ef7eb2e8f9f7 959 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 960 /* ================ DMA ================ */
<> 144:ef7eb2e8f9f7 961 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 962
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /**
<> 144:ef7eb2e8f9f7 965 * @brief DMA controller (DMA)
<> 144:ef7eb2e8f9f7 966 */
<> 144:ef7eb2e8f9f7 967
<> 144:ef7eb2e8f9f7 968 typedef struct { /*!< (@ 0x50008000) DMA Structure */
<> 144:ef7eb2e8f9f7 969 __IO uint32_t CTRL; /*!< (@ 0x50008000) DMA control. */
<> 144:ef7eb2e8f9f7 970 __I uint32_t INTSTAT; /*!< (@ 0x50008004) Interrupt status. */
<> 144:ef7eb2e8f9f7 971 __IO uint32_t SRAMBASE; /*!< (@ 0x50008008) SRAM address of the channel configuration table. */
<> 144:ef7eb2e8f9f7 972 __I uint32_t RESERVED0[5];
<> 144:ef7eb2e8f9f7 973 __IO uint32_t ENABLESET0; /*!< (@ 0x50008020) Channel Enable read and Set for all DMA channels. */
<> 144:ef7eb2e8f9f7 974 __I uint32_t RESERVED1;
<> 144:ef7eb2e8f9f7 975 __O uint32_t ENABLECLR0; /*!< (@ 0x50008028) Channel Enable Clear for all DMA channels. */
<> 144:ef7eb2e8f9f7 976 __I uint32_t RESERVED2;
<> 144:ef7eb2e8f9f7 977 __I uint32_t ACTIVE0; /*!< (@ 0x50008030) Channel Active status for all DMA channels. */
<> 144:ef7eb2e8f9f7 978 __I uint32_t RESERVED3;
<> 144:ef7eb2e8f9f7 979 __I uint32_t BUSY0; /*!< (@ 0x50008038) Channel Busy status for all DMA channels. */
<> 144:ef7eb2e8f9f7 980 __I uint32_t RESERVED4;
<> 144:ef7eb2e8f9f7 981 __IO uint32_t ERRINT0; /*!< (@ 0x50008040) Error Interrupt status for all DMA channels. */
<> 144:ef7eb2e8f9f7 982 __I uint32_t RESERVED5;
<> 144:ef7eb2e8f9f7 983 __IO uint32_t INTENSET0; /*!< (@ 0x50008048) Interrupt Enable read and Set for all DMA channels. */
<> 144:ef7eb2e8f9f7 984 __I uint32_t RESERVED6;
<> 144:ef7eb2e8f9f7 985 __O uint32_t INTENCLR0; /*!< (@ 0x50008050) Interrupt Enable Clear for all DMA channels. */
<> 144:ef7eb2e8f9f7 986 __I uint32_t RESERVED7;
<> 144:ef7eb2e8f9f7 987 __IO uint32_t INTA0; /*!< (@ 0x50008058) Interrupt A status for all DMA channels. */
<> 144:ef7eb2e8f9f7 988 __I uint32_t RESERVED8;
<> 144:ef7eb2e8f9f7 989 __IO uint32_t INTB0; /*!< (@ 0x50008060) Interrupt B status for all DMA channels. */
<> 144:ef7eb2e8f9f7 990 __I uint32_t RESERVED9;
<> 144:ef7eb2e8f9f7 991 __O uint32_t SETVALID0; /*!< (@ 0x50008068) Set ValidPending control bits for all DMA channels. */
<> 144:ef7eb2e8f9f7 992 __I uint32_t RESERVED10;
<> 144:ef7eb2e8f9f7 993 __O uint32_t SETTRIG0; /*!< (@ 0x50008070) Set Trigger control bits for all DMA channels. */
<> 144:ef7eb2e8f9f7 994 __I uint32_t RESERVED11;
<> 144:ef7eb2e8f9f7 995 __O uint32_t ABORT0; /*!< (@ 0x50008078) Channel Abort control for all DMA channels. */
<> 144:ef7eb2e8f9f7 996 __I uint32_t RESERVED12[225];
<> 144:ef7eb2e8f9f7 997 __IO uint32_t CFG0; /*!< (@ 0x50008400) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 998 __I uint32_t CTLSTAT0; /*!< (@ 0x50008404) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 999 __IO uint32_t XFERCFG0; /*!< (@ 0x50008408) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1000 0. */
<> 144:ef7eb2e8f9f7 1001 __I uint32_t RESERVED13;
<> 144:ef7eb2e8f9f7 1002 __IO uint32_t CFG1; /*!< (@ 0x50008410) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1003 __I uint32_t CTLSTAT1; /*!< (@ 0x50008414) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1004 __IO uint32_t XFERCFG1; /*!< (@ 0x50008418) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1005 0. */
<> 144:ef7eb2e8f9f7 1006 __I uint32_t RESERVED14;
<> 144:ef7eb2e8f9f7 1007 __IO uint32_t CFG2; /*!< (@ 0x50008420) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1008 __I uint32_t CTLSTAT2; /*!< (@ 0x50008424) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1009 __IO uint32_t XFERCFG2; /*!< (@ 0x50008428) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1010 0. */
<> 144:ef7eb2e8f9f7 1011 __I uint32_t RESERVED15;
<> 144:ef7eb2e8f9f7 1012 __IO uint32_t CFG3; /*!< (@ 0x50008430) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1013 __I uint32_t CTLSTAT3; /*!< (@ 0x50008434) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1014 __IO uint32_t XFERCFG3; /*!< (@ 0x50008438) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1015 0. */
<> 144:ef7eb2e8f9f7 1016 __I uint32_t RESERVED16;
<> 144:ef7eb2e8f9f7 1017 __IO uint32_t CFG4; /*!< (@ 0x50008440) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1018 __I uint32_t CTLSTAT4; /*!< (@ 0x50008444) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1019 __IO uint32_t XFERCFG4; /*!< (@ 0x50008448) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1020 0. */
<> 144:ef7eb2e8f9f7 1021 __I uint32_t RESERVED17;
<> 144:ef7eb2e8f9f7 1022 __IO uint32_t CFG5; /*!< (@ 0x50008450) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1023 __I uint32_t CTLSTAT5; /*!< (@ 0x50008454) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1024 __IO uint32_t XFERCFG5; /*!< (@ 0x50008458) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1025 0. */
<> 144:ef7eb2e8f9f7 1026 __I uint32_t RESERVED18;
<> 144:ef7eb2e8f9f7 1027 __IO uint32_t CFG6; /*!< (@ 0x50008460) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1028 __I uint32_t CTLSTAT6; /*!< (@ 0x50008464) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1029 __IO uint32_t XFERCFG6; /*!< (@ 0x50008468) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1030 0. */
<> 144:ef7eb2e8f9f7 1031 __I uint32_t RESERVED19;
<> 144:ef7eb2e8f9f7 1032 __IO uint32_t CFG7; /*!< (@ 0x50008470) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1033 __I uint32_t CTLSTAT7; /*!< (@ 0x50008474) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1034 __IO uint32_t XFERCFG7; /*!< (@ 0x50008478) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1035 0. */
<> 144:ef7eb2e8f9f7 1036 __I uint32_t RESERVED20;
<> 144:ef7eb2e8f9f7 1037 __IO uint32_t CFG8; /*!< (@ 0x50008480) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1038 __I uint32_t CTLSTAT8; /*!< (@ 0x50008484) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1039 __IO uint32_t XFERCFG8; /*!< (@ 0x50008488) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1040 0. */
<> 144:ef7eb2e8f9f7 1041 __I uint32_t RESERVED21;
<> 144:ef7eb2e8f9f7 1042 __IO uint32_t CFG9; /*!< (@ 0x50008490) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1043 __I uint32_t CTLSTAT9; /*!< (@ 0x50008494) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1044 __IO uint32_t XFERCFG9; /*!< (@ 0x50008498) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1045 0. */
<> 144:ef7eb2e8f9f7 1046 __I uint32_t RESERVED22;
<> 144:ef7eb2e8f9f7 1047 __IO uint32_t CFG10; /*!< (@ 0x500084A0) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1048 __I uint32_t CTLSTAT10; /*!< (@ 0x500084A4) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1049 __IO uint32_t XFERCFG10; /*!< (@ 0x500084A8) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1050 0. */
<> 144:ef7eb2e8f9f7 1051 __I uint32_t RESERVED23;
<> 144:ef7eb2e8f9f7 1052 __IO uint32_t CFG11; /*!< (@ 0x500084B0) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1053 __I uint32_t CTLSTAT11; /*!< (@ 0x500084B4) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1054 __IO uint32_t XFERCFG11; /*!< (@ 0x500084B8) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1055 0. */
<> 144:ef7eb2e8f9f7 1056 __I uint32_t RESERVED24;
<> 144:ef7eb2e8f9f7 1057 __IO uint32_t CFG12; /*!< (@ 0x500084C0) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1058 __I uint32_t CTLSTAT12; /*!< (@ 0x500084C4) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1059 __IO uint32_t XFERCFG12; /*!< (@ 0x500084C8) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1060 0. */
<> 144:ef7eb2e8f9f7 1061 __I uint32_t RESERVED25;
<> 144:ef7eb2e8f9f7 1062 __IO uint32_t CFG13; /*!< (@ 0x500084D0) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1063 __I uint32_t CTLSTAT13; /*!< (@ 0x500084D4) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1064 __IO uint32_t XFERCFG13; /*!< (@ 0x500084D8) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1065 0. */
<> 144:ef7eb2e8f9f7 1066 __I uint32_t RESERVED26;
<> 144:ef7eb2e8f9f7 1067 __IO uint32_t CFG14; /*!< (@ 0x500084E0) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1068 __I uint32_t CTLSTAT14; /*!< (@ 0x500084E4) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1069 __IO uint32_t XFERCFG14; /*!< (@ 0x500084E8) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1070 0. */
<> 144:ef7eb2e8f9f7 1071 __I uint32_t RESERVED27;
<> 144:ef7eb2e8f9f7 1072 __IO uint32_t CFG15; /*!< (@ 0x500084F0) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1073 __I uint32_t CTLSTAT15; /*!< (@ 0x500084F4) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1074 __IO uint32_t XFERCFG15; /*!< (@ 0x500084F8) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1075 0. */
<> 144:ef7eb2e8f9f7 1076 __I uint32_t RESERVED28;
<> 144:ef7eb2e8f9f7 1077 __IO uint32_t CFG16; /*!< (@ 0x50008500) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1078 __I uint32_t CTLSTAT16; /*!< (@ 0x50008504) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1079 __IO uint32_t XFERCFG16; /*!< (@ 0x50008508) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1080 0. */
<> 144:ef7eb2e8f9f7 1081 __I uint32_t RESERVED29;
<> 144:ef7eb2e8f9f7 1082 __IO uint32_t CFG17; /*!< (@ 0x50008510) Configuration register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1083 __I uint32_t CTLSTAT17; /*!< (@ 0x50008514) Control and status register for DMA channel 0. */
<> 144:ef7eb2e8f9f7 1084 __IO uint32_t XFERCFG17; /*!< (@ 0x50008518) Transfer configuration register for DMA channel
<> 144:ef7eb2e8f9f7 1085 0. */
<> 144:ef7eb2e8f9f7 1086 } LPC_DMA_Type;
<> 144:ef7eb2e8f9f7 1087
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1090 /* ================ GPIO_PORT ================ */
<> 144:ef7eb2e8f9f7 1091 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1092
<> 144:ef7eb2e8f9f7 1093
<> 144:ef7eb2e8f9f7 1094 /**
<> 144:ef7eb2e8f9f7 1095 * @brief General Purpose I/O port (GPIO) (GPIO_PORT)
<> 144:ef7eb2e8f9f7 1096 */
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 typedef struct { /*!< (@ 0xA0000000) GPIO_PORT Structure */
<> 144:ef7eb2e8f9f7 1099 __IO uint8_t B0; /*!< (@ 0xA0000000) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1100 __IO uint8_t B1; /*!< (@ 0xA0000001) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1101 __IO uint8_t B2; /*!< (@ 0xA0000002) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1102 __IO uint8_t B3; /*!< (@ 0xA0000003) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1103 __IO uint8_t B4; /*!< (@ 0xA0000004) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1104 __IO uint8_t B5; /*!< (@ 0xA0000005) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1105 __IO uint8_t B6; /*!< (@ 0xA0000006) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1106 __IO uint8_t B7; /*!< (@ 0xA0000007) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1107 __IO uint8_t B8; /*!< (@ 0xA0000008) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1108 __IO uint8_t B9; /*!< (@ 0xA0000009) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1109 __IO uint8_t B10; /*!< (@ 0xA000000A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1110 __IO uint8_t B11; /*!< (@ 0xA000000B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1111 __IO uint8_t B12; /*!< (@ 0xA000000C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1112 __IO uint8_t B13; /*!< (@ 0xA000000D) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1113 __IO uint8_t B14; /*!< (@ 0xA000000E) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1114 __IO uint8_t B15; /*!< (@ 0xA000000F) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1115 __IO uint8_t B16; /*!< (@ 0xA0000010) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1116 __IO uint8_t B17; /*!< (@ 0xA0000011) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1117 __IO uint8_t B18; /*!< (@ 0xA0000012) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1118 __IO uint8_t B19; /*!< (@ 0xA0000013) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1119 __IO uint8_t B20; /*!< (@ 0xA0000014) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1120 __IO uint8_t B21; /*!< (@ 0xA0000015) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1121 __IO uint8_t B22; /*!< (@ 0xA0000016) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1122 __IO uint8_t B23; /*!< (@ 0xA0000017) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1123 __IO uint8_t B24; /*!< (@ 0xA0000018) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1124 __IO uint8_t B25; /*!< (@ 0xA0000019) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1125 __IO uint8_t B26; /*!< (@ 0xA000001A) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1126 __IO uint8_t B27; /*!< (@ 0xA000001B) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1127 __IO uint8_t B28; /*!< (@ 0xA000001C) Byte pin registers port 0; pins PIO0_0 to PIO0_28 */
<> 144:ef7eb2e8f9f7 1128 __I uint8_t RESERVED0[4067];
<> 144:ef7eb2e8f9f7 1129 __IO uint32_t W0; /*!< (@ 0xA0001000) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1130 __IO uint32_t W1; /*!< (@ 0xA0001004) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1131 __IO uint32_t W2; /*!< (@ 0xA0001008) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1132 __IO uint32_t W3; /*!< (@ 0xA000100C) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1133 __IO uint32_t W4; /*!< (@ 0xA0001010) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1134 __IO uint32_t W5; /*!< (@ 0xA0001014) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1135 __IO uint32_t W6; /*!< (@ 0xA0001018) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1136 __IO uint32_t W7; /*!< (@ 0xA000101C) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1137 __IO uint32_t W8; /*!< (@ 0xA0001020) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1138 __IO uint32_t W9; /*!< (@ 0xA0001024) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1139 __IO uint32_t W10; /*!< (@ 0xA0001028) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1140 __IO uint32_t W11; /*!< (@ 0xA000102C) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1141 __IO uint32_t W12; /*!< (@ 0xA0001030) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1142 __IO uint32_t W13; /*!< (@ 0xA0001034) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1143 __IO uint32_t W14; /*!< (@ 0xA0001038) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1144 __IO uint32_t W15; /*!< (@ 0xA000103C) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1145 __IO uint32_t W16; /*!< (@ 0xA0001040) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1146 __IO uint32_t W17; /*!< (@ 0xA0001044) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1147 __IO uint32_t W18; /*!< (@ 0xA0001048) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1148 __IO uint32_t W19; /*!< (@ 0xA000104C) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1149 __IO uint32_t W20; /*!< (@ 0xA0001050) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1150 __IO uint32_t W21; /*!< (@ 0xA0001054) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1151 __IO uint32_t W22; /*!< (@ 0xA0001058) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1152 __IO uint32_t W23; /*!< (@ 0xA000105C) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1153 __IO uint32_t W24; /*!< (@ 0xA0001060) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1154 __IO uint32_t W25; /*!< (@ 0xA0001064) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1155 __IO uint32_t W26; /*!< (@ 0xA0001068) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1156 __IO uint32_t W27; /*!< (@ 0xA000106C) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1157 __IO uint32_t W28; /*!< (@ 0xA0001070) Word pin registers port 0 */
<> 144:ef7eb2e8f9f7 1158 __I uint32_t RESERVED1[995];
<> 144:ef7eb2e8f9f7 1159 __IO uint32_t DIR0; /*!< (@ 0xA0002000) Direction registers port 0 */
<> 144:ef7eb2e8f9f7 1160 __I uint32_t RESERVED2[31];
<> 144:ef7eb2e8f9f7 1161 __IO uint32_t MASK0; /*!< (@ 0xA0002080) Mask register port 0 */
<> 144:ef7eb2e8f9f7 1162 __I uint32_t RESERVED3[31];
<> 144:ef7eb2e8f9f7 1163 __IO uint32_t PIN0; /*!< (@ 0xA0002100) Port pin register port 0 */
<> 144:ef7eb2e8f9f7 1164 __I uint32_t RESERVED4[31];
<> 144:ef7eb2e8f9f7 1165 __IO uint32_t MPIN0; /*!< (@ 0xA0002180) Masked port register port 0 */
<> 144:ef7eb2e8f9f7 1166 __I uint32_t RESERVED5[31];
<> 144:ef7eb2e8f9f7 1167 __IO uint32_t SET0; /*!< (@ 0xA0002200) Write: Set register for port 0 Read: output bits
<> 144:ef7eb2e8f9f7 1168 for port 0 */
<> 144:ef7eb2e8f9f7 1169 __I uint32_t RESERVED6[31];
<> 144:ef7eb2e8f9f7 1170 __O uint32_t CLR0; /*!< (@ 0xA0002280) Clear port 0 */
<> 144:ef7eb2e8f9f7 1171 __I uint32_t RESERVED7[31];
<> 144:ef7eb2e8f9f7 1172 __O uint32_t NOT0; /*!< (@ 0xA0002300) Toggle port 0 */
<> 144:ef7eb2e8f9f7 1173 __I uint32_t RESERVED8[31];
<> 144:ef7eb2e8f9f7 1174 __O uint32_t DIRSET0; /*!< (@ 0xA0002380) Set pin direction bits for port 0. */
<> 144:ef7eb2e8f9f7 1175 __I uint32_t RESERVED9[31];
<> 144:ef7eb2e8f9f7 1176 __O uint32_t DIRCLR0; /*!< (@ 0xA0002400) Clear pin direction bits for port 0. */
<> 144:ef7eb2e8f9f7 1177 __I uint32_t RESERVED10[31];
<> 144:ef7eb2e8f9f7 1178 __O uint32_t DIRNOT0; /*!< (@ 0xA0002480) Toggle pin direction bits for port 0. */
<> 144:ef7eb2e8f9f7 1179 } LPC_GPIO_PORT_Type;
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181
<> 144:ef7eb2e8f9f7 1182 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1183 /* ================ PIN_INT ================ */
<> 144:ef7eb2e8f9f7 1184 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /**
<> 144:ef7eb2e8f9f7 1188 * @brief Pin interrupt and pattern match engine (PIN_INT)
<> 144:ef7eb2e8f9f7 1189 */
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 typedef struct { /*!< (@ 0xA0004000) PIN_INT Structure */
<> 144:ef7eb2e8f9f7 1192 __IO uint32_t ISEL; /*!< (@ 0xA0004000) Pin Interrupt Mode register */
<> 144:ef7eb2e8f9f7 1193 __IO uint32_t IENR; /*!< (@ 0xA0004004) Pin interrupt level or rising edge interrupt
<> 144:ef7eb2e8f9f7 1194 enable register */
<> 144:ef7eb2e8f9f7 1195 __O uint32_t SIENR; /*!< (@ 0xA0004008) Pin interrupt level (rising edge) interrupt set
<> 144:ef7eb2e8f9f7 1196 register */
<> 144:ef7eb2e8f9f7 1197 __O uint32_t CIENR; /*!< (@ 0xA000400C) Pin interrupt level or rising edge interrupt
<> 144:ef7eb2e8f9f7 1198 clear register */
<> 144:ef7eb2e8f9f7 1199 __IO uint32_t IENF; /*!< (@ 0xA0004010) Pin interrupt active level or falling edge interrupt
<> 144:ef7eb2e8f9f7 1200 enable register */
<> 144:ef7eb2e8f9f7 1201 __O uint32_t SIENF; /*!< (@ 0xA0004014) Pin interrupt active level or falling edge interrupt
<> 144:ef7eb2e8f9f7 1202 set register */
<> 144:ef7eb2e8f9f7 1203 __O uint32_t CIENF; /*!< (@ 0xA0004018) Pin interrupt active level (falling edge) interrupt
<> 144:ef7eb2e8f9f7 1204 clear register */
<> 144:ef7eb2e8f9f7 1205 __IO uint32_t RISE; /*!< (@ 0xA000401C) Pin interrupt rising edge register */
<> 144:ef7eb2e8f9f7 1206 __IO uint32_t FALL; /*!< (@ 0xA0004020) Pin interrupt falling edge register */
<> 144:ef7eb2e8f9f7 1207 __IO uint32_t IST; /*!< (@ 0xA0004024) Pin interrupt status register */
<> 144:ef7eb2e8f9f7 1208 __IO uint32_t PMCTRL; /*!< (@ 0xA0004028) GPIO pattern match interrupt control register */
<> 144:ef7eb2e8f9f7 1209 __IO uint32_t PMSRC; /*!< (@ 0xA000402C) GPIO pattern match interrupt bit-slice source
<> 144:ef7eb2e8f9f7 1210 register */
<> 144:ef7eb2e8f9f7 1211 __IO uint32_t PMCFG; /*!< (@ 0xA0004030) GPIO pattern match interrupt bit slice configuration
<> 144:ef7eb2e8f9f7 1212 register */
<> 144:ef7eb2e8f9f7 1213 } LPC_PIN_INT_Type;
<> 144:ef7eb2e8f9f7 1214
<> 144:ef7eb2e8f9f7 1215
<> 144:ef7eb2e8f9f7 1216 /* -------------------- End of section using anonymous unions ------------------- */
<> 144:ef7eb2e8f9f7 1217 #if defined(__CC_ARM)
<> 144:ef7eb2e8f9f7 1218 #pragma pop
<> 144:ef7eb2e8f9f7 1219 #elif defined(__ICCARM__)
<> 144:ef7eb2e8f9f7 1220 /* leave anonymous unions enabled */
<> 144:ef7eb2e8f9f7 1221 #elif defined(__GNUC__)
<> 144:ef7eb2e8f9f7 1222 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 1223 #elif defined(__TMS470__)
<> 144:ef7eb2e8f9f7 1224 /* anonymous unions are enabled by default */
<> 144:ef7eb2e8f9f7 1225 #elif defined(__TASKING__)
<> 144:ef7eb2e8f9f7 1226 #pragma warning restore
<> 144:ef7eb2e8f9f7 1227 #else
<> 144:ef7eb2e8f9f7 1228 #warning Not supported compiler type
<> 144:ef7eb2e8f9f7 1229 #endif
<> 144:ef7eb2e8f9f7 1230
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233
<> 144:ef7eb2e8f9f7 1234 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1235 /* ================ Peripheral memory map ================ */
<> 144:ef7eb2e8f9f7 1236 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1237
<> 144:ef7eb2e8f9f7 1238 #define LPC_WWDT_BASE 0x40000000UL
<> 144:ef7eb2e8f9f7 1239 #define LPC_MRT_BASE 0x40004000UL
<> 144:ef7eb2e8f9f7 1240 #define LPC_WKT_BASE 0x40008000UL
<> 144:ef7eb2e8f9f7 1241 #define LPC_SWM_BASE 0x4000C000UL
<> 144:ef7eb2e8f9f7 1242 #define LPC_ADC_BASE 0x4001C000UL
<> 144:ef7eb2e8f9f7 1243 #define LPC_PMU_BASE 0x40020000UL
<> 144:ef7eb2e8f9f7 1244 #define LPC_CMP_BASE 0x40024000UL
<> 144:ef7eb2e8f9f7 1245 #define LPC_DMATRIGMUX_BASE 0x40028000UL
<> 144:ef7eb2e8f9f7 1246 #define LPC_INPUTMUX_BASE 0x4002C000UL
<> 144:ef7eb2e8f9f7 1247 #define LPC_FLASHCTRL_BASE 0x40040000UL
<> 144:ef7eb2e8f9f7 1248 #define LPC_IOCON_BASE 0x40044000UL
<> 144:ef7eb2e8f9f7 1249 #define LPC_SYSCON_BASE 0x40048000UL
<> 144:ef7eb2e8f9f7 1250 #define LPC_I2C0_BASE 0x40050000UL
<> 144:ef7eb2e8f9f7 1251 #define LPC_I2C1_BASE 0x40054000UL
<> 144:ef7eb2e8f9f7 1252 #define LPC_SPI0_BASE 0x40058000UL
<> 144:ef7eb2e8f9f7 1253 #define LPC_SPI1_BASE 0x4005C000UL
<> 144:ef7eb2e8f9f7 1254 #define LPC_USART0_BASE 0x40064000UL
<> 144:ef7eb2e8f9f7 1255 #define LPC_USART1_BASE 0x40068000UL
<> 144:ef7eb2e8f9f7 1256 #define LPC_USART2_BASE 0x4006C000UL
<> 144:ef7eb2e8f9f7 1257 #define LPC_I2C2_BASE 0x40070000UL
<> 144:ef7eb2e8f9f7 1258 #define LPC_I2C3_BASE 0x40074000UL
<> 144:ef7eb2e8f9f7 1259 #define LPC_CRC_BASE 0x50000000UL
<> 144:ef7eb2e8f9f7 1260 #define LPC_SCT_BASE 0x50004000UL
<> 144:ef7eb2e8f9f7 1261 #define LPC_DMA_BASE 0x50008000UL
<> 144:ef7eb2e8f9f7 1262 #define LPC_GPIO_PORT_BASE 0xA0000000UL
<> 144:ef7eb2e8f9f7 1263 #define LPC_PIN_INT_BASE 0xA0004000UL
<> 144:ef7eb2e8f9f7 1264
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1267 /* ================ Peripheral declaration ================ */
<> 144:ef7eb2e8f9f7 1268 /* ================================================================================ */
<> 144:ef7eb2e8f9f7 1269
<> 144:ef7eb2e8f9f7 1270 #define LPC_WWDT ((LPC_WWDT_Type *) LPC_WWDT_BASE)
<> 144:ef7eb2e8f9f7 1271 #define LPC_MRT ((LPC_MRT_Type *) LPC_MRT_BASE)
<> 144:ef7eb2e8f9f7 1272 #define LPC_WKT ((LPC_WKT_Type *) LPC_WKT_BASE)
<> 144:ef7eb2e8f9f7 1273 #define LPC_SWM ((LPC_SWM_Type *) LPC_SWM_BASE)
<> 144:ef7eb2e8f9f7 1274 #define LPC_ADC ((LPC_ADC_Type *) LPC_ADC_BASE)
<> 144:ef7eb2e8f9f7 1275 #define LPC_PMU ((LPC_PMU_Type *) LPC_PMU_BASE)
<> 144:ef7eb2e8f9f7 1276 #define LPC_CMP ((LPC_CMP_Type *) LPC_CMP_BASE)
<> 144:ef7eb2e8f9f7 1277 #define LPC_DMATRIGMUX ((LPC_DMATRIGMUX_Type *) LPC_DMATRIGMUX_BASE)
<> 144:ef7eb2e8f9f7 1278 #define LPC_INPUTMUX ((LPC_INPUTMUX_Type *) LPC_INPUTMUX_BASE)
<> 144:ef7eb2e8f9f7 1279 #define LPC_FLASHCTRL ((LPC_FLASHCTRL_Type *) LPC_FLASHCTRL_BASE)
<> 144:ef7eb2e8f9f7 1280 #define LPC_IOCON ((LPC_IOCON_Type *) LPC_IOCON_BASE)
<> 144:ef7eb2e8f9f7 1281 #define LPC_SYSCON ((LPC_SYSCON_Type *) LPC_SYSCON_BASE)
<> 144:ef7eb2e8f9f7 1282 #define LPC_I2C0 ((LPC_I2C0_Type *) LPC_I2C0_BASE)
<> 144:ef7eb2e8f9f7 1283 #define LPC_I2C1 ((LPC_I2C0_Type *) LPC_I2C1_BASE)
<> 144:ef7eb2e8f9f7 1284 #define LPC_SPI0 ((LPC_SPI0_Type *) LPC_SPI0_BASE)
<> 144:ef7eb2e8f9f7 1285 #define LPC_SPI1 ((LPC_SPI0_Type *) LPC_SPI1_BASE)
<> 144:ef7eb2e8f9f7 1286 #define LPC_USART0 ((LPC_USART0_Type *) LPC_USART0_BASE)
<> 144:ef7eb2e8f9f7 1287 #define LPC_USART1 ((LPC_USART0_Type *) LPC_USART1_BASE)
<> 144:ef7eb2e8f9f7 1288 #define LPC_USART2 ((LPC_USART0_Type *) LPC_USART2_BASE)
<> 144:ef7eb2e8f9f7 1289 #define LPC_I2C2 ((LPC_I2C0_Type *) LPC_I2C2_BASE)
<> 144:ef7eb2e8f9f7 1290 #define LPC_I2C3 ((LPC_I2C0_Type *) LPC_I2C3_BASE)
<> 144:ef7eb2e8f9f7 1291 #define LPC_CRC ((LPC_CRC_Type *) LPC_CRC_BASE)
<> 144:ef7eb2e8f9f7 1292 #define LPC_SCT ((LPC_SCT_Type *) LPC_SCT_BASE)
<> 144:ef7eb2e8f9f7 1293 #define LPC_DMA ((LPC_DMA_Type *) LPC_DMA_BASE)
<> 144:ef7eb2e8f9f7 1294 #define LPC_GPIO_PORT ((LPC_GPIO_PORT_Type *) LPC_GPIO_PORT_BASE)
<> 144:ef7eb2e8f9f7 1295 #define LPC_PIN_INT ((LPC_PIN_INT_Type *) LPC_PIN_INT_BASE)
<> 144:ef7eb2e8f9f7 1296
<> 144:ef7eb2e8f9f7 1297
<> 144:ef7eb2e8f9f7 1298 /** @} */ /* End of group Device_Peripheral_Registers */
<> 144:ef7eb2e8f9f7 1299 /** @} */ /* End of group LPC82x */
<> 144:ef7eb2e8f9f7 1300 /** @} */ /* End of group (null) */
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 1303 }
<> 144:ef7eb2e8f9f7 1304 #endif
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306
<> 144:ef7eb2e8f9f7 1307 #endif /* LPC82x_H */
<> 144:ef7eb2e8f9f7 1308