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targets/TARGET_STM/TARGET_STM32F2/device/stm32f2xx_hal_tim_ex.c@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_STM/TARGET_STM32F2/stm32f2xx_hal_tim_ex.c@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f2xx_hal_tim_ex.c
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 144:ef7eb2e8f9f7 5 * @version V1.1.3
<> 144:ef7eb2e8f9f7 6 * @date 29-June-2016
<> 144:ef7eb2e8f9f7 7 * @brief TIM HAL module driver.
<> 144:ef7eb2e8f9f7 8 * This file provides firmware functions to manage the following
<> 144:ef7eb2e8f9f7 9 * functionalities of the Timer extension peripheral:
<> 144:ef7eb2e8f9f7 10 * + Time Hall Sensor Interface Initialization
<> 144:ef7eb2e8f9f7 11 * + Time Hall Sensor Interface Start
<> 144:ef7eb2e8f9f7 12 * + Time Complementary signal bread and dead time configuration
<> 144:ef7eb2e8f9f7 13 * + Time Master and Slave synchronization configuration
<> 144:ef7eb2e8f9f7 14 @verbatim
<> 144:ef7eb2e8f9f7 15 ==============================================================================
<> 144:ef7eb2e8f9f7 16 ##### TIMER Extended features #####
<> 144:ef7eb2e8f9f7 17 ==============================================================================
<> 144:ef7eb2e8f9f7 18 [..]
<> 144:ef7eb2e8f9f7 19 The Timer Extension features include:
<> 144:ef7eb2e8f9f7 20 (#) Complementary outputs with programmable dead-time for :
<> 144:ef7eb2e8f9f7 21 (++) Input Capture
<> 144:ef7eb2e8f9f7 22 (++) Output Compare
<> 144:ef7eb2e8f9f7 23 (++) PWM generation (Edge and Center-aligned Mode)
<> 144:ef7eb2e8f9f7 24 (++) One-pulse mode output
<> 144:ef7eb2e8f9f7 25 (#) Synchronization circuit to control the timer with external signals and to
<> 144:ef7eb2e8f9f7 26 interconnect several timers together.
<> 144:ef7eb2e8f9f7 27 (#) Break input to put the timer output signals in reset state or in a known state.
<> 144:ef7eb2e8f9f7 28 (#) Supports incremental (quadrature) encoder and hall-sensor circuitry for
<> 144:ef7eb2e8f9f7 29 positioning purposes
<> 144:ef7eb2e8f9f7 30
<> 144:ef7eb2e8f9f7 31 ##### How to use this driver #####
<> 144:ef7eb2e8f9f7 32 ==============================================================================
<> 144:ef7eb2e8f9f7 33 [..]
<> 144:ef7eb2e8f9f7 34 (#) Initialize the TIM low level resources by implementing the following functions
<> 144:ef7eb2e8f9f7 35 depending from feature used :
<> 144:ef7eb2e8f9f7 36 (++) Complementary Output Compare : HAL_TIM_OC_MspInit()
<> 144:ef7eb2e8f9f7 37 (++) Complementary PWM generation : HAL_TIM_PWM_MspInit()
<> 144:ef7eb2e8f9f7 38 (++) Complementary One-pulse mode output : HAL_TIM_OnePulse_MspInit()
<> 144:ef7eb2e8f9f7 39 (++) Hall Sensor output : HAL_TIM_HallSensor_MspInit()
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 (#) Initialize the TIM low level resources :
<> 144:ef7eb2e8f9f7 42 (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 43 (##) TIM pins configuration
<> 144:ef7eb2e8f9f7 44 (+++) Enable the clock for the TIM GPIOs using the following function:
<> 144:ef7eb2e8f9f7 45 __GPIOx_CLK_ENABLE();
<> 144:ef7eb2e8f9f7 46 (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 (#) The external Clock can be configured, if needed (the default clock is the
<> 144:ef7eb2e8f9f7 49 internal clock from the APBx), using the following function:
<> 144:ef7eb2e8f9f7 50 HAL_TIM_ConfigClockSource, the clock configuration should be done before
<> 144:ef7eb2e8f9f7 51 any start function.
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 (#) Configure the TIM in the desired functioning mode using one of the
<> 144:ef7eb2e8f9f7 54 initialization function of this driver:
<> 144:ef7eb2e8f9f7 55 (++) HAL_TIMEx_HallSensor_Init and HAL_TIMEx_ConfigCommutationEvent: to use the
<> 144:ef7eb2e8f9f7 56 Timer Hall Sensor Interface and the commutation event with the corresponding
<> 144:ef7eb2e8f9f7 57 Interrupt and DMA request if needed (Note that One Timer is used to interface
<> 144:ef7eb2e8f9f7 58 with the Hall sensor Interface and another Timer should be used to use
<> 144:ef7eb2e8f9f7 59 the commutation event).
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 (#) Activate the TIM peripheral using one of the start functions:
<> 144:ef7eb2e8f9f7 62 (++) Complementary Output Compare : HAL_TIMEx_OCN_Start(), HAL_TIMEx_OCN_Start_DMA(), HAL_TIMEx_OC_Start_IT()
<> 144:ef7eb2e8f9f7 63 (++) Complementary PWM generation : HAL_TIMEx_PWMN_Start(), HAL_TIMEx_PWMN_Start_DMA(), HAL_TIMEx_PWMN_Start_IT()
<> 144:ef7eb2e8f9f7 64 (++) Complementary One-pulse mode output : HAL_TIMEx_OnePulseN_Start(), HAL_TIMEx_OnePulseN_Start_IT()
<> 144:ef7eb2e8f9f7 65 (++) Hall Sensor output : HAL_TIMEx_HallSensor_Start(), HAL_TIMEx_HallSensor_Start_DMA(), HAL_TIMEx_HallSensor_Start_IT().
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67
<> 144:ef7eb2e8f9f7 68 @endverbatim
<> 144:ef7eb2e8f9f7 69 ******************************************************************************
<> 144:ef7eb2e8f9f7 70 * @attention
<> 144:ef7eb2e8f9f7 71 *
<> 144:ef7eb2e8f9f7 72 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 73 *
<> 144:ef7eb2e8f9f7 74 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 75 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 76 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 77 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 78 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 79 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 80 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 81 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 82 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 83 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 84 *
<> 144:ef7eb2e8f9f7 85 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 86 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 87 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 88 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 89 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 90 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 91 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 92 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 93 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 94 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 95 *
<> 144:ef7eb2e8f9f7 96 ******************************************************************************
<> 144:ef7eb2e8f9f7 97 */
<> 144:ef7eb2e8f9f7 98
<> 144:ef7eb2e8f9f7 99 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 100 #include "stm32f2xx_hal.h"
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 /** @addtogroup STM32F2xx_HAL_Driver
<> 144:ef7eb2e8f9f7 103 * @{
<> 144:ef7eb2e8f9f7 104 */
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 /** @defgroup TIMEx TIMEx
<> 144:ef7eb2e8f9f7 107 * @brief TIM HAL module driver
<> 144:ef7eb2e8f9f7 108 * @{
<> 144:ef7eb2e8f9f7 109 */
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 #ifdef HAL_TIM_MODULE_ENABLED
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /* Private typedef -----------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 114 /* Private define ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 115 /* Private macro -------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 116 /* Private variables ---------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 117 /** @addtogroup TIMEx_Private_Functions
<> 144:ef7eb2e8f9f7 118 * @{
<> 144:ef7eb2e8f9f7 119 */
<> 144:ef7eb2e8f9f7 120 /* Private function prototypes -----------------------------------------------*/
<> 144:ef7eb2e8f9f7 121 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState);
<> 144:ef7eb2e8f9f7 122 /**
<> 144:ef7eb2e8f9f7 123 * @}
<> 144:ef7eb2e8f9f7 124 */
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 127 /** @defgroup TIMEx_Exported_Functions TIM Exported Functions
<> 144:ef7eb2e8f9f7 128 * @{
<> 144:ef7eb2e8f9f7 129 */
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 /** @defgroup TIMEx_Exported_Functions_Group1 Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 132 * @brief Timer Hall Sensor functions
<> 144:ef7eb2e8f9f7 133 *
<> 144:ef7eb2e8f9f7 134 @verbatim
<> 144:ef7eb2e8f9f7 135 ==============================================================================
<> 144:ef7eb2e8f9f7 136 ##### Timer Hall Sensor functions #####
<> 144:ef7eb2e8f9f7 137 ==============================================================================
<> 144:ef7eb2e8f9f7 138 [..]
<> 144:ef7eb2e8f9f7 139 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 140 (+) Initialize and configure TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 141 (+) De-initialize TIM HAL Sensor.
<> 144:ef7eb2e8f9f7 142 (+) Start the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 143 (+) Stop the Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 144 (+) Start the Hall Sensor Interface and enable interrupts.
<> 144:ef7eb2e8f9f7 145 (+) Stop the Hall Sensor Interface and disable interrupts.
<> 144:ef7eb2e8f9f7 146 (+) Start the Hall Sensor Interface and enable DMA transfers.
<> 144:ef7eb2e8f9f7 147 (+) Stop the Hall Sensor Interface and disable DMA transfers.
<> 144:ef7eb2e8f9f7 148
<> 144:ef7eb2e8f9f7 149 @endverbatim
<> 144:ef7eb2e8f9f7 150 * @{
<> 144:ef7eb2e8f9f7 151 */
<> 144:ef7eb2e8f9f7 152 /**
<> 144:ef7eb2e8f9f7 153 * @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
<> 144:ef7eb2e8f9f7 154 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 155 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 156 * @param sConfig: TIM Hall Sensor configuration structure
<> 144:ef7eb2e8f9f7 157 * @retval HAL status
<> 144:ef7eb2e8f9f7 158 */
<> 144:ef7eb2e8f9f7 159 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 TIM_OC_InitTypeDef OC_Config;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 /* Check the TIM handle allocation */
<> 144:ef7eb2e8f9f7 164 if(htim == NULL)
<> 144:ef7eb2e8f9f7 165 {
<> 144:ef7eb2e8f9f7 166 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 167 }
<> 144:ef7eb2e8f9f7 168
<> 144:ef7eb2e8f9f7 169 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 170 assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
<> 144:ef7eb2e8f9f7 171 assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
<> 144:ef7eb2e8f9f7 172 assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
<> 144:ef7eb2e8f9f7 173 assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
<> 144:ef7eb2e8f9f7 174 assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
<> 144:ef7eb2e8f9f7 175
<> 144:ef7eb2e8f9f7 176 /* Set the TIM state */
<> 144:ef7eb2e8f9f7 177 htim->State= HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
<> 144:ef7eb2e8f9f7 180 HAL_TIMEx_HallSensor_MspInit(htim);
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /* Configure the Time base in the Encoder Mode */
<> 144:ef7eb2e8f9f7 183 TIM_Base_SetConfig(htim->Instance, &htim->Init);
<> 144:ef7eb2e8f9f7 184
<> 144:ef7eb2e8f9f7 185 /* Configure the Channel 1 as Input Channel to interface with the three Outputs of the Hall sensor */
<> 144:ef7eb2e8f9f7 186 TIM_TI1_SetConfig(htim->Instance, sConfig->IC1Polarity, TIM_ICSELECTION_TRC, sConfig->IC1Filter);
<> 144:ef7eb2e8f9f7 187
<> 144:ef7eb2e8f9f7 188 /* Reset the IC1PSC Bits */
<> 144:ef7eb2e8f9f7 189 htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
<> 144:ef7eb2e8f9f7 190 /* Set the IC1PSC value */
<> 144:ef7eb2e8f9f7 191 htim->Instance->CCMR1 |= sConfig->IC1Prescaler;
<> 144:ef7eb2e8f9f7 192
<> 144:ef7eb2e8f9f7 193 /* Enable the Hall sensor interface (XOR function of the three inputs) */
<> 144:ef7eb2e8f9f7 194 htim->Instance->CR2 |= TIM_CR2_TI1S;
<> 144:ef7eb2e8f9f7 195
<> 144:ef7eb2e8f9f7 196 /* Select the TIM_TS_TI1F_ED signal as Input trigger for the TIM */
<> 144:ef7eb2e8f9f7 197 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 198 htim->Instance->SMCR |= TIM_TS_TI1F_ED;
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 /* Use the TIM_TS_TI1F_ED signal to reset the TIM counter each edge detection */
<> 144:ef7eb2e8f9f7 201 htim->Instance->SMCR &= ~TIM_SMCR_SMS;
<> 144:ef7eb2e8f9f7 202 htim->Instance->SMCR |= TIM_SLAVEMODE_RESET;
<> 144:ef7eb2e8f9f7 203
<> 144:ef7eb2e8f9f7 204 /* Program channel 2 in PWM 2 mode with the desired Commutation_Delay*/
<> 144:ef7eb2e8f9f7 205 OC_Config.OCFastMode = TIM_OCFAST_DISABLE;
<> 144:ef7eb2e8f9f7 206 OC_Config.OCIdleState = TIM_OCIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 207 OC_Config.OCMode = TIM_OCMODE_PWM2;
<> 144:ef7eb2e8f9f7 208 OC_Config.OCNIdleState = TIM_OCNIDLESTATE_RESET;
<> 144:ef7eb2e8f9f7 209 OC_Config.OCNPolarity = TIM_OCNPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 210 OC_Config.OCPolarity = TIM_OCPOLARITY_HIGH;
<> 144:ef7eb2e8f9f7 211 OC_Config.Pulse = sConfig->Commutation_Delay;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 TIM_OC2_SetConfig(htim->Instance, &OC_Config);
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 /* Select OC2REF as trigger output on TRGO: write the MMS bits in the TIMx_CR2
<> 144:ef7eb2e8f9f7 216 register to 101 */
<> 144:ef7eb2e8f9f7 217 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 218 htim->Instance->CR2 |= TIM_TRGO_OC2REF;
<> 144:ef7eb2e8f9f7 219
<> 144:ef7eb2e8f9f7 220 /* Initialize the TIM state*/
<> 144:ef7eb2e8f9f7 221 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 222
<> 144:ef7eb2e8f9f7 223 return HAL_OK;
<> 144:ef7eb2e8f9f7 224 }
<> 144:ef7eb2e8f9f7 225
<> 144:ef7eb2e8f9f7 226 /**
<> 144:ef7eb2e8f9f7 227 * @brief DeInitializes the TIM Hall Sensor interface
<> 144:ef7eb2e8f9f7 228 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 229 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 230 * @retval HAL status
<> 144:ef7eb2e8f9f7 231 */
<> 144:ef7eb2e8f9f7 232 HAL_StatusTypeDef HAL_TIMEx_HallSensor_DeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 233 {
<> 144:ef7eb2e8f9f7 234 /* Check the parameters */
<> 144:ef7eb2e8f9f7 235 assert_param(IS_TIM_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 236
<> 144:ef7eb2e8f9f7 237 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /* Disable the TIM Peripheral Clock */
<> 144:ef7eb2e8f9f7 240 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 241
<> 144:ef7eb2e8f9f7 242 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
<> 144:ef7eb2e8f9f7 243 HAL_TIMEx_HallSensor_MspDeInit(htim);
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* Change TIM state */
<> 144:ef7eb2e8f9f7 246 htim->State = HAL_TIM_STATE_RESET;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* Release Lock */
<> 144:ef7eb2e8f9f7 249 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 return HAL_OK;
<> 144:ef7eb2e8f9f7 252 }
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /**
<> 144:ef7eb2e8f9f7 255 * @brief Initializes the TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 256 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 257 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 258 * @retval None
<> 144:ef7eb2e8f9f7 259 */
<> 144:ef7eb2e8f9f7 260 __weak void HAL_TIMEx_HallSensor_MspInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 263 UNUSED(htim);
<> 144:ef7eb2e8f9f7 264 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 265 the HAL_TIMEx_HallSensor_MspInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 266 */
<> 144:ef7eb2e8f9f7 267 }
<> 144:ef7eb2e8f9f7 268
<> 144:ef7eb2e8f9f7 269 /**
<> 144:ef7eb2e8f9f7 270 * @brief DeInitializes TIM Hall Sensor MSP.
<> 144:ef7eb2e8f9f7 271 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 272 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 273 * @retval None
<> 144:ef7eb2e8f9f7 274 */
<> 144:ef7eb2e8f9f7 275 __weak void HAL_TIMEx_HallSensor_MspDeInit(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 276 {
<> 144:ef7eb2e8f9f7 277 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 278 UNUSED(htim);
<> 144:ef7eb2e8f9f7 279 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 280 the HAL_TIMEx_HallSensor_MspDeInit could be implemented in the user file
<> 144:ef7eb2e8f9f7 281 */
<> 144:ef7eb2e8f9f7 282 }
<> 144:ef7eb2e8f9f7 283
<> 144:ef7eb2e8f9f7 284 /**
<> 144:ef7eb2e8f9f7 285 * @brief Starts the TIM Hall Sensor Interface.
<> 144:ef7eb2e8f9f7 286 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 287 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 288 * @retval HAL status
<> 144:ef7eb2e8f9f7 289 */
<> 144:ef7eb2e8f9f7 290 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 291 {
<> 144:ef7eb2e8f9f7 292 /* Check the parameters */
<> 144:ef7eb2e8f9f7 293 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 294
<> 144:ef7eb2e8f9f7 295 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 296 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 297 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 298
<> 144:ef7eb2e8f9f7 299 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 300 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 301
<> 144:ef7eb2e8f9f7 302 /* Return function status */
<> 144:ef7eb2e8f9f7 303 return HAL_OK;
<> 144:ef7eb2e8f9f7 304 }
<> 144:ef7eb2e8f9f7 305
<> 144:ef7eb2e8f9f7 306 /**
<> 144:ef7eb2e8f9f7 307 * @brief Stops the TIM Hall sensor Interface.
<> 144:ef7eb2e8f9f7 308 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 309 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 310 * @retval HAL status
<> 144:ef7eb2e8f9f7 311 */
<> 144:ef7eb2e8f9f7 312 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 313 {
<> 144:ef7eb2e8f9f7 314 /* Check the parameters */
<> 144:ef7eb2e8f9f7 315 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 316
<> 144:ef7eb2e8f9f7 317 /* Disable the Input Capture channels 1, 2 and 3
<> 144:ef7eb2e8f9f7 318 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 319 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 322 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 /* Return function status */
<> 144:ef7eb2e8f9f7 325 return HAL_OK;
<> 144:ef7eb2e8f9f7 326 }
<> 144:ef7eb2e8f9f7 327
<> 144:ef7eb2e8f9f7 328 /**
<> 144:ef7eb2e8f9f7 329 * @brief Starts the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 330 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 331 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 332 * @retval HAL status
<> 144:ef7eb2e8f9f7 333 */
<> 144:ef7eb2e8f9f7 334 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 335 {
<> 144:ef7eb2e8f9f7 336 /* Check the parameters */
<> 144:ef7eb2e8f9f7 337 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 338
<> 144:ef7eb2e8f9f7 339 /* Enable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 340 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 341
<> 144:ef7eb2e8f9f7 342 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 343 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 344 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 345
<> 144:ef7eb2e8f9f7 346 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 347 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 348
<> 144:ef7eb2e8f9f7 349 /* Return function status */
<> 144:ef7eb2e8f9f7 350 return HAL_OK;
<> 144:ef7eb2e8f9f7 351 }
<> 144:ef7eb2e8f9f7 352
<> 144:ef7eb2e8f9f7 353 /**
<> 144:ef7eb2e8f9f7 354 * @brief Stops the TIM Hall Sensor Interface in interrupt mode.
<> 144:ef7eb2e8f9f7 355 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 356 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 357 * @retval HAL status
<> 144:ef7eb2e8f9f7 358 */
<> 144:ef7eb2e8f9f7 359 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_IT(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 360 {
<> 144:ef7eb2e8f9f7 361 /* Check the parameters */
<> 144:ef7eb2e8f9f7 362 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 363
<> 144:ef7eb2e8f9f7 364 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 365 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 366 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 /* Disable the capture compare Interrupts event */
<> 144:ef7eb2e8f9f7 369 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 372 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 /* Return function status */
<> 144:ef7eb2e8f9f7 375 return HAL_OK;
<> 144:ef7eb2e8f9f7 376 }
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 /**
<> 144:ef7eb2e8f9f7 379 * @brief Starts the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 380 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 381 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 382 * @param pData: The destination Buffer address.
<> 144:ef7eb2e8f9f7 383 * @param Length: The length of data to be transferred from TIM peripheral to memory.
<> 144:ef7eb2e8f9f7 384 * @retval HAL status
<> 144:ef7eb2e8f9f7 385 */
<> 144:ef7eb2e8f9f7 386 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 387 {
<> 144:ef7eb2e8f9f7 388 /* Check the parameters */
<> 144:ef7eb2e8f9f7 389 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 390
<> 144:ef7eb2e8f9f7 391 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 392 {
<> 144:ef7eb2e8f9f7 393 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 394 }
<> 144:ef7eb2e8f9f7 395 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 396 {
<> 144:ef7eb2e8f9f7 397 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 398 {
<> 144:ef7eb2e8f9f7 399 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 400 }
<> 144:ef7eb2e8f9f7 401 else
<> 144:ef7eb2e8f9f7 402 {
<> 144:ef7eb2e8f9f7 403 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 404 }
<> 144:ef7eb2e8f9f7 405 }
<> 144:ef7eb2e8f9f7 406 /* Enable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 407 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 408 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
<> 144:ef7eb2e8f9f7 409
<> 144:ef7eb2e8f9f7 410 /* Set the DMA Input Capture 1 Callback */
<> 144:ef7eb2e8f9f7 411 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
<> 144:ef7eb2e8f9f7 412 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 413 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 414
<> 144:ef7eb2e8f9f7 415 /* Enable the DMA Stream for Capture 1*/
<> 144:ef7eb2e8f9f7 416 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
<> 144:ef7eb2e8f9f7 417
<> 144:ef7eb2e8f9f7 418 /* Enable the capture compare 1 Interrupt */
<> 144:ef7eb2e8f9f7 419 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 420
<> 144:ef7eb2e8f9f7 421 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 422 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 423
<> 144:ef7eb2e8f9f7 424 /* Return function status */
<> 144:ef7eb2e8f9f7 425 return HAL_OK;
<> 144:ef7eb2e8f9f7 426 }
<> 144:ef7eb2e8f9f7 427
<> 144:ef7eb2e8f9f7 428 /**
<> 144:ef7eb2e8f9f7 429 * @brief Stops the TIM Hall Sensor Interface in DMA mode.
<> 144:ef7eb2e8f9f7 430 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 431 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 432 * @retval HAL status
<> 144:ef7eb2e8f9f7 433 */
<> 144:ef7eb2e8f9f7 434 HAL_StatusTypeDef HAL_TIMEx_HallSensor_Stop_DMA(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 435 {
<> 144:ef7eb2e8f9f7 436 /* Check the parameters */
<> 144:ef7eb2e8f9f7 437 assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 /* Disable the Input Capture channels 1
<> 144:ef7eb2e8f9f7 440 (in the Hall Sensor Interface the Three possible channels that can be used are TIM_CHANNEL_1, TIM_CHANNEL_2 and TIM_CHANNEL_3) */
<> 144:ef7eb2e8f9f7 441 TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443
<> 144:ef7eb2e8f9f7 444 /* Disable the capture compare Interrupts 1 event */
<> 144:ef7eb2e8f9f7 445 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 448 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 449
<> 144:ef7eb2e8f9f7 450 /* Return function status */
<> 144:ef7eb2e8f9f7 451 return HAL_OK;
<> 144:ef7eb2e8f9f7 452 }
<> 144:ef7eb2e8f9f7 453 /**
<> 144:ef7eb2e8f9f7 454 * @}
<> 144:ef7eb2e8f9f7 455 */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 /** @defgroup TIMEx_Exported_Functions_Group2 Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 458 * @brief Timer Complementary Output Compare functions
<> 144:ef7eb2e8f9f7 459 *
<> 144:ef7eb2e8f9f7 460 @verbatim
<> 144:ef7eb2e8f9f7 461 ==============================================================================
<> 144:ef7eb2e8f9f7 462 ##### Timer Complementary Output Compare functions #####
<> 144:ef7eb2e8f9f7 463 ==============================================================================
<> 144:ef7eb2e8f9f7 464 [..]
<> 144:ef7eb2e8f9f7 465 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 466 (+) Start the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 467 (+) Stop the Complementary Output Compare/PWM.
<> 144:ef7eb2e8f9f7 468 (+) Start the Complementary Output Compare/PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 469 (+) Stop the Complementary Output Compare/PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 470 (+) Start the Complementary Output Compare/PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 471 (+) Stop the Complementary Output Compare/PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 472
<> 144:ef7eb2e8f9f7 473 @endverbatim
<> 144:ef7eb2e8f9f7 474 * @{
<> 144:ef7eb2e8f9f7 475 */
<> 144:ef7eb2e8f9f7 476
<> 144:ef7eb2e8f9f7 477 /**
<> 144:ef7eb2e8f9f7 478 * @brief Starts the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 479 * output.
<> 144:ef7eb2e8f9f7 480 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 481 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 482 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 483 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 484 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 485 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 486 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 487 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 488 * @retval HAL status
<> 144:ef7eb2e8f9f7 489 */
<> 144:ef7eb2e8f9f7 490 HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 491 {
<> 144:ef7eb2e8f9f7 492 /* Check the parameters */
<> 144:ef7eb2e8f9f7 493 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 496 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 499 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 500
<> 144:ef7eb2e8f9f7 501 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 502 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 503
<> 144:ef7eb2e8f9f7 504 /* Return function status */
<> 144:ef7eb2e8f9f7 505 return HAL_OK;
<> 144:ef7eb2e8f9f7 506 }
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /**
<> 144:ef7eb2e8f9f7 509 * @brief Stops the TIM Output Compare signal generation on the complementary
<> 144:ef7eb2e8f9f7 510 * output.
<> 144:ef7eb2e8f9f7 511 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 512 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 513 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 514 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 515 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 516 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 517 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 518 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 519 * @retval HAL status
<> 144:ef7eb2e8f9f7 520 */
<> 144:ef7eb2e8f9f7 521 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 522 {
<> 144:ef7eb2e8f9f7 523 /* Check the parameters */
<> 144:ef7eb2e8f9f7 524 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 525
<> 144:ef7eb2e8f9f7 526 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 527 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 530 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 531
<> 144:ef7eb2e8f9f7 532 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 533 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 /* Return function status */
<> 144:ef7eb2e8f9f7 536 return HAL_OK;
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 /**
<> 144:ef7eb2e8f9f7 540 * @brief Starts the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 541 * on the complementary output.
<> 144:ef7eb2e8f9f7 542 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 543 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 544 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 545 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 546 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 547 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 548 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 549 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 550 * @retval HAL status
<> 144:ef7eb2e8f9f7 551 */
<> 144:ef7eb2e8f9f7 552 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 553 {
<> 144:ef7eb2e8f9f7 554 /* Check the parameters */
<> 144:ef7eb2e8f9f7 555 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 switch (Channel)
<> 144:ef7eb2e8f9f7 558 {
<> 144:ef7eb2e8f9f7 559 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 560 {
<> 144:ef7eb2e8f9f7 561 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 562 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 563 }
<> 144:ef7eb2e8f9f7 564 break;
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 567 {
<> 144:ef7eb2e8f9f7 568 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 569 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 570 }
<> 144:ef7eb2e8f9f7 571 break;
<> 144:ef7eb2e8f9f7 572
<> 144:ef7eb2e8f9f7 573 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 574 {
<> 144:ef7eb2e8f9f7 575 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 576 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 577 }
<> 144:ef7eb2e8f9f7 578 break;
<> 144:ef7eb2e8f9f7 579
<> 144:ef7eb2e8f9f7 580 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 581 {
<> 144:ef7eb2e8f9f7 582 /* Enable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 583 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 584 }
<> 144:ef7eb2e8f9f7 585 break;
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 default:
<> 144:ef7eb2e8f9f7 588 break;
<> 144:ef7eb2e8f9f7 589 }
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 592 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 595 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 598 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 599
<> 144:ef7eb2e8f9f7 600 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 601 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 602
<> 144:ef7eb2e8f9f7 603 /* Return function status */
<> 144:ef7eb2e8f9f7 604 return HAL_OK;
<> 144:ef7eb2e8f9f7 605 }
<> 144:ef7eb2e8f9f7 606
<> 144:ef7eb2e8f9f7 607 /**
<> 144:ef7eb2e8f9f7 608 * @brief Stops the TIM Output Compare signal generation in interrupt mode
<> 144:ef7eb2e8f9f7 609 * on the complementary output.
<> 144:ef7eb2e8f9f7 610 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 611 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 612 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 613 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 614 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 615 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 616 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 617 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 618 * @retval HAL status
<> 144:ef7eb2e8f9f7 619 */
<> 144:ef7eb2e8f9f7 620 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 621 {
<> 144:ef7eb2e8f9f7 622 /* Check the parameters */
<> 144:ef7eb2e8f9f7 623 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 switch (Channel)
<> 144:ef7eb2e8f9f7 626 {
<> 144:ef7eb2e8f9f7 627 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 630 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 631 }
<> 144:ef7eb2e8f9f7 632 break;
<> 144:ef7eb2e8f9f7 633
<> 144:ef7eb2e8f9f7 634 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 635 {
<> 144:ef7eb2e8f9f7 636 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 637 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 638 }
<> 144:ef7eb2e8f9f7 639 break;
<> 144:ef7eb2e8f9f7 640
<> 144:ef7eb2e8f9f7 641 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 642 {
<> 144:ef7eb2e8f9f7 643 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 644 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 645 }
<> 144:ef7eb2e8f9f7 646 break;
<> 144:ef7eb2e8f9f7 647
<> 144:ef7eb2e8f9f7 648 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 649 {
<> 144:ef7eb2e8f9f7 650 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 651 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 652 }
<> 144:ef7eb2e8f9f7 653 break;
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655 default:
<> 144:ef7eb2e8f9f7 656 break;
<> 144:ef7eb2e8f9f7 657 }
<> 144:ef7eb2e8f9f7 658
<> 144:ef7eb2e8f9f7 659 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 660 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 661
<> 144:ef7eb2e8f9f7 662 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 663 if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 664 {
<> 144:ef7eb2e8f9f7 665 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 666 }
<> 144:ef7eb2e8f9f7 667
<> 144:ef7eb2e8f9f7 668 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 669 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 670
<> 144:ef7eb2e8f9f7 671 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 672 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 673
<> 144:ef7eb2e8f9f7 674 /* Return function status */
<> 144:ef7eb2e8f9f7 675 return HAL_OK;
<> 144:ef7eb2e8f9f7 676 }
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /**
<> 144:ef7eb2e8f9f7 679 * @brief Starts the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 680 * on the complementary output.
<> 144:ef7eb2e8f9f7 681 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 682 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 683 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 684 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 685 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 686 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 687 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 688 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 689 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 690 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 691 * @retval HAL status
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 694 {
<> 144:ef7eb2e8f9f7 695 /* Check the parameters */
<> 144:ef7eb2e8f9f7 696 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 697
<> 144:ef7eb2e8f9f7 698 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 699 {
<> 144:ef7eb2e8f9f7 700 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 701 }
<> 144:ef7eb2e8f9f7 702 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 703 {
<> 144:ef7eb2e8f9f7 704 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 705 {
<> 144:ef7eb2e8f9f7 706 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708 else
<> 144:ef7eb2e8f9f7 709 {
<> 144:ef7eb2e8f9f7 710 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 711 }
<> 144:ef7eb2e8f9f7 712 }
<> 144:ef7eb2e8f9f7 713 switch (Channel)
<> 144:ef7eb2e8f9f7 714 {
<> 144:ef7eb2e8f9f7 715 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 716 {
<> 144:ef7eb2e8f9f7 717 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 718 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 719
<> 144:ef7eb2e8f9f7 720 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 721 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 724 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 727 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 728 }
<> 144:ef7eb2e8f9f7 729 break;
<> 144:ef7eb2e8f9f7 730
<> 144:ef7eb2e8f9f7 731 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 734 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 737 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 738
<> 144:ef7eb2e8f9f7 739 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 740 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 741
<> 144:ef7eb2e8f9f7 742 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 743 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 744 }
<> 144:ef7eb2e8f9f7 745 break;
<> 144:ef7eb2e8f9f7 746
<> 144:ef7eb2e8f9f7 747 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 748 {
<> 144:ef7eb2e8f9f7 749 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 750 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 751
<> 144:ef7eb2e8f9f7 752 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 753 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 754
<> 144:ef7eb2e8f9f7 755 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 756 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 759 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 760 }
<> 144:ef7eb2e8f9f7 761 break;
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 764 {
<> 144:ef7eb2e8f9f7 765 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 766 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 769 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 770
<> 144:ef7eb2e8f9f7 771 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 772 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 773
<> 144:ef7eb2e8f9f7 774 /* Enable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 775 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 776 }
<> 144:ef7eb2e8f9f7 777 break;
<> 144:ef7eb2e8f9f7 778
<> 144:ef7eb2e8f9f7 779 default:
<> 144:ef7eb2e8f9f7 780 break;
<> 144:ef7eb2e8f9f7 781 }
<> 144:ef7eb2e8f9f7 782
<> 144:ef7eb2e8f9f7 783 /* Enable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 784 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 787 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 788
<> 144:ef7eb2e8f9f7 789 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 790 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 791
<> 144:ef7eb2e8f9f7 792 /* Return function status */
<> 144:ef7eb2e8f9f7 793 return HAL_OK;
<> 144:ef7eb2e8f9f7 794 }
<> 144:ef7eb2e8f9f7 795
<> 144:ef7eb2e8f9f7 796 /**
<> 144:ef7eb2e8f9f7 797 * @brief Stops the TIM Output Compare signal generation in DMA mode
<> 144:ef7eb2e8f9f7 798 * on the complementary output.
<> 144:ef7eb2e8f9f7 799 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 800 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 801 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 802 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 803 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 804 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 805 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 806 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 807 * @retval HAL status
<> 144:ef7eb2e8f9f7 808 */
<> 144:ef7eb2e8f9f7 809 HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 /* Check the parameters */
<> 144:ef7eb2e8f9f7 812 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814 switch (Channel)
<> 144:ef7eb2e8f9f7 815 {
<> 144:ef7eb2e8f9f7 816 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 817 {
<> 144:ef7eb2e8f9f7 818 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 819 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 820 }
<> 144:ef7eb2e8f9f7 821 break;
<> 144:ef7eb2e8f9f7 822
<> 144:ef7eb2e8f9f7 823 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 824 {
<> 144:ef7eb2e8f9f7 825 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 826 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 827 }
<> 144:ef7eb2e8f9f7 828 break;
<> 144:ef7eb2e8f9f7 829
<> 144:ef7eb2e8f9f7 830 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 831 {
<> 144:ef7eb2e8f9f7 832 /* Disable the TIM Output Compare DMA request */
<> 144:ef7eb2e8f9f7 833 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 834 }
<> 144:ef7eb2e8f9f7 835 break;
<> 144:ef7eb2e8f9f7 836
<> 144:ef7eb2e8f9f7 837 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 838 {
<> 144:ef7eb2e8f9f7 839 /* Disable the TIM Output Compare interrupt */
<> 144:ef7eb2e8f9f7 840 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 841 }
<> 144:ef7eb2e8f9f7 842 break;
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 default:
<> 144:ef7eb2e8f9f7 845 break;
<> 144:ef7eb2e8f9f7 846 }
<> 144:ef7eb2e8f9f7 847
<> 144:ef7eb2e8f9f7 848 /* Disable the Capture compare channel N */
<> 144:ef7eb2e8f9f7 849 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 850
<> 144:ef7eb2e8f9f7 851 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 852 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 853
<> 144:ef7eb2e8f9f7 854 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 855 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /* Change the htim state */
<> 144:ef7eb2e8f9f7 858 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 859
<> 144:ef7eb2e8f9f7 860 /* Return function status */
<> 144:ef7eb2e8f9f7 861 return HAL_OK;
<> 144:ef7eb2e8f9f7 862 }
<> 144:ef7eb2e8f9f7 863 /**
<> 144:ef7eb2e8f9f7 864 * @}
<> 144:ef7eb2e8f9f7 865 */
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /** @defgroup TIMEx_Exported_Functions_Group3 Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 868 * @brief Timer Complementary PWM functions
<> 144:ef7eb2e8f9f7 869 *
<> 144:ef7eb2e8f9f7 870 @verbatim
<> 144:ef7eb2e8f9f7 871 ==============================================================================
<> 144:ef7eb2e8f9f7 872 ##### Timer Complementary PWM functions #####
<> 144:ef7eb2e8f9f7 873 ==============================================================================
<> 144:ef7eb2e8f9f7 874 [..]
<> 144:ef7eb2e8f9f7 875 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 876 (+) Start the Complementary PWM.
<> 144:ef7eb2e8f9f7 877 (+) Stop the Complementary PWM.
<> 144:ef7eb2e8f9f7 878 (+) Start the Complementary PWM and enable interrupts.
<> 144:ef7eb2e8f9f7 879 (+) Stop the Complementary PWM and disable interrupts.
<> 144:ef7eb2e8f9f7 880 (+) Start the Complementary PWM and enable DMA transfers.
<> 144:ef7eb2e8f9f7 881 (+) Stop the Complementary PWM and disable DMA transfers.
<> 144:ef7eb2e8f9f7 882 (+) Start the Complementary Input Capture measurement.
<> 144:ef7eb2e8f9f7 883 (+) Stop the Complementary Input Capture.
<> 144:ef7eb2e8f9f7 884 (+) Start the Complementary Input Capture and enable interrupts.
<> 144:ef7eb2e8f9f7 885 (+) Stop the Complementary Input Capture and disable interrupts.
<> 144:ef7eb2e8f9f7 886 (+) Start the Complementary Input Capture and enable DMA transfers.
<> 144:ef7eb2e8f9f7 887 (+) Stop the Complementary Input Capture and disable DMA transfers.
<> 144:ef7eb2e8f9f7 888 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 889 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 890 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 891 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 892
<> 144:ef7eb2e8f9f7 893 @endverbatim
<> 144:ef7eb2e8f9f7 894 * @{
<> 144:ef7eb2e8f9f7 895 */
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @brief Starts the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 899 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 900 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 901 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 902 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 903 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 904 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 905 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 906 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 907 * @retval HAL status
<> 144:ef7eb2e8f9f7 908 */
<> 144:ef7eb2e8f9f7 909 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 910 {
<> 144:ef7eb2e8f9f7 911 /* Check the parameters */
<> 144:ef7eb2e8f9f7 912 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 913
<> 144:ef7eb2e8f9f7 914 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 915 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 918 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 919
<> 144:ef7eb2e8f9f7 920 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 921 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 922
<> 144:ef7eb2e8f9f7 923 /* Return function status */
<> 144:ef7eb2e8f9f7 924 return HAL_OK;
<> 144:ef7eb2e8f9f7 925 }
<> 144:ef7eb2e8f9f7 926
<> 144:ef7eb2e8f9f7 927 /**
<> 144:ef7eb2e8f9f7 928 * @brief Stops the PWM signal generation on the complementary output.
<> 144:ef7eb2e8f9f7 929 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 930 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 931 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 932 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 933 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 934 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 935 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 936 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 937 * @retval HAL status
<> 144:ef7eb2e8f9f7 938 */
<> 144:ef7eb2e8f9f7 939 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 940 {
<> 144:ef7eb2e8f9f7 941 /* Check the parameters */
<> 144:ef7eb2e8f9f7 942 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 943
<> 144:ef7eb2e8f9f7 944 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 945 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 946
<> 144:ef7eb2e8f9f7 947 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 948 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 949
<> 144:ef7eb2e8f9f7 950 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 951 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /* Return function status */
<> 144:ef7eb2e8f9f7 954 return HAL_OK;
<> 144:ef7eb2e8f9f7 955 }
<> 144:ef7eb2e8f9f7 956
<> 144:ef7eb2e8f9f7 957 /**
<> 144:ef7eb2e8f9f7 958 * @brief Starts the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 959 * complementary output.
<> 144:ef7eb2e8f9f7 960 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 961 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 962 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 963 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 964 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 965 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 966 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 967 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 968 * @retval HAL status
<> 144:ef7eb2e8f9f7 969 */
<> 144:ef7eb2e8f9f7 970 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 971 {
<> 144:ef7eb2e8f9f7 972 /* Check the parameters */
<> 144:ef7eb2e8f9f7 973 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 switch (Channel)
<> 144:ef7eb2e8f9f7 976 {
<> 144:ef7eb2e8f9f7 977 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 978 {
<> 144:ef7eb2e8f9f7 979 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 980 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 981 }
<> 144:ef7eb2e8f9f7 982 break;
<> 144:ef7eb2e8f9f7 983
<> 144:ef7eb2e8f9f7 984 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 985 {
<> 144:ef7eb2e8f9f7 986 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 987 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 988 }
<> 144:ef7eb2e8f9f7 989 break;
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 992 {
<> 144:ef7eb2e8f9f7 993 /* Enable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 994 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 995 }
<> 144:ef7eb2e8f9f7 996 break;
<> 144:ef7eb2e8f9f7 997
<> 144:ef7eb2e8f9f7 998 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 999 {
<> 144:ef7eb2e8f9f7 1000 /* Enable the TIM Capture/Compare 4 interrupt */
<> 144:ef7eb2e8f9f7 1001 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1002 }
<> 144:ef7eb2e8f9f7 1003 break;
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 default:
<> 144:ef7eb2e8f9f7 1006 break;
<> 144:ef7eb2e8f9f7 1007 }
<> 144:ef7eb2e8f9f7 1008
<> 144:ef7eb2e8f9f7 1009 /* Enable the TIM Break interrupt */
<> 144:ef7eb2e8f9f7 1010 __HAL_TIM_ENABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1011
<> 144:ef7eb2e8f9f7 1012 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1013 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1014
<> 144:ef7eb2e8f9f7 1015 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1016 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1017
<> 144:ef7eb2e8f9f7 1018 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1019 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1020
<> 144:ef7eb2e8f9f7 1021 /* Return function status */
<> 144:ef7eb2e8f9f7 1022 return HAL_OK;
<> 144:ef7eb2e8f9f7 1023 }
<> 144:ef7eb2e8f9f7 1024
<> 144:ef7eb2e8f9f7 1025 /**
<> 144:ef7eb2e8f9f7 1026 * @brief Stops the PWM signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1027 * complementary output.
<> 144:ef7eb2e8f9f7 1028 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1029 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1030 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1031 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1032 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1033 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1034 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1035 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1036 * @retval HAL status
<> 144:ef7eb2e8f9f7 1037 */
<> 144:ef7eb2e8f9f7 1038 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1039 {
<> 144:ef7eb2e8f9f7 1040 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1041 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1042
<> 144:ef7eb2e8f9f7 1043 switch (Channel)
<> 144:ef7eb2e8f9f7 1044 {
<> 144:ef7eb2e8f9f7 1045 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1046 {
<> 144:ef7eb2e8f9f7 1047 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1048 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1049 }
<> 144:ef7eb2e8f9f7 1050 break;
<> 144:ef7eb2e8f9f7 1051
<> 144:ef7eb2e8f9f7 1052 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1053 {
<> 144:ef7eb2e8f9f7 1054 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1055 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1056 }
<> 144:ef7eb2e8f9f7 1057 break;
<> 144:ef7eb2e8f9f7 1058
<> 144:ef7eb2e8f9f7 1059 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1060 {
<> 144:ef7eb2e8f9f7 1061 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1062 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
<> 144:ef7eb2e8f9f7 1063 }
<> 144:ef7eb2e8f9f7 1064 break;
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1067 {
<> 144:ef7eb2e8f9f7 1068 /* Disable the TIM Capture/Compare 3 interrupt */
<> 144:ef7eb2e8f9f7 1069 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
<> 144:ef7eb2e8f9f7 1070 }
<> 144:ef7eb2e8f9f7 1071 break;
<> 144:ef7eb2e8f9f7 1072
<> 144:ef7eb2e8f9f7 1073 default:
<> 144:ef7eb2e8f9f7 1074 break;
<> 144:ef7eb2e8f9f7 1075 }
<> 144:ef7eb2e8f9f7 1076
<> 144:ef7eb2e8f9f7 1077 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1078 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /* Disable the TIM Break interrupt (only if no more channel is active) */
<> 144:ef7eb2e8f9f7 1081 if((READ_REG(htim->Instance->CCER) & (TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE)) == RESET)
<> 144:ef7eb2e8f9f7 1082 {
<> 144:ef7eb2e8f9f7 1083 __HAL_TIM_DISABLE_IT(htim, TIM_IT_BREAK);
<> 144:ef7eb2e8f9f7 1084 }
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1087 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1088
<> 144:ef7eb2e8f9f7 1089 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1090 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1091
<> 144:ef7eb2e8f9f7 1092 /* Return function status */
<> 144:ef7eb2e8f9f7 1093 return HAL_OK;
<> 144:ef7eb2e8f9f7 1094 }
<> 144:ef7eb2e8f9f7 1095
<> 144:ef7eb2e8f9f7 1096 /**
<> 144:ef7eb2e8f9f7 1097 * @brief Starts the TIM PWM signal generation in DMA mode on the
<> 144:ef7eb2e8f9f7 1098 * complementary output
<> 144:ef7eb2e8f9f7 1099 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1100 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1101 * @param Channel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1102 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1103 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1104 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1105 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1106 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1107 * @param pData: The source Buffer address.
<> 144:ef7eb2e8f9f7 1108 * @param Length: The length of data to be transferred from memory to TIM peripheral
<> 144:ef7eb2e8f9f7 1109 * @retval HAL status
<> 144:ef7eb2e8f9f7 1110 */
<> 144:ef7eb2e8f9f7 1111 HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
<> 144:ef7eb2e8f9f7 1112 {
<> 144:ef7eb2e8f9f7 1113 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1114 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1115
<> 144:ef7eb2e8f9f7 1116 if((htim->State == HAL_TIM_STATE_BUSY))
<> 144:ef7eb2e8f9f7 1117 {
<> 144:ef7eb2e8f9f7 1118 return HAL_BUSY;
<> 144:ef7eb2e8f9f7 1119 }
<> 144:ef7eb2e8f9f7 1120 else if((htim->State == HAL_TIM_STATE_READY))
<> 144:ef7eb2e8f9f7 1121 {
<> 144:ef7eb2e8f9f7 1122 if(((uint32_t)pData == 0U ) && (Length > 0U))
<> 144:ef7eb2e8f9f7 1123 {
<> 144:ef7eb2e8f9f7 1124 return HAL_ERROR;
<> 144:ef7eb2e8f9f7 1125 }
<> 144:ef7eb2e8f9f7 1126 else
<> 144:ef7eb2e8f9f7 1127 {
<> 144:ef7eb2e8f9f7 1128 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1129 }
<> 144:ef7eb2e8f9f7 1130 }
<> 144:ef7eb2e8f9f7 1131 switch (Channel)
<> 144:ef7eb2e8f9f7 1132 {
<> 144:ef7eb2e8f9f7 1133 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1134 {
<> 144:ef7eb2e8f9f7 1135 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1136 htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1137
<> 144:ef7eb2e8f9f7 1138 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1139 htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1142 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
<> 144:ef7eb2e8f9f7 1143
<> 144:ef7eb2e8f9f7 1144 /* Enable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1145 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1146 }
<> 144:ef7eb2e8f9f7 1147 break;
<> 144:ef7eb2e8f9f7 1148
<> 144:ef7eb2e8f9f7 1149 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1150 {
<> 144:ef7eb2e8f9f7 1151 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1152 htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1153
<> 144:ef7eb2e8f9f7 1154 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1155 htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1156
<> 144:ef7eb2e8f9f7 1157 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1158 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
<> 144:ef7eb2e8f9f7 1159
<> 144:ef7eb2e8f9f7 1160 /* Enable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1161 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1162 }
<> 144:ef7eb2e8f9f7 1163 break;
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1166 {
<> 144:ef7eb2e8f9f7 1167 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1168 htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1169
<> 144:ef7eb2e8f9f7 1170 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1171 htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1172
<> 144:ef7eb2e8f9f7 1173 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1174 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
<> 144:ef7eb2e8f9f7 1175
<> 144:ef7eb2e8f9f7 1176 /* Enable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1177 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1178 }
<> 144:ef7eb2e8f9f7 1179 break;
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1182 {
<> 144:ef7eb2e8f9f7 1183 /* Set the DMA Period elapsed callback */
<> 144:ef7eb2e8f9f7 1184 htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
<> 144:ef7eb2e8f9f7 1185
<> 144:ef7eb2e8f9f7 1186 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1187 htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
<> 144:ef7eb2e8f9f7 1188
<> 144:ef7eb2e8f9f7 1189 /* Enable the DMA Stream */
<> 144:ef7eb2e8f9f7 1190 HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
<> 144:ef7eb2e8f9f7 1191
<> 144:ef7eb2e8f9f7 1192 /* Enable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1193 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1194 }
<> 144:ef7eb2e8f9f7 1195 break;
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 default:
<> 144:ef7eb2e8f9f7 1198 break;
<> 144:ef7eb2e8f9f7 1199 }
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 /* Enable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1202 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1203
<> 144:ef7eb2e8f9f7 1204 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1205 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1206
<> 144:ef7eb2e8f9f7 1207 /* Enable the Peripheral */
<> 144:ef7eb2e8f9f7 1208 __HAL_TIM_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1209
<> 144:ef7eb2e8f9f7 1210 /* Return function status */
<> 144:ef7eb2e8f9f7 1211 return HAL_OK;
<> 144:ef7eb2e8f9f7 1212 }
<> 144:ef7eb2e8f9f7 1213
<> 144:ef7eb2e8f9f7 1214 /**
<> 144:ef7eb2e8f9f7 1215 * @brief Stops the TIM PWM signal generation in DMA mode on the complementary
<> 144:ef7eb2e8f9f7 1216 * output
<> 144:ef7eb2e8f9f7 1217 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1218 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1219 * @param Channel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1220 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1221 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1222 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1223 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
<> 144:ef7eb2e8f9f7 1224 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
<> 144:ef7eb2e8f9f7 1225 * @retval HAL status
<> 144:ef7eb2e8f9f7 1226 */
<> 144:ef7eb2e8f9f7 1227 HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
<> 144:ef7eb2e8f9f7 1228 {
<> 144:ef7eb2e8f9f7 1229 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1230 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, Channel));
<> 144:ef7eb2e8f9f7 1231
<> 144:ef7eb2e8f9f7 1232 switch (Channel)
<> 144:ef7eb2e8f9f7 1233 {
<> 144:ef7eb2e8f9f7 1234 case TIM_CHANNEL_1:
<> 144:ef7eb2e8f9f7 1235 {
<> 144:ef7eb2e8f9f7 1236 /* Disable the TIM Capture/Compare 1 DMA request */
<> 144:ef7eb2e8f9f7 1237 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
<> 144:ef7eb2e8f9f7 1238 }
<> 144:ef7eb2e8f9f7 1239 break;
<> 144:ef7eb2e8f9f7 1240
<> 144:ef7eb2e8f9f7 1241 case TIM_CHANNEL_2:
<> 144:ef7eb2e8f9f7 1242 {
<> 144:ef7eb2e8f9f7 1243 /* Disable the TIM Capture/Compare 2 DMA request */
<> 144:ef7eb2e8f9f7 1244 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
<> 144:ef7eb2e8f9f7 1245 }
<> 144:ef7eb2e8f9f7 1246 break;
<> 144:ef7eb2e8f9f7 1247
<> 144:ef7eb2e8f9f7 1248 case TIM_CHANNEL_3:
<> 144:ef7eb2e8f9f7 1249 {
<> 144:ef7eb2e8f9f7 1250 /* Disable the TIM Capture/Compare 3 DMA request */
<> 144:ef7eb2e8f9f7 1251 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
<> 144:ef7eb2e8f9f7 1252 }
<> 144:ef7eb2e8f9f7 1253 break;
<> 144:ef7eb2e8f9f7 1254
<> 144:ef7eb2e8f9f7 1255 case TIM_CHANNEL_4:
<> 144:ef7eb2e8f9f7 1256 {
<> 144:ef7eb2e8f9f7 1257 /* Disable the TIM Capture/Compare 4 DMA request */
<> 144:ef7eb2e8f9f7 1258 __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
<> 144:ef7eb2e8f9f7 1259 }
<> 144:ef7eb2e8f9f7 1260 break;
<> 144:ef7eb2e8f9f7 1261
<> 144:ef7eb2e8f9f7 1262 default:
<> 144:ef7eb2e8f9f7 1263 break;
<> 144:ef7eb2e8f9f7 1264 }
<> 144:ef7eb2e8f9f7 1265
<> 144:ef7eb2e8f9f7 1266 /* Disable the complementary PWM output */
<> 144:ef7eb2e8f9f7 1267 TIM_CCxNChannelCmd(htim->Instance, Channel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1268
<> 144:ef7eb2e8f9f7 1269 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1270 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1271
<> 144:ef7eb2e8f9f7 1272 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1273 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1274
<> 144:ef7eb2e8f9f7 1275 /* Change the htim state */
<> 144:ef7eb2e8f9f7 1276 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1277
<> 144:ef7eb2e8f9f7 1278 /* Return function status */
<> 144:ef7eb2e8f9f7 1279 return HAL_OK;
<> 144:ef7eb2e8f9f7 1280 }
<> 144:ef7eb2e8f9f7 1281
<> 144:ef7eb2e8f9f7 1282 /**
<> 144:ef7eb2e8f9f7 1283 * @}
<> 144:ef7eb2e8f9f7 1284 */
<> 144:ef7eb2e8f9f7 1285
<> 144:ef7eb2e8f9f7 1286 /** @defgroup TIMEx_Exported_Functions_Group4 Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1287 * @brief Timer Complementary One Pulse functions
<> 144:ef7eb2e8f9f7 1288 *
<> 144:ef7eb2e8f9f7 1289 @verbatim
<> 144:ef7eb2e8f9f7 1290 ==============================================================================
<> 144:ef7eb2e8f9f7 1291 ##### Timer Complementary One Pulse functions #####
<> 144:ef7eb2e8f9f7 1292 ==============================================================================
<> 144:ef7eb2e8f9f7 1293 [..]
<> 144:ef7eb2e8f9f7 1294 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1295 (+) Start the Complementary One Pulse generation.
<> 144:ef7eb2e8f9f7 1296 (+) Stop the Complementary One Pulse.
<> 144:ef7eb2e8f9f7 1297 (+) Start the Complementary One Pulse and enable interrupts.
<> 144:ef7eb2e8f9f7 1298 (+) Stop the Complementary One Pulse and disable interrupts.
<> 144:ef7eb2e8f9f7 1299
<> 144:ef7eb2e8f9f7 1300 @endverbatim
<> 144:ef7eb2e8f9f7 1301 * @{
<> 144:ef7eb2e8f9f7 1302 */
<> 144:ef7eb2e8f9f7 1303
<> 144:ef7eb2e8f9f7 1304 /**
<> 144:ef7eb2e8f9f7 1305 * @brief Starts the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1306 * output.
<> 144:ef7eb2e8f9f7 1307 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1308 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1309 * @param OutputChannel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1310 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1311 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1312 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1313 * @retval HAL status
<> 144:ef7eb2e8f9f7 1314 */
<> 144:ef7eb2e8f9f7 1315 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1316 {
<> 144:ef7eb2e8f9f7 1317 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1318 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1319
<> 144:ef7eb2e8f9f7 1320 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1321 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1322
<> 144:ef7eb2e8f9f7 1323 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1324 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1325
<> 144:ef7eb2e8f9f7 1326 /* Return function status */
<> 144:ef7eb2e8f9f7 1327 return HAL_OK;
<> 144:ef7eb2e8f9f7 1328 }
<> 144:ef7eb2e8f9f7 1329
<> 144:ef7eb2e8f9f7 1330 /**
<> 144:ef7eb2e8f9f7 1331 * @brief Stops the TIM One Pulse signal generation on the complementary
<> 144:ef7eb2e8f9f7 1332 * output.
<> 144:ef7eb2e8f9f7 1333 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1334 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1335 * @param OutputChannel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1336 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1337 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1338 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1339 * @retval HAL status
<> 144:ef7eb2e8f9f7 1340 */
<> 144:ef7eb2e8f9f7 1341 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1342 {
<> 144:ef7eb2e8f9f7 1343
<> 144:ef7eb2e8f9f7 1344 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1345 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1346
<> 144:ef7eb2e8f9f7 1347 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1348 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1351 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1352
<> 144:ef7eb2e8f9f7 1353 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1354 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1355
<> 144:ef7eb2e8f9f7 1356 /* Return function status */
<> 144:ef7eb2e8f9f7 1357 return HAL_OK;
<> 144:ef7eb2e8f9f7 1358 }
<> 144:ef7eb2e8f9f7 1359
<> 144:ef7eb2e8f9f7 1360 /**
<> 144:ef7eb2e8f9f7 1361 * @brief Starts the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1362 * complementary channel.
<> 144:ef7eb2e8f9f7 1363 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1364 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1365 * @param OutputChannel: TIM Channel to be enabled.
<> 144:ef7eb2e8f9f7 1366 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1367 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1368 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1369 * @retval HAL status
<> 144:ef7eb2e8f9f7 1370 */
<> 144:ef7eb2e8f9f7 1371 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1372 {
<> 144:ef7eb2e8f9f7 1373 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1374 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1375
<> 144:ef7eb2e8f9f7 1376 /* Enable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1377 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1378
<> 144:ef7eb2e8f9f7 1379 /* Enable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1380 __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1381
<> 144:ef7eb2e8f9f7 1382 /* Enable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1383 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_ENABLE);
<> 144:ef7eb2e8f9f7 1384
<> 144:ef7eb2e8f9f7 1385 /* Enable the Main Output */
<> 144:ef7eb2e8f9f7 1386 __HAL_TIM_MOE_ENABLE(htim);
<> 144:ef7eb2e8f9f7 1387
<> 144:ef7eb2e8f9f7 1388 /* Return function status */
<> 144:ef7eb2e8f9f7 1389 return HAL_OK;
<> 144:ef7eb2e8f9f7 1390 }
<> 144:ef7eb2e8f9f7 1391
<> 144:ef7eb2e8f9f7 1392 /**
<> 144:ef7eb2e8f9f7 1393 * @brief Stops the TIM One Pulse signal generation in interrupt mode on the
<> 144:ef7eb2e8f9f7 1394 * complementary channel.
<> 144:ef7eb2e8f9f7 1395 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1396 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1397 * @param OutputChannel: TIM Channel to be disabled.
<> 144:ef7eb2e8f9f7 1398 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1399 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
<> 144:ef7eb2e8f9f7 1400 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
<> 144:ef7eb2e8f9f7 1401 * @retval HAL status
<> 144:ef7eb2e8f9f7 1402 */
<> 144:ef7eb2e8f9f7 1403 HAL_StatusTypeDef HAL_TIMEx_OnePulseN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
<> 144:ef7eb2e8f9f7 1404 {
<> 144:ef7eb2e8f9f7 1405 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1406 assert_param(IS_TIM_CCXN_INSTANCE(htim->Instance, OutputChannel));
<> 144:ef7eb2e8f9f7 1407
<> 144:ef7eb2e8f9f7 1408 /* Disable the TIM Capture/Compare 1 interrupt */
<> 144:ef7eb2e8f9f7 1409 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
<> 144:ef7eb2e8f9f7 1410
<> 144:ef7eb2e8f9f7 1411 /* Disable the TIM Capture/Compare 2 interrupt */
<> 144:ef7eb2e8f9f7 1412 __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
<> 144:ef7eb2e8f9f7 1413
<> 144:ef7eb2e8f9f7 1414 /* Disable the complementary One Pulse output */
<> 144:ef7eb2e8f9f7 1415 TIM_CCxNChannelCmd(htim->Instance, OutputChannel, TIM_CCxN_DISABLE);
<> 144:ef7eb2e8f9f7 1416
<> 144:ef7eb2e8f9f7 1417 /* Disable the Main Output */
<> 144:ef7eb2e8f9f7 1418 __HAL_TIM_MOE_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1419
<> 144:ef7eb2e8f9f7 1420 /* Disable the Peripheral */
<> 144:ef7eb2e8f9f7 1421 __HAL_TIM_DISABLE(htim);
<> 144:ef7eb2e8f9f7 1422
<> 144:ef7eb2e8f9f7 1423 /* Return function status */
<> 144:ef7eb2e8f9f7 1424 return HAL_OK;
<> 144:ef7eb2e8f9f7 1425 }
<> 144:ef7eb2e8f9f7 1426 /**
<> 144:ef7eb2e8f9f7 1427 * @}
<> 144:ef7eb2e8f9f7 1428 */
<> 144:ef7eb2e8f9f7 1429
<> 144:ef7eb2e8f9f7 1430 /** @defgroup TIMEx_Exported_Functions_Group5 Peripheral Control functions
<> 144:ef7eb2e8f9f7 1431 * @brief Peripheral Control functions
<> 144:ef7eb2e8f9f7 1432 *
<> 144:ef7eb2e8f9f7 1433 @verbatim
<> 144:ef7eb2e8f9f7 1434 ==============================================================================
<> 144:ef7eb2e8f9f7 1435 ##### Peripheral Control functions #####
<> 144:ef7eb2e8f9f7 1436 ==============================================================================
<> 144:ef7eb2e8f9f7 1437 [..]
<> 144:ef7eb2e8f9f7 1438 This section provides functions allowing to:
<> 144:ef7eb2e8f9f7 1439 (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
<> 144:ef7eb2e8f9f7 1440 (+) Configure External Clock source.
<> 144:ef7eb2e8f9f7 1441 (+) Configure Complementary channels, break features and dead time.
<> 144:ef7eb2e8f9f7 1442 (+) Configure Master and the Slave synchronization.
<> 144:ef7eb2e8f9f7 1443 (+) Configure the commutation event in case of use of the Hall sensor interface.
<> 144:ef7eb2e8f9f7 1444 (+) Configure the DMA Burst Mode.
<> 144:ef7eb2e8f9f7 1445
<> 144:ef7eb2e8f9f7 1446 @endverbatim
<> 144:ef7eb2e8f9f7 1447 * @{
<> 144:ef7eb2e8f9f7 1448 */
<> 144:ef7eb2e8f9f7 1449 /**
<> 144:ef7eb2e8f9f7 1450 * @brief Configure the TIM commutation event sequence.
<> 144:ef7eb2e8f9f7 1451 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1452 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1453 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1454 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1455 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1456 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1457 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1458 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1459 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1460 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1461 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1462 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1463 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1464 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1465 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1466 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1467 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1468 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1469 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1470 * @retval HAL status
<> 144:ef7eb2e8f9f7 1471 */
<> 144:ef7eb2e8f9f7 1472 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1473 {
<> 144:ef7eb2e8f9f7 1474 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1475 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1476 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1477
<> 144:ef7eb2e8f9f7 1478 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1479
<> 144:ef7eb2e8f9f7 1480 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1481 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1482 {
<> 144:ef7eb2e8f9f7 1483 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1484 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1485 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1486 }
<> 144:ef7eb2e8f9f7 1487
<> 144:ef7eb2e8f9f7 1488 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1489 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1490 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1491 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1492 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1493
<> 144:ef7eb2e8f9f7 1494 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1495
<> 144:ef7eb2e8f9f7 1496 return HAL_OK;
<> 144:ef7eb2e8f9f7 1497 }
<> 144:ef7eb2e8f9f7 1498
<> 144:ef7eb2e8f9f7 1499 /**
<> 144:ef7eb2e8f9f7 1500 * @brief Configure the TIM commutation event sequence with interrupt.
<> 144:ef7eb2e8f9f7 1501 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1502 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1503 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1504 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1505 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1506 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1507 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1508 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1509 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1510 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1511 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1512 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1513 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1514 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1515 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1516 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1517 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1518 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1519 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1520 * @retval HAL status
<> 144:ef7eb2e8f9f7 1521 */
<> 144:ef7eb2e8f9f7 1522 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_IT(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1523 {
<> 144:ef7eb2e8f9f7 1524 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1525 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1526 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1527
<> 144:ef7eb2e8f9f7 1528 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1529
<> 144:ef7eb2e8f9f7 1530 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1531 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1532 {
<> 144:ef7eb2e8f9f7 1533 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1534 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1535 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1536 }
<> 144:ef7eb2e8f9f7 1537
<> 144:ef7eb2e8f9f7 1538 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1539 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1540 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1541 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1542 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1543
<> 144:ef7eb2e8f9f7 1544 /* Enable the Commutation Interrupt Request */
<> 144:ef7eb2e8f9f7 1545 __HAL_TIM_ENABLE_IT(htim, TIM_IT_COM);
<> 144:ef7eb2e8f9f7 1546
<> 144:ef7eb2e8f9f7 1547 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1548
<> 144:ef7eb2e8f9f7 1549 return HAL_OK;
<> 144:ef7eb2e8f9f7 1550 }
<> 144:ef7eb2e8f9f7 1551
<> 144:ef7eb2e8f9f7 1552 /**
<> 144:ef7eb2e8f9f7 1553 * @brief Configure the TIM commutation event sequence with DMA.
<> 144:ef7eb2e8f9f7 1554 * @note This function is mandatory to use the commutation event in order to
<> 144:ef7eb2e8f9f7 1555 * update the configuration at each commutation detection on the TRGI input of the Timer,
<> 144:ef7eb2e8f9f7 1556 * the typical use of this feature is with the use of another Timer(interface Timer)
<> 144:ef7eb2e8f9f7 1557 * configured in Hall sensor interface, this interface Timer will generate the
<> 144:ef7eb2e8f9f7 1558 * commutation at its TRGO output (connected to Timer used in this function) each time
<> 144:ef7eb2e8f9f7 1559 * the TI1 of the Interface Timer detect a commutation at its input TI1.
<> 144:ef7eb2e8f9f7 1560 * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
<> 144:ef7eb2e8f9f7 1561 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1562 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1563 * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
<> 144:ef7eb2e8f9f7 1564 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1565 * @arg TIM_TS_ITR0: Internal trigger 0 selected
<> 144:ef7eb2e8f9f7 1566 * @arg TIM_TS_ITR1: Internal trigger 1 selected
<> 144:ef7eb2e8f9f7 1567 * @arg TIM_TS_ITR2: Internal trigger 2 selected
<> 144:ef7eb2e8f9f7 1568 * @arg TIM_TS_ITR3: Internal trigger 3 selected
<> 144:ef7eb2e8f9f7 1569 * @arg TIM_TS_NONE: No trigger is needed
<> 144:ef7eb2e8f9f7 1570 * @param CommutationSource: the Commutation Event source.
<> 144:ef7eb2e8f9f7 1571 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1572 * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
<> 144:ef7eb2e8f9f7 1573 * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
<> 144:ef7eb2e8f9f7 1574 * @retval HAL status
<> 144:ef7eb2e8f9f7 1575 */
<> 144:ef7eb2e8f9f7 1576 HAL_StatusTypeDef HAL_TIMEx_ConfigCommutationEvent_DMA(TIM_HandleTypeDef *htim, uint32_t InputTrigger, uint32_t CommutationSource)
<> 144:ef7eb2e8f9f7 1577 {
<> 144:ef7eb2e8f9f7 1578 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1579 assert_param(IS_TIM_ADVANCED_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1580 assert_param(IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(InputTrigger));
<> 144:ef7eb2e8f9f7 1581
<> 144:ef7eb2e8f9f7 1582 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1583
<> 144:ef7eb2e8f9f7 1584 if ((InputTrigger == TIM_TS_ITR0) || (InputTrigger == TIM_TS_ITR1) ||
<> 144:ef7eb2e8f9f7 1585 (InputTrigger == TIM_TS_ITR2) || (InputTrigger == TIM_TS_ITR3))
<> 144:ef7eb2e8f9f7 1586 {
<> 144:ef7eb2e8f9f7 1587 /* Select the Input trigger */
<> 144:ef7eb2e8f9f7 1588 htim->Instance->SMCR &= ~TIM_SMCR_TS;
<> 144:ef7eb2e8f9f7 1589 htim->Instance->SMCR |= InputTrigger;
<> 144:ef7eb2e8f9f7 1590 }
<> 144:ef7eb2e8f9f7 1591
<> 144:ef7eb2e8f9f7 1592 /* Select the Capture Compare preload feature */
<> 144:ef7eb2e8f9f7 1593 htim->Instance->CR2 |= TIM_CR2_CCPC;
<> 144:ef7eb2e8f9f7 1594 /* Select the Commutation event source */
<> 144:ef7eb2e8f9f7 1595 htim->Instance->CR2 &= ~TIM_CR2_CCUS;
<> 144:ef7eb2e8f9f7 1596 htim->Instance->CR2 |= CommutationSource;
<> 144:ef7eb2e8f9f7 1597
<> 144:ef7eb2e8f9f7 1598 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1599 /* Set the DMA Commutation Callback */
<> 144:ef7eb2e8f9f7 1600 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferCpltCallback = TIMEx_DMACommutationCplt;
<> 144:ef7eb2e8f9f7 1601 /* Set the DMA error callback */
<> 144:ef7eb2e8f9f7 1602 htim->hdma[TIM_DMA_ID_COMMUTATION]->XferErrorCallback = TIM_DMAError;
<> 144:ef7eb2e8f9f7 1603
<> 144:ef7eb2e8f9f7 1604 /* Enable the Commutation DMA Request */
<> 144:ef7eb2e8f9f7 1605 __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_COM);
<> 144:ef7eb2e8f9f7 1606
<> 144:ef7eb2e8f9f7 1607 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1608
<> 144:ef7eb2e8f9f7 1609 return HAL_OK;
<> 144:ef7eb2e8f9f7 1610 }
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /**
<> 144:ef7eb2e8f9f7 1613 * @brief Configures the TIM in master mode.
<> 144:ef7eb2e8f9f7 1614 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1615 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1616 * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
<> 144:ef7eb2e8f9f7 1617 * contains the selected trigger output (TRGO) and the Master/Slave
<> 144:ef7eb2e8f9f7 1618 * mode.
<> 144:ef7eb2e8f9f7 1619 * @retval HAL status
<> 144:ef7eb2e8f9f7 1620 */
<> 144:ef7eb2e8f9f7 1621 HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
<> 144:ef7eb2e8f9f7 1622 {
<> 144:ef7eb2e8f9f7 1623 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1624 assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1625 assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
<> 144:ef7eb2e8f9f7 1626 assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
<> 144:ef7eb2e8f9f7 1627
<> 144:ef7eb2e8f9f7 1628 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1629
<> 144:ef7eb2e8f9f7 1630 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1631
<> 144:ef7eb2e8f9f7 1632 /* Reset the MMS Bits */
<> 144:ef7eb2e8f9f7 1633 htim->Instance->CR2 &= ~TIM_CR2_MMS;
<> 144:ef7eb2e8f9f7 1634 /* Select the TRGO source */
<> 144:ef7eb2e8f9f7 1635 htim->Instance->CR2 |= sMasterConfig->MasterOutputTrigger;
<> 144:ef7eb2e8f9f7 1636
<> 144:ef7eb2e8f9f7 1637 /* Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1638 htim->Instance->SMCR &= ~TIM_SMCR_MSM;
<> 144:ef7eb2e8f9f7 1639 /* Set or Reset the MSM Bit */
<> 144:ef7eb2e8f9f7 1640 htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
<> 144:ef7eb2e8f9f7 1641
<> 144:ef7eb2e8f9f7 1642 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1643
<> 144:ef7eb2e8f9f7 1644 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1645
<> 144:ef7eb2e8f9f7 1646 return HAL_OK;
<> 144:ef7eb2e8f9f7 1647 }
<> 144:ef7eb2e8f9f7 1648
<> 144:ef7eb2e8f9f7 1649 /**
<> 144:ef7eb2e8f9f7 1650 * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
<> 144:ef7eb2e8f9f7 1651 * and the AOE(automatic output enable).
<> 144:ef7eb2e8f9f7 1652 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1653 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1654 * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
<> 144:ef7eb2e8f9f7 1655 * contains the BDTR Register configuration information for the TIM peripheral.
<> 144:ef7eb2e8f9f7 1656 * @retval HAL status
<> 144:ef7eb2e8f9f7 1657 */
<> 144:ef7eb2e8f9f7 1658 HAL_StatusTypeDef HAL_TIMEx_ConfigBreakDeadTime(TIM_HandleTypeDef *htim,
<> 144:ef7eb2e8f9f7 1659 TIM_BreakDeadTimeConfigTypeDef * sBreakDeadTimeConfig)
<> 144:ef7eb2e8f9f7 1660 {
<> 144:ef7eb2e8f9f7 1661 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1662 assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1663 assert_param(IS_TIM_OSSR_STATE(sBreakDeadTimeConfig->OffStateRunMode));
<> 144:ef7eb2e8f9f7 1664 assert_param(IS_TIM_OSSI_STATE(sBreakDeadTimeConfig->OffStateIDLEMode));
<> 144:ef7eb2e8f9f7 1665 assert_param(IS_TIM_LOCK_LEVEL(sBreakDeadTimeConfig->LockLevel));
<> 144:ef7eb2e8f9f7 1666 assert_param(IS_TIM_BREAK_STATE(sBreakDeadTimeConfig->BreakState));
<> 144:ef7eb2e8f9f7 1667 assert_param(IS_TIM_BREAK_POLARITY(sBreakDeadTimeConfig->BreakPolarity));
<> 144:ef7eb2e8f9f7 1668 assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(sBreakDeadTimeConfig->AutomaticOutput));
<> 144:ef7eb2e8f9f7 1669 assert_param(IS_TIM_DEADTIME(sBreakDeadTimeConfig->DeadTime));
<> 144:ef7eb2e8f9f7 1670
<> 144:ef7eb2e8f9f7 1671 /* Process Locked */
<> 144:ef7eb2e8f9f7 1672 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1673
<> 144:ef7eb2e8f9f7 1674 htim->State = HAL_TIM_STATE_BUSY;
<> 144:ef7eb2e8f9f7 1675
<> 144:ef7eb2e8f9f7 1676 /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
<> 144:ef7eb2e8f9f7 1677 the OSSI State, the dead time value and the Automatic Output Enable Bit */
<> 144:ef7eb2e8f9f7 1678 htim->Instance->BDTR = (uint32_t)sBreakDeadTimeConfig->OffStateRunMode |
<> 144:ef7eb2e8f9f7 1679 sBreakDeadTimeConfig->OffStateIDLEMode |
<> 144:ef7eb2e8f9f7 1680 sBreakDeadTimeConfig->LockLevel |
<> 144:ef7eb2e8f9f7 1681 sBreakDeadTimeConfig->DeadTime |
<> 144:ef7eb2e8f9f7 1682 sBreakDeadTimeConfig->BreakState |
<> 144:ef7eb2e8f9f7 1683 sBreakDeadTimeConfig->BreakPolarity |
<> 144:ef7eb2e8f9f7 1684 sBreakDeadTimeConfig->AutomaticOutput;
<> 144:ef7eb2e8f9f7 1685
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1688
<> 144:ef7eb2e8f9f7 1689 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1690
<> 144:ef7eb2e8f9f7 1691 return HAL_OK;
<> 144:ef7eb2e8f9f7 1692 }
<> 144:ef7eb2e8f9f7 1693
<> 144:ef7eb2e8f9f7 1694 /**
<> 144:ef7eb2e8f9f7 1695 * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
<> 144:ef7eb2e8f9f7 1696 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1697 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1698 * @param Remap: specifies the TIM input remapping source.
<> 144:ef7eb2e8f9f7 1699 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1700 * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
<> 144:ef7eb2e8f9f7 1701 * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
<> 144:ef7eb2e8f9f7 1702 * @arg TIM_TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF.
<> 144:ef7eb2e8f9f7 1703 * @arg TIM_TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF.
<> 144:ef7eb2e8f9f7 1704 * @arg TIM_TIM5_GPIO: TIM5 CH4 input is connected to dedicated Timer pin(default)
<> 144:ef7eb2e8f9f7 1705 * @arg TIM_TIM5_LSI: TIM5 CH4 input is connected to LSI clock.
<> 144:ef7eb2e8f9f7 1706 * @arg TIM_TIM5_LSE: TIM5 CH4 input is connected to LSE clock.
<> 144:ef7eb2e8f9f7 1707 * @arg TIM_TIM5_RTC: TIM5 CH4 input is connected to RTC Output event.
<> 144:ef7eb2e8f9f7 1708 * @arg TIM_TIM11_GPIO: TIM11 CH4 input is connected to dedicated Timer pin(default)
<> 144:ef7eb2e8f9f7 1709 * @arg TIM_TIM11_HSE: TIM11 CH4 input is connected to HSE_RTC clock
<> 144:ef7eb2e8f9f7 1710 * (HSE divided by a programmable prescaler)
<> 144:ef7eb2e8f9f7 1711 * @retval HAL status
<> 144:ef7eb2e8f9f7 1712 */
<> 144:ef7eb2e8f9f7 1713 HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
<> 144:ef7eb2e8f9f7 1714 {
<> 144:ef7eb2e8f9f7 1715 __HAL_LOCK(htim);
<> 144:ef7eb2e8f9f7 1716
<> 144:ef7eb2e8f9f7 1717 /* Check parameters */
<> 144:ef7eb2e8f9f7 1718 assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
<> 144:ef7eb2e8f9f7 1719 assert_param(IS_TIM_REMAP(Remap));
<> 144:ef7eb2e8f9f7 1720
<> 144:ef7eb2e8f9f7 1721 /* Set the Timer remapping configuration */
<> 144:ef7eb2e8f9f7 1722 htim->Instance->OR = Remap;
<> 144:ef7eb2e8f9f7 1723
<> 144:ef7eb2e8f9f7 1724 htim->State = HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1725
<> 144:ef7eb2e8f9f7 1726 __HAL_UNLOCK(htim);
<> 144:ef7eb2e8f9f7 1727
<> 144:ef7eb2e8f9f7 1728 return HAL_OK;
<> 144:ef7eb2e8f9f7 1729 }
<> 144:ef7eb2e8f9f7 1730
<> 144:ef7eb2e8f9f7 1731 /**
<> 144:ef7eb2e8f9f7 1732 * @}
<> 144:ef7eb2e8f9f7 1733 */
<> 144:ef7eb2e8f9f7 1734
<> 144:ef7eb2e8f9f7 1735 /** @defgroup TIMEx_Exported_Functions_Group6 Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1736 * @brief Extension Callbacks functions
<> 144:ef7eb2e8f9f7 1737 *
<> 144:ef7eb2e8f9f7 1738 @verbatim
<> 144:ef7eb2e8f9f7 1739 ==============================================================================
<> 144:ef7eb2e8f9f7 1740 ##### Extension Callbacks functions #####
<> 144:ef7eb2e8f9f7 1741 ==============================================================================
<> 144:ef7eb2e8f9f7 1742 [..]
<> 144:ef7eb2e8f9f7 1743 This section provides Extension TIM callback functions:
<> 144:ef7eb2e8f9f7 1744 (+) Timer Commutation callback
<> 144:ef7eb2e8f9f7 1745 (+) Timer Break callback
<> 144:ef7eb2e8f9f7 1746
<> 144:ef7eb2e8f9f7 1747 @endverbatim
<> 144:ef7eb2e8f9f7 1748 * @{
<> 144:ef7eb2e8f9f7 1749 */
<> 144:ef7eb2e8f9f7 1750
<> 144:ef7eb2e8f9f7 1751 /**
<> 144:ef7eb2e8f9f7 1752 * @brief Hall commutation changed callback in non blocking mode
<> 144:ef7eb2e8f9f7 1753 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1754 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1755 * @retval None
<> 144:ef7eb2e8f9f7 1756 */
<> 144:ef7eb2e8f9f7 1757 __weak void HAL_TIMEx_CommutationCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1758 {
<> 144:ef7eb2e8f9f7 1759 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1760 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1761 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1762 the HAL_TIMEx_CommutationCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1763 */
<> 144:ef7eb2e8f9f7 1764 }
<> 144:ef7eb2e8f9f7 1765
<> 144:ef7eb2e8f9f7 1766 /**
<> 144:ef7eb2e8f9f7 1767 * @brief Hall Break detection callback in non blocking mode
<> 144:ef7eb2e8f9f7 1768 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1769 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1770 * @retval None
<> 144:ef7eb2e8f9f7 1771 */
<> 144:ef7eb2e8f9f7 1772 __weak void HAL_TIMEx_BreakCallback(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1773 {
<> 144:ef7eb2e8f9f7 1774 /* Prevent unused argument(s) compilation warning */
<> 144:ef7eb2e8f9f7 1775 UNUSED(htim);
<> 144:ef7eb2e8f9f7 1776 /* NOTE : This function Should not be modified, when the callback is needed,
<> 144:ef7eb2e8f9f7 1777 the HAL_TIMEx_BreakCallback could be implemented in the user file
<> 144:ef7eb2e8f9f7 1778 */
<> 144:ef7eb2e8f9f7 1779 }
<> 144:ef7eb2e8f9f7 1780 /**
<> 144:ef7eb2e8f9f7 1781 * @}
<> 144:ef7eb2e8f9f7 1782 */
<> 144:ef7eb2e8f9f7 1783
<> 144:ef7eb2e8f9f7 1784 /** @defgroup TIMEx_Exported_Functions_Group7 Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1785 * @brief Extension Peripheral State functions
<> 144:ef7eb2e8f9f7 1786 *
<> 144:ef7eb2e8f9f7 1787 @verbatim
<> 144:ef7eb2e8f9f7 1788 ==============================================================================
<> 144:ef7eb2e8f9f7 1789 ##### Extension Peripheral State functions #####
<> 144:ef7eb2e8f9f7 1790 ==============================================================================
<> 144:ef7eb2e8f9f7 1791 [..]
<> 144:ef7eb2e8f9f7 1792 This subsection permits to get in run-time the status of the peripheral
<> 144:ef7eb2e8f9f7 1793 and the data flow.
<> 144:ef7eb2e8f9f7 1794
<> 144:ef7eb2e8f9f7 1795 @endverbatim
<> 144:ef7eb2e8f9f7 1796 * @{
<> 144:ef7eb2e8f9f7 1797 */
<> 144:ef7eb2e8f9f7 1798
<> 144:ef7eb2e8f9f7 1799 /**
<> 144:ef7eb2e8f9f7 1800 * @brief Return the TIM Hall Sensor interface state
<> 144:ef7eb2e8f9f7 1801 * @param htim: pointer to a TIM_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1802 * the configuration information for TIM module.
<> 144:ef7eb2e8f9f7 1803 * @retval HAL state
<> 144:ef7eb2e8f9f7 1804 */
<> 144:ef7eb2e8f9f7 1805 HAL_TIM_StateTypeDef HAL_TIMEx_HallSensor_GetState(TIM_HandleTypeDef *htim)
<> 144:ef7eb2e8f9f7 1806 {
<> 144:ef7eb2e8f9f7 1807 return htim->State;
<> 144:ef7eb2e8f9f7 1808 }
<> 144:ef7eb2e8f9f7 1809
<> 144:ef7eb2e8f9f7 1810 /**
<> 144:ef7eb2e8f9f7 1811 * @}
<> 144:ef7eb2e8f9f7 1812 */
<> 144:ef7eb2e8f9f7 1813
<> 144:ef7eb2e8f9f7 1814 /**
<> 144:ef7eb2e8f9f7 1815 * @brief TIM DMA Commutation callback.
<> 144:ef7eb2e8f9f7 1816 * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
<> 144:ef7eb2e8f9f7 1817 * the configuration information for the specified DMA module.
<> 144:ef7eb2e8f9f7 1818 * @retval None
<> 144:ef7eb2e8f9f7 1819 */
<> 144:ef7eb2e8f9f7 1820 void TIMEx_DMACommutationCplt(DMA_HandleTypeDef *hdma)
<> 144:ef7eb2e8f9f7 1821 {
<> 144:ef7eb2e8f9f7 1822 TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 htim->State= HAL_TIM_STATE_READY;
<> 144:ef7eb2e8f9f7 1825
<> 144:ef7eb2e8f9f7 1826 HAL_TIMEx_CommutationCallback(htim);
<> 144:ef7eb2e8f9f7 1827 }
<> 144:ef7eb2e8f9f7 1828 /**
<> 144:ef7eb2e8f9f7 1829 * @}
<> 144:ef7eb2e8f9f7 1830 */
<> 144:ef7eb2e8f9f7 1831
<> 144:ef7eb2e8f9f7 1832 /**
<> 144:ef7eb2e8f9f7 1833 * @brief Enables or disables the TIM Capture Compare Channel xN.
<> 144:ef7eb2e8f9f7 1834 * @param TIMx to select the TIM peripheral
<> 144:ef7eb2e8f9f7 1835 * @param Channel: specifies the TIM Channel
<> 144:ef7eb2e8f9f7 1836 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1837 * @arg TIM_Channel_1: TIM Channel 1
<> 144:ef7eb2e8f9f7 1838 * @arg TIM_Channel_2: TIM Channel 2
<> 144:ef7eb2e8f9f7 1839 * @arg TIM_Channel_3: TIM Channel 3
<> 144:ef7eb2e8f9f7 1840 * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
<> 144:ef7eb2e8f9f7 1841 * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
<> 144:ef7eb2e8f9f7 1842 * @retval None
<> 144:ef7eb2e8f9f7 1843 */
<> 144:ef7eb2e8f9f7 1844 static void TIM_CCxNChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelNState)
<> 144:ef7eb2e8f9f7 1845 {
<> 144:ef7eb2e8f9f7 1846 uint32_t tmp = 0U;
<> 144:ef7eb2e8f9f7 1847
<> 144:ef7eb2e8f9f7 1848 /* Check the parameters */
<> 144:ef7eb2e8f9f7 1849 assert_param(IS_TIM_CC4_INSTANCE(TIMx));
<> 144:ef7eb2e8f9f7 1850 assert_param(IS_TIM_COMPLEMENTARY_CHANNELS(Channel));
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 tmp = TIM_CCER_CC1NE << Channel;
<> 144:ef7eb2e8f9f7 1853
<> 144:ef7eb2e8f9f7 1854 /* Reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1855 TIMx->CCER &= ~tmp;
<> 144:ef7eb2e8f9f7 1856
<> 144:ef7eb2e8f9f7 1857 /* Set or reset the CCxNE Bit */
<> 144:ef7eb2e8f9f7 1858 TIMx->CCER |= (uint32_t)(ChannelNState << Channel);
<> 144:ef7eb2e8f9f7 1859 }
<> 144:ef7eb2e8f9f7 1860
<> 144:ef7eb2e8f9f7 1861 /**
<> 144:ef7eb2e8f9f7 1862 * @}
<> 144:ef7eb2e8f9f7 1863 */
<> 144:ef7eb2e8f9f7 1864
<> 144:ef7eb2e8f9f7 1865 #endif /* HAL_TIM_MODULE_ENABLED */
<> 144:ef7eb2e8f9f7 1866 /**
<> 144:ef7eb2e8f9f7 1867 * @}
<> 144:ef7eb2e8f9f7 1868 */
<> 144:ef7eb2e8f9f7 1869
<> 144:ef7eb2e8f9f7 1870 /**
<> 144:ef7eb2e8f9f7 1871 * @}
<> 144:ef7eb2e8f9f7 1872 */
<> 144:ef7eb2e8f9f7 1873 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/