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targets/TARGET_Maxim/TARGET_MAX32625/device/max32625.h@150:02e0a0aed4ec, 2016-11-08 (annotated)

Committer:
<>
Date:
Tue Nov 08 17:45:16 2016 +0000
Revision:
150:02e0a0aed4ec
This updates the lib to the mbed lib v129

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 ******************************************************************************/
<> 150:02e0a0aed4ec 32
<> 150:02e0a0aed4ec 33 #ifndef _MAX32625_H_
<> 150:02e0a0aed4ec 34 #define _MAX32625_H_
<> 150:02e0a0aed4ec 35
<> 150:02e0a0aed4ec 36 #include <stdint.h>
<> 150:02e0a0aed4ec 37
<> 150:02e0a0aed4ec 38 #ifndef FALSE
<> 150:02e0a0aed4ec 39 #define FALSE (0)
<> 150:02e0a0aed4ec 40 #endif
<> 150:02e0a0aed4ec 41
<> 150:02e0a0aed4ec 42 #ifndef TRUE
<> 150:02e0a0aed4ec 43 #define TRUE (1)
<> 150:02e0a0aed4ec 44 #endif
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 /* COMPILER SPECIFIC DEFINES (IAR, ARMCC and GNUC) */
<> 150:02e0a0aed4ec 47 #if defined ( __GNUC__ )
<> 150:02e0a0aed4ec 48 #define __weak __attribute__((weak))
<> 150:02e0a0aed4ec 49
<> 150:02e0a0aed4ec 50 #elif defined ( __CC_ARM)
<> 150:02e0a0aed4ec 51
<> 150:02e0a0aed4ec 52 #define inline __inline
<> 150:02e0a0aed4ec 53 #pragma anon_unions
<> 150:02e0a0aed4ec 54
<> 150:02e0a0aed4ec 55 #endif
<> 150:02e0a0aed4ec 56
<> 150:02e0a0aed4ec 57 typedef enum {
<> 150:02e0a0aed4ec 58 NonMaskableInt_IRQn = -14,
<> 150:02e0a0aed4ec 59 HardFault_IRQn = -13,
<> 150:02e0a0aed4ec 60 MemoryManagement_IRQn = -12,
<> 150:02e0a0aed4ec 61 BusFault_IRQn = -11,
<> 150:02e0a0aed4ec 62 UsageFault_IRQn = -10,
<> 150:02e0a0aed4ec 63 SVCall_IRQn = -5,
<> 150:02e0a0aed4ec 64 DebugMonitor_IRQn = -4,
<> 150:02e0a0aed4ec 65 PendSV_IRQn = -2,
<> 150:02e0a0aed4ec 66 SysTick_IRQn = -1,
<> 150:02e0a0aed4ec 67
<> 150:02e0a0aed4ec 68 /* Device-specific interrupt sources (external to ARM core) */
<> 150:02e0a0aed4ec 69 /* table entry number */
<> 150:02e0a0aed4ec 70 /* |||| */
<> 150:02e0a0aed4ec 71 /* |||| table offset address */
<> 150:02e0a0aed4ec 72 /* vvvv vvvvvv */
<> 150:02e0a0aed4ec 73
<> 150:02e0a0aed4ec 74 CLKMAN_IRQn = 0, /* 0x10 0x0040,CLKMAN */
<> 150:02e0a0aed4ec 75 PWRMAN_IRQn = 1, /* 0x11 0x0044 PWRMAN */
<> 150:02e0a0aed4ec 76 FLC_IRQn = 2, /* 0x12 0x0048 Flash Controller */
<> 150:02e0a0aed4ec 77 RTC0_IRQn = 3, /* 0x13 0x004C RTC Counter match with Compare 0 */
<> 150:02e0a0aed4ec 78 RTC1_IRQn = 4, /* 0x14 0x0050 RTC Counter match with Compare 1 */
<> 150:02e0a0aed4ec 79 RTC2_IRQn = 5, /* 0x15 0x0054 RTC Prescaler interval compare match */
<> 150:02e0a0aed4ec 80 RTC3_IRQn = 6, /* 0x16 0x0058 RTC Overflow */
<> 150:02e0a0aed4ec 81 PMU_IRQn = 7, /* 0x17 0x005C Peripheral Management Unit (PMU/DMA) */
<> 150:02e0a0aed4ec 82 USB_IRQn = 8, /* 0x18 0x0060 USB */
<> 150:02e0a0aed4ec 83 AES_IRQn = 9, /* 0x19 0x0064 AES */
<> 150:02e0a0aed4ec 84 MAA_IRQn = 10, /* 0x1A 0x0068 MAA */
<> 150:02e0a0aed4ec 85 WDT0_IRQn = 11, /* 0x1B 0x006C Watchdog 0 timeout */
<> 150:02e0a0aed4ec 86 WDT0_P_IRQn = 12, /* 0x1C 0x0070 Watchdog 0 pre-window (fed too early) */
<> 150:02e0a0aed4ec 87 WDT1_IRQn = 13, /* 0x1D 0x0074 Watchdog 1 timeout */
<> 150:02e0a0aed4ec 88 WDT1_P_IRQn = 14, /* 0x1E 0x0078 Watchdog 1 pre-window (fed too early) */
<> 150:02e0a0aed4ec 89 GPIO_P0_IRQn = 15, /* 0x1F 0x007C GPIO Port 0 */
<> 150:02e0a0aed4ec 90 GPIO_P1_IRQn = 16, /* 0x20 0x0080 GPIO Port 1 */
<> 150:02e0a0aed4ec 91 GPIO_P2_IRQn = 17, /* 0x21 0x0084 GPIO Port 2 */
<> 150:02e0a0aed4ec 92 GPIO_P3_IRQn = 18, /* 0x22 0x0088 GPIO Port 3 */
<> 150:02e0a0aed4ec 93 GPIO_P4_IRQn = 19, /* 0x23 0x008C GPIO Port 4 */
<> 150:02e0a0aed4ec 94 GPIO_P5_IRQn = 20, /* 0x24 0x0090 GPIO Port 5 (Unused) */
<> 150:02e0a0aed4ec 95 GPIO_P6_IRQn = 21, /* 0x25 0x0094 GPIO Port 6 (Unused) */
<> 150:02e0a0aed4ec 96 TMR0_0_IRQn = 22, /* 0x26 0x0098 Timer 0 (32-bit, 16-bit #0) */
<> 150:02e0a0aed4ec 97 TMR0_1_IRQn = 23, /* 0x27 0x009C Timer 0 (16-bit #1) */
<> 150:02e0a0aed4ec 98 TMR1_0_IRQn = 24, /* 0x28 0x00A0 Timer 1 (32-bit, 16-bit #0) */
<> 150:02e0a0aed4ec 99 TMR1_1_IRQn = 25, /* 0x29 0x00A4 Timer 1 (16-bit #1) */
<> 150:02e0a0aed4ec 100 TMR2_0_IRQn = 26, /* 0x2A 0x00A8 Timer 2 (32-bit, 16-bit #0) */
<> 150:02e0a0aed4ec 101 TMR2_1_IRQn = 27, /* 0x2B 0x00AC Timer 2 (16-bit #1) */
<> 150:02e0a0aed4ec 102 TMR3_0_IRQn = 28, /* 0x2C 0x00B0 Timer 3 (32-bit, 16-bit #0) */
<> 150:02e0a0aed4ec 103 TMR3_1_IRQn = 29, /* 0x2D 0x00B4 Timer 3 (16-bit #1) */
<> 150:02e0a0aed4ec 104 TMR4_0_IRQn = 30, /* 0x2E 0x00B8 Timer 4 (32-bit, 16-bit #0) */
<> 150:02e0a0aed4ec 105 TMR4_1_IRQn = 31, /* 0x2F 0x00BC Timer 4 (16-bit #1) */
<> 150:02e0a0aed4ec 106 TMR5_0_IRQn = 32, /* 0x30 0x00C0 Timer 5 (32-bit, 16-bit #0) */
<> 150:02e0a0aed4ec 107 TMR5_1_IRQn = 33, /* 0x31 0x00C4 Timer 5 (16-bit #1) */
<> 150:02e0a0aed4ec 108 UART0_IRQn = 34, /* 0x32 0x00C8 UART 0 */
<> 150:02e0a0aed4ec 109 UART1_IRQn = 35, /* 0x33 0x00CC UART 1 */
<> 150:02e0a0aed4ec 110 UART2_IRQn = 36, /* 0x34 0x00D0 UART 2 */
<> 150:02e0a0aed4ec 111 UART3_IRQn = 37, /* 0x35 0x00D4 UART 3 (Unused) */
<> 150:02e0a0aed4ec 112 PT_IRQn = 38, /* 0x36 0x00D8 Pulse Trains */
<> 150:02e0a0aed4ec 113 I2CM0_IRQn = 39, /* 0x37 0x00DC I2C Master 0 */
<> 150:02e0a0aed4ec 114 I2CM1_IRQn = 40, /* 0x38 0x00E0 I2C Master 1 */
<> 150:02e0a0aed4ec 115 I2CM2_IRQn = 41, /* 0x39 0x00E4 I2C Master 2 (Unused) */
<> 150:02e0a0aed4ec 116 I2CS_IRQn = 42, /* 0x3A 0x00E8 I2C Slave */
<> 150:02e0a0aed4ec 117 SPIM0_IRQn = 43, /* 0x3B 0x00EC SPI Master 0 */
<> 150:02e0a0aed4ec 118 SPIM1_IRQn = 44, /* 0x3C 0x00F0 SPI Master 1 */
<> 150:02e0a0aed4ec 119 SPIM2_IRQn = 45, /* 0x3D 0x00F4 SPI Master 2 */
<> 150:02e0a0aed4ec 120 SPIB_IRQn = 46, /* 0x3E 0x00F8 SPI Bridge (Unused) */
<> 150:02e0a0aed4ec 121 OWM_IRQn = 47, /* 0x3F 0x00FC 1-Wire Master */
<> 150:02e0a0aed4ec 122 AFE_IRQn = 48, /* 0x40 0x0100 Analog Front End, ADC */
<> 150:02e0a0aed4ec 123 SPIS_IRQn = 49, /* 0x41 0x0104 SPI Slave */
<> 150:02e0a0aed4ec 124 MXC_IRQ_EXT_COUNT,
<> 150:02e0a0aed4ec 125 } IRQn_Type;
<> 150:02e0a0aed4ec 126
<> 150:02e0a0aed4ec 127 #define MXC_IRQ_COUNT (MXC_IRQ_EXT_COUNT + 16)
<> 150:02e0a0aed4ec 128
<> 150:02e0a0aed4ec 129
<> 150:02e0a0aed4ec 130 /* ================================================================================ */
<> 150:02e0a0aed4ec 131 /* ================ Processor and Core Peripheral Section ================ */
<> 150:02e0a0aed4ec 132 /* ================================================================================ */
<> 150:02e0a0aed4ec 133
<> 150:02e0a0aed4ec 134 /* ---------------------- Configuration of the Cortex-M Processor and Core Peripherals ---------------------- */
<> 150:02e0a0aed4ec 135 #define __CM4_REV 0x0100 /*!< Cortex-M4 Core Revision */
<> 150:02e0a0aed4ec 136 #define __MPU_PRESENT 0 /*!< MPU present or not */
<> 150:02e0a0aed4ec 137 #define __NVIC_PRIO_BITS 3 /*!< Number of Bits used for Priority Levels */
<> 150:02e0a0aed4ec 138 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
<> 150:02e0a0aed4ec 139 #define __FPU_PRESENT 1 /*!< FPU present or not */
<> 150:02e0a0aed4ec 140
<> 150:02e0a0aed4ec 141 #include <core_cm4.h> /*!< Cortex-M4 processor and core peripherals */
<> 150:02e0a0aed4ec 142 #include "system_max32625.h" /*!< System Header */
<> 150:02e0a0aed4ec 143
<> 150:02e0a0aed4ec 144
<> 150:02e0a0aed4ec 145 /* ================================================================================ */
<> 150:02e0a0aed4ec 146 /* ================== Device Specific Memory Section ================== */
<> 150:02e0a0aed4ec 147 /* ================================================================================ */
<> 150:02e0a0aed4ec 148
<> 150:02e0a0aed4ec 149 #define MXC_FLASH_MEM_BASE 0x00000000UL
<> 150:02e0a0aed4ec 150 #define MXC_FLASH_PAGE_SIZE 0x00002000UL
<> 150:02e0a0aed4ec 151 #define MXC_FLASH_FULL_MEM_SIZE 0x00080000UL
<> 150:02e0a0aed4ec 152 #define MXC_SYS_MEM_BASE 0x20000000UL
<> 150:02e0a0aed4ec 153 #define MXC_SRAM_FULL_MEM_SIZE 0x00028000UL
<> 150:02e0a0aed4ec 154 #define MXC_EXT_FLASH_MEM_BASE 0x10000000UL
<> 150:02e0a0aed4ec 155
<> 150:02e0a0aed4ec 156 /* ================================================================================ */
<> 150:02e0a0aed4ec 157 /* ================ Device Specific Peripheral Section ================ */
<> 150:02e0a0aed4ec 158 /* ================================================================================ */
<> 150:02e0a0aed4ec 159
<> 150:02e0a0aed4ec 160
<> 150:02e0a0aed4ec 161 /*
<> 150:02e0a0aed4ec 162 Base addresses and configuration settings for all MAX32625 peripheral modules.
<> 150:02e0a0aed4ec 163 */
<> 150:02e0a0aed4ec 164
<> 150:02e0a0aed4ec 165
<> 150:02e0a0aed4ec 166 /*******************************************************************************/
<> 150:02e0a0aed4ec 167 /* System Manager Settings */
<> 150:02e0a0aed4ec 168
<> 150:02e0a0aed4ec 169 #define MXC_BASE_SYSMAN ((uint32_t)0x40000000UL)
<> 150:02e0a0aed4ec 170 #define MXC_SYSMAN ((mxc_sysman_regs_t *)MXC_BASE_SYSMAN)
<> 150:02e0a0aed4ec 171
<> 150:02e0a0aed4ec 172
<> 150:02e0a0aed4ec 173
<> 150:02e0a0aed4ec 174 /*******************************************************************************/
<> 150:02e0a0aed4ec 175 /* System Clock Manager */
<> 150:02e0a0aed4ec 176
<> 150:02e0a0aed4ec 177 #define MXC_BASE_CLKMAN ((uint32_t)0x40000400UL)
<> 150:02e0a0aed4ec 178 #define MXC_CLKMAN ((mxc_clkman_regs_t *)MXC_BASE_CLKMAN)
<> 150:02e0a0aed4ec 179
<> 150:02e0a0aed4ec 180
<> 150:02e0a0aed4ec 181
<> 150:02e0a0aed4ec 182 /*******************************************************************************/
<> 150:02e0a0aed4ec 183 /* System Power Manager */
<> 150:02e0a0aed4ec 184
<> 150:02e0a0aed4ec 185 #define MXC_BASE_PWRMAN ((uint32_t)0x40000800UL)
<> 150:02e0a0aed4ec 186 #define MXC_PWRMAN ((mxc_pwrman_regs_t *)MXC_BASE_PWRMAN)
<> 150:02e0a0aed4ec 187
<> 150:02e0a0aed4ec 188
<> 150:02e0a0aed4ec 189
<> 150:02e0a0aed4ec 190 /*******************************************************************************/
<> 150:02e0a0aed4ec 191 /* Real Time Clock */
<> 150:02e0a0aed4ec 192
<> 150:02e0a0aed4ec 193 #define MXC_BASE_RTCTMR ((uint32_t)0x40000A00UL)
<> 150:02e0a0aed4ec 194 #define MXC_RTCTMR ((mxc_rtctmr_regs_t *)MXC_BASE_RTCTMR)
<> 150:02e0a0aed4ec 195 #define MXC_BASE_RTCCFG ((uint32_t)0x40000A70UL)
<> 150:02e0a0aed4ec 196 #define MXC_RTCCFG ((mxc_rtccfg_regs_t *)MXC_BASE_RTCCFG)
<> 150:02e0a0aed4ec 197
<> 150:02e0a0aed4ec 198 #define MXC_RTCTMR_GET_IRQ(i) (IRQn_Type)((i) == 0 ? RTC0_IRQn : \
<> 150:02e0a0aed4ec 199 (i) == 1 ? RTC1_IRQn : \
<> 150:02e0a0aed4ec 200 (i) == 2 ? RTC2_IRQn : \
<> 150:02e0a0aed4ec 201 (i) == 3 ? RTC3_IRQn : 0)
<> 150:02e0a0aed4ec 202
<> 150:02e0a0aed4ec 203
<> 150:02e0a0aed4ec 204
<> 150:02e0a0aed4ec 205 /*******************************************************************************/
<> 150:02e0a0aed4ec 206 /* Power Sequencer */
<> 150:02e0a0aed4ec 207
<> 150:02e0a0aed4ec 208 #define MXC_BASE_PWRSEQ ((uint32_t)0x40000A30UL)
<> 150:02e0a0aed4ec 209 #define MXC_PWRSEQ ((mxc_pwrseq_regs_t *)MXC_BASE_PWRSEQ)
<> 150:02e0a0aed4ec 210
<> 150:02e0a0aed4ec 211
<> 150:02e0a0aed4ec 212
<> 150:02e0a0aed4ec 213 /*******************************************************************************/
<> 150:02e0a0aed4ec 214 /* System I/O Manager */
<> 150:02e0a0aed4ec 215
<> 150:02e0a0aed4ec 216 #define MXC_BASE_IOMAN ((uint32_t)0x40000C00UL)
<> 150:02e0a0aed4ec 217 #define MXC_IOMAN ((mxc_ioman_regs_t *)MXC_BASE_IOMAN)
<> 150:02e0a0aed4ec 218
<> 150:02e0a0aed4ec 219
<> 150:02e0a0aed4ec 220
<> 150:02e0a0aed4ec 221 /*******************************************************************************/
<> 150:02e0a0aed4ec 222 /* Shadow Trim Registers */
<> 150:02e0a0aed4ec 223
<> 150:02e0a0aed4ec 224 #define MXC_BASE_TRIM ((uint32_t)0x40001000UL)
<> 150:02e0a0aed4ec 225 #define MXC_TRIM ((mxc_trim_regs_t *)MXC_BASE_TRIM)
<> 150:02e0a0aed4ec 226
<> 150:02e0a0aed4ec 227
<> 150:02e0a0aed4ec 228
<> 150:02e0a0aed4ec 229 /*******************************************************************************/
<> 150:02e0a0aed4ec 230 /* Flash Controller */
<> 150:02e0a0aed4ec 231
<> 150:02e0a0aed4ec 232 #define MXC_BASE_FLC ((uint32_t)0x40002000UL)
<> 150:02e0a0aed4ec 233 #define MXC_FLC ((mxc_flc_regs_t *)MXC_BASE_FLC)
<> 150:02e0a0aed4ec 234
<> 150:02e0a0aed4ec 235 #define MXC_FLC_PAGE_SIZE_SHIFT (13)
<> 150:02e0a0aed4ec 236 #define MXC_FLC_PAGE_SIZE (1 << MXC_FLC_PAGE_SIZE_SHIFT)
<> 150:02e0a0aed4ec 237 #define MXC_FLC_PAGE_ERASE_MSK ((~(1 << (MXC_FLC_PAGE_SIZE_SHIFT - 1))) >> MXC_FLC_PAGE_SIZE_SHIFT) << MXC_FLC_PAGE_SIZE_SHIFT
<> 150:02e0a0aed4ec 238
<> 150:02e0a0aed4ec 239
<> 150:02e0a0aed4ec 240
<> 150:02e0a0aed4ec 241 /*******************************************************************************/
<> 150:02e0a0aed4ec 242 /* Instruction Cache */
<> 150:02e0a0aed4ec 243
<> 150:02e0a0aed4ec 244 #define MXC_BASE_ICC ((uint32_t)0x40003000UL)
<> 150:02e0a0aed4ec 245 #define MXC_ICC ((mxc_icc_regs_t *)MXC_BASE_ICC)
<> 150:02e0a0aed4ec 246
<> 150:02e0a0aed4ec 247
<> 150:02e0a0aed4ec 248
<> 150:02e0a0aed4ec 249 /*******************************************************************************/
<> 150:02e0a0aed4ec 250 /* SPI XIP Interface */
<> 150:02e0a0aed4ec 251
<> 150:02e0a0aed4ec 252 #define MXC_BASE_SPIX ((uint32_t)0x40004000UL)
<> 150:02e0a0aed4ec 253 #define MXC_SPIX ((mxc_spix_regs_t *)MXC_BASE_SPIX)
<> 150:02e0a0aed4ec 254
<> 150:02e0a0aed4ec 255
<> 150:02e0a0aed4ec 256
<> 150:02e0a0aed4ec 257 /*******************************************************************************/
<> 150:02e0a0aed4ec 258 /* Peripheral Management Unit */
<> 150:02e0a0aed4ec 259
<> 150:02e0a0aed4ec 260 #define MXC_CFG_PMU_CHANNELS (6)
<> 150:02e0a0aed4ec 261
<> 150:02e0a0aed4ec 262 #define MXC_BASE_PMU0 ((uint32_t)0x40005000UL)
<> 150:02e0a0aed4ec 263 #define MXC_PMU0 ((mxc_pmu_regs_t *)MXC_BASE_PMU0)
<> 150:02e0a0aed4ec 264 #define MXC_BASE_PMU1 ((uint32_t)0x40005020UL)
<> 150:02e0a0aed4ec 265 #define MXC_PMU1 ((mxc_pmu_regs_t *)MXC_BASE_PMU1)
<> 150:02e0a0aed4ec 266 #define MXC_BASE_PMU2 ((uint32_t)0x40005040UL)
<> 150:02e0a0aed4ec 267 #define MXC_PMU2 ((mxc_pmu_regs_t *)MXC_BASE_PMU2)
<> 150:02e0a0aed4ec 268 #define MXC_BASE_PMU3 ((uint32_t)0x40005060UL)
<> 150:02e0a0aed4ec 269 #define MXC_PMU3 ((mxc_pmu_regs_t *)MXC_BASE_PMU3)
<> 150:02e0a0aed4ec 270 #define MXC_BASE_PMU4 ((uint32_t)0x40005080UL)
<> 150:02e0a0aed4ec 271 #define MXC_PMU4 ((mxc_pmu_regs_t *)MXC_BASE_PMU4)
<> 150:02e0a0aed4ec 272 #define MXC_BASE_PMU5 ((uint32_t)0x400050A0UL)
<> 150:02e0a0aed4ec 273 #define MXC_PMU5 ((mxc_pmu_regs_t *)MXC_BASE_PMU5)
<> 150:02e0a0aed4ec 274
<> 150:02e0a0aed4ec 275 #define MXC_PMU_GET_BASE(i) ((i) == 0 ? MXC_BASE_PMU0 : \
<> 150:02e0a0aed4ec 276 (i) == 1 ? MXC_BASE_PMU1 : \
<> 150:02e0a0aed4ec 277 (i) == 2 ? MXC_BASE_PMU2 : \
<> 150:02e0a0aed4ec 278 (i) == 3 ? MXC_BASE_PMU3 : \
<> 150:02e0a0aed4ec 279 (i) == 4 ? MXC_BASE_PMU4 : \
<> 150:02e0a0aed4ec 280 (i) == 5 ? MXC_BASE_PMU5 : 0)
<> 150:02e0a0aed4ec 281
<> 150:02e0a0aed4ec 282 #define MXC_PMU_GET_PMU(i) ((i) == 0 ? MXC_PMU0 : \
<> 150:02e0a0aed4ec 283 (i) == 1 ? MXC_PMU1 : \
<> 150:02e0a0aed4ec 284 (i) == 2 ? MXC_PMU2 : \
<> 150:02e0a0aed4ec 285 (i) == 3 ? MXC_PMU3 : \
<> 150:02e0a0aed4ec 286 (i) == 4 ? MXC_PMU4 : \
<> 150:02e0a0aed4ec 287 (i) == 5 ? MXC_PMU5 : 0)
<> 150:02e0a0aed4ec 288
<> 150:02e0a0aed4ec 289 #define MXC_PMU_GET_IDX(p) ((p) == MXC_PMU0 ? 0 : \
<> 150:02e0a0aed4ec 290 (p) == MXC_PMU1 ? 1 : \
<> 150:02e0a0aed4ec 291 (p) == MXC_PMU2 ? 2 : \
<> 150:02e0a0aed4ec 292 (p) == MXC_PMU3 ? 3 : \
<> 150:02e0a0aed4ec 293 (p) == MXC_PMU4 ? 4 : \
<> 150:02e0a0aed4ec 294 (p) == MXC_PMU5 ? 5 : -1)
<> 150:02e0a0aed4ec 295
<> 150:02e0a0aed4ec 296
<> 150:02e0a0aed4ec 297 /*******************************************************************************/
<> 150:02e0a0aed4ec 298 /* USB Device Controller */
<> 150:02e0a0aed4ec 299
<> 150:02e0a0aed4ec 300 #define MXC_BASE_USB ((uint32_t)0x40100000UL)
<> 150:02e0a0aed4ec 301 #define MXC_USB ((mxc_usb_regs_t *)MXC_BASE_USB)
<> 150:02e0a0aed4ec 302
<> 150:02e0a0aed4ec 303 #define MXC_USB_MAX_PACKET (64)
<> 150:02e0a0aed4ec 304 #define MXC_USB_NUM_EP (8)
<> 150:02e0a0aed4ec 305
<> 150:02e0a0aed4ec 306
<> 150:02e0a0aed4ec 307
<> 150:02e0a0aed4ec 308 /*******************************************************************************/
<> 150:02e0a0aed4ec 309 /* CRC-16/CRC-32 Engine */
<> 150:02e0a0aed4ec 310
<> 150:02e0a0aed4ec 311 #define MXC_BASE_CRC ((uint32_t)0x40006000UL)
<> 150:02e0a0aed4ec 312 #define MXC_CRC ((mxc_crc_regs_t *)MXC_BASE_CRC)
<> 150:02e0a0aed4ec 313 #define MXC_BASE_CRC_DATA ((uint32_t)0x40101000UL)
<> 150:02e0a0aed4ec 314 #define MXC_CRC_DATA ((mxc_crc_data_regs_t *)MXC_BASE_CRC_DATA)
<> 150:02e0a0aed4ec 315
<> 150:02e0a0aed4ec 316
<> 150:02e0a0aed4ec 317
<> 150:02e0a0aed4ec 318 /*******************************************************************************/
<> 150:02e0a0aed4ec 319 /* Pseudo-random number generator (PRNG) */
<> 150:02e0a0aed4ec 320
<> 150:02e0a0aed4ec 321 #define MXC_BASE_PRNG ((uint32_t)0x40007000UL)
<> 150:02e0a0aed4ec 322 #define MXC_PRNG ((mxc_prng_regs_t *)MXC_BASE_PRNG)
<> 150:02e0a0aed4ec 323
<> 150:02e0a0aed4ec 324 /*******************************************************************************/
<> 150:02e0a0aed4ec 325 /* AES Cryptographic Engine */
<> 150:02e0a0aed4ec 326
<> 150:02e0a0aed4ec 327 #define MXC_BASE_AES ((uint32_t)0x40007400UL)
<> 150:02e0a0aed4ec 328 #define MXC_AES ((mxc_aes_regs_t *)MXC_BASE_AES)
<> 150:02e0a0aed4ec 329 #define MXC_BASE_AES_MEM ((uint32_t)0x40102000UL)
<> 150:02e0a0aed4ec 330 #define MXC_AES_MEM ((mxc_aes_mem_regs_t *)MXC_BASE_AES_MEM)
<> 150:02e0a0aed4ec 331
<> 150:02e0a0aed4ec 332
<> 150:02e0a0aed4ec 333
<> 150:02e0a0aed4ec 334 /*******************************************************************************/
<> 150:02e0a0aed4ec 335 /* MAA Cryptographic Engine */
<> 150:02e0a0aed4ec 336
<> 150:02e0a0aed4ec 337 #define MXC_BASE_MAA ((uint32_t)0x40007800UL)
<> 150:02e0a0aed4ec 338 #define MXC_MAA ((mxc_maa_regs_t *)MXC_BASE_MAA)
<> 150:02e0a0aed4ec 339 #define MXC_BASE_MAA_MEM ((uint32_t)0x40102800UL)
<> 150:02e0a0aed4ec 340 #define MXC_MAA_MEM ((mxc_maa_mem_regs_t *)MXC_BASE_MAA_MEM)
<> 150:02e0a0aed4ec 341
<> 150:02e0a0aed4ec 342 /*******************************************************************************/
<> 150:02e0a0aed4ec 343 /* Trust Protection Unit (TPU) */
<> 150:02e0a0aed4ec 344
<> 150:02e0a0aed4ec 345 #define MXC_BASE_TPU ((uint32_t)0x40007000UL)
<> 150:02e0a0aed4ec 346 #define MXC_TPU ((mxc_tpu_regs_t *)MXC_BASE_TPU)
<> 150:02e0a0aed4ec 347 #define MXC_BASE_TPU_TSR ((uint32_t)0x40007C00UL)
<> 150:02e0a0aed4ec 348 #define MXC_TPU_TSR ((mxc_tpu_tsr_regs_t *)MXC_BASE_TPU_TSR)
<> 150:02e0a0aed4ec 349
<> 150:02e0a0aed4ec 350 /*******************************************************************************/
<> 150:02e0a0aed4ec 351 /* Watchdog Timers */
<> 150:02e0a0aed4ec 352
<> 150:02e0a0aed4ec 353 #define MXC_CFG_WDT_INSTANCES (2)
<> 150:02e0a0aed4ec 354
<> 150:02e0a0aed4ec 355 #define MXC_BASE_WDT0 ((uint32_t)0x40008000UL)
<> 150:02e0a0aed4ec 356 #define MXC_WDT0 ((mxc_wdt_regs_t *)MXC_BASE_WDT0)
<> 150:02e0a0aed4ec 357 #define MXC_BASE_WDT1 ((uint32_t)0x40009000UL)
<> 150:02e0a0aed4ec 358 #define MXC_WDT1 ((mxc_wdt_regs_t *)MXC_BASE_WDT1)
<> 150:02e0a0aed4ec 359
<> 150:02e0a0aed4ec 360 #define MXC_WDT_GET_IRQ(i) (IRQn_Type)((i) == 0 ? WDT0_IRQn : \
<> 150:02e0a0aed4ec 361 (i) == 1 ? WDT1_IRQn : 0)
<> 150:02e0a0aed4ec 362
<> 150:02e0a0aed4ec 363 #define MXC_WDT_GET_IRQ_P(i) (IRQn_Type)((i) == 0 ? WDT0_P_IRQn : \
<> 150:02e0a0aed4ec 364 (i) == 1 ? WDT1_P_IRQn : 0)
<> 150:02e0a0aed4ec 365
<> 150:02e0a0aed4ec 366 #define MXC_WDT_GET_BASE(i) ((i) == 0 ? MXC_BASE_WDT0 : \
<> 150:02e0a0aed4ec 367 (i) == 1 ? MXC_BASE_WDT1 : 0)
<> 150:02e0a0aed4ec 368
<> 150:02e0a0aed4ec 369 #define MXC_WDT_GET_WDT(i) ((i) == 0 ? MXC_WDT0 : \
<> 150:02e0a0aed4ec 370 (i) == 1 ? MXC_WDT1 : 0)
<> 150:02e0a0aed4ec 371
<> 150:02e0a0aed4ec 372 #define MXC_WDT_GET_IDX(i) ((i) == MXC_WDT0 ? 0: \
<> 150:02e0a0aed4ec 373 (i) == MXC_WDT1 ? 1: -1)
<> 150:02e0a0aed4ec 374
<> 150:02e0a0aed4ec 375
<> 150:02e0a0aed4ec 376 /*******************************************************************************/
<> 150:02e0a0aed4ec 377 /* Low-Level Watchdog Timer */
<> 150:02e0a0aed4ec 378
<> 150:02e0a0aed4ec 379 #define MXC_BASE_WDT2 ((uint32_t)0x40007C60UL)
<> 150:02e0a0aed4ec 380 #define MXC_WDT2 ((mxc_wdt2_regs_t *)MXC_BASE_WDT2)
<> 150:02e0a0aed4ec 381
<> 150:02e0a0aed4ec 382
<> 150:02e0a0aed4ec 383
<> 150:02e0a0aed4ec 384 /*******************************************************************************/
<> 150:02e0a0aed4ec 385 /* General Purpose I/O Ports (GPIO) */
<> 150:02e0a0aed4ec 386
<> 150:02e0a0aed4ec 387 #define MXC_GPIO_NUM_PORTS (5)
<> 150:02e0a0aed4ec 388 #define MXC_GPIO_MAX_PINS_PER_PORT (8)
<> 150:02e0a0aed4ec 389
<> 150:02e0a0aed4ec 390 #define MXC_BASE_GPIO ((uint32_t)0x4000A000UL)
<> 150:02e0a0aed4ec 391 #define MXC_GPIO ((mxc_gpio_regs_t *)MXC_BASE_GPIO)
<> 150:02e0a0aed4ec 392
<> 150:02e0a0aed4ec 393 #define MXC_GPIO_GET_IRQ(i) (IRQn_Type)((i) == 0 ? GPIO_P0_IRQn : \
<> 150:02e0a0aed4ec 394 (i) == 1 ? GPIO_P1_IRQn : \
<> 150:02e0a0aed4ec 395 (i) == 2 ? GPIO_P2_IRQn : \
<> 150:02e0a0aed4ec 396 (i) == 3 ? GPIO_P3_IRQn : \
<> 150:02e0a0aed4ec 397 (i) == 4 ? GPIO_P4_IRQn : 0)
<> 150:02e0a0aed4ec 398
<> 150:02e0a0aed4ec 399
<> 150:02e0a0aed4ec 400
<> 150:02e0a0aed4ec 401 /*******************************************************************************/
<> 150:02e0a0aed4ec 402 /* 16/32 bit Timer/Counters */
<> 150:02e0a0aed4ec 403
<> 150:02e0a0aed4ec 404 #define MXC_CFG_TMR_INSTANCES (6)
<> 150:02e0a0aed4ec 405
<> 150:02e0a0aed4ec 406 #define MXC_BASE_TMR0 ((uint32_t)0x4000B000UL)
<> 150:02e0a0aed4ec 407 #define MXC_TMR0 ((mxc_tmr_regs_t *)MXC_BASE_TMR0)
<> 150:02e0a0aed4ec 408 #define MXC_BASE_TMR1 ((uint32_t)0x4000C000UL)
<> 150:02e0a0aed4ec 409 #define MXC_TMR1 ((mxc_tmr_regs_t *)MXC_BASE_TMR1)
<> 150:02e0a0aed4ec 410 #define MXC_BASE_TMR2 ((uint32_t)0x4000D000UL)
<> 150:02e0a0aed4ec 411 #define MXC_TMR2 ((mxc_tmr_regs_t *)MXC_BASE_TMR2)
<> 150:02e0a0aed4ec 412 #define MXC_BASE_TMR3 ((uint32_t)0x4000E000UL)
<> 150:02e0a0aed4ec 413 #define MXC_TMR3 ((mxc_tmr_regs_t *)MXC_BASE_TMR3)
<> 150:02e0a0aed4ec 414 #define MXC_BASE_TMR4 ((uint32_t)0x4000F000UL)
<> 150:02e0a0aed4ec 415 #define MXC_TMR4 ((mxc_tmr_regs_t *)MXC_BASE_TMR4)
<> 150:02e0a0aed4ec 416 #define MXC_BASE_TMR5 ((uint32_t)0x40010000UL)
<> 150:02e0a0aed4ec 417 #define MXC_TMR5 ((mxc_tmr_regs_t *)MXC_BASE_TMR5)
<> 150:02e0a0aed4ec 418
<> 150:02e0a0aed4ec 419 #define MXC_TMR_GET_IRQ_32(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
<> 150:02e0a0aed4ec 420 (i) == 1 ? TMR1_0_IRQn : \
<> 150:02e0a0aed4ec 421 (i) == 2 ? TMR2_0_IRQn : \
<> 150:02e0a0aed4ec 422 (i) == 3 ? TMR3_0_IRQn : \
<> 150:02e0a0aed4ec 423 (i) == 4 ? TMR4_0_IRQn : \
<> 150:02e0a0aed4ec 424 (i) == 5 ? TMR5_0_IRQn : 0)
<> 150:02e0a0aed4ec 425
<> 150:02e0a0aed4ec 426 #define MXC_TMR_GET_IRQ_16(i) (IRQn_Type)((i) == 0 ? TMR0_0_IRQn : \
<> 150:02e0a0aed4ec 427 (i) == 1 ? TMR1_0_IRQn : \
<> 150:02e0a0aed4ec 428 (i) == 2 ? TMR2_0_IRQn : \
<> 150:02e0a0aed4ec 429 (i) == 3 ? TMR3_0_IRQn : \
<> 150:02e0a0aed4ec 430 (i) == 4 ? TMR4_0_IRQn : \
<> 150:02e0a0aed4ec 431 (i) == 5 ? TMR5_0_IRQn : \
<> 150:02e0a0aed4ec 432 (i) == 6 ? TMR0_1_IRQn : \
<> 150:02e0a0aed4ec 433 (i) == 7 ? TMR1_1_IRQn : \
<> 150:02e0a0aed4ec 434 (i) == 8 ? TMR2_1_IRQn : \
<> 150:02e0a0aed4ec 435 (i) == 9 ? TMR3_1_IRQn : \
<> 150:02e0a0aed4ec 436 (i) == 10 ? TMR4_1_IRQn : \
<> 150:02e0a0aed4ec 437 (i) == 11 ? TMR5_1_IRQn : 0)
<> 150:02e0a0aed4ec 438
<> 150:02e0a0aed4ec 439 #define MXC_TMR_GET_BASE(i) ((i) == 0 ? MXC_BASE_TMR0 : \
<> 150:02e0a0aed4ec 440 (i) == 1 ? MXC_BASE_TMR1 : \
<> 150:02e0a0aed4ec 441 (i) == 2 ? MXC_BASE_TMR2 : \
<> 150:02e0a0aed4ec 442 (i) == 3 ? MXC_BASE_TMR3 : \
<> 150:02e0a0aed4ec 443 (i) == 4 ? MXC_BASE_TMR4 : \
<> 150:02e0a0aed4ec 444 (i) == 5 ? MXC_BASE_TMR5 : 0)
<> 150:02e0a0aed4ec 445
<> 150:02e0a0aed4ec 446 #define MXC_TMR_GET_TMR(i) ((i) == 0 ? MXC_TMR0 : \
<> 150:02e0a0aed4ec 447 (i) == 1 ? MXC_TMR1 : \
<> 150:02e0a0aed4ec 448 (i) == 2 ? MXC_TMR2 : \
<> 150:02e0a0aed4ec 449 (i) == 3 ? MXC_TMR3 : \
<> 150:02e0a0aed4ec 450 (i) == 4 ? MXC_TMR4 : \
<> 150:02e0a0aed4ec 451 (i) == 5 ? MXC_TMR5 : 0)
<> 150:02e0a0aed4ec 452
<> 150:02e0a0aed4ec 453 #define MXC_TMR_GET_IDX(p) ((p) == MXC_TMR0 ? 0 : \
<> 150:02e0a0aed4ec 454 (p) == MXC_TMR1 ? 1 : \
<> 150:02e0a0aed4ec 455 (p) == MXC_TMR2 ? 2 : \
<> 150:02e0a0aed4ec 456 (p) == MXC_TMR3 ? 3 : \
<> 150:02e0a0aed4ec 457 (p) == MXC_TMR4 ? 4 : \
<> 150:02e0a0aed4ec 458 (p) == MXC_TMR5 ? 5 : -1)
<> 150:02e0a0aed4ec 459
<> 150:02e0a0aed4ec 460
<> 150:02e0a0aed4ec 461
<> 150:02e0a0aed4ec 462
<> 150:02e0a0aed4ec 463 /*******************************************************************************/
<> 150:02e0a0aed4ec 464 /* Pulse Train Generation */
<> 150:02e0a0aed4ec 465
<> 150:02e0a0aed4ec 466 #define MXC_CFG_PT_INSTANCES (16)
<> 150:02e0a0aed4ec 467
<> 150:02e0a0aed4ec 468 #define MXC_BASE_PTG ((uint32_t)0x40011000UL)
<> 150:02e0a0aed4ec 469 #define MXC_PTG ((mxc_ptg_regs_t *)MXC_BASE_PTG)
<> 150:02e0a0aed4ec 470 #define MXC_BASE_PT0 ((uint32_t)0x40011020UL)
<> 150:02e0a0aed4ec 471 #define MXC_PT0 ((mxc_pt_regs_t *)MXC_BASE_PT0)
<> 150:02e0a0aed4ec 472 #define MXC_BASE_PT1 ((uint32_t)0x40011040UL)
<> 150:02e0a0aed4ec 473 #define MXC_PT1 ((mxc_pt_regs_t *)MXC_BASE_PT1)
<> 150:02e0a0aed4ec 474 #define MXC_BASE_PT2 ((uint32_t)0x40011060UL)
<> 150:02e0a0aed4ec 475 #define MXC_PT2 ((mxc_pt_regs_t *)MXC_BASE_PT2)
<> 150:02e0a0aed4ec 476 #define MXC_BASE_PT3 ((uint32_t)0x40011080UL)
<> 150:02e0a0aed4ec 477 #define MXC_PT3 ((mxc_pt_regs_t *)MXC_BASE_PT3)
<> 150:02e0a0aed4ec 478 #define MXC_BASE_PT4 ((uint32_t)0x400110A0UL)
<> 150:02e0a0aed4ec 479 #define MXC_PT4 ((mxc_pt_regs_t *)MXC_BASE_PT4)
<> 150:02e0a0aed4ec 480 #define MXC_BASE_PT5 ((uint32_t)0x400110C0UL)
<> 150:02e0a0aed4ec 481 #define MXC_PT5 ((mxc_pt_regs_t *)MXC_BASE_PT5)
<> 150:02e0a0aed4ec 482 #define MXC_BASE_PT6 ((uint32_t)0x400110E0UL)
<> 150:02e0a0aed4ec 483 #define MXC_PT6 ((mxc_pt_regs_t *)MXC_BASE_PT6)
<> 150:02e0a0aed4ec 484 #define MXC_BASE_PT7 ((uint32_t)0x40011100UL)
<> 150:02e0a0aed4ec 485 #define MXC_PT7 ((mxc_pt_regs_t *)MXC_BASE_PT7)
<> 150:02e0a0aed4ec 486 #define MXC_BASE_PT8 ((uint32_t)0x40011120UL)
<> 150:02e0a0aed4ec 487 #define MXC_PT8 ((mxc_pt_regs_t *)MXC_BASE_PT8)
<> 150:02e0a0aed4ec 488 #define MXC_BASE_PT9 ((uint32_t)0x40011140UL)
<> 150:02e0a0aed4ec 489 #define MXC_PT9 ((mxc_pt_regs_t *)MXC_BASE_PT9)
<> 150:02e0a0aed4ec 490 #define MXC_BASE_PT10 ((uint32_t)0x40011160UL)
<> 150:02e0a0aed4ec 491 #define MXC_PT10 ((mxc_pt_regs_t *)MXC_BASE_PT10)
<> 150:02e0a0aed4ec 492 #define MXC_BASE_PT11 ((uint32_t)0x40011180UL)
<> 150:02e0a0aed4ec 493 #define MXC_PT11 ((mxc_pt_regs_t *)MXC_BASE_PT11)
<> 150:02e0a0aed4ec 494 #define MXC_BASE_PT12 ((uint32_t)0x400111A0UL)
<> 150:02e0a0aed4ec 495 #define MXC_PT12 ((mxc_pt_regs_t *)MXC_BASE_PT12)
<> 150:02e0a0aed4ec 496 #define MXC_BASE_PT13 ((uint32_t)0x400111C0UL)
<> 150:02e0a0aed4ec 497 #define MXC_PT13 ((mxc_pt_regs_t *)MXC_BASE_PT13)
<> 150:02e0a0aed4ec 498 #define MXC_BASE_PT14 ((uint32_t)0x400111E0UL)
<> 150:02e0a0aed4ec 499 #define MXC_PT14 ((mxc_pt_regs_t *)MXC_BASE_PT14)
<> 150:02e0a0aed4ec 500 #define MXC_BASE_PT15 ((uint32_t)0x40011200UL)
<> 150:02e0a0aed4ec 501 #define MXC_PT15 ((mxc_pt_regs_t *)MXC_BASE_PT15)
<> 150:02e0a0aed4ec 502
<> 150:02e0a0aed4ec 503 #define MXC_PT_GET_BASE(i) ((i) == 0 ? MXC_BASE_PT0 : \
<> 150:02e0a0aed4ec 504 (i) == 1 ? MXC_BASE_PT1 : \
<> 150:02e0a0aed4ec 505 (i) == 2 ? MXC_BASE_PT2 : \
<> 150:02e0a0aed4ec 506 (i) == 3 ? MXC_BASE_PT3 : \
<> 150:02e0a0aed4ec 507 (i) == 4 ? MXC_BASE_PT4 : \
<> 150:02e0a0aed4ec 508 (i) == 5 ? MXC_BASE_PT5 : \
<> 150:02e0a0aed4ec 509 (i) == 6 ? MXC_BASE_PT6 : \
<> 150:02e0a0aed4ec 510 (i) == 7 ? MXC_BASE_PT7 : \
<> 150:02e0a0aed4ec 511 (i) == 8 ? MXC_BASE_PT8 : \
<> 150:02e0a0aed4ec 512 (i) == 9 ? MXC_BASE_PT9 : \
<> 150:02e0a0aed4ec 513 (i) == 10 ? MXC_BASE_PT10 : \
<> 150:02e0a0aed4ec 514 (i) == 11 ? MXC_BASE_PT11 : \
<> 150:02e0a0aed4ec 515 (i) == 12 ? MXC_BASE_PT12 : \
<> 150:02e0a0aed4ec 516 (i) == 13 ? MXC_BASE_PT13 : \
<> 150:02e0a0aed4ec 517 (i) == 14 ? MXC_BASE_PT14 : \
<> 150:02e0a0aed4ec 518 (i) == 15 ? MXC_BASE_PT15 : 0)
<> 150:02e0a0aed4ec 519
<> 150:02e0a0aed4ec 520 #define MXC_PT_GET_PT(i) ((i) == 0 ? MXC_PT0 : \
<> 150:02e0a0aed4ec 521 (i) == 1 ? MXC_PT1 : \
<> 150:02e0a0aed4ec 522 (i) == 2 ? MXC_PT2 : \
<> 150:02e0a0aed4ec 523 (i) == 3 ? MXC_PT3 : \
<> 150:02e0a0aed4ec 524 (i) == 4 ? MXC_PT4 : \
<> 150:02e0a0aed4ec 525 (i) == 5 ? MXC_PT5 : \
<> 150:02e0a0aed4ec 526 (i) == 6 ? MXC_PT6 : \
<> 150:02e0a0aed4ec 527 (i) == 7 ? MXC_PT7 : \
<> 150:02e0a0aed4ec 528 (i) == 8 ? MXC_PT8 : \
<> 150:02e0a0aed4ec 529 (i) == 9 ? MXC_PT9 : \
<> 150:02e0a0aed4ec 530 (i) == 10 ? MXC_PT10 : \
<> 150:02e0a0aed4ec 531 (i) == 11 ? MXC_PT11 : \
<> 150:02e0a0aed4ec 532 (i) == 12 ? MXC_PT12 : \
<> 150:02e0a0aed4ec 533 (i) == 13 ? MXC_PT13 : \
<> 150:02e0a0aed4ec 534 (i) == 14 ? MXC_PT14 : \
<> 150:02e0a0aed4ec 535 (i) == 15 ? MXC_PT15 : 0)
<> 150:02e0a0aed4ec 536
<> 150:02e0a0aed4ec 537 #define MXC_PT_GET_IDX(p) ((p) == MXC_PT0 ? 0 : \
<> 150:02e0a0aed4ec 538 (p) == MXC_PT1 ? 1 : \
<> 150:02e0a0aed4ec 539 (p) == MXC_PT2 ? 2 : \
<> 150:02e0a0aed4ec 540 (p) == MXC_PT3 ? 3 : \
<> 150:02e0a0aed4ec 541 (p) == MXC_PT4 ? 4 : \
<> 150:02e0a0aed4ec 542 (p) == MXC_PT5 ? 5 : \
<> 150:02e0a0aed4ec 543 (p) == MXC_PT6 ? 6 : \
<> 150:02e0a0aed4ec 544 (p) == MXC_PT7 ? 7 : \
<> 150:02e0a0aed4ec 545 (p) == MXC_PT8 ? 8 : \
<> 150:02e0a0aed4ec 546 (p) == MXC_PT9 ? 9 : \
<> 150:02e0a0aed4ec 547 (p) == MXC_PT10 ? 10 : \
<> 150:02e0a0aed4ec 548 (p) == MXC_PT11 ? 11 : \
<> 150:02e0a0aed4ec 549 (p) == MXC_PT12 ? 12 : \
<> 150:02e0a0aed4ec 550 (p) == MXC_PT13 ? 13 : \
<> 150:02e0a0aed4ec 551 (p) == MXC_PT14 ? 14 : \
<> 150:02e0a0aed4ec 552 (p) == MXC_PT15 ? 15 : -1)
<> 150:02e0a0aed4ec 553
<> 150:02e0a0aed4ec 554
<> 150:02e0a0aed4ec 555
<> 150:02e0a0aed4ec 556 /*******************************************************************************/
<> 150:02e0a0aed4ec 557 /* UART / Serial Port Interface */
<> 150:02e0a0aed4ec 558
<> 150:02e0a0aed4ec 559 #define MXC_CFG_UART_INSTANCES (3)
<> 150:02e0a0aed4ec 560 #define MXC_UART_FIFO_DEPTH (32)
<> 150:02e0a0aed4ec 561
<> 150:02e0a0aed4ec 562 #define MXC_BASE_UART0 ((uint32_t)0x40012000UL)
<> 150:02e0a0aed4ec 563 #define MXC_UART0 ((mxc_uart_regs_t *)MXC_BASE_UART0)
<> 150:02e0a0aed4ec 564 #define MXC_BASE_UART1 ((uint32_t)0x40013000UL)
<> 150:02e0a0aed4ec 565 #define MXC_UART1 ((mxc_uart_regs_t *)MXC_BASE_UART1)
<> 150:02e0a0aed4ec 566 #define MXC_BASE_UART2 ((uint32_t)0x40014000UL)
<> 150:02e0a0aed4ec 567 #define MXC_UART2 ((mxc_uart_regs_t *)MXC_BASE_UART2)
<> 150:02e0a0aed4ec 568 #define MXC_BASE_UART0_FIFO ((uint32_t)0x40103000UL)
<> 150:02e0a0aed4ec 569 #define MXC_UART0_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART0_FIFO)
<> 150:02e0a0aed4ec 570 #define MXC_BASE_UART1_FIFO ((uint32_t)0x40104000UL)
<> 150:02e0a0aed4ec 571 #define MXC_UART1_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART1_FIFO)
<> 150:02e0a0aed4ec 572 #define MXC_BASE_UART2_FIFO ((uint32_t)0x40105000UL)
<> 150:02e0a0aed4ec 573 #define MXC_UART2_FIFO ((mxc_uart_fifo_regs_t *)MXC_BASE_UART2_FIFO)
<> 150:02e0a0aed4ec 574
<> 150:02e0a0aed4ec 575 #define MXC_UART_GET_IRQ(i) (IRQn_Type)((i) == 0 ? UART0_IRQn : \
<> 150:02e0a0aed4ec 576 (i) == 1 ? UART1_IRQn : \
<> 150:02e0a0aed4ec 577 (i) == 2 ? UART2_IRQn : 0)
<> 150:02e0a0aed4ec 578
<> 150:02e0a0aed4ec 579 #define MXC_UART_GET_BASE(i) ((i) == 0 ? MXC_BASE_UART0 : \
<> 150:02e0a0aed4ec 580 (i) == 1 ? MXC_BASE_UART1 : \
<> 150:02e0a0aed4ec 581 (i) == 2 ? MXC_BASE_UART2 : 0)
<> 150:02e0a0aed4ec 582
<> 150:02e0a0aed4ec 583 #define MXC_UART_GET_UART(i) ((i) == 0 ? MXC_UART0 : \
<> 150:02e0a0aed4ec 584 (i) == 1 ? MXC_UART1 : \
<> 150:02e0a0aed4ec 585 (i) == 2 ? MXC_UART2 : 0)
<> 150:02e0a0aed4ec 586
<> 150:02e0a0aed4ec 587 #define MXC_UART_GET_IDX(p) ((p) == MXC_UART0 ? 0 : \
<> 150:02e0a0aed4ec 588 (p) == MXC_UART1 ? 1 : \
<> 150:02e0a0aed4ec 589 (p) == MXC_UART2 ? 2 : -1)
<> 150:02e0a0aed4ec 590
<> 150:02e0a0aed4ec 591 #define MXC_UART_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_UART0_FIFO : \
<> 150:02e0a0aed4ec 592 (i) == 1 ? MXC_BASE_UART1_FIFO : \
<> 150:02e0a0aed4ec 593 (i) == 2 ? MXC_BASE_UART2_FIFO : 0)
<> 150:02e0a0aed4ec 594
<> 150:02e0a0aed4ec 595 #define MXC_UART_GET_FIFO(i) ((i) == 0 ? MXC_UART0_FIFO : \
<> 150:02e0a0aed4ec 596 (i) == 1 ? MXC_UART1_FIFO : \
<> 150:02e0a0aed4ec 597 (i) == 2 ? MXC_UART2_FIFO : 0)
<> 150:02e0a0aed4ec 598
<> 150:02e0a0aed4ec 599
<> 150:02e0a0aed4ec 600
<> 150:02e0a0aed4ec 601 /*******************************************************************************/
<> 150:02e0a0aed4ec 602 /* I2C Master Interface */
<> 150:02e0a0aed4ec 603
<> 150:02e0a0aed4ec 604 #define MXC_CFG_I2CM_INSTANCES (2)
<> 150:02e0a0aed4ec 605 #define MXC_I2CM_FIFO_DEPTH (8)
<> 150:02e0a0aed4ec 606
<> 150:02e0a0aed4ec 607 #define MXC_BASE_I2CM0 ((uint32_t)0x40016000UL)
<> 150:02e0a0aed4ec 608 #define MXC_I2CM0 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM0)
<> 150:02e0a0aed4ec 609 #define MXC_BASE_I2CM1 ((uint32_t)0x40017000UL)
<> 150:02e0a0aed4ec 610 #define MXC_I2CM1 ((mxc_i2cm_regs_t *)MXC_BASE_I2CM1)
<> 150:02e0a0aed4ec 611 #define MXC_BASE_I2CM0_FIFO ((uint32_t)0x40107000UL)
<> 150:02e0a0aed4ec 612 #define MXC_I2CM0_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM0_FIFO)
<> 150:02e0a0aed4ec 613 #define MXC_BASE_I2CM1_FIFO ((uint32_t)0x40108000UL)
<> 150:02e0a0aed4ec 614 #define MXC_I2CM1_FIFO ((mxc_i2cm_fifo_regs_t *)MXC_BASE_I2CM1_FIFO)
<> 150:02e0a0aed4ec 615
<> 150:02e0a0aed4ec 616 #define MXC_I2CM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CM0_IRQn : \
<> 150:02e0a0aed4ec 617 (i) == 1 ? I2CM1_IRQn : 0)
<> 150:02e0a0aed4ec 618
<> 150:02e0a0aed4ec 619 #define MXC_I2CM_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CM0 : \
<> 150:02e0a0aed4ec 620 (i) == 1 ? MXC_BASE_I2CM1 : 0)
<> 150:02e0a0aed4ec 621
<> 150:02e0a0aed4ec 622 #define MXC_I2CM_GET_I2CM(i) ((i) == 0 ? MXC_I2CM0 : \
<> 150:02e0a0aed4ec 623 (i) == 1 ? MXC_I2CM1 : 0)
<> 150:02e0a0aed4ec 624
<> 150:02e0a0aed4ec 625 #define MXC_I2CM_GET_IDX(p) ((p) == MXC_I2CM0 ? 0 : \
<> 150:02e0a0aed4ec 626 (p) == MXC_I2CM1 ? 1 : -1)
<> 150:02e0a0aed4ec 627
<> 150:02e0a0aed4ec 628 #define MXC_I2CM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_I2CM0_FIFO : \
<> 150:02e0a0aed4ec 629 (i) == 1 ? MXC_BASE_I2CM1_FIFO : 0)
<> 150:02e0a0aed4ec 630
<> 150:02e0a0aed4ec 631 #define MXC_I2CM_GET_FIFO(i) ((i) == 0 ? MXC_I2CM0_FIFO : \
<> 150:02e0a0aed4ec 632 (i) == 1 ? MXC_I2CM1_FIFO : 0)
<> 150:02e0a0aed4ec 633
<> 150:02e0a0aed4ec 634
<> 150:02e0a0aed4ec 635
<> 150:02e0a0aed4ec 636 /*******************************************************************************/
<> 150:02e0a0aed4ec 637 /* I2C Slave Interface (Mailbox type) */
<> 150:02e0a0aed4ec 638
<> 150:02e0a0aed4ec 639 #define MXC_CFG_I2CS_INSTANCES (1)
<> 150:02e0a0aed4ec 640 #define MXC_CFG_I2CS_BUFFER_SIZE (32)
<> 150:02e0a0aed4ec 641
<> 150:02e0a0aed4ec 642 #define MXC_BASE_I2CS ((uint32_t)0x40019000UL)
<> 150:02e0a0aed4ec 643 #define MXC_I2CS ((mxc_i2cs_regs_t *)MXC_BASE_I2CS)
<> 150:02e0a0aed4ec 644
<> 150:02e0a0aed4ec 645 #define MXC_I2CS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? I2CS_IRQn : 0)
<> 150:02e0a0aed4ec 646
<> 150:02e0a0aed4ec 647 #define MXC_I2CS_GET_BASE(i) ((i) == 0 ? MXC_BASE_I2CS : 0)
<> 150:02e0a0aed4ec 648
<> 150:02e0a0aed4ec 649 #define MXC_I2CS_GET_I2CS(i) ((i) == 0 ? MXC_I2CS : 0)
<> 150:02e0a0aed4ec 650
<> 150:02e0a0aed4ec 651 #define MXC_I2CS_GET_IDX(p) ((p) == MXC_I2CS ? 0 : -1)
<> 150:02e0a0aed4ec 652
<> 150:02e0a0aed4ec 653 /*******************************************************************************/
<> 150:02e0a0aed4ec 654 /* SPI Master Interface */
<> 150:02e0a0aed4ec 655
<> 150:02e0a0aed4ec 656 #define MXC_CFG_SPIM_INSTANCES (3)
<> 150:02e0a0aed4ec 657 #define MXC_CFG_SPIM_FIFO_DEPTH (16)
<> 150:02e0a0aed4ec 658
<> 150:02e0a0aed4ec 659 #define MXC_BASE_SPIM0 ((uint32_t)0x4001A000UL)
<> 150:02e0a0aed4ec 660 #define MXC_SPIM0 ((mxc_spim_regs_t *)MXC_BASE_SPIM0)
<> 150:02e0a0aed4ec 661 #define MXC_BASE_SPIM1 ((uint32_t)0x4001B000UL)
<> 150:02e0a0aed4ec 662 #define MXC_SPIM1 ((mxc_spim_regs_t *)MXC_BASE_SPIM1)
<> 150:02e0a0aed4ec 663 #define MXC_BASE_SPIM2 ((uint32_t)0x4001C000UL)
<> 150:02e0a0aed4ec 664 #define MXC_SPIM2 ((mxc_spim_regs_t *)MXC_BASE_SPIM2)
<> 150:02e0a0aed4ec 665 #define MXC_BASE_SPIM0_FIFO ((uint32_t)0x4010A000UL)
<> 150:02e0a0aed4ec 666 #define MXC_SPIM0_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM0_FIFO)
<> 150:02e0a0aed4ec 667 #define MXC_BASE_SPIM1_FIFO ((uint32_t)0x4010B000UL)
<> 150:02e0a0aed4ec 668 #define MXC_SPIM1_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM1_FIFO)
<> 150:02e0a0aed4ec 669 #define MXC_BASE_SPIM2_FIFO ((uint32_t)0x4010C000UL)
<> 150:02e0a0aed4ec 670 #define MXC_SPIM2_FIFO ((mxc_spim_fifo_regs_t *)MXC_BASE_SPIM2_FIFO)
<> 150:02e0a0aed4ec 671
<> 150:02e0a0aed4ec 672 #define MXC_SPIM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIM0_IRQn : \
<> 150:02e0a0aed4ec 673 (i) == 1 ? SPIM1_IRQn : \
<> 150:02e0a0aed4ec 674 (i) == 2 ? SPIM2_IRQn : 0)
<> 150:02e0a0aed4ec 675
<> 150:02e0a0aed4ec 676 #define MXC_SPIM_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIM0 : \
<> 150:02e0a0aed4ec 677 (i) == 1 ? MXC_BASE_SPIM1 : \
<> 150:02e0a0aed4ec 678 (i) == 2 ? MXC_BASE_SPIM2 : 0)
<> 150:02e0a0aed4ec 679
<> 150:02e0a0aed4ec 680 #define MXC_SPIM_GET_SPIM(i) ((i) == 0 ? MXC_SPIM0 : \
<> 150:02e0a0aed4ec 681 (i) == 1 ? MXC_SPIM1 : \
<> 150:02e0a0aed4ec 682 (i) == 2 ? MXC_SPIM2 : 0)
<> 150:02e0a0aed4ec 683
<> 150:02e0a0aed4ec 684 #define MXC_SPIM_GET_IDX(p) ((p) == MXC_SPIM0 ? 0 : \
<> 150:02e0a0aed4ec 685 (p) == MXC_SPIM1 ? 1 : \
<> 150:02e0a0aed4ec 686 (p) == MXC_SPIM2 ? 2 : -1)
<> 150:02e0a0aed4ec 687
<> 150:02e0a0aed4ec 688 #define MXC_SPIM_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIM0_FIFO : \
<> 150:02e0a0aed4ec 689 (i) == 1 ? MXC_BASE_SPIM1_FIFO : \
<> 150:02e0a0aed4ec 690 (i) == 2 ? MXC_BASE_SPIM2_FIFO : 0)
<> 150:02e0a0aed4ec 691
<> 150:02e0a0aed4ec 692 #define MXC_SPIM_GET_SPIM_FIFO(i) ((i) == 0 ? MXC_SPIM0_FIFO : \
<> 150:02e0a0aed4ec 693 (i) == 1 ? MXC_SPIM1_FIFO : \
<> 150:02e0a0aed4ec 694 (i) == 2 ? MXC_SPIM2_FIFO : 0)
<> 150:02e0a0aed4ec 695
<> 150:02e0a0aed4ec 696
<> 150:02e0a0aed4ec 697
<> 150:02e0a0aed4ec 698 /*******************************************************************************/
<> 150:02e0a0aed4ec 699 /* 1-Wire Master Interface */
<> 150:02e0a0aed4ec 700
<> 150:02e0a0aed4ec 701 #define MXC_CFG_OWM_INSTANCES (1)
<> 150:02e0a0aed4ec 702
<> 150:02e0a0aed4ec 703 #define MXC_BASE_OWM ((uint32_t)0x4001E000UL)
<> 150:02e0a0aed4ec 704 #define MXC_OWM ((mxc_owm_regs_t *)MXC_BASE_OWM)
<> 150:02e0a0aed4ec 705
<> 150:02e0a0aed4ec 706 #define MXC_OWM_GET_IRQ(i) (IRQn_Type)((i) == 0 ? OWM_IRQn : 0)
<> 150:02e0a0aed4ec 707
<> 150:02e0a0aed4ec 708 #define MXC_OWM_GET_BASE(i) ((i) == 0 ? MXC_BASE_OWM : 0)
<> 150:02e0a0aed4ec 709
<> 150:02e0a0aed4ec 710 #define MXC_OWM_GET_OWM(i) ((i) == 0 ? MXC_OWM : 0)
<> 150:02e0a0aed4ec 711
<> 150:02e0a0aed4ec 712 #define MXC_OWM_GET_IDX(p) ((p) == MXC_OWM ? 0 : -1)
<> 150:02e0a0aed4ec 713
<> 150:02e0a0aed4ec 714 /*******************************************************************************/
<> 150:02e0a0aed4ec 715 /* ADC / AFE */
<> 150:02e0a0aed4ec 716
<> 150:02e0a0aed4ec 717 #define MXC_CFG_ADC_FIFO_DEPTH (32)
<> 150:02e0a0aed4ec 718
<> 150:02e0a0aed4ec 719 #define MXC_BASE_ADC ((uint32_t)0x4001F000UL)
<> 150:02e0a0aed4ec 720 #define MXC_ADC ((mxc_adc_regs_t *)MXC_BASE_ADC)
<> 150:02e0a0aed4ec 721
<> 150:02e0a0aed4ec 722
<> 150:02e0a0aed4ec 723
<> 150:02e0a0aed4ec 724 /*******************************************************************************/
<> 150:02e0a0aed4ec 725 /* SPI Slave Interface */
<> 150:02e0a0aed4ec 726 #define MXC_CFG_SPIS_INSTANCES (1)
<> 150:02e0a0aed4ec 727 #define MXC_CFG_SPIS_FIFO_DEPTH (32)
<> 150:02e0a0aed4ec 728
<> 150:02e0a0aed4ec 729 #define MXC_BASE_SPIS ((uint32_t)0x40020000UL)
<> 150:02e0a0aed4ec 730 #define MXC_SPIS ((mxc_spis_regs_t *)MXC_BASE_SPIS)
<> 150:02e0a0aed4ec 731 #define MXC_BASE_SPIS_FIFO ((uint32_t)0x4010E000UL)
<> 150:02e0a0aed4ec 732 #define MXC_SPIS_FIFO ((mxc_spis_fifo_regs_t *)MXC_BASE_SPIS_FIFO)
<> 150:02e0a0aed4ec 733
<> 150:02e0a0aed4ec 734 #define MXC_SPIS_GET_IRQ(i) (IRQn_Type)((i) == 0 ? SPIS_IRQn : 0)
<> 150:02e0a0aed4ec 735
<> 150:02e0a0aed4ec 736 #define MXC_SPIS_GET_BASE(i) ((i) == 0 ? MXC_BASE_SPIS : 0)
<> 150:02e0a0aed4ec 737
<> 150:02e0a0aed4ec 738 #define MXC_SPIS_GET_SPIS(i) ((i) == 0 ? MXC_SPIS : 0)
<> 150:02e0a0aed4ec 739
<> 150:02e0a0aed4ec 740 #define MXC_SPIS_GET_IDX(p) ((p) == MXC_SPIS ? 0 : -1)
<> 150:02e0a0aed4ec 741
<> 150:02e0a0aed4ec 742 #define MXC_SPIS_GET_BASE_FIFO(i) ((i) == 0 ? MXC_BASE_SPIS_FIFO : 0)
<> 150:02e0a0aed4ec 743
<> 150:02e0a0aed4ec 744 #define MXC_SPIS_GET_SPIS_FIFO(i) ((i) == 0 ? MXC_SPIS_FIFO :0)
<> 150:02e0a0aed4ec 745
<> 150:02e0a0aed4ec 746 /*******************************************************************************/
<> 150:02e0a0aed4ec 747 /* Bit Shifting */
<> 150:02e0a0aed4ec 748
<> 150:02e0a0aed4ec 749 #define MXC_F_BIT_0 (1 << 0)
<> 150:02e0a0aed4ec 750 #define MXC_F_BIT_1 (1 << 1)
<> 150:02e0a0aed4ec 751 #define MXC_F_BIT_2 (1 << 2)
<> 150:02e0a0aed4ec 752 #define MXC_F_BIT_3 (1 << 3)
<> 150:02e0a0aed4ec 753 #define MXC_F_BIT_4 (1 << 4)
<> 150:02e0a0aed4ec 754 #define MXC_F_BIT_5 (1 << 5)
<> 150:02e0a0aed4ec 755 #define MXC_F_BIT_6 (1 << 6)
<> 150:02e0a0aed4ec 756 #define MXC_F_BIT_7 (1 << 7)
<> 150:02e0a0aed4ec 757 #define MXC_F_BIT_8 (1 << 8)
<> 150:02e0a0aed4ec 758 #define MXC_F_BIT_9 (1 << 9)
<> 150:02e0a0aed4ec 759 #define MXC_F_BIT_10 (1 << 10)
<> 150:02e0a0aed4ec 760 #define MXC_F_BIT_11 (1 << 11)
<> 150:02e0a0aed4ec 761 #define MXC_F_BIT_12 (1 << 12)
<> 150:02e0a0aed4ec 762 #define MXC_F_BIT_13 (1 << 13)
<> 150:02e0a0aed4ec 763 #define MXC_F_BIT_14 (1 << 14)
<> 150:02e0a0aed4ec 764 #define MXC_F_BIT_15 (1 << 15)
<> 150:02e0a0aed4ec 765 #define MXC_F_BIT_16 (1 << 16)
<> 150:02e0a0aed4ec 766 #define MXC_F_BIT_17 (1 << 17)
<> 150:02e0a0aed4ec 767 #define MXC_F_BIT_18 (1 << 18)
<> 150:02e0a0aed4ec 768 #define MXC_F_BIT_19 (1 << 19)
<> 150:02e0a0aed4ec 769 #define MXC_F_BIT_20 (1 << 20)
<> 150:02e0a0aed4ec 770 #define MXC_F_BIT_21 (1 << 21)
<> 150:02e0a0aed4ec 771 #define MXC_F_BIT_22 (1 << 22)
<> 150:02e0a0aed4ec 772 #define MXC_F_BIT_23 (1 << 23)
<> 150:02e0a0aed4ec 773 #define MXC_F_BIT_24 (1 << 24)
<> 150:02e0a0aed4ec 774 #define MXC_F_BIT_25 (1 << 25)
<> 150:02e0a0aed4ec 775 #define MXC_F_BIT_26 (1 << 26)
<> 150:02e0a0aed4ec 776 #define MXC_F_BIT_27 (1 << 27)
<> 150:02e0a0aed4ec 777 #define MXC_F_BIT_28 (1 << 28)
<> 150:02e0a0aed4ec 778 #define MXC_F_BIT_29 (1 << 29)
<> 150:02e0a0aed4ec 779 #define MXC_F_BIT_30 (1 << 30)
<> 150:02e0a0aed4ec 780 #define MXC_F_BIT_31 (1 << 31)
<> 150:02e0a0aed4ec 781
<> 150:02e0a0aed4ec 782
<> 150:02e0a0aed4ec 783 /*******************************************************************************/
<> 150:02e0a0aed4ec 784
<> 150:02e0a0aed4ec 785 #define BITBAND(reg, bit) ((0xf0000000 & (uint32_t)(reg)) + 0x2000000 + (((uint32_t)(reg) & 0x0fffffff) << 5) + ((bit) << 2))
<> 150:02e0a0aed4ec 786 #define MXC_CLRBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 0)
<> 150:02e0a0aed4ec 787 #define MXC_SETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit) = 1)
<> 150:02e0a0aed4ec 788 #define MXC_GETBIT(reg, bit) (*(volatile uint32_t *)BITBAND(reg, bit))
<> 150:02e0a0aed4ec 789 #define MXC_SET_FIELD(reg, clr, set) (*(volatile uint32_t *)reg = ((*(volatile uint32_t *)reg & ~clr) | set))
<> 150:02e0a0aed4ec 790
<> 150:02e0a0aed4ec 791
<> 150:02e0a0aed4ec 792 /*******************************************************************************/
<> 150:02e0a0aed4ec 793
<> 150:02e0a0aed4ec 794 /* SCB CPACR Register Definitions */
<> 150:02e0a0aed4ec 795 /* Note: Added by Maxim Integrated, as these are missing from CMSIS/Core/Include/core_cm4.h */
<> 150:02e0a0aed4ec 796 #define SCB_CPACR_CP10_Pos 20 /*!< SCB CPACR: Coprocessor 10 Position */
<> 150:02e0a0aed4ec 797 #define SCB_CPACR_CP10_Msk (0x3UL << SCB_CPACR_CP10_Pos) /*!< SCB CPACR: Coprocessor 10 Mask */
<> 150:02e0a0aed4ec 798 #define SCB_CPACR_CP11_Pos 22 /*!< SCB CPACR: Coprocessor 11 Position */
<> 150:02e0a0aed4ec 799 #define SCB_CPACR_CP11_Msk (0x3UL << SCB_CPACR_CP11_Pos) /*!< SCB CPACR: Coprocessor 11 Mask */
<> 150:02e0a0aed4ec 800
<> 150:02e0a0aed4ec 801 #endif /* _MAX32625_H_ */
<> 150:02e0a0aed4ec 802