Frank 26080115
Date: March 20, 2011 This library is created from "LPC17xx CMSIS-Compliant Standard Peripheral Firmware Driver Library (GNU, Keil, IAR) (Jan 28, 2011)", available from NXP's website, under "All microcontrollers support documents" [[http://ics.nxp.com/support/documents/microcontrollers/?type=software]] You will need to follow [[/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h]] while using this library Examples provided here [[/users/frank26080115/programs/LPC1700CMSIS_Examples/]] The beautiful thing is that NXP does not place copyright protection on any of the files in here Only a few modifications are made to make it compile with the mbed online compiler, I fixed some warnings as well. This is untested as of March 20, 2011 Forum post about this library: [[/forum/mbed/topic/2030/]]
lpc17xx_ssp.h@0:84d7747641aa, 2011-03-20 (annotated)
- Committer:
- frank26080115
- Date:
- Sun Mar 20 18:45:15 2011 +0000
- Revision:
- 0:84d7747641aa
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| frank26080115 | 0:84d7747641aa | 1 | /***********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 2 | * @file lpc17xx_ssp.h |
| frank26080115 | 0:84d7747641aa | 3 | * @brief Contains all macro definitions and function prototypes |
| frank26080115 | 0:84d7747641aa | 4 | * support for SSP firmware library on LPC17xx |
| frank26080115 | 0:84d7747641aa | 5 | * @version 3.0 |
| frank26080115 | 0:84d7747641aa | 6 | * @date 18. June. 2010 |
| frank26080115 | 0:84d7747641aa | 7 | * @author NXP MCU SW Application Team |
| frank26080115 | 0:84d7747641aa | 8 | ************************************************************************** |
| frank26080115 | 0:84d7747641aa | 9 | * Software that is described herein is for illustrative purposes only |
| frank26080115 | 0:84d7747641aa | 10 | * which provides customers with programming information regarding the |
| frank26080115 | 0:84d7747641aa | 11 | * products. This software is supplied "AS IS" without any warranties. |
| frank26080115 | 0:84d7747641aa | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| frank26080115 | 0:84d7747641aa | 13 | * use of the software, conveys no license or title under any patent, |
| frank26080115 | 0:84d7747641aa | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| frank26080115 | 0:84d7747641aa | 15 | * reserves the right to make changes in the software without |
| frank26080115 | 0:84d7747641aa | 16 | * notification. NXP Semiconductors also make no representation or |
| frank26080115 | 0:84d7747641aa | 17 | * warranty that such application will be suitable for the specified |
| frank26080115 | 0:84d7747641aa | 18 | * use without further testing or modification. |
| frank26080115 | 0:84d7747641aa | 19 | **************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 20 | |
| frank26080115 | 0:84d7747641aa | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 22 | /** @defgroup SSP SSP |
| frank26080115 | 0:84d7747641aa | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| frank26080115 | 0:84d7747641aa | 24 | * @{ |
| frank26080115 | 0:84d7747641aa | 25 | */ |
| frank26080115 | 0:84d7747641aa | 26 | |
| frank26080115 | 0:84d7747641aa | 27 | #ifndef LPC17XX_SSP_H_ |
| frank26080115 | 0:84d7747641aa | 28 | #define LPC17XX_SSP_H_ |
| frank26080115 | 0:84d7747641aa | 29 | |
| frank26080115 | 0:84d7747641aa | 30 | /* Includes ------------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 31 | #include "LPC17xx.h" |
| frank26080115 | 0:84d7747641aa | 32 | #include "lpc_types.h" |
| frank26080115 | 0:84d7747641aa | 33 | |
| frank26080115 | 0:84d7747641aa | 34 | |
| frank26080115 | 0:84d7747641aa | 35 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 36 | extern "C" |
| frank26080115 | 0:84d7747641aa | 37 | { |
| frank26080115 | 0:84d7747641aa | 38 | #endif |
| frank26080115 | 0:84d7747641aa | 39 | |
| frank26080115 | 0:84d7747641aa | 40 | /* Public Macros -------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 41 | /** @defgroup SSP_Public_Macros SSP Public Macros |
| frank26080115 | 0:84d7747641aa | 42 | * @{ |
| frank26080115 | 0:84d7747641aa | 43 | */ |
| frank26080115 | 0:84d7747641aa | 44 | |
| frank26080115 | 0:84d7747641aa | 45 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 46 | * SSP configuration parameter defines |
| frank26080115 | 0:84d7747641aa | 47 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 48 | /** Clock phase control bit */ |
| frank26080115 | 0:84d7747641aa | 49 | #define SSP_CPHA_FIRST ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 50 | #define SSP_CPHA_SECOND SSP_CR0_CPHA_SECOND |
| frank26080115 | 0:84d7747641aa | 51 | |
| frank26080115 | 0:84d7747641aa | 52 | |
| frank26080115 | 0:84d7747641aa | 53 | /** Clock polarity control bit */ |
| frank26080115 | 0:84d7747641aa | 54 | /* There's no bug here!!! |
| frank26080115 | 0:84d7747641aa | 55 | * - If bit[6] in SSPnCR0 is 0: SSP controller maintains the bus clock low between frames. |
| frank26080115 | 0:84d7747641aa | 56 | * That means the active clock is in HI state. |
| frank26080115 | 0:84d7747641aa | 57 | * - If bit[6] in SSPnCR0 is 1 (SSP_CR0_CPOL_HI): SSP controller maintains the bus clock |
| frank26080115 | 0:84d7747641aa | 58 | * high between frames. That means the active clock is in LO state. |
| frank26080115 | 0:84d7747641aa | 59 | */ |
| frank26080115 | 0:84d7747641aa | 60 | #define SSP_CPOL_HI ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 61 | #define SSP_CPOL_LO SSP_CR0_CPOL_HI |
| frank26080115 | 0:84d7747641aa | 62 | |
| frank26080115 | 0:84d7747641aa | 63 | /** SSP master mode enable */ |
| frank26080115 | 0:84d7747641aa | 64 | #define SSP_SLAVE_MODE SSP_CR1_SLAVE_EN |
| frank26080115 | 0:84d7747641aa | 65 | #define SSP_MASTER_MODE ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 66 | |
| frank26080115 | 0:84d7747641aa | 67 | /** SSP data bit number defines */ |
| frank26080115 | 0:84d7747641aa | 68 | #define SSP_DATABIT_4 SSP_CR0_DSS(4) /*!< Databit number = 4 */ |
| frank26080115 | 0:84d7747641aa | 69 | #define SSP_DATABIT_5 SSP_CR0_DSS(5) /*!< Databit number = 5 */ |
| frank26080115 | 0:84d7747641aa | 70 | #define SSP_DATABIT_6 SSP_CR0_DSS(6) /*!< Databit number = 6 */ |
| frank26080115 | 0:84d7747641aa | 71 | #define SSP_DATABIT_7 SSP_CR0_DSS(7) /*!< Databit number = 7 */ |
| frank26080115 | 0:84d7747641aa | 72 | #define SSP_DATABIT_8 SSP_CR0_DSS(8) /*!< Databit number = 8 */ |
| frank26080115 | 0:84d7747641aa | 73 | #define SSP_DATABIT_9 SSP_CR0_DSS(9) /*!< Databit number = 9 */ |
| frank26080115 | 0:84d7747641aa | 74 | #define SSP_DATABIT_10 SSP_CR0_DSS(10) /*!< Databit number = 10 */ |
| frank26080115 | 0:84d7747641aa | 75 | #define SSP_DATABIT_11 SSP_CR0_DSS(11) /*!< Databit number = 11 */ |
| frank26080115 | 0:84d7747641aa | 76 | #define SSP_DATABIT_12 SSP_CR0_DSS(12) /*!< Databit number = 12 */ |
| frank26080115 | 0:84d7747641aa | 77 | #define SSP_DATABIT_13 SSP_CR0_DSS(13) /*!< Databit number = 13 */ |
| frank26080115 | 0:84d7747641aa | 78 | #define SSP_DATABIT_14 SSP_CR0_DSS(14) /*!< Databit number = 14 */ |
| frank26080115 | 0:84d7747641aa | 79 | #define SSP_DATABIT_15 SSP_CR0_DSS(15) /*!< Databit number = 15 */ |
| frank26080115 | 0:84d7747641aa | 80 | #define SSP_DATABIT_16 SSP_CR0_DSS(16) /*!< Databit number = 16 */ |
| frank26080115 | 0:84d7747641aa | 81 | |
| frank26080115 | 0:84d7747641aa | 82 | /** SSP Frame Format definition */ |
| frank26080115 | 0:84d7747641aa | 83 | /** Motorola SPI mode */ |
| frank26080115 | 0:84d7747641aa | 84 | #define SSP_FRAME_SPI SSP_CR0_FRF_SPI |
| frank26080115 | 0:84d7747641aa | 85 | /** TI synchronous serial mode */ |
| frank26080115 | 0:84d7747641aa | 86 | #define SSP_FRAME_TI SSP_CR0_FRF_TI |
| frank26080115 | 0:84d7747641aa | 87 | /** National Micro-wire mode */ |
| frank26080115 | 0:84d7747641aa | 88 | #define SSP_FRAME_MICROWIRE SSP_CR0_FRF_MICROWIRE |
| frank26080115 | 0:84d7747641aa | 89 | |
| frank26080115 | 0:84d7747641aa | 90 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 91 | * SSP Status defines |
| frank26080115 | 0:84d7747641aa | 92 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 93 | /** SSP status TX FIFO Empty bit */ |
| frank26080115 | 0:84d7747641aa | 94 | #define SSP_STAT_TXFIFO_EMPTY SSP_SR_TFE |
| frank26080115 | 0:84d7747641aa | 95 | /** SSP status TX FIFO not full bit */ |
| frank26080115 | 0:84d7747641aa | 96 | #define SSP_STAT_TXFIFO_NOTFULL SSP_SR_TNF |
| frank26080115 | 0:84d7747641aa | 97 | /** SSP status RX FIFO not empty bit */ |
| frank26080115 | 0:84d7747641aa | 98 | #define SSP_STAT_RXFIFO_NOTEMPTY SSP_SR_RNE |
| frank26080115 | 0:84d7747641aa | 99 | /** SSP status RX FIFO full bit */ |
| frank26080115 | 0:84d7747641aa | 100 | #define SSP_STAT_RXFIFO_FULL SSP_SR_RFF |
| frank26080115 | 0:84d7747641aa | 101 | /** SSP status SSP Busy bit */ |
| frank26080115 | 0:84d7747641aa | 102 | #define SSP_STAT_BUSY SSP_SR_BSY |
| frank26080115 | 0:84d7747641aa | 103 | |
| frank26080115 | 0:84d7747641aa | 104 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 105 | * SSP Interrupt Configuration defines |
| frank26080115 | 0:84d7747641aa | 106 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 107 | /** Receive Overrun */ |
| frank26080115 | 0:84d7747641aa | 108 | #define SSP_INTCFG_ROR SSP_IMSC_ROR |
| frank26080115 | 0:84d7747641aa | 109 | /** Receive TimeOut */ |
| frank26080115 | 0:84d7747641aa | 110 | #define SSP_INTCFG_RT SSP_IMSC_RT |
| frank26080115 | 0:84d7747641aa | 111 | /** Rx FIFO is at least half full */ |
| frank26080115 | 0:84d7747641aa | 112 | #define SSP_INTCFG_RX SSP_IMSC_RX |
| frank26080115 | 0:84d7747641aa | 113 | /** Tx FIFO is at least half empty */ |
| frank26080115 | 0:84d7747641aa | 114 | #define SSP_INTCFG_TX SSP_IMSC_TX |
| frank26080115 | 0:84d7747641aa | 115 | |
| frank26080115 | 0:84d7747641aa | 116 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 117 | * SSP Configured Interrupt Status defines |
| frank26080115 | 0:84d7747641aa | 118 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 119 | /** Receive Overrun */ |
| frank26080115 | 0:84d7747641aa | 120 | #define SSP_INTSTAT_ROR SSP_MIS_ROR |
| frank26080115 | 0:84d7747641aa | 121 | /** Receive TimeOut */ |
| frank26080115 | 0:84d7747641aa | 122 | #define SSP_INTSTAT_RT SSP_MIS_RT |
| frank26080115 | 0:84d7747641aa | 123 | /** Rx FIFO is at least half full */ |
| frank26080115 | 0:84d7747641aa | 124 | #define SSP_INTSTAT_RX SSP_MIS_RX |
| frank26080115 | 0:84d7747641aa | 125 | /** Tx FIFO is at least half empty */ |
| frank26080115 | 0:84d7747641aa | 126 | #define SSP_INTSTAT_TX SSP_MIS_TX |
| frank26080115 | 0:84d7747641aa | 127 | |
| frank26080115 | 0:84d7747641aa | 128 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 129 | * SSP Raw Interrupt Status defines |
| frank26080115 | 0:84d7747641aa | 130 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 131 | /** Receive Overrun */ |
| frank26080115 | 0:84d7747641aa | 132 | #define SSP_INTSTAT_RAW_ROR SSP_RIS_ROR |
| frank26080115 | 0:84d7747641aa | 133 | /** Receive TimeOut */ |
| frank26080115 | 0:84d7747641aa | 134 | #define SSP_INTSTAT_RAW_RT SSP_RIS_RT |
| frank26080115 | 0:84d7747641aa | 135 | /** Rx FIFO is at least half full */ |
| frank26080115 | 0:84d7747641aa | 136 | #define SSP_INTSTAT_RAW_RX SSP_RIS_RX |
| frank26080115 | 0:84d7747641aa | 137 | /** Tx FIFO is at least half empty */ |
| frank26080115 | 0:84d7747641aa | 138 | #define SSP_INTSTAT_RAW_TX SSP_RIS_TX |
| frank26080115 | 0:84d7747641aa | 139 | |
| frank26080115 | 0:84d7747641aa | 140 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 141 | * SSP Interrupt Clear defines |
| frank26080115 | 0:84d7747641aa | 142 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 143 | /** Writing a 1 to this bit clears the "frame was received when |
| frank26080115 | 0:84d7747641aa | 144 | * RxFIFO was full" interrupt */ |
| frank26080115 | 0:84d7747641aa | 145 | #define SSP_INTCLR_ROR SSP_ICR_ROR |
| frank26080115 | 0:84d7747641aa | 146 | /** Writing a 1 to this bit clears the "Rx FIFO was not empty and |
| frank26080115 | 0:84d7747641aa | 147 | * has not been read for a timeout period" interrupt */ |
| frank26080115 | 0:84d7747641aa | 148 | #define SSP_INTCLR_RT SSP_ICR_RT |
| frank26080115 | 0:84d7747641aa | 149 | |
| frank26080115 | 0:84d7747641aa | 150 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 151 | * SSP DMA defines |
| frank26080115 | 0:84d7747641aa | 152 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 153 | /** SSP bit for enabling RX DMA */ |
| frank26080115 | 0:84d7747641aa | 154 | #define SSP_DMA_RX SSP_DMA_RXDMA_EN |
| frank26080115 | 0:84d7747641aa | 155 | /** SSP bit for enabling TX DMA */ |
| frank26080115 | 0:84d7747641aa | 156 | #define SSP_DMA_TX SSP_DMA_TXDMA_EN |
| frank26080115 | 0:84d7747641aa | 157 | |
| frank26080115 | 0:84d7747641aa | 158 | /* SSP Status Implementation definitions */ |
| frank26080115 | 0:84d7747641aa | 159 | #define SSP_STAT_DONE (1UL<<8) /**< Done */ |
| frank26080115 | 0:84d7747641aa | 160 | #define SSP_STAT_ERROR (1UL<<9) /**< Error */ |
| frank26080115 | 0:84d7747641aa | 161 | |
| frank26080115 | 0:84d7747641aa | 162 | /** |
| frank26080115 | 0:84d7747641aa | 163 | * @} |
| frank26080115 | 0:84d7747641aa | 164 | */ |
| frank26080115 | 0:84d7747641aa | 165 | |
| frank26080115 | 0:84d7747641aa | 166 | /* Private Macros ------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 167 | /** @defgroup SSP_Private_Macros SSP Private Macros |
| frank26080115 | 0:84d7747641aa | 168 | * @{ |
| frank26080115 | 0:84d7747641aa | 169 | */ |
| frank26080115 | 0:84d7747641aa | 170 | |
| frank26080115 | 0:84d7747641aa | 171 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 172 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 173 | * Macro defines for CR0 register |
| frank26080115 | 0:84d7747641aa | 174 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 175 | /** SSP data size select, must be 4 bits to 16 bits */ |
| frank26080115 | 0:84d7747641aa | 176 | #define SSP_CR0_DSS(n) ((uint32_t)((n-1)&0xF)) |
| frank26080115 | 0:84d7747641aa | 177 | /** SSP control 0 Motorola SPI mode */ |
| frank26080115 | 0:84d7747641aa | 178 | #define SSP_CR0_FRF_SPI ((uint32_t)(0<<4)) |
| frank26080115 | 0:84d7747641aa | 179 | /** SSP control 0 TI synchronous serial mode */ |
| frank26080115 | 0:84d7747641aa | 180 | #define SSP_CR0_FRF_TI ((uint32_t)(1<<4)) |
| frank26080115 | 0:84d7747641aa | 181 | /** SSP control 0 National Micro-wire mode */ |
| frank26080115 | 0:84d7747641aa | 182 | #define SSP_CR0_FRF_MICROWIRE ((uint32_t)(2<<4)) |
| frank26080115 | 0:84d7747641aa | 183 | /** SPI clock polarity bit (used in SPI mode only), (1) = maintains the |
| frank26080115 | 0:84d7747641aa | 184 | bus clock high between frames, (0) = low */ |
| frank26080115 | 0:84d7747641aa | 185 | #define SSP_CR0_CPOL_HI ((uint32_t)(1<<6)) |
| frank26080115 | 0:84d7747641aa | 186 | /** SPI clock out phase bit (used in SPI mode only), (1) = captures data |
| frank26080115 | 0:84d7747641aa | 187 | on the second clock transition of the frame, (0) = first */ |
| frank26080115 | 0:84d7747641aa | 188 | #define SSP_CR0_CPHA_SECOND ((uint32_t)(1<<7)) |
| frank26080115 | 0:84d7747641aa | 189 | /** SSP serial clock rate value load macro, divider rate is |
| frank26080115 | 0:84d7747641aa | 190 | PERIPH_CLK / (cpsr * (SCR + 1)) */ |
| frank26080115 | 0:84d7747641aa | 191 | #define SSP_CR0_SCR(n) ((uint32_t)((n&0xFF)<<8)) |
| frank26080115 | 0:84d7747641aa | 192 | /** SSP CR0 bit mask */ |
| frank26080115 | 0:84d7747641aa | 193 | #define SSP_CR0_BITMASK ((uint32_t)(0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 194 | |
| frank26080115 | 0:84d7747641aa | 195 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 196 | * Macro defines for CR1 register |
| frank26080115 | 0:84d7747641aa | 197 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 198 | /** SSP control 1 loopback mode enable bit */ |
| frank26080115 | 0:84d7747641aa | 199 | #define SSP_CR1_LBM_EN ((uint32_t)(1<<0)) |
| frank26080115 | 0:84d7747641aa | 200 | /** SSP control 1 enable bit */ |
| frank26080115 | 0:84d7747641aa | 201 | #define SSP_CR1_SSP_EN ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 202 | /** SSP control 1 slave enable */ |
| frank26080115 | 0:84d7747641aa | 203 | #define SSP_CR1_SLAVE_EN ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 204 | /** SSP control 1 slave out disable bit, disables transmit line in slave |
| frank26080115 | 0:84d7747641aa | 205 | mode */ |
| frank26080115 | 0:84d7747641aa | 206 | #define SSP_CR1_SO_DISABLE ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 207 | /** SSP CR1 bit mask */ |
| frank26080115 | 0:84d7747641aa | 208 | #define SSP_CR1_BITMASK ((uint32_t)(0x0F)) |
| frank26080115 | 0:84d7747641aa | 209 | |
| frank26080115 | 0:84d7747641aa | 210 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 211 | * Macro defines for DR register |
| frank26080115 | 0:84d7747641aa | 212 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 213 | /** SSP data bit mask */ |
| frank26080115 | 0:84d7747641aa | 214 | #define SSP_DR_BITMASK(n) ((n)&0xFFFF) |
| frank26080115 | 0:84d7747641aa | 215 | |
| frank26080115 | 0:84d7747641aa | 216 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 217 | * Macro defines for SR register |
| frank26080115 | 0:84d7747641aa | 218 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 219 | /** SSP status TX FIFO Empty bit */ |
| frank26080115 | 0:84d7747641aa | 220 | #define SSP_SR_TFE ((uint32_t)(1<<0)) |
| frank26080115 | 0:84d7747641aa | 221 | /** SSP status TX FIFO not full bit */ |
| frank26080115 | 0:84d7747641aa | 222 | #define SSP_SR_TNF ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 223 | /** SSP status RX FIFO not empty bit */ |
| frank26080115 | 0:84d7747641aa | 224 | #define SSP_SR_RNE ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 225 | /** SSP status RX FIFO full bit */ |
| frank26080115 | 0:84d7747641aa | 226 | #define SSP_SR_RFF ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 227 | /** SSP status SSP Busy bit */ |
| frank26080115 | 0:84d7747641aa | 228 | #define SSP_SR_BSY ((uint32_t)(1<<4)) |
| frank26080115 | 0:84d7747641aa | 229 | /** SSP SR bit mask */ |
| frank26080115 | 0:84d7747641aa | 230 | #define SSP_SR_BITMASK ((uint32_t)(0x1F)) |
| frank26080115 | 0:84d7747641aa | 231 | |
| frank26080115 | 0:84d7747641aa | 232 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 233 | * Macro defines for CPSR register |
| frank26080115 | 0:84d7747641aa | 234 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 235 | /** SSP clock prescaler */ |
| frank26080115 | 0:84d7747641aa | 236 | #define SSP_CPSR_CPDVSR(n) ((uint32_t)(n&0xFF)) |
| frank26080115 | 0:84d7747641aa | 237 | /** SSP CPSR bit mask */ |
| frank26080115 | 0:84d7747641aa | 238 | #define SSP_CPSR_BITMASK ((uint32_t)(0xFF)) |
| frank26080115 | 0:84d7747641aa | 239 | |
| frank26080115 | 0:84d7747641aa | 240 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 241 | * Macro define for (IMSC) Interrupt Mask Set/Clear registers |
| frank26080115 | 0:84d7747641aa | 242 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 243 | /** Receive Overrun */ |
| frank26080115 | 0:84d7747641aa | 244 | #define SSP_IMSC_ROR ((uint32_t)(1<<0)) |
| frank26080115 | 0:84d7747641aa | 245 | /** Receive TimeOut */ |
| frank26080115 | 0:84d7747641aa | 246 | #define SSP_IMSC_RT ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 247 | /** Rx FIFO is at least half full */ |
| frank26080115 | 0:84d7747641aa | 248 | #define SSP_IMSC_RX ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 249 | /** Tx FIFO is at least half empty */ |
| frank26080115 | 0:84d7747641aa | 250 | #define SSP_IMSC_TX ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 251 | /** IMSC bit mask */ |
| frank26080115 | 0:84d7747641aa | 252 | #define SSP_IMSC_BITMASK ((uint32_t)(0x0F)) |
| frank26080115 | 0:84d7747641aa | 253 | |
| frank26080115 | 0:84d7747641aa | 254 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 255 | * Macro define for (RIS) Raw Interrupt Status registers |
| frank26080115 | 0:84d7747641aa | 256 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 257 | /** Receive Overrun */ |
| frank26080115 | 0:84d7747641aa | 258 | #define SSP_RIS_ROR ((uint32_t)(1<<0)) |
| frank26080115 | 0:84d7747641aa | 259 | /** Receive TimeOut */ |
| frank26080115 | 0:84d7747641aa | 260 | #define SSP_RIS_RT ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 261 | /** Rx FIFO is at least half full */ |
| frank26080115 | 0:84d7747641aa | 262 | #define SSP_RIS_RX ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 263 | /** Tx FIFO is at least half empty */ |
| frank26080115 | 0:84d7747641aa | 264 | #define SSP_RIS_TX ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 265 | /** RIS bit mask */ |
| frank26080115 | 0:84d7747641aa | 266 | #define SSP_RIS_BITMASK ((uint32_t)(0x0F)) |
| frank26080115 | 0:84d7747641aa | 267 | |
| frank26080115 | 0:84d7747641aa | 268 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 269 | * Macro define for (MIS) Masked Interrupt Status registers |
| frank26080115 | 0:84d7747641aa | 270 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 271 | /** Receive Overrun */ |
| frank26080115 | 0:84d7747641aa | 272 | #define SSP_MIS_ROR ((uint32_t)(1<<0)) |
| frank26080115 | 0:84d7747641aa | 273 | /** Receive TimeOut */ |
| frank26080115 | 0:84d7747641aa | 274 | #define SSP_MIS_RT ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 275 | /** Rx FIFO is at least half full */ |
| frank26080115 | 0:84d7747641aa | 276 | #define SSP_MIS_RX ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 277 | /** Tx FIFO is at least half empty */ |
| frank26080115 | 0:84d7747641aa | 278 | #define SSP_MIS_TX ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 279 | /** MIS bit mask */ |
| frank26080115 | 0:84d7747641aa | 280 | #define SSP_MIS_BITMASK ((uint32_t)(0x0F)) |
| frank26080115 | 0:84d7747641aa | 281 | |
| frank26080115 | 0:84d7747641aa | 282 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 283 | * Macro define for (ICR) Interrupt Clear registers |
| frank26080115 | 0:84d7747641aa | 284 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 285 | /** Writing a 1 to this bit clears the "frame was received when |
| frank26080115 | 0:84d7747641aa | 286 | * RxFIFO was full" interrupt */ |
| frank26080115 | 0:84d7747641aa | 287 | #define SSP_ICR_ROR ((uint32_t)(1<<0)) |
| frank26080115 | 0:84d7747641aa | 288 | /** Writing a 1 to this bit clears the "Rx FIFO was not empty and |
| frank26080115 | 0:84d7747641aa | 289 | * has not been read for a timeout period" interrupt */ |
| frank26080115 | 0:84d7747641aa | 290 | #define SSP_ICR_RT ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 291 | /** ICR bit mask */ |
| frank26080115 | 0:84d7747641aa | 292 | #define SSP_ICR_BITMASK ((uint32_t)(0x03)) |
| frank26080115 | 0:84d7747641aa | 293 | |
| frank26080115 | 0:84d7747641aa | 294 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 295 | * Macro defines for DMACR register |
| frank26080115 | 0:84d7747641aa | 296 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 297 | /** SSP bit for enabling RX DMA */ |
| frank26080115 | 0:84d7747641aa | 298 | #define SSP_DMA_RXDMA_EN ((uint32_t)(1<<0)) |
| frank26080115 | 0:84d7747641aa | 299 | /** SSP bit for enabling TX DMA */ |
| frank26080115 | 0:84d7747641aa | 300 | #define SSP_DMA_TXDMA_EN ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 301 | /** DMACR bit mask */ |
| frank26080115 | 0:84d7747641aa | 302 | #define SSP_DMA_BITMASK ((uint32_t)(0x03)) |
| frank26080115 | 0:84d7747641aa | 303 | |
| frank26080115 | 0:84d7747641aa | 304 | |
| frank26080115 | 0:84d7747641aa | 305 | /* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */ |
| frank26080115 | 0:84d7747641aa | 306 | /** Macro to determine if it is valid SSP port number */ |
| frank26080115 | 0:84d7747641aa | 307 | #define PARAM_SSPx(n) ((((uint32_t *)n)==((uint32_t *)LPC_SSP0)) \ |
| frank26080115 | 0:84d7747641aa | 308 | || (((uint32_t *)n)==((uint32_t *)LPC_SSP1))) |
| frank26080115 | 0:84d7747641aa | 309 | |
| frank26080115 | 0:84d7747641aa | 310 | /** Macro check clock phase control mode */ |
| frank26080115 | 0:84d7747641aa | 311 | #define PARAM_SSP_CPHA(n) ((n==SSP_CPHA_FIRST) || (n==SSP_CPHA_SECOND)) |
| frank26080115 | 0:84d7747641aa | 312 | |
| frank26080115 | 0:84d7747641aa | 313 | /** Macro check clock polarity mode */ |
| frank26080115 | 0:84d7747641aa | 314 | #define PARAM_SSP_CPOL(n) ((n==SSP_CPOL_HI) || (n==SSP_CPOL_LO)) |
| frank26080115 | 0:84d7747641aa | 315 | |
| frank26080115 | 0:84d7747641aa | 316 | /* Macro check master/slave mode */ |
| frank26080115 | 0:84d7747641aa | 317 | #define PARAM_SSP_MODE(n) ((n==SSP_SLAVE_MODE) || (n==SSP_MASTER_MODE)) |
| frank26080115 | 0:84d7747641aa | 318 | |
| frank26080115 | 0:84d7747641aa | 319 | /* Macro check databit value */ |
| frank26080115 | 0:84d7747641aa | 320 | #define PARAM_SSP_DATABIT(n) ((n==SSP_DATABIT_4) || (n==SSP_DATABIT_5) \ |
| frank26080115 | 0:84d7747641aa | 321 | || (n==SSP_DATABIT_6) || (n==SSP_DATABIT_16) \ |
| frank26080115 | 0:84d7747641aa | 322 | || (n==SSP_DATABIT_7) || (n==SSP_DATABIT_8) \ |
| frank26080115 | 0:84d7747641aa | 323 | || (n==SSP_DATABIT_9) || (n==SSP_DATABIT_10) \ |
| frank26080115 | 0:84d7747641aa | 324 | || (n==SSP_DATABIT_11) || (n==SSP_DATABIT_12) \ |
| frank26080115 | 0:84d7747641aa | 325 | || (n==SSP_DATABIT_13) || (n==SSP_DATABIT_14) \ |
| frank26080115 | 0:84d7747641aa | 326 | || (n==SSP_DATABIT_15)) |
| frank26080115 | 0:84d7747641aa | 327 | |
| frank26080115 | 0:84d7747641aa | 328 | /* Macro check frame type */ |
| frank26080115 | 0:84d7747641aa | 329 | #define PARAM_SSP_FRAME(n) ((n==SSP_FRAME_SPI) || (n==SSP_FRAME_TI)\ |
| frank26080115 | 0:84d7747641aa | 330 | || (n==SSP_FRAME_MICROWIRE)) |
| frank26080115 | 0:84d7747641aa | 331 | |
| frank26080115 | 0:84d7747641aa | 332 | /* Macro check SSP status */ |
| frank26080115 | 0:84d7747641aa | 333 | #define PARAM_SSP_STAT(n) ((n==SSP_STAT_TXFIFO_EMPTY) || (n==SSP_STAT_TXFIFO_NOTFULL) \ |
| frank26080115 | 0:84d7747641aa | 334 | || (n==SSP_STAT_RXFIFO_NOTEMPTY) || (n==SSP_STAT_RXFIFO_FULL) \ |
| frank26080115 | 0:84d7747641aa | 335 | || (n==SSP_STAT_BUSY)) |
| frank26080115 | 0:84d7747641aa | 336 | |
| frank26080115 | 0:84d7747641aa | 337 | /* Macro check interrupt configuration */ |
| frank26080115 | 0:84d7747641aa | 338 | #define PARAM_SSP_INTCFG(n) ((n==SSP_INTCFG_ROR) || (n==SSP_INTCFG_RT) \ |
| frank26080115 | 0:84d7747641aa | 339 | || (n==SSP_INTCFG_RX) || (n==SSP_INTCFG_TX)) |
| frank26080115 | 0:84d7747641aa | 340 | |
| frank26080115 | 0:84d7747641aa | 341 | /* Macro check interrupt status value */ |
| frank26080115 | 0:84d7747641aa | 342 | #define PARAM_SSP_INTSTAT(n) ((n==SSP_INTSTAT_ROR) || (n==SSP_INTSTAT_RT) \ |
| frank26080115 | 0:84d7747641aa | 343 | || (n==SSP_INTSTAT_RX) || (n==SSP_INTSTAT_TX)) |
| frank26080115 | 0:84d7747641aa | 344 | |
| frank26080115 | 0:84d7747641aa | 345 | /* Macro check interrupt status raw value */ |
| frank26080115 | 0:84d7747641aa | 346 | #define PARAM_SSP_INTSTAT_RAW(n) ((n==SSP_INTSTAT_RAW_ROR) || (n==SSP_INTSTAT_RAW_RT) \ |
| frank26080115 | 0:84d7747641aa | 347 | || (n==SSP_INTSTAT_RAW_RX) || (n==SSP_INTSTAT_RAW_TX)) |
| frank26080115 | 0:84d7747641aa | 348 | |
| frank26080115 | 0:84d7747641aa | 349 | /* Macro check interrupt clear mode */ |
| frank26080115 | 0:84d7747641aa | 350 | #define PARAM_SSP_INTCLR(n) ((n==SSP_INTCLR_ROR) || (n==SSP_INTCLR_RT)) |
| frank26080115 | 0:84d7747641aa | 351 | |
| frank26080115 | 0:84d7747641aa | 352 | /* Macro check DMA mode */ |
| frank26080115 | 0:84d7747641aa | 353 | #define PARAM_SSP_DMA(n) ((n==SSP_DMA_TX) || (n==SSP_DMA_RX)) |
| frank26080115 | 0:84d7747641aa | 354 | /** |
| frank26080115 | 0:84d7747641aa | 355 | * @} |
| frank26080115 | 0:84d7747641aa | 356 | */ |
| frank26080115 | 0:84d7747641aa | 357 | |
| frank26080115 | 0:84d7747641aa | 358 | |
| frank26080115 | 0:84d7747641aa | 359 | /* Public Types --------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 360 | /** @defgroup SSP_Public_Types SSP Public Types |
| frank26080115 | 0:84d7747641aa | 361 | * @{ |
| frank26080115 | 0:84d7747641aa | 362 | */ |
| frank26080115 | 0:84d7747641aa | 363 | |
| frank26080115 | 0:84d7747641aa | 364 | /** @brief SSP configuration structure */ |
| frank26080115 | 0:84d7747641aa | 365 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 366 | uint32_t Databit; /** Databit number, should be SSP_DATABIT_x, |
| frank26080115 | 0:84d7747641aa | 367 | where x is in range from 4 - 16 */ |
| frank26080115 | 0:84d7747641aa | 368 | uint32_t CPHA; /** Clock phase, should be: |
| frank26080115 | 0:84d7747641aa | 369 | - SSP_CPHA_FIRST: first clock edge |
| frank26080115 | 0:84d7747641aa | 370 | - SSP_CPHA_SECOND: second clock edge */ |
| frank26080115 | 0:84d7747641aa | 371 | uint32_t CPOL; /** Clock polarity, should be: |
| frank26080115 | 0:84d7747641aa | 372 | - SSP_CPOL_HI: high level |
| frank26080115 | 0:84d7747641aa | 373 | - SSP_CPOL_LO: low level */ |
| frank26080115 | 0:84d7747641aa | 374 | uint32_t Mode; /** SSP mode, should be: |
| frank26080115 | 0:84d7747641aa | 375 | - SSP_MASTER_MODE: Master mode |
| frank26080115 | 0:84d7747641aa | 376 | - SSP_SLAVE_MODE: Slave mode */ |
| frank26080115 | 0:84d7747641aa | 377 | uint32_t FrameFormat; /** Frame Format: |
| frank26080115 | 0:84d7747641aa | 378 | - SSP_FRAME_SPI: Motorola SPI frame format |
| frank26080115 | 0:84d7747641aa | 379 | - SSP_FRAME_TI: TI frame format |
| frank26080115 | 0:84d7747641aa | 380 | - SSP_FRAME_MICROWIRE: National Microwire frame format */ |
| frank26080115 | 0:84d7747641aa | 381 | uint32_t ClockRate; /** Clock rate,in Hz */ |
| frank26080115 | 0:84d7747641aa | 382 | } SSP_CFG_Type; |
| frank26080115 | 0:84d7747641aa | 383 | |
| frank26080115 | 0:84d7747641aa | 384 | /** |
| frank26080115 | 0:84d7747641aa | 385 | * @brief SSP Transfer Type definitions |
| frank26080115 | 0:84d7747641aa | 386 | */ |
| frank26080115 | 0:84d7747641aa | 387 | typedef enum { |
| frank26080115 | 0:84d7747641aa | 388 | SSP_TRANSFER_POLLING = 0, /**< Polling transfer */ |
| frank26080115 | 0:84d7747641aa | 389 | SSP_TRANSFER_INTERRUPT /**< Interrupt transfer */ |
| frank26080115 | 0:84d7747641aa | 390 | } SSP_TRANSFER_Type; |
| frank26080115 | 0:84d7747641aa | 391 | |
| frank26080115 | 0:84d7747641aa | 392 | /** |
| frank26080115 | 0:84d7747641aa | 393 | * @brief SPI Data configuration structure definitions |
| frank26080115 | 0:84d7747641aa | 394 | */ |
| frank26080115 | 0:84d7747641aa | 395 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 396 | void *tx_data; /**< Pointer to transmit data */ |
| frank26080115 | 0:84d7747641aa | 397 | uint32_t tx_cnt; /**< Transmit counter */ |
| frank26080115 | 0:84d7747641aa | 398 | void *rx_data; /**< Pointer to transmit data */ |
| frank26080115 | 0:84d7747641aa | 399 | uint32_t rx_cnt; /**< Receive counter */ |
| frank26080115 | 0:84d7747641aa | 400 | uint32_t length; /**< Length of transfer data */ |
| frank26080115 | 0:84d7747641aa | 401 | uint32_t status; /**< Current status of SSP activity */ |
| frank26080115 | 0:84d7747641aa | 402 | } SSP_DATA_SETUP_Type; |
| frank26080115 | 0:84d7747641aa | 403 | |
| frank26080115 | 0:84d7747641aa | 404 | |
| frank26080115 | 0:84d7747641aa | 405 | /** |
| frank26080115 | 0:84d7747641aa | 406 | * @} |
| frank26080115 | 0:84d7747641aa | 407 | */ |
| frank26080115 | 0:84d7747641aa | 408 | |
| frank26080115 | 0:84d7747641aa | 409 | |
| frank26080115 | 0:84d7747641aa | 410 | /* Public Functions ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 411 | /** @defgroup SSP_Public_Functions SSP Public Functions |
| frank26080115 | 0:84d7747641aa | 412 | * @{ |
| frank26080115 | 0:84d7747641aa | 413 | */ |
| frank26080115 | 0:84d7747641aa | 414 | |
| frank26080115 | 0:84d7747641aa | 415 | /* SSP Init/DeInit functions --------------------------------------------------*/ |
| frank26080115 | 0:84d7747641aa | 416 | void SSP_Init(LPC_SSP_TypeDef *SSPx, SSP_CFG_Type *SSP_ConfigStruct); |
| frank26080115 | 0:84d7747641aa | 417 | void SSP_DeInit(LPC_SSP_TypeDef* SSPx); |
| frank26080115 | 0:84d7747641aa | 418 | |
| frank26080115 | 0:84d7747641aa | 419 | /* SSP configure functions ----------------------------------------------------*/ |
| frank26080115 | 0:84d7747641aa | 420 | void SSP_ConfigStructInit(SSP_CFG_Type *SSP_InitStruct); |
| frank26080115 | 0:84d7747641aa | 421 | |
| frank26080115 | 0:84d7747641aa | 422 | /* SSP enable/disable functions -----------------------------------------------*/ |
| frank26080115 | 0:84d7747641aa | 423 | void SSP_Cmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 424 | void SSP_LoopBackCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 425 | void SSP_SlaveOutputCmd(LPC_SSP_TypeDef* SSPx, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 426 | void SSP_DMACmd(LPC_SSP_TypeDef *SSPx, uint32_t DMAMode, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 427 | |
| frank26080115 | 0:84d7747641aa | 428 | /* SSP get information functions ----------------------------------------------*/ |
| frank26080115 | 0:84d7747641aa | 429 | FlagStatus SSP_GetStatus(LPC_SSP_TypeDef* SSPx, uint32_t FlagType); |
| frank26080115 | 0:84d7747641aa | 430 | uint8_t SSP_GetDataSize(LPC_SSP_TypeDef* SSPx); |
| frank26080115 | 0:84d7747641aa | 431 | IntStatus SSP_GetRawIntStatus(LPC_SSP_TypeDef *SSPx, uint32_t RawIntType); |
| frank26080115 | 0:84d7747641aa | 432 | uint32_t SSP_GetRawIntStatusReg(LPC_SSP_TypeDef *SSPx); |
| frank26080115 | 0:84d7747641aa | 433 | IntStatus SSP_GetIntStatus (LPC_SSP_TypeDef *SSPx, uint32_t IntType); |
| frank26080115 | 0:84d7747641aa | 434 | |
| frank26080115 | 0:84d7747641aa | 435 | /* SSP transfer data functions ------------------------------------------------*/ |
| frank26080115 | 0:84d7747641aa | 436 | void SSP_SendData(LPC_SSP_TypeDef* SSPx, uint16_t Data); |
| frank26080115 | 0:84d7747641aa | 437 | uint16_t SSP_ReceiveData(LPC_SSP_TypeDef* SSPx); |
| frank26080115 | 0:84d7747641aa | 438 | int32_t SSP_ReadWrite (LPC_SSP_TypeDef *SSPx, SSP_DATA_SETUP_Type *dataCfg, \ |
| frank26080115 | 0:84d7747641aa | 439 | SSP_TRANSFER_Type xfType); |
| frank26080115 | 0:84d7747641aa | 440 | |
| frank26080115 | 0:84d7747641aa | 441 | /* SSP IRQ function ------------------------------------------------------------*/ |
| frank26080115 | 0:84d7747641aa | 442 | void SSP_IntConfig(LPC_SSP_TypeDef *SSPx, uint32_t IntType, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 443 | void SSP_ClearIntPending(LPC_SSP_TypeDef *SSPx, uint32_t IntType); |
| frank26080115 | 0:84d7747641aa | 444 | |
| frank26080115 | 0:84d7747641aa | 445 | |
| frank26080115 | 0:84d7747641aa | 446 | /** |
| frank26080115 | 0:84d7747641aa | 447 | * @} |
| frank26080115 | 0:84d7747641aa | 448 | */ |
| frank26080115 | 0:84d7747641aa | 449 | |
| frank26080115 | 0:84d7747641aa | 450 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 451 | } |
| frank26080115 | 0:84d7747641aa | 452 | #endif |
| frank26080115 | 0:84d7747641aa | 453 | |
| frank26080115 | 0:84d7747641aa | 454 | #endif /* LPC17XX_SSP_H_ */ |
| frank26080115 | 0:84d7747641aa | 455 | |
| frank26080115 | 0:84d7747641aa | 456 | /** |
| frank26080115 | 0:84d7747641aa | 457 | * @} |
| frank26080115 | 0:84d7747641aa | 458 | */ |
| frank26080115 | 0:84d7747641aa | 459 | |
| frank26080115 | 0:84d7747641aa | 460 | /* --------------------------------- End Of File ------------------------------ */ |