LPC1700CMSIS_Lib - Date: March 20, 2011 This library is created f…

Users » frank26080115 » Code » LPC1700CMSIS_Lib

Date: March 20, 2011 This library is created from "LPC17xx CMSIS-Compliant Standard Peripheral Firmware Driver Library (GNU, Keil, IAR) (Jan 28, 2011)", available from NXP's website, under "All microcontrollers support documents" [[http://ics.nxp.com/support/documents/microcontrollers/?type=software]] You will need to follow [[/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h]] while using this library Examples provided here [[/users/frank26080115/programs/LPC1700CMSIS_Examples/]] The beautiful thing is that NXP does not place copyright protection on any of the files in here Only a few modifications are made to make it compile with the mbed online compiler, I fixed some warnings as well. This is untested as of March 20, 2011 Forum post about this library: [[/forum/mbed/topic/2030/]]

lpc17xx_spi.h@0:84d7747641aa, 2011-03-20 (annotated)

Committer:: frank26080115
Date:: Sun Mar 20 18:45:15 2011 +0000
Revision:: 0:84d7747641aa

Who changed what in which revision?

User	Revision	Line number	New contents of line
frank26080115	0:84d7747641aa	1	/*********************************************************************//
frank26080115	0:84d7747641aa	2	* @file lpc17xx_spi.h
frank26080115	0:84d7747641aa	3	* @brief Contains all macro definitions and function prototypes
frank26080115	0:84d7747641aa	4	* support for SPI firmware library on LPC17xx
frank26080115	0:84d7747641aa	5	* @version 2.0
frank26080115	0:84d7747641aa	6	* @date 21. May. 2010
frank26080115	0:84d7747641aa	7	* @author NXP MCU SW Application Team
frank26080115	0:84d7747641aa	8	**************************************************************************
frank26080115	0:84d7747641aa	9	* Software that is described herein is for illustrative purposes only
frank26080115	0:84d7747641aa	10	* which provides customers with programming information regarding the
frank26080115	0:84d7747641aa	11	* products. This software is supplied "AS IS" without any warranties.
frank26080115	0:84d7747641aa	12	* NXP Semiconductors assumes no responsibility or liability for the
frank26080115	0:84d7747641aa	13	* use of the software, conveys no license or title under any patent,
frank26080115	0:84d7747641aa	14	* copyright, or mask work right to the product. NXP Semiconductors
frank26080115	0:84d7747641aa	15	* reserves the right to make changes in the software without
frank26080115	0:84d7747641aa	16	* notification. NXP Semiconductors also make no representation or
frank26080115	0:84d7747641aa	17	* warranty that such application will be suitable for the specified
frank26080115	0:84d7747641aa	18	* use without further testing or modification.
frank26080115	0:84d7747641aa	19	**************************************************************************/
frank26080115	0:84d7747641aa	20
frank26080115	0:84d7747641aa	21	/* Peripheral group ----------------------------------------------------------- */
frank26080115	0:84d7747641aa	22	/** @defgroup SPI SPI
frank26080115	0:84d7747641aa	23	* @ingroup LPC1700CMSIS_FwLib_Drivers
frank26080115	0:84d7747641aa	24	* @{
frank26080115	0:84d7747641aa	25	*/
frank26080115	0:84d7747641aa	26
frank26080115	0:84d7747641aa	27	#ifndef LPC17XX_SPI_H_
frank26080115	0:84d7747641aa	28	#define LPC17XX_SPI_H_
frank26080115	0:84d7747641aa	29
frank26080115	0:84d7747641aa	30	/* Includes ------------------------------------------------------------------- */
frank26080115	0:84d7747641aa	31	#include "LPC17xx.h"
frank26080115	0:84d7747641aa	32	#include "lpc_types.h"
frank26080115	0:84d7747641aa	33
frank26080115	0:84d7747641aa	34
frank26080115	0:84d7747641aa	35	#ifdef __cplusplus
frank26080115	0:84d7747641aa	36	extern "C"
frank26080115	0:84d7747641aa	37	{
frank26080115	0:84d7747641aa	38	#endif
frank26080115	0:84d7747641aa	39
frank26080115	0:84d7747641aa	40	/* Public Macros -------------------------------------------------------------- */
frank26080115	0:84d7747641aa	41	/** @defgroup SPI_Public_Macros SPI Public Macros
frank26080115	0:84d7747641aa	42	* @{
frank26080115	0:84d7747641aa	43	*/
frank26080115	0:84d7747641aa	44
frank26080115	0:84d7747641aa	45	/*******************************************************************//
frank26080115	0:84d7747641aa	46	* SPI configuration parameter defines
frank26080115	0:84d7747641aa	47	**********************************************************************/
frank26080115	0:84d7747641aa	48	/** Clock phase control bit */
frank26080115	0:84d7747641aa	49	#define SPI_CPHA_FIRST ((uint32_t)(0))
frank26080115	0:84d7747641aa	50	#define SPI_CPHA_SECOND ((uint32_t)(1<<3))
frank26080115	0:84d7747641aa	51
frank26080115	0:84d7747641aa	52	/** Clock polarity control bit */
frank26080115	0:84d7747641aa	53	#define SPI_CPOL_HI ((uint32_t)(0))
frank26080115	0:84d7747641aa	54	#define SPI_CPOL_LO ((uint32_t)(1<<4))
frank26080115	0:84d7747641aa	55
frank26080115	0:84d7747641aa	56	/** SPI master mode enable */
frank26080115	0:84d7747641aa	57	#define SPI_SLAVE_MODE ((uint32_t)(0))
frank26080115	0:84d7747641aa	58	#define SPI_MASTER_MODE ((uint32_t)(1<<5))
frank26080115	0:84d7747641aa	59
frank26080115	0:84d7747641aa	60	/** LSB enable bit */
frank26080115	0:84d7747641aa	61	#define SPI_DATA_MSB_FIRST ((uint32_t)(0))
frank26080115	0:84d7747641aa	62	#define SPI_DATA_LSB_FIRST ((uint32_t)(1<<6))
frank26080115	0:84d7747641aa	63
frank26080115	0:84d7747641aa	64	/** SPI data bit number defines */
frank26080115	0:84d7747641aa	65	#define SPI_DATABIT_16 SPI_SPCR_BITS(0) /!< Databit number = 16 /
frank26080115	0:84d7747641aa	66	#define SPI_DATABIT_8 SPI_SPCR_BITS(0x08) /!< Databit number = 8 /
frank26080115	0:84d7747641aa	67	#define SPI_DATABIT_9 SPI_SPCR_BITS(0x09) /!< Databit number = 9 /
frank26080115	0:84d7747641aa	68	#define SPI_DATABIT_10 SPI_SPCR_BITS(0x0A) /!< Databit number = 10 /
frank26080115	0:84d7747641aa	69	#define SPI_DATABIT_11 SPI_SPCR_BITS(0x0B) /!< Databit number = 11 /
frank26080115	0:84d7747641aa	70	#define SPI_DATABIT_12 SPI_SPCR_BITS(0x0C) /!< Databit number = 12 /
frank26080115	0:84d7747641aa	71	#define SPI_DATABIT_13 SPI_SPCR_BITS(0x0D) /!< Databit number = 13 /
frank26080115	0:84d7747641aa	72	#define SPI_DATABIT_14 SPI_SPCR_BITS(0x0E) /!< Databit number = 14 /
frank26080115	0:84d7747641aa	73	#define SPI_DATABIT_15 SPI_SPCR_BITS(0x0F) /!< Databit number = 15 /
frank26080115	0:84d7747641aa	74
frank26080115	0:84d7747641aa	75	/*******************************************************************//
frank26080115	0:84d7747641aa	76	* SPI Status Flag defines
frank26080115	0:84d7747641aa	77	**********************************************************************/
frank26080115	0:84d7747641aa	78	/** Slave abort */
frank26080115	0:84d7747641aa	79	#define SPI_STAT_ABRT SPI_SPSR_ABRT
frank26080115	0:84d7747641aa	80	/** Mode fault */
frank26080115	0:84d7747641aa	81	#define SPI_STAT_MODF SPI_SPSR_MODF
frank26080115	0:84d7747641aa	82	/** Read overrun */
frank26080115	0:84d7747641aa	83	#define SPI_STAT_ROVR SPI_SPSR_ROVR
frank26080115	0:84d7747641aa	84	/** Write collision */
frank26080115	0:84d7747641aa	85	#define SPI_STAT_WCOL SPI_SPSR_WCOL
frank26080115	0:84d7747641aa	86	/** SPI transfer complete flag */
frank26080115	0:84d7747641aa	87	#define SPI_STAT_SPIF SPI_SPSR_SPIF
frank26080115	0:84d7747641aa	88
frank26080115	0:84d7747641aa	89	/* SPI Status Implementation definitions */
frank26080115	0:84d7747641aa	90	#define SPI_STAT_DONE (1UL<<8) /*< Done /
frank26080115	0:84d7747641aa	91	#define SPI_STAT_ERROR (1UL<<9) /*< Error /
frank26080115	0:84d7747641aa	92
frank26080115	0:84d7747641aa	93	/**
frank26080115	0:84d7747641aa	94	* @}
frank26080115	0:84d7747641aa	95	*/
frank26080115	0:84d7747641aa	96
frank26080115	0:84d7747641aa	97
frank26080115	0:84d7747641aa	98	/* Private Macros ------------------------------------------------------------- */
frank26080115	0:84d7747641aa	99	/** @defgroup SPI_Private_Macros SPI Private Macros
frank26080115	0:84d7747641aa	100	* @{
frank26080115	0:84d7747641aa	101	*/
frank26080115	0:84d7747641aa	102
frank26080115	0:84d7747641aa	103	/* --------------------- BIT DEFINITIONS -------------------------------------- */
frank26080115	0:84d7747641aa	104	/*******************************************************************//
frank26080115	0:84d7747641aa	105	* Macro defines for SPI Control Register
frank26080115	0:84d7747641aa	106	**********************************************************************/
frank26080115	0:84d7747641aa	107	/** Bit enable, the SPI controller sends and receives the number
frank26080115	0:84d7747641aa	108	* of bits selected by bits 11:8 */
frank26080115	0:84d7747641aa	109	#define SPI_SPCR_BIT_EN ((uint32_t)(1<<2))
frank26080115	0:84d7747641aa	110	/** Clock phase control bit */
frank26080115	0:84d7747641aa	111	#define SPI_SPCR_CPHA_SECOND ((uint32_t)(1<<3))
frank26080115	0:84d7747641aa	112	/** Clock polarity control bit */
frank26080115	0:84d7747641aa	113	#define SPI_SPCR_CPOL_LOW ((uint32_t)(1<<4))
frank26080115	0:84d7747641aa	114	/** SPI master mode enable */
frank26080115	0:84d7747641aa	115	#define SPI_SPCR_MSTR ((uint32_t)(1<<5))
frank26080115	0:84d7747641aa	116	/** LSB enable bit */
frank26080115	0:84d7747641aa	117	#define SPI_SPCR_LSBF ((uint32_t)(1<<6))
frank26080115	0:84d7747641aa	118	/** SPI interrupt enable bit */
frank26080115	0:84d7747641aa	119	#define SPI_SPCR_SPIE ((uint32_t)(1<<7))
frank26080115	0:84d7747641aa	120	/** When bit 2 of this register is 1, this field controls the
frank26080115	0:84d7747641aa	121	number of bits per transfer */
frank26080115	0:84d7747641aa	122	#define SPI_SPCR_BITS(n) ((n==0) ? ((uint32_t)0) : ((uint32_t)((n&0x0F)<<8)))
frank26080115	0:84d7747641aa	123	/** SPI Control bit mask */
frank26080115	0:84d7747641aa	124	#define SPI_SPCR_BITMASK ((uint32_t)(0xFFC))
frank26080115	0:84d7747641aa	125
frank26080115	0:84d7747641aa	126	/*******************************************************************//
frank26080115	0:84d7747641aa	127	* Macro defines for SPI Status Register
frank26080115	0:84d7747641aa	128	**********************************************************************/
frank26080115	0:84d7747641aa	129	/** Slave abort */
frank26080115	0:84d7747641aa	130	#define SPI_SPSR_ABRT ((uint32_t)(1<<3))
frank26080115	0:84d7747641aa	131	/** Mode fault */
frank26080115	0:84d7747641aa	132	#define SPI_SPSR_MODF ((uint32_t)(1<<4))
frank26080115	0:84d7747641aa	133	/** Read overrun */
frank26080115	0:84d7747641aa	134	#define SPI_SPSR_ROVR ((uint32_t)(1<<5))
frank26080115	0:84d7747641aa	135	/** Write collision */
frank26080115	0:84d7747641aa	136	#define SPI_SPSR_WCOL ((uint32_t)(1<<6))
frank26080115	0:84d7747641aa	137	/** SPI transfer complete flag */
frank26080115	0:84d7747641aa	138	#define SPI_SPSR_SPIF ((uint32_t)(1<<7))
frank26080115	0:84d7747641aa	139	/** SPI Status bit mask */
frank26080115	0:84d7747641aa	140	#define SPI_SPSR_BITMASK ((uint32_t)(0xF8))
frank26080115	0:84d7747641aa	141
frank26080115	0:84d7747641aa	142	/*******************************************************************//
frank26080115	0:84d7747641aa	143	* Macro defines for SPI Data Register
frank26080115	0:84d7747641aa	144	**********************************************************************/
frank26080115	0:84d7747641aa	145	/** SPI Data low bit-mask */
frank26080115	0:84d7747641aa	146	#define SPI_SPDR_LO_MASK ((uint32_t)(0xFF))
frank26080115	0:84d7747641aa	147	/** SPI Data high bit-mask */
frank26080115	0:84d7747641aa	148	#define SPI_SPDR_HI_MASK ((uint32_t)(0xFF00))
frank26080115	0:84d7747641aa	149	/** SPI Data bit-mask */
frank26080115	0:84d7747641aa	150	#define SPI_SPDR_BITMASK ((uint32_t)(0xFFFF))
frank26080115	0:84d7747641aa	151
frank26080115	0:84d7747641aa	152	/*******************************************************************//
frank26080115	0:84d7747641aa	153	* Macro defines for SPI Clock Counter Register
frank26080115	0:84d7747641aa	154	**********************************************************************/
frank26080115	0:84d7747641aa	155	/** SPI clock counter setting */
frank26080115	0:84d7747641aa	156	#define SPI_SPCCR_COUNTER(n) ((uint32_t)(n&0xFF))
frank26080115	0:84d7747641aa	157	/** SPI clock counter bit-mask */
frank26080115	0:84d7747641aa	158	#define SPI_SPCCR_BITMASK ((uint32_t)(0xFF))
frank26080115	0:84d7747641aa	159
frank26080115	0:84d7747641aa	160	/***********************************************************************
frank26080115	0:84d7747641aa	161	* Macro defines for SPI Test Control Register
frank26080115	0:84d7747641aa	162	**********************************************************************/
frank26080115	0:84d7747641aa	163	/** SPI Test bit */
frank26080115	0:84d7747641aa	164	#define SPI_SPTCR_TEST_MASK ((uint32_t)(0xFE))
frank26080115	0:84d7747641aa	165	/** SPI Test register bit mask */
frank26080115	0:84d7747641aa	166	#define SPI_SPTCR_BITMASK ((uint32_t)(0xFE))
frank26080115	0:84d7747641aa	167
frank26080115	0:84d7747641aa	168	/*******************************************************************//
frank26080115	0:84d7747641aa	169	* Macro defines for SPI Test Status Register
frank26080115	0:84d7747641aa	170	**********************************************************************/
frank26080115	0:84d7747641aa	171	/** Slave abort */
frank26080115	0:84d7747641aa	172	#define SPI_SPTSR_ABRT ((uint32_t)(1<<3))
frank26080115	0:84d7747641aa	173	/** Mode fault */
frank26080115	0:84d7747641aa	174	#define SPI_SPTSR_MODF ((uint32_t)(1<<4))
frank26080115	0:84d7747641aa	175	/** Read overrun */
frank26080115	0:84d7747641aa	176	#define SPI_SPTSR_ROVR ((uint32_t)(1<<5))
frank26080115	0:84d7747641aa	177	/** Write collision */
frank26080115	0:84d7747641aa	178	#define SPI_SPTSR_WCOL ((uint32_t)(1<<6))
frank26080115	0:84d7747641aa	179	/** SPI transfer complete flag */
frank26080115	0:84d7747641aa	180	#define SPI_SPTSR_SPIF ((uint32_t)(1<<7))
frank26080115	0:84d7747641aa	181	/** SPI Status bit mask */
frank26080115	0:84d7747641aa	182	#define SPI_SPTSR_MASKBIT ((uint32_t)(0xF8))
frank26080115	0:84d7747641aa	183
frank26080115	0:84d7747641aa	184	/*******************************************************************//
frank26080115	0:84d7747641aa	185	* Macro defines for SPI Interrupt Register
frank26080115	0:84d7747641aa	186	**********************************************************************/
frank26080115	0:84d7747641aa	187	/** SPI interrupt flag */
frank26080115	0:84d7747641aa	188	#define SPI_SPINT_INTFLAG ((uint32_t)(1<<0))
frank26080115	0:84d7747641aa	189	/** SPI interrupt register bit mask */
frank26080115	0:84d7747641aa	190	#define SPI_SPINT_BITMASK ((uint32_t)(0x01))
frank26080115	0:84d7747641aa	191
frank26080115	0:84d7747641aa	192
frank26080115	0:84d7747641aa	193	/* ---------------- CHECK PARAMETER DEFINITIONS ---------------------------- */
frank26080115	0:84d7747641aa	194	/** Macro to determine if it is valid SPI port number */
frank26080115	0:84d7747641aa	195	#define PARAM_SPIx(n) (((uint32_t )n)==((uint32_t )LPC_SPI))
frank26080115	0:84d7747641aa	196
frank26080115	0:84d7747641aa	197	/** Macro check Clock phase control mode */
frank26080115	0:84d7747641aa	198	#define PARAM_SPI_CPHA(n) ((n==SPI_CPHA_FIRST) \|\| (n==SPI_CPHA_SECOND))
frank26080115	0:84d7747641aa	199
frank26080115	0:84d7747641aa	200	/** Macro check Clock polarity control mode */
frank26080115	0:84d7747641aa	201	#define PARAM_SPI_CPOL(n) ((n==SPI_CPOL_HI) \|\| (n==SPI_CPOL_LO))
frank26080115	0:84d7747641aa	202
frank26080115	0:84d7747641aa	203	/** Macro check master/slave mode */
frank26080115	0:84d7747641aa	204	#define PARAM_SPI_MODE(n) ((n==SPI_SLAVE_MODE) \|\| (n==SPI_MASTER_MODE))
frank26080115	0:84d7747641aa	205
frank26080115	0:84d7747641aa	206	/** Macro check LSB/MSB mode */
frank26080115	0:84d7747641aa	207	#define PARAM_SPI_DATA_ORDER(n) ((n==SPI_DATA_MSB_FIRST) \|\| (n==SPI_DATA_LSB_FIRST))
frank26080115	0:84d7747641aa	208
frank26080115	0:84d7747641aa	209	/** Macro check databit value */
frank26080115	0:84d7747641aa	210	#define PARAM_SPI_DATABIT(n) ((n==SPI_DATABIT_16) \|\| (n==SPI_DATABIT_8) \
frank26080115	0:84d7747641aa	211	\|\| (n==SPI_DATABIT_9) \|\| (n==SPI_DATABIT_10) \
frank26080115	0:84d7747641aa	212	\|\| (n==SPI_DATABIT_11) \|\| (n==SPI_DATABIT_12) \
frank26080115	0:84d7747641aa	213	\|\| (n==SPI_DATABIT_13) \|\| (n==SPI_DATABIT_14) \
frank26080115	0:84d7747641aa	214	\|\| (n==SPI_DATABIT_15))
frank26080115	0:84d7747641aa	215
frank26080115	0:84d7747641aa	216	/** Macro check status flag */
frank26080115	0:84d7747641aa	217	#define PARAM_SPI_STAT(n) ((n==SPI_STAT_ABRT) \|\| (n==SPI_STAT_MODF) \
frank26080115	0:84d7747641aa	218	\|\| (n==SPI_STAT_ROVR) \|\| (n==SPI_STAT_WCOL) \
frank26080115	0:84d7747641aa	219	\|\| (n==SPI_STAT_SPIF))
frank26080115	0:84d7747641aa	220
frank26080115	0:84d7747641aa	221	/**
frank26080115	0:84d7747641aa	222	* @}
frank26080115	0:84d7747641aa	223	*/
frank26080115	0:84d7747641aa	224
frank26080115	0:84d7747641aa	225
frank26080115	0:84d7747641aa	226	/* Public Types --------------------------------------------------------------- */
frank26080115	0:84d7747641aa	227	/** @defgroup SPI_Public_Types SPI Public Types
frank26080115	0:84d7747641aa	228	* @{
frank26080115	0:84d7747641aa	229	*/
frank26080115	0:84d7747641aa	230
frank26080115	0:84d7747641aa	231	/** @brief SPI configuration structure */
frank26080115	0:84d7747641aa	232	typedef struct {
frank26080115	0:84d7747641aa	233	uint32_t Databit; /** Databit number, should be SPI_DATABIT_x,
frank26080115	0:84d7747641aa	234	where x is in range from 8 - 16 */
frank26080115	0:84d7747641aa	235	uint32_t CPHA; /** Clock phase, should be:
frank26080115	0:84d7747641aa	236	- SPI_CPHA_FIRST: first clock edge
frank26080115	0:84d7747641aa	237	- SPI_CPHA_SECOND: second clock edge */
frank26080115	0:84d7747641aa	238	uint32_t CPOL; /** Clock polarity, should be:
frank26080115	0:84d7747641aa	239	- SPI_CPOL_HI: high level
frank26080115	0:84d7747641aa	240	- SPI_CPOL_LO: low level */
frank26080115	0:84d7747641aa	241	uint32_t Mode; /** SPI mode, should be:
frank26080115	0:84d7747641aa	242	- SPI_MASTER_MODE: Master mode
frank26080115	0:84d7747641aa	243	- SPI_SLAVE_MODE: Slave mode */
frank26080115	0:84d7747641aa	244	uint32_t DataOrder; /** Data order, should be:
frank26080115	0:84d7747641aa	245	- SPI_DATA_MSB_FIRST: MSB first
frank26080115	0:84d7747641aa	246	- SPI_DATA_LSB_FIRST: LSB first */
frank26080115	0:84d7747641aa	247	uint32_t ClockRate; /** Clock rate,in Hz, should not exceed
frank26080115	0:84d7747641aa	248	(SPI peripheral clock)/8 */
frank26080115	0:84d7747641aa	249	} SPI_CFG_Type;
frank26080115	0:84d7747641aa	250
frank26080115	0:84d7747641aa	251
frank26080115	0:84d7747641aa	252	/**
frank26080115	0:84d7747641aa	253	* @brief SPI Transfer Type definitions
frank26080115	0:84d7747641aa	254	*/
frank26080115	0:84d7747641aa	255	typedef enum {
frank26080115	0:84d7747641aa	256	SPI_TRANSFER_POLLING = 0, /*< Polling transfer /
frank26080115	0:84d7747641aa	257	SPI_TRANSFER_INTERRUPT /*< Interrupt transfer /
frank26080115	0:84d7747641aa	258	} SPI_TRANSFER_Type;
frank26080115	0:84d7747641aa	259
frank26080115	0:84d7747641aa	260	/**
frank26080115	0:84d7747641aa	261	* @brief SPI Data configuration structure definitions
frank26080115	0:84d7747641aa	262	*/
frank26080115	0:84d7747641aa	263	typedef struct {
frank26080115	0:84d7747641aa	264	void tx_data; /< Pointer to transmit data /
frank26080115	0:84d7747641aa	265	void rx_data; /< Pointer to transmit data /
frank26080115	0:84d7747641aa	266	uint32_t length; /*< Length of transfer data /
frank26080115	0:84d7747641aa	267	uint32_t counter; /*< Data counter index /
frank26080115	0:84d7747641aa	268	uint32_t status; /*< Current status of SPI activity /
frank26080115	0:84d7747641aa	269	} SPI_DATA_SETUP_Type;
frank26080115	0:84d7747641aa	270
frank26080115	0:84d7747641aa	271	/**
frank26080115	0:84d7747641aa	272	* @}
frank26080115	0:84d7747641aa	273	*/
frank26080115	0:84d7747641aa	274
frank26080115	0:84d7747641aa	275
frank26080115	0:84d7747641aa	276	/* Public Functions ----------------------------------------------------------- */
frank26080115	0:84d7747641aa	277	/** @defgroup SPI_Public_Functions SPI Public Functions
frank26080115	0:84d7747641aa	278	* @{
frank26080115	0:84d7747641aa	279	*/
frank26080115	0:84d7747641aa	280
frank26080115	0:84d7747641aa	281	/* SPI Init/DeInit functions ---------*/
frank26080115	0:84d7747641aa	282	void SPI_Init(LPC_SPI_TypeDef SPIx, SPI_CFG_Type SPI_ConfigStruct);
frank26080115	0:84d7747641aa	283	void SPI_DeInit(LPC_SPI_TypeDef *SPIx);
frank26080115	0:84d7747641aa	284	void SPI_SetClock (LPC_SPI_TypeDef *SPIx, uint32_t target_clock);
frank26080115	0:84d7747641aa	285	void SPI_ConfigStructInit(SPI_CFG_Type *SPI_InitStruct);
frank26080115	0:84d7747641aa	286
frank26080115	0:84d7747641aa	287	/* SPI transfer functions ------------*/
frank26080115	0:84d7747641aa	288	void SPI_SendData(LPC_SPI_TypeDef *SPIx, uint16_t Data);
frank26080115	0:84d7747641aa	289	uint16_t SPI_ReceiveData(LPC_SPI_TypeDef *SPIx);
frank26080115	0:84d7747641aa	290	int32_t SPI_ReadWrite (LPC_SPI_TypeDef SPIx, SPI_DATA_SETUP_Type dataCfg, SPI_TRANSFER_Type xfType);
frank26080115	0:84d7747641aa	291
frank26080115	0:84d7747641aa	292	/* SPI Interrupt functions ---------*/
frank26080115	0:84d7747641aa	293	void SPI_IntCmd(LPC_SPI_TypeDef *SPIx, FunctionalState NewState);
frank26080115	0:84d7747641aa	294	IntStatus SPI_GetIntStatus (LPC_SPI_TypeDef *SPIx);
frank26080115	0:84d7747641aa	295	void SPI_ClearIntPending(LPC_SPI_TypeDef *SPIx);
frank26080115	0:84d7747641aa	296
frank26080115	0:84d7747641aa	297	/* SPI get information functions-----*/
frank26080115	0:84d7747641aa	298	uint8_t SPI_GetDataSize (LPC_SPI_TypeDef *SPIx);
frank26080115	0:84d7747641aa	299	uint32_t SPI_GetStatus(LPC_SPI_TypeDef *SPIx);
frank26080115	0:84d7747641aa	300	FlagStatus SPI_CheckStatus (uint32_t inputSPIStatus, uint8_t SPIStatus);
frank26080115	0:84d7747641aa	301
frank26080115	0:84d7747641aa	302	/**
frank26080115	0:84d7747641aa	303	* @}
frank26080115	0:84d7747641aa	304	*/
frank26080115	0:84d7747641aa	305
frank26080115	0:84d7747641aa	306	#ifdef __cplusplus
frank26080115	0:84d7747641aa	307	}
frank26080115	0:84d7747641aa	308	#endif
frank26080115	0:84d7747641aa	309
frank26080115	0:84d7747641aa	310	#endif /* LPC17XX_SPI_H_ */
frank26080115	0:84d7747641aa	311
frank26080115	0:84d7747641aa	312	/**
frank26080115	0:84d7747641aa	313	* @}
frank26080115	0:84d7747641aa	314	*/
frank26080115	0:84d7747641aa	315
frank26080115	0:84d7747641aa	316	/* --------------------------------- End Of File ------------------------------ */

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	20 Mar 2011
Imports:	652
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	20

lpc17xx_spi.h@0:84d7747641aa, 2011-03-20 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning