Frank 26080115
Date: March 20, 2011 This library is created from "LPC17xx CMSIS-Compliant Standard Peripheral Firmware Driver Library (GNU, Keil, IAR) (Jan 28, 2011)", available from NXP's website, under "All microcontrollers support documents" [[http://ics.nxp.com/support/documents/microcontrollers/?type=software]] You will need to follow [[/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h]] while using this library Examples provided here [[/users/frank26080115/programs/LPC1700CMSIS_Examples/]] The beautiful thing is that NXP does not place copyright protection on any of the files in here Only a few modifications are made to make it compile with the mbed online compiler, I fixed some warnings as well. This is untested as of March 20, 2011 Forum post about this library: [[/forum/mbed/topic/2030/]]
lpc17xx_gpdma.h@0:84d7747641aa, 2011-03-20 (annotated)
- Committer:
- frank26080115
- Date:
- Sun Mar 20 18:45:15 2011 +0000
- Revision:
- 0:84d7747641aa
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| frank26080115 | 0:84d7747641aa | 1 | /***********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 2 | * @file : lpc17xx_gpdma.h |
| frank26080115 | 0:84d7747641aa | 3 | * @brief : Contains all macro definitions and function prototypes |
| frank26080115 | 0:84d7747641aa | 4 | * support for GPDMA firmware library on LPC17xx |
| frank26080115 | 0:84d7747641aa | 5 | * @version : 1.0 |
| frank26080115 | 0:84d7747641aa | 6 | * @date : 20. Apr. 2009 |
| frank26080115 | 0:84d7747641aa | 7 | * @author : HieuNguyen |
| frank26080115 | 0:84d7747641aa | 8 | ************************************************************************** |
| frank26080115 | 0:84d7747641aa | 9 | * Software that is described herein is for illustrative purposes only |
| frank26080115 | 0:84d7747641aa | 10 | * which provides customers with programming information regarding the |
| frank26080115 | 0:84d7747641aa | 11 | * products. This software is supplied "AS IS" without any warranties. |
| frank26080115 | 0:84d7747641aa | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| frank26080115 | 0:84d7747641aa | 13 | * use of the software, conveys no license or title under any patent, |
| frank26080115 | 0:84d7747641aa | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| frank26080115 | 0:84d7747641aa | 15 | * reserves the right to make changes in the software without |
| frank26080115 | 0:84d7747641aa | 16 | * notification. NXP Semiconductors also make no representation or |
| frank26080115 | 0:84d7747641aa | 17 | * warranty that such application will be suitable for the specified |
| frank26080115 | 0:84d7747641aa | 18 | * use without further testing or modification. |
| frank26080115 | 0:84d7747641aa | 19 | **************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 20 | |
| frank26080115 | 0:84d7747641aa | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 22 | /** @defgroup GPDMA |
| frank26080115 | 0:84d7747641aa | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| frank26080115 | 0:84d7747641aa | 24 | * @{ |
| frank26080115 | 0:84d7747641aa | 25 | */ |
| frank26080115 | 0:84d7747641aa | 26 | |
| frank26080115 | 0:84d7747641aa | 27 | #ifndef LPC17XX_GPDMA_H_ |
| frank26080115 | 0:84d7747641aa | 28 | #define LPC17XX_GPDMA_H_ |
| frank26080115 | 0:84d7747641aa | 29 | |
| frank26080115 | 0:84d7747641aa | 30 | /* Includes ------------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 31 | #include "cmsis.h" |
| frank26080115 | 0:84d7747641aa | 32 | #include "lpc_types.h" |
| frank26080115 | 0:84d7747641aa | 33 | |
| frank26080115 | 0:84d7747641aa | 34 | |
| frank26080115 | 0:84d7747641aa | 35 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 36 | extern "C" |
| frank26080115 | 0:84d7747641aa | 37 | { |
| frank26080115 | 0:84d7747641aa | 38 | #endif |
| frank26080115 | 0:84d7747641aa | 39 | |
| frank26080115 | 0:84d7747641aa | 40 | |
| frank26080115 | 0:84d7747641aa | 41 | /* Private Macros ------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 42 | /** @defgroup GPDMA_Private_Macros |
| frank26080115 | 0:84d7747641aa | 43 | * @{ |
| frank26080115 | 0:84d7747641aa | 44 | */ |
| frank26080115 | 0:84d7747641aa | 45 | |
| frank26080115 | 0:84d7747641aa | 46 | /** @defgroup DMA_REGISTER_BIT_DEFINITIONS |
| frank26080115 | 0:84d7747641aa | 47 | * @{ |
| frank26080115 | 0:84d7747641aa | 48 | */ |
| frank26080115 | 0:84d7747641aa | 49 | |
| frank26080115 | 0:84d7747641aa | 50 | /** Macros define for DMA interrupt */ |
| frank26080115 | 0:84d7747641aa | 51 | /** DMA Interrupt Status register */ |
| frank26080115 | 0:84d7747641aa | 52 | #define GPDMA_DMACIntStat_Ch(n) (((1UL<<n)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 53 | #define GPDMA_DMACIntStat_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 54 | |
| frank26080115 | 0:84d7747641aa | 55 | /** DMA Interrupt Terminal Count Request Status register */ |
| frank26080115 | 0:84d7747641aa | 56 | #define GPDMA_DMACIntTCStat_Ch(n) (((1UL<<n)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 57 | #define GPDMA_DMACIntTCStat_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 58 | |
| frank26080115 | 0:84d7747641aa | 59 | /** DMA Interrupt Terminal Count Request Clear register */ |
| frank26080115 | 0:84d7747641aa | 60 | #define GPDMA_DMACIntTCClear_Ch(n) (((1UL<<n)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 61 | #define GPDMA_DMACIntTCClear_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 62 | |
| frank26080115 | 0:84d7747641aa | 63 | /** DMA Interrupt Error Status register */ |
| frank26080115 | 0:84d7747641aa | 64 | #define GPDMA_DMACIntErrStat_Ch(n) (((1UL<<n)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 65 | #define GPDMA_DMACIntErrStat_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 66 | |
| frank26080115 | 0:84d7747641aa | 67 | /** DMA Interrupt Error Clear register */ |
| frank26080115 | 0:84d7747641aa | 68 | #define GPDMA_DMACIntErrClr_Ch(n) (((1UL<<n)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 69 | #define GPDMA_DMACIntErrClr_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 70 | |
| frank26080115 | 0:84d7747641aa | 71 | /** DMA Raw Interrupt Terminal Count Status register */ |
| frank26080115 | 0:84d7747641aa | 72 | #define GPDMA_DMACRawIntTCStat_Ch(n) (((1UL<<n)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 73 | #define GPDMA_DMACRawIntTCStat_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 74 | |
| frank26080115 | 0:84d7747641aa | 75 | /** DMA Raw Error Interrupt Status register */ |
| frank26080115 | 0:84d7747641aa | 76 | #define GPDMA_DMACRawIntErrStat_Ch(n) (((1UL<<n)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 77 | #define GPDMA_DMACRawIntErrStat_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 78 | |
| frank26080115 | 0:84d7747641aa | 79 | /** DMA Enabled Channel register */ |
| frank26080115 | 0:84d7747641aa | 80 | #define GPDMA_DMACEnbldChns_Ch(n) (((1UL<<n)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 81 | #define GPDMA_DMACEnbldChns_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 82 | |
| frank26080115 | 0:84d7747641aa | 83 | |
| frank26080115 | 0:84d7747641aa | 84 | /** Macro defines for DMA Software Burst Request register */ |
| frank26080115 | 0:84d7747641aa | 85 | #define GPDMA_DMACSoftBReq_Src(n) (((1UL<<n)&0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 86 | #define GPDMA_DMACSoftBReq_BITMASK ((0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 87 | |
| frank26080115 | 0:84d7747641aa | 88 | /** Macro defines for DMA Software Single Request register */ |
| frank26080115 | 0:84d7747641aa | 89 | #define GPDMA_DMACSoftSReq_Src(n) (((1UL<<n)&0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 90 | #define GPDMA_DMACSoftSReq_BITMASK ((0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 91 | |
| frank26080115 | 0:84d7747641aa | 92 | /** Macro defines for DMA Software Last Burst Request register */ |
| frank26080115 | 0:84d7747641aa | 93 | #define GPDMA_DMACSoftLBReq_Src(n) (((1UL<<n)&0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 94 | #define GPDMA_DMACSoftLBReq_BITMASK ((0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 95 | |
| frank26080115 | 0:84d7747641aa | 96 | /** Macro defines for DMA Software Last Single Request register */ |
| frank26080115 | 0:84d7747641aa | 97 | #define GPDMA_DMACSoftLSReq_Src(n) (((1UL<<n)&0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 98 | #define GPDMA_DMACSoftLSReq_BITMASK ((0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 99 | |
| frank26080115 | 0:84d7747641aa | 100 | /** DMA Configuration register bit description*/ |
| frank26080115 | 0:84d7747641aa | 101 | #define GPDMA_DMACConfig_E ((0x01)) /**< DMA Controller enable*/ |
| frank26080115 | 0:84d7747641aa | 102 | #define GPDMA_DMACConfig_M ((0x02)) /**< AHB Master endianness configuration*/ |
| frank26080115 | 0:84d7747641aa | 103 | #define GPDMA_DMACConfig_BITMASK ((0x03)) |
| frank26080115 | 0:84d7747641aa | 104 | |
| frank26080115 | 0:84d7747641aa | 105 | |
| frank26080115 | 0:84d7747641aa | 106 | /** Macro defines for DMA Synchronization register */ |
| frank26080115 | 0:84d7747641aa | 107 | #define GPDMA_DMACSync_Src(n) (((1UL<<n)&0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 108 | #define GPDMA_DMACSync_BITMASK ((0xFFFF)) |
| frank26080115 | 0:84d7747641aa | 109 | |
| frank26080115 | 0:84d7747641aa | 110 | /** Macro defines for DMA Request Select register */ |
| frank26080115 | 0:84d7747641aa | 111 | #define GPDMA_DMAReqSel_Input(n) (((1UL<<(n-8))&0xFF)) |
| frank26080115 | 0:84d7747641aa | 112 | #define GPDMA_DMAReqSel_BITMASK ((0xFF)) |
| frank26080115 | 0:84d7747641aa | 113 | |
| frank26080115 | 0:84d7747641aa | 114 | /** DMA Channel Linked List Item registers bit mask*/ |
| frank26080115 | 0:84d7747641aa | 115 | #define GPDMA_DMACCxLLI_BITMASK ((0xFFFFFFFC)) |
| frank26080115 | 0:84d7747641aa | 116 | |
| frank26080115 | 0:84d7747641aa | 117 | /** DMA channel control registers bit description */ |
| frank26080115 | 0:84d7747641aa | 118 | #define GPDMA_DMACCxControl_TransferSize(n) (((n&0xFFF)<<0)) /**< Transfer size*/ |
| frank26080115 | 0:84d7747641aa | 119 | #define GPDMA_DMACCxControl_SBSize(n) (((n&0x07)<<12)) /**< Source burst size*/ |
| frank26080115 | 0:84d7747641aa | 120 | #define GPDMA_DMACCxControl_DBSize(n) (((n&0x07)<<15)) /**< Destination burst size*/ |
| frank26080115 | 0:84d7747641aa | 121 | #define GPDMA_DMACCxControl_SWidth(n) (((n&0x07)<<18)) /**< Source transfer width*/ |
| frank26080115 | 0:84d7747641aa | 122 | #define GPDMA_DMACCxControl_DWidth(n) (((n&0x07)<<21)) /**< Destination transfer width*/ |
| frank26080115 | 0:84d7747641aa | 123 | #define GPDMA_DMACCxControl_SI ((1UL<<26)) /**< Source increment*/ |
| frank26080115 | 0:84d7747641aa | 124 | #define GPDMA_DMACCxControl_DI ((1UL<<27)) /**< Destination increment*/ |
| frank26080115 | 0:84d7747641aa | 125 | #define GPDMA_DMACCxControl_Prot1 ((1UL<<28)) /**< Indicates that the access is in user mode or privileged mode*/ |
| frank26080115 | 0:84d7747641aa | 126 | #define GPDMA_DMACCxControl_Prot2 ((1UL<<29)) /**< Indicates that the access is bufferable or not bufferable*/ |
| frank26080115 | 0:84d7747641aa | 127 | #define GPDMA_DMACCxControl_Prot3 ((1UL<<30)) /**< Indicates that the access is cacheable or not cacheable*/ |
| frank26080115 | 0:84d7747641aa | 128 | #define GPDMA_DMACCxControl_I ((1UL<<31)) /**< Terminal count interrupt enable bit */ |
| frank26080115 | 0:84d7747641aa | 129 | /** DMA channel control registers bit mask */ |
| frank26080115 | 0:84d7747641aa | 130 | #define GPDMA_DMACCxControl_BITMASK ((0xFCFFFFFF)) |
| frank26080115 | 0:84d7747641aa | 131 | |
| frank26080115 | 0:84d7747641aa | 132 | |
| frank26080115 | 0:84d7747641aa | 133 | /** DMA Channel Configuration registers bit description*/ |
| frank26080115 | 0:84d7747641aa | 134 | #define GPDMA_DMACCxConfig_E ((1UL<<0)) /**< DMA control enable*/ |
| frank26080115 | 0:84d7747641aa | 135 | #define GPDMA_DMACCxConfig_SrcPeripheral(n) (((n&0x1F)<<1)) /**< Source peripheral*/ |
| frank26080115 | 0:84d7747641aa | 136 | #define GPDMA_DMACCxConfig_DestPeripheral(n) (((n&0x1F)<<6)) /**< Destination peripheral*/ |
| frank26080115 | 0:84d7747641aa | 137 | #define GPDMA_DMACCxConfig_TransferType(n) (((n&0x7)<<11)) /**< This value indicates the type of transfer*/ |
| frank26080115 | 0:84d7747641aa | 138 | #define GPDMA_DMACCxConfig_IE ((1UL<<14)) /**< Interrupt error mask*/ |
| frank26080115 | 0:84d7747641aa | 139 | #define GPDMA_DMACCxConfig_ITC ((1UL<<15)) /**< Terminal count interrupt mask*/ |
| frank26080115 | 0:84d7747641aa | 140 | #define GPDMA_DMACCxConfig_L ((1UL<<16)) /**< Lock*/ |
| frank26080115 | 0:84d7747641aa | 141 | #define GPDMA_DMACCxConfig_A ((1UL<<17)) /**< Active*/ |
| frank26080115 | 0:84d7747641aa | 142 | #define GPDMA_DMACCxConfig_H ((1UL<<18)) /**< Halt*/ |
| frank26080115 | 0:84d7747641aa | 143 | /** DMA Channel Configuration registers bit mask */ |
| frank26080115 | 0:84d7747641aa | 144 | #define GPDMA_DMACCxConfig_BITMASK ((0x7FFFF)) |
| frank26080115 | 0:84d7747641aa | 145 | |
| frank26080115 | 0:84d7747641aa | 146 | |
| frank26080115 | 0:84d7747641aa | 147 | /** |
| frank26080115 | 0:84d7747641aa | 148 | * @} |
| frank26080115 | 0:84d7747641aa | 149 | */ |
| frank26080115 | 0:84d7747641aa | 150 | |
| frank26080115 | 0:84d7747641aa | 151 | /** |
| frank26080115 | 0:84d7747641aa | 152 | * @} |
| frank26080115 | 0:84d7747641aa | 153 | */ |
| frank26080115 | 0:84d7747641aa | 154 | |
| frank26080115 | 0:84d7747641aa | 155 | |
| frank26080115 | 0:84d7747641aa | 156 | /* Public Types --------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 157 | /** @defgroup GPDMA_Public_Types |
| frank26080115 | 0:84d7747641aa | 158 | * @{ |
| frank26080115 | 0:84d7747641aa | 159 | */ |
| frank26080115 | 0:84d7747641aa | 160 | |
| frank26080115 | 0:84d7747641aa | 161 | |
| frank26080115 | 0:84d7747641aa | 162 | /** |
| frank26080115 | 0:84d7747641aa | 163 | * @brief GPDMA Channel configuration structure type definition |
| frank26080115 | 0:84d7747641aa | 164 | */ |
| frank26080115 | 0:84d7747641aa | 165 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 166 | uint32_t ChannelNum; /**< DMA channel number, should be in |
| frank26080115 | 0:84d7747641aa | 167 | range from 0 to 7. |
| frank26080115 | 0:84d7747641aa | 168 | Note: DMA channel 0 has the highest priority |
| frank26080115 | 0:84d7747641aa | 169 | and DMA channel 7 the lowest priority. |
| frank26080115 | 0:84d7747641aa | 170 | */ |
| frank26080115 | 0:84d7747641aa | 171 | uint32_t TransferSize; /**< Length/Size of transfer */ |
| frank26080115 | 0:84d7747641aa | 172 | uint32_t TransferWidth; /**< Transfer width - used for TransferType is GPDMA_TRANSFERTYPE_M2M only */ |
| frank26080115 | 0:84d7747641aa | 173 | uint32_t SrcMemAddr; /**< Physical Source Address, used in case TransferType is chosen as |
| frank26080115 | 0:84d7747641aa | 174 | GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_M2P */ |
| frank26080115 | 0:84d7747641aa | 175 | uint32_t DstMemAddr; /**< Physical Destination Address, used in case TransferType is chosen as |
| frank26080115 | 0:84d7747641aa | 176 | GPDMA_TRANSFERTYPE_M2M or GPDMA_TRANSFERTYPE_P2M */ |
| frank26080115 | 0:84d7747641aa | 177 | uint32_t TransferType; /**< Transfer Type, should be one of the following: |
| frank26080115 | 0:84d7747641aa | 178 | - GPDMA_TRANSFERTYPE_M2M: Memory to memory - DMA control |
| frank26080115 | 0:84d7747641aa | 179 | - GPDMA_TRANSFERTYPE_M2P: Memory to peripheral - DMA control |
| frank26080115 | 0:84d7747641aa | 180 | - GPDMA_TRANSFERTYPE_P2M: Peripheral to memory - DMA control |
| frank26080115 | 0:84d7747641aa | 181 | - GPDMA_TRANSFERTYPE_P2P: Source peripheral to destination peripheral - DMA control |
| frank26080115 | 0:84d7747641aa | 182 | */ |
| frank26080115 | 0:84d7747641aa | 183 | uint32_t SrcConn; /**< Peripheral Source Connection type, used in case TransferType is chosen as |
| frank26080115 | 0:84d7747641aa | 184 | GPDMA_TRANSFERTYPE_P2M or GPDMA_TRANSFERTYPE_P2P, should be one of |
| frank26080115 | 0:84d7747641aa | 185 | following: |
| frank26080115 | 0:84d7747641aa | 186 | - GPDMA_CONN_SSP0_Tx: SSP0, Tx |
| frank26080115 | 0:84d7747641aa | 187 | - GPDMA_CONN_SSP0_Rx: SSP0, Rx |
| frank26080115 | 0:84d7747641aa | 188 | - GPDMA_CONN_SSP1_Tx: SSP1, Tx |
| frank26080115 | 0:84d7747641aa | 189 | - GPDMA_CONN_SSP1_Rx: SSP1, Rx |
| frank26080115 | 0:84d7747641aa | 190 | - GPDMA_CONN_ADC: ADC |
| frank26080115 | 0:84d7747641aa | 191 | - GPDMA_CONN_I2S_Channel_0: I2S Channel 0 |
| frank26080115 | 0:84d7747641aa | 192 | - GPDMA_CONN_I2S_Channel_1: I2S Channel 1 |
| frank26080115 | 0:84d7747641aa | 193 | - GPDMA_CONN_DAC: DAC |
| frank26080115 | 0:84d7747641aa | 194 | - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0 |
| frank26080115 | 0:84d7747641aa | 195 | - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1 |
| frank26080115 | 0:84d7747641aa | 196 | - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0 |
| frank26080115 | 0:84d7747641aa | 197 | - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1 |
| frank26080115 | 0:84d7747641aa | 198 | - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0 |
| frank26080115 | 0:84d7747641aa | 199 | - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1 |
| frank26080115 | 0:84d7747641aa | 200 | - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0 |
| frank26080115 | 0:84d7747641aa | 201 | - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1 |
| frank26080115 | 0:84d7747641aa | 202 | */ |
| frank26080115 | 0:84d7747641aa | 203 | uint32_t DstConn; /**< Peripheral Destination Connection type, used in case TransferType is chosen as |
| frank26080115 | 0:84d7747641aa | 204 | GPDMA_TRANSFERTYPE_M2P or GPDMA_TRANSFERTYPE_P2P, should be one of |
| frank26080115 | 0:84d7747641aa | 205 | following: |
| frank26080115 | 0:84d7747641aa | 206 | - GPDMA_CONN_SSP0_Tx: SSP0, Tx |
| frank26080115 | 0:84d7747641aa | 207 | - GPDMA_CONN_SSP0_Rx: SSP0, Rx |
| frank26080115 | 0:84d7747641aa | 208 | - GPDMA_CONN_SSP1_Tx: SSP1, Tx |
| frank26080115 | 0:84d7747641aa | 209 | - GPDMA_CONN_SSP1_Rx: SSP1, Rx |
| frank26080115 | 0:84d7747641aa | 210 | - GPDMA_CONN_ADC: ADC |
| frank26080115 | 0:84d7747641aa | 211 | - GPDMA_CONN_I2S_Channel_0: I2S Channel 0 |
| frank26080115 | 0:84d7747641aa | 212 | - GPDMA_CONN_I2S_Channel_1: I2S Channel 1 |
| frank26080115 | 0:84d7747641aa | 213 | - GPDMA_CONN_DAC: DAC |
| frank26080115 | 0:84d7747641aa | 214 | - GPDMA_CONN_UART0_Tx_MAT0_0: UART0 Tx / MAT0.0 |
| frank26080115 | 0:84d7747641aa | 215 | - GPDMA_CONN_UART0_Rx_MAT0_1: UART0 Rx / MAT0.1 |
| frank26080115 | 0:84d7747641aa | 216 | - GPDMA_CONN_UART1_Tx_MAT1_0: UART1 Tx / MAT1.0 |
| frank26080115 | 0:84d7747641aa | 217 | - GPDMA_CONN_UART1_Rx_MAT1_1: UART1 Rx / MAT1.1 |
| frank26080115 | 0:84d7747641aa | 218 | - GPDMA_CONN_UART2_Tx_MAT2_0: UART2 Tx / MAT2.0 |
| frank26080115 | 0:84d7747641aa | 219 | - GPDMA_CONN_UART2_Rx_MAT2_1: UART2 Rx / MAT2.1 |
| frank26080115 | 0:84d7747641aa | 220 | - GPDMA_CONN_UART3_Tx_MAT3_0: UART3 Tx / MAT3.0 |
| frank26080115 | 0:84d7747641aa | 221 | - GPDMA_CONN_UART3_Rx_MAT3_1: UART3 Rx / MAT3.1 |
| frank26080115 | 0:84d7747641aa | 222 | */ |
| frank26080115 | 0:84d7747641aa | 223 | uint32_t DMALLI; /**< Linker List Item structure data address |
| frank26080115 | 0:84d7747641aa | 224 | if there's no Linker List, set as '0' |
| frank26080115 | 0:84d7747641aa | 225 | */ |
| frank26080115 | 0:84d7747641aa | 226 | } GPDMA_Channel_CFG_Type; |
| frank26080115 | 0:84d7747641aa | 227 | |
| frank26080115 | 0:84d7747641aa | 228 | |
| frank26080115 | 0:84d7747641aa | 229 | /** |
| frank26080115 | 0:84d7747641aa | 230 | * @brief GPDMA Linker List Item structure type definition |
| frank26080115 | 0:84d7747641aa | 231 | */ |
| frank26080115 | 0:84d7747641aa | 232 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 233 | uint32_t SrcAddr; /**< Source Address */ |
| frank26080115 | 0:84d7747641aa | 234 | uint32_t DstAddr; /**< Destination address */ |
| frank26080115 | 0:84d7747641aa | 235 | uint32_t NextLLI; /**< Next LLI address, otherwise set to '0' */ |
| frank26080115 | 0:84d7747641aa | 236 | uint32_t Control; /**< GPDMA Control of this LLI */ |
| frank26080115 | 0:84d7747641aa | 237 | } GPDMA_LLI_Type; |
| frank26080115 | 0:84d7747641aa | 238 | |
| frank26080115 | 0:84d7747641aa | 239 | |
| frank26080115 | 0:84d7747641aa | 240 | /** GPDMA call-back function type definitions */ |
| frank26080115 | 0:84d7747641aa | 241 | typedef void (fnGPDMACbs_Type)(uint32_t channelStatus); |
| frank26080115 | 0:84d7747641aa | 242 | |
| frank26080115 | 0:84d7747641aa | 243 | |
| frank26080115 | 0:84d7747641aa | 244 | /** |
| frank26080115 | 0:84d7747641aa | 245 | * @} |
| frank26080115 | 0:84d7747641aa | 246 | */ |
| frank26080115 | 0:84d7747641aa | 247 | |
| frank26080115 | 0:84d7747641aa | 248 | |
| frank26080115 | 0:84d7747641aa | 249 | /* Public Macros -------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 250 | /** @defgroup GPDMA_Public_Macros |
| frank26080115 | 0:84d7747641aa | 251 | * @{ |
| frank26080115 | 0:84d7747641aa | 252 | */ |
| frank26080115 | 0:84d7747641aa | 253 | |
| frank26080115 | 0:84d7747641aa | 254 | #define PARAM_GPDMA_CHANNEL(n) ((n>=0) && (n<=7)) |
| frank26080115 | 0:84d7747641aa | 255 | |
| frank26080115 | 0:84d7747641aa | 256 | /** DMA Connection number definitions */ |
| frank26080115 | 0:84d7747641aa | 257 | #define GPDMA_CONN_SSP0_Tx ((0UL)) /**< SSP0 Tx */ |
| frank26080115 | 0:84d7747641aa | 258 | #define GPDMA_CONN_SSP0_Rx ((1UL)) /**< SSP0 Rx */ |
| frank26080115 | 0:84d7747641aa | 259 | #define GPDMA_CONN_SSP1_Tx ((2UL)) /**< SSP1 Tx */ |
| frank26080115 | 0:84d7747641aa | 260 | #define GPDMA_CONN_SSP1_Rx ((3UL)) /**< SSP1 Rx */ |
| frank26080115 | 0:84d7747641aa | 261 | #define GPDMA_CONN_ADC ((4UL)) /**< ADC */ |
| frank26080115 | 0:84d7747641aa | 262 | #define GPDMA_CONN_I2S_Channel_0 ((5UL)) /**< I2S channel 0 */ |
| frank26080115 | 0:84d7747641aa | 263 | #define GPDMA_CONN_I2S_Channel_1 ((6UL)) /**< I2S channel 1 */ |
| frank26080115 | 0:84d7747641aa | 264 | #define GPDMA_CONN_DAC ((7UL)) /**< DAC */ |
| frank26080115 | 0:84d7747641aa | 265 | #define GPDMA_CONN_UART0_Tx ((8UL)) /**< UART0 Tx */ |
| frank26080115 | 0:84d7747641aa | 266 | #define GPDMA_CONN_UART0_Rx ((9UL)) /**< UART0 Rx */ |
| frank26080115 | 0:84d7747641aa | 267 | #define GPDMA_CONN_UART1_Tx ((10UL)) /**< UART1 Tx */ |
| frank26080115 | 0:84d7747641aa | 268 | #define GPDMA_CONN_UART1_Rx ((11UL)) /**< UART1 Rx */ |
| frank26080115 | 0:84d7747641aa | 269 | #define GPDMA_CONN_UART2_Tx ((12UL)) /**< UART2 Tx */ |
| frank26080115 | 0:84d7747641aa | 270 | #define GPDMA_CONN_UART2_Rx ((13UL)) /**< UART2 Rx */ |
| frank26080115 | 0:84d7747641aa | 271 | #define GPDMA_CONN_UART3_Tx ((14UL)) /**< UART3 Tx */ |
| frank26080115 | 0:84d7747641aa | 272 | #define GPDMA_CONN_UART3_Rx ((15UL)) /**< UART3 Rx */ |
| frank26080115 | 0:84d7747641aa | 273 | #define GPDMA_CONN_MAT0_0 ((16UL)) /**< MAT0.0 */ |
| frank26080115 | 0:84d7747641aa | 274 | #define GPDMA_CONN_MAT0_1 ((17UL)) /**< MAT0.1 */ |
| frank26080115 | 0:84d7747641aa | 275 | #define GPDMA_CONN_MAT1_0 ((18UL)) /**< MAT1.0 */ |
| frank26080115 | 0:84d7747641aa | 276 | #define GPDMA_CONN_MAT1_1 ((19UL)) /**< MAT1.1 */ |
| frank26080115 | 0:84d7747641aa | 277 | #define GPDMA_CONN_MAT2_0 ((20UL)) /**< MAT2.0 */ |
| frank26080115 | 0:84d7747641aa | 278 | #define GPDMA_CONN_MAT2_1 ((21UL)) /**< MAT2.1 */ |
| frank26080115 | 0:84d7747641aa | 279 | #define GPDMA_CONN_MAT3_0 ((22UL)) /**< MAT3.0 */ |
| frank26080115 | 0:84d7747641aa | 280 | #define GPDMA_CONN_MAT3_1 ((23UL)) /**< MAT3.1 */ |
| frank26080115 | 0:84d7747641aa | 281 | |
| frank26080115 | 0:84d7747641aa | 282 | #define PARAM_GPDMA_CONN(n) ((n==GPDMA_CONN_SSP0_Tx) || (n==GPDMA_CONN_SSP0_Rx) \ |
| frank26080115 | 0:84d7747641aa | 283 | || (n==GPDMA_CONN_SSP1_Tx) || (n==GPDMA_CONN_SSP1_Rx) \ |
| frank26080115 | 0:84d7747641aa | 284 | || (n==GPDMA_CONN_ADC) || (n==GPDMA_CONN_I2S_Channel_0) \ |
| frank26080115 | 0:84d7747641aa | 285 | || (n==GPDMA_CONN_I2S_Channel_1) || (n==GPDMA_CONN_DAC) \ |
| frank26080115 | 0:84d7747641aa | 286 | || (n==GPDMA_CONN_UART0_Tx) || (n==GPDMA_CONN_UART0_Rx) \ |
| frank26080115 | 0:84d7747641aa | 287 | || (n==GPDMA_CONN_UART1_Tx) || (n==GPDMA_CONN_UART1_Rx) \ |
| frank26080115 | 0:84d7747641aa | 288 | || (n==GPDMA_CONN_UART2_Tx) || (n==GPDMA_CONN_UART2_Rx) \ |
| frank26080115 | 0:84d7747641aa | 289 | || (n==GPDMA_CONN_UART3_Tx) || (n==GPDMA_CONN_UART3_Rx) \ |
| frank26080115 | 0:84d7747641aa | 290 | || (n==GPDMA_CONN_MAT0_0) || (n==GPDMA_CONN_MAT0_1) \ |
| frank26080115 | 0:84d7747641aa | 291 | || (n==GPDMA_CONN_MAT1_0) || (n==GPDMA_CONN_MAT1_1) \ |
| frank26080115 | 0:84d7747641aa | 292 | || (n==GPDMA_CONN_MAT2_0) || (n==GPDMA_CONN_MAT2_1) \ |
| frank26080115 | 0:84d7747641aa | 293 | || (n==GPDMA_CONN_MAT3_0) || (n==GPDMA_CONN_MAT3_1)) |
| frank26080115 | 0:84d7747641aa | 294 | |
| frank26080115 | 0:84d7747641aa | 295 | |
| frank26080115 | 0:84d7747641aa | 296 | /** GPDMA Transfer type definitions */ |
| frank26080115 | 0:84d7747641aa | 297 | #define GPDMA_TRANSFERTYPE_M2M ((0UL)) /**< Memory to memory - DMA control */ |
| frank26080115 | 0:84d7747641aa | 298 | #define GPDMA_TRANSFERTYPE_M2P ((1UL)) /**< Memory to peripheral - DMA control */ |
| frank26080115 | 0:84d7747641aa | 299 | #define GPDMA_TRANSFERTYPE_P2M ((2UL)) /**< Peripheral to memory - DMA control */ |
| frank26080115 | 0:84d7747641aa | 300 | #define GPDMA_TRANSFERTYPE_P2P ((3UL)) /**< Source peripheral to destination peripheral - DMA control */ |
| frank26080115 | 0:84d7747641aa | 301 | |
| frank26080115 | 0:84d7747641aa | 302 | |
| frank26080115 | 0:84d7747641aa | 303 | #define PARAM_GPDMA_TRANSFERTYPE(n) ((n==GPDMA_TRANSFERTYPE_M2M)||(n==GPDMA_TRANSFERTYPE_M2P) \ |
| frank26080115 | 0:84d7747641aa | 304 | ||(n==GPDMA_TRANSFERTYPE_P2M)||(n==GPDMA_TRANSFERTYPE_P2P)) |
| frank26080115 | 0:84d7747641aa | 305 | |
| frank26080115 | 0:84d7747641aa | 306 | |
| frank26080115 | 0:84d7747641aa | 307 | /** Burst size in Source and Destination definitions */ |
| frank26080115 | 0:84d7747641aa | 308 | #define GPDMA_BSIZE_1 ((0UL)) /**< Burst size = 1 */ |
| frank26080115 | 0:84d7747641aa | 309 | #define GPDMA_BSIZE_4 ((1UL)) /**< Burst size = 4 */ |
| frank26080115 | 0:84d7747641aa | 310 | #define GPDMA_BSIZE_8 ((2UL)) /**< Burst size = 8 */ |
| frank26080115 | 0:84d7747641aa | 311 | #define GPDMA_BSIZE_16 ((3UL)) /**< Burst size = 16 */ |
| frank26080115 | 0:84d7747641aa | 312 | #define GPDMA_BSIZE_32 ((4UL)) /**< Burst size = 32 */ |
| frank26080115 | 0:84d7747641aa | 313 | #define GPDMA_BSIZE_64 ((5UL)) /**< Burst size = 64 */ |
| frank26080115 | 0:84d7747641aa | 314 | #define GPDMA_BSIZE_128 ((6UL)) /**< Burst size = 128 */ |
| frank26080115 | 0:84d7747641aa | 315 | #define GPDMA_BSIZE_256 ((7UL)) /**< Burst size = 256 */ |
| frank26080115 | 0:84d7747641aa | 316 | |
| frank26080115 | 0:84d7747641aa | 317 | #define PARAM_GPDMA_BSIZE(n) ((n==GPDMA_BSIZE_1) || (n==GPDMA_BSIZE_4) \ |
| frank26080115 | 0:84d7747641aa | 318 | || (n==GPDMA_BSIZE_8) || (n==GPDMA_BSIZE_16) \ |
| frank26080115 | 0:84d7747641aa | 319 | || (n==GPDMA_BSIZE_32) || (n==GPDMA_BSIZE_64) \ |
| frank26080115 | 0:84d7747641aa | 320 | || (n==GPDMA_BSIZE_128) || (n==GPDMA_BSIZE_256)) |
| frank26080115 | 0:84d7747641aa | 321 | |
| frank26080115 | 0:84d7747641aa | 322 | |
| frank26080115 | 0:84d7747641aa | 323 | /** Width in Source transfer width and Destination transfer width definitions */ |
| frank26080115 | 0:84d7747641aa | 324 | #define GPDMA_WIDTH_BYTE ((0UL)) /**< Width = 1 byte */ |
| frank26080115 | 0:84d7747641aa | 325 | #define GPDMA_WIDTH_HALFWORD ((1UL)) /**< Width = 2 bytes */ |
| frank26080115 | 0:84d7747641aa | 326 | #define GPDMA_WIDTH_WORD ((2UL)) /**< Width = 4 bytes */ |
| frank26080115 | 0:84d7747641aa | 327 | |
| frank26080115 | 0:84d7747641aa | 328 | #define PARAM_GPDMA_WIDTH(n) ((n==GPDMA_WIDTH_BYTE) || (n==GPDMA_WIDTH_HALFWORD) \ |
| frank26080115 | 0:84d7747641aa | 329 | || (n==GPDMA_WIDTH_WORD)) |
| frank26080115 | 0:84d7747641aa | 330 | |
| frank26080115 | 0:84d7747641aa | 331 | |
| frank26080115 | 0:84d7747641aa | 332 | /** DMA Request Select Mode definitions */ |
| frank26080115 | 0:84d7747641aa | 333 | #define GPDMA_REQSEL_UART ((0UL)) /**< UART TX/RX is selected */ |
| frank26080115 | 0:84d7747641aa | 334 | #define GPDMA_REQSEL_TIMER ((1UL)) /**< Timer match is selected */ |
| frank26080115 | 0:84d7747641aa | 335 | |
| frank26080115 | 0:84d7747641aa | 336 | #define PARAM_GPDMA_REQSEL(n) ((n==GPDMA_REQSEL_UART) || (n==GPDMA_REQSEL_TIMER)) |
| frank26080115 | 0:84d7747641aa | 337 | |
| frank26080115 | 0:84d7747641aa | 338 | /** GPDMA Status type definitions */ |
| frank26080115 | 0:84d7747641aa | 339 | /** GPDMA Interrupt Status */ |
| frank26080115 | 0:84d7747641aa | 340 | #define GPDMA_STAT_INT ((0UL)) |
| frank26080115 | 0:84d7747641aa | 341 | /** GPDMA Interrupt Terminal Count Request Status */ |
| frank26080115 | 0:84d7747641aa | 342 | #define GPDMA_STAT_INTTC ((1UL)) |
| frank26080115 | 0:84d7747641aa | 343 | /** GPDMA Interrupt Error Status */ |
| frank26080115 | 0:84d7747641aa | 344 | #define GPDMA_STAT_INTERR ((2UL)) |
| frank26080115 | 0:84d7747641aa | 345 | /** GPDMA Raw Interrupt Terminal Count Status */ |
| frank26080115 | 0:84d7747641aa | 346 | #define GPDMA_STAT_RAWINTTC ((3UL)) |
| frank26080115 | 0:84d7747641aa | 347 | /** GPDMA Raw Error Interrupt Status */ |
| frank26080115 | 0:84d7747641aa | 348 | #define GPDMA_STAT_RAWINTERR ((4UL)) |
| frank26080115 | 0:84d7747641aa | 349 | /** DMA Enabled Channel Status */ |
| frank26080115 | 0:84d7747641aa | 350 | #define GPDMA_STAT_ENABLED_CH ((5UL)) |
| frank26080115 | 0:84d7747641aa | 351 | |
| frank26080115 | 0:84d7747641aa | 352 | #define PARAM_GPDMA_STAT(n) ((n==GPDMA_STAT_INT) || (n==GPDMA_STAT_INTTC) \ |
| frank26080115 | 0:84d7747641aa | 353 | || (n==GPDMA_STAT_INTERR) || (n==GPDMA_STAT_RAWINTTC) \ |
| frank26080115 | 0:84d7747641aa | 354 | || (n==GPDMA_STAT_RAWINTERR) || (n==GPDMA_STAT_ENABLED_CH)) |
| frank26080115 | 0:84d7747641aa | 355 | |
| frank26080115 | 0:84d7747641aa | 356 | /** GPDMA status type definition that can be clear */ |
| frank26080115 | 0:84d7747641aa | 357 | /** GPDMA Interrupt Terminal Count Request Clear */ |
| frank26080115 | 0:84d7747641aa | 358 | #define GPDMA_STATCLR_INTTC ((0UL)) |
| frank26080115 | 0:84d7747641aa | 359 | /** GPDMA Interrupt Error Clear */ |
| frank26080115 | 0:84d7747641aa | 360 | #define GPDMA_STATCLR_INTERR ((1UL)) |
| frank26080115 | 0:84d7747641aa | 361 | |
| frank26080115 | 0:84d7747641aa | 362 | #define GPDMA_STATCLR(n) ((n==GPDMA_STATCLR_INTTC) || (n==GPDMA_STATCLR_INTERR)) |
| frank26080115 | 0:84d7747641aa | 363 | |
| frank26080115 | 0:84d7747641aa | 364 | /** |
| frank26080115 | 0:84d7747641aa | 365 | * @} |
| frank26080115 | 0:84d7747641aa | 366 | */ |
| frank26080115 | 0:84d7747641aa | 367 | |
| frank26080115 | 0:84d7747641aa | 368 | |
| frank26080115 | 0:84d7747641aa | 369 | /* Public Functions ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 370 | /** @defgroup GPDMA_Public_Functions |
| frank26080115 | 0:84d7747641aa | 371 | * @{ |
| frank26080115 | 0:84d7747641aa | 372 | */ |
| frank26080115 | 0:84d7747641aa | 373 | |
| frank26080115 | 0:84d7747641aa | 374 | void GPDMA_Init(void); |
| frank26080115 | 0:84d7747641aa | 375 | Status GPDMA_Setup(GPDMA_Channel_CFG_Type *GPDMAChannelConfig, fnGPDMACbs_Type *pfnGPDMACbs); |
| frank26080115 | 0:84d7747641aa | 376 | void GPDMA_ChannelCmd(uint8_t channelNum, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 377 | void GPDMA_IntHandler(void); |
| frank26080115 | 0:84d7747641aa | 378 | |
| frank26080115 | 0:84d7747641aa | 379 | /** |
| frank26080115 | 0:84d7747641aa | 380 | * @} |
| frank26080115 | 0:84d7747641aa | 381 | */ |
| frank26080115 | 0:84d7747641aa | 382 | |
| frank26080115 | 0:84d7747641aa | 383 | |
| frank26080115 | 0:84d7747641aa | 384 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 385 | } |
| frank26080115 | 0:84d7747641aa | 386 | #endif |
| frank26080115 | 0:84d7747641aa | 387 | |
| frank26080115 | 0:84d7747641aa | 388 | #endif /* LPC17XX_GPDMA_H_ */ |
| frank26080115 | 0:84d7747641aa | 389 | |
| frank26080115 | 0:84d7747641aa | 390 | /** |
| frank26080115 | 0:84d7747641aa | 391 | * @} |
| frank26080115 | 0:84d7747641aa | 392 | */ |
| frank26080115 | 0:84d7747641aa | 393 | |
| frank26080115 | 0:84d7747641aa | 394 | /* --------------------------------- End Of File ------------------------------ */ |