Frank 26080115
Date: March 20, 2011 This library is created from "LPC17xx CMSIS-Compliant Standard Peripheral Firmware Driver Library (GNU, Keil, IAR) (Jan 28, 2011)", available from NXP's website, under "All microcontrollers support documents" [[http://ics.nxp.com/support/documents/microcontrollers/?type=software]] You will need to follow [[/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h]] while using this library Examples provided here [[/users/frank26080115/programs/LPC1700CMSIS_Examples/]] The beautiful thing is that NXP does not place copyright protection on any of the files in here Only a few modifications are made to make it compile with the mbed online compiler, I fixed some warnings as well. This is untested as of March 20, 2011 Forum post about this library: [[/forum/mbed/topic/2030/]]
lpc17xx_emac.h@0:84d7747641aa, 2011-03-20 (annotated)
- Committer:
- frank26080115
- Date:
- Sun Mar 20 18:45:15 2011 +0000
- Revision:
- 0:84d7747641aa
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| frank26080115 | 0:84d7747641aa | 1 | /***********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 2 | * @file lpc17xx_emac.h |
| frank26080115 | 0:84d7747641aa | 3 | * @brief Contains all macro definitions and function prototypes |
| frank26080115 | 0:84d7747641aa | 4 | * support for Ethernet MAC firmware library on LPC17xx |
| frank26080115 | 0:84d7747641aa | 5 | * @version 2.0 |
| frank26080115 | 0:84d7747641aa | 6 | * @date 21. May. 2010 |
| frank26080115 | 0:84d7747641aa | 7 | * @author NXP MCU SW Application Team |
| frank26080115 | 0:84d7747641aa | 8 | ************************************************************************** |
| frank26080115 | 0:84d7747641aa | 9 | * Software that is described herein is for illustrative purposes only |
| frank26080115 | 0:84d7747641aa | 10 | * which provides customers with programming information regarding the |
| frank26080115 | 0:84d7747641aa | 11 | * products. This software is supplied "AS IS" without any warranties. |
| frank26080115 | 0:84d7747641aa | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| frank26080115 | 0:84d7747641aa | 13 | * use of the software, conveys no license or title under any patent, |
| frank26080115 | 0:84d7747641aa | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| frank26080115 | 0:84d7747641aa | 15 | * reserves the right to make changes in the software without |
| frank26080115 | 0:84d7747641aa | 16 | * notification. NXP Semiconductors also make no representation or |
| frank26080115 | 0:84d7747641aa | 17 | * warranty that such application will be suitable for the specified |
| frank26080115 | 0:84d7747641aa | 18 | * use without further testing or modification. |
| frank26080115 | 0:84d7747641aa | 19 | **************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 20 | |
| frank26080115 | 0:84d7747641aa | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 22 | /** @defgroup EMAC EMAC |
| frank26080115 | 0:84d7747641aa | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| frank26080115 | 0:84d7747641aa | 24 | * @{ |
| frank26080115 | 0:84d7747641aa | 25 | */ |
| frank26080115 | 0:84d7747641aa | 26 | |
| frank26080115 | 0:84d7747641aa | 27 | #ifndef LPC17XX_EMAC_H_ |
| frank26080115 | 0:84d7747641aa | 28 | #define LPC17XX_EMAC_H_ |
| frank26080115 | 0:84d7747641aa | 29 | |
| frank26080115 | 0:84d7747641aa | 30 | /* Includes ------------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 31 | #include "LPC17xx.h" |
| frank26080115 | 0:84d7747641aa | 32 | #include "lpc_types.h" |
| frank26080115 | 0:84d7747641aa | 33 | |
| frank26080115 | 0:84d7747641aa | 34 | |
| frank26080115 | 0:84d7747641aa | 35 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 36 | extern "C" |
| frank26080115 | 0:84d7747641aa | 37 | { |
| frank26080115 | 0:84d7747641aa | 38 | #endif |
| frank26080115 | 0:84d7747641aa | 39 | |
| frank26080115 | 0:84d7747641aa | 40 | #define MCB_LPC_1768 |
| frank26080115 | 0:84d7747641aa | 41 | //#define IAR_LPC_1768 |
| frank26080115 | 0:84d7747641aa | 42 | |
| frank26080115 | 0:84d7747641aa | 43 | /* Public Macros -------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 44 | /** @defgroup EMAC_Public_Macros EMAC Public Macros |
| frank26080115 | 0:84d7747641aa | 45 | * @{ |
| frank26080115 | 0:84d7747641aa | 46 | */ |
| frank26080115 | 0:84d7747641aa | 47 | |
| frank26080115 | 0:84d7747641aa | 48 | |
| frank26080115 | 0:84d7747641aa | 49 | /* EMAC PHY status type definitions */ |
| frank26080115 | 0:84d7747641aa | 50 | #define EMAC_PHY_STAT_LINK (0) /**< Link Status */ |
| frank26080115 | 0:84d7747641aa | 51 | #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */ |
| frank26080115 | 0:84d7747641aa | 52 | #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */ |
| frank26080115 | 0:84d7747641aa | 53 | |
| frank26080115 | 0:84d7747641aa | 54 | /* EMAC PHY device Speed definitions */ |
| frank26080115 | 0:84d7747641aa | 55 | #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */ |
| frank26080115 | 0:84d7747641aa | 56 | #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */ |
| frank26080115 | 0:84d7747641aa | 57 | #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */ |
| frank26080115 | 0:84d7747641aa | 58 | #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */ |
| frank26080115 | 0:84d7747641aa | 59 | #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */ |
| frank26080115 | 0:84d7747641aa | 60 | |
| frank26080115 | 0:84d7747641aa | 61 | /** |
| frank26080115 | 0:84d7747641aa | 62 | * @} |
| frank26080115 | 0:84d7747641aa | 63 | */ |
| frank26080115 | 0:84d7747641aa | 64 | /* Private Macros ------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 65 | /** @defgroup EMAC_Private_Macros EMAC Private Macros |
| frank26080115 | 0:84d7747641aa | 66 | * @{ |
| frank26080115 | 0:84d7747641aa | 67 | */ |
| frank26080115 | 0:84d7747641aa | 68 | |
| frank26080115 | 0:84d7747641aa | 69 | |
| frank26080115 | 0:84d7747641aa | 70 | /* EMAC Memory Buffer configuration for 16K Ethernet RAM */ |
| frank26080115 | 0:84d7747641aa | 71 | #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */ |
| frank26080115 | 0:84d7747641aa | 72 | #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */ |
| frank26080115 | 0:84d7747641aa | 73 | #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */ |
| frank26080115 | 0:84d7747641aa | 74 | #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */ |
| frank26080115 | 0:84d7747641aa | 75 | |
| frank26080115 | 0:84d7747641aa | 76 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 77 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 78 | * Macro defines for MAC Configuration Register 1 |
| frank26080115 | 0:84d7747641aa | 79 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 80 | #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */ |
| frank26080115 | 0:84d7747641aa | 81 | #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */ |
| frank26080115 | 0:84d7747641aa | 82 | #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */ |
| frank26080115 | 0:84d7747641aa | 83 | #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */ |
| frank26080115 | 0:84d7747641aa | 84 | #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */ |
| frank26080115 | 0:84d7747641aa | 85 | #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */ |
| frank26080115 | 0:84d7747641aa | 86 | #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */ |
| frank26080115 | 0:84d7747641aa | 87 | #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */ |
| frank26080115 | 0:84d7747641aa | 88 | #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */ |
| frank26080115 | 0:84d7747641aa | 89 | #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */ |
| frank26080115 | 0:84d7747641aa | 90 | #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */ |
| frank26080115 | 0:84d7747641aa | 91 | |
| frank26080115 | 0:84d7747641aa | 92 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 93 | * Macro defines for MAC Configuration Register 2 |
| frank26080115 | 0:84d7747641aa | 94 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 95 | #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */ |
| frank26080115 | 0:84d7747641aa | 96 | #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */ |
| frank26080115 | 0:84d7747641aa | 97 | #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */ |
| frank26080115 | 0:84d7747641aa | 98 | #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */ |
| frank26080115 | 0:84d7747641aa | 99 | #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */ |
| frank26080115 | 0:84d7747641aa | 100 | #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */ |
| frank26080115 | 0:84d7747641aa | 101 | #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */ |
| frank26080115 | 0:84d7747641aa | 102 | #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */ |
| frank26080115 | 0:84d7747641aa | 103 | #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */ |
| frank26080115 | 0:84d7747641aa | 104 | #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */ |
| frank26080115 | 0:84d7747641aa | 105 | #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */ |
| frank26080115 | 0:84d7747641aa | 106 | #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */ |
| frank26080115 | 0:84d7747641aa | 107 | #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */ |
| frank26080115 | 0:84d7747641aa | 108 | |
| frank26080115 | 0:84d7747641aa | 109 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 110 | * Macro defines for Back-to-Back Inter-Packet-Gap Register |
| frank26080115 | 0:84d7747641aa | 111 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 112 | /** Programmable field representing the nibble time offset of the minimum possible period |
| frank26080115 | 0:84d7747641aa | 113 | * between the end of any transmitted packet to the beginning of the next */ |
| frank26080115 | 0:84d7747641aa | 114 | #define EMAC_IPGT_BBIPG(n) (n&0x7F) |
| frank26080115 | 0:84d7747641aa | 115 | /** Recommended value for Full Duplex of Programmable field representing the nibble time |
| frank26080115 | 0:84d7747641aa | 116 | * offset of the minimum possible period between the end of any transmitted packet to the |
| frank26080115 | 0:84d7747641aa | 117 | * beginning of the next */ |
| frank26080115 | 0:84d7747641aa | 118 | #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15)) |
| frank26080115 | 0:84d7747641aa | 119 | /** Recommended value for Half Duplex of Programmable field representing the nibble time |
| frank26080115 | 0:84d7747641aa | 120 | * offset of the minimum possible period between the end of any transmitted packet to the |
| frank26080115 | 0:84d7747641aa | 121 | * beginning of the next */ |
| frank26080115 | 0:84d7747641aa | 122 | #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12)) |
| frank26080115 | 0:84d7747641aa | 123 | |
| frank26080115 | 0:84d7747641aa | 124 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 125 | * Macro defines for Non Back-to-Back Inter-Packet-Gap Register |
| frank26080115 | 0:84d7747641aa | 126 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 127 | /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */ |
| frank26080115 | 0:84d7747641aa | 128 | #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F) |
| frank26080115 | 0:84d7747641aa | 129 | /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */ |
| frank26080115 | 0:84d7747641aa | 130 | #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12)) |
| frank26080115 | 0:84d7747641aa | 131 | /** Programmable field representing the optional carrierSense window referenced in |
| frank26080115 | 0:84d7747641aa | 132 | * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */ |
| frank26080115 | 0:84d7747641aa | 133 | #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8) |
| frank26080115 | 0:84d7747641aa | 134 | /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */ |
| frank26080115 | 0:84d7747641aa | 135 | #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C) |
| frank26080115 | 0:84d7747641aa | 136 | |
| frank26080115 | 0:84d7747641aa | 137 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 138 | * Macro defines for Collision Window/Retry Register |
| frank26080115 | 0:84d7747641aa | 139 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 140 | /** Programmable field specifying the number of retransmission attempts following a collision before |
| frank26080115 | 0:84d7747641aa | 141 | * aborting the packet due to excessive collisions */ |
| frank26080115 | 0:84d7747641aa | 142 | #define EMAC_CLRT_MAX_RETX(n) (n&0x0F) |
| frank26080115 | 0:84d7747641aa | 143 | /** Programmable field representing the slot time or collision window during which collisions occur |
| frank26080115 | 0:84d7747641aa | 144 | * in properly configured networks */ |
| frank26080115 | 0:84d7747641aa | 145 | #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8) |
| frank26080115 | 0:84d7747641aa | 146 | /** Default value for Collision Window / Retry register */ |
| frank26080115 | 0:84d7747641aa | 147 | #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37))) |
| frank26080115 | 0:84d7747641aa | 148 | |
| frank26080115 | 0:84d7747641aa | 149 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 150 | * Macro defines for Maximum Frame Register |
| frank26080115 | 0:84d7747641aa | 151 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 152 | /** Represents a maximum receive frame of 1536 octets */ |
| frank26080115 | 0:84d7747641aa | 153 | #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF) |
| frank26080115 | 0:84d7747641aa | 154 | |
| frank26080115 | 0:84d7747641aa | 155 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 156 | * Macro defines for PHY Support Register |
| frank26080115 | 0:84d7747641aa | 157 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 158 | #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */ |
| frank26080115 | 0:84d7747641aa | 159 | #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */ |
| frank26080115 | 0:84d7747641aa | 160 | |
| frank26080115 | 0:84d7747641aa | 161 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 162 | * Macro defines for Test Register |
| frank26080115 | 0:84d7747641aa | 163 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 164 | #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */ |
| frank26080115 | 0:84d7747641aa | 165 | #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */ |
| frank26080115 | 0:84d7747641aa | 166 | #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */ |
| frank26080115 | 0:84d7747641aa | 167 | |
| frank26080115 | 0:84d7747641aa | 168 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 169 | * Macro defines for MII Management Configuration Register |
| frank26080115 | 0:84d7747641aa | 170 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 171 | #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */ |
| frank26080115 | 0:84d7747641aa | 172 | #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */ |
| frank26080115 | 0:84d7747641aa | 173 | #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */ |
| frank26080115 | 0:84d7747641aa | 174 | #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */ |
| frank26080115 | 0:84d7747641aa | 175 | #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */ |
| frank26080115 | 0:84d7747641aa | 176 | |
| frank26080115 | 0:84d7747641aa | 177 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 178 | * Macro defines for MII Management Command Register |
| frank26080115 | 0:84d7747641aa | 179 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 180 | #define EMAC_MCMD_READ 0x00000001 /**< MII Read */ |
| frank26080115 | 0:84d7747641aa | 181 | #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */ |
| frank26080115 | 0:84d7747641aa | 182 | |
| frank26080115 | 0:84d7747641aa | 183 | #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */ |
| frank26080115 | 0:84d7747641aa | 184 | #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */ |
| frank26080115 | 0:84d7747641aa | 185 | |
| frank26080115 | 0:84d7747641aa | 186 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 187 | * Macro defines for MII Management Address Register |
| frank26080115 | 0:84d7747641aa | 188 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 189 | #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */ |
| frank26080115 | 0:84d7747641aa | 190 | #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */ |
| frank26080115 | 0:84d7747641aa | 191 | |
| frank26080115 | 0:84d7747641aa | 192 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 193 | * Macro defines for MII Management Write Data Register |
| frank26080115 | 0:84d7747641aa | 194 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 195 | #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */ |
| frank26080115 | 0:84d7747641aa | 196 | |
| frank26080115 | 0:84d7747641aa | 197 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 198 | * Macro defines for MII Management Read Data Register |
| frank26080115 | 0:84d7747641aa | 199 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 200 | #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */ |
| frank26080115 | 0:84d7747641aa | 201 | |
| frank26080115 | 0:84d7747641aa | 202 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 203 | * Macro defines for MII Management Indicators Register |
| frank26080115 | 0:84d7747641aa | 204 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 205 | #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */ |
| frank26080115 | 0:84d7747641aa | 206 | #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */ |
| frank26080115 | 0:84d7747641aa | 207 | #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */ |
| frank26080115 | 0:84d7747641aa | 208 | #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */ |
| frank26080115 | 0:84d7747641aa | 209 | |
| frank26080115 | 0:84d7747641aa | 210 | /* Station Address 0 Register */ |
| frank26080115 | 0:84d7747641aa | 211 | /* Station Address 1 Register */ |
| frank26080115 | 0:84d7747641aa | 212 | /* Station Address 2 Register */ |
| frank26080115 | 0:84d7747641aa | 213 | |
| frank26080115 | 0:84d7747641aa | 214 | |
| frank26080115 | 0:84d7747641aa | 215 | /* Control register definitions --------------------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 216 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 217 | * Macro defines for Command Register |
| frank26080115 | 0:84d7747641aa | 218 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 219 | #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */ |
| frank26080115 | 0:84d7747641aa | 220 | #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */ |
| frank26080115 | 0:84d7747641aa | 221 | #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */ |
| frank26080115 | 0:84d7747641aa | 222 | #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */ |
| frank26080115 | 0:84d7747641aa | 223 | #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */ |
| frank26080115 | 0:84d7747641aa | 224 | #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */ |
| frank26080115 | 0:84d7747641aa | 225 | #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */ |
| frank26080115 | 0:84d7747641aa | 226 | #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */ |
| frank26080115 | 0:84d7747641aa | 227 | #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */ |
| frank26080115 | 0:84d7747641aa | 228 | #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */ |
| frank26080115 | 0:84d7747641aa | 229 | |
| frank26080115 | 0:84d7747641aa | 230 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 231 | * Macro defines for Status Register |
| frank26080115 | 0:84d7747641aa | 232 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 233 | #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */ |
| frank26080115 | 0:84d7747641aa | 234 | #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */ |
| frank26080115 | 0:84d7747641aa | 235 | |
| frank26080115 | 0:84d7747641aa | 236 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 237 | * Macro defines for Transmit Status Vector 0 Register |
| frank26080115 | 0:84d7747641aa | 238 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 239 | #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */ |
| frank26080115 | 0:84d7747641aa | 240 | #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */ |
| frank26080115 | 0:84d7747641aa | 241 | #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */ |
| frank26080115 | 0:84d7747641aa | 242 | #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */ |
| frank26080115 | 0:84d7747641aa | 243 | #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */ |
| frank26080115 | 0:84d7747641aa | 244 | #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */ |
| frank26080115 | 0:84d7747641aa | 245 | #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */ |
| frank26080115 | 0:84d7747641aa | 246 | #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */ |
| frank26080115 | 0:84d7747641aa | 247 | #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */ |
| frank26080115 | 0:84d7747641aa | 248 | #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */ |
| frank26080115 | 0:84d7747641aa | 249 | #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */ |
| frank26080115 | 0:84d7747641aa | 250 | #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */ |
| frank26080115 | 0:84d7747641aa | 251 | #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */ |
| frank26080115 | 0:84d7747641aa | 252 | #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */ |
| frank26080115 | 0:84d7747641aa | 253 | #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */ |
| frank26080115 | 0:84d7747641aa | 254 | #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */ |
| frank26080115 | 0:84d7747641aa | 255 | #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */ |
| frank26080115 | 0:84d7747641aa | 256 | |
| frank26080115 | 0:84d7747641aa | 257 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 258 | * Macro defines for Transmit Status Vector 1 Register |
| frank26080115 | 0:84d7747641aa | 259 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 260 | #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */ |
| frank26080115 | 0:84d7747641aa | 261 | #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */ |
| frank26080115 | 0:84d7747641aa | 262 | |
| frank26080115 | 0:84d7747641aa | 263 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 264 | * Macro defines for Receive Status Vector Register |
| frank26080115 | 0:84d7747641aa | 265 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 266 | #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */ |
| frank26080115 | 0:84d7747641aa | 267 | #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */ |
| frank26080115 | 0:84d7747641aa | 268 | #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */ |
| frank26080115 | 0:84d7747641aa | 269 | #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */ |
| frank26080115 | 0:84d7747641aa | 270 | #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */ |
| frank26080115 | 0:84d7747641aa | 271 | #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */ |
| frank26080115 | 0:84d7747641aa | 272 | #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */ |
| frank26080115 | 0:84d7747641aa | 273 | #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */ |
| frank26080115 | 0:84d7747641aa | 274 | #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */ |
| frank26080115 | 0:84d7747641aa | 275 | #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */ |
| frank26080115 | 0:84d7747641aa | 276 | #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */ |
| frank26080115 | 0:84d7747641aa | 277 | #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */ |
| frank26080115 | 0:84d7747641aa | 278 | #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */ |
| frank26080115 | 0:84d7747641aa | 279 | #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */ |
| frank26080115 | 0:84d7747641aa | 280 | #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */ |
| frank26080115 | 0:84d7747641aa | 281 | #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */ |
| frank26080115 | 0:84d7747641aa | 282 | |
| frank26080115 | 0:84d7747641aa | 283 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 284 | * Macro defines for Flow Control Counter Register |
| frank26080115 | 0:84d7747641aa | 285 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 286 | #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */ |
| frank26080115 | 0:84d7747641aa | 287 | #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */ |
| frank26080115 | 0:84d7747641aa | 288 | |
| frank26080115 | 0:84d7747641aa | 289 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 290 | * Macro defines for Flow Control Status Register |
| frank26080115 | 0:84d7747641aa | 291 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 292 | #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */ |
| frank26080115 | 0:84d7747641aa | 293 | |
| frank26080115 | 0:84d7747641aa | 294 | |
| frank26080115 | 0:84d7747641aa | 295 | /* Receive filter register definitions -------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 296 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 297 | * Macro defines for Receive Filter Control Register |
| frank26080115 | 0:84d7747641aa | 298 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 299 | #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */ |
| frank26080115 | 0:84d7747641aa | 300 | #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */ |
| frank26080115 | 0:84d7747641aa | 301 | #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */ |
| frank26080115 | 0:84d7747641aa | 302 | #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */ |
| frank26080115 | 0:84d7747641aa | 303 | #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/ |
| frank26080115 | 0:84d7747641aa | 304 | #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */ |
| frank26080115 | 0:84d7747641aa | 305 | #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */ |
| frank26080115 | 0:84d7747641aa | 306 | #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */ |
| frank26080115 | 0:84d7747641aa | 307 | |
| frank26080115 | 0:84d7747641aa | 308 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 309 | * Macro defines for Receive Filter WoL Status/Clear Registers |
| frank26080115 | 0:84d7747641aa | 310 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 311 | #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */ |
| frank26080115 | 0:84d7747641aa | 312 | #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */ |
| frank26080115 | 0:84d7747641aa | 313 | #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */ |
| frank26080115 | 0:84d7747641aa | 314 | #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */ |
| frank26080115 | 0:84d7747641aa | 315 | #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */ |
| frank26080115 | 0:84d7747641aa | 316 | #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */ |
| frank26080115 | 0:84d7747641aa | 317 | #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */ |
| frank26080115 | 0:84d7747641aa | 318 | #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */ |
| frank26080115 | 0:84d7747641aa | 319 | #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */ |
| frank26080115 | 0:84d7747641aa | 320 | |
| frank26080115 | 0:84d7747641aa | 321 | |
| frank26080115 | 0:84d7747641aa | 322 | /* Module control register definitions ---------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 323 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 324 | * Macro defines for Interrupt Status/Enable/Clear/Set Registers |
| frank26080115 | 0:84d7747641aa | 325 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 326 | #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */ |
| frank26080115 | 0:84d7747641aa | 327 | #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */ |
| frank26080115 | 0:84d7747641aa | 328 | #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */ |
| frank26080115 | 0:84d7747641aa | 329 | #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */ |
| frank26080115 | 0:84d7747641aa | 330 | #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */ |
| frank26080115 | 0:84d7747641aa | 331 | #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */ |
| frank26080115 | 0:84d7747641aa | 332 | #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */ |
| frank26080115 | 0:84d7747641aa | 333 | #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */ |
| frank26080115 | 0:84d7747641aa | 334 | #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */ |
| frank26080115 | 0:84d7747641aa | 335 | #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */ |
| frank26080115 | 0:84d7747641aa | 336 | |
| frank26080115 | 0:84d7747641aa | 337 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 338 | * Macro defines for Power Down Register |
| frank26080115 | 0:84d7747641aa | 339 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 340 | #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */ |
| frank26080115 | 0:84d7747641aa | 341 | |
| frank26080115 | 0:84d7747641aa | 342 | /* Descriptor and status formats ---------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 343 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 344 | * Macro defines for RX Descriptor Control Word |
| frank26080115 | 0:84d7747641aa | 345 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 346 | #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */ |
| frank26080115 | 0:84d7747641aa | 347 | #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */ |
| frank26080115 | 0:84d7747641aa | 348 | |
| frank26080115 | 0:84d7747641aa | 349 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 350 | * Macro defines for RX Status Hash CRC Word |
| frank26080115 | 0:84d7747641aa | 351 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 352 | #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */ |
| frank26080115 | 0:84d7747641aa | 353 | #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */ |
| frank26080115 | 0:84d7747641aa | 354 | |
| frank26080115 | 0:84d7747641aa | 355 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 356 | * Macro defines for RX Status Information Word |
| frank26080115 | 0:84d7747641aa | 357 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 358 | #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */ |
| frank26080115 | 0:84d7747641aa | 359 | #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */ |
| frank26080115 | 0:84d7747641aa | 360 | #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */ |
| frank26080115 | 0:84d7747641aa | 361 | #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */ |
| frank26080115 | 0:84d7747641aa | 362 | #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */ |
| frank26080115 | 0:84d7747641aa | 363 | #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */ |
| frank26080115 | 0:84d7747641aa | 364 | #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */ |
| frank26080115 | 0:84d7747641aa | 365 | #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */ |
| frank26080115 | 0:84d7747641aa | 366 | #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */ |
| frank26080115 | 0:84d7747641aa | 367 | #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */ |
| frank26080115 | 0:84d7747641aa | 368 | #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */ |
| frank26080115 | 0:84d7747641aa | 369 | #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */ |
| frank26080115 | 0:84d7747641aa | 370 | #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */ |
| frank26080115 | 0:84d7747641aa | 371 | #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */ |
| frank26080115 | 0:84d7747641aa | 372 | #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ |
| frank26080115 | 0:84d7747641aa | 373 | #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \ |
| frank26080115 | 0:84d7747641aa | 374 | EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN) |
| frank26080115 | 0:84d7747641aa | 375 | |
| frank26080115 | 0:84d7747641aa | 376 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 377 | * Macro defines for TX Descriptor Control Word |
| frank26080115 | 0:84d7747641aa | 378 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 379 | #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */ |
| frank26080115 | 0:84d7747641aa | 380 | #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */ |
| frank26080115 | 0:84d7747641aa | 381 | #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */ |
| frank26080115 | 0:84d7747641aa | 382 | #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */ |
| frank26080115 | 0:84d7747641aa | 383 | #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */ |
| frank26080115 | 0:84d7747641aa | 384 | #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */ |
| frank26080115 | 0:84d7747641aa | 385 | #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */ |
| frank26080115 | 0:84d7747641aa | 386 | |
| frank26080115 | 0:84d7747641aa | 387 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 388 | * Macro defines for TX Status Information Word |
| frank26080115 | 0:84d7747641aa | 389 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 390 | #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */ |
| frank26080115 | 0:84d7747641aa | 391 | #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */ |
| frank26080115 | 0:84d7747641aa | 392 | #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */ |
| frank26080115 | 0:84d7747641aa | 393 | #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */ |
| frank26080115 | 0:84d7747641aa | 394 | #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */ |
| frank26080115 | 0:84d7747641aa | 395 | #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */ |
| frank26080115 | 0:84d7747641aa | 396 | #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */ |
| frank26080115 | 0:84d7747641aa | 397 | #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */ |
| frank26080115 | 0:84d7747641aa | 398 | |
| frank26080115 | 0:84d7747641aa | 399 | #ifdef MCB_LPC_1768 |
| frank26080115 | 0:84d7747641aa | 400 | /* DP83848C PHY definition ------------------------------------------------------------ */ |
| frank26080115 | 0:84d7747641aa | 401 | |
| frank26080115 | 0:84d7747641aa | 402 | /** PHY device reset time out definition */ |
| frank26080115 | 0:84d7747641aa | 403 | #define EMAC_PHY_RESP_TOUT 0x100000UL |
| frank26080115 | 0:84d7747641aa | 404 | |
| frank26080115 | 0:84d7747641aa | 405 | /* ENET Device Revision ID */ |
| frank26080115 | 0:84d7747641aa | 406 | #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ |
| frank26080115 | 0:84d7747641aa | 407 | |
| frank26080115 | 0:84d7747641aa | 408 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 409 | * Macro defines for DP83848C PHY Registers |
| frank26080115 | 0:84d7747641aa | 410 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 411 | #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */ |
| frank26080115 | 0:84d7747641aa | 412 | #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */ |
| frank26080115 | 0:84d7747641aa | 413 | #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ |
| frank26080115 | 0:84d7747641aa | 414 | #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ |
| frank26080115 | 0:84d7747641aa | 415 | #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ |
| frank26080115 | 0:84d7747641aa | 416 | #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ |
| frank26080115 | 0:84d7747641aa | 417 | #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ |
| frank26080115 | 0:84d7747641aa | 418 | #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ |
| frank26080115 | 0:84d7747641aa | 419 | #define EMAC_PHY_REG_LPNPA 0x08 |
| frank26080115 | 0:84d7747641aa | 420 | |
| frank26080115 | 0:84d7747641aa | 421 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 422 | * Macro defines for PHY Extended Registers |
| frank26080115 | 0:84d7747641aa | 423 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 424 | #define EMAC_PHY_REG_STS 0x10 /**< Status Register */ |
| frank26080115 | 0:84d7747641aa | 425 | #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */ |
| frank26080115 | 0:84d7747641aa | 426 | #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */ |
| frank26080115 | 0:84d7747641aa | 427 | #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */ |
| frank26080115 | 0:84d7747641aa | 428 | #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */ |
| frank26080115 | 0:84d7747641aa | 429 | #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */ |
| frank26080115 | 0:84d7747641aa | 430 | #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */ |
| frank26080115 | 0:84d7747641aa | 431 | #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */ |
| frank26080115 | 0:84d7747641aa | 432 | #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */ |
| frank26080115 | 0:84d7747641aa | 433 | #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */ |
| frank26080115 | 0:84d7747641aa | 434 | #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */ |
| frank26080115 | 0:84d7747641aa | 435 | #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */ |
| frank26080115 | 0:84d7747641aa | 436 | |
| frank26080115 | 0:84d7747641aa | 437 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 438 | * Macro defines for PHY Basic Mode Control Register |
| frank26080115 | 0:84d7747641aa | 439 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 440 | #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */ |
| frank26080115 | 0:84d7747641aa | 441 | #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ |
| frank26080115 | 0:84d7747641aa | 442 | #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */ |
| frank26080115 | 0:84d7747641aa | 443 | #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ |
| frank26080115 | 0:84d7747641aa | 444 | #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */ |
| frank26080115 | 0:84d7747641aa | 445 | #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ |
| frank26080115 | 0:84d7747641aa | 446 | #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ |
| frank26080115 | 0:84d7747641aa | 447 | #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */ |
| frank26080115 | 0:84d7747641aa | 448 | |
| frank26080115 | 0:84d7747641aa | 449 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 450 | * Macro defines for PHY Basic Mode Status Status Register |
| frank26080115 | 0:84d7747641aa | 451 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 452 | #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */ |
| frank26080115 | 0:84d7747641aa | 453 | #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */ |
| frank26080115 | 0:84d7747641aa | 454 | #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */ |
| frank26080115 | 0:84d7747641aa | 455 | #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */ |
| frank26080115 | 0:84d7747641aa | 456 | #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */ |
| frank26080115 | 0:84d7747641aa | 457 | #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ |
| frank26080115 | 0:84d7747641aa | 458 | #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ |
| frank26080115 | 0:84d7747641aa | 459 | #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */ |
| frank26080115 | 0:84d7747641aa | 460 | #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */ |
| frank26080115 | 0:84d7747641aa | 461 | #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */ |
| frank26080115 | 0:84d7747641aa | 462 | |
| frank26080115 | 0:84d7747641aa | 463 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 464 | * Macro defines for PHY Status Register |
| frank26080115 | 0:84d7747641aa | 465 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 466 | #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */ |
| frank26080115 | 0:84d7747641aa | 467 | #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */ |
| frank26080115 | 0:84d7747641aa | 468 | #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */ |
| frank26080115 | 0:84d7747641aa | 469 | #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */ |
| frank26080115 | 0:84d7747641aa | 470 | #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */ |
| frank26080115 | 0:84d7747641aa | 471 | #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */ |
| frank26080115 | 0:84d7747641aa | 472 | #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */ |
| frank26080115 | 0:84d7747641aa | 473 | |
| frank26080115 | 0:84d7747641aa | 474 | #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */ |
| frank26080115 | 0:84d7747641aa | 475 | #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */ |
| frank26080115 | 0:84d7747641aa | 476 | #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */ |
| frank26080115 | 0:84d7747641aa | 477 | #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */ |
| frank26080115 | 0:84d7747641aa | 478 | #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */ |
| frank26080115 | 0:84d7747641aa | 479 | |
| frank26080115 | 0:84d7747641aa | 480 | #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */ |
| frank26080115 | 0:84d7747641aa | 481 | #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */ |
| frank26080115 | 0:84d7747641aa | 482 | |
| frank26080115 | 0:84d7747641aa | 483 | #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13)) |
| frank26080115 | 0:84d7747641aa | 484 | #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12)) |
| frank26080115 | 0:84d7747641aa | 485 | #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */ |
| frank26080115 | 0:84d7747641aa | 486 | |
| frank26080115 | 0:84d7747641aa | 487 | #elif defined(IAR_LPC_1768) |
| frank26080115 | 0:84d7747641aa | 488 | /* KSZ8721BL PHY definition ------------------------------------------------------------ */ |
| frank26080115 | 0:84d7747641aa | 489 | /** PHY device reset time out definition */ |
| frank26080115 | 0:84d7747641aa | 490 | #define EMAC_PHY_RESP_TOUT 0x100000UL |
| frank26080115 | 0:84d7747641aa | 491 | |
| frank26080115 | 0:84d7747641aa | 492 | /* ENET Device Revision ID */ |
| frank26080115 | 0:84d7747641aa | 493 | #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */ |
| frank26080115 | 0:84d7747641aa | 494 | |
| frank26080115 | 0:84d7747641aa | 495 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 496 | * Macro defines for KSZ8721BL PHY Registers |
| frank26080115 | 0:84d7747641aa | 497 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 498 | #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */ |
| frank26080115 | 0:84d7747641aa | 499 | #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */ |
| frank26080115 | 0:84d7747641aa | 500 | #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */ |
| frank26080115 | 0:84d7747641aa | 501 | #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */ |
| frank26080115 | 0:84d7747641aa | 502 | #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */ |
| frank26080115 | 0:84d7747641aa | 503 | #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */ |
| frank26080115 | 0:84d7747641aa | 504 | #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */ |
| frank26080115 | 0:84d7747641aa | 505 | #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */ |
| frank26080115 | 0:84d7747641aa | 506 | #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */ |
| frank26080115 | 0:84d7747641aa | 507 | #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */ |
| frank26080115 | 0:84d7747641aa | 508 | #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */ |
| frank26080115 | 0:84d7747641aa | 509 | #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */ |
| frank26080115 | 0:84d7747641aa | 510 | |
| frank26080115 | 0:84d7747641aa | 511 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 512 | * Macro defines for PHY Basic Mode Control Register |
| frank26080115 | 0:84d7747641aa | 513 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 514 | #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */ |
| frank26080115 | 0:84d7747641aa | 515 | #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */ |
| frank26080115 | 0:84d7747641aa | 516 | #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */ |
| frank26080115 | 0:84d7747641aa | 517 | #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */ |
| frank26080115 | 0:84d7747641aa | 518 | #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */ |
| frank26080115 | 0:84d7747641aa | 519 | #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */ |
| frank26080115 | 0:84d7747641aa | 520 | #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */ |
| frank26080115 | 0:84d7747641aa | 521 | #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */ |
| frank26080115 | 0:84d7747641aa | 522 | #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */ |
| frank26080115 | 0:84d7747641aa | 523 | #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */ |
| frank26080115 | 0:84d7747641aa | 524 | |
| frank26080115 | 0:84d7747641aa | 525 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 526 | * Macro defines for PHY Basic Mode Status Register |
| frank26080115 | 0:84d7747641aa | 527 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 528 | #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */ |
| frank26080115 | 0:84d7747641aa | 529 | #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */ |
| frank26080115 | 0:84d7747641aa | 530 | #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */ |
| frank26080115 | 0:84d7747641aa | 531 | #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */ |
| frank26080115 | 0:84d7747641aa | 532 | #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */ |
| frank26080115 | 0:84d7747641aa | 533 | #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */ |
| frank26080115 | 0:84d7747641aa | 534 | #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */ |
| frank26080115 | 0:84d7747641aa | 535 | #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */ |
| frank26080115 | 0:84d7747641aa | 536 | #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */ |
| frank26080115 | 0:84d7747641aa | 537 | #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */ |
| frank26080115 | 0:84d7747641aa | 538 | #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */ |
| frank26080115 | 0:84d7747641aa | 539 | #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */ |
| frank26080115 | 0:84d7747641aa | 540 | |
| frank26080115 | 0:84d7747641aa | 541 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 542 | * Macro defines for PHY Identifier |
| frank26080115 | 0:84d7747641aa | 543 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 544 | /* PHY Identifier 1 bitmap definitions */ |
| frank26080115 | 0:84d7747641aa | 545 | #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */ |
| frank26080115 | 0:84d7747641aa | 546 | |
| frank26080115 | 0:84d7747641aa | 547 | /* PHY Identifier 2 bitmap definitions */ |
| frank26080115 | 0:84d7747641aa | 548 | #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */ |
| frank26080115 | 0:84d7747641aa | 549 | |
| frank26080115 | 0:84d7747641aa | 550 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 551 | * Macro defines for Auto-Negotiation Advertisement |
| frank26080115 | 0:84d7747641aa | 552 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 553 | #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */ |
| frank26080115 | 0:84d7747641aa | 554 | #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */ |
| frank26080115 | 0:84d7747641aa | 555 | #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */ |
| frank26080115 | 0:84d7747641aa | 556 | #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */ |
| frank26080115 | 0:84d7747641aa | 557 | #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */ |
| frank26080115 | 0:84d7747641aa | 558 | #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */ |
| frank26080115 | 0:84d7747641aa | 559 | #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */ |
| frank26080115 | 0:84d7747641aa | 560 | #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */ |
| frank26080115 | 0:84d7747641aa | 561 | #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */ |
| frank26080115 | 0:84d7747641aa | 562 | |
| frank26080115 | 0:84d7747641aa | 563 | #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */ |
| frank26080115 | 0:84d7747641aa | 564 | #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */ |
| frank26080115 | 0:84d7747641aa | 565 | #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */ |
| frank26080115 | 0:84d7747641aa | 566 | #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */ |
| frank26080115 | 0:84d7747641aa | 567 | #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */ |
| frank26080115 | 0:84d7747641aa | 568 | |
| frank26080115 | 0:84d7747641aa | 569 | #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13)) |
| frank26080115 | 0:84d7747641aa | 570 | #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12)) |
| frank26080115 | 0:84d7747641aa | 571 | |
| frank26080115 | 0:84d7747641aa | 572 | #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */ |
| frank26080115 | 0:84d7747641aa | 573 | #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */ |
| frank26080115 | 0:84d7747641aa | 574 | #endif |
| frank26080115 | 0:84d7747641aa | 575 | |
| frank26080115 | 0:84d7747641aa | 576 | /** |
| frank26080115 | 0:84d7747641aa | 577 | * @} |
| frank26080115 | 0:84d7747641aa | 578 | */ |
| frank26080115 | 0:84d7747641aa | 579 | |
| frank26080115 | 0:84d7747641aa | 580 | |
| frank26080115 | 0:84d7747641aa | 581 | /* Public Types --------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 582 | /** @defgroup EMAC_Public_Types EMAC Public Types |
| frank26080115 | 0:84d7747641aa | 583 | * @{ |
| frank26080115 | 0:84d7747641aa | 584 | */ |
| frank26080115 | 0:84d7747641aa | 585 | |
| frank26080115 | 0:84d7747641aa | 586 | /* Descriptor and status formats ---------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 587 | |
| frank26080115 | 0:84d7747641aa | 588 | /** |
| frank26080115 | 0:84d7747641aa | 589 | * @brief RX Descriptor structure type definition |
| frank26080115 | 0:84d7747641aa | 590 | */ |
| frank26080115 | 0:84d7747641aa | 591 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 592 | uint32_t Packet; /**< Receive Packet Descriptor */ |
| frank26080115 | 0:84d7747641aa | 593 | uint32_t Ctrl; /**< Receive Control Descriptor */ |
| frank26080115 | 0:84d7747641aa | 594 | } RX_Desc; |
| frank26080115 | 0:84d7747641aa | 595 | |
| frank26080115 | 0:84d7747641aa | 596 | /** |
| frank26080115 | 0:84d7747641aa | 597 | * @brief RX Status structure type definition |
| frank26080115 | 0:84d7747641aa | 598 | */ |
| frank26080115 | 0:84d7747641aa | 599 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 600 | uint32_t Info; /**< Receive Information Status */ |
| frank26080115 | 0:84d7747641aa | 601 | uint32_t HashCRC; /**< Receive Hash CRC Status */ |
| frank26080115 | 0:84d7747641aa | 602 | } RX_Stat; |
| frank26080115 | 0:84d7747641aa | 603 | |
| frank26080115 | 0:84d7747641aa | 604 | /** |
| frank26080115 | 0:84d7747641aa | 605 | * @brief TX Descriptor structure type definition |
| frank26080115 | 0:84d7747641aa | 606 | */ |
| frank26080115 | 0:84d7747641aa | 607 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 608 | uint32_t Packet; /**< Transmit Packet Descriptor */ |
| frank26080115 | 0:84d7747641aa | 609 | uint32_t Ctrl; /**< Transmit Control Descriptor */ |
| frank26080115 | 0:84d7747641aa | 610 | } TX_Desc; |
| frank26080115 | 0:84d7747641aa | 611 | |
| frank26080115 | 0:84d7747641aa | 612 | /** |
| frank26080115 | 0:84d7747641aa | 613 | * @brief TX Status structure type definition |
| frank26080115 | 0:84d7747641aa | 614 | */ |
| frank26080115 | 0:84d7747641aa | 615 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 616 | uint32_t Info; /**< Transmit Information Status */ |
| frank26080115 | 0:84d7747641aa | 617 | } TX_Stat; |
| frank26080115 | 0:84d7747641aa | 618 | |
| frank26080115 | 0:84d7747641aa | 619 | |
| frank26080115 | 0:84d7747641aa | 620 | /** |
| frank26080115 | 0:84d7747641aa | 621 | * @brief TX Data Buffer structure definition |
| frank26080115 | 0:84d7747641aa | 622 | */ |
| frank26080115 | 0:84d7747641aa | 623 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 624 | uint32_t ulDataLen; /**< Data length */ |
| frank26080115 | 0:84d7747641aa | 625 | uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */ |
| frank26080115 | 0:84d7747641aa | 626 | } EMAC_PACKETBUF_Type; |
| frank26080115 | 0:84d7747641aa | 627 | |
| frank26080115 | 0:84d7747641aa | 628 | /** |
| frank26080115 | 0:84d7747641aa | 629 | * @brief EMAC configuration structure definition |
| frank26080115 | 0:84d7747641aa | 630 | */ |
| frank26080115 | 0:84d7747641aa | 631 | typedef struct { |
| frank26080115 | 0:84d7747641aa | 632 | uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following: |
| frank26080115 | 0:84d7747641aa | 633 | - EMAC_MODE_AUTO |
| frank26080115 | 0:84d7747641aa | 634 | - EMAC_MODE_10M_FULL |
| frank26080115 | 0:84d7747641aa | 635 | - EMAC_MODE_10M_HALF |
| frank26080115 | 0:84d7747641aa | 636 | - EMAC_MODE_100M_FULL |
| frank26080115 | 0:84d7747641aa | 637 | - EMAC_MODE_100M_HALF |
| frank26080115 | 0:84d7747641aa | 638 | */ |
| frank26080115 | 0:84d7747641aa | 639 | uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes |
| frank26080115 | 0:84d7747641aa | 640 | of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5]) |
| frank26080115 | 0:84d7747641aa | 641 | */ |
| frank26080115 | 0:84d7747641aa | 642 | } EMAC_CFG_Type; |
| frank26080115 | 0:84d7747641aa | 643 | |
| frank26080115 | 0:84d7747641aa | 644 | |
| frank26080115 | 0:84d7747641aa | 645 | /** |
| frank26080115 | 0:84d7747641aa | 646 | * @} |
| frank26080115 | 0:84d7747641aa | 647 | */ |
| frank26080115 | 0:84d7747641aa | 648 | |
| frank26080115 | 0:84d7747641aa | 649 | |
| frank26080115 | 0:84d7747641aa | 650 | /* Public Functions ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 651 | /** @defgroup EMAC_Public_Functions EMAC Public Functions |
| frank26080115 | 0:84d7747641aa | 652 | * @{ |
| frank26080115 | 0:84d7747641aa | 653 | */ |
| frank26080115 | 0:84d7747641aa | 654 | /* Init/DeInit EMAC peripheral */ |
| frank26080115 | 0:84d7747641aa | 655 | Status EMAC_Init(EMAC_CFG_Type *EMAC_ConfigStruct); |
| frank26080115 | 0:84d7747641aa | 656 | void EMAC_DeInit(void); |
| frank26080115 | 0:84d7747641aa | 657 | |
| frank26080115 | 0:84d7747641aa | 658 | /* PHY functions --------------*/ |
| frank26080115 | 0:84d7747641aa | 659 | int32_t EMAC_CheckPHYStatus(uint32_t ulPHYState); |
| frank26080115 | 0:84d7747641aa | 660 | int32_t EMAC_SetPHYMode(uint32_t ulPHYMode); |
| frank26080115 | 0:84d7747641aa | 661 | int32_t EMAC_UpdatePHYStatus(void); |
| frank26080115 | 0:84d7747641aa | 662 | |
| frank26080115 | 0:84d7747641aa | 663 | /* Filter functions ----------*/ |
| frank26080115 | 0:84d7747641aa | 664 | void EMAC_SetHashFilter(uint8_t dstMAC_addr[], FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 665 | void EMAC_SetFilterMode(uint32_t ulFilterMode, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 666 | |
| frank26080115 | 0:84d7747641aa | 667 | /* EMAC Packet Buffer functions */ |
| frank26080115 | 0:84d7747641aa | 668 | void EMAC_WritePacketBuffer(EMAC_PACKETBUF_Type *pDataStruct); |
| frank26080115 | 0:84d7747641aa | 669 | void EMAC_ReadPacketBuffer(EMAC_PACKETBUF_Type *pDataStruct); |
| frank26080115 | 0:84d7747641aa | 670 | |
| frank26080115 | 0:84d7747641aa | 671 | /* EMAC Interrupt functions -------*/ |
| frank26080115 | 0:84d7747641aa | 672 | void EMAC_IntCmd(uint32_t ulIntType, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 673 | IntStatus EMAC_IntGetStatus(uint32_t ulIntType); |
| frank26080115 | 0:84d7747641aa | 674 | |
| frank26080115 | 0:84d7747641aa | 675 | /* EMAC Index functions -----------*/ |
| frank26080115 | 0:84d7747641aa | 676 | Bool EMAC_CheckReceiveIndex(void); |
| frank26080115 | 0:84d7747641aa | 677 | Bool EMAC_CheckTransmitIndex(void); |
| frank26080115 | 0:84d7747641aa | 678 | void EMAC_UpdateRxConsumeIndex(void); |
| frank26080115 | 0:84d7747641aa | 679 | void EMAC_UpdateTxProduceIndex(void); |
| frank26080115 | 0:84d7747641aa | 680 | |
| frank26080115 | 0:84d7747641aa | 681 | FlagStatus EMAC_CheckReceiveDataStatus(uint32_t ulRxStatType); |
| frank26080115 | 0:84d7747641aa | 682 | uint32_t EMAC_GetReceiveDataSize(void); |
| frank26080115 | 0:84d7747641aa | 683 | FlagStatus EMAC_GetWoLStatus(uint32_t ulWoLMode); |
| frank26080115 | 0:84d7747641aa | 684 | |
| frank26080115 | 0:84d7747641aa | 685 | /** |
| frank26080115 | 0:84d7747641aa | 686 | * @} |
| frank26080115 | 0:84d7747641aa | 687 | */ |
| frank26080115 | 0:84d7747641aa | 688 | |
| frank26080115 | 0:84d7747641aa | 689 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 690 | } |
| frank26080115 | 0:84d7747641aa | 691 | #endif |
| frank26080115 | 0:84d7747641aa | 692 | |
| frank26080115 | 0:84d7747641aa | 693 | #endif /* LPC17XX_EMAC_H_ */ |
| frank26080115 | 0:84d7747641aa | 694 | |
| frank26080115 | 0:84d7747641aa | 695 | /** |
| frank26080115 | 0:84d7747641aa | 696 | * @} |
| frank26080115 | 0:84d7747641aa | 697 | */ |
| frank26080115 | 0:84d7747641aa | 698 | |
| frank26080115 | 0:84d7747641aa | 699 | /* --------------------------------- End Of File ------------------------------ */ |