Frank 26080115
Date: March 20, 2011 This library is created from "LPC17xx CMSIS-Compliant Standard Peripheral Firmware Driver Library (GNU, Keil, IAR) (Jan 28, 2011)", available from NXP's website, under "All microcontrollers support documents" [[http://ics.nxp.com/support/documents/microcontrollers/?type=software]] You will need to follow [[/projects/libraries/svn/mbed/trunk/LPC1768/LPC17xx.h]] while using this library Examples provided here [[/users/frank26080115/programs/LPC1700CMSIS_Examples/]] The beautiful thing is that NXP does not place copyright protection on any of the files in here Only a few modifications are made to make it compile with the mbed online compiler, I fixed some warnings as well. This is untested as of March 20, 2011 Forum post about this library: [[/forum/mbed/topic/2030/]]
lpc17xx_clkpwr.h@0:84d7747641aa, 2011-03-20 (annotated)
- Committer:
- frank26080115
- Date:
- Sun Mar 20 18:45:15 2011 +0000
- Revision:
- 0:84d7747641aa
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| frank26080115 | 0:84d7747641aa | 1 | /***********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 2 | * @file lpc17xx_clkpwr.h |
| frank26080115 | 0:84d7747641aa | 3 | * @brief Contains all macro definitions and function prototypes |
| frank26080115 | 0:84d7747641aa | 4 | * support for Clock and Power Control firmware library on LPC17xx |
| frank26080115 | 0:84d7747641aa | 5 | * @version 2.0 |
| frank26080115 | 0:84d7747641aa | 6 | * @date 21. May. 2010 |
| frank26080115 | 0:84d7747641aa | 7 | * @author NXP MCU SW Application Team |
| frank26080115 | 0:84d7747641aa | 8 | ************************************************************************** |
| frank26080115 | 0:84d7747641aa | 9 | * Software that is described herein is for illustrative purposes only |
| frank26080115 | 0:84d7747641aa | 10 | * which provides customers with programming information regarding the |
| frank26080115 | 0:84d7747641aa | 11 | * products. This software is supplied "AS IS" without any warranties. |
| frank26080115 | 0:84d7747641aa | 12 | * NXP Semiconductors assumes no responsibility or liability for the |
| frank26080115 | 0:84d7747641aa | 13 | * use of the software, conveys no license or title under any patent, |
| frank26080115 | 0:84d7747641aa | 14 | * copyright, or mask work right to the product. NXP Semiconductors |
| frank26080115 | 0:84d7747641aa | 15 | * reserves the right to make changes in the software without |
| frank26080115 | 0:84d7747641aa | 16 | * notification. NXP Semiconductors also make no representation or |
| frank26080115 | 0:84d7747641aa | 17 | * warranty that such application will be suitable for the specified |
| frank26080115 | 0:84d7747641aa | 18 | * use without further testing or modification. |
| frank26080115 | 0:84d7747641aa | 19 | **************************************************************************/ |
| frank26080115 | 0:84d7747641aa | 20 | |
| frank26080115 | 0:84d7747641aa | 21 | /* Peripheral group ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 22 | /** @defgroup CLKPWR CLKPWR |
| frank26080115 | 0:84d7747641aa | 23 | * @ingroup LPC1700CMSIS_FwLib_Drivers |
| frank26080115 | 0:84d7747641aa | 24 | * @{ |
| frank26080115 | 0:84d7747641aa | 25 | */ |
| frank26080115 | 0:84d7747641aa | 26 | |
| frank26080115 | 0:84d7747641aa | 27 | #ifndef LPC17XX_CLKPWR_H_ |
| frank26080115 | 0:84d7747641aa | 28 | #define LPC17XX_CLKPWR_H_ |
| frank26080115 | 0:84d7747641aa | 29 | |
| frank26080115 | 0:84d7747641aa | 30 | /* Includes ------------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 31 | #include "lpc17xx.h" |
| frank26080115 | 0:84d7747641aa | 32 | #include "lpc_types.h" |
| frank26080115 | 0:84d7747641aa | 33 | |
| frank26080115 | 0:84d7747641aa | 34 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 35 | extern "C" |
| frank26080115 | 0:84d7747641aa | 36 | { |
| frank26080115 | 0:84d7747641aa | 37 | #endif |
| frank26080115 | 0:84d7747641aa | 38 | |
| frank26080115 | 0:84d7747641aa | 39 | /* Public Macros -------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 40 | /** @defgroup CLKPWR_Public_Macros CLKPWR Public Macros |
| frank26080115 | 0:84d7747641aa | 41 | * @{ |
| frank26080115 | 0:84d7747641aa | 42 | */ |
| frank26080115 | 0:84d7747641aa | 43 | |
| frank26080115 | 0:84d7747641aa | 44 | /********************************************************************** |
| frank26080115 | 0:84d7747641aa | 45 | * Peripheral Clock Selection Definitions |
| frank26080115 | 0:84d7747641aa | 46 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 47 | /** Peripheral clock divider bit position for WDT */ |
| frank26080115 | 0:84d7747641aa | 48 | #define CLKPWR_PCLKSEL_WDT ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 49 | /** Peripheral clock divider bit position for TIMER0 */ |
| frank26080115 | 0:84d7747641aa | 50 | #define CLKPWR_PCLKSEL_TIMER0 ((uint32_t)(2)) |
| frank26080115 | 0:84d7747641aa | 51 | /** Peripheral clock divider bit position for TIMER1 */ |
| frank26080115 | 0:84d7747641aa | 52 | #define CLKPWR_PCLKSEL_TIMER1 ((uint32_t)(4)) |
| frank26080115 | 0:84d7747641aa | 53 | /** Peripheral clock divider bit position for UART0 */ |
| frank26080115 | 0:84d7747641aa | 54 | #define CLKPWR_PCLKSEL_UART0 ((uint32_t)(6)) |
| frank26080115 | 0:84d7747641aa | 55 | /** Peripheral clock divider bit position for UART1 */ |
| frank26080115 | 0:84d7747641aa | 56 | #define CLKPWR_PCLKSEL_UART1 ((uint32_t)(8)) |
| frank26080115 | 0:84d7747641aa | 57 | /** Peripheral clock divider bit position for PWM1 */ |
| frank26080115 | 0:84d7747641aa | 58 | #define CLKPWR_PCLKSEL_PWM1 ((uint32_t)(12)) |
| frank26080115 | 0:84d7747641aa | 59 | /** Peripheral clock divider bit position for I2C0 */ |
| frank26080115 | 0:84d7747641aa | 60 | #define CLKPWR_PCLKSEL_I2C0 ((uint32_t)(14)) |
| frank26080115 | 0:84d7747641aa | 61 | /** Peripheral clock divider bit position for SPI */ |
| frank26080115 | 0:84d7747641aa | 62 | #define CLKPWR_PCLKSEL_SPI ((uint32_t)(16)) |
| frank26080115 | 0:84d7747641aa | 63 | /** Peripheral clock divider bit position for SSP1 */ |
| frank26080115 | 0:84d7747641aa | 64 | #define CLKPWR_PCLKSEL_SSP1 ((uint32_t)(20)) |
| frank26080115 | 0:84d7747641aa | 65 | /** Peripheral clock divider bit position for DAC */ |
| frank26080115 | 0:84d7747641aa | 66 | #define CLKPWR_PCLKSEL_DAC ((uint32_t)(22)) |
| frank26080115 | 0:84d7747641aa | 67 | /** Peripheral clock divider bit position for ADC */ |
| frank26080115 | 0:84d7747641aa | 68 | #define CLKPWR_PCLKSEL_ADC ((uint32_t)(24)) |
| frank26080115 | 0:84d7747641aa | 69 | /** Peripheral clock divider bit position for CAN1 */ |
| frank26080115 | 0:84d7747641aa | 70 | #define CLKPWR_PCLKSEL_CAN1 ((uint32_t)(26)) |
| frank26080115 | 0:84d7747641aa | 71 | /** Peripheral clock divider bit position for CAN2 */ |
| frank26080115 | 0:84d7747641aa | 72 | #define CLKPWR_PCLKSEL_CAN2 ((uint32_t)(28)) |
| frank26080115 | 0:84d7747641aa | 73 | /** Peripheral clock divider bit position for ACF */ |
| frank26080115 | 0:84d7747641aa | 74 | #define CLKPWR_PCLKSEL_ACF ((uint32_t)(30)) |
| frank26080115 | 0:84d7747641aa | 75 | /** Peripheral clock divider bit position for QEI */ |
| frank26080115 | 0:84d7747641aa | 76 | #define CLKPWR_PCLKSEL_QEI ((uint32_t)(32)) |
| frank26080115 | 0:84d7747641aa | 77 | /** Peripheral clock divider bit position for PCB */ |
| frank26080115 | 0:84d7747641aa | 78 | #define CLKPWR_PCLKSEL_PCB ((uint32_t)(36)) |
| frank26080115 | 0:84d7747641aa | 79 | /** Peripheral clock divider bit position for I2C1 */ |
| frank26080115 | 0:84d7747641aa | 80 | #define CLKPWR_PCLKSEL_I2C1 ((uint32_t)(38)) |
| frank26080115 | 0:84d7747641aa | 81 | /** Peripheral clock divider bit position for SSP0 */ |
| frank26080115 | 0:84d7747641aa | 82 | #define CLKPWR_PCLKSEL_SSP0 ((uint32_t)(42)) |
| frank26080115 | 0:84d7747641aa | 83 | /** Peripheral clock divider bit position for TIMER2 */ |
| frank26080115 | 0:84d7747641aa | 84 | #define CLKPWR_PCLKSEL_TIMER2 ((uint32_t)(44)) |
| frank26080115 | 0:84d7747641aa | 85 | /** Peripheral clock divider bit position for TIMER3 */ |
| frank26080115 | 0:84d7747641aa | 86 | #define CLKPWR_PCLKSEL_TIMER3 ((uint32_t)(46)) |
| frank26080115 | 0:84d7747641aa | 87 | /** Peripheral clock divider bit position for UART2 */ |
| frank26080115 | 0:84d7747641aa | 88 | #define CLKPWR_PCLKSEL_UART2 ((uint32_t)(48)) |
| frank26080115 | 0:84d7747641aa | 89 | /** Peripheral clock divider bit position for UART3 */ |
| frank26080115 | 0:84d7747641aa | 90 | #define CLKPWR_PCLKSEL_UART3 ((uint32_t)(50)) |
| frank26080115 | 0:84d7747641aa | 91 | /** Peripheral clock divider bit position for I2C2 */ |
| frank26080115 | 0:84d7747641aa | 92 | #define CLKPWR_PCLKSEL_I2C2 ((uint32_t)(52)) |
| frank26080115 | 0:84d7747641aa | 93 | /** Peripheral clock divider bit position for I2S */ |
| frank26080115 | 0:84d7747641aa | 94 | #define CLKPWR_PCLKSEL_I2S ((uint32_t)(54)) |
| frank26080115 | 0:84d7747641aa | 95 | /** Peripheral clock divider bit position for RIT */ |
| frank26080115 | 0:84d7747641aa | 96 | #define CLKPWR_PCLKSEL_RIT ((uint32_t)(58)) |
| frank26080115 | 0:84d7747641aa | 97 | /** Peripheral clock divider bit position for SYSCON */ |
| frank26080115 | 0:84d7747641aa | 98 | #define CLKPWR_PCLKSEL_SYSCON ((uint32_t)(60)) |
| frank26080115 | 0:84d7747641aa | 99 | /** Peripheral clock divider bit position for MC */ |
| frank26080115 | 0:84d7747641aa | 100 | #define CLKPWR_PCLKSEL_MC ((uint32_t)(62)) |
| frank26080115 | 0:84d7747641aa | 101 | |
| frank26080115 | 0:84d7747641aa | 102 | /** Macro for Peripheral Clock Selection register bit values |
| frank26080115 | 0:84d7747641aa | 103 | * Note: When CCLK_DIV_8, Peripheral�s clock is selected to |
| frank26080115 | 0:84d7747641aa | 104 | * PCLK_xyz = CCLK/8 except for CAN1, CAN2, and CAN filtering |
| frank26080115 | 0:84d7747641aa | 105 | * when �11�selects PCLK_xyz = CCLK/6 */ |
| frank26080115 | 0:84d7747641aa | 106 | /* Peripheral clock divider is set to 4 from CCLK */ |
| frank26080115 | 0:84d7747641aa | 107 | #define CLKPWR_PCLKSEL_CCLK_DIV_4 ((uint32_t)(0)) |
| frank26080115 | 0:84d7747641aa | 108 | /** Peripheral clock divider is the same with CCLK */ |
| frank26080115 | 0:84d7747641aa | 109 | #define CLKPWR_PCLKSEL_CCLK_DIV_1 ((uint32_t)(1)) |
| frank26080115 | 0:84d7747641aa | 110 | /** Peripheral clock divider is set to 2 from CCLK */ |
| frank26080115 | 0:84d7747641aa | 111 | #define CLKPWR_PCLKSEL_CCLK_DIV_2 ((uint32_t)(2)) |
| frank26080115 | 0:84d7747641aa | 112 | |
| frank26080115 | 0:84d7747641aa | 113 | |
| frank26080115 | 0:84d7747641aa | 114 | /******************************************************************** |
| frank26080115 | 0:84d7747641aa | 115 | * Power Control for Peripherals Definitions |
| frank26080115 | 0:84d7747641aa | 116 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 117 | /** Timer/Counter 0 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 118 | #define CLKPWR_PCONP_PCTIM0 ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 119 | /* Timer/Counter 1 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 120 | #define CLKPWR_PCONP_PCTIM1 ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 121 | /** UART0 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 122 | #define CLKPWR_PCONP_PCUART0 ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 123 | /** UART1 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 124 | #define CLKPWR_PCONP_PCUART1 ((uint32_t)(1<<4)) |
| frank26080115 | 0:84d7747641aa | 125 | /** PWM1 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 126 | #define CLKPWR_PCONP_PCPWM1 ((uint32_t)(1<<6)) |
| frank26080115 | 0:84d7747641aa | 127 | /** The I2C0 interface power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 128 | #define CLKPWR_PCONP_PCI2C0 ((uint32_t)(1<<7)) |
| frank26080115 | 0:84d7747641aa | 129 | /** The SPI interface power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 130 | #define CLKPWR_PCONP_PCSPI ((uint32_t)(1<<8)) |
| frank26080115 | 0:84d7747641aa | 131 | /** The RTC power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 132 | #define CLKPWR_PCONP_PCRTC ((uint32_t)(1<<9)) |
| frank26080115 | 0:84d7747641aa | 133 | /** The SSP1 interface power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 134 | #define CLKPWR_PCONP_PCSSP1 ((uint32_t)(1<<10)) |
| frank26080115 | 0:84d7747641aa | 135 | /** A/D converter 0 (ADC0) power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 136 | #define CLKPWR_PCONP_PCAD ((uint32_t)(1<<12)) |
| frank26080115 | 0:84d7747641aa | 137 | /** CAN Controller 1 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 138 | #define CLKPWR_PCONP_PCAN1 ((uint32_t)(1<<13)) |
| frank26080115 | 0:84d7747641aa | 139 | /** CAN Controller 2 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 140 | #define CLKPWR_PCONP_PCAN2 ((uint32_t)(1<<14)) |
| frank26080115 | 0:84d7747641aa | 141 | /** GPIO power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 142 | #define CLKPWR_PCONP_PCGPIO ((uint32_t)(1<<15)) |
| frank26080115 | 0:84d7747641aa | 143 | /** Repetitive Interrupt Timer power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 144 | #define CLKPWR_PCONP_PCRIT ((uint32_t)(1<<16)) |
| frank26080115 | 0:84d7747641aa | 145 | /** Motor Control PWM */ |
| frank26080115 | 0:84d7747641aa | 146 | #define CLKPWR_PCONP_PCMC ((uint32_t)(1<<17)) |
| frank26080115 | 0:84d7747641aa | 147 | /** Quadrature Encoder Interface power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 148 | #define CLKPWR_PCONP_PCQEI ((uint32_t)(1<<18)) |
| frank26080115 | 0:84d7747641aa | 149 | /** The I2C1 interface power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 150 | #define CLKPWR_PCONP_PCI2C1 ((uint32_t)(1<<19)) |
| frank26080115 | 0:84d7747641aa | 151 | /** The SSP0 interface power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 152 | #define CLKPWR_PCONP_PCSSP0 ((uint32_t)(1<<21)) |
| frank26080115 | 0:84d7747641aa | 153 | /** Timer 2 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 154 | #define CLKPWR_PCONP_PCTIM2 ((uint32_t)(1<<22)) |
| frank26080115 | 0:84d7747641aa | 155 | /** Timer 3 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 156 | #define CLKPWR_PCONP_PCTIM3 ((uint32_t)(1<<23)) |
| frank26080115 | 0:84d7747641aa | 157 | /** UART 2 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 158 | #define CLKPWR_PCONP_PCUART2 ((uint32_t)(1<<24)) |
| frank26080115 | 0:84d7747641aa | 159 | /** UART 3 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 160 | #define CLKPWR_PCONP_PCUART3 ((uint32_t)(1<<25)) |
| frank26080115 | 0:84d7747641aa | 161 | /** I2C interface 2 power/clock control bit */ |
| frank26080115 | 0:84d7747641aa | 162 | #define CLKPWR_PCONP_PCI2C2 ((uint32_t)(1<<26)) |
| frank26080115 | 0:84d7747641aa | 163 | /** I2S interface power/clock control bit*/ |
| frank26080115 | 0:84d7747641aa | 164 | #define CLKPWR_PCONP_PCI2S ((uint32_t)(1<<27)) |
| frank26080115 | 0:84d7747641aa | 165 | /** GP DMA function power/clock control bit*/ |
| frank26080115 | 0:84d7747641aa | 166 | #define CLKPWR_PCONP_PCGPDMA ((uint32_t)(1<<29)) |
| frank26080115 | 0:84d7747641aa | 167 | /** Ethernet block power/clock control bit*/ |
| frank26080115 | 0:84d7747641aa | 168 | #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30)) |
| frank26080115 | 0:84d7747641aa | 169 | /** USB interface power/clock control bit*/ |
| frank26080115 | 0:84d7747641aa | 170 | #define CLKPWR_PCONP_PCUSB ((uint32_t)(1<<31)) |
| frank26080115 | 0:84d7747641aa | 171 | |
| frank26080115 | 0:84d7747641aa | 172 | |
| frank26080115 | 0:84d7747641aa | 173 | /** |
| frank26080115 | 0:84d7747641aa | 174 | * @} |
| frank26080115 | 0:84d7747641aa | 175 | */ |
| frank26080115 | 0:84d7747641aa | 176 | /* Private Macros ------------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 177 | /** @defgroup CLKPWR_Private_Macros CLKPWR Private Macros |
| frank26080115 | 0:84d7747641aa | 178 | * @{ |
| frank26080115 | 0:84d7747641aa | 179 | */ |
| frank26080115 | 0:84d7747641aa | 180 | |
| frank26080115 | 0:84d7747641aa | 181 | /* --------------------- BIT DEFINITIONS -------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 182 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 183 | * Macro defines for Clock Source Select Register |
| frank26080115 | 0:84d7747641aa | 184 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 185 | /** Internal RC oscillator */ |
| frank26080115 | 0:84d7747641aa | 186 | #define CLKPWR_CLKSRCSEL_CLKSRC_IRC ((uint32_t)(0x00)) |
| frank26080115 | 0:84d7747641aa | 187 | /** Main oscillator */ |
| frank26080115 | 0:84d7747641aa | 188 | #define CLKPWR_CLKSRCSEL_CLKSRC_MAINOSC ((uint32_t)(0x01)) |
| frank26080115 | 0:84d7747641aa | 189 | /** RTC oscillator */ |
| frank26080115 | 0:84d7747641aa | 190 | #define CLKPWR_CLKSRCSEL_CLKSRC_RTC ((uint32_t)(0x02)) |
| frank26080115 | 0:84d7747641aa | 191 | /** Clock source selection bit mask */ |
| frank26080115 | 0:84d7747641aa | 192 | #define CLKPWR_CLKSRCSEL_BITMASK ((uint32_t)(0x03)) |
| frank26080115 | 0:84d7747641aa | 193 | |
| frank26080115 | 0:84d7747641aa | 194 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 195 | * Macro defines for Clock Output Configuration Register |
| frank26080115 | 0:84d7747641aa | 196 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 197 | /* Clock Output Configuration register definition */ |
| frank26080115 | 0:84d7747641aa | 198 | /** Selects the CPU clock as the CLKOUT source */ |
| frank26080115 | 0:84d7747641aa | 199 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_CPU ((uint32_t)(0x00)) |
| frank26080115 | 0:84d7747641aa | 200 | /** Selects the main oscillator as the CLKOUT source */ |
| frank26080115 | 0:84d7747641aa | 201 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_MAINOSC ((uint32_t)(0x01)) |
| frank26080115 | 0:84d7747641aa | 202 | /** Selects the Internal RC oscillator as the CLKOUT source */ |
| frank26080115 | 0:84d7747641aa | 203 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RC ((uint32_t)(0x02)) |
| frank26080115 | 0:84d7747641aa | 204 | /** Selects the USB clock as the CLKOUT source */ |
| frank26080115 | 0:84d7747641aa | 205 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_USB ((uint32_t)(0x03)) |
| frank26080115 | 0:84d7747641aa | 206 | /** Selects the RTC oscillator as the CLKOUT source */ |
| frank26080115 | 0:84d7747641aa | 207 | #define CLKPWR_CLKOUTCFG_CLKOUTSEL_RTC ((uint32_t)(0x04)) |
| frank26080115 | 0:84d7747641aa | 208 | /** Integer value to divide the output clock by, minus one */ |
| frank26080115 | 0:84d7747641aa | 209 | #define CLKPWR_CLKOUTCFG_CLKOUTDIV(n) ((uint32_t)((n&0x0F)<<4)) |
| frank26080115 | 0:84d7747641aa | 210 | /** CLKOUT enable control */ |
| frank26080115 | 0:84d7747641aa | 211 | #define CLKPWR_CLKOUTCFG_CLKOUT_EN ((uint32_t)(1<<8)) |
| frank26080115 | 0:84d7747641aa | 212 | /** CLKOUT activity indication */ |
| frank26080115 | 0:84d7747641aa | 213 | #define CLKPWR_CLKOUTCFG_CLKOUT_ACT ((uint32_t)(1<<9)) |
| frank26080115 | 0:84d7747641aa | 214 | /** Clock source selection bit mask */ |
| frank26080115 | 0:84d7747641aa | 215 | #define CLKPWR_CLKOUTCFG_BITMASK ((uint32_t)(0x3FF)) |
| frank26080115 | 0:84d7747641aa | 216 | |
| frank26080115 | 0:84d7747641aa | 217 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 218 | * Macro defines for PPL0 Control Register |
| frank26080115 | 0:84d7747641aa | 219 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 220 | /** PLL 0 control enable */ |
| frank26080115 | 0:84d7747641aa | 221 | #define CLKPWR_PLL0CON_ENABLE ((uint32_t)(0x01)) |
| frank26080115 | 0:84d7747641aa | 222 | /** PLL 0 control connect */ |
| frank26080115 | 0:84d7747641aa | 223 | #define CLKPWR_PLL0CON_CONNECT ((uint32_t)(0x02)) |
| frank26080115 | 0:84d7747641aa | 224 | /** PLL 0 control bit mask */ |
| frank26080115 | 0:84d7747641aa | 225 | #define CLKPWR_PLL0CON_BITMASK ((uint32_t)(0x03)) |
| frank26080115 | 0:84d7747641aa | 226 | |
| frank26080115 | 0:84d7747641aa | 227 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 228 | * Macro defines for PPL0 Configuration Register |
| frank26080115 | 0:84d7747641aa | 229 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 230 | /** PLL 0 Configuration MSEL field */ |
| frank26080115 | 0:84d7747641aa | 231 | #define CLKPWR_PLL0CFG_MSEL(n) ((uint32_t)(n&0x7FFF)) |
| frank26080115 | 0:84d7747641aa | 232 | /** PLL 0 Configuration NSEL field */ |
| frank26080115 | 0:84d7747641aa | 233 | #define CLKPWR_PLL0CFG_NSEL(n) ((uint32_t)((n<<16)&0xFF0000)) |
| frank26080115 | 0:84d7747641aa | 234 | /** PLL 0 Configuration bit mask */ |
| frank26080115 | 0:84d7747641aa | 235 | #define CLKPWR_PLL0CFG_BITMASK ((uint32_t)(0xFF7FFF)) |
| frank26080115 | 0:84d7747641aa | 236 | |
| frank26080115 | 0:84d7747641aa | 237 | |
| frank26080115 | 0:84d7747641aa | 238 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 239 | * Macro defines for PPL0 Status Register |
| frank26080115 | 0:84d7747641aa | 240 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 241 | /** PLL 0 MSEL value */ |
| frank26080115 | 0:84d7747641aa | 242 | #define CLKPWR_PLL0STAT_MSEL(n) ((uint32_t)(n&0x7FFF)) |
| frank26080115 | 0:84d7747641aa | 243 | /** PLL NSEL get value */ |
| frank26080115 | 0:84d7747641aa | 244 | #define CLKPWR_PLL0STAT_NSEL(n) ((uint32_t)((n>>16)&0xFF)) |
| frank26080115 | 0:84d7747641aa | 245 | /** PLL status enable bit */ |
| frank26080115 | 0:84d7747641aa | 246 | #define CLKPWR_PLL0STAT_PLLE ((uint32_t)(1<<24)) |
| frank26080115 | 0:84d7747641aa | 247 | /** PLL status Connect bit */ |
| frank26080115 | 0:84d7747641aa | 248 | #define CLKPWR_PLL0STAT_PLLC ((uint32_t)(1<<25)) |
| frank26080115 | 0:84d7747641aa | 249 | /** PLL status lock */ |
| frank26080115 | 0:84d7747641aa | 250 | #define CLKPWR_PLL0STAT_PLOCK ((uint32_t)(1<<26)) |
| frank26080115 | 0:84d7747641aa | 251 | |
| frank26080115 | 0:84d7747641aa | 252 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 253 | * Macro defines for PPL0 Feed Register |
| frank26080115 | 0:84d7747641aa | 254 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 255 | /** PLL0 Feed bit mask */ |
| frank26080115 | 0:84d7747641aa | 256 | #define CLKPWR_PLL0FEED_BITMASK ((uint32_t)0xFF) |
| frank26080115 | 0:84d7747641aa | 257 | |
| frank26080115 | 0:84d7747641aa | 258 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 259 | * Macro defines for PLL1 Control Register |
| frank26080115 | 0:84d7747641aa | 260 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 261 | /** USB PLL control enable */ |
| frank26080115 | 0:84d7747641aa | 262 | #define CLKPWR_PLL1CON_ENABLE ((uint32_t)(0x01)) |
| frank26080115 | 0:84d7747641aa | 263 | /** USB PLL control connect */ |
| frank26080115 | 0:84d7747641aa | 264 | #define CLKPWR_PLL1CON_CONNECT ((uint32_t)(0x02)) |
| frank26080115 | 0:84d7747641aa | 265 | /** USB PLL control bit mask */ |
| frank26080115 | 0:84d7747641aa | 266 | #define CLKPWR_PLL1CON_BITMASK ((uint32_t)(0x03)) |
| frank26080115 | 0:84d7747641aa | 267 | |
| frank26080115 | 0:84d7747641aa | 268 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 269 | * Macro defines for PLL1 Configuration Register |
| frank26080115 | 0:84d7747641aa | 270 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 271 | /** USB PLL MSEL set value */ |
| frank26080115 | 0:84d7747641aa | 272 | #define CLKPWR_PLL1CFG_MSEL(n) ((uint32_t)(n&0x1F)) |
| frank26080115 | 0:84d7747641aa | 273 | /** USB PLL PSEL set value */ |
| frank26080115 | 0:84d7747641aa | 274 | #define CLKPWR_PLL1CFG_PSEL(n) ((uint32_t)((n&0x03)<<5)) |
| frank26080115 | 0:84d7747641aa | 275 | /** USB PLL configuration bit mask */ |
| frank26080115 | 0:84d7747641aa | 276 | #define CLKPWR_PLL1CFG_BITMASK ((uint32_t)(0x7F)) |
| frank26080115 | 0:84d7747641aa | 277 | |
| frank26080115 | 0:84d7747641aa | 278 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 279 | * Macro defines for PLL1 Status Register |
| frank26080115 | 0:84d7747641aa | 280 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 281 | /** USB PLL MSEL get value */ |
| frank26080115 | 0:84d7747641aa | 282 | #define CLKPWR_PLL1STAT_MSEL(n) ((uint32_t)(n&0x1F)) |
| frank26080115 | 0:84d7747641aa | 283 | /** USB PLL PSEL get value */ |
| frank26080115 | 0:84d7747641aa | 284 | #define CLKPWR_PLL1STAT_PSEL(n) ((uint32_t)((n>>5)&0x03)) |
| frank26080115 | 0:84d7747641aa | 285 | /** USB PLL status enable bit */ |
| frank26080115 | 0:84d7747641aa | 286 | #define CLKPWR_PLL1STAT_PLLE ((uint32_t)(1<<8)) |
| frank26080115 | 0:84d7747641aa | 287 | /** USB PLL status Connect bit */ |
| frank26080115 | 0:84d7747641aa | 288 | #define CLKPWR_PLL1STAT_PLLC ((uint32_t)(1<<9)) |
| frank26080115 | 0:84d7747641aa | 289 | /** USB PLL status lock */ |
| frank26080115 | 0:84d7747641aa | 290 | #define CLKPWR_PLL1STAT_PLOCK ((uint32_t)(1<<10)) |
| frank26080115 | 0:84d7747641aa | 291 | |
| frank26080115 | 0:84d7747641aa | 292 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 293 | * Macro defines for PLL1 Feed Register |
| frank26080115 | 0:84d7747641aa | 294 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 295 | /** PLL1 Feed bit mask */ |
| frank26080115 | 0:84d7747641aa | 296 | #define CLKPWR_PLL1FEED_BITMASK ((uint32_t)0xFF) |
| frank26080115 | 0:84d7747641aa | 297 | |
| frank26080115 | 0:84d7747641aa | 298 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 299 | * Macro defines for CPU Clock Configuration Register |
| frank26080115 | 0:84d7747641aa | 300 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 301 | /** CPU Clock configuration bit mask */ |
| frank26080115 | 0:84d7747641aa | 302 | #define CLKPWR_CCLKCFG_BITMASK ((uint32_t)(0xFF)) |
| frank26080115 | 0:84d7747641aa | 303 | |
| frank26080115 | 0:84d7747641aa | 304 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 305 | * Macro defines for USB Clock Configuration Register |
| frank26080115 | 0:84d7747641aa | 306 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 307 | /** USB Clock Configuration bit mask */ |
| frank26080115 | 0:84d7747641aa | 308 | #define CLKPWR_USBCLKCFG_BITMASK ((uint32_t)(0x0F)) |
| frank26080115 | 0:84d7747641aa | 309 | |
| frank26080115 | 0:84d7747641aa | 310 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 311 | * Macro defines for IRC Trim Register |
| frank26080115 | 0:84d7747641aa | 312 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 313 | /** IRC Trim bit mask */ |
| frank26080115 | 0:84d7747641aa | 314 | #define CLKPWR_IRCTRIM_BITMASK ((uint32_t)(0x0F)) |
| frank26080115 | 0:84d7747641aa | 315 | |
| frank26080115 | 0:84d7747641aa | 316 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 317 | * Macro defines for Peripheral Clock Selection Register 0 and 1 |
| frank26080115 | 0:84d7747641aa | 318 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 319 | /** Peripheral Clock Selection 0 mask bit */ |
| frank26080115 | 0:84d7747641aa | 320 | #define CLKPWR_PCLKSEL0_BITMASK ((uint32_t)(0xFFF3F3FF)) |
| frank26080115 | 0:84d7747641aa | 321 | /** Peripheral Clock Selection 1 mask bit */ |
| frank26080115 | 0:84d7747641aa | 322 | #define CLKPWR_PCLKSEL1_BITMASK ((uint32_t)(0xFCF3F0F3)) |
| frank26080115 | 0:84d7747641aa | 323 | /** Macro to set peripheral clock of each type |
| frank26080115 | 0:84d7747641aa | 324 | * p: position of two bits that hold divider of peripheral clock |
| frank26080115 | 0:84d7747641aa | 325 | * n: value of divider of peripheral clock to be set */ |
| frank26080115 | 0:84d7747641aa | 326 | #define CLKPWR_PCLKSEL_SET(p,n) _SBF(p,n) |
| frank26080115 | 0:84d7747641aa | 327 | /** Macro to mask peripheral clock of each type */ |
| frank26080115 | 0:84d7747641aa | 328 | #define CLKPWR_PCLKSEL_BITMASK(p) _SBF(p,0x03) |
| frank26080115 | 0:84d7747641aa | 329 | /** Macro to get peripheral clock of each type */ |
| frank26080115 | 0:84d7747641aa | 330 | #define CLKPWR_PCLKSEL_GET(p, n) ((uint32_t)((n>>p)&0x03)) |
| frank26080115 | 0:84d7747641aa | 331 | |
| frank26080115 | 0:84d7747641aa | 332 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 333 | * Macro defines for Power Mode Control Register |
| frank26080115 | 0:84d7747641aa | 334 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 335 | /** Power mode control bit 0 */ |
| frank26080115 | 0:84d7747641aa | 336 | #define CLKPWR_PCON_PM0 ((uint32_t)(1<<0)) |
| frank26080115 | 0:84d7747641aa | 337 | /** Power mode control bit 1 */ |
| frank26080115 | 0:84d7747641aa | 338 | #define CLKPWR_PCON_PM1 ((uint32_t)(1<<1)) |
| frank26080115 | 0:84d7747641aa | 339 | /** Brown-Out Reduced Power Mode */ |
| frank26080115 | 0:84d7747641aa | 340 | #define CLKPWR_PCON_BODPDM ((uint32_t)(1<<2)) |
| frank26080115 | 0:84d7747641aa | 341 | /** Brown-Out Global Disable */ |
| frank26080115 | 0:84d7747641aa | 342 | #define CLKPWR_PCON_BOGD ((uint32_t)(1<<3)) |
| frank26080115 | 0:84d7747641aa | 343 | /** Brown Out Reset Disable */ |
| frank26080115 | 0:84d7747641aa | 344 | #define CLKPWR_PCON_BORD ((uint32_t)(1<<4)) |
| frank26080115 | 0:84d7747641aa | 345 | /** Sleep Mode entry flag */ |
| frank26080115 | 0:84d7747641aa | 346 | #define CLKPWR_PCON_SMFLAG ((uint32_t)(1<<8)) |
| frank26080115 | 0:84d7747641aa | 347 | /** Deep Sleep entry flag */ |
| frank26080115 | 0:84d7747641aa | 348 | #define CLKPWR_PCON_DSFLAG ((uint32_t)(1<<9)) |
| frank26080115 | 0:84d7747641aa | 349 | /** Power-down entry flag */ |
| frank26080115 | 0:84d7747641aa | 350 | #define CLKPWR_PCON_PDFLAG ((uint32_t)(1<<10)) |
| frank26080115 | 0:84d7747641aa | 351 | /** Deep Power-down entry flag */ |
| frank26080115 | 0:84d7747641aa | 352 | #define CLKPWR_PCON_DPDFLAG ((uint32_t)(1<<11)) |
| frank26080115 | 0:84d7747641aa | 353 | |
| frank26080115 | 0:84d7747641aa | 354 | /*********************************************************************//** |
| frank26080115 | 0:84d7747641aa | 355 | * Macro defines for Power Control for Peripheral Register |
| frank26080115 | 0:84d7747641aa | 356 | **********************************************************************/ |
| frank26080115 | 0:84d7747641aa | 357 | /** Power Control for Peripherals bit mask */ |
| frank26080115 | 0:84d7747641aa | 358 | #define CLKPWR_PCONP_BITMASK 0xEFEFF7DE |
| frank26080115 | 0:84d7747641aa | 359 | |
| frank26080115 | 0:84d7747641aa | 360 | /** |
| frank26080115 | 0:84d7747641aa | 361 | * @} |
| frank26080115 | 0:84d7747641aa | 362 | */ |
| frank26080115 | 0:84d7747641aa | 363 | |
| frank26080115 | 0:84d7747641aa | 364 | |
| frank26080115 | 0:84d7747641aa | 365 | /* Public Functions ----------------------------------------------------------- */ |
| frank26080115 | 0:84d7747641aa | 366 | /** @defgroup CLKPWR_Public_Functions CLKPWR Public Functions |
| frank26080115 | 0:84d7747641aa | 367 | * @{ |
| frank26080115 | 0:84d7747641aa | 368 | */ |
| frank26080115 | 0:84d7747641aa | 369 | |
| frank26080115 | 0:84d7747641aa | 370 | void CLKPWR_SetPCLKDiv (uint32_t ClkType, uint32_t DivVal); |
| frank26080115 | 0:84d7747641aa | 371 | uint32_t CLKPWR_GetPCLKSEL (uint32_t ClkType); |
| frank26080115 | 0:84d7747641aa | 372 | uint32_t CLKPWR_GetPCLK (uint32_t ClkType); |
| frank26080115 | 0:84d7747641aa | 373 | void CLKPWR_ConfigPPWR (uint32_t PPType, FunctionalState NewState); |
| frank26080115 | 0:84d7747641aa | 374 | void CLKPWR_Sleep(void); |
| frank26080115 | 0:84d7747641aa | 375 | void CLKPWR_DeepSleep(void); |
| frank26080115 | 0:84d7747641aa | 376 | void CLKPWR_PowerDown(void); |
| frank26080115 | 0:84d7747641aa | 377 | void CLKPWR_DeepPowerDown(void); |
| frank26080115 | 0:84d7747641aa | 378 | |
| frank26080115 | 0:84d7747641aa | 379 | /** |
| frank26080115 | 0:84d7747641aa | 380 | * @} |
| frank26080115 | 0:84d7747641aa | 381 | */ |
| frank26080115 | 0:84d7747641aa | 382 | |
| frank26080115 | 0:84d7747641aa | 383 | |
| frank26080115 | 0:84d7747641aa | 384 | #ifdef __cplusplus |
| frank26080115 | 0:84d7747641aa | 385 | } |
| frank26080115 | 0:84d7747641aa | 386 | #endif |
| frank26080115 | 0:84d7747641aa | 387 | |
| frank26080115 | 0:84d7747641aa | 388 | #endif /* LPC17XX_CLKPWR_H_ */ |
| frank26080115 | 0:84d7747641aa | 389 | |
| frank26080115 | 0:84d7747641aa | 390 | /** |
| frank26080115 | 0:84d7747641aa | 391 | * @} |
| frank26080115 | 0:84d7747641aa | 392 | */ |
| frank26080115 | 0:84d7747641aa | 393 | |
| frank26080115 | 0:84d7747641aa | 394 | /* --------------------------------- End Of File ------------------------------ */ |