Revision 639:b32fded6b0ae, committed 2016-09-27

Comitter:

floatlei

Date:

Tue Sep 27 09:40:53 2016 +0000

Parent:

638:56887a2974b9

Commit message:

sf

Changed in this revision

--- a/api/AnalogIn.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_H
-#define MBED_ANALOGIN_H
-
-#include "platform.h"
-
-#if DEVICE_ANALOGIN
-
-#include "analogin_api.h"
-
-namespace mbed {
-
-/** An analog input, used for reading the voltage on a pin
- *
- * Example:
- * @code
- * // Print messages when the AnalogIn is greater than 50%
- *
- * #include "mbed.h"
- *
- * AnalogIn temperature(p20);
- *
- * int main() {
- *     while(1) {
- *         if(temperature > 0.5) {
- *             printf("Too hot! (%f)", temperature.read());
- *         }
- *     }
- * }
- * @endcode
- */
-class AnalogIn {
-
-public:
-
-    /** Create an AnalogIn, connected to the specified pin
-     *
-     * @param pin AnalogIn pin to connect to
-     * @param name (optional) A string to identify the object
-     */
-    AnalogIn(PinName pin) {
-        analogin_init(&_adc, pin);
-    }
-
-    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
-     *
-     * @returns A floating-point value representing the current input voltage, measured as a percentage
-     */
-    float read() {
-        return analogin_read(&_adc);
-    }
-
-    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
-     *
-     * @returns
-     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
-     */
-    unsigned short read_u16() {
-        return analogin_read_u16(&_adc);
-    }
-
-#ifdef MBED_OPERATORS
-    /** An operator shorthand for read()
-     *
-     * The float() operator can be used as a shorthand for read() to simplify common code sequences
-     *
-     * Example:
-     * @code
-     * float x = volume.read();
-     * float x = volume;
-     *
-     * if(volume.read() > 0.25) { ... }
-     * if(volume > 0.25) { ... }
-     * @endcode
-     */
-    operator float() {
-        return read();
-    }
-#endif
-
-protected:
-    analogin_t _adc;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/AnalogOut.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_H
-#define MBED_ANALOGOUT_H
-
-#include "platform.h"
-
-#if DEVICE_ANALOGOUT
-
-#include "analogout_api.h"
-
-namespace mbed {
-
-/** An analog output, used for setting the voltage on a pin
- *
- * Example:
- * @code
- * // Make a sawtooth output
- *
- * #include "mbed.h"
- *
- * AnalogOut tri(p18);
- * int main() {
- *     while(1) {
- *         tri = tri + 0.01;
- *         wait_us(1);
- *         if(tri == 1) {
- *             tri = 0;
- *         }
- *     }
- * }
- * @endcode
- */
-class AnalogOut {
-
-public:
-
-    /** Create an AnalogOut connected to the specified pin
-     *
-     *  @param AnalogOut pin to connect to (18)
-     */
-    AnalogOut(PinName pin) {
-        analogout_init(&_dac, pin);
-    }
-
-    /** Set the output voltage, specified as a percentage (float)
-     *
-     *  @param value A floating-point value representing the output voltage,
-     *    specified as a percentage. The value should lie between
-     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
-     *    Values outside this range will be saturated to 0.0f or 1.0f.
-     */
-    void write(float value) {
-        analogout_write(&_dac, value);
-    }
-
-    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
-     *
-     *  @param value 16-bit unsigned short representing the output voltage,
-     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
-     */
-    void write_u16(unsigned short value) {
-        analogout_write_u16(&_dac, value);
-    }
-
-    /** Return the current output voltage setting, measured as a percentage (float)
-     *
-     *  @returns
-     *    A floating-point value representing the current voltage being output on the pin,
-     *    measured as a percentage. The returned value will lie between
-     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
-     *
-     *  @note
-     *    This value may not match exactly the value set by a previous write().
-     */
-    float read() {
-        return analogout_read(&_dac);
-    }
-
-#ifdef MBED_OPERATORS
-    /** An operator shorthand for write()
-     */
-    AnalogOut& operator= (float percent) {
-        write(percent);
-        return *this;
-    }
-
-    AnalogOut& operator= (AnalogOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** An operator shorthand for read()
-     */
-    operator float() {
-        return read();
-    }
-#endif
-
-protected:
-    dac_t _dac;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/BusIn.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSIN_H
-#define MBED_BUSIN_H
-
-#include "platform.h"
-#include "DigitalIn.h"
-
-namespace mbed {
-
-/** A digital input bus, used for reading the state of a collection of pins
- */
-class BusIn {
-
-public:
-    /* Group: Configuration Methods */
-
-    /** Create an BusIn, connected to the specified pins
-     *
-     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
-     *
-     * @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusIn(PinName pins[16]);
-
-    virtual ~BusIn();
-
-    /** Read the value of the input bus
-     *
-     *  @returns
-     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
-     */
-    int read();
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone
-     */
-    void mode(PinMode pull);
-
-    /** Binary mask of bus pins connected to actual pins (not NC pins)
-     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
-     *
-     *  @returns
-     *    Binary mask of connected pins
-     */
-    int mask() {
-        return _nc_mask;
-    }
-
-#ifdef MBED_OPERATORS
-    /** A shorthand for read()
-     */
-    operator int();
-
-    /** Access to particular bit in random-iterator fashion
-     */
-    DigitalIn & operator[] (int index);
-#endif
-
-protected:
-    DigitalIn* _pin[16];
-
-    /** Mask of bus's NC pins
-     * If bit[n] is set to 1 - pin is connected
-     * if bit[n] is cleared - pin is not connected (NC)
-     */
-    int _nc_mask;
-
-    /* disallow copy constructor and assignment operators */
-private:
-    BusIn(const BusIn&);
-    BusIn & operator = (const BusIn&);
-};
-
-} // namespace mbed
-
-#endif

--- a/api/BusInOut.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,117 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSINOUT_H
-#define MBED_BUSINOUT_H
-
-#include "DigitalInOut.h"
-
-namespace mbed {
-
-/** A digital input output bus, used for setting the state of a collection of pins
- */
-class BusInOut {
-
-public:
-
-    /** Create an BusInOut, connected to the specified pins
-     *
-     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
-     *
-     *  @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusInOut(PinName pins[16]);
-
-    virtual ~BusInOut();
-
-    /* Group: Access Methods */
-
-    /** Write the value to the output bus
-     *
-     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
-     */
-    void write(int value);
-
-    /** Read the value currently output on the bus
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated DigitalInOut pin setting
-     */
-    int read();
-
-    /** Set as an output
-     */
-    void output();
-
-    /** Set as an input
-     */
-    void input();
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone
-     */
-    void mode(PinMode pull);
-
-    /** Binary mask of bus pins connected to actual pins (not NC pins)
-     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
-     *
-     *  @returns
-     *    Binary mask of connected pins
-     */
-    int mask() {
-        return _nc_mask;
-    }
-
-#ifdef MBED_OPERATORS
-     /** A shorthand for write()
-     */
-    BusInOut& operator= (int v);
-    BusInOut& operator= (BusInOut& rhs);
-
-    /** Access to particular bit in random-iterator fashion
-    */
-    DigitalInOut& operator[] (int index);
-
-    /** A shorthand for read()
-     */
-    operator int();
-#endif
-
-protected:
-    DigitalInOut* _pin[16];
-
-    /** Mask of bus's NC pins
-     * If bit[n] is set to 1 - pin is connected
-     * if bit[n] is cleared - pin is not connected (NC)
-     */
-    int _nc_mask;
-
-    /* disallow copy constructor and assignment operators */
-private:
-    BusInOut(const BusInOut&);
-    BusInOut & operator = (const BusInOut&);
-};
-
-} // namespace mbed
-
-#endif

--- a/api/BusOut.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,101 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUSOUT_H
-#define MBED_BUSOUT_H
-
-#include "DigitalOut.h"
-
-namespace mbed {
-
-/** A digital output bus, used for setting the state of a collection of pins
- */
-class BusOut {
-
-public:
-
-    /** Create an BusOut, connected to the specified pins
-     *
-     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
-     *
-     *  @note
-     *  It is only required to specify as many pin variables as is required
-     *  for the bus; the rest will default to NC (not connected)
-     */
-    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
-           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
-           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
-           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
-
-    BusOut(PinName pins[16]);
-
-    virtual ~BusOut();
-
-    /** Write the value to the output bus
-     *
-     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
-     */
-    void write(int value);
-
-    /** Read the value currently output on the bus
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated DigitalOut pin setting
-     */
-    int read();
-
-    /** Binary mask of bus pins connected to actual pins (not NC pins)
-     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
-     *
-     *  @returns
-     *    Binary mask of connected pins
-     */
-    int mask() {
-        return _nc_mask;
-    }
-
-#ifdef MBED_OPERATORS
-    /** A shorthand for write()
-     */
-    BusOut& operator= (int v);
-    BusOut& operator= (BusOut& rhs);
-
-    /** Access to particular bit in random-iterator fashion
-     */
-    DigitalOut& operator[] (int index);
-
-    /** A shorthand for read()
-     */
-    operator int();
-#endif
-
-protected:
-    DigitalOut* _pin[16];
-
-    /** Mask of bus's NC pins
-     * If bit[n] is set to 1 - pin is connected
-     * if bit[n] is cleared - pin is not connected (NC)
-     */
-    int _nc_mask;
-
-   /* disallow copy constructor and assignment operators */
-private:
-    BusOut(const BusOut&);
-    BusOut & operator = (const BusOut&);
-};
-
-} // namespace mbed
-
-#endif

--- a/api/CAN.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,243 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_H
-#define MBED_CAN_H
-
-#include "platform.h"
-
-#if DEVICE_CAN
-
-#include "can_api.h"
-#include "can_helper.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** CANMessage class
- */
-class CANMessage : public CAN_Message {
-
-public:
-    /** Creates empty CAN message.
-     */
-    CANMessage() : CAN_Message() {
-        len    = 8;
-        type   = CANData;
-        format = CANStandard;
-        id     = 0;
-        memset(data, 0, 8);
-    }
-
-    /** Creates CAN message with specific content.
-     */
-    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
-      len    = _len & 0xF;
-      type   = _type;
-      format = _format;
-      id     = _id;
-      memcpy(data, _data, _len);
-    }
-
-    /** Creates CAN remote message.
-     */
-    CANMessage(int _id, CANFormat _format = CANStandard) {
-      len    = 0;
-      type   = CANRemote;
-      format = _format;
-      id     = _id;
-      memset(data, 0, 8);
-    }
-};
-
-/** A can bus client, used for communicating with can devices
- */
-class CAN {
-
-public:
-    /** Creates an CAN interface connected to specific pins.
-     *
-     *  @param rd read from transmitter
-     *  @param td transmit to transmitter
-     *
-     * Example:
-     * @code
-     * #include "mbed.h"
-     *
-     * Ticker ticker;
-     * DigitalOut led1(LED1);
-     * DigitalOut led2(LED2);
-     * CAN can1(p9, p10);
-     * CAN can2(p30, p29);
-     *
-     * char counter = 0;
-     *
-     * void send() {
-     *     if(can1.write(CANMessage(1337, &counter, 1))) {
-     *         printf("Message sent: %d\n", counter);
-     *         counter++;
-     *     }
-     *     led1 = !led1;
-     * }
-     *
-     * int main() {
-     *     ticker.attach(&send, 1);
-     *    CANMessage msg;
-     *     while(1) {
-     *         if(can2.read(msg)) {
-     *             printf("Message received: %d\n\n", msg.data[0]);
-     *             led2 = !led2;
-     *         }
-     *         wait(0.2);
-     *     }
-     * }
-     * @endcode
-     */
-    CAN(PinName rd, PinName td);
-    virtual ~CAN();
-
-    /** Set the frequency of the CAN interface
-     *
-     *  @param hz The bus frequency in hertz
-     *
-     *  @returns
-     *    1 if successful,
-     *    0 otherwise
-     */
-    int frequency(int hz);
-
-    /** Write a CANMessage to the bus.
-     *
-     *  @param msg The CANMessage to write.
-     *
-     *  @returns
-     *    0 if write failed,
-     *    1 if write was successful
-     */
-    int write(CANMessage msg);
-
-    /** Read a CANMessage from the bus.
-     *
-     *  @param msg A CANMessage to read to.
-     *  @param handle message filter handle (0 for any message)
-     *
-     *  @returns
-     *    0 if no message arrived,
-     *    1 if message arrived
-     */
-    int read(CANMessage &msg, int handle = 0);
-
-    /** Reset CAN interface.
-     *
-     * To use after error overflow.
-     */
-    void reset();
-
-    /** Puts or removes the CAN interface into silent monitoring mode
-     *
-     *  @param silent boolean indicating whether to go into silent mode or not
-     */
-    void monitor(bool silent);
-
-    enum Mode {
-        Reset = 0,
-        Normal,
-        Silent,
-        LocalTest,
-        GlobalTest,
-        SilentTest
-    };
-
-    /** Change CAN operation to the specified mode
-     *
-     *  @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
-     *
-     *  @returns
-     *    0 if mode change failed or unsupported,
-     *    1 if mode change was successful
-     */
-    int mode(Mode mode);
-
-    /** Filter out incomming messages
-     *
-     *  @param id the id to filter on
-     *  @param mask the mask applied to the id
-     *  @param format format to filter on (Default CANAny)
-     *  @param handle message filter handle (Optional)
-     *
-     *  @returns
-     *    0 if filter change failed or unsupported,
-     *    new filter handle if successful
-     */
-    int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
-
-    /** Returns number of read errors to detect read overflow errors.
-     */
-    unsigned char rderror();
-
-    /** Returns number of write errors to detect write overflow errors.
-     */
-    unsigned char tderror();
-
-    enum IrqType {
-        RxIrq = 0,
-        TxIrq,
-        EwIrq,
-        DoIrq,
-        WuIrq,
-        EpIrq,
-        AlIrq,
-        BeIrq,
-        IdIrq
-    };
-
-    /** Attach a function to call whenever a CAN frame received interrupt is
-     *  generated.
-     *
-     *  @param fptr A pointer to a void function, or 0 to set as none
-     *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
-     */
-    void attach(void (*fptr)(void), IrqType type=RxIrq);
-
-   /** Attach a member function to call whenever a CAN frame received interrupt
-    *  is generated.
-    *
-    *  @param tptr pointer to the object to call the member function on
-    *  @param mptr pointer to the member function to be called
-    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
-    */
-   template<typename T>
-   void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
-        if((mptr != NULL) && (tptr != NULL)) {
-            _irq[type].attach(tptr, mptr);
-            can_irq_set(&_can, (CanIrqType)type, 1);
-        }
-        else {
-            can_irq_set(&_can, (CanIrqType)type, 0);
-        }
-    }
-
-    static void _irq_handler(uint32_t id, CanIrqType type);
-
-protected:
-    can_t           _can;
-    FunctionPointer _irq[9];
-};
-
-} // namespace mbed
-
-#endif
-
-#endif    // MBED_CAN_H

--- a/api/CThunk.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,202 +0,0 @@
-/* General C++ Object Thunking class
- *
- * - allows direct callbacks to non-static C++ class functions
- * - keeps track for the corresponding class instance
- * - supports an optional context parameter for the called function
- * - ideally suited for class object receiving interrupts (NVIC_SetVector)
- *
- * Copyright (c) 2014-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef __CTHUNK_H__
-#define __CTHUNK_H__
-
-#define CTHUNK_ADDRESS 1
-
-#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)
-#define CTHUNK_VARIABLES volatile uint32_t code[1]
-/**
-* CTHUNK disassembly for Cortex-M3/M4 (thumb2):
-* * ldm.w pc,{r0,r1,r2,pc}
-*
-* This instruction loads the arguments for the static thunking function to r0-r2, and
-* branches to that function by loading its address into PC.
-*
-* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
-* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
-*/
-#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
-
-#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0)
-/*
-* CTHUNK disassembly for Cortex M0 (thumb):
-* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
-* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1)
-* * add r4,pc set up address to load arguments from (immediately following this code block) (2)
-* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function
-* * blx r3 call static thunk function
-* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function
-*/
-#define CTHUNK_VARIABLES volatile uint32_t code[3]
-#define CTHUNK_ASSIGMENT do {                              \
-                             m_thunk.code[0] = 0x2404B51F; \
-                             m_thunk.code[1] = 0xCC0F447C; \
-                             m_thunk.code[2] = 0xBD1F4798; \
-                         } while (0)
-
-#else
-#error "Target is not currently suported."
-#endif
-
-/* IRQ/Exception compatible thunk entry function */
-typedef void (*CThunkEntry)(void);
-
-template<class T>
-class CThunk
-{
-    public:
-        typedef void (T::*CCallbackSimple)(void);
-        typedef void (T::*CCallback)(void* context);
-
-        inline CThunk(T *instance)
-        {
-            init(instance, NULL, NULL);
-        }
-
-        inline CThunk(T *instance, CCallback callback)
-        {
-            init(instance, callback, NULL);
-        }
-
-        ~CThunk() {
-
-        }
-
-        inline CThunk(T *instance, CCallbackSimple callback)
-        {
-            init(instance, (CCallback)callback, NULL);
-        }
-
-        inline CThunk(T &instance, CCallback callback)
-        {
-            init(instance, callback, NULL);
-        }
-
-        inline CThunk(T &instance, CCallbackSimple callback)
-        {
-            init(instance, (CCallback)callback, NULL);
-        }
-
-        inline CThunk(T &instance, CCallback callback, void* context)
-        {
-            init(instance, callback, context);
-        }
-
-        inline void callback(CCallback callback)
-        {
-            m_callback = callback;
-        }
-
-        inline void callback(CCallbackSimple callback)
-        {
-            m_callback = (CCallback)callback;
-        }
-
-        inline void context(void* context)
-        {
-            m_thunk.context = (uint32_t)context;
-        }
-
-        inline void context(uint32_t context)
-        {
-            m_thunk.context = context;
-        }
-        
-        inline uint32_t entry(void)
-        {
-            return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
-        }
-
-        /* get thunk entry point for connecting rhunk to an IRQ table */
-        inline operator CThunkEntry(void)
-        {
-            return (CThunkEntry)entry();
-        }
-
-        /* get thunk entry point for connecting rhunk to an IRQ table */
-        inline operator uint32_t(void)
-        {
-            return entry();
-        }
-
-        /* simple test function */
-        inline void call(void)
-        {
-            (((CThunkEntry)(entry()))());
-        }
-
-    private:
-        T* m_instance;
-        volatile CCallback m_callback;
-
-// TODO: this needs proper fix, to refactor toolchain header file and all its use
-// PACKED there is not defined properly for IAR
-#if defined (__ICCARM__)
-        typedef __packed struct
-        {
-            CTHUNK_VARIABLES;
-            volatile uint32_t instance;
-            volatile uint32_t context;
-            volatile uint32_t callback;
-            volatile uint32_t trampoline;
-        }  CThunkTrampoline;
-#else
-        typedef struct
-        {
-            CTHUNK_VARIABLES;
-            volatile uint32_t instance;
-            volatile uint32_t context;
-            volatile uint32_t callback;
-            volatile uint32_t trampoline;
-        } __attribute__((__packed__)) CThunkTrampoline;
-#endif
-
-        static void trampoline(T* instance, void* context, CCallback* callback)
-        {
-            if(instance && *callback) {
-                (static_cast<T*>(instance)->**callback)(context);
-            }
-        }
-
-        volatile CThunkTrampoline m_thunk;
-
-        inline void init(T *instance, CCallback callback, void* context)
-        {
-            /* remember callback - need to add this level of redirection
-               as pointer size for member functions differs between platforms */
-            m_callback = callback;
-
-            /* populate thunking trampoline */
-            CTHUNK_ASSIGMENT;
-            m_thunk.context = (uint32_t)context;
-            m_thunk.instance = (uint32_t)instance;
-            m_thunk.callback = (uint32_t)&m_callback;
-            m_thunk.trampoline = (uint32_t)&trampoline;
-
-            __ISB();
-            __DSB();
-        }
-};
-
-#endif/*__CTHUNK_H__*/

--- a/api/CallChain.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,181 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CALLCHAIN_H
-#define MBED_CALLCHAIN_H
-
-#include "FunctionPointer.h"
-#include <string.h>
-
-namespace mbed {
-
-/** Group one or more functions in an instance of a CallChain, then call them in
- * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
- * but can be used for other purposes.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * CallChain chain;
- *
- * void first(void) {
- *     printf("'first' function.\n");
- * }
- *
- * void second(void) {
- *     printf("'second' function.\n");
- * }
- *
- * class Test {
- * public:
- *     void f(void) {
- *         printf("A::f (class member).\n");
- *     }
- * };
- *
- * int main() {
- *     Test test;
- *
- *     chain.add(second);
- *     chain.add_front(first);
- *     chain.add(&test, &Test::f);
- *     chain.call();
- * }
- * @endcode
- */
-
-typedef FunctionPointer* pFunctionPointer_t;
-
-class CallChain {
-public:
-    /** Create an empty chain
-     *
-     *  @param size (optional) Initial size of the chain
-     */
-    CallChain(int size = 4);
-    virtual ~CallChain();
-
-    /** Add a function at the end of the chain
-     *
-     *  @param function A pointer to a void function
-     *
-     *  @returns
-     *  The function object created for 'function'
-     */
-    pFunctionPointer_t add(void (*function)(void));
-
-    /** Add a function at the end of the chain
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *
-     *  @returns
-     *  The function object created for 'tptr' and 'mptr'
-     */
-    template<typename T>
-    pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
-        return common_add(new FunctionPointer(tptr, mptr));
-    }
-
-    /** Add a function at the beginning of the chain
-     *
-     *  @param function A pointer to a void function
-     *
-     *  @returns
-     *  The function object created for 'function'
-     */
-    pFunctionPointer_t add_front(void (*function)(void));
-
-    /** Add a function at the beginning of the chain
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *
-     *  @returns
-     *  The function object created for 'tptr' and 'mptr'
-     */
-    template<typename T>
-    pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
-        return common_add_front(new FunctionPointer(tptr, mptr));
-    }
-
-    /** Get the number of functions in the chain
-     */
-    int size() const;
-
-    /** Get a function object from the chain
-     *
-     *  @param i function object index
-     *
-     *  @returns
-     *  The function object at position 'i' in the chain
-     */
-    pFunctionPointer_t get(int i) const;
-
-    /** Look for a function object in the call chain
-     *
-     *  @param f the function object to search
-     *
-     *  @returns
-     *  The index of the function object if found, -1 otherwise.
-     */
-    int find(pFunctionPointer_t f) const;
-
-    /** Clear the call chain (remove all functions in the chain).
-     */
-    void clear();
-
-    /** Remove a function object from the chain
-     *
-     *  @arg f the function object to remove
-     *
-     *  @returns
-     *  true if the function object was found and removed, false otherwise.
-     */
-    bool remove(pFunctionPointer_t f);
-
-    /** Call all the functions in the chain in sequence
-     */
-    void call();
-
-#ifdef MBED_OPERATORS
-    void operator ()(void) {
-        call();
-    }
-    pFunctionPointer_t operator [](int i) const {
-        return get(i);
-    }
-#endif
-
-private:
-    void _check_size();
-    pFunctionPointer_t common_add(pFunctionPointer_t pf);
-    pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
-
-    pFunctionPointer_t* _chain;
-    int _size;
-    int _elements;
-
-    /* disallow copy constructor and assignment operators */
-private:
-    CallChain(const CallChain&);
-    CallChain & operator = (const CallChain&);
-};
-
-} // namespace mbed
-
-#endif
-

--- a/api/CircularBuffer.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CIRCULARBUFFER_H
-#define MBED_CIRCULARBUFFER_H
-
-namespace mbed {
-
-/** Templated Circular buffer class
- */
-template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
-class CircularBuffer {
-public:
-    CircularBuffer() : _head(0), _tail(0), _full(false) {
-    }
-
-    ~CircularBuffer() {
-    }
-
-    /** Push the transaction to the buffer. This overwrites the buffer if it's
-     *  full
-     *
-     * @param data Data to be pushed to the buffer
-     */
-    void push(const T& data) {
-        if (full()) {
-            _tail++;
-            _tail %= BufferSize;
-        }
-        _pool[_head++] = data;
-        _head %= BufferSize;
-        if (_head == _tail) {
-            _full = true;
-        }
-    }
-
-    /** Pop the transaction from the buffer
-     *
-     * @param data Data to be pushed to the buffer
-     * @return True if the buffer is not empty and data contains a transaction, false otherwise
-     */
-    bool pop(T& data) {
-        if (!empty()) {
-            data = _pool[_tail++];
-            _tail %= BufferSize;
-            _full = false;
-            return true;
-        }
-        return false;
-    }
-
-    /** Check if the buffer is empty
-     *
-     * @return True if the buffer is empty, false if not
-     */
-    bool empty() {
-        return (_head == _tail) && !_full;
-    }
-
-    /** Check if the buffer is full
-     *
-     * @return True if the buffer is full, false if not
-     */
-    bool full() {
-        return _full;
-    }
-
-    /** Reset the buffer
-     *
-     */
-    void reset() {
-        _head = 0;
-        _tail = 0;
-        _full = false;
-    }
-
-private:
-    T _pool[BufferSize];
-    volatile CounterType _head;
-    volatile CounterType _tail;
-    volatile bool _full;
-};
-
-}
-
-#endif

--- a/api/DigitalIn.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,107 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALIN_H
-#define MBED_DIGITALIN_H
-
-#include "platform.h"
-
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital input, used for reading the state of a pin
- *
- * Example:
- * @code
- * // Flash an LED while a DigitalIn is true
- *
- * #include "mbed.h"
- *
- * DigitalIn enable(p5);
- * DigitalOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         if(enable) {
- *             led = !led;
- *         }
- *         wait(0.25);
- *     }
- * }
- * @endcode
- */
-class DigitalIn {
-
-public:
-    /** Create a DigitalIn connected to the specified pin
-     *
-     *  @param pin DigitalIn pin to connect to
-     */
-    DigitalIn(PinName pin) : gpio() {
-        gpio_init_in(&gpio, pin);
-    }
-
-    /** Create a DigitalIn connected to the specified pin
-     *
-     *  @param pin DigitalIn pin to connect to
-     *  @param mode the initial mode of the pin
-     */
-    DigitalIn(PinName pin, PinMode mode) : gpio() {
-        gpio_init_in_ex(&gpio, pin, mode);
-    }
-    /** Read the input, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    An integer representing the state of the input pin,
-     *    0 for logical 0, 1 for logical 1
-     */
-    int read() {
-        return gpio_read(&gpio);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode pull) {
-        gpio_mode(&gpio, pull);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    Non zero value if pin is connected to uc GPIO
-     *    0 if gpio object was initialized with NC
-     */
-    int is_connected() {
-        return gpio_is_connected(&gpio);
-    }
-
-#ifdef MBED_OPERATORS
-    /** An operator shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-#endif
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif

--- a/api/DigitalInOut.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,124 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALINOUT_H
-#define MBED_DIGITALINOUT_H
-
-#include "platform.h"
-
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital input/output, used for setting or reading a bi-directional pin
- */
-class DigitalInOut {
-
-public:
-    /** Create a DigitalInOut connected to the specified pin
-     *
-     *  @param pin DigitalInOut pin to connect to
-     */
-    DigitalInOut(PinName pin) : gpio() {
-        gpio_init_in(&gpio, pin);
-    }
-
-    /** Create a DigitalInOut connected to the specified pin
-     *
-     *  @param pin DigitalInOut pin to connect to
-     *  @param direction the initial direction of the pin
-     *  @param mode the initial mode of the pin
-     *  @param value the initial value of the pin if is an output
-     */
-    DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
-        gpio_init_inout(&gpio, pin, direction, mode, value);
-    }
-
-    /** Set the output, specified as 0 or 1 (int)
-     *
-     *  @param value An integer specifying the pin output value,
-     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
-     */
-    void write(int value) {
-        gpio_write(&gpio, value);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    an integer representing the output setting of the pin if it is an output,
-     *    or read the input if set as an input
-     */
-    int read() {
-        return gpio_read(&gpio);
-    }
-
-    /** Set as an output
-     */
-    void output() {
-        gpio_dir(&gpio, PIN_OUTPUT);
-    }
-
-    /** Set as an input
-     */
-    void input() {
-        gpio_dir(&gpio, PIN_INPUT);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode pull) {
-        gpio_mode(&gpio, pull);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    Non zero value if pin is connected to uc GPIO
-     *    0 if gpio object was initialized with NC
-     */
-    int is_connected() {
-        return gpio_is_connected(&gpio);
-    }
-
-#ifdef MBED_OPERATORS
-    /** A shorthand for write()
-     */
-    DigitalInOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    DigitalInOut& operator= (DigitalInOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-#endif
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif

--- a/api/DigitalOut.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,116 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIGITALOUT_H
-#define MBED_DIGITALOUT_H
-
-#include "platform.h"
-#include "gpio_api.h"
-
-namespace mbed {
-
-/** A digital output, used for setting the state of a pin
- *
- * Example:
- * @code
- * // Toggle a LED
- * #include "mbed.h"
- *
- * DigitalOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         led = !led;
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class DigitalOut {
-
-public:
-    /** Create a DigitalOut connected to the specified pin
-     *
-     *  @param pin DigitalOut pin to connect to
-     */
-    DigitalOut(PinName pin) : gpio() {
-        gpio_init_out(&gpio, pin);
-    }
-
-    /** Create a DigitalOut connected to the specified pin
-     *
-     *  @param pin DigitalOut pin to connect to
-     *  @param value the initial pin value
-     */
-    DigitalOut(PinName pin, int value) : gpio() {
-        gpio_init_out_ex(&gpio, pin, value);
-    }
-
-    /** Set the output, specified as 0 or 1 (int)
-     *
-     *  @param value An integer specifying the pin output value,
-     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
-     */
-    void write(int value) {
-        gpio_write(&gpio, value);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    an integer representing the output setting of the pin,
-     *    0 for logical 0, 1 for logical 1
-     */
-    int read() {
-        return gpio_read(&gpio);
-    }
-
-    /** Return the output setting, represented as 0 or 1 (int)
-     *
-     *  @returns
-     *    Non zero value if pin is connected to uc GPIO
-     *    0 if gpio object was initialized with NC
-     */
-    int is_connected() {
-        return gpio_is_connected(&gpio);
-    }
-
-#ifdef MBED_OPERATORS
-    /** A shorthand for write()
-     */
-    DigitalOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    DigitalOut& operator= (DigitalOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-#endif
-
-protected:
-    gpio_t gpio;
-};
-
-} // namespace mbed
-
-#endif

--- a/api/DirHandle.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DIRHANDLE_H
-#define MBED_DIRHANDLE_H
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-#   define NAME_MAX 255
-typedef int mode_t;
-
-#else
-#   include <sys/syslimits.h>
-#endif
-
-#include "FileHandle.h"
-
-struct dirent {
-    char d_name[NAME_MAX+1];
-};
-
-namespace mbed {
-
-/** Represents a directory stream. Objects of this type are returned
- *  by a FileSystemLike's opendir method. Implementations must define
- *  at least closedir, readdir and rewinddir.
- *
- *  If a FileSystemLike class defines the opendir method, then the
- *  directories of an object of that type can be accessed by
- *  DIR *d = opendir("/example/directory") (or opendir("/example")
- *  to open the root of the filesystem), and then using readdir(d) etc.
- *
- *  The root directory is considered to contain all FileLike and
- *  FileSystemLike objects, so the DIR* returned by opendir("/") will
- *  reflect this.
- */
-class DirHandle {
-
-public:
-    /** Closes the directory.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on error.
-     */
-    virtual int closedir()=0;
-
-    /** Return the directory entry at the current position, and
-     *  advances the position to the next entry.
-     *
-     * @returns
-     *  A pointer to a dirent structure representing the
-     *  directory entry at the current position, or NULL on reaching
-     *  end of directory or error.
-     */
-    virtual struct dirent *readdir()=0;
-
-    /** Resets the position to the beginning of the directory.
-     */
-    virtual void rewinddir()=0;
-
-    /** Returns the current position of the DirHandle.
-     *
-     * @returns
-     *   the current position,
-     *  -1 on error.
-     */
-    virtual off_t telldir() { return -1; }
-
-    /** Sets the position of the DirHandle.
-     *
-     *  @param location The location to seek to. Must be a value returned by telldir.
-     */
-    virtual void seekdir(off_t location) { }
-
-    virtual ~DirHandle() {}
-};
-
-} // namespace mbed
-
-typedef mbed::DirHandle DIR;
-
-extern "C" {
-    DIR *opendir(const char*);
-    struct dirent *readdir(DIR *);
-    int closedir(DIR*);
-    void rewinddir(DIR*);
-    long telldir(DIR*);
-    void seekdir(DIR*, long);
-    int mkdir(const char *name, mode_t n);
-};
-
-#endif /* MBED_DIRHANDLE_H */

--- a/api/Ethernet.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,170 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_H
-#define MBED_ETHERNET_H
-
-#include "platform.h"
-
-#if DEVICE_ETHERNET
-
-namespace mbed {
-
-/** An ethernet interface, to use with the ethernet pins.
- *
- * Example:
- * @code
- * // Read destination and source from every ethernet packet
- *
- * #include "mbed.h"
- *
- * Ethernet eth;
- *
- * int main() {
- *     char buf[0x600];
- *
- *     while(1) {
- *         int size = eth.receive();
- *         if(size > 0) {
- *             eth.read(buf, size);
- *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
- *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
- *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
- *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
- *         }
- *
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-class Ethernet {
-
-public:
-
-    /** Initialise the ethernet interface.
-     */
-    Ethernet();
-
-    /** Powers the hardware down.
-     */
-    virtual ~Ethernet();
-
-    enum Mode {
-        AutoNegotiate,
-        HalfDuplex10,
-        FullDuplex10,
-        HalfDuplex100,
-        FullDuplex100
-    };
-
-    /** Writes into an outgoing ethernet packet.
-     *
-     *  It will append size bytes of data to the previously written bytes.
-     *
-     *  @param data An array to write.
-     *  @param size The size of data.
-     *
-     *  @returns
-     *   The number of written bytes.
-     */
-    int write(const char *data, int size);
-
-    /** Send an outgoing ethernet packet.
-     *
-     *  After filling in the data in an ethernet packet it must be send.
-     *  Send will provide a new packet to write to.
-     *
-     *  @returns
-     *    0 if the sending was failed,
-     *    or the size of the packet successfully sent.
-     */
-    int send();
-
-    /** Recevies an arrived ethernet packet.
-     *
-     *  Receiving an ethernet packet will drop the last received ethernet packet
-     *  and make a new ethernet packet ready to read.
-     *  If no ethernet packet is arrived it will return 0.
-     *
-     *  @returns
-     *    0 if no ethernet packet is arrived,
-     *    or the size of the arrived packet.
-     */
-    int receive();
-
-    /** Read from an recevied ethernet packet.
-     *
-     *  After receive returnd a number bigger than 0it is
-     *  possible to read bytes from this packet.
-     *  Read will write up to size bytes into data.
-     *
-     *  It is possible to use read multible times.
-     *  Each time read will start reading after the last read byte before.
-     *
-     *  @returns
-     *  The number of byte read.
-     */
-    int read(char *data, int size);
-
-    /** Gives the ethernet address of the mbed.
-     *
-     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
-     */
-    void address(char *mac);
-
-    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
-     *
-     *  @returns
-     *   0 if no ethernet link is pressent,
-     *   1 if an ethernet link is pressent.
-     *
-     * Example:
-     * @code
-     * // Using the Ethernet link function
-     * #include "mbed.h"
-     *
-     * Ethernet eth;
-     *
-     * int main() {
-     *     wait(1); // Needed after startup.
-     *     if (eth.link()) {
-     *          printf("online\n");
-     *     } else {
-     *          printf("offline\n");
-     *     }
-     * }
-     * @endcode
-     */
-    int link();
-
-    /** Sets the speed and duplex parameters of an ethernet link
-     *
-     * - AutoNegotiate      Auto negotiate speed and duplex
-     * - HalfDuplex10       10 Mbit, half duplex
-     * - FullDuplex10       10 Mbit, full duplex
-     * - HalfDuplex100      100 Mbit, half duplex
-     * - FullDuplex100      100 Mbit, full duplex
-     *
-     *  @param mode the speed and duplex mode to set the link to:
-     */
-    void set_link(Mode mode);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/FileBase.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,80 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEBASE_H
-#define MBED_FILEBASE_H
-
-typedef int FILEHANDLE;
-
-#include <stdio.h>
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-#    define O_RDONLY 0
-#    define O_WRONLY 1
-#    define O_RDWR   2
-#    define O_CREAT  0x0200
-#    define O_TRUNC  0x0400
-#    define O_APPEND 0x0008
-
-#    define NAME_MAX 255
-
-typedef int mode_t;
-typedef int ssize_t;
-typedef long off_t;
-
-#else
-#    include <sys/fcntl.h>
-#    include <sys/types.h>
-#    include <sys/syslimits.h>
-#endif
-
-#include "platform.h"
-
-namespace mbed {
-
-typedef enum {
-    FilePathType,
-    FileSystemPathType
-} PathType;
-
-class FileBase {
-public:
-    FileBase(const char *name, PathType t);
-
-    virtual ~FileBase();
-
-    const char* getName(void);
-    PathType    getPathType(void);
-
-    static FileBase *lookup(const char *name, unsigned int len);
-
-    static FileBase *get(int n);
-
-protected:
-    static FileBase *_head;
-
-    FileBase   *_next;
-    const char *_name;
-    PathType    _path_type;
-
-    /* disallow copy constructor and assignment operators */
-private:
-    FileBase(const FileBase&);
-    FileBase & operator = (const FileBase&);
-};
-
-} // namespace mbed
-
-#endif

--- a/api/FileHandle.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,119 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEHANDLE_H
-#define MBED_FILEHANDLE_H
-
-typedef int FILEHANDLE;
-
-#include <stdio.h>
-
-#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
-typedef int ssize_t;
-typedef long off_t;
-
-#else
-#   include <sys/types.h>
-#endif
-
-namespace mbed {
-
-/** An OO equivalent of the internal FILEHANDLE variable
- *  and associated _sys_* functions.
- *
- * FileHandle is an abstract class, needing at least sys_write and
- *  sys_read to be implmented for a simple interactive device.
- *
- * No one ever directly tals to/instanciates a FileHandle - it gets
- *  created by FileSystem, and wrapped up by stdio.
- */
-class FileHandle {
-
-public:
-    /** Write the contents of a buffer to the file
-     *
-     *  @param buffer the buffer to write from
-     *  @param length the number of characters to write
-     *
-     *  @returns
-     *  The number of characters written (possibly 0) on success, -1 on error.
-     */
-    virtual ssize_t write(const void* buffer, size_t length) = 0;
-
-    /** Close the file
-     *
-     *  @returns
-     *  Zero on success, -1 on error.
-     */
-    virtual int close() = 0;
-
-    /** Function read
-     *  Reads the contents of the file into a buffer
-     *
-     *  @param buffer the buffer to read in to
-     *  @param length the number of characters to read
-     *
-     *  @returns
-     *  The number of characters read (zero at end of file) on success, -1 on error.
-     */
-    virtual ssize_t read(void* buffer, size_t length) = 0;
-
-    /** Check if the handle is for a interactive terminal device.
-     * If so, line buffered behaviour is used by default
-     *
-     *  @returns
-     *    1 if it is a terminal,
-     *    0 otherwise
-     */
-    virtual int isatty() = 0;
-
-    /** Move the file position to a given offset from a given location.
-     *
-     *  @param offset The offset from whence to move to
-     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
-     *   current file position, or SEEK_END for the end of the file.
-     *
-     *  @returns
-     *    new file position on success,
-     *    -1 on failure or unsupported
-     */
-    virtual off_t lseek(off_t offset, int whence) = 0;
-
-    /** Flush any buffers associated with the FileHandle, ensuring it
-     *  is up to date on disk
-     *
-     *  @returns
-     *    0 on success or un-needed,
-     *   -1 on error
-     */
-    virtual int fsync() = 0;
-
-    virtual off_t flen() {
-        /* remember our current position */
-        off_t pos = lseek(0, SEEK_CUR);
-        if(pos == -1) return -1;
-        /* seek to the end to get the file length */
-        off_t res = lseek(0, SEEK_END);
-        /* return to our old position */
-        lseek(pos, SEEK_SET);
-        return res;
-    }
-
-    virtual ~FileHandle();
-};
-
-} // namespace mbed
-
-#endif

--- a/api/FileLike.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILELIKE_H
-#define MBED_FILELIKE_H
-
-#include "FileBase.h"
-#include "FileHandle.h"
-
-namespace mbed {
-
-/* Class FileLike
- *  A file-like object is one that can be opened with fopen by
- *  fopen("/name", mode). It is intersection of the classes Base and
- *  FileHandle.
- */
-class FileLike : public FileHandle, public FileBase {
-
-public:
-    /* Constructor FileLike
-     *
-     * Variables
-     *  name - The name to use to open the file.
-     */
-    FileLike(const char *name);
-
-    virtual ~FileLike();
-};
-
-} // namespace mbed
-
-#endif

--- a/api/FilePath.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,46 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILEPATH_H
-#define MBED_FILEPATH_H
-
-#include "platform.h"
-
-#include "FileSystemLike.h"
-#include "FileLike.h"
-
-namespace mbed {
-
-class FilePath {
-public:
-    FilePath(const char* file_path);
-
-    const char* fileName(void);
-
-    bool          isFileSystem(void);
-    FileSystemLike* fileSystem(void);
-
-    bool    isFile(void);
-    FileLike* file(void);
-    bool    exists(void);
-
-private:
-    const char* file_name;
-    FileBase* fb;
-};
-
-} // namespace mbed
-
-#endif

--- a/api/FileSystemLike.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FILESYSTEMLIKE_H
-#define MBED_FILESYSTEMLIKE_H
-
-#include "platform.h"
-
-#include "FileBase.h"
-#include "FileHandle.h"
-#include "DirHandle.h"
-
-namespace mbed {
-
-/** A filesystem-like object is one that can be used to open files
- *  though it by fopen("/name/filename", mode)
- *
- *  Implementations must define at least open (the default definitions
- *  of the rest of the functions just return error values).
- */
-class FileSystemLike : public FileBase {
-
-public:
-    /** FileSystemLike constructor
-     *
-     *  @param name The name to use for the filesystem.
-     */
-    FileSystemLike(const char *name);
-
-    virtual ~FileSystemLike();
-
-    static DirHandle *opendir();
-    friend class BaseDirHandle;
-
-    /** Opens a file from the filesystem
-     *
-     *  @param filename The name of the file to open.
-     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
-     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.
-     *
-     *  @returns
-     *    A pointer to a FileHandle object representing the
-     *   file on success, or NULL on failure.
-     */
-    virtual FileHandle *open(const char *filename, int flags) = 0;
-
-    /** Remove a file from the filesystem.
-     *
-     *  @param filename the name of the file to remove.
-     *  @param returns 0 on success, -1 on failure.
-     */
-    virtual int remove(const char *filename) { return -1; };
-
-    /** Rename a file in the filesystem.
-     *
-     *  @param oldname the name of the file to rename.
-     *  @param newname the name to rename it to.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on failure.
-     */
-    virtual int rename(const char *oldname, const char *newname) { return -1; };
-
-    /** Opens a directory in the filesystem and returns a DirHandle
-     *   representing the directory stream.
-     *
-     *  @param name The name of the directory to open.
-     *
-     *  @returns
-     *    A DirHandle representing the directory stream, or
-     *   NULL on failure.
-     */
-    virtual DirHandle *opendir(const char *name) { return NULL; };
-
-    /** Creates a directory in the filesystem.
-     *
-     *  @param name The name of the directory to create.
-     *  @param mode The permissions to create the directory with.
-     *
-     *  @returns
-     *    0 on success,
-     *   -1 on failure.
-     */
-    virtual int mkdir(const char *name, mode_t mode) { return -1; }
-
-    // TODO other filesystem functions (mkdir, rm, rn, ls etc)
-};
-
-} // namespace mbed
-
-#endif

--- a/api/FunctionPointer.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,202 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_FUNCTIONPOINTER_H
-#define MBED_FUNCTIONPOINTER_H
-
-#include <string.h>
-#include <stdint.h>
-
-namespace mbed {
-
-/* If we had variaditic templates, this wouldn't be a problem, but until C++11 is enabled, we are stuck with multiple classes... */
-
-/** A class for storing and calling a pointer to a static or member function
- */
-template <typename R, typename A1>
-class FunctionPointerArg1{
-public:
-    /** Create a FunctionPointer, attaching a static function
-     *
-     *  @param function The static function to attach (default is none)
-     */
-    FunctionPointerArg1(R (*function)(A1) = 0) {
-        attach(function);
-    }
-
-    /** Create a FunctionPointer, attaching a member function
-     *
-     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
-     *  @param function The address of the member function to attach
-     */
-    template<typename T>
-    FunctionPointerArg1(T *object, R (T::*member)(A1)) {
-        attach(object, member);
-    }
-
-    /** Attach a static function
-     *
-     *  @param function The static function to attach (default is none)
-     */
-    void attach(R (*function)(A1)) {
-        _p.function = function;
-        _membercaller = 0;
-    }
-
-    /** Attach a member function
-     *
-     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
-     *  @param function The address of the member function to attach
-     */
-    template<typename T>
-    void attach(T *object, R (T::*member)(A1)) {
-        _p.object = static_cast<void*>(object);
-        *reinterpret_cast<R (T::**)(A1)>(_member) = member;
-        _membercaller = &FunctionPointerArg1::membercaller<T>;
-    }
-
-    /** Call the attached static or member function
-     */
-    R call(A1 a) {
-        if (_membercaller == 0 && _p.function) {
-           return _p.function(a);
-        } else if (_membercaller && _p.object) {
-           return _membercaller(_p.object, _member, a);
-        }
-        return (R)0;
-    }
-
-    /** Get registered static function
-     */
-    R(*get_function(A1))() {
-        return _membercaller ? (R(*)(A1))0 : (R(*)(A1))_p.function;
-    }
-
-#ifdef MBED_OPERATORS
-    R operator ()(A1 a) {
-        return call(a);
-    }
-    operator bool(void) const {
-        return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL;
-    }
-#endif
-private:
-    template<typename T>
-    static R membercaller(void *object, uintptr_t *member, A1 a) {
-        T* o = static_cast<T*>(object);
-        R (T::**m)(A1) = reinterpret_cast<R (T::**)(A1)>(member);
-        return (o->**m)(a);
-    }
-
-    union {
-        R (*function)(A1); // static function pointer
-        void *object;      // object this pointer
-    } _p;
-    uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller
-    R (*_membercaller)(void*, uintptr_t*, A1); // registered membercaller function to convert back and call _m.member on _object
-};
-
-/** A class for storing and calling a pointer to a static or member function (R ()(void))
- */
-template <typename R>
-class FunctionPointerArg1<R, void>{
-public:
-    /** Create a FunctionPointer, attaching a static function
-     *
-     *  @param function The static function to attach (default is none)
-     */
-    FunctionPointerArg1(R (*function)(void) = 0) {
-        attach(function);
-    }
-
-    /** Create a FunctionPointer, attaching a member function
-     *
-     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
-     *  @param function The address of the void member function to attach
-     */
-    template<typename T>
-    FunctionPointerArg1(T *object, R (T::*member)(void)) {
-        attach(object, member);
-    }
-
-    /** Attach a static function
-     *
-     *  @param function The void static function to attach (default is none)
-     */
-    void attach(R (*function)(void)) {
-        _p.function = function;
-        _membercaller = 0;
-    }
-
-    /** Attach a member function
-     *
-     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
-     *  @param function The address of the void member function to attach
-     */
-    template<typename T>
-    void attach(T *object, R (T::*member)(void)) {
-        _p.object = static_cast<void*>(object);
-        *reinterpret_cast<R (T::**)(void)>(_member) = member;
-        _membercaller = &FunctionPointerArg1::membercaller<T>;
-    }
-
-    /** Call the attached static or member function
-     */
-    R call(){
-        if (_membercaller == 0 && _p.function) {
-            return _p.function();
-        } else if (_membercaller && _p.object) {
-            return _membercaller(_p.object, _member);
-        }
-        return (R)0;
-    }
-
-    /** Get registered static function
-     */
-    R(*get_function())() {
-        return _membercaller ? (R(*)())0 : (R(*)())_p.function;
-    }
-
-#ifdef MBED_OPERATORS
-    R operator ()(void) {
-        return call();
-    }
-    operator bool(void) const {
-        return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL;
-    }
-#endif
-
-private:
-    template<typename T>
-    static R membercaller(void *object, uintptr_t *member) {
-        T* o = static_cast<T*>(object);
-        R (T::**m)(void) = reinterpret_cast<R (T::**)(void)>(member);
-        return (o->**m)();
-    }
-
-    union {
-        R (*function)(void); // static function pointer
-        void *object;        // object this pointer
-    } _p;
-    uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller
-    R (*_membercaller)(void*, uintptr_t*); // registered membercaller function to convert back and call _m.member on _object
-};
-
-typedef FunctionPointerArg1<void, void> FunctionPointer;
-typedef FunctionPointerArg1<void, int> event_callback_t;
-
-} // namespace mbed
-
-#endif

--- a/api/I2C.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,176 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_H
-#define MBED_I2C_H
-
-#include "platform.h"
-
-#if DEVICE_I2C
-
-#include "i2c_api.h"
-
-#if DEVICE_I2C_ASYNCH
-#include "CThunk.h"
-#include "dma_api.h"
-#include "FunctionPointer.h"
-#endif
-
-namespace mbed {
-
-/** An I2C Master, used for communicating with I2C slave devices
- *
- * Example:
- * @code
- * // Read from I2C slave at address 0x62
- *
- * #include "mbed.h"
- *
- * I2C i2c(p28, p27);
- *
- * int main() {
- *     int address = 0x62;
- *     char data[2];
- *     i2c.read(address, data, 2);
- * }
- * @endcode
- */
-class I2C {
-
-public:
-    enum RxStatus {
-        NoData,
-        MasterGeneralCall,
-        MasterWrite,
-        MasterRead
-    };
-
-    enum Acknowledge {
-        NoACK = 0,
-        ACK   = 1
-    };
-
-    /** Create an I2C Master interface, connected to the specified pins
-     *
-     *  @param sda I2C data line pin
-     *  @param scl I2C clock line pin
-     */
-    I2C(PinName sda, PinName scl);
-
-    /** Set the frequency of the I2C interface
-     *
-     *  @param hz The bus frequency in hertz
-     */
-    void frequency(int hz);
-
-    /** Read from an I2C slave
-     *
-     * Performs a complete read transaction. The bottom bit of
-     * the address is forced to 1 to indicate a read.
-     *
-     *  @param address 8-bit I2C slave address [ addr | 1 ]
-     *  @param data Pointer to the byte-array to read data in to
-     *  @param length Number of bytes to read
-     *  @param repeated Repeated start, true - don't send stop at end
-     *
-     *  @returns
-     *       0 on success (ack),
-     *   non-0 on failure (nack)
-     */
-    int read(int address, char *data, int length, bool repeated = false);
-
-    /** Read a single byte from the I2C bus
-     *
-     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
-     *
-     *  @returns
-     *    the byte read
-     */
-    int read(int ack);
-
-    /** Write to an I2C slave
-     *
-     * Performs a complete write transaction. The bottom bit of
-     * the address is forced to 0 to indicate a write.
-     *
-     *  @param address 8-bit I2C slave address [ addr | 0 ]
-     *  @param data Pointer to the byte-array data to send
-     *  @param length Number of bytes to send
-     *  @param repeated Repeated start, true - do not send stop at end
-     *
-     *  @returns
-     *       0 on success (ack),
-     *   non-0 on failure (nack)
-     */
-    int write(int address, const char *data, int length, bool repeated = false);
-
-    /** Write single byte out on the I2C bus
-     *
-     *  @param data data to write out on bus
-     *
-     *  @returns
-     *    '1' if an ACK was received,
-     *    '0' otherwise
-     */
-    int write(int data);
-
-    /** Creates a start condition on the I2C bus
-     */
-
-    void start(void);
-
-    /** Creates a stop condition on the I2C bus
-     */
-    void stop(void);
-
-#if DEVICE_I2C_ASYNCH
-
-    /** Start non-blocking I2C transfer.
-     *
-     * @param address   8/10 bit I2c slave address
-     * @param tx_buffer The TX buffer with data to be transfered
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data
-     * @param rx_length The length of RX buffer in bytes
-     * @param event     The logical OR of events to modify
-     * @param callback  The event callback function
-     * @param repeated Repeated start, true - do not send stop at end
-     * @return Zero if the transfer has started, or -1 if I2C peripheral is busy
-     */
-    int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
-
-    /** Abort the on-going I2C transfer
-     */
-    void abort_transfer();
-protected:
-    void irq_handler_asynch(void);
-    event_callback_t _callback;
-    CThunk<I2C> _irq;
-    DMAUsage _usage;
-#endif
-
-protected:
-    void aquire();
-
-    i2c_t _i2c;
-    static I2C  *_owner;
-    int         _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/I2CSlave.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,154 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_SLAVE_H
-#define MBED_I2C_SLAVE_H
-
-#include "platform.h"
-
-#if DEVICE_I2CSLAVE
-
-#include "i2c_api.h"
-
-namespace mbed {
-
-/** An I2C Slave, used for communicating with an I2C Master device
- *
- * Example:
- * @code
- * // Simple I2C responder
- * #include <mbed.h>
- *
- * I2CSlave slave(p9, p10);
- *
- * int main() {
- *     char buf[10];
- *     char msg[] = "Slave!";
- *
- *     slave.address(0xA0);
- *     while (1) {
- *         int i = slave.receive();
- *         switch (i) {
- *             case I2CSlave::ReadAddressed:
- *                 slave.write(msg, strlen(msg) + 1); // Includes null char
- *                 break;
- *             case I2CSlave::WriteGeneral:
- *                 slave.read(buf, 10);
- *                 printf("Read G: %s\n", buf);
- *                 break;
- *             case I2CSlave::WriteAddressed:
- *                 slave.read(buf, 10);
- *                 printf("Read A: %s\n", buf);
- *                 break;
- *         }
- *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
- *     }
- * }
- * @endcode
- */
-class I2CSlave {
-
-public:
-    enum RxStatus {
-        NoData         = 0,
-        ReadAddressed  = 1,
-        WriteGeneral   = 2,
-        WriteAddressed = 3
-    };
-
-    /** Create an I2C Slave interface, connected to the specified pins.
-     *
-     *  @param sda I2C data line pin
-     *  @param scl I2C clock line pin
-     */
-    I2CSlave(PinName sda, PinName scl);
-
-    /** Set the frequency of the I2C interface
-     *
-     *  @param hz The bus frequency in hertz
-     */
-    void frequency(int hz);
-
-    /** Checks to see if this I2C Slave has been addressed.
-     *
-     *  @returns
-     *  A status indicating if the device has been addressed, and how
-     *  - NoData            - the slave has not been addressed
-     *  - ReadAddressed     - the master has requested a read from this slave
-     *  - WriteAddressed    - the master is writing to this slave
-     *  - WriteGeneral      - the master is writing to all slave
-     */
-    int receive(void);
-
-    /** Read from an I2C master.
-     *
-     *  @param data pointer to the byte array to read data in to
-     *  @param length maximum number of bytes to read
-     *
-     *  @returns
-     *       0 on success,
-     *   non-0 otherwise
-     */
-    int read(char *data, int length);
-
-    /** Read a single byte from an I2C master.
-     *
-     *  @returns
-     *    the byte read
-     */
-    int read(void);
-
-    /** Write to an I2C master.
-     *
-     *  @param data pointer to the byte array to be transmitted
-     *  @param length the number of bytes to transmite
-     *
-     *  @returns
-     *       0 on success,
-     *   non-0 otherwise
-     */
-    int write(const char *data, int length);
-
-    /** Write a single byte to an I2C master.
-     *
-     *  @data the byte to write
-     *
-     *  @returns
-     *    '1' if an ACK was received,
-     *    '0' otherwise
-     */
-    int write(int data);
-
-    /** Sets the I2C slave address.
-     *
-     *  @param address The address to set for the slave (ignoring the least
-     *  signifcant bit). If set to 0, the slave will only respond to the
-     *  general call address.
-     */
-    void address(int address);
-
-    /** Reset the I2C slave back into the known ready receiving state.
-     */
-    void stop(void);
-
-protected:
-    i2c_t _i2c;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/InterruptIn.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,135 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERRUPTIN_H
-#define MBED_INTERRUPTIN_H
-
-#include "platform.h"
-
-#if DEVICE_INTERRUPTIN
-
-#include "gpio_api.h"
-#include "gpio_irq_api.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** A digital interrupt input, used to call a function on a rising or falling edge
- *
- * Example:
- * @code
- * // Flash an LED while waiting for events
- *
- * #include "mbed.h"
- *
- * InterruptIn event(p16);
- * DigitalOut led(LED1);
- *
- * void trigger() {
- *     printf("triggered!\n");
- * }
- *
- * int main() {
- *     event.rise(&trigger);
- *     while(1) {
- *         led = !led;
- *         wait(0.25);
- *     }
- * }
- * @endcode
- */
-class InterruptIn {
-
-public:
-
-    /** Create an InterruptIn connected to the specified pin
-     *
-     *  @param pin InterruptIn pin to connect to
-     *  @param name (optional) A string to identify the object
-     */
-    InterruptIn(PinName pin);
-    virtual ~InterruptIn();
-
-     int read();
-#ifdef MBED_OPERATORS
-    operator int();
-
-#endif
-
-    /** Attach a function to call when a rising edge occurs on the input
-     *
-     *  @param fptr A pointer to a void function, or 0 to set as none
-     */
-    void rise(void (*fptr)(void));
-
-    /** Attach a member function to call when a rising edge occurs on the input
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     */
-    template<typename T>
-    void rise(T* tptr, void (T::*mptr)(void)) {
-        _rise.attach(tptr, mptr);
-        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
-    }
-
-    /** Attach a function to call when a falling edge occurs on the input
-     *
-     *  @param fptr A pointer to a void function, or 0 to set as none
-     */
-    void fall(void (*fptr)(void));
-
-    /** Attach a member function to call when a falling edge occurs on the input
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     */
-    template<typename T>
-    void fall(T* tptr, void (T::*mptr)(void)) {
-        _fall.attach(tptr, mptr);
-        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone
-     */
-    void mode(PinMode pull);
-
-    /** Enable IRQ. This method depends on hw implementation, might enable one
-     *  port interrupts. For further information, check gpio_irq_enable().
-     */
-    void enable_irq();
-
-    /** Disable IRQ. This method depends on hw implementation, might disable one
-     *  port interrupts. For further information, check gpio_irq_disable().
-     */
-    void disable_irq();
-
-    static void _irq_handler(uint32_t id, gpio_irq_event event);
-
-protected:
-    gpio_t gpio;
-    gpio_irq_t gpio_irq;
-
-    FunctionPointer _rise;
-    FunctionPointer _fall;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/InterruptManager.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,143 +0,0 @@
-#ifndef MBED_INTERRUPTMANAGER_H
-#define MBED_INTERRUPTMANAGER_H
-
-#include "cmsis.h"
-#include "CallChain.h"
-#include <string.h>
-
-namespace mbed {
-
-/** Use this singleton if you need to chain interrupt handlers.
- *
- * Example (for LPC1768):
- * @code
- * #include "InterruptManager.h"
- * #include "mbed.h"
- *
- * Ticker flipper;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * void flip(void) {
- *     led1 = !led1;
- * }
- *
- * void handler(void) {
- *     led2 = !led1;
- * }
- *
- * int main() {
- *     led1 = led2 = 0;
- *     flipper.attach(&flip, 1.0);
- *     InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
- * }
- * @endcode
- */
-class InterruptManager {
-public:
-    /** Return the only instance of this class
-     */
-    static InterruptManager* get();
-
-    /** Destroy the current instance of the interrupt manager
-     */
-    static void destroy();
-
-    /** Add a handler for an interrupt at the end of the handler list
-     *
-     *  @param function the handler to add
-     *  @param irq interrupt number
-     *
-     *  @returns
-     *  The function object created for 'function'
-     */
-    pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
-        return add_common(function, irq);
-    }
-
-    /** Add a handler for an interrupt at the beginning of the handler list
-     *
-     *  @param function the handler to add
-     *  @param irq interrupt number
-     *
-     *  @returns
-     *  The function object created for 'function'
-     */
-    pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
-        return add_common(function, irq, true);
-    }
-
-    /** Add a handler for an interrupt at the end of the handler list
-     *
-     *  @param tptr pointer to the object that has the handler function
-     *  @param mptr pointer to the actual handler function
-     *  @param irq interrupt number
-     *
-     *  @returns
-     *  The function object created for 'tptr' and 'mptr'
-     */
-    template<typename T>
-    pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
-        return add_common(tptr, mptr, irq);
-    }
-
-    /** Add a handler for an interrupt at the beginning of the handler list
-     *
-     *  @param tptr pointer to the object that has the handler function
-     *  @param mptr pointer to the actual handler function
-     *  @param irq interrupt number
-     *
-     *  @returns
-     *  The function object created for 'tptr' and 'mptr'
-     */
-    template<typename T>
-    pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
-        return add_common(tptr, mptr, irq, true);
-    }
-
-    /** Remove a handler from an interrupt
-     *
-     *  @param handler the function object for the handler to remove
-     *  @param irq the interrupt number
-     *
-     *  @returns
-     *  true if the handler was found and removed, false otherwise
-     */
-    bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
-
-private:
-    InterruptManager();
-    ~InterruptManager();
-
-    // We declare the copy contructor and the assignment operator, but we don't
-    // implement them. This way, if someone tries to copy/assign our instance,
-    // he will get an error at compile time.
-    InterruptManager(const InterruptManager&);
-    InterruptManager& operator =(const InterruptManager&);
-
-    template<typename T>
-    pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
-        int irq_pos = get_irq_index(irq);
-        bool change = must_replace_vector(irq);
-
-        pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
-        if (change)
-            NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
-        return pf;
-    }
-
-    pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
-    bool must_replace_vector(IRQn_Type irq);
-    int get_irq_index(IRQn_Type irq);
-    void irq_helper();
-    void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
-    static void static_irq_helper();
-
-    CallChain* _chains[NVIC_NUM_VECTORS];
-    static InterruptManager* _instance;
-};
-
-} // namespace mbed
-
-#endif
-

--- a/api/LocalFileSystem.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOCALFILESYSTEM_H
-#define MBED_LOCALFILESYSTEM_H
-
-#include "platform.h"
-
-#if DEVICE_LOCALFILESYSTEM
-
-#include "FileSystemLike.h"
-
-namespace mbed {
-
-FILEHANDLE local_file_open(const char* name, int flags);
-
-class LocalFileHandle : public FileHandle {
-
-public:
-    LocalFileHandle(FILEHANDLE fh);
-
-    virtual int close();
-
-    virtual ssize_t write(const void *buffer, size_t length);
-
-    virtual ssize_t read(void *buffer, size_t length);
-
-    virtual int isatty();
-
-    virtual off_t lseek(off_t position, int whence);
-
-    virtual int fsync();
-
-    virtual off_t flen();
-
-protected:
-    FILEHANDLE _fh;
-    int pos;
-};
-
-/** A filesystem for accessing the local mbed Microcontroller USB disk drive
- *
- *  This allows programs to read and write files on the same disk drive that is used to program the
- *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
- *  read and write files.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
- *
- * int main() {
- *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
- *     fprintf(fp, "Hello World!");
- *     fclose(fp);
- *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
- *
- *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
- *     struct dirent *p;
- *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
- *       printf("%s\n", p->d_name);              // to stdout.
- *     }
- *     closedir(d);
- * }
- * @endcode
- *
- * @note
- *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
- *  on the Host computer. This means it is no longer accessible from the Host Computer.
- *
- *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
- *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
- */
-class LocalFileSystem : public FileSystemLike {
-
-public:
-    LocalFileSystem(const char* n) : FileSystemLike(n) {
-
-    }
-
-    virtual FileHandle *open(const char* name, int flags);
-    virtual int remove(const char *filename);
-    virtual DirHandle *opendir(const char *name);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/LowPowerTicker.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTICKER_H
-#define MBED_LOWPOWERTICKER_H
-
-#include "platform.h"
-#include "Ticker.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "lp_ticker_api.h"
-
-namespace mbed {
-
-/** Low Power Ticker
- */
-class LowPowerTicker : public Ticker {
-
-public:
-    LowPowerTicker() : Ticker(get_lp_ticker_data()) {
-    }
-
-    virtual ~LowPowerTicker() {
-    }
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/LowPowerTimeout.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTIMEOUT_H
-#define MBED_LOWPOWERTIMEOUT_H
-
-#include "platform.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "lp_ticker_api.h"
-#include "LowPowerTicker.h"
-
-namespace mbed {
-
-/** Low Power Timout
- */
-class LowPowerTimeout : public LowPowerTicker {
-
-private:
-    virtual void handler(void) {
-        _function.call();
-    }
-};
-
-}
-
-#endif
-
-#endif

--- a/api/LowPowerTimer.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LOWPOWERTIMER_H
-#define MBED_LOWPOWERTIMER_H
-
-#include "platform.h"
-#include "Timer.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "lp_ticker_api.h"
-
-namespace mbed {
-
-/** Low power timer
- */
-class LowPowerTimer : public Timer {
-
-public:
-    LowPowerTimer() : Timer(get_lp_ticker_data()) {
-    }
-
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/PortIn.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTIN_H
-#define MBED_PORTIN_H
-
-#include "platform.h"
-
-#if DEVICE_PORTIN
-
-#include "port_api.h"
-
-namespace mbed {
-
-/** A multiple pin digital input
- *
- *  Example:
- * @code
- * // Switch on an LED if any of mbed pins 21-26 is high
- *
- * #include "mbed.h"
- *
- * PortIn     p(Port2, 0x0000003F);   // p21-p26
- * DigitalOut ind(LED4);
- *
- * int main() {
- *     while(1) {
- *         int pins = p.read();
- *         if(pins) {
- *             ind = 1;
- *         } else {
- *             ind = 0;
- *         }
- *     }
- * }
- * @endcode
- */
-class PortIn {
-public:
-
-    /** Create an PortIn, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-        */
-    PortIn(PortName port, int mask = 0xFFFFFFFF) {
-        port_init(&_port, port, mask, PIN_INPUT);
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated port pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode mode) {
-        port_mode(&_port, mode);
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/PortInOut.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTINOUT_H
-#define MBED_PORTINOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PORTINOUT
-
-#include "port_api.h"
-
-namespace mbed {
-
-/** A multiple pin digital in/out used to set/read multiple bi-directional pins
- */
-class PortInOut {
-public:
-
-    /** Create an PortInOut, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-     */
-    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
-        port_init(&_port, port, mask, PIN_INPUT);
-    }
-
-    /** Write the value to the output port
-     *
-     *  @param value An integer specifying a bit to write for every corresponding port pin
-     */
-    void write(int value) {
-        port_write(&_port, value);
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated port pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** Set as an output
-     */
-    void output() {
-        port_dir(&_port, PIN_OUTPUT);
-    }
-
-    /** Set as an input
-     */
-    void input() {
-        port_dir(&_port, PIN_INPUT);
-    }
-
-    /** Set the input pin mode
-     *
-     *  @param mode PullUp, PullDown, PullNone, OpenDrain
-     */
-    void mode(PinMode mode) {
-        port_mode(&_port, mode);
-    }
-
-    /** A shorthand for write()
-     */
-    PortInOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    PortInOut& operator= (PortInOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/PortOut.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,104 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTOUT_H
-#define MBED_PORTOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PORTOUT
-
-#include "port_api.h"
-
-namespace mbed {
-/** A multiple pin digital out
- *
- * Example:
- * @code
- * // Toggle all four LEDs
- *
- * #include "mbed.h"
- *
- * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
- * #define LED_MASK 0x00B40000
- *
- * PortOut ledport(Port1, LED_MASK);
- *
- * int main() {
- *     while(1) {
- *         ledport = LED_MASK;
- *         wait(1);
- *         ledport = 0;
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-class PortOut {
-public:
-
-    /** Create an PortOut, connected to the specified port
-     *
-     *  @param port Port to connect to (Port0-Port5)
-     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
-     */
-    PortOut(PortName port, int mask = 0xFFFFFFFF) {
-        port_init(&_port, port, mask, PIN_OUTPUT);
-    }
-
-    /** Write the value to the output port
-     *
-     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
-     */
-    void write(int value) {
-        port_write(&_port, value);
-    }
-
-    /** Read the value currently output on the port
-     *
-     *  @returns
-     *    An integer with each bit corresponding to associated PortOut pin setting
-     */
-    int read() {
-        return port_read(&_port);
-    }
-
-    /** A shorthand for write()
-     */
-    PortOut& operator= (int value) {
-        write(value);
-        return *this;
-    }
-
-    PortOut& operator= (PortOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** A shorthand for read()
-     */
-    operator int() {
-        return read();
-    }
-
-private:
-    port_t _port;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/PwmOut.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,158 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_H
-#define MBED_PWMOUT_H
-
-#include "platform.h"
-
-#if DEVICE_PWMOUT
-#include "pwmout_api.h"
-
-namespace mbed {
-
-/** A pulse-width modulation digital output
- *
- * Example
- * @code
- * // Fade a led on.
- * #include "mbed.h"
- *
- * PwmOut led(LED1);
- *
- * int main() {
- *     while(1) {
- *         led = led + 0.01;
- *         wait(0.2);
- *         if(led == 1.0) {
- *             led = 0;
- *         }
- *     }
- * }
- * @endcode
- *
- * @note
- *  On the LPC1768 and LPC2368, the PWMs all share the same
- *  period - if you change the period for one, you change it for all.
- *  Although routines that change the period maintain the duty cycle
- *  for its PWM, all other PWMs will require their duty cycle to be
- *  refreshed.
- */
-class PwmOut {
-
-public:
-
-    /** Create a PwmOut connected to the specified pin
-     *
-     *  @param pin PwmOut pin to connect to
-     */
-    PwmOut(PinName pin) {
-        pwmout_init(&_pwm, pin);
-    }
-
-    /** Set the ouput duty-cycle, specified as a percentage (float)
-     *
-     *  @param value A floating-point value representing the output duty-cycle,
-     *    specified as a percentage. The value should lie between
-     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
-     *    Values outside this range will be saturated to 0.0f or 1.0f.
-     */
-    void write(float value) {
-        pwmout_write(&_pwm, value);
-    }
-
-    /** Return the current output duty-cycle setting, measured as a percentage (float)
-     *
-     *  @returns
-     *    A floating-point value representing the current duty-cycle being output on the pin,
-     *    measured as a percentage. The returned value will lie between
-     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
-     *
-     *  @note
-     *  This value may not match exactly the value set by a previous <write>.
-     */
-    float read() {
-        return pwmout_read(&_pwm);
-    }
-
-    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
-     *
-     *  @note
-     *   The resolution is currently in microseconds; periods smaller than this
-     *   will be set to zero.
-     */
-    void period(float seconds) {
-        pwmout_period(&_pwm, seconds);
-    }
-
-    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
-     */
-    void period_ms(int ms) {
-        pwmout_period_ms(&_pwm, ms);
-    }
-
-    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
-     */
-    void period_us(int us) {
-        pwmout_period_us(&_pwm, us);
-    }
-
-    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
-     */
-    void pulsewidth(float seconds) {
-        pwmout_pulsewidth(&_pwm, seconds);
-    }
-
-    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
-     */
-    void pulsewidth_ms(int ms) {
-        pwmout_pulsewidth_ms(&_pwm, ms);
-    }
-
-    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
-     */
-    void pulsewidth_us(int us) {
-        pwmout_pulsewidth_us(&_pwm, us);
-    }
-
-#ifdef MBED_OPERATORS
-    /** A operator shorthand for write()
-     */
-    PwmOut& operator= (float value) {
-        write(value);
-        return *this;
-    }
-
-    PwmOut& operator= (PwmOut& rhs) {
-        write(rhs.read());
-        return *this;
-    }
-
-    /** An operator shorthand for read()
-     */
-    operator float() {
-        return read();
-    }
-#endif
-
-protected:
-    pwmout_t _pwm;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/RawSerial.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,90 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_RAW_SERIAL_H
-#define MBED_RAW_SERIAL_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "SerialBase.h"
-#include "serial_api.h"
-
-namespace mbed {
-
-/** A serial port (UART) for communication with other serial devices
- * This is a variation of the Serial class that doesn't use streams,
- * thus making it safe to use in interrupt handlers with the RTOS.
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * Example:
- * @code
- * // Send a char to the PC
- *
- * #include "mbed.h"
- *
- * RawSerial pc(USBTX, USBRX);
- *
- * int main() {
- *     pc.putc('A');
- * }
- * @endcode
- */
-class RawSerial: public SerialBase {
-
-public:
-    /** Create a RawSerial port, connected to the specified transmit and receive pins
-     *
-     *  @param tx Transmit pin
-     *  @param rx Receive pin
-     *
-     *  @note
-     *    Either tx or rx may be specified as NC if unused
-     */
-    RawSerial(PinName tx, PinName rx);
-
-    /** Write a char to the serial port
-     *
-     * @param c The char to write
-     *
-     * @returns The written char or -1 if an error occured
-     */
-    int putc(int c);
-
-    /** Read a char from the serial port
-     *
-     * @returns The char read from the serial port
-     */
-    int getc();
-
-    /** Write a string to the serial port
-     *
-     * @param str The string to write
-     *
-     * @returns 0 if the write succeeds, EOF for error
-     */
-    int puts(const char *str);
-
-    int printf(const char *format, ...);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/SPI.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,245 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_H
-#define MBED_SPI_H
-
-#include "platform.h"
-
-#if DEVICE_SPI
-
-#include "spi_api.h"
-
-#if DEVICE_SPI_ASYNCH
-#include "CThunk.h"
-#include "dma_api.h"
-#include "CircularBuffer.h"
-#include "FunctionPointer.h"
-#include "Transaction.h"
-#endif
-
-namespace mbed {
-
-/** A SPI Master, used for communicating with SPI slave devices
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
- *
- * Most SPI devices will also require Chip Select and Reset signals. These
- * can be controlled using <DigitalOut> pins
- *
- * Example:
- * @code
- * // Send a byte to a SPI slave, and record the response
- *
- * #include "mbed.h"
- *
- * // hardware ssel (where applicable)
- * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
- *
- * // software ssel
- * SPI device(p5, p6, p7); // mosi, miso, sclk
- * DigitalOut cs(p8); // ssel
- *
- * int main() {
- *     // hardware ssel (where applicable)
- *     //int response = device.write(0xFF);
- *
- *     // software ssel
- *     cs = 0;
- *     int response = device.write(0xFF);
- *     cs = 1;
- * }
- * @endcode
- */
-class SPI {
-
-public:
-
-    /** Create a SPI master connected to the specified pins
-     *
-     *  mosi or miso can be specfied as NC if not used
-     *
-     *  @param mosi SPI Master Out, Slave In pin
-     *  @param miso SPI Master In, Slave Out pin
-     *  @param sclk SPI Clock pin
-     *  @param ssel SPI chip select pin
-     */
-    SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
-
-    /** Configure the data transmission format
-     *
-     *  @param bits Number of bits per SPI frame (4 - 16)
-     *  @param mode Clock polarity and phase mode (0 - 3)
-     *
-     * @code
-     * mode | POL PHA
-     * -----+--------
-     *   0  |  0   0
-     *   1  |  0   1
-     *   2  |  1   0
-     *   3  |  1   1
-     * @endcode
-     */
-    void format(int bits, int mode = 0);
-
-    /** Set the spi bus clock frequency
-     *
-     *  @param hz SCLK frequency in hz (default = 1MHz)
-     */
-    void frequency(int hz = 1000000);
-
-    /** Write to the SPI Slave and return the response
-     *
-     *  @param value Data to be sent to the SPI slave
-     *
-     *  @returns
-     *    Response from the SPI slave
-    */
-    virtual int write(int value);
-
-#if DEVICE_SPI_ASYNCH
-
-    /** Start non-blocking SPI transfer using 8bit buffers.
-     *
-     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
-     *                  the default SPI value is sent
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
-     *                  received data are ignored
-     * @param rx_length The length of RX buffer in bytes
-     * @param callback  The event callback function
-     * @param event     The logical OR of events to modify. Look at spi hal header file for SPI events.
-     * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
-     */
-    template<typename Type>
-    int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
-        if (spi_active(&_spi)) {
-            return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
-        }
-        start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
-        return 0;
-    }
-
-    /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
-     */
-    void abort_transfer();
-
-    /** Clear the transaction buffer
-     */
-    void clear_transfer_buffer();
-
-    /** Clear the transaction buffer and abort on-going transfer.
-     */
-    void abort_all_transfers();
-
-    /** Configure DMA usage suggestion for non-blocking transfers
-     *
-     *  @param usage The usage DMA hint for peripheral
-     *  @return Zero if the usage was set, -1 if a transaction is on-going
-    */
-    int set_dma_usage(DMAUsage usage);
-
-protected:
-    /** SPI IRQ handler
-     *
-    */
-    void irq_handler_asynch(void);
-
-    /** Common transfer method
-     *
-     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
-     *                  the default SPI value is sent
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
-     *                  received data are ignored
-     * @param rx_length The length of RX buffer in bytes
-     * @param bit_width The buffers element width
-     * @param callback  The event callback function
-     * @param event     The logical OR of events to modify
-     * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
-    */
-    int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
-
-    /**
-     *
-     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
-     *                  the default SPI value is sent
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
-     *                  received data are ignored
-     * @param rx_length The length of RX buffer in bytes
-     * @param bit_width The buffers element width
-     * @param callback  The event callback function
-     * @param event     The logical OR of events to modify
-     * @return Zero if a transfer was added to the queue, or -1 if the queue is full
-    */
-    int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
-
-    /** Configures a callback, spi peripheral and initiate a new transfer
-     *
-     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
-     *                  the default SPI value is sent
-     * @param tx_length The length of TX buffer in bytes
-     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
-     *                  received data are ignored
-     * @param rx_length The length of RX buffer in bytes
-     * @param bit_width The buffers element width
-     * @param callback  The event callback function
-     * @param event     The logical OR of events to modify
-    */
-    void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
-
-#if TRANSACTION_QUEUE_SIZE_SPI
-
-    /** Start a new transaction
-     *
-     *  @param data Transaction data
-    */
-    void start_transaction(transaction_t *data);
-
-    /** Dequeue a transaction
-     *
-    */
-    void dequeue_transaction();
-    static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
-#endif
-
-#endif
-
-public:
-    virtual ~SPI() {
-    }
-
-protected:
-    spi_t _spi;
-
-#if DEVICE_SPI_ASYNCH
-    CThunk<SPI> _irq;
-    event_callback_t _callback;
-    DMAUsage _usage;
-#endif
-
-    void aquire(void);
-    static SPI *_owner;
-    int _bits;
-    int _mode;
-    int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/SPISlave.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,122 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPISLAVE_H
-#define MBED_SPISLAVE_H
-
-#include "platform.h"
-
-#if DEVICE_SPISLAVE
-
-#include "spi_api.h"
-
-namespace mbed {
-
-/** A SPI slave, used for communicating with a SPI Master device
- *
- * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
- *
- * Example:
- * @code
- * // Reply to a SPI master as slave
- *
- * #include "mbed.h"
- *
- * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
- *
- * int main() {
- *     device.reply(0x00);              // Prime SPI with first reply
- *     while(1) {
- *         if(device.receive()) {
- *             int v = device.read();   // Read byte from master
- *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
- *             device.reply(v);         // Make this the next reply
- *         }
- *     }
- * }
- * @endcode
- */
-class SPISlave {
-
-public:
-
-    /** Create a SPI slave connected to the specified pins
-     *
-     *  mosi or miso can be specfied as NC if not used
-     *
-     *  @param mosi SPI Master Out, Slave In pin
-     *  @param miso SPI Master In, Slave Out pin
-     *  @param sclk SPI Clock pin
-     *  @param ssel SPI chip select pin
-     */
-    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
-
-    /** Configure the data transmission format
-     *
-     *  @param bits Number of bits per SPI frame (4 - 16)
-     *  @param mode Clock polarity and phase mode (0 - 3)
-     *
-     * @code
-     * mode | POL PHA
-     * -----+--------
-     *   0  |  0   0
-     *   1  |  0   1
-     *   2  |  1   0
-     *   3  |  1   1
-     * @endcode
-     */
-    void format(int bits, int mode = 0);
-
-    /** Set the spi bus clock frequency
-     *
-     *  @param hz SCLK frequency in hz (default = 1MHz)
-     */
-    void frequency(int hz = 1000000);
-
-    /** Polls the SPI to see if data has been received
-     *
-     *  @returns
-     *    0 if no data,
-     *    1 otherwise
-     */
-    int receive(void);
-
-    /** Retrieve  data from receive buffer as slave
-     *
-     *  @returns
-     *    the data in the receive buffer
-     */
-    int read(void);
-
-    /** Fill the transmission buffer with the value to be written out
-     *  as slave on the next received message from the master.
-     *
-     *  @param value the data to be transmitted next
-     */
-    void reply(int value);
-
-protected:
-    spi_t _spi;
-
-    int _bits;
-    int _mode;
-    int _hz;
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/Serial.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,74 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_H
-#define MBED_SERIAL_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "Stream.h"
-#include "SerialBase.h"
-#include "serial_api.h"
-
-namespace mbed {
-
-/** A serial port (UART) for communication with other serial devices
- *
- * Can be used for Full Duplex communication, or Simplex by specifying
- * one pin as NC (Not Connected)
- *
- * Example:
- * @code
- * // Print "Hello World" to the PC
- *
- * #include "mbed.h"
- *
- * Serial pc(USBTX, USBRX);
- *
- * int main() {
- *     pc.printf("Hello World\n");
- * }
- * @endcode
- */
-class Serial : public SerialBase, public Stream {
-
-public:
-#if DEVICE_SERIAL_ASYNCH
-    using SerialBase::read;
-    using SerialBase::write;
-#endif
-
-    /** Create a Serial port, connected to the specified transmit and receive pins
-     *
-     *  @param tx Transmit pin
-     *  @param rx Receive pin
-     *
-     *  @note
-     *    Either tx or rx may be specified as NC if unused
-     */
-    Serial(PinName tx, PinName rx, const char *name=NULL);
-
-protected:
-    virtual int _getc();
-    virtual int _putc(int c);
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/SerialBase.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,223 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIALBASE_H
-#define MBED_SERIALBASE_H
-
-#include "platform.h"
-
-#if DEVICE_SERIAL
-
-#include "Stream.h"
-#include "FunctionPointer.h"
-#include "serial_api.h"
-
-#if DEVICE_SERIAL_ASYNCH
-#include "CThunk.h"
-#include "dma_api.h"
-#endif
-
-namespace mbed {
-
-/** A base class for serial port implementations
- * Can't be instantiated directly (use Serial or RawSerial)
- */
-class SerialBase {
-
-public:
-    /** Set the baud rate of the serial port
-     *
-     *  @param baudrate The baudrate of the serial port (default = 9600).
-     */
-    void baud(int baudrate);
-
-    enum Parity {
-        None = 0,
-        Odd,
-        Even,
-        Forced1,
-        Forced0
-    };
-
-    enum IrqType {
-        RxIrq = 0,
-        TxIrq
-    };
-
-    enum Flow {
-        Disabled = 0,
-        RTS,
-        CTS,
-        RTSCTS
-    };
-
-    /** Set the transmission format used by the serial port
-     *
-     *  @param bits The number of bits in a word (5-8; default = 8)
-     *  @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
-     *  @param stop The number of stop bits (1 or 2; default = 1)
-     */
-    void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
-
-    /** Determine if there is a character available to read
-     *
-     *  @returns
-     *    1 if there is a character available to read,
-     *    0 otherwise
-     */
-    int readable();
-
-    /** Determine if there is space available to write a character
-     *
-     *  @returns
-     *    1 if there is space to write a character,
-     *    0 otherwise
-     */
-    int writeable();
-
-    /** Attach a function to call whenever a serial interrupt is generated
-     *
-     *  @param fptr A pointer to a void function, or 0 to set as none
-     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
-     */
-    void attach(void (*fptr)(void), IrqType type=RxIrq);
-
-    /** Attach a member function to call whenever a serial interrupt is generated
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
-     */
-    template<typename T>
-    void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
-        if((mptr != NULL) && (tptr != NULL)) {
-            _irq[type].attach(tptr, mptr);
-            serial_irq_set(&_serial, (SerialIrq)type, 1);
-        } else {
-            serial_irq_set(&_serial, (SerialIrq)type, 0);
-        }
-    }
-
-    /** Generate a break condition on the serial line
-     */
-    void send_break();
-
-#if DEVICE_SERIAL_FC
-    /** Set the flow control type on the serial port
-     *
-     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
-     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
-     *  @param flow2 the second flow control pin (CTS for RTSCTS)
-     */
-    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
-#endif
-
-    static void _irq_handler(uint32_t id, SerialIrq irq_type);
-
-#if DEVICE_SERIAL_ASYNCH
-
-    /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
-     *
-     *  @param buffer   The buffer where received data will be stored
-     *  @param length   The buffer length in bytes
-     *  @param callback The event callback function
-     *  @param event    The logical OR of TX events
-     */
-    int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
-
-    /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
-     *
-     *  @param buffer   The buffer where received data will be stored
-     *  @param length   The buffer length in bytes
-     *  @param callback The event callback function
-     *  @param event    The logical OR of TX events
-     */
-    int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
-
-    /** Abort the on-going write transfer
-     */
-    void abort_write();
-
-    /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
-     *
-     *  @param buffer     The buffer where received data will be stored
-     *  @param length     The buffer length in bytes
-     *  @param callback   The event callback function
-     *  @param event      The logical OR of RX events
-     *  @param char_match The matching character
-     */
-    int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
-
-    /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
-     *
-     *  @param buffer     The buffer where received data will be stored
-     *  @param length     The buffer length in bytes
-     *  @param callback   The event callback function
-     *  @param event      The logical OR of RX events
-     *  @param char_match The matching character
-     */
-    int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
-
-    /** Abort the on-going read transfer
-     */
-    void abort_read();
-
-    /** Configure DMA usage suggestion for non-blocking TX transfers
-     *
-     *  @param usage The usage DMA hint for peripheral
-     *  @return Zero if the usage was set, -1 if a transaction is on-going
-     */
-    int set_dma_usage_tx(DMAUsage usage);
-
-    /** Configure DMA usage suggestion for non-blocking RX transfers
-     *
-     *  @param usage The usage DMA hint for peripheral
-     *  @return Zero if the usage was set, -1 if a transaction is on-going
-     */
-    int set_dma_usage_rx(DMAUsage usage);
-
-protected:
-    void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match);
-    void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event);
-    void interrupt_handler_asynch(void);
-#endif
-
-protected:
-    SerialBase(PinName tx, PinName rx);
-    virtual ~SerialBase() {
-    }
-
-    int _base_getc();
-    int _base_putc(int c);
-
-#if DEVICE_SERIAL_ASYNCH
-    CThunk<SerialBase> _thunk_irq;
-    event_callback_t _tx_callback;
-    event_callback_t _rx_callback;
-    DMAUsage _tx_usage;
-    DMAUsage _rx_usage;
-#endif
-
-    serial_t        _serial;
-    FunctionPointer _irq[2];
-    int             _baud;
-
-};
-
-} // namespace mbed
-
-#endif
-
-#endif

--- a/api/Stream.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,65 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_STREAM_H
-#define MBED_STREAM_H
-
-#include "platform.h"
-#include "FileLike.h"
-
-namespace mbed {
-
-extern void mbed_set_unbuffered_stream(FILE *_file);
-extern int mbed_getc(FILE *_file);
-extern char* mbed_gets(char *s, int size, FILE *_file);
-
-class Stream : public FileLike {
-
-public:
-    Stream(const char *name=NULL);
-    virtual ~Stream();
-
-    int putc(int c);
-    int puts(const char *s);
-    int getc();
-    char *gets(char *s, int size);
-    int printf(const char* format, ...);
-    int scanf(const char* format, ...);
-
-    operator std::FILE*() {return _file;}
-
-protected:
-    virtual int close();
-    virtual ssize_t write(const void* buffer, size_t length);
-    virtual ssize_t read(void* buffer, size_t length);
-    virtual off_t lseek(off_t offset, int whence);
-    virtual int isatty();
-    virtual int fsync();
-    virtual off_t flen();
-
-    virtual int _putc(int c) = 0;
-    virtual int _getc() = 0;
-
-    std::FILE *_file;
-
-    /* disallow copy constructor and assignment operators */
-private:
-    Stream(const Stream&);
-    Stream & operator = (const Stream&);
-};
-
-} // namespace mbed
-
-#endif

--- a/api/Ticker.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,127 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TICKER_H
-#define MBED_TICKER_H
-
-#include "TimerEvent.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** A Ticker is used to call a function at a recurring interval
- *
- *  You can use as many seperate Ticker objects as you require.
- *
- * Example:
- * @code
- * // Toggle the blinking led after 5 seconds
- *
- * #include "mbed.h"
- *
- * Ticker timer;
- * DigitalOut led1(LED1);
- * DigitalOut led2(LED2);
- *
- * int flip = 0;
- *
- * void attime() {
- *     flip = !flip;
- * }
- *
- * int main() {
- *     timer.attach(&attime, 5);
- *     while(1) {
- *         if(flip == 0) {
- *             led1 = !led1;
- *         } else {
- *             led2 = !led2;
- *         }
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class Ticker : public TimerEvent {
-
-public:
-    Ticker() : TimerEvent() {
-    }
-
-    Ticker(const ticker_data_t *data) : TimerEvent(data) {
-    }
-
-    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
-     *
-     *  @param fptr pointer to the function to be called
-     *  @param t the time between calls in seconds
-     */
-    void attach(void (*fptr)(void), float t) {
-        attach_us(fptr, t * 1000000.0f);
-    }
-
-    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *  @param t the time between calls in seconds
-     */
-    template<typename T>
-    void attach(T* tptr, void (T::*mptr)(void), float t) {
-        attach_us(tptr, mptr, t * 1000000.0f);
-    }
-
-    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
-     *
-     *  @param fptr pointer to the function to be called
-     *  @param t the time between calls in micro-seconds
-     */
-    void attach_us(void (*fptr)(void), timestamp_t t) {
-        _function.attach(fptr);
-        setup(t);
-    }
-
-    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
-     *
-     *  @param tptr pointer to the object to call the member function on
-     *  @param mptr pointer to the member function to be called
-     *  @param t the time between calls in micro-seconds
-     */
-    template<typename T>
-    void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) {
-        _function.attach(tptr, mptr);
-        setup(t);
-    }
-
-    virtual ~Ticker() {
-        detach();
-    }
-
-    /** Detach the function
-     */
-    void detach();
-
-protected:
-    void setup(timestamp_t t);
-    virtual void handler();
-
-protected:
-    timestamp_t     _delay;     /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
-    FunctionPointer _function;  /**< Callback. */
-};
-
-} // namespace mbed
-
-#endif

--- a/api/Timeout.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEOUT_H
-#define MBED_TIMEOUT_H
-
-#include "Ticker.h"
-
-namespace mbed {
-
-/** A Timeout is used to call a function at a point in the future
- *
- * You can use as many seperate Timeout objects as you require.
- *
- * Example:
- * @code
- * // Blink until timeout.
- *
- * #include "mbed.h"
- *
- * Timeout timeout;
- * DigitalOut led(LED1);
- *
- * int on = 1;
- *
- * void attimeout() {
- *     on = 0;
- * }
- *
- * int main() {
- *     timeout.attach(&attimeout, 5);
- *     while(on) {
- *         led = !led;
- *         wait(0.2);
- *     }
- * }
- * @endcode
- */
-class Timeout : public Ticker {
-
-protected:
-    virtual void handler();
-};
-
-} // namespace mbed
-
-#endif

--- a/api/Timer.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,91 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMER_H
-#define MBED_TIMER_H
-
-#include "platform.h"
-#include "ticker_api.h"
-
-namespace mbed {
-
-/** A general purpose timer
- *
- * Example:
- * @code
- * // Count the time to toggle a LED
- *
- * #include "mbed.h"
- *
- * Timer timer;
- * DigitalOut led(LED1);
- * int begin, end;
- *
- * int main() {
- *     timer.start();
- *     begin = timer.read_us();
- *     led = !led;
- *     end = timer.read_us();
- *     printf("Toggle the led takes %d us", end - begin);
- * }
- * @endcode
- */
-class Timer {
-
-public:
-    Timer();
-    Timer(const ticker_data_t *data);
-
-    /** Start the timer
-     */
-    void start();
-
-    /** Stop the timer
-     */
-    void stop();
-
-    /** Reset the timer to 0.
-     *
-     * If it was already counting, it will continue
-     */
-    void reset();
-
-    /** Get the time passed in seconds
-     */
-    float read();
-
-    /** Get the time passed in mili-seconds
-     */
-    int read_ms();
-
-    /** Get the time passed in micro-seconds
-     */
-    int read_us();
-
-#ifdef MBED_OPERATORS
-    operator float();
-#endif
-
-protected:
-    int slicetime();
-    int _running;          // whether the timer is running
-    unsigned int _start;   // the start time of the latest slice
-    int _time;             // any accumulated time from previous slices
-    const ticker_data_t *_ticker_data;
-};
-
-} // namespace mbed
-
-#endif

--- a/api/TimerEvent.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TIMEREVENT_H
-#define MBED_TIMEREVENT_H
-
-#include "ticker_api.h"
-#include "us_ticker_api.h"
-
-namespace mbed {
-
-/** Base abstraction for timer interrupts
-*/
-class TimerEvent {
-public:
-    TimerEvent();
-    TimerEvent(const ticker_data_t *data);
-
-    /** The handler registered with the underlying timer interrupt
-     */
-    static void irq(uint32_t id);
-
-    /** Destruction removes it...
-     */
-    virtual ~TimerEvent();
-
-protected:
-    // The handler called to service the timer event of the derived class
-    virtual void handler() = 0;
-
-    // insert in to linked list
-    void insert(timestamp_t timestamp);
-
-    // remove from linked list, if in it
-    void remove();
-
-    ticker_event_t event;
-
-    const ticker_data_t *_ticker_data;
-};
-
-} // namespace mbed
-
-#endif

--- a/api/Transaction.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,73 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TRANSACTION_H
-#define MBED_TRANSACTION_H
-
-#include "platform.h"
-#include "FunctionPointer.h"
-
-namespace mbed {
-
-/** Transaction structure
- */
-typedef struct {
-    void *tx_buffer;           /**< Tx buffer */
-    size_t tx_length;          /**< Length of Tx buffer*/
-    void *rx_buffer;           /**< Rx buffer */
-    size_t rx_length;          /**< Length of Rx buffer */
-    uint32_t event;            /**< Event for a transaction */
-    event_callback_t callback; /**< User's callback */
-    uint8_t width;             /**< Buffer's word width (8, 16, 32, 64) */
-} transaction_t;
-
-/** Transaction class defines a transaction.
- */
-template<typename Class>
-class Transaction {
-public:
-    Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) {
-    }
-
-    Transaction() : _obj(), _data() {
-    }
-
-    ~Transaction() {
-    }
-
-    /** Get object's instance for the transaction
-     *
-     * @return The object which was stored
-     */
-    Class* get_object() {
-        return _obj;
-    }
-
-    /** Get the transaction
-     *
-     * @return The transaction which was stored
-     */
-    transaction_t* get_transaction() {
-        return &_data;
-    }
-
-private:
-    Class* _obj;
-    transaction_t _data;
-};
-
-}
-
-#endif

--- a/api/can_helper.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,53 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_HELPER_H
-#define MBED_CAN_HELPER_H
-
-#if DEVICE_CAN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-enum CANFormat {
-    CANStandard = 0,
-    CANExtended = 1,
-    CANAny = 2
-};
-typedef enum CANFormat CANFormat;
-
-enum CANType {
-    CANData   = 0,
-    CANRemote = 1
-};
-typedef enum CANType CANType;
-
-struct CAN_Message {
-    unsigned int   id;                 // 29 bit identifier
-    unsigned char  data[8];            // Data field
-    unsigned char  len;                // Length of data field in bytes
-    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
-    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
-};
-typedef struct CAN_Message CAN_Message;
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif
-
-#endif // MBED_CAN_HELPER_H

--- a/api/mbed.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,69 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_H
-#define MBED_H
-
-#define MBED_LIBRARY_VERSION 107
-
-#include "platform.h"
-
-// Useful C libraries
-#include <math.h>
-#include <time.h>
-
-// mbed Debug libraries
-#include "mbed_error.h"
-#include "mbed_interface.h"
-
-// mbed Peripheral components
-#include "DigitalIn.h"
-#include "DigitalOut.h"
-#include "DigitalInOut.h"
-#include "BusIn.h"
-#include "BusOut.h"
-#include "BusInOut.h"
-#include "PortIn.h"
-#include "PortInOut.h"
-#include "PortOut.h"
-#include "AnalogIn.h"
-#include "AnalogOut.h"
-#include "PwmOut.h"
-#include "Serial.h"
-#include "SPI.h"
-#include "SPISlave.h"
-#include "I2C.h"
-#include "I2CSlave.h"
-#include "Ethernet.h"
-#include "CAN.h"
-#include "RawSerial.h"
-
-// mbed Internal components
-#include "Timer.h"
-#include "Ticker.h"
-#include "Timeout.h"
-#include "LowPowerTimeout.h"
-#include "LowPowerTicker.h"
-#include "LowPowerTimer.h"
-#include "LocalFileSystem.h"
-#include "InterruptIn.h"
-#include "wait_api.h"
-#include "sleep_api.h"
-#include "rtc_time.h"
-
-using namespace mbed;
-using namespace std;
-
-#endif

--- a/api/mbed_assert.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ASSERT_H
-#define MBED_ASSERT_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
- *  This function is active only if NDEBUG is not defined prior to including this
- *  assert header file.
- *  In case of MBED_ASSERT failing condition, error() is called with the assertation message.
- *  @param expr Expresion to be checked.
- *  @param file File where assertation failed.
- *  @param line Failing assertation line number.
- */
-void mbed_assert_internal(const char *expr, const char *file, int line);
-
-#ifdef __cplusplus
-}
-#endif
-
-#ifdef NDEBUG
-#define MBED_ASSERT(expr) ((void)0)
-
-#else
-#define MBED_ASSERT(expr)                                \
-do {                                                     \
-    if (!(expr)) {                                       \
-        mbed_assert_internal(#expr, __FILE__, __LINE__); \
-    }                                                    \
-} while (0)
-#endif
-
-#endif

--- a/api/mbed_debug.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DEBUG_H
-#define MBED_DEBUG_H
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#include <stdarg.h>
-
-/** Output a debug message
- *
- * @param format printf-style format string, followed by variables
- */
-static inline void debug(const char *format, ...) {
-    va_list args;
-    va_start(args, format);
-    vfprintf(stderr, format, args);
-    va_end(args);
-}
-
-/** Conditionally output a debug message
- *
- * NOTE: If the condition is constant false (!= 1) and the compiler optimization
- * level is greater than 0, then the whole function will be compiled away.
- *
- * @param condition output only if condition is true (== 1)
- * @param format printf-style format string, followed by variables
- */
-static inline void debug_if(int condition, const char *format, ...) {
-    if (condition == 1) {
-        va_list args;
-        va_start(args, format);
-        vfprintf(stderr, format, args);
-        va_end(args);
-    }
-}
-
-#else
-static inline void debug(const char *format, ...) {}
-static inline void debug_if(int condition, const char *format, ...) {}
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/api/mbed_error.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ERROR_H
-#define MBED_ERROR_H
-
-/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
- *
- * @code
- * #error "That shouldn't have happened!"
- * @endcode
- *
- * If the compiler evaluates this line, it will report the error and stop the compile.
- *
- * For example, you could use this to check some user-defined compile-time variables:
- *
- * @code
- * #define NUM_PORTS 7
- * #if (NUM_PORTS > 4)
- *     #error "NUM_PORTS must be less than 4"
- * #endif
- * @endcode
- *
- * Reporting Run-Time Errors:
- * To generate a fatal run-time error, you can use the mbed error() function.
- *
- * @code
- * error("That shouldn't have happened!");
- * @endcode
- *
- * If the mbed running the program executes this function, it will print the
- * message via the USB serial port, and then die with the blue lights of death!
- *
- * The message can use printf-style formatting, so you can report variables in the
- * message too. For example, you could use this to check a run-time condition:
- *
- * @code
- * if(x >= 5) {
- *     error("expected x to be less than 5, but got %d", x);
- * }
- * #endcode
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void error(const char* format, ...);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/api/mbed_interface.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,114 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_INTERFACE_H
-#define MBED_INTERFACE_H
-
-#include "device.h"
-
-/* Mbed interface mac address
- * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
- * otherwise MAC_ADD_x are used.
- */
-#define MBED_MAC_ADDR_INTERFACE 0x00
-#define MBED_MAC_ADDR_0  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_1  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_2  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_3  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_4  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDR_5  MBED_MAC_ADDR_INTERFACE
-#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-/** Functions to control the mbed interface
- *
- * mbed Microcontrollers have a built-in interface to provide functionality such as
- * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
- * system. These functions provide means to control the interface suing semihost
- * calls it supports.
- */
-
-/** Determine whether the mbed interface is connected, based on whether debug is enabled
- *
- *  @returns
- *    1 if interface is connected,
- *    0 otherwise
- */
-int mbed_interface_connected(void);
-
-/** Instruct the mbed interface to reset, as if the reset button had been pressed
- *
- *  @returns
- *    1 if successful,
- *    0 otherwise (e.g. interface not present)
- */
-int mbed_interface_reset(void);
-
-/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
- * The interface will still support the USB serial aspect
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_disconnect(void);
-
-/** This will disconnect the debug aspect of the interface, and if the USB cable is not
- * connected, also power down the interface. If the USB cable is connected, the interface
- * will remain powered up and visible to the host
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_powerdown(void);
-
-/** This returns a string containing the 32-character UID of the mbed interface
- *  This is a weak function that can be overwritten if required
- *
- *  @param uid A 33-byte array to write the null terminated 32-byte string
- *
- *  @returns
- *    0 if successful,
- *   -1 otherwise (e.g. interface not present)
- */
-int mbed_interface_uid(char *uid);
-
-#endif
-
-/** This returns a unique 6-byte MAC address, based on the interface UID
- * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
- *
- * This is a weak function that can be overwritten if you want to provide your own mechanism to
- * provide a MAC address.
- *
- *  @param mac A 6-byte array to write the MAC address
- */
-void mbed_mac_address(char *mac);
-
-/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
- */
-void mbed_die(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/api/platform.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PLATFORM_H
-#define MBED_PLATFORM_H
-
-#define MBED_OPERATORS    1
-
-#include "device.h"
-#include "PinNames.h"
-#include "PeripheralNames.h"
-
-#include <cstddef>
-#include <cstdlib>
-#include <cstdio>
-#include <cstring>
-
-#endif

--- a/api/rtc_time.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,85 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Implementation of the C time.h functions
- *
- * Provides mechanisms to set and read the current time, based
- * on the microcontroller Real-Time Clock (RTC), plus some
- * standard C manipulation and formating functions.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37
- *
- *     while(1) {
- *         time_t seconds = time(NULL);
- *
- *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);
- *
- *         printf("Time as a basic string = %s", ctime(&seconds));
- *
- *         char buffer[32];
- *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
- *         printf("Time as a custom formatted string = %s", buffer);
- *
- *         wait(1);
- *     }
- * }
- * @endcode
- */
-
-/** Set the current time
- *
- * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
- * to the time represented by the number of seconds since January 1, 1970
- * (the UNIX timestamp).
- *
- * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * int main() {
- *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
- * }
- * @endcode
- */
-void set_time(time_t t);
-
-/** Attach an external RTC to be used for the C time functions
- *
- * Do not call this function from an interrupt while an RTC read/write operation may be occurring 
- *
- * @param read_rtc pointer to function which returns current UNIX timestamp
- * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
- * @param init_rtc pointer to funtion which initializes RTC, can be NULL
- * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
- */
-void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
-
-#ifdef __cplusplus
-}
-#endif

--- a/api/semihost_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SEMIHOST_H
-#define MBED_SEMIHOST_H
-
-#include "device.h"
-#include "toolchain.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#if DEVICE_SEMIHOST
-
-#ifndef __CC_ARM
-
-#if defined(__ICCARM__)
-inline int __semihost(int reason, const void *arg) {
-    return __semihosting(reason, (void*)arg);
-}
-#else
-
-#ifdef __thumb__
-#   define AngelSWI            0xAB
-#   define AngelSWIInsn        "bkpt"
-#   define AngelSWIAsm          bkpt
-#else
-#   define AngelSWI            0x123456
-#   define AngelSWIInsn        "swi"
-#   define AngelSWIAsm          swi
-#endif
-
-static inline int __semihost(int reason, const void *arg) {
-    int value;
-
-    asm volatile (
-       "mov r0, %1"          "\n\t"
-       "mov r1, %2"          "\n\t"
-       AngelSWIInsn " %a3"   "\n\t"
-       "mov %0, r0"
-       : "=r" (value)                                         /* output operands             */
-       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */
-       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */
-    );
-
-    return value;
-}
-#endif
-#endif
-
-#if DEVICE_LOCALFILESYSTEM
-FILEHANDLE semihost_open(const char* name, int openmode);
-int semihost_close (FILEHANDLE fh);
-int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
-int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
-int semihost_ensure(FILEHANDLE fh);
-long semihost_flen (FILEHANDLE fh);
-int semihost_seek  (FILEHANDLE fh, long position);
-int semihost_istty (FILEHANDLE fh);
-
-int semihost_remove(const char *name);
-int semihost_rename(const char *old_name, const char *new_name);
-#endif
-
-int semihost_uid(char *uid);
-int semihost_reset(void);
-int semihost_vbus(void);
-int semihost_powerdown(void);
-int semihost_exit(void);
-
-int semihost_connected(void);
-int semihost_disabledebug(void);
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/api/toolchain.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TOOLCHAIN_H
-#define MBED_TOOLCHAIN_H
-
-#if defined(TOOLCHAIN_ARM)
-#include <rt_sys.h>
-#endif
-
-#ifndef FILEHANDLE
-typedef int FILEHANDLE;
-#endif
-
-#if defined (__ICCARM__)
-#   define WEAK     __weak
-#   define PACKED   __packed
-#else
-#   define WEAK     __attribute__((weak))
-#   define PACKED   __attribute__((packed))
-#endif
-
-#endif

--- a/api/wait_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_WAIT_API_H
-#define MBED_WAIT_API_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Generic wait functions.
- *
- * These provide simple NOP type wait capabilities.
- *
- * Example:
- * @code
- * #include "mbed.h"
- *
- * DigitalOut heartbeat(LED1);
- *
- * int main() {
- *     while (1) {
- *         heartbeat = 1;
- *         wait(0.5);
- *         heartbeat = 0;
- *         wait(0.5);
- *     }
- * }
- */
-
-/** Waits for a number of seconds, with microsecond resolution (within
- *  the accuracy of single precision floating point).
- *
- *  @param s number of seconds to wait
- */
-void wait(float s);
-
-/** Waits a number of milliseconds.
- *
- *  @param ms the whole number of milliseconds to wait
- */
-void wait_ms(int ms);
-
-/** Waits a number of microseconds.
- *
- *  @param us the whole number of microseconds to wait
- */
-void wait_us(int us);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/AnalogIn.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_H
+#define MBED_ANALOGIN_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGIN
+
+#include "analogin_api.h"
+
+namespace mbed {
+
+/** An analog input, used for reading the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Print messages when the AnalogIn is greater than 50%
+ *
+ * #include "mbed.h"
+ *
+ * AnalogIn temperature(p20);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(temperature > 0.5) {
+ *             printf("Too hot! (%f)", temperature.read());
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class AnalogIn {
+
+public:
+
+    /** Create an AnalogIn, connected to the specified pin
+     *
+     * @param pin AnalogIn pin to connect to
+     * @param name (optional) A string to identify the object
+     */
+    AnalogIn(PinName pin) {
+        analogin_init(&_adc, pin);
+    }
+
+    /** Read the input voltage, represented as a float in the range [0.0, 1.0]
+     *
+     * @returns A floating-point value representing the current input voltage, measured as a percentage
+     */
+    float read() {
+        return analogin_read(&_adc);
+    }
+
+    /** Read the input voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     * @returns
+     *   16-bit unsigned short representing the current input voltage, normalised to a 16-bit value
+     */
+    unsigned short read_u16() {
+        return analogin_read_u16(&_adc);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for read()
+     *
+     * The float() operator can be used as a shorthand for read() to simplify common code sequences
+     *
+     * Example:
+     * @code
+     * float x = volume.read();
+     * float x = volume;
+     *
+     * if(volume.read() > 0.25) { ... }
+     * if(volume > 0.25) { ... }
+     * @endcode
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    analogin_t _adc;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/AnalogOut.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,121 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_H
+#define MBED_ANALOGOUT_H
+
+#include "platform.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "analogout_api.h"
+
+namespace mbed {
+
+/** An analog output, used for setting the voltage on a pin
+ *
+ * Example:
+ * @code
+ * // Make a sawtooth output
+ *
+ * #include "mbed.h"
+ *
+ * AnalogOut tri(p18);
+ * int main() {
+ *     while(1) {
+ *         tri = tri + 0.01;
+ *         wait_us(1);
+ *         if(tri == 1) {
+ *             tri = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class AnalogOut {
+
+public:
+
+    /** Create an AnalogOut connected to the specified pin
+     *
+     *  @param AnalogOut pin to connect to (18)
+     */
+    AnalogOut(PinName pin) {
+        analogout_init(&_dac, pin);
+    }
+
+    /** Set the output voltage, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output voltage,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        analogout_write(&_dac, value);
+    }
+
+    /** Set the output voltage, represented as an unsigned short in the range [0x0, 0xFFFF]
+     *
+     *  @param value 16-bit unsigned short representing the output voltage,
+     *            normalised to a 16-bit value (0x0000 = 0v, 0xFFFF = 3.3v)
+     */
+    void write_u16(unsigned short value) {
+        analogout_write_u16(&_dac, value);
+    }
+
+    /** Return the current output voltage setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current voltage being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing 0v / 0%) and 1.0f (representing 3.3v / 100%).
+     *
+     *  @note
+     *    This value may not match exactly the value set by a previous write().
+     */
+    float read() {
+        return analogout_read(&_dac);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for write()
+     */
+    AnalogOut& operator= (float percent) {
+        write(percent);
+        return *this;
+    }
+
+    AnalogOut& operator= (AnalogOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    dac_t _dac;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/BusIn.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSIN_H
+#define MBED_BUSIN_H
+
+#include "platform.h"
+#include "DigitalIn.h"
+
+namespace mbed {
+
+/** A digital input bus, used for reading the state of a collection of pins
+ */
+class BusIn {
+
+public:
+    /* Group: Configuration Methods */
+
+    /** Create an BusIn, connected to the specified pins
+     *
+     * @param <n> DigitalIn pin to connect to bus bit <n> (p5-p30, NC)
+     *
+     * @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusIn(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+          PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+          PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+          PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusIn(PinName pins[16]);
+
+    virtual ~BusIn();
+
+    /** Read the value of the input bus
+     *
+     *  @returns
+     *   An integer with each bit corresponding to the value read from the associated DigitalIn pin
+     */
+    int read();
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        return _nc_mask;
+    }
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for read()
+     */
+    operator int();
+
+    /** Access to particular bit in random-iterator fashion
+     */
+    DigitalIn & operator[] (int index);
+#endif
+
+protected:
+    DigitalIn* _pin[16];
+
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    BusIn(const BusIn&);
+    BusIn & operator = (const BusIn&);
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/BusInOut.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,117 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSINOUT_H
+#define MBED_BUSINOUT_H
+
+#include "DigitalInOut.h"
+
+namespace mbed {
+
+/** A digital input output bus, used for setting the state of a collection of pins
+ */
+class BusInOut {
+
+public:
+
+    /** Create an BusInOut, connected to the specified pins
+     *
+     *  @param p<n> DigitalInOut pin to connect to bus bit p<n> (p5-p30, NC)
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusInOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+             PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+             PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+             PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusInOut(PinName pins[16]);
+
+    virtual ~BusInOut();
+
+    /* Group: Access Methods */
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalInOut pin
+     */
+    void write(int value);
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalInOut pin setting
+     */
+    int read();
+
+    /** Set as an output
+     */
+    void output();
+
+    /** Set as an input
+     */
+    void input();
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        return _nc_mask;
+    }
+
+#ifdef MBED_OPERATORS
+     /** A shorthand for write()
+     */
+    BusInOut& operator= (int v);
+    BusInOut& operator= (BusInOut& rhs);
+
+    /** Access to particular bit in random-iterator fashion
+    */
+    DigitalInOut& operator[] (int index);
+
+    /** A shorthand for read()
+     */
+    operator int();
+#endif
+
+protected:
+    DigitalInOut* _pin[16];
+
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    BusInOut(const BusInOut&);
+    BusInOut & operator = (const BusInOut&);
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/BusOut.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,101 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUSOUT_H
+#define MBED_BUSOUT_H
+
+#include "DigitalOut.h"
+
+namespace mbed {
+
+/** A digital output bus, used for setting the state of a collection of pins
+ */
+class BusOut {
+
+public:
+
+    /** Create an BusOut, connected to the specified pins
+     *
+     *  @param p<n> DigitalOut pin to connect to bus bit <n> (p5-p30, NC)
+     *
+     *  @note
+     *  It is only required to specify as many pin variables as is required
+     *  for the bus; the rest will default to NC (not connected)
+     */
+    BusOut(PinName p0, PinName p1 = NC, PinName p2 = NC, PinName p3 = NC,
+           PinName p4 = NC, PinName p5 = NC, PinName p6 = NC, PinName p7 = NC,
+           PinName p8 = NC, PinName p9 = NC, PinName p10 = NC, PinName p11 = NC,
+           PinName p12 = NC, PinName p13 = NC, PinName p14 = NC, PinName p15 = NC);
+
+    BusOut(PinName pins[16]);
+
+    virtual ~BusOut();
+
+    /** Write the value to the output bus
+     *
+     *  @param value An integer specifying a bit to write for every corresponding DigitalOut pin
+     */
+    void write(int value);
+
+    /** Read the value currently output on the bus
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated DigitalOut pin setting
+     */
+    int read();
+
+    /** Binary mask of bus pins connected to actual pins (not NC pins)
+     *  If bus pin is in NC state make corresponding bit will be cleared (set to 0), else bit will be set to 1
+     *
+     *  @returns
+     *    Binary mask of connected pins
+     */
+    int mask() {
+        return _nc_mask;
+    }
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    BusOut& operator= (int v);
+    BusOut& operator= (BusOut& rhs);
+
+    /** Access to particular bit in random-iterator fashion
+     */
+    DigitalOut& operator[] (int index);
+
+    /** A shorthand for read()
+     */
+    operator int();
+#endif
+
+protected:
+    DigitalOut* _pin[16];
+
+    /** Mask of bus's NC pins
+     * If bit[n] is set to 1 - pin is connected
+     * if bit[n] is cleared - pin is not connected (NC)
+     */
+    int _nc_mask;
+
+   /* disallow copy constructor and assignment operators */
+private:
+    BusOut(const BusOut&);
+    BusOut & operator = (const BusOut&);
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/CAN.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_H
+#define MBED_CAN_H
+
+#include "platform.h"
+
+#if DEVICE_CAN
+
+#include "can_api.h"
+#include "can_helper.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** CANMessage class
+ */
+class CANMessage : public CAN_Message {
+
+public:
+    /** Creates empty CAN message.
+     */
+    CANMessage() : CAN_Message() {
+        len    = 8;
+        type   = CANData;
+        format = CANStandard;
+        id     = 0;
+        memset(data, 0, 8);
+    }
+
+    /** Creates CAN message with specific content.
+     */
+    CANMessage(int _id, const char *_data, char _len = 8, CANType _type = CANData, CANFormat _format = CANStandard) {
+      len    = _len & 0xF;
+      type   = _type;
+      format = _format;
+      id     = _id;
+      memcpy(data, _data, _len);
+    }
+
+    /** Creates CAN remote message.
+     */
+    CANMessage(int _id, CANFormat _format = CANStandard) {
+      len    = 0;
+      type   = CANRemote;
+      format = _format;
+      id     = _id;
+      memset(data, 0, 8);
+    }
+};
+
+/** A can bus client, used for communicating with can devices
+ */
+class CAN {
+
+public:
+    /** Creates an CAN interface connected to specific pins.
+     *
+     *  @param rd read from transmitter
+     *  @param td transmit to transmitter
+     *
+     * Example:
+     * @code
+     * #include "mbed.h"
+     *
+     * Ticker ticker;
+     * DigitalOut led1(LED1);
+     * DigitalOut led2(LED2);
+     * CAN can1(p9, p10);
+     * CAN can2(p30, p29);
+     *
+     * char counter = 0;
+     *
+     * void send() {
+     *     if(can1.write(CANMessage(1337, &counter, 1))) {
+     *         printf("Message sent: %d\n", counter);
+     *         counter++;
+     *     }
+     *     led1 = !led1;
+     * }
+     *
+     * int main() {
+     *     ticker.attach(&send, 1);
+     *    CANMessage msg;
+     *     while(1) {
+     *         if(can2.read(msg)) {
+     *             printf("Message received: %d\n\n", msg.data[0]);
+     *             led2 = !led2;
+     *         }
+     *         wait(0.2);
+     *     }
+     * }
+     * @endcode
+     */
+    CAN(PinName rd, PinName td);
+    virtual ~CAN();
+
+    /** Set the frequency of the CAN interface
+     *
+     *  @param hz The bus frequency in hertz
+     *
+     *  @returns
+     *    1 if successful,
+     *    0 otherwise
+     */
+    int frequency(int hz);
+
+    /** Write a CANMessage to the bus.
+     *
+     *  @param msg The CANMessage to write.
+     *
+     *  @returns
+     *    0 if write failed,
+     *    1 if write was successful
+     */
+    int write(CANMessage msg);
+
+    /** Read a CANMessage from the bus.
+     *
+     *  @param msg A CANMessage to read to.
+     *  @param handle message filter handle (0 for any message)
+     *
+     *  @returns
+     *    0 if no message arrived,
+     *    1 if message arrived
+     */
+    int read(CANMessage &msg, int handle = 0);
+
+    /** Reset CAN interface.
+     *
+     * To use after error overflow.
+     */
+    void reset();
+
+    /** Puts or removes the CAN interface into silent monitoring mode
+     *
+     *  @param silent boolean indicating whether to go into silent mode or not
+     */
+    void monitor(bool silent);
+
+    enum Mode {
+        Reset = 0,
+        Normal,
+        Silent,
+        LocalTest,
+        GlobalTest,
+        SilentTest
+    };
+
+    /** Change CAN operation to the specified mode
+     *
+     *  @param mode The new operation mode (CAN::Normal, CAN::Silent, CAN::LocalTest, CAN::GlobalTest, CAN::SilentTest)
+     *
+     *  @returns
+     *    0 if mode change failed or unsupported,
+     *    1 if mode change was successful
+     */
+    int mode(Mode mode);
+
+    /** Filter out incomming messages
+     *
+     *  @param id the id to filter on
+     *  @param mask the mask applied to the id
+     *  @param format format to filter on (Default CANAny)
+     *  @param handle message filter handle (Optional)
+     *
+     *  @returns
+     *    0 if filter change failed or unsupported,
+     *    new filter handle if successful
+     */
+    int filter(unsigned int id, unsigned int mask, CANFormat format = CANAny, int handle = 0);
+
+    /** Returns number of read errors to detect read overflow errors.
+     */
+    unsigned char rderror();
+
+    /** Returns number of write errors to detect write overflow errors.
+     */
+    unsigned char tderror();
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq,
+        EwIrq,
+        DoIrq,
+        WuIrq,
+        EpIrq,
+        AlIrq,
+        BeIrq,
+        IdIrq
+    };
+
+    /** Attach a function to call whenever a CAN frame received interrupt is
+     *  generated.
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, CAN::TxIrq for transmitted or aborted, CAN::EwIrq for error warning, CAN::DoIrq for data overrun, CAN::WuIrq for wake-up, CAN::EpIrq for error passive, CAN::AlIrq for arbitration lost, CAN::BeIrq for bus error)
+     */
+    void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+   /** Attach a member function to call whenever a CAN frame received interrupt
+    *  is generated.
+    *
+    *  @param tptr pointer to the object to call the member function on
+    *  @param mptr pointer to the member function to be called
+    *  @param event Which CAN interrupt to attach the member function to (CAN::RxIrq for message received, TxIrq for transmitted or aborted, EwIrq for error warning, DoIrq for data overrun, WuIrq for wake-up, EpIrq for error passive, AlIrq for arbitration lost, BeIrq for bus error)
+    */
+   template<typename T>
+   void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            _irq[type].attach(tptr, mptr);
+            can_irq_set(&_can, (CanIrqType)type, 1);
+        }
+        else {
+            can_irq_set(&_can, (CanIrqType)type, 0);
+        }
+    }
+
+    static void _irq_handler(uint32_t id, CanIrqType type);
+
+protected:
+    can_t           _can;
+    FunctionPointer _irq[9];
+};
+
+} // namespace mbed
+
+#endif
+
+#endif    // MBED_CAN_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/CThunk.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,202 @@
+/* General C++ Object Thunking class
+ *
+ * - allows direct callbacks to non-static C++ class functions
+ * - keeps track for the corresponding class instance
+ * - supports an optional context parameter for the called function
+ * - ideally suited for class object receiving interrupts (NVIC_SetVector)
+ *
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef __CTHUNK_H__
+#define __CTHUNK_H__
+
+#define CTHUNK_ADDRESS 1
+
+#if defined(__CORTEX_M3) || defined(__CORTEX_M4) || defined(__thumb2__)
+#define CTHUNK_VARIABLES volatile uint32_t code[1]
+/**
+* CTHUNK disassembly for Cortex-M3/M4 (thumb2):
+* * ldm.w pc,{r0,r1,r2,pc}
+*
+* This instruction loads the arguments for the static thunking function to r0-r2, and
+* branches to that function by loading its address into PC.
+*
+* This is safe for both regular calling and interrupt calling, since it only touches scratch registers
+* which should be saved by the caller, and are automatically saved as part of the IRQ context switch.
+*/
+#define CTHUNK_ASSIGMENT m_thunk.code[0] = 0x8007E89F
+
+#elif defined(__CORTEX_M0PLUS) || defined(__CORTEX_M0)
+/*
+* CTHUNK disassembly for Cortex M0 (thumb):
+* * push {r0,r1,r2,r3,r4,lr} save touched registers and return address
+* * movs r4,#4 set up address to load arguments from (immediately following this code block) (1)
+* * add r4,pc set up address to load arguments from (immediately following this code block) (2)
+* * ldm r4!,{r0,r1,r2,r3} load arguments for static thunk function
+* * blx r3 call static thunk function
+* * pop {r0,r1,r2,r3,r4,pc} restore scratch registers and return from function
+*/
+#define CTHUNK_VARIABLES volatile uint32_t code[3]
+#define CTHUNK_ASSIGMENT do {                              \
+                             m_thunk.code[0] = 0x2404B51F; \
+                             m_thunk.code[1] = 0xCC0F447C; \
+                             m_thunk.code[2] = 0xBD1F4798; \
+                         } while (0)
+
+#else
+#error "Target is not currently suported."
+#endif
+
+/* IRQ/Exception compatible thunk entry function */
+typedef void (*CThunkEntry)(void);
+
+template<class T>
+class CThunk
+{
+    public:
+        typedef void (T::*CCallbackSimple)(void);
+        typedef void (T::*CCallback)(void* context);
+
+        inline CThunk(T *instance)
+        {
+            init(instance, NULL, NULL);
+        }
+
+        inline CThunk(T *instance, CCallback callback)
+        {
+            init(instance, callback, NULL);
+        }
+
+        ~CThunk() {
+
+        }
+
+        inline CThunk(T *instance, CCallbackSimple callback)
+        {
+            init(instance, (CCallback)callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallback callback)
+        {
+            init(instance, callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallbackSimple callback)
+        {
+            init(instance, (CCallback)callback, NULL);
+        }
+
+        inline CThunk(T &instance, CCallback callback, void* context)
+        {
+            init(instance, callback, context);
+        }
+
+        inline void callback(CCallback callback)
+        {
+            m_callback = callback;
+        }
+
+        inline void callback(CCallbackSimple callback)
+        {
+            m_callback = (CCallback)callback;
+        }
+
+        inline void context(void* context)
+        {
+            m_thunk.context = (uint32_t)context;
+        }
+
+        inline void context(uint32_t context)
+        {
+            m_thunk.context = context;
+        }
+        
+        inline uint32_t entry(void)
+        {
+            return (((uint32_t)&m_thunk)|CTHUNK_ADDRESS);
+        }
+
+        /* get thunk entry point for connecting rhunk to an IRQ table */
+        inline operator CThunkEntry(void)
+        {
+            return (CThunkEntry)entry();
+        }
+
+        /* get thunk entry point for connecting rhunk to an IRQ table */
+        inline operator uint32_t(void)
+        {
+            return entry();
+        }
+
+        /* simple test function */
+        inline void call(void)
+        {
+            (((CThunkEntry)(entry()))());
+        }
+
+    private:
+        T* m_instance;
+        volatile CCallback m_callback;
+
+// TODO: this needs proper fix, to refactor toolchain header file and all its use
+// PACKED there is not defined properly for IAR
+#if defined (__ICCARM__)
+        typedef __packed struct
+        {
+            CTHUNK_VARIABLES;
+            volatile uint32_t instance;
+            volatile uint32_t context;
+            volatile uint32_t callback;
+            volatile uint32_t trampoline;
+        }  CThunkTrampoline;
+#else
+        typedef struct
+        {
+            CTHUNK_VARIABLES;
+            volatile uint32_t instance;
+            volatile uint32_t context;
+            volatile uint32_t callback;
+            volatile uint32_t trampoline;
+        } __attribute__((__packed__)) CThunkTrampoline;
+#endif
+
+        static void trampoline(T* instance, void* context, CCallback* callback)
+        {
+            if(instance && *callback) {
+                (static_cast<T*>(instance)->**callback)(context);
+            }
+        }
+
+        volatile CThunkTrampoline m_thunk;
+
+        inline void init(T *instance, CCallback callback, void* context)
+        {
+            /* remember callback - need to add this level of redirection
+               as pointer size for member functions differs between platforms */
+            m_callback = callback;
+
+            /* populate thunking trampoline */
+            CTHUNK_ASSIGMENT;
+            m_thunk.context = (uint32_t)context;
+            m_thunk.instance = (uint32_t)instance;
+            m_thunk.callback = (uint32_t)&m_callback;
+            m_thunk.trampoline = (uint32_t)&trampoline;
+
+            __ISB();
+            __DSB();
+        }
+};
+
+#endif/*__CTHUNK_H__*/

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/CallChain.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,181 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CALLCHAIN_H
+#define MBED_CALLCHAIN_H
+
+#include "FunctionPointer.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Group one or more functions in an instance of a CallChain, then call them in
+ * sequence using CallChain::call(). Used mostly by the interrupt chaining code,
+ * but can be used for other purposes.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * CallChain chain;
+ *
+ * void first(void) {
+ *     printf("'first' function.\n");
+ * }
+ *
+ * void second(void) {
+ *     printf("'second' function.\n");
+ * }
+ *
+ * class Test {
+ * public:
+ *     void f(void) {
+ *         printf("A::f (class member).\n");
+ *     }
+ * };
+ *
+ * int main() {
+ *     Test test;
+ *
+ *     chain.add(second);
+ *     chain.add_front(first);
+ *     chain.add(&test, &Test::f);
+ *     chain.call();
+ * }
+ * @endcode
+ */
+
+typedef FunctionPointer* pFunctionPointer_t;
+
+class CallChain {
+public:
+    /** Create an empty chain
+     *
+     *  @param size (optional) Initial size of the chain
+     */
+    CallChain(int size = 4);
+    virtual ~CallChain();
+
+    /** Add a function at the end of the chain
+     *
+     *  @param function A pointer to a void function
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add(void (*function)(void));
+
+    /** Add a function at the end of the chain
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add(T *tptr, void (T::*mptr)(void)) {
+        return common_add(new FunctionPointer(tptr, mptr));
+    }
+
+    /** Add a function at the beginning of the chain
+     *
+     *  @param function A pointer to a void function
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_front(void (*function)(void));
+
+    /** Add a function at the beginning of the chain
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_front(T *tptr, void (T::*mptr)(void)) {
+        return common_add_front(new FunctionPointer(tptr, mptr));
+    }
+
+    /** Get the number of functions in the chain
+     */
+    int size() const;
+
+    /** Get a function object from the chain
+     *
+     *  @param i function object index
+     *
+     *  @returns
+     *  The function object at position 'i' in the chain
+     */
+    pFunctionPointer_t get(int i) const;
+
+    /** Look for a function object in the call chain
+     *
+     *  @param f the function object to search
+     *
+     *  @returns
+     *  The index of the function object if found, -1 otherwise.
+     */
+    int find(pFunctionPointer_t f) const;
+
+    /** Clear the call chain (remove all functions in the chain).
+     */
+    void clear();
+
+    /** Remove a function object from the chain
+     *
+     *  @arg f the function object to remove
+     *
+     *  @returns
+     *  true if the function object was found and removed, false otherwise.
+     */
+    bool remove(pFunctionPointer_t f);
+
+    /** Call all the functions in the chain in sequence
+     */
+    void call();
+
+#ifdef MBED_OPERATORS
+    void operator ()(void) {
+        call();
+    }
+    pFunctionPointer_t operator [](int i) const {
+        return get(i);
+    }
+#endif
+
+private:
+    void _check_size();
+    pFunctionPointer_t common_add(pFunctionPointer_t pf);
+    pFunctionPointer_t common_add_front(pFunctionPointer_t pf);
+
+    pFunctionPointer_t* _chain;
+    int _size;
+    int _elements;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    CallChain(const CallChain&);
+    CallChain & operator = (const CallChain&);
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/CircularBuffer.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,98 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CIRCULARBUFFER_H
+#define MBED_CIRCULARBUFFER_H
+
+namespace mbed {
+
+/** Templated Circular buffer class
+ */
+template<typename T, uint32_t BufferSize, typename CounterType = uint32_t>
+class CircularBuffer {
+public:
+    CircularBuffer() : _head(0), _tail(0), _full(false) {
+    }
+
+    ~CircularBuffer() {
+    }
+
+    /** Push the transaction to the buffer. This overwrites the buffer if it's
+     *  full
+     *
+     * @param data Data to be pushed to the buffer
+     */
+    void push(const T& data) {
+        if (full()) {
+            _tail++;
+            _tail %= BufferSize;
+        }
+        _pool[_head++] = data;
+        _head %= BufferSize;
+        if (_head == _tail) {
+            _full = true;
+        }
+    }
+
+    /** Pop the transaction from the buffer
+     *
+     * @param data Data to be pushed to the buffer
+     * @return True if the buffer is not empty and data contains a transaction, false otherwise
+     */
+    bool pop(T& data) {
+        if (!empty()) {
+            data = _pool[_tail++];
+            _tail %= BufferSize;
+            _full = false;
+            return true;
+        }
+        return false;
+    }
+
+    /** Check if the buffer is empty
+     *
+     * @return True if the buffer is empty, false if not
+     */
+    bool empty() {
+        return (_head == _tail) && !_full;
+    }
+
+    /** Check if the buffer is full
+     *
+     * @return True if the buffer is full, false if not
+     */
+    bool full() {
+        return _full;
+    }
+
+    /** Reset the buffer
+     *
+     */
+    void reset() {
+        _head = 0;
+        _tail = 0;
+        _full = false;
+    }
+
+private:
+    T _pool[BufferSize];
+    volatile CounterType _head;
+    volatile CounterType _tail;
+    volatile bool _full;
+};
+
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/DigitalIn.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,107 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALIN_H
+#define MBED_DIGITALIN_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input, used for reading the state of a pin
+ *
+ * Example:
+ * @code
+ * // Flash an LED while a DigitalIn is true
+ *
+ * #include "mbed.h"
+ *
+ * DigitalIn enable(p5);
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         if(enable) {
+ *             led = !led;
+ *         }
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ */
+class DigitalIn {
+
+public:
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     */
+    DigitalIn(PinName pin) : gpio() {
+        gpio_init_in(&gpio, pin);
+    }
+
+    /** Create a DigitalIn connected to the specified pin
+     *
+     *  @param pin DigitalIn pin to connect to
+     *  @param mode the initial mode of the pin
+     */
+    DigitalIn(PinName pin, PinMode mode) : gpio() {
+        gpio_init_in_ex(&gpio, pin, mode);
+    }
+    /** Read the input, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    An integer representing the state of the input pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        gpio_mode(&gpio, pull);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        return gpio_is_connected(&gpio);
+    }
+
+#ifdef MBED_OPERATORS
+    /** An operator shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/DigitalInOut.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,124 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALINOUT_H
+#define MBED_DIGITALINOUT_H
+
+#include "platform.h"
+
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital input/output, used for setting or reading a bi-directional pin
+ */
+class DigitalInOut {
+
+public:
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     */
+    DigitalInOut(PinName pin) : gpio() {
+        gpio_init_in(&gpio, pin);
+    }
+
+    /** Create a DigitalInOut connected to the specified pin
+     *
+     *  @param pin DigitalInOut pin to connect to
+     *  @param direction the initial direction of the pin
+     *  @param mode the initial mode of the pin
+     *  @param value the initial value of the pin if is an output
+     */
+    DigitalInOut(PinName pin, PinDirection direction, PinMode mode, int value) : gpio() {
+        gpio_init_inout(&gpio, pin, direction, mode, value);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin if it is an output,
+     *    or read the input if set as an input
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        gpio_dir(&gpio, PIN_OUTPUT);
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        gpio_dir(&gpio, PIN_INPUT);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode pull) {
+        gpio_mode(&gpio, pull);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        return gpio_is_connected(&gpio);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    DigitalInOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    DigitalInOut& operator= (DigitalInOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/DigitalOut.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,116 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIGITALOUT_H
+#define MBED_DIGITALOUT_H
+
+#include "platform.h"
+#include "gpio_api.h"
+
+namespace mbed {
+
+/** A digital output, used for setting the state of a pin
+ *
+ * Example:
+ * @code
+ * // Toggle a LED
+ * #include "mbed.h"
+ *
+ * DigitalOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class DigitalOut {
+
+public:
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     */
+    DigitalOut(PinName pin) : gpio() {
+        gpio_init_out(&gpio, pin);
+    }
+
+    /** Create a DigitalOut connected to the specified pin
+     *
+     *  @param pin DigitalOut pin to connect to
+     *  @param value the initial pin value
+     */
+    DigitalOut(PinName pin, int value) : gpio() {
+        gpio_init_out_ex(&gpio, pin, value);
+    }
+
+    /** Set the output, specified as 0 or 1 (int)
+     *
+     *  @param value An integer specifying the pin output value,
+     *      0 for logical 0, 1 (or any other non-zero value) for logical 1
+     */
+    void write(int value) {
+        gpio_write(&gpio, value);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    an integer representing the output setting of the pin,
+     *    0 for logical 0, 1 for logical 1
+     */
+    int read() {
+        return gpio_read(&gpio);
+    }
+
+    /** Return the output setting, represented as 0 or 1 (int)
+     *
+     *  @returns
+     *    Non zero value if pin is connected to uc GPIO
+     *    0 if gpio object was initialized with NC
+     */
+    int is_connected() {
+        return gpio_is_connected(&gpio);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A shorthand for write()
+     */
+    DigitalOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    DigitalOut& operator= (DigitalOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+#endif
+
+protected:
+    gpio_t gpio;
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/DirHandle.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DIRHANDLE_H
+#define MBED_DIRHANDLE_H
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#   define NAME_MAX 255
+typedef int mode_t;
+
+#else
+#   include <sys/syslimits.h>
+#endif
+
+#include "FileHandle.h"
+
+struct dirent {
+    char d_name[NAME_MAX+1];
+};
+
+namespace mbed {
+
+/** Represents a directory stream. Objects of this type are returned
+ *  by a FileSystemLike's opendir method. Implementations must define
+ *  at least closedir, readdir and rewinddir.
+ *
+ *  If a FileSystemLike class defines the opendir method, then the
+ *  directories of an object of that type can be accessed by
+ *  DIR *d = opendir("/example/directory") (or opendir("/example")
+ *  to open the root of the filesystem), and then using readdir(d) etc.
+ *
+ *  The root directory is considered to contain all FileLike and
+ *  FileSystemLike objects, so the DIR* returned by opendir("/") will
+ *  reflect this.
+ */
+class DirHandle {
+
+public:
+    /** Closes the directory.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on error.
+     */
+    virtual int closedir()=0;
+
+    /** Return the directory entry at the current position, and
+     *  advances the position to the next entry.
+     *
+     * @returns
+     *  A pointer to a dirent structure representing the
+     *  directory entry at the current position, or NULL on reaching
+     *  end of directory or error.
+     */
+    virtual struct dirent *readdir()=0;
+
+    /** Resets the position to the beginning of the directory.
+     */
+    virtual void rewinddir()=0;
+
+    /** Returns the current position of the DirHandle.
+     *
+     * @returns
+     *   the current position,
+     *  -1 on error.
+     */
+    virtual off_t telldir() { return -1; }
+
+    /** Sets the position of the DirHandle.
+     *
+     *  @param location The location to seek to. Must be a value returned by telldir.
+     */
+    virtual void seekdir(off_t location) { }
+
+    virtual ~DirHandle() {}
+};
+
+} // namespace mbed
+
+typedef mbed::DirHandle DIR;
+
+extern "C" {
+    DIR *opendir(const char*);
+    struct dirent *readdir(DIR *);
+    int closedir(DIR*);
+    void rewinddir(DIR*);
+    long telldir(DIR*);
+    void seekdir(DIR*, long);
+    int mkdir(const char *name, mode_t n);
+};
+
+#endif /* MBED_DIRHANDLE_H */

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/Ethernet.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ETHERNET_H
+#define MBED_ETHERNET_H
+
+#include "platform.h"
+
+#if DEVICE_ETHERNET
+
+namespace mbed {
+
+/** An ethernet interface, to use with the ethernet pins.
+ *
+ * Example:
+ * @code
+ * // Read destination and source from every ethernet packet
+ *
+ * #include "mbed.h"
+ *
+ * Ethernet eth;
+ *
+ * int main() {
+ *     char buf[0x600];
+ *
+ *     while(1) {
+ *         int size = eth.receive();
+ *         if(size > 0) {
+ *             eth.read(buf, size);
+ *             printf("Destination:  %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[0], buf[1], buf[2], buf[3], buf[4], buf[5]);
+ *             printf("Source: %02X:%02X:%02X:%02X:%02X:%02X\n",
+ *                     buf[6], buf[7], buf[8], buf[9], buf[10], buf[11]);
+ *         }
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+class Ethernet {
+
+public:
+
+    /** Initialise the ethernet interface.
+     */
+    Ethernet();
+
+    /** Powers the hardware down.
+     */
+    virtual ~Ethernet();
+
+    enum Mode {
+        AutoNegotiate,
+        HalfDuplex10,
+        FullDuplex10,
+        HalfDuplex100,
+        FullDuplex100
+    };
+
+    /** Writes into an outgoing ethernet packet.
+     *
+     *  It will append size bytes of data to the previously written bytes.
+     *
+     *  @param data An array to write.
+     *  @param size The size of data.
+     *
+     *  @returns
+     *   The number of written bytes.
+     */
+    int write(const char *data, int size);
+
+    /** Send an outgoing ethernet packet.
+     *
+     *  After filling in the data in an ethernet packet it must be send.
+     *  Send will provide a new packet to write to.
+     *
+     *  @returns
+     *    0 if the sending was failed,
+     *    or the size of the packet successfully sent.
+     */
+    int send();
+
+    /** Recevies an arrived ethernet packet.
+     *
+     *  Receiving an ethernet packet will drop the last received ethernet packet
+     *  and make a new ethernet packet ready to read.
+     *  If no ethernet packet is arrived it will return 0.
+     *
+     *  @returns
+     *    0 if no ethernet packet is arrived,
+     *    or the size of the arrived packet.
+     */
+    int receive();
+
+    /** Read from an recevied ethernet packet.
+     *
+     *  After receive returnd a number bigger than 0it is
+     *  possible to read bytes from this packet.
+     *  Read will write up to size bytes into data.
+     *
+     *  It is possible to use read multible times.
+     *  Each time read will start reading after the last read byte before.
+     *
+     *  @returns
+     *  The number of byte read.
+     */
+    int read(char *data, int size);
+
+    /** Gives the ethernet address of the mbed.
+     *
+     *  @param mac Must be a pointer to a 6 byte char array to copy the ethernet address in.
+     */
+    void address(char *mac);
+
+    /** Returns if an ethernet link is pressent or not. It takes a wile after Ethernet initializion to show up.
+     *
+     *  @returns
+     *   0 if no ethernet link is pressent,
+     *   1 if an ethernet link is pressent.
+     *
+     * Example:
+     * @code
+     * // Using the Ethernet link function
+     * #include "mbed.h"
+     *
+     * Ethernet eth;
+     *
+     * int main() {
+     *     wait(1); // Needed after startup.
+     *     if (eth.link()) {
+     *          printf("online\n");
+     *     } else {
+     *          printf("offline\n");
+     *     }
+     * }
+     * @endcode
+     */
+    int link();
+
+    /** Sets the speed and duplex parameters of an ethernet link
+     *
+     * - AutoNegotiate      Auto negotiate speed and duplex
+     * - HalfDuplex10       10 Mbit, half duplex
+     * - FullDuplex10       10 Mbit, full duplex
+     * - HalfDuplex100      100 Mbit, half duplex
+     * - FullDuplex100      100 Mbit, full duplex
+     *
+     *  @param mode the speed and duplex mode to set the link to:
+     */
+    void set_link(Mode mode);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/FileBase.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,80 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEBASE_H
+#define MBED_FILEBASE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+#    define O_RDONLY 0
+#    define O_WRONLY 1
+#    define O_RDWR   2
+#    define O_CREAT  0x0200
+#    define O_TRUNC  0x0400
+#    define O_APPEND 0x0008
+
+#    define NAME_MAX 255
+
+typedef int mode_t;
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+#    include <sys/fcntl.h>
+#    include <sys/types.h>
+#    include <sys/syslimits.h>
+#endif
+
+#include "platform.h"
+
+namespace mbed {
+
+typedef enum {
+    FilePathType,
+    FileSystemPathType
+} PathType;
+
+class FileBase {
+public:
+    FileBase(const char *name, PathType t);
+
+    virtual ~FileBase();
+
+    const char* getName(void);
+    PathType    getPathType(void);
+
+    static FileBase *lookup(const char *name, unsigned int len);
+
+    static FileBase *get(int n);
+
+protected:
+    static FileBase *_head;
+
+    FileBase   *_next;
+    const char *_name;
+    PathType    _path_type;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    FileBase(const FileBase&);
+    FileBase & operator = (const FileBase&);
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/FileHandle.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,119 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEHANDLE_H
+#define MBED_FILEHANDLE_H
+
+typedef int FILEHANDLE;
+
+#include <stdio.h>
+
+#if defined(__ARMCC_VERSION) || defined(__ICCARM__)
+typedef int ssize_t;
+typedef long off_t;
+
+#else
+#   include <sys/types.h>
+#endif
+
+namespace mbed {
+
+/** An OO equivalent of the internal FILEHANDLE variable
+ *  and associated _sys_* functions.
+ *
+ * FileHandle is an abstract class, needing at least sys_write and
+ *  sys_read to be implmented for a simple interactive device.
+ *
+ * No one ever directly tals to/instanciates a FileHandle - it gets
+ *  created by FileSystem, and wrapped up by stdio.
+ */
+class FileHandle {
+
+public:
+    /** Write the contents of a buffer to the file
+     *
+     *  @param buffer the buffer to write from
+     *  @param length the number of characters to write
+     *
+     *  @returns
+     *  The number of characters written (possibly 0) on success, -1 on error.
+     */
+    virtual ssize_t write(const void* buffer, size_t length) = 0;
+
+    /** Close the file
+     *
+     *  @returns
+     *  Zero on success, -1 on error.
+     */
+    virtual int close() = 0;
+
+    /** Function read
+     *  Reads the contents of the file into a buffer
+     *
+     *  @param buffer the buffer to read in to
+     *  @param length the number of characters to read
+     *
+     *  @returns
+     *  The number of characters read (zero at end of file) on success, -1 on error.
+     */
+    virtual ssize_t read(void* buffer, size_t length) = 0;
+
+    /** Check if the handle is for a interactive terminal device.
+     * If so, line buffered behaviour is used by default
+     *
+     *  @returns
+     *    1 if it is a terminal,
+     *    0 otherwise
+     */
+    virtual int isatty() = 0;
+
+    /** Move the file position to a given offset from a given location.
+     *
+     *  @param offset The offset from whence to move to
+     *  @param whence SEEK_SET for the start of the file, SEEK_CUR for the
+     *   current file position, or SEEK_END for the end of the file.
+     *
+     *  @returns
+     *    new file position on success,
+     *    -1 on failure or unsupported
+     */
+    virtual off_t lseek(off_t offset, int whence) = 0;
+
+    /** Flush any buffers associated with the FileHandle, ensuring it
+     *  is up to date on disk
+     *
+     *  @returns
+     *    0 on success or un-needed,
+     *   -1 on error
+     */
+    virtual int fsync() = 0;
+
+    virtual off_t flen() {
+        /* remember our current position */
+        off_t pos = lseek(0, SEEK_CUR);
+        if(pos == -1) return -1;
+        /* seek to the end to get the file length */
+        off_t res = lseek(0, SEEK_END);
+        /* return to our old position */
+        lseek(pos, SEEK_SET);
+        return res;
+    }
+
+    virtual ~FileHandle();
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/FileLike.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILELIKE_H
+#define MBED_FILELIKE_H
+
+#include "FileBase.h"
+#include "FileHandle.h"
+
+namespace mbed {
+
+/* Class FileLike
+ *  A file-like object is one that can be opened with fopen by
+ *  fopen("/name", mode). It is intersection of the classes Base and
+ *  FileHandle.
+ */
+class FileLike : public FileHandle, public FileBase {
+
+public:
+    /* Constructor FileLike
+     *
+     * Variables
+     *  name - The name to use to open the file.
+     */
+    FileLike(const char *name);
+
+    virtual ~FileLike();
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/FilePath.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,46 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILEPATH_H
+#define MBED_FILEPATH_H
+
+#include "platform.h"
+
+#include "FileSystemLike.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+class FilePath {
+public:
+    FilePath(const char* file_path);
+
+    const char* fileName(void);
+
+    bool          isFileSystem(void);
+    FileSystemLike* fileSystem(void);
+
+    bool    isFile(void);
+    FileLike* file(void);
+    bool    exists(void);
+
+private:
+    const char* file_name;
+    FileBase* fb;
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/FileSystemLike.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FILESYSTEMLIKE_H
+#define MBED_FILESYSTEMLIKE_H
+
+#include "platform.h"
+
+#include "FileBase.h"
+#include "FileHandle.h"
+#include "DirHandle.h"
+
+namespace mbed {
+
+/** A filesystem-like object is one that can be used to open files
+ *  though it by fopen("/name/filename", mode)
+ *
+ *  Implementations must define at least open (the default definitions
+ *  of the rest of the functions just return error values).
+ */
+class FileSystemLike : public FileBase {
+
+public:
+    /** FileSystemLike constructor
+     *
+     *  @param name The name to use for the filesystem.
+     */
+    FileSystemLike(const char *name);
+
+    virtual ~FileSystemLike();
+
+    static DirHandle *opendir();
+    friend class BaseDirHandle;
+
+    /** Opens a file from the filesystem
+     *
+     *  @param filename The name of the file to open.
+     *  @param flags One of O_RDONLY, O_WRONLY, or O_RDWR, OR'd with
+     *    zero or more of O_CREAT, O_TRUNC, or O_APPEND.
+     *
+     *  @returns
+     *    A pointer to a FileHandle object representing the
+     *   file on success, or NULL on failure.
+     */
+    virtual FileHandle *open(const char *filename, int flags) = 0;
+
+    /** Remove a file from the filesystem.
+     *
+     *  @param filename the name of the file to remove.
+     *  @param returns 0 on success, -1 on failure.
+     */
+    virtual int remove(const char *filename) { return -1; };
+
+    /** Rename a file in the filesystem.
+     *
+     *  @param oldname the name of the file to rename.
+     *  @param newname the name to rename it to.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on failure.
+     */
+    virtual int rename(const char *oldname, const char *newname) { return -1; };
+
+    /** Opens a directory in the filesystem and returns a DirHandle
+     *   representing the directory stream.
+     *
+     *  @param name The name of the directory to open.
+     *
+     *  @returns
+     *    A DirHandle representing the directory stream, or
+     *   NULL on failure.
+     */
+    virtual DirHandle *opendir(const char *name) { return NULL; };
+
+    /** Creates a directory in the filesystem.
+     *
+     *  @param name The name of the directory to create.
+     *  @param mode The permissions to create the directory with.
+     *
+     *  @returns
+     *    0 on success,
+     *   -1 on failure.
+     */
+    virtual int mkdir(const char *name, mode_t mode) { return -1; }
+
+    // TODO other filesystem functions (mkdir, rm, rn, ls etc)
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/FunctionPointer.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,202 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_FUNCTIONPOINTER_H
+#define MBED_FUNCTIONPOINTER_H
+
+#include <string.h>
+#include <stdint.h>
+
+namespace mbed {
+
+/* If we had variaditic templates, this wouldn't be a problem, but until C++11 is enabled, we are stuck with multiple classes... */
+
+/** A class for storing and calling a pointer to a static or member function
+ */
+template <typename R, typename A1>
+class FunctionPointerArg1{
+public:
+    /** Create a FunctionPointer, attaching a static function
+     *
+     *  @param function The static function to attach (default is none)
+     */
+    FunctionPointerArg1(R (*function)(A1) = 0) {
+        attach(function);
+    }
+
+    /** Create a FunctionPointer, attaching a member function
+     *
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
+     *  @param function The address of the member function to attach
+     */
+    template<typename T>
+    FunctionPointerArg1(T *object, R (T::*member)(A1)) {
+        attach(object, member);
+    }
+
+    /** Attach a static function
+     *
+     *  @param function The static function to attach (default is none)
+     */
+    void attach(R (*function)(A1)) {
+        _p.function = function;
+        _membercaller = 0;
+    }
+
+    /** Attach a member function
+     *
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
+     *  @param function The address of the member function to attach
+     */
+    template<typename T>
+    void attach(T *object, R (T::*member)(A1)) {
+        _p.object = static_cast<void*>(object);
+        *reinterpret_cast<R (T::**)(A1)>(_member) = member;
+        _membercaller = &FunctionPointerArg1::membercaller<T>;
+    }
+
+    /** Call the attached static or member function
+     */
+    R call(A1 a) {
+        if (_membercaller == 0 && _p.function) {
+           return _p.function(a);
+        } else if (_membercaller && _p.object) {
+           return _membercaller(_p.object, _member, a);
+        }
+        return (R)0;
+    }
+
+    /** Get registered static function
+     */
+    R(*get_function(A1))() {
+        return _membercaller ? (R(*)(A1))0 : (R(*)(A1))_p.function;
+    }
+
+#ifdef MBED_OPERATORS
+    R operator ()(A1 a) {
+        return call(a);
+    }
+    operator bool(void) const {
+        return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL;
+    }
+#endif
+private:
+    template<typename T>
+    static R membercaller(void *object, uintptr_t *member, A1 a) {
+        T* o = static_cast<T*>(object);
+        R (T::**m)(A1) = reinterpret_cast<R (T::**)(A1)>(member);
+        return (o->**m)(a);
+    }
+
+    union {
+        R (*function)(A1); // static function pointer
+        void *object;      // object this pointer
+    } _p;
+    uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller
+    R (*_membercaller)(void*, uintptr_t*, A1); // registered membercaller function to convert back and call _m.member on _object
+};
+
+/** A class for storing and calling a pointer to a static or member function (R ()(void))
+ */
+template <typename R>
+class FunctionPointerArg1<R, void>{
+public:
+    /** Create a FunctionPointer, attaching a static function
+     *
+     *  @param function The static function to attach (default is none)
+     */
+    FunctionPointerArg1(R (*function)(void) = 0) {
+        attach(function);
+    }
+
+    /** Create a FunctionPointer, attaching a member function
+     *
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
+     *  @param function The address of the void member function to attach
+     */
+    template<typename T>
+    FunctionPointerArg1(T *object, R (T::*member)(void)) {
+        attach(object, member);
+    }
+
+    /** Attach a static function
+     *
+     *  @param function The void static function to attach (default is none)
+     */
+    void attach(R (*function)(void)) {
+        _p.function = function;
+        _membercaller = 0;
+    }
+
+    /** Attach a member function
+     *
+     *  @param object The object pointer to invoke the member function on (i.e. the this pointer)
+     *  @param function The address of the void member function to attach
+     */
+    template<typename T>
+    void attach(T *object, R (T::*member)(void)) {
+        _p.object = static_cast<void*>(object);
+        *reinterpret_cast<R (T::**)(void)>(_member) = member;
+        _membercaller = &FunctionPointerArg1::membercaller<T>;
+    }
+
+    /** Call the attached static or member function
+     */
+    R call(){
+        if (_membercaller == 0 && _p.function) {
+            return _p.function();
+        } else if (_membercaller && _p.object) {
+            return _membercaller(_p.object, _member);
+        }
+        return (R)0;
+    }
+
+    /** Get registered static function
+     */
+    R(*get_function())() {
+        return _membercaller ? (R(*)())0 : (R(*)())_p.function;
+    }
+
+#ifdef MBED_OPERATORS
+    R operator ()(void) {
+        return call();
+    }
+    operator bool(void) const {
+        return (_membercaller != NULL ? _p.object : (void*)_p.function) != NULL;
+    }
+#endif
+
+private:
+    template<typename T>
+    static R membercaller(void *object, uintptr_t *member) {
+        T* o = static_cast<T*>(object);
+        R (T::**m)(void) = reinterpret_cast<R (T::**)(void)>(member);
+        return (o->**m)();
+    }
+
+    union {
+        R (*function)(void); // static function pointer
+        void *object;        // object this pointer
+    } _p;
+    uintptr_t _member[4]; // aligned raw member function pointer storage - converted back by registered _membercaller
+    R (*_membercaller)(void*, uintptr_t*); // registered membercaller function to convert back and call _m.member on _object
+};
+
+typedef FunctionPointerArg1<void, void> FunctionPointer;
+typedef FunctionPointerArg1<void, int> event_callback_t;
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/I2C.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,176 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_H
+#define MBED_I2C_H
+
+#include "platform.h"
+
+#if DEVICE_I2C
+
+#include "i2c_api.h"
+
+#if DEVICE_I2C_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#include "FunctionPointer.h"
+#endif
+
+namespace mbed {
+
+/** An I2C Master, used for communicating with I2C slave devices
+ *
+ * Example:
+ * @code
+ * // Read from I2C slave at address 0x62
+ *
+ * #include "mbed.h"
+ *
+ * I2C i2c(p28, p27);
+ *
+ * int main() {
+ *     int address = 0x62;
+ *     char data[2];
+ *     i2c.read(address, data, 2);
+ * }
+ * @endcode
+ */
+class I2C {
+
+public:
+    enum RxStatus {
+        NoData,
+        MasterGeneralCall,
+        MasterWrite,
+        MasterRead
+    };
+
+    enum Acknowledge {
+        NoACK = 0,
+        ACK   = 1
+    };
+
+    /** Create an I2C Master interface, connected to the specified pins
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2C(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Read from an I2C slave
+     *
+     * Performs a complete read transaction. The bottom bit of
+     * the address is forced to 1 to indicate a read.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 1 ]
+     *  @param data Pointer to the byte-array to read data in to
+     *  @param length Number of bytes to read
+     *  @param repeated Repeated start, true - don't send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int read(int address, char *data, int length, bool repeated = false);
+
+    /** Read a single byte from the I2C bus
+     *
+     *  @param ack indicates if the byte is to be acknowledged (1 = acknowledge)
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(int ack);
+
+    /** Write to an I2C slave
+     *
+     * Performs a complete write transaction. The bottom bit of
+     * the address is forced to 0 to indicate a write.
+     *
+     *  @param address 8-bit I2C slave address [ addr | 0 ]
+     *  @param data Pointer to the byte-array data to send
+     *  @param length Number of bytes to send
+     *  @param repeated Repeated start, true - do not send stop at end
+     *
+     *  @returns
+     *       0 on success (ack),
+     *   non-0 on failure (nack)
+     */
+    int write(int address, const char *data, int length, bool repeated = false);
+
+    /** Write single byte out on the I2C bus
+     *
+     *  @param data data to write out on bus
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Creates a start condition on the I2C bus
+     */
+
+    void start(void);
+
+    /** Creates a stop condition on the I2C bus
+     */
+    void stop(void);
+
+#if DEVICE_I2C_ASYNCH
+
+    /** Start non-blocking I2C transfer.
+     *
+     * @param address   8/10 bit I2c slave address
+     * @param tx_buffer The TX buffer with data to be transfered
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data
+     * @param rx_length The length of RX buffer in bytes
+     * @param event     The logical OR of events to modify
+     * @param callback  The event callback function
+     * @param repeated Repeated start, true - do not send stop at end
+     * @return Zero if the transfer has started, or -1 if I2C peripheral is busy
+     */
+    int transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event = I2C_EVENT_TRANSFER_COMPLETE, bool repeated = false);
+
+    /** Abort the on-going I2C transfer
+     */
+    void abort_transfer();
+protected:
+    void irq_handler_asynch(void);
+    event_callback_t _callback;
+    CThunk<I2C> _irq;
+    DMAUsage _usage;
+#endif
+
+protected:
+    void aquire();
+
+    i2c_t _i2c;
+    static I2C  *_owner;
+    int         _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/I2CSlave.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,154 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_SLAVE_H
+#define MBED_I2C_SLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_I2CSLAVE
+
+#include "i2c_api.h"
+
+namespace mbed {
+
+/** An I2C Slave, used for communicating with an I2C Master device
+ *
+ * Example:
+ * @code
+ * // Simple I2C responder
+ * #include <mbed.h>
+ *
+ * I2CSlave slave(p9, p10);
+ *
+ * int main() {
+ *     char buf[10];
+ *     char msg[] = "Slave!";
+ *
+ *     slave.address(0xA0);
+ *     while (1) {
+ *         int i = slave.receive();
+ *         switch (i) {
+ *             case I2CSlave::ReadAddressed:
+ *                 slave.write(msg, strlen(msg) + 1); // Includes null char
+ *                 break;
+ *             case I2CSlave::WriteGeneral:
+ *                 slave.read(buf, 10);
+ *                 printf("Read G: %s\n", buf);
+ *                 break;
+ *             case I2CSlave::WriteAddressed:
+ *                 slave.read(buf, 10);
+ *                 printf("Read A: %s\n", buf);
+ *                 break;
+ *         }
+ *         for(int i = 0; i < 10; i++) buf[i] = 0;    // Clear buffer
+ *     }
+ * }
+ * @endcode
+ */
+class I2CSlave {
+
+public:
+    enum RxStatus {
+        NoData         = 0,
+        ReadAddressed  = 1,
+        WriteGeneral   = 2,
+        WriteAddressed = 3
+    };
+
+    /** Create an I2C Slave interface, connected to the specified pins.
+     *
+     *  @param sda I2C data line pin
+     *  @param scl I2C clock line pin
+     */
+    I2CSlave(PinName sda, PinName scl);
+
+    /** Set the frequency of the I2C interface
+     *
+     *  @param hz The bus frequency in hertz
+     */
+    void frequency(int hz);
+
+    /** Checks to see if this I2C Slave has been addressed.
+     *
+     *  @returns
+     *  A status indicating if the device has been addressed, and how
+     *  - NoData            - the slave has not been addressed
+     *  - ReadAddressed     - the master has requested a read from this slave
+     *  - WriteAddressed    - the master is writing to this slave
+     *  - WriteGeneral      - the master is writing to all slave
+     */
+    int receive(void);
+
+    /** Read from an I2C master.
+     *
+     *  @param data pointer to the byte array to read data in to
+     *  @param length maximum number of bytes to read
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int read(char *data, int length);
+
+    /** Read a single byte from an I2C master.
+     *
+     *  @returns
+     *    the byte read
+     */
+    int read(void);
+
+    /** Write to an I2C master.
+     *
+     *  @param data pointer to the byte array to be transmitted
+     *  @param length the number of bytes to transmite
+     *
+     *  @returns
+     *       0 on success,
+     *   non-0 otherwise
+     */
+    int write(const char *data, int length);
+
+    /** Write a single byte to an I2C master.
+     *
+     *  @data the byte to write
+     *
+     *  @returns
+     *    '1' if an ACK was received,
+     *    '0' otherwise
+     */
+    int write(int data);
+
+    /** Sets the I2C slave address.
+     *
+     *  @param address The address to set for the slave (ignoring the least
+     *  signifcant bit). If set to 0, the slave will only respond to the
+     *  general call address.
+     */
+    void address(int address);
+
+    /** Reset the I2C slave back into the known ready receiving state.
+     */
+    void stop(void);
+
+protected:
+    i2c_t _i2c;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/InterruptIn.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERRUPTIN_H
+#define MBED_INTERRUPTIN_H
+
+#include "platform.h"
+
+#if DEVICE_INTERRUPTIN
+
+#include "gpio_api.h"
+#include "gpio_irq_api.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A digital interrupt input, used to call a function on a rising or falling edge
+ *
+ * Example:
+ * @code
+ * // Flash an LED while waiting for events
+ *
+ * #include "mbed.h"
+ *
+ * InterruptIn event(p16);
+ * DigitalOut led(LED1);
+ *
+ * void trigger() {
+ *     printf("triggered!\n");
+ * }
+ *
+ * int main() {
+ *     event.rise(&trigger);
+ *     while(1) {
+ *         led = !led;
+ *         wait(0.25);
+ *     }
+ * }
+ * @endcode
+ */
+class InterruptIn {
+
+public:
+
+    /** Create an InterruptIn connected to the specified pin
+     *
+     *  @param pin InterruptIn pin to connect to
+     *  @param name (optional) A string to identify the object
+     */
+    InterruptIn(PinName pin);
+    virtual ~InterruptIn();
+
+     int read();
+#ifdef MBED_OPERATORS
+    operator int();
+
+#endif
+
+    /** Attach a function to call when a rising edge occurs on the input
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     */
+    void rise(void (*fptr)(void));
+
+    /** Attach a member function to call when a rising edge occurs on the input
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    void rise(T* tptr, void (T::*mptr)(void)) {
+        _rise.attach(tptr, mptr);
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+    }
+
+    /** Attach a function to call when a falling edge occurs on the input
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     */
+    void fall(void (*fptr)(void));
+
+    /** Attach a member function to call when a falling edge occurs on the input
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     */
+    template<typename T>
+    void fall(T* tptr, void (T::*mptr)(void)) {
+        _fall.attach(tptr, mptr);
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone
+     */
+    void mode(PinMode pull);
+
+    /** Enable IRQ. This method depends on hw implementation, might enable one
+     *  port interrupts. For further information, check gpio_irq_enable().
+     */
+    void enable_irq();
+
+    /** Disable IRQ. This method depends on hw implementation, might disable one
+     *  port interrupts. For further information, check gpio_irq_disable().
+     */
+    void disable_irq();
+
+    static void _irq_handler(uint32_t id, gpio_irq_event event);
+
+protected:
+    gpio_t gpio;
+    gpio_irq_t gpio_irq;
+
+    FunctionPointer _rise;
+    FunctionPointer _fall;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/InterruptManager.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,143 @@
+#ifndef MBED_INTERRUPTMANAGER_H
+#define MBED_INTERRUPTMANAGER_H
+
+#include "cmsis.h"
+#include "CallChain.h"
+#include <string.h>
+
+namespace mbed {
+
+/** Use this singleton if you need to chain interrupt handlers.
+ *
+ * Example (for LPC1768):
+ * @code
+ * #include "InterruptManager.h"
+ * #include "mbed.h"
+ *
+ * Ticker flipper;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * void flip(void) {
+ *     led1 = !led1;
+ * }
+ *
+ * void handler(void) {
+ *     led2 = !led1;
+ * }
+ *
+ * int main() {
+ *     led1 = led2 = 0;
+ *     flipper.attach(&flip, 1.0);
+ *     InterruptManager::get()->add_handler(handler, TIMER3_IRQn);
+ * }
+ * @endcode
+ */
+class InterruptManager {
+public:
+    /** Return the only instance of this class
+     */
+    static InterruptManager* get();
+
+    /** Destroy the current instance of the interrupt manager
+     */
+    static void destroy();
+
+    /** Add a handler for an interrupt at the end of the handler list
+     *
+     *  @param function the handler to add
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_handler(void (*function)(void), IRQn_Type irq) {
+        return add_common(function, irq);
+    }
+
+    /** Add a handler for an interrupt at the beginning of the handler list
+     *
+     *  @param function the handler to add
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'function'
+     */
+    pFunctionPointer_t add_handler_front(void (*function)(void), IRQn_Type irq) {
+        return add_common(function, irq, true);
+    }
+
+    /** Add a handler for an interrupt at the end of the handler list
+     *
+     *  @param tptr pointer to the object that has the handler function
+     *  @param mptr pointer to the actual handler function
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_handler(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+        return add_common(tptr, mptr, irq);
+    }
+
+    /** Add a handler for an interrupt at the beginning of the handler list
+     *
+     *  @param tptr pointer to the object that has the handler function
+     *  @param mptr pointer to the actual handler function
+     *  @param irq interrupt number
+     *
+     *  @returns
+     *  The function object created for 'tptr' and 'mptr'
+     */
+    template<typename T>
+    pFunctionPointer_t add_handler_front(T* tptr, void (T::*mptr)(void), IRQn_Type irq) {
+        return add_common(tptr, mptr, irq, true);
+    }
+
+    /** Remove a handler from an interrupt
+     *
+     *  @param handler the function object for the handler to remove
+     *  @param irq the interrupt number
+     *
+     *  @returns
+     *  true if the handler was found and removed, false otherwise
+     */
+    bool remove_handler(pFunctionPointer_t handler, IRQn_Type irq);
+
+private:
+    InterruptManager();
+    ~InterruptManager();
+
+    // We declare the copy contructor and the assignment operator, but we don't
+    // implement them. This way, if someone tries to copy/assign our instance,
+    // he will get an error at compile time.
+    InterruptManager(const InterruptManager&);
+    InterruptManager& operator =(const InterruptManager&);
+
+    template<typename T>
+    pFunctionPointer_t add_common(T *tptr, void (T::*mptr)(void), IRQn_Type irq, bool front=false) {
+        int irq_pos = get_irq_index(irq);
+        bool change = must_replace_vector(irq);
+
+        pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(tptr, mptr) : _chains[irq_pos]->add(tptr, mptr);
+        if (change)
+            NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+        return pf;
+    }
+
+    pFunctionPointer_t add_common(void (*function)(void), IRQn_Type irq, bool front=false);
+    bool must_replace_vector(IRQn_Type irq);
+    int get_irq_index(IRQn_Type irq);
+    void irq_helper();
+    void add_helper(void (*function)(void), IRQn_Type irq, bool front=false);
+    static void static_irq_helper();
+
+    CallChain* _chains[NVIC_NUM_VECTORS];
+    static InterruptManager* _instance;
+};
+
+} // namespace mbed
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/LocalFileSystem.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOCALFILESYSTEM_H
+#define MBED_LOCALFILESYSTEM_H
+
+#include "platform.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+FILEHANDLE local_file_open(const char* name, int flags);
+
+class LocalFileHandle : public FileHandle {
+
+public:
+    LocalFileHandle(FILEHANDLE fh);
+
+    virtual int close();
+
+    virtual ssize_t write(const void *buffer, size_t length);
+
+    virtual ssize_t read(void *buffer, size_t length);
+
+    virtual int isatty();
+
+    virtual off_t lseek(off_t position, int whence);
+
+    virtual int fsync();
+
+    virtual off_t flen();
+
+protected:
+    FILEHANDLE _fh;
+    int pos;
+};
+
+/** A filesystem for accessing the local mbed Microcontroller USB disk drive
+ *
+ *  This allows programs to read and write files on the same disk drive that is used to program the
+ *  mbed Microcontroller. Once created, the standard C file access functions are used to open,
+ *  read and write files.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * LocalFileSystem local("local");               // Create the local filesystem under the name "local"
+ *
+ * int main() {
+ *     FILE *fp = fopen("/local/out.txt", "w");  // Open "out.txt" on the local file system for writing
+ *     fprintf(fp, "Hello World!");
+ *     fclose(fp);
+ *     remove("/local/out.txt");                 // Removes the file "out.txt" from the local file system
+ *
+ *     DIR *d = opendir("/local");               // Opens the root directory of the local file system
+ *     struct dirent *p;
+ *     while((p = readdir(d)) != NULL) {         // Print the names of the files in the local file system
+ *       printf("%s\n", p->d_name);              // to stdout.
+ *     }
+ *     closedir(d);
+ * }
+ * @endcode
+ *
+ * @note
+ *  If the microcontroller program makes an access to the local drive, it will be marked as "removed"
+ *  on the Host computer. This means it is no longer accessible from the Host Computer.
+ *
+ *  The drive will only re-appear when the microcontroller program exists. Note that if the program does
+ *  not exit, you will need to hold down reset on the mbed Microcontroller to be able to see the drive again!
+ */
+class LocalFileSystem : public FileSystemLike {
+
+public:
+    LocalFileSystem(const char* n) : FileSystemLike(n) {
+
+    }
+
+    virtual FileHandle *open(const char* name, int flags);
+    virtual int remove(const char *filename);
+    virtual DirHandle *opendir(const char *name);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/LowPowerTicker.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,44 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTICKER_H
+#define MBED_LOWPOWERTICKER_H
+
+#include "platform.h"
+#include "Ticker.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+
+namespace mbed {
+
+/** Low Power Ticker
+ */
+class LowPowerTicker : public Ticker {
+
+public:
+    LowPowerTicker() : Ticker(get_lp_ticker_data()) {
+    }
+
+    virtual ~LowPowerTicker() {
+    }
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/LowPowerTimeout.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMEOUT_H
+#define MBED_LOWPOWERTIMEOUT_H
+
+#include "platform.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+#include "LowPowerTicker.h"
+
+namespace mbed {
+
+/** Low Power Timout
+ */
+class LowPowerTimeout : public LowPowerTicker {
+
+private:
+    virtual void handler(void) {
+        _function.call();
+    }
+};
+
+}
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/LowPowerTimer.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LOWPOWERTIMER_H
+#define MBED_LOWPOWERTIMER_H
+
+#include "platform.h"
+#include "Timer.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "lp_ticker_api.h"
+
+namespace mbed {
+
+/** Low power timer
+ */
+class LowPowerTimer : public Timer {
+
+public:
+    LowPowerTimer() : Timer(get_lp_ticker_data()) {
+    }
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/PortIn.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTIN_H
+#define MBED_PORTIN_H
+
+#include "platform.h"
+
+#if DEVICE_PORTIN
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital input
+ *
+ *  Example:
+ * @code
+ * // Switch on an LED if any of mbed pins 21-26 is high
+ *
+ * #include "mbed.h"
+ *
+ * PortIn     p(Port2, 0x0000003F);   // p21-p26
+ * DigitalOut ind(LED4);
+ *
+ * int main() {
+ *     while(1) {
+ *         int pins = p.read();
+ *         if(pins) {
+ *             ind = 1;
+ *         } else {
+ *             ind = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class PortIn {
+public:
+
+    /** Create an PortIn, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+        */
+    PortIn(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_INPUT);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        port_mode(&_port, mode);
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/PortInOut.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTINOUT_H
+#define MBED_PORTINOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTINOUT
+
+#include "port_api.h"
+
+namespace mbed {
+
+/** A multiple pin digital in/out used to set/read multiple bi-directional pins
+ */
+class PortInOut {
+public:
+
+    /** Create an PortInOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortInOut(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_INPUT);
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding port pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated port pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** Set as an output
+     */
+    void output() {
+        port_dir(&_port, PIN_OUTPUT);
+    }
+
+    /** Set as an input
+     */
+    void input() {
+        port_dir(&_port, PIN_INPUT);
+    }
+
+    /** Set the input pin mode
+     *
+     *  @param mode PullUp, PullDown, PullNone, OpenDrain
+     */
+    void mode(PinMode mode) {
+        port_mode(&_port, mode);
+    }
+
+    /** A shorthand for write()
+     */
+    PortInOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    PortInOut& operator= (PortInOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/PortOut.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,104 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTOUT_H
+#define MBED_PORTOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PORTOUT
+
+#include "port_api.h"
+
+namespace mbed {
+/** A multiple pin digital out
+ *
+ * Example:
+ * @code
+ * // Toggle all four LEDs
+ *
+ * #include "mbed.h"
+ *
+ * // LED1 = P1.18  LED2 = P1.20  LED3 = P1.21  LED4 = P1.23
+ * #define LED_MASK 0x00B40000
+ *
+ * PortOut ledport(Port1, LED_MASK);
+ *
+ * int main() {
+ *     while(1) {
+ *         ledport = LED_MASK;
+ *         wait(1);
+ *         ledport = 0;
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+class PortOut {
+public:
+
+    /** Create an PortOut, connected to the specified port
+     *
+     *  @param port Port to connect to (Port0-Port5)
+     *  @param mask A bitmask to identify which bits in the port should be included (0 - ignore)
+     */
+    PortOut(PortName port, int mask = 0xFFFFFFFF) {
+        port_init(&_port, port, mask, PIN_OUTPUT);
+    }
+
+    /** Write the value to the output port
+     *
+     *  @param value An integer specifying a bit to write for every corresponding PortOut pin
+     */
+    void write(int value) {
+        port_write(&_port, value);
+    }
+
+    /** Read the value currently output on the port
+     *
+     *  @returns
+     *    An integer with each bit corresponding to associated PortOut pin setting
+     */
+    int read() {
+        return port_read(&_port);
+    }
+
+    /** A shorthand for write()
+     */
+    PortOut& operator= (int value) {
+        write(value);
+        return *this;
+    }
+
+    PortOut& operator= (PortOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** A shorthand for read()
+     */
+    operator int() {
+        return read();
+    }
+
+private:
+    port_t _port;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/PwmOut.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,158 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_H
+#define MBED_PWMOUT_H
+
+#include "platform.h"
+
+#if DEVICE_PWMOUT
+#include "pwmout_api.h"
+
+namespace mbed {
+
+/** A pulse-width modulation digital output
+ *
+ * Example
+ * @code
+ * // Fade a led on.
+ * #include "mbed.h"
+ *
+ * PwmOut led(LED1);
+ *
+ * int main() {
+ *     while(1) {
+ *         led = led + 0.01;
+ *         wait(0.2);
+ *         if(led == 1.0) {
+ *             led = 0;
+ *         }
+ *     }
+ * }
+ * @endcode
+ *
+ * @note
+ *  On the LPC1768 and LPC2368, the PWMs all share the same
+ *  period - if you change the period for one, you change it for all.
+ *  Although routines that change the period maintain the duty cycle
+ *  for its PWM, all other PWMs will require their duty cycle to be
+ *  refreshed.
+ */
+class PwmOut {
+
+public:
+
+    /** Create a PwmOut connected to the specified pin
+     *
+     *  @param pin PwmOut pin to connect to
+     */
+    PwmOut(PinName pin) {
+        pwmout_init(&_pwm, pin);
+    }
+
+    /** Set the ouput duty-cycle, specified as a percentage (float)
+     *
+     *  @param value A floating-point value representing the output duty-cycle,
+     *    specified as a percentage. The value should lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *    Values outside this range will be saturated to 0.0f or 1.0f.
+     */
+    void write(float value) {
+        pwmout_write(&_pwm, value);
+    }
+
+    /** Return the current output duty-cycle setting, measured as a percentage (float)
+     *
+     *  @returns
+     *    A floating-point value representing the current duty-cycle being output on the pin,
+     *    measured as a percentage. The returned value will lie between
+     *    0.0f (representing on 0%) and 1.0f (representing on 100%).
+     *
+     *  @note
+     *  This value may not match exactly the value set by a previous <write>.
+     */
+    float read() {
+        return pwmout_read(&_pwm);
+    }
+
+    /** Set the PWM period, specified in seconds (float), keeping the duty cycle the same.
+     *
+     *  @note
+     *   The resolution is currently in microseconds; periods smaller than this
+     *   will be set to zero.
+     */
+    void period(float seconds) {
+        pwmout_period(&_pwm, seconds);
+    }
+
+    /** Set the PWM period, specified in milli-seconds (int), keeping the duty cycle the same.
+     */
+    void period_ms(int ms) {
+        pwmout_period_ms(&_pwm, ms);
+    }
+
+    /** Set the PWM period, specified in micro-seconds (int), keeping the duty cycle the same.
+     */
+    void period_us(int us) {
+        pwmout_period_us(&_pwm, us);
+    }
+
+    /** Set the PWM pulsewidth, specified in seconds (float), keeping the period the same.
+     */
+    void pulsewidth(float seconds) {
+        pwmout_pulsewidth(&_pwm, seconds);
+    }
+
+    /** Set the PWM pulsewidth, specified in milli-seconds (int), keeping the period the same.
+     */
+    void pulsewidth_ms(int ms) {
+        pwmout_pulsewidth_ms(&_pwm, ms);
+    }
+
+    /** Set the PWM pulsewidth, specified in micro-seconds (int), keeping the period the same.
+     */
+    void pulsewidth_us(int us) {
+        pwmout_pulsewidth_us(&_pwm, us);
+    }
+
+#ifdef MBED_OPERATORS
+    /** A operator shorthand for write()
+     */
+    PwmOut& operator= (float value) {
+        write(value);
+        return *this;
+    }
+
+    PwmOut& operator= (PwmOut& rhs) {
+        write(rhs.read());
+        return *this;
+    }
+
+    /** An operator shorthand for read()
+     */
+    operator float() {
+        return read();
+    }
+#endif
+
+protected:
+    pwmout_t _pwm;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/RawSerial.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,90 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RAW_SERIAL_H
+#define MBED_RAW_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ * This is a variation of the Serial class that doesn't use streams,
+ * thus making it safe to use in interrupt handlers with the RTOS.
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Send a char to the PC
+ *
+ * #include "mbed.h"
+ *
+ * RawSerial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.putc('A');
+ * }
+ * @endcode
+ */
+class RawSerial: public SerialBase {
+
+public:
+    /** Create a RawSerial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    RawSerial(PinName tx, PinName rx);
+
+    /** Write a char to the serial port
+     *
+     * @param c The char to write
+     *
+     * @returns The written char or -1 if an error occured
+     */
+    int putc(int c);
+
+    /** Read a char from the serial port
+     *
+     * @returns The char read from the serial port
+     */
+    int getc();
+
+    /** Write a string to the serial port
+     *
+     * @param str The string to write
+     *
+     * @returns 0 if the write succeeds, EOF for error
+     */
+    int puts(const char *str);
+
+    int printf(const char *format, ...);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/SPI.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,245 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_H
+#define MBED_SPI_H
+
+#include "platform.h"
+
+#if DEVICE_SPI
+
+#include "spi_api.h"
+
+#if DEVICE_SPI_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#include "CircularBuffer.h"
+#include "FunctionPointer.h"
+#include "Transaction.h"
+#endif
+
+namespace mbed {
+
+/** A SPI Master, used for communicating with SPI slave devices
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Most SPI devices will also require Chip Select and Reset signals. These
+ * can be controlled using <DigitalOut> pins
+ *
+ * Example:
+ * @code
+ * // Send a byte to a SPI slave, and record the response
+ *
+ * #include "mbed.h"
+ *
+ * // hardware ssel (where applicable)
+ * //SPI device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * // software ssel
+ * SPI device(p5, p6, p7); // mosi, miso, sclk
+ * DigitalOut cs(p8); // ssel
+ *
+ * int main() {
+ *     // hardware ssel (where applicable)
+ *     //int response = device.write(0xFF);
+ *
+ *     // software ssel
+ *     cs = 0;
+ *     int response = device.write(0xFF);
+ *     cs = 1;
+ * }
+ * @endcode
+ */
+class SPI {
+
+public:
+
+    /** Create a SPI master connected to the specified pins
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     *  @param ssel SPI chip select pin
+     */
+    SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel=NC);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Write to the SPI Slave and return the response
+     *
+     *  @param value Data to be sent to the SPI slave
+     *
+     *  @returns
+     *    Response from the SPI slave
+    */
+    virtual int write(int value);
+
+#if DEVICE_SPI_ASYNCH
+
+    /** Start non-blocking SPI transfer using 8bit buffers.
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify. Look at spi hal header file for SPI events.
+     * @return Zero if the transfer has started, or -1 if SPI peripheral is busy
+     */
+    template<typename Type>
+    int transfer(const Type *tx_buffer, int tx_length, Type *rx_buffer, int rx_length, const event_callback_t& callback, int event = SPI_EVENT_COMPLETE) {
+        if (spi_active(&_spi)) {
+            return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
+        }
+        start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, sizeof(Type)*8, callback, event);
+        return 0;
+    }
+
+    /** Abort the on-going SPI transfer, and continue with transfer's in the queue if any.
+     */
+    void abort_transfer();
+
+    /** Clear the transaction buffer
+     */
+    void clear_transfer_buffer();
+
+    /** Clear the transaction buffer and abort on-going transfer.
+     */
+    void abort_all_transfers();
+
+    /** Configure DMA usage suggestion for non-blocking transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+    */
+    int set_dma_usage(DMAUsage usage);
+
+protected:
+    /** SPI IRQ handler
+     *
+    */
+    void irq_handler_asynch(void);
+
+    /** Common transfer method
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+     * @return Zero if the transfer has started or was added to the queue, or -1 if SPI peripheral is busy/buffer is full
+    */
+    int transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+    /**
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+     * @return Zero if a transfer was added to the queue, or -1 if the queue is full
+    */
+    int queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+    /** Configures a callback, spi peripheral and initiate a new transfer
+     *
+     * @param tx_buffer The TX buffer with data to be transfered. If NULL is passed,
+     *                  the default SPI value is sent
+     * @param tx_length The length of TX buffer in bytes
+     * @param rx_buffer The RX buffer which is used for received data. If NULL is passed,
+     *                  received data are ignored
+     * @param rx_length The length of RX buffer in bytes
+     * @param bit_width The buffers element width
+     * @param callback  The event callback function
+     * @param event     The logical OR of events to modify
+    */
+    void start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event);
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+    /** Start a new transaction
+     *
+     *  @param data Transaction data
+    */
+    void start_transaction(transaction_t *data);
+
+    /** Dequeue a transaction
+     *
+    */
+    void dequeue_transaction();
+    static CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> _transaction_buffer;
+#endif
+
+#endif
+
+public:
+    virtual ~SPI() {
+    }
+
+protected:
+    spi_t _spi;
+
+#if DEVICE_SPI_ASYNCH
+    CThunk<SPI> _irq;
+    event_callback_t _callback;
+    DMAUsage _usage;
+#endif
+
+    void aquire(void);
+    static SPI *_owner;
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/SPISlave.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,122 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPISLAVE_H
+#define MBED_SPISLAVE_H
+
+#include "platform.h"
+
+#if DEVICE_SPISLAVE
+
+#include "spi_api.h"
+
+namespace mbed {
+
+/** A SPI slave, used for communicating with a SPI Master device
+ *
+ * The default format is set to 8-bits, mode 0, and a clock frequency of 1MHz
+ *
+ * Example:
+ * @code
+ * // Reply to a SPI master as slave
+ *
+ * #include "mbed.h"
+ *
+ * SPISlave device(p5, p6, p7, p8); // mosi, miso, sclk, ssel
+ *
+ * int main() {
+ *     device.reply(0x00);              // Prime SPI with first reply
+ *     while(1) {
+ *         if(device.receive()) {
+ *             int v = device.read();   // Read byte from master
+ *             v = (v + 1) % 0x100;     // Add one to it, modulo 256
+ *             device.reply(v);         // Make this the next reply
+ *         }
+ *     }
+ * }
+ * @endcode
+ */
+class SPISlave {
+
+public:
+
+    /** Create a SPI slave connected to the specified pins
+     *
+     *  mosi or miso can be specfied as NC if not used
+     *
+     *  @param mosi SPI Master Out, Slave In pin
+     *  @param miso SPI Master In, Slave Out pin
+     *  @param sclk SPI Clock pin
+     *  @param ssel SPI chip select pin
+     */
+    SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+    /** Configure the data transmission format
+     *
+     *  @param bits Number of bits per SPI frame (4 - 16)
+     *  @param mode Clock polarity and phase mode (0 - 3)
+     *
+     * @code
+     * mode | POL PHA
+     * -----+--------
+     *   0  |  0   0
+     *   1  |  0   1
+     *   2  |  1   0
+     *   3  |  1   1
+     * @endcode
+     */
+    void format(int bits, int mode = 0);
+
+    /** Set the spi bus clock frequency
+     *
+     *  @param hz SCLK frequency in hz (default = 1MHz)
+     */
+    void frequency(int hz = 1000000);
+
+    /** Polls the SPI to see if data has been received
+     *
+     *  @returns
+     *    0 if no data,
+     *    1 otherwise
+     */
+    int receive(void);
+
+    /** Retrieve  data from receive buffer as slave
+     *
+     *  @returns
+     *    the data in the receive buffer
+     */
+    int read(void);
+
+    /** Fill the transmission buffer with the value to be written out
+     *  as slave on the next received message from the master.
+     *
+     *  @param value the data to be transmitted next
+     */
+    void reply(int value);
+
+protected:
+    spi_t _spi;
+
+    int _bits;
+    int _mode;
+    int _hz;
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/Serial.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,74 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_H
+#define MBED_SERIAL_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "SerialBase.h"
+#include "serial_api.h"
+
+namespace mbed {
+
+/** A serial port (UART) for communication with other serial devices
+ *
+ * Can be used for Full Duplex communication, or Simplex by specifying
+ * one pin as NC (Not Connected)
+ *
+ * Example:
+ * @code
+ * // Print "Hello World" to the PC
+ *
+ * #include "mbed.h"
+ *
+ * Serial pc(USBTX, USBRX);
+ *
+ * int main() {
+ *     pc.printf("Hello World\n");
+ * }
+ * @endcode
+ */
+class Serial : public SerialBase, public Stream {
+
+public:
+#if DEVICE_SERIAL_ASYNCH
+    using SerialBase::read;
+    using SerialBase::write;
+#endif
+
+    /** Create a Serial port, connected to the specified transmit and receive pins
+     *
+     *  @param tx Transmit pin
+     *  @param rx Receive pin
+     *
+     *  @note
+     *    Either tx or rx may be specified as NC if unused
+     */
+    Serial(PinName tx, PinName rx, const char *name=NULL);
+
+protected:
+    virtual int _getc();
+    virtual int _putc(int c);
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/SerialBase.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,223 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIALBASE_H
+#define MBED_SERIALBASE_H
+
+#include "platform.h"
+
+#if DEVICE_SERIAL
+
+#include "Stream.h"
+#include "FunctionPointer.h"
+#include "serial_api.h"
+
+#if DEVICE_SERIAL_ASYNCH
+#include "CThunk.h"
+#include "dma_api.h"
+#endif
+
+namespace mbed {
+
+/** A base class for serial port implementations
+ * Can't be instantiated directly (use Serial or RawSerial)
+ */
+class SerialBase {
+
+public:
+    /** Set the baud rate of the serial port
+     *
+     *  @param baudrate The baudrate of the serial port (default = 9600).
+     */
+    void baud(int baudrate);
+
+    enum Parity {
+        None = 0,
+        Odd,
+        Even,
+        Forced1,
+        Forced0
+    };
+
+    enum IrqType {
+        RxIrq = 0,
+        TxIrq
+    };
+
+    enum Flow {
+        Disabled = 0,
+        RTS,
+        CTS,
+        RTSCTS
+    };
+
+    /** Set the transmission format used by the serial port
+     *
+     *  @param bits The number of bits in a word (5-8; default = 8)
+     *  @param parity The parity used (SerialBase::None, SerialBase::Odd, SerialBase::Even, SerialBase::Forced1, SerialBase::Forced0; default = SerialBase::None)
+     *  @param stop The number of stop bits (1 or 2; default = 1)
+     */
+    void format(int bits=8, Parity parity=SerialBase::None, int stop_bits=1);
+
+    /** Determine if there is a character available to read
+     *
+     *  @returns
+     *    1 if there is a character available to read,
+     *    0 otherwise
+     */
+    int readable();
+
+    /** Determine if there is space available to write a character
+     *
+     *  @returns
+     *    1 if there is space to write a character,
+     *    0 otherwise
+     */
+    int writeable();
+
+    /** Attach a function to call whenever a serial interrupt is generated
+     *
+     *  @param fptr A pointer to a void function, or 0 to set as none
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    void attach(void (*fptr)(void), IrqType type=RxIrq);
+
+    /** Attach a member function to call whenever a serial interrupt is generated
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param type Which serial interrupt to attach the member function to (Seriall::RxIrq for receive, TxIrq for transmit buffer empty)
+     */
+    template<typename T>
+    void attach(T* tptr, void (T::*mptr)(void), IrqType type=RxIrq) {
+        if((mptr != NULL) && (tptr != NULL)) {
+            _irq[type].attach(tptr, mptr);
+            serial_irq_set(&_serial, (SerialIrq)type, 1);
+        } else {
+            serial_irq_set(&_serial, (SerialIrq)type, 0);
+        }
+    }
+
+    /** Generate a break condition on the serial line
+     */
+    void send_break();
+
+#if DEVICE_SERIAL_FC
+    /** Set the flow control type on the serial port
+     *
+     *  @param type the flow control type (Disabled, RTS, CTS, RTSCTS)
+     *  @param flow1 the first flow control pin (RTS for RTS or RTSCTS, CTS for CTS)
+     *  @param flow2 the second flow control pin (CTS for RTSCTS)
+     */
+    void set_flow_control(Flow type, PinName flow1=NC, PinName flow2=NC);
+#endif
+
+    static void _irq_handler(uint32_t id, SerialIrq irq_type);
+
+#if DEVICE_SERIAL_ASYNCH
+
+    /** Begin asynchronous write using 8bit buffer. The completition invokes registered TX event callback
+     *
+     *  @param buffer   The buffer where received data will be stored
+     *  @param length   The buffer length in bytes
+     *  @param callback The event callback function
+     *  @param event    The logical OR of TX events
+     */
+    int write(const uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+    /** Begin asynchronous write using 16bit buffer. The completition invokes registered TX event callback
+     *
+     *  @param buffer   The buffer where received data will be stored
+     *  @param length   The buffer length in bytes
+     *  @param callback The event callback function
+     *  @param event    The logical OR of TX events
+     */
+    int write(const uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_TX_COMPLETE);
+
+    /** Abort the on-going write transfer
+     */
+    void abort_write();
+
+    /** Begin asynchronous reading using 8bit buffer. The completition invokes registred RX event callback.
+     *
+     *  @param buffer     The buffer where received data will be stored
+     *  @param length     The buffer length in bytes
+     *  @param callback   The event callback function
+     *  @param event      The logical OR of RX events
+     *  @param char_match The matching character
+     */
+    int read(uint8_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+    /** Begin asynchronous reading using 16bit buffer. The completition invokes registred RX event callback.
+     *
+     *  @param buffer     The buffer where received data will be stored
+     *  @param length     The buffer length in bytes
+     *  @param callback   The event callback function
+     *  @param event      The logical OR of RX events
+     *  @param char_match The matching character
+     */
+    int read(uint16_t *buffer, int length, const event_callback_t& callback, int event = SERIAL_EVENT_RX_COMPLETE, unsigned char char_match = SERIAL_RESERVED_CHAR_MATCH);
+
+    /** Abort the on-going read transfer
+     */
+    void abort_read();
+
+    /** Configure DMA usage suggestion for non-blocking TX transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+     */
+    int set_dma_usage_tx(DMAUsage usage);
+
+    /** Configure DMA usage suggestion for non-blocking RX transfers
+     *
+     *  @param usage The usage DMA hint for peripheral
+     *  @return Zero if the usage was set, -1 if a transaction is on-going
+     */
+    int set_dma_usage_rx(DMAUsage usage);
+
+protected:
+    void start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match);
+    void start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event);
+    void interrupt_handler_asynch(void);
+#endif
+
+protected:
+    SerialBase(PinName tx, PinName rx);
+    virtual ~SerialBase() {
+    }
+
+    int _base_getc();
+    int _base_putc(int c);
+
+#if DEVICE_SERIAL_ASYNCH
+    CThunk<SerialBase> _thunk_irq;
+    event_callback_t _tx_callback;
+    event_callback_t _rx_callback;
+    DMAUsage _tx_usage;
+    DMAUsage _rx_usage;
+#endif
+
+    serial_t        _serial;
+    FunctionPointer _irq[2];
+    int             _baud;
+
+};
+
+} // namespace mbed
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/Stream.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,65 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_STREAM_H
+#define MBED_STREAM_H
+
+#include "platform.h"
+#include "FileLike.h"
+
+namespace mbed {
+
+extern void mbed_set_unbuffered_stream(FILE *_file);
+extern int mbed_getc(FILE *_file);
+extern char* mbed_gets(char *s, int size, FILE *_file);
+
+class Stream : public FileLike {
+
+public:
+    Stream(const char *name=NULL);
+    virtual ~Stream();
+
+    int putc(int c);
+    int puts(const char *s);
+    int getc();
+    char *gets(char *s, int size);
+    int printf(const char* format, ...);
+    int scanf(const char* format, ...);
+
+    operator std::FILE*() {return _file;}
+
+protected:
+    virtual int close();
+    virtual ssize_t write(const void* buffer, size_t length);
+    virtual ssize_t read(void* buffer, size_t length);
+    virtual off_t lseek(off_t offset, int whence);
+    virtual int isatty();
+    virtual int fsync();
+    virtual off_t flen();
+
+    virtual int _putc(int c) = 0;
+    virtual int _getc() = 0;
+
+    std::FILE *_file;
+
+    /* disallow copy constructor and assignment operators */
+private:
+    Stream(const Stream&);
+    Stream & operator = (const Stream&);
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/Ticker.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,127 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_H
+#define MBED_TICKER_H
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** A Ticker is used to call a function at a recurring interval
+ *
+ *  You can use as many seperate Ticker objects as you require.
+ *
+ * Example:
+ * @code
+ * // Toggle the blinking led after 5 seconds
+ *
+ * #include "mbed.h"
+ *
+ * Ticker timer;
+ * DigitalOut led1(LED1);
+ * DigitalOut led2(LED2);
+ *
+ * int flip = 0;
+ *
+ * void attime() {
+ *     flip = !flip;
+ * }
+ *
+ * int main() {
+ *     timer.attach(&attime, 5);
+ *     while(1) {
+ *         if(flip == 0) {
+ *             led1 = !led1;
+ *         } else {
+ *             led2 = !led2;
+ *         }
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class Ticker : public TimerEvent {
+
+public:
+    Ticker() : TimerEvent() {
+    }
+
+    Ticker(const ticker_data_t *data) : TimerEvent(data) {
+    }
+
+    /** Attach a function to be called by the Ticker, specifiying the interval in seconds
+     *
+     *  @param fptr pointer to the function to be called
+     *  @param t the time between calls in seconds
+     */
+    void attach(void (*fptr)(void), float t) {
+        attach_us(fptr, t * 1000000.0f);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifiying the interval in seconds
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param t the time between calls in seconds
+     */
+    template<typename T>
+    void attach(T* tptr, void (T::*mptr)(void), float t) {
+        attach_us(tptr, mptr, t * 1000000.0f);
+    }
+
+    /** Attach a function to be called by the Ticker, specifiying the interval in micro-seconds
+     *
+     *  @param fptr pointer to the function to be called
+     *  @param t the time between calls in micro-seconds
+     */
+    void attach_us(void (*fptr)(void), timestamp_t t) {
+        _function.attach(fptr);
+        setup(t);
+    }
+
+    /** Attach a member function to be called by the Ticker, specifiying the interval in micro-seconds
+     *
+     *  @param tptr pointer to the object to call the member function on
+     *  @param mptr pointer to the member function to be called
+     *  @param t the time between calls in micro-seconds
+     */
+    template<typename T>
+    void attach_us(T* tptr, void (T::*mptr)(void), timestamp_t t) {
+        _function.attach(tptr, mptr);
+        setup(t);
+    }
+
+    virtual ~Ticker() {
+        detach();
+    }
+
+    /** Detach the function
+     */
+    void detach();
+
+protected:
+    void setup(timestamp_t t);
+    virtual void handler();
+
+protected:
+    timestamp_t     _delay;     /**< Time delay (in microseconds) for re-setting the multi-shot callback. */
+    FunctionPointer _function;  /**< Callback. */
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/Timeout.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEOUT_H
+#define MBED_TIMEOUT_H
+
+#include "Ticker.h"
+
+namespace mbed {
+
+/** A Timeout is used to call a function at a point in the future
+ *
+ * You can use as many seperate Timeout objects as you require.
+ *
+ * Example:
+ * @code
+ * // Blink until timeout.
+ *
+ * #include "mbed.h"
+ *
+ * Timeout timeout;
+ * DigitalOut led(LED1);
+ *
+ * int on = 1;
+ *
+ * void attimeout() {
+ *     on = 0;
+ * }
+ *
+ * int main() {
+ *     timeout.attach(&attimeout, 5);
+ *     while(on) {
+ *         led = !led;
+ *         wait(0.2);
+ *     }
+ * }
+ * @endcode
+ */
+class Timeout : public Ticker {
+
+protected:
+    virtual void handler();
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/Timer.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMER_H
+#define MBED_TIMER_H
+
+#include "platform.h"
+#include "ticker_api.h"
+
+namespace mbed {
+
+/** A general purpose timer
+ *
+ * Example:
+ * @code
+ * // Count the time to toggle a LED
+ *
+ * #include "mbed.h"
+ *
+ * Timer timer;
+ * DigitalOut led(LED1);
+ * int begin, end;
+ *
+ * int main() {
+ *     timer.start();
+ *     begin = timer.read_us();
+ *     led = !led;
+ *     end = timer.read_us();
+ *     printf("Toggle the led takes %d us", end - begin);
+ * }
+ * @endcode
+ */
+class Timer {
+
+public:
+    Timer();
+    Timer(const ticker_data_t *data);
+
+    /** Start the timer
+     */
+    void start();
+
+    /** Stop the timer
+     */
+    void stop();
+
+    /** Reset the timer to 0.
+     *
+     * If it was already counting, it will continue
+     */
+    void reset();
+
+    /** Get the time passed in seconds
+     */
+    float read();
+
+    /** Get the time passed in mili-seconds
+     */
+    int read_ms();
+
+    /** Get the time passed in micro-seconds
+     */
+    int read_us();
+
+#ifdef MBED_OPERATORS
+    operator float();
+#endif
+
+protected:
+    int slicetime();
+    int _running;          // whether the timer is running
+    unsigned int _start;   // the start time of the latest slice
+    int _time;             // any accumulated time from previous slices
+    const ticker_data_t *_ticker_data;
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/TimerEvent.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,56 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TIMEREVENT_H
+#define MBED_TIMEREVENT_H
+
+#include "ticker_api.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+/** Base abstraction for timer interrupts
+*/
+class TimerEvent {
+public:
+    TimerEvent();
+    TimerEvent(const ticker_data_t *data);
+
+    /** The handler registered with the underlying timer interrupt
+     */
+    static void irq(uint32_t id);
+
+    /** Destruction removes it...
+     */
+    virtual ~TimerEvent();
+
+protected:
+    // The handler called to service the timer event of the derived class
+    virtual void handler() = 0;
+
+    // insert in to linked list
+    void insert(timestamp_t timestamp);
+
+    // remove from linked list, if in it
+    void remove();
+
+    ticker_event_t event;
+
+    const ticker_data_t *_ticker_data;
+};
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/Transaction.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TRANSACTION_H
+#define MBED_TRANSACTION_H
+
+#include "platform.h"
+#include "FunctionPointer.h"
+
+namespace mbed {
+
+/** Transaction structure
+ */
+typedef struct {
+    void *tx_buffer;           /**< Tx buffer */
+    size_t tx_length;          /**< Length of Tx buffer*/
+    void *rx_buffer;           /**< Rx buffer */
+    size_t rx_length;          /**< Length of Rx buffer */
+    uint32_t event;            /**< Event for a transaction */
+    event_callback_t callback; /**< User's callback */
+    uint8_t width;             /**< Buffer's word width (8, 16, 32, 64) */
+} transaction_t;
+
+/** Transaction class defines a transaction.
+ */
+template<typename Class>
+class Transaction {
+public:
+    Transaction(Class *tpointer, const transaction_t& transaction) : _obj(tpointer), _data(transaction) {
+    }
+
+    Transaction() : _obj(), _data() {
+    }
+
+    ~Transaction() {
+    }
+
+    /** Get object's instance for the transaction
+     *
+     * @return The object which was stored
+     */
+    Class* get_object() {
+        return _obj;
+    }
+
+    /** Get the transaction
+     *
+     * @return The transaction which was stored
+     */
+    transaction_t* get_transaction() {
+        return &_data;
+    }
+
+private:
+    Class* _obj;
+    transaction_t _data;
+};
+
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/analogin_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,39 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGIN_API_H
+#define MBED_ANALOGIN_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct analogin_s analogin_t;
+
+void     analogin_init    (analogin_t *obj, PinName pin);
+float    analogin_read    (analogin_t *obj);
+uint16_t analogin_read_u16(analogin_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/analogout_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ANALOGOUT_API_H
+#define MBED_ANALOGOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_ANALOGOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct dac_s dac_t;
+
+void     analogout_init     (dac_t *obj, PinName pin);
+void     analogout_free     (dac_t *obj);
+void     analogout_write    (dac_t *obj, float value);
+void     analogout_write_u16(dac_t *obj, uint16_t value);
+float    analogout_read     (dac_t *obj);
+uint16_t analogout_read_u16 (dac_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/buffer.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_BUFFER_H
+#define MBED_BUFFER_H
+
+#include <stddef.h>
+
+/** Generic buffer structure
+ */
+typedef struct buffer_s {
+    void    *buffer; /**< the pointer to a buffer */
+    size_t   length; /**< the buffer length */
+    size_t   pos;    /**< actual buffer position */
+    uint8_t  width;  /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
+} buffer_t;
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/can_helper.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,53 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_CAN_HELPER_H
+#define MBED_CAN_HELPER_H
+
+#if DEVICE_CAN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+enum CANFormat {
+    CANStandard = 0,
+    CANExtended = 1,
+    CANAny = 2
+};
+typedef enum CANFormat CANFormat;
+
+enum CANType {
+    CANData   = 0,
+    CANRemote = 1
+};
+typedef enum CANType CANType;
+
+struct CAN_Message {
+    unsigned int   id;                 // 29 bit identifier
+    unsigned char  data[8];            // Data field
+    unsigned char  len;                // Length of data field in bytes
+    CANFormat      format;             // 0 - STANDARD, 1- EXTENDED IDENTIFIER
+    CANType        type;               // 0 - DATA FRAME, 1 - REMOTE FRAME
+};
+typedef struct CAN_Message CAN_Message;
+
+#ifdef __cplusplus
+};
+#endif
+
+#endif
+
+#endif // MBED_CAN_HELPER_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/dma_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2014-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DMA_API_H
+#define MBED_DMA_API_H
+
+#include <stdint.h>
+
+#define DMA_ERROR_OUT_OF_CHANNELS (-1)
+
+typedef enum {
+    DMA_USAGE_NEVER,
+    DMA_USAGE_OPPORTUNISTIC,
+    DMA_USAGE_ALWAYS,
+    DMA_USAGE_TEMPORARY_ALLOCATED,
+    DMA_USAGE_ALLOCATED
+} DMAUsage;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void dma_init(void);
+
+int dma_channel_allocate(uint32_t capabilities);
+
+int dma_channel_free(int channelid);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/gpio_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,57 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_API_H
+#define MBED_GPIO_API_H
+
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Set the given pin as GPIO
+ * @param pin The pin to be set as GPIO
+ * @return The GPIO port mask for this pin
+ **/
+uint32_t gpio_set(PinName pin);
+
+/* Checks if gpio object is connected (pin was not initialized with NC)
+ * @param pin The pin to be set as GPIO
+ * @return 0 if port is initialized with NC
+ **/
+int gpio_is_connected(const gpio_t *obj);
+
+/* GPIO object */
+void gpio_init(gpio_t *obj, PinName pin);
+
+void gpio_mode (gpio_t *obj, PinMode mode);
+void gpio_dir  (gpio_t *obj, PinDirection direction);
+
+void gpio_write(gpio_t *obj, int value);
+int  gpio_read (gpio_t *obj);
+
+// the following set of functions are generic and are implemented in the common gpio.c file
+void gpio_init_in(gpio_t* gpio, PinName pin);
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
+void gpio_init_out(gpio_t* gpio, PinName pin);
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/gpio_irq_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_GPIO_IRQ_API_H
+#define MBED_GPIO_IRQ_API_H
+
+#include "device.h"
+
+#if DEVICE_INTERRUPTIN
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    IRQ_NONE,
+    IRQ_RISE,
+    IRQ_FALL
+} gpio_irq_event;
+
+typedef struct gpio_irq_s gpio_irq_t;
+
+typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
+
+int  gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
+void gpio_irq_free(gpio_irq_t *obj);
+void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
+void gpio_irq_enable(gpio_irq_t *obj);
+void gpio_irq_disable(gpio_irq_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/gpio_object.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_GPIO_OBJECT_H
+#define MBED_GPIO_OBJECT_H
+
+#include "mbed_assert.h"
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName  pin;
+    uint32_t mask;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_set;
+    __IO uint32_t *reg_clr;
+} gpio_t;
+
+static inline void gpio_write(gpio_t *obj, int value)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    if (value) {
+        *obj->reg_set = obj->mask;
+    } else {
+        *obj->reg_clr = obj->mask;
+    }
+}
+
+static inline int gpio_read(gpio_t *obj)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    return ((*obj->reg_in & obj->mask) ? 1 : 0);
+}
+
+static inline int gpio_is_connected(const gpio_t *obj)
+{
+    return obj->pin != (PinName)NC;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/i2c_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,223 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_I2C_API_H
+#define MBED_I2C_API_H
+
+#include "device.h"
+#include "buffer.h"
+
+#if DEVICE_I2C
+
+/**
+ * @defgroup I2CEvents I2C Events Macros
+ *
+ * @{
+ */
+#define I2C_EVENT_ERROR               (1 << 1)
+#define I2C_EVENT_ERROR_NO_SLAVE      (1 << 2)
+#define I2C_EVENT_TRANSFER_COMPLETE   (1 << 3)
+#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
+#define I2C_EVENT_ALL                 (I2C_EVENT_ERROR |  I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+/** Asynch i2c hal structure
+ */
+typedef struct {
+    struct i2c_s    i2c;     /**< Target specific i2c structure */
+    struct buffer_s tx_buff; /**< Tx buffer */
+    struct buffer_s rx_buff; /**< Rx buffer */
+} i2c_t;
+
+#else
+/** Non-asynch i2c hal structure
+ */
+typedef struct i2c_s i2c_t;
+
+#endif
+
+enum {
+  I2C_ERROR_NO_SLAVE = -1,
+  I2C_ERROR_BUS_BUSY = -2
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup GeneralI2C I2C Configuration Functions
+ * @{
+ */
+
+/** Initialize the I2C peripheral. It sets the default parameters for I2C
+ *  peripheral, and configure its specifieds pins.
+ *  @param obj  The i2c object
+ *  @param sda  The sda pin
+ *  @param scl  The scl pin
+ */
+void i2c_init(i2c_t *obj, PinName sda, PinName scl);
+
+/** Configure the I2C frequency.
+ *  @param obj The i2c object
+ *  @param hz  Frequency in Hz
+ */
+void i2c_frequency(i2c_t *obj, int hz);
+
+/** Send START command.
+ *  @param obj The i2c object
+ */
+int  i2c_start(i2c_t *obj);
+
+/** Send STOP command.
+ *  @param obj The i2c object
+ */
+int  i2c_stop(i2c_t *obj);
+
+/** Blocking reading data.
+ *  @param obj     The i2c object
+ *  @param address 7-bit address (last bit is 1)
+ *  @param data    The buffer for receiving
+ *  @param length  Number of bytes to read
+ *  @param stop    Stop to be generated after the transfer is done
+ *  @return Number of read bytes
+ */
+int  i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
+
+/** Blocking sending data.
+ *  @param obj     The i2c object
+ *  @param address 7-bit address (last bit is 0)
+ *  @param data    The buffer for sending
+ *  @param length  Number of bytes to wrte
+ *  @param stop    Stop to be generated after the transfer is done
+ *  @return Number of written bytes
+ */
+int  i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
+
+/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop().
+ *  @param obj The i2c object
+ */
+void i2c_reset(i2c_t *obj);
+
+/** Read one byte.
+ *  @param obj The i2c object
+ *  @param last Acknoledge
+ *  @return The read byte
+ */
+int  i2c_byte_read(i2c_t *obj, int last);
+
+/** Write one byte.
+ *  @param obj The i2c object
+ *  @param data Byte to be written
+ *  @return 1 if NAK was received, 0 if ACK was received, 2 for timeout.
+ */
+int  i2c_byte_write(i2c_t *obj, int data);
+
+/**@}*/
+
+#if DEVICE_I2CSLAVE
+
+/**
+ * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
+ * @{
+ */
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @return non-zero if a value is available
+ */
+void i2c_slave_mode(i2c_t *obj, int enable_slave);
+
+/** Check to see if the I2C slave has been addressed.
+ *  @param obj The I2C object
+ *  @return The status - 1 - read addresses, 2 - write to all slaves,
+ *         3 write addressed, 0 - the slave has not been addressed
+ */
+int  i2c_slave_receive(i2c_t *obj);
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @return non-zero if a value is available
+ */
+int  i2c_slave_read(i2c_t *obj, char *data, int length);
+
+/** Configure I2C as slave or master.
+ *  @param obj The I2C object
+ *  @return non-zero if a value is available
+ */
+int  i2c_slave_write(i2c_t *obj, const char *data, int length);
+
+/** Configure I2C address.
+ *  @param obj     The I2C object
+ *  @param idx     Currently not used
+ *  @param address The address to be set
+ *  @param mask    Currently not used
+ */
+void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
+
+#endif
+
+/**@}*/
+
+#if DEVICE_I2C_ASYNCH
+
+/**
+ * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer
+ * @{
+ */
+
+/** Start i2c asynchronous transfer.
+ *  @param obj       The I2C object
+ *  @param tx        The buffer to send
+ *  @param tx_length The number of words to transmit
+ *  @param rx        The buffer to receive
+ *  @param rx_length The number of words to receive
+ *  @param address   The address to be set - 7bit or 9 bit
+ *  @param stop      If true, stop will be generated after the transfer is done
+ *  @param handler   The I2C IRQ handler to be set
+ *  @param hint      DMA hint usage
+ */
+void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *  @param obj The I2C object which holds the transfer information
+ *  @return event flags if a transfer termination condition was met or 0 otherwise.
+ */
+uint32_t i2c_irq_handler_asynch(i2c_t *obj);
+
+/** Attempts to determine if I2C peripheral is already in use.
+ *  @param obj The I2C object
+ *  @return non-zero if the I2C module is active or zero if it is not
+ */
+uint8_t i2c_active(i2c_t *obj);
+
+/** Abort ongoing asynchronous transaction.
+ *  @param obj The I2C object
+ */
+void i2c_abort_asynch(i2c_t *obj);
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/lp_ticker_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_LPTICKER_API_H
+#define MBED_LPTICKER_API_H
+
+#include "device.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+#include "ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup LpTicker Low Power Ticker Functions
+ * @{
+ */
+
+/** Get low power ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_lp_ticker_data(void);
+
+/** The wrapper for ticker_irq_handler, to pass lp ticker's data
+ *
+ */
+void lp_ticker_irq_handler(void);
+
+/* HAL lp ticker */
+
+/** Initialize the low power ticker
+ *
+ */
+void lp_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t lp_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void lp_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable low power ticker interrupt
+ *
+ */
+void lp_ticker_disable_interrupt(void);
+
+/** Clear the low power ticker interrupt
+ *
+ */
+void lp_ticker_clear_interrupt(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/mbed.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,69 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_H
+#define MBED_H
+
+#define MBED_LIBRARY_VERSION 107
+
+#include "platform.h"
+
+// Useful C libraries
+#include <math.h>
+#include <time.h>
+
+// mbed Debug libraries
+#include "mbed_error.h"
+#include "mbed_interface.h"
+
+// mbed Peripheral components
+#include "DigitalIn.h"
+#include "DigitalOut.h"
+#include "DigitalInOut.h"
+#include "BusIn.h"
+#include "BusOut.h"
+#include "BusInOut.h"
+#include "PortIn.h"
+#include "PortInOut.h"
+#include "PortOut.h"
+#include "AnalogIn.h"
+#include "AnalogOut.h"
+#include "PwmOut.h"
+#include "Serial.h"
+#include "SPI.h"
+#include "SPISlave.h"
+#include "I2C.h"
+#include "I2CSlave.h"
+#include "Ethernet.h"
+#include "CAN.h"
+#include "RawSerial.h"
+
+// mbed Internal components
+#include "Timer.h"
+#include "Ticker.h"
+#include "Timeout.h"
+#include "LowPowerTimeout.h"
+#include "LowPowerTicker.h"
+#include "LowPowerTimer.h"
+#include "LocalFileSystem.h"
+#include "InterruptIn.h"
+#include "wait_api.h"
+#include "sleep_api.h"
+#include "rtc_time.h"
+
+using namespace mbed;
+using namespace std;
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/mbed_assert.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ASSERT_H
+#define MBED_ASSERT_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Internal mbed assert function which is invoked when MBED_ASSERT macro failes.
+ *  This function is active only if NDEBUG is not defined prior to including this
+ *  assert header file.
+ *  In case of MBED_ASSERT failing condition, error() is called with the assertation message.
+ *  @param expr Expresion to be checked.
+ *  @param file File where assertation failed.
+ *  @param line Failing assertation line number.
+ */
+void mbed_assert_internal(const char *expr, const char *file, int line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#ifdef NDEBUG
+#define MBED_ASSERT(expr) ((void)0)
+
+#else
+#define MBED_ASSERT(expr)                                \
+do {                                                     \
+    if (!(expr)) {                                       \
+        mbed_assert_internal(#expr, __FILE__, __LINE__); \
+    }                                                    \
+} while (0)
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/mbed_debug.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_DEBUG_H
+#define MBED_DEBUG_H
+#include "device.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#include <stdarg.h>
+
+/** Output a debug message
+ *
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug(const char *format, ...) {
+    va_list args;
+    va_start(args, format);
+    vfprintf(stderr, format, args);
+    va_end(args);
+}
+
+/** Conditionally output a debug message
+ *
+ * NOTE: If the condition is constant false (!= 1) and the compiler optimization
+ * level is greater than 0, then the whole function will be compiled away.
+ *
+ * @param condition output only if condition is true (== 1)
+ * @param format printf-style format string, followed by variables
+ */
+static inline void debug_if(int condition, const char *format, ...) {
+    if (condition == 1) {
+        va_list args;
+        va_start(args, format);
+        vfprintf(stderr, format, args);
+        va_end(args);
+    }
+}
+
+#else
+static inline void debug(const char *format, ...) {}
+static inline void debug_if(int condition, const char *format, ...) {}
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/mbed_error.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_ERROR_H
+#define MBED_ERROR_H
+
+/** To generate a fatal compile-time error, you can use the pre-processor #error directive.
+ *
+ * @code
+ * #error "That shouldn't have happened!"
+ * @endcode
+ *
+ * If the compiler evaluates this line, it will report the error and stop the compile.
+ *
+ * For example, you could use this to check some user-defined compile-time variables:
+ *
+ * @code
+ * #define NUM_PORTS 7
+ * #if (NUM_PORTS > 4)
+ *     #error "NUM_PORTS must be less than 4"
+ * #endif
+ * @endcode
+ *
+ * Reporting Run-Time Errors:
+ * To generate a fatal run-time error, you can use the mbed error() function.
+ *
+ * @code
+ * error("That shouldn't have happened!");
+ * @endcode
+ *
+ * If the mbed running the program executes this function, it will print the
+ * message via the USB serial port, and then die with the blue lights of death!
+ *
+ * The message can use printf-style formatting, so you can report variables in the
+ * message too. For example, you could use this to check a run-time condition:
+ *
+ * @code
+ * if(x >= 5) {
+ *     error("expected x to be less than 5, but got %d", x);
+ * }
+ * #endcode
+ */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void error(const char* format, ...);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/mbed_interface.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,114 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_INTERFACE_H
+#define MBED_INTERFACE_H
+
+#include "device.h"
+
+/* Mbed interface mac address
+ * if MBED_MAC_ADD_x are zero, interface uid sets mac address,
+ * otherwise MAC_ADD_x are used.
+ */
+#define MBED_MAC_ADDR_INTERFACE 0x00
+#define MBED_MAC_ADDR_0  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_1  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_2  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_3  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_4  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDR_5  MBED_MAC_ADDR_INTERFACE
+#define MBED_MAC_ADDRESS_SUM (MBED_MAC_ADDR_0 | MBED_MAC_ADDR_1 | MBED_MAC_ADDR_2 | MBED_MAC_ADDR_3 | MBED_MAC_ADDR_4 | MBED_MAC_ADDR_5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+/** Functions to control the mbed interface
+ *
+ * mbed Microcontrollers have a built-in interface to provide functionality such as
+ * drag-n-drop download, reset, serial-over-usb, and access to the mbed local file
+ * system. These functions provide means to control the interface suing semihost
+ * calls it supports.
+ */
+
+/** Determine whether the mbed interface is connected, based on whether debug is enabled
+ *
+ *  @returns
+ *    1 if interface is connected,
+ *    0 otherwise
+ */
+int mbed_interface_connected(void);
+
+/** Instruct the mbed interface to reset, as if the reset button had been pressed
+ *
+ *  @returns
+ *    1 if successful,
+ *    0 otherwise (e.g. interface not present)
+ */
+int mbed_interface_reset(void);
+
+/** This will disconnect the debug aspect of the interface, so semihosting will be disabled.
+ * The interface will still support the USB serial aspect
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_disconnect(void);
+
+/** This will disconnect the debug aspect of the interface, and if the USB cable is not
+ * connected, also power down the interface. If the USB cable is connected, the interface
+ * will remain powered up and visible to the host
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_powerdown(void);
+
+/** This returns a string containing the 32-character UID of the mbed interface
+ *  This is a weak function that can be overwritten if required
+ *
+ *  @param uid A 33-byte array to write the null terminated 32-byte string
+ *
+ *  @returns
+ *    0 if successful,
+ *   -1 otherwise (e.g. interface not present)
+ */
+int mbed_interface_uid(char *uid);
+
+#endif
+
+/** This returns a unique 6-byte MAC address, based on the interface UID
+ * If the interface is not present, it returns a default fixed MAC address (00:02:F7:F0:00:00)
+ *
+ * This is a weak function that can be overwritten if you want to provide your own mechanism to
+ * provide a MAC address.
+ *
+ *  @param mac A 6-byte array to write the MAC address
+ */
+void mbed_mac_address(char *mac);
+
+/** Cause the mbed to flash the BLOD (Blue LEDs Of Death) sequence
+ */
+void mbed_die(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/pinmap.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINMAP_H
+#define MBED_PINMAP_H
+
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct {
+    PinName pin;
+    int peripheral;
+    int function;
+} PinMap;
+
+void pin_function(PinName pin, int function);
+void pin_mode    (PinName pin, PinMode mode);
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_function(PinName pin, const PinMap* map);
+uint32_t pinmap_merge     (uint32_t a, uint32_t b);
+void     pinmap_pinout    (PinName pin, const PinMap *map);
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
+uint32_t pinmap_find_function(PinName pin, const PinMap* map);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/platform.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PLATFORM_H
+#define MBED_PLATFORM_H
+
+#define MBED_OPERATORS    1
+
+#include "device.h"
+#include "PinNames.h"
+#include "PeripheralNames.h"
+
+#include <cstddef>
+#include <cstdlib>
+#include <cstdio>
+#include <cstring>
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/port_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PORTMAP_H
+#define MBED_PORTMAP_H
+
+#include "device.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct port_s port_t;
+
+PinName port_pin(PortName port, int pin_n);
+
+void port_init (port_t *obj, PortName port, int mask, PinDirection dir);
+void port_mode (port_t *obj, PinMode mode);
+void port_dir  (port_t *obj, PinDirection dir);
+void port_write(port_t *obj, int value);
+int  port_read (port_t *obj);
+
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/pwmout_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,49 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PWMOUT_API_H
+#define MBED_PWMOUT_API_H
+
+#include "device.h"
+
+#if DEVICE_PWMOUT
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef struct pwmout_s pwmout_t;
+
+void pwmout_init         (pwmout_t* obj, PinName pin);
+void pwmout_free         (pwmout_t* obj);
+
+void  pwmout_write       (pwmout_t* obj, float percent);
+float pwmout_read        (pwmout_t* obj);
+
+void pwmout_period       (pwmout_t* obj, float seconds);
+void pwmout_period_ms    (pwmout_t* obj, int ms);
+void pwmout_period_us    (pwmout_t* obj, int us);
+
+void pwmout_pulsewidth   (pwmout_t* obj, float seconds);
+void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);
+void pwmout_pulsewidth_us(pwmout_t* obj, int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/rtc_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,42 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_RTC_API_H
+#define MBED_RTC_API_H
+
+#include "device.h"
+
+#if DEVICE_RTC
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void rtc_init(void);
+void rtc_free(void);
+int rtc_isenabled(void);
+
+time_t rtc_read(void);
+void rtc_write(time_t t);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/rtc_time.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include <time.h>
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Implementation of the C time.h functions
+ *
+ * Provides mechanisms to set and read the current time, based
+ * on the microcontroller Real-Time Clock (RTC), plus some
+ * standard C manipulation and formating functions.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737);  // Set RTC time to Wed, 28 Oct 2009 11:35:37
+ *
+ *     while(1) {
+ *         time_t seconds = time(NULL);
+ *
+ *         printf("Time as seconds since January 1, 1970 = %d\n", seconds);
+ *
+ *         printf("Time as a basic string = %s", ctime(&seconds));
+ *
+ *         char buffer[32];
+ *         strftime(buffer, 32, "%I:%M %p\n", localtime(&seconds));
+ *         printf("Time as a custom formatted string = %s", buffer);
+ *
+ *         wait(1);
+ *     }
+ * }
+ * @endcode
+ */
+
+/** Set the current time
+ *
+ * Initialises and sets the time of the microcontroller Real-Time Clock (RTC)
+ * to the time represented by the number of seconds since January 1, 1970
+ * (the UNIX timestamp).
+ *
+ * @param t Number of seconds since January 1, 1970 (the UNIX timestamp)
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * int main() {
+ *     set_time(1256729737); // Set time to Wed, 28 Oct 2009 11:35:37
+ * }
+ * @endcode
+ */
+void set_time(time_t t);
+
+/** Attach an external RTC to be used for the C time functions
+ *
+ * Do not call this function from an interrupt while an RTC read/write operation may be occurring 
+ *
+ * @param read_rtc pointer to function which returns current UNIX timestamp
+ * @param write_rtc pointer to function which sets current UNIX timestamp, can be NULL
+ * @param init_rtc pointer to funtion which initializes RTC, can be NULL
+ * @param isenabled_rtc pointer to function wich returns if the rtc is enabled, can be NULL
+ */
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void));
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/semihost_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,93 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SEMIHOST_H
+#define MBED_SEMIHOST_H
+
+#include "device.h"
+#include "toolchain.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if DEVICE_SEMIHOST
+
+#ifndef __CC_ARM
+
+#if defined(__ICCARM__)
+inline int __semihost(int reason, const void *arg) {
+    return __semihosting(reason, (void*)arg);
+}
+#else
+
+#ifdef __thumb__
+#   define AngelSWI            0xAB
+#   define AngelSWIInsn        "bkpt"
+#   define AngelSWIAsm          bkpt
+#else
+#   define AngelSWI            0x123456
+#   define AngelSWIInsn        "swi"
+#   define AngelSWIAsm          swi
+#endif
+
+static inline int __semihost(int reason, const void *arg) {
+    int value;
+
+    asm volatile (
+       "mov r0, %1"          "\n\t"
+       "mov r1, %2"          "\n\t"
+       AngelSWIInsn " %a3"   "\n\t"
+       "mov %0, r0"
+       : "=r" (value)                                         /* output operands             */
+       : "r" (reason), "r" (arg), "i" (AngelSWI)              /* input operands              */
+       : "r0", "r1", "r2", "r3", "ip", "lr", "memory", "cc"   /* list of clobbered registers */
+    );
+
+    return value;
+}
+#endif
+#endif
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode);
+int semihost_close (FILEHANDLE fh);
+int semihost_read  (FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode);
+int semihost_write (FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode);
+int semihost_ensure(FILEHANDLE fh);
+long semihost_flen (FILEHANDLE fh);
+int semihost_seek  (FILEHANDLE fh, long position);
+int semihost_istty (FILEHANDLE fh);
+
+int semihost_remove(const char *name);
+int semihost_rename(const char *old_name, const char *new_name);
+#endif
+
+int semihost_uid(char *uid);
+int semihost_reset(void);
+int semihost_vbus(void);
+int semihost_powerdown(void);
+int semihost_exit(void);
+
+int semihost_connected(void);
+int semihost_disabledebug(void);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/serial_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,302 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SERIAL_API_H
+#define MBED_SERIAL_API_H
+
+#include "device.h"
+#include "buffer.h"
+#include "dma_api.h"
+
+#if DEVICE_SERIAL
+
+#define SERIAL_EVENT_TX_SHIFT (2)
+#define SERIAL_EVENT_RX_SHIFT (8)
+
+#define SERIAL_EVENT_TX_MASK (0x00FC)
+#define SERIAL_EVENT_RX_MASK (0x3F00)
+
+#define SERIAL_EVENT_ERROR (1 << 1)
+
+/**
+ * @defgroup SerialTXEvents Serial TX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
+#define SERIAL_EVENT_TX_ALL      (SERIAL_EVENT_TX_COMPLETE)
+/**@}*/
+
+/**
+ * @defgroup SerialRXEvents Serial RX Events Macros
+ *
+ * @{
+ */
+#define SERIAL_EVENT_RX_COMPLETE        (1 << (SERIAL_EVENT_RX_SHIFT + 0))
+#define SERIAL_EVENT_RX_OVERRUN_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 1))
+#define SERIAL_EVENT_RX_FRAMING_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 2))
+#define SERIAL_EVENT_RX_PARITY_ERROR    (1 << (SERIAL_EVENT_RX_SHIFT + 3))
+#define SERIAL_EVENT_RX_OVERFLOW        (1 << (SERIAL_EVENT_RX_SHIFT + 4))
+#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
+#define SERIAL_EVENT_RX_ALL             (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
+                                         SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
+                                         SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
+/**@}*/
+
+#define SERIAL_RESERVED_CHAR_MATCH (255)
+
+typedef enum {
+    ParityNone = 0,
+    ParityOdd = 1,
+    ParityEven = 2,
+    ParityForced1 = 3,
+    ParityForced0 = 4
+} SerialParity;
+
+typedef enum {
+    RxIrq,
+    TxIrq
+} SerialIrq;
+
+typedef enum {
+    FlowControlNone,
+    FlowControlRTS,
+    FlowControlCTS,
+    FlowControlRTSCTS
+} FlowControl;
+
+typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
+
+#if DEVICE_SERIAL_ASYNCH
+/** Asynch serial hal structure
+ */
+typedef struct {
+    struct serial_s serial;  /**< Target specific serial structure */
+    struct buffer_s tx_buff; /**< Tx buffer */
+    struct buffer_s rx_buff; /**< Rx buffer */
+    uint8_t char_match;      /**< Character to be matched */
+    uint8_t char_found;      /**< State of the matched character */
+} serial_t;
+
+#else
+/** Non-asynch serial hal structure
+ */
+typedef struct serial_s serial_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup GeneralSerial Serial Configuration Functions
+ * @{
+ */
+
+/** Initialize the serial peripheral. It sets the default parameters for serial
+ *  peripheral, and configure its specifieds pins.
+ *
+ * @param obj The serial object
+ * @param tx  The TX pin
+ * @param rx  The RX pin
+ */
+void serial_init(serial_t *obj, PinName tx, PinName rx);
+
+/** Release the serial peripheral, not currently invoked. It requires further
+ *  resource management.
+ *
+ * @param obj The serial object
+ */
+void serial_free(serial_t *obj);
+
+/** Configure the baud rate
+ *
+ * @param obj      The serial object
+ * @param baudrate The baud rate to be configured
+ */
+void serial_baud(serial_t *obj, int baudrate);
+
+/** Configure the format. Set the number of bits, parity and the number of stop bits
+ *
+ * @param obj       The serial object
+ * @param data_bits The number of data bits
+ * @param parity    The parity
+ * @param stop_bits The number of stop bits
+ */
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
+
+/** The serial interrupt handler registration.
+ *
+ * @param obj     The serial object
+ * @param handler The interrupt handler which will be invoked when interrupt fires.
+ * @param id      The SerialBase object
+ */
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
+
+/** Configure serial interrupt. This function is used for word-approach
+ *
+ * @param obj    The serial object
+ * @param irq    The serial IRQ type (RX or TX)
+ * @param enable Set to non-zero to enable events, or zero to disable them
+ */
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
+
+/** Get character. This is a blocking call, waiting for a character
+ *
+ * @param obj The serial object
+ */
+int  serial_getc(serial_t *obj);
+
+/** Put a character. This is a blocking call, waiting for a peripheral to be available
+ *  for writing
+ *
+ * @param obj The serial object
+ * @param c   The character to be sent
+ */
+void serial_putc(serial_t *obj, int c);
+
+/** Check if the serial peripheral is readable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be read, 0 if nothing to read.
+ */
+int  serial_readable(serial_t *obj);
+
+/** Check if the serial peripheral is writable
+ *
+ * @param obj The serial object
+ * @return Non-zero value if a character can be written, 0 otherwise.
+ */
+int  serial_writable(serial_t *obj);
+
+/** Clear the serial peripheral
+ *
+ * @param obj The serial object
+ */
+void serial_clear(serial_t *obj);
+
+/** Set the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_set(serial_t *obj);
+
+/** Clear the break
+ *
+ * @param obj The serial object
+ */
+void serial_break_clear(serial_t *obj);
+
+/** Configure the TX pin for UART function.
+ *
+ * @param tx The pin used for TX
+ */
+void serial_pinout_tx(PinName tx);
+
+/** Configure the serial for the flow control. It sets flow control in the hardware
+ *  if a serial peripheral supports it, otherwise software emulation is used.
+ *
+ * @param obj    The serial object
+ * @param type   The type of the flow control. Look at the available FlowControl types.
+ * @param rxflow The tx pin
+ * @param txflow The rx pin
+ */
+void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
+
+#if DEVICE_SERIAL_ASYNCH
+
+/**@}*/
+
+/**
+ * \defgroup AsynchSerial Asynchronous Serial Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
+ *  tx_buff
+ *
+ * @param obj       The serial object
+ * @param tx        The buffer for sending
+ * @param tx_length The number of words to transmit
+ * @param tx_width  The bit width of buffer word
+ * @param handler   The serial handler
+ * @param event     The logical OR of events to be registered
+ * @param hint      A suggestion for how to use DMA with this transfer
+ * @return Returns number of data transfered, or 0 otherwise
+ */
+int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** Begin asynchronous RX transfer (enable interrupt for data collecting)
+ *  The used buffer is specified in the serial object - rx_buff
+ *
+ * @param obj        The serial object
+ * @param rx         The buffer for sending
+ * @param rx_length  The number of words to transmit
+ * @param rx_width   The bit width of buffer word
+ * @param handler    The serial handler
+ * @param event      The logical OR of events to be registered
+ * @param handler    The serial handler
+ * @param char_match A character in range 0-254 to be matched
+ * @param hint       A suggestion for how to use DMA with this transfer
+ */
+void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
+
+/** Attempts to determine if the serial peripheral is already in use for TX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_tx_active(serial_t *obj);
+
+/** Attempts to determine if the serial peripheral is already in use for RX
+ *
+ * @param obj The serial object
+ * @return Non-zero if the RX transaction is ongoing, 0 otherwise
+ */
+uint8_t serial_rx_active(serial_t *obj);
+
+/** The asynchronous TX and RX handler.
+ *
+ * @param obj The serial object
+ * @return Returns event flags if a RX transfer termination condition was met or 0 otherwise
+ */
+int serial_irq_handler_asynch(serial_t *obj);
+
+/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
+ *  flush TX hardware buffer if TX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_tx_abort_asynch(serial_t *obj);
+
+/** Abort the ongoing RX transaction It disables the enabled interrupt for RX and
+ *  flush RX hardware buffer if RX FIFO is used
+ *
+ * @param obj The serial object
+ */
+void serial_rx_abort_asynch(serial_t *obj);
+
+/**@}*/
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/sleep_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,64 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SLEEP_API_H
+#define MBED_SLEEP_API_H
+
+#include "device.h"
+
+#if DEVICE_SLEEP
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Send the microcontroller to sleep
+ *
+ * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
+ * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
+ * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
+ * memory state are maintained, and the peripherals continue to work and can generate interrupts.
+ *
+ * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void sleep(void);
+
+/** Send the microcontroller to deep sleep
+ *
+ * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
+ * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
+ * is still maintained.
+ *
+ * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
+ *
+ * @note
+ *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
+ * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
+ * able to access the LocalFileSystem
+ */
+void deepsleep(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/spi_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,213 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_SPI_API_H
+#define MBED_SPI_API_H
+
+#include "device.h"
+#include "dma_api.h"
+#include "buffer.h"
+
+#if DEVICE_SPI
+
+#define SPI_EVENT_ERROR       (1 << 1)
+#define SPI_EVENT_COMPLETE    (1 << 2)
+#define SPI_EVENT_RX_OVERFLOW (1 << 3)
+#define SPI_EVENT_ALL         (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
+
+#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
+
+#define SPI_FILL_WORD         (0xFFFF)
+
+#if DEVICE_SPI_ASYNCH
+/** Asynch spi hal structure
+ */
+typedef struct {
+    struct spi_s spi;        /**< Target specific spi structure */
+    struct buffer_s tx_buff; /**< Tx buffer */
+    struct buffer_s rx_buff; /**< Rx buffer */
+} spi_t;
+
+#else
+/** Non-asynch spi hal structure
+ */
+typedef struct spi_s spi_t;
+
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup GeneralSPI SPI Configuration Functions
+ * @{
+ */
+
+/** Initialize the SPI peripheral
+ *
+ * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
+ * @param[out] obj  The SPI object to initialize
+ * @param[in]  mosi The pin to use for MOSI
+ * @param[in]  miso The pin to use for MISO
+ * @param[in]  sclk The pin to use for SCLK
+ * @param[in]  ssel The pin to use for SSEL
+ */
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
+
+/** Release a SPI object
+ *
+ * TODO: spi_free is currently unimplemented
+ * This will require reference counting at the C++ level to be safe
+ *
+ * Return the pins owned by the SPI object to their reset state
+ * Disable the SPI peripheral
+ * Disable the SPI clock
+ * @param[in] obj The SPI object to deinitialize
+ */
+void spi_free(spi_t *obj);
+
+/** Configure the SPI format
+ *
+ * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
+ * @param[in,out] obj   The SPI object to configure
+ * @param[in]     bits  The number of bits per frame
+ * @param[in]     mode  The SPI mode (clock polarity, phase, and shift direction)
+ * @param[in]     slave Zero for master mode or non-zero for slave mode
+ */
+void spi_format(spi_t *obj, int bits, int mode, int slave);
+
+/** Set the SPI baud rate
+ *
+ * Actual frequency may differ from the desired frequency due to available dividers and bus clock
+ * Configures the SPI peripheral's baud rate
+ * @param[in,out] obj The SPI object to configure
+ * @param[in]     hz  The baud rate in Hz
+ */
+void spi_frequency(spi_t *obj, int hz);
+
+/**@}*/
+/**
+ * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Write a byte out in master mode and receive a value
+ *
+ * @param[in] obj   The SPI peripheral to use for sending
+ * @param[in] value The value to send
+ * @return Returns the value received during send
+ */
+int  spi_master_write(spi_t *obj, int value);
+
+/** Check if a value is available to read
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if a value is available
+ */
+int  spi_slave_receive(spi_t *obj);
+
+/** Get a received value out of the SPI receive buffer in slave mode
+ *
+ * Blocks until a value is available
+ * @param[in] obj The SPI peripheral to read
+ * @return The value received
+ */
+int  spi_slave_read(spi_t *obj);
+
+/** Write a value to the SPI peripheral in slave mode
+ *
+ * Blocks until the SPI peripheral can be written to
+ * @param[in] obj   The SPI peripheral to write
+ * @param[in] value The value to write
+ */
+void spi_slave_write(spi_t *obj, int value);
+
+/** Checks if the specified SPI peripheral is in use
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return non-zero if the peripheral is currently transmitting
+ */
+int  spi_busy(spi_t *obj);
+
+/** Get the module number
+ *
+ * @param[in] obj The SPI peripheral to check
+ * @return The module number
+ */
+uint8_t spi_get_module(spi_t *obj);
+
+/**@}*/
+
+#if DEVICE_SPI_ASYNCH
+/**
+ * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
+ * @{
+ */
+
+/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
+ *
+ * @param[in] obj       The SPI object which holds the transfer information
+ * @param[in] tx        The buffer to send
+ * @param[in] tx_length The number of words to transmit
+ * @param[in] rx        The buffer to receive
+ * @param[in] rx_length The number of words to receive
+ * @param[in] bit_width The bit width of buffer words
+ * @param[in] event     The logical OR of events to be registered
+ * @param[in] handler   SPI interrupt handler
+ * @param[in] hint      A suggestion for how to use DMA with this transfer
+ */
+void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
+
+/** The asynchronous IRQ handler
+ *
+ * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
+ * conditions, such as buffer overflows or transfer complete.
+ * @param[in] obj     The SPI object which holds the transfer information
+ * @return event flags if a transfer termination condition was met or 0 otherwise.
+ */
+uint32_t spi_irq_handler_asynch(spi_t *obj);
+
+/** Attempts to determine if the SPI peripheral is already in use.
+ *
+ * If a temporary DMA channel has been allocated, peripheral is in use.
+ * If a permanent DMA channel has been allocated, check if the DMA channel is in use.  If not, proceed as though no DMA
+ * channel were allocated.
+ * If no DMA channel is allocated, check whether tx and rx buffers have been assigned.  For each assigned buffer, check
+ * if the corresponding buffer position is less than the buffer length.  If buffers do not indicate activity, check if
+ * there are any bytes in the FIFOs.
+ * @param[in] obj The SPI object to check for activity
+ * @return non-zero if the SPI port is active or zero if it is not.
+ */
+uint8_t spi_active(spi_t *obj);
+
+/** Abort an SPI transfer
+ *
+ * @param obj The SPI peripheral to stop
+ */
+void spi_abort_asynch(spi_t *obj);
+
+
+#endif
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#endif // SPI_DEVICE
+
+#endif // MBED_SPI_API_H

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/ticker_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,108 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TICKER_API_H
+#define MBED_TICKER_API_H
+
+#include "device.h"
+
+typedef uint32_t timestamp_t;
+
+/** Ticker's event structure
+ */
+typedef struct ticker_event_s {
+    timestamp_t            timestamp; /**< Event's timestamp */
+    uint32_t               id;        /**< TimerEvent object */
+    struct ticker_event_s *next;      /**< Next event in the queue */
+} ticker_event_t;
+
+typedef void (*ticker_event_handler)(uint32_t id);
+
+/** Ticker's interface structure - required API for a ticker
+ */
+typedef struct {
+    void (*init)(void);                           /**< Init function */
+    uint32_t (*read)(void);                       /**< Read function */
+    void (*disable_interrupt)(void);              /**< Disable interrupt function */
+    void (*clear_interrupt)(void);                /**< Clear interrupt function */
+    void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
+} ticker_interface_t;
+
+/** Tickers events queue structure
+ */
+typedef struct {
+    ticker_event_handler event_handler; /**< Event handler */
+    ticker_event_t *head;               /**< A pointer to head */
+} ticker_event_queue_t;
+
+/** Tickers data structure
+ */
+typedef struct {
+    const ticker_interface_t *interface; /**< Ticker's interface */
+    ticker_event_queue_t *queue;         /**< Ticker's events queue */
+} ticker_data_t;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Initialize a ticker and sets the event handler
+ *
+ * @param data    The ticker's data
+ * @param handler A handler to be set
+ */
+void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler);
+
+/** Irq handler which goes through the events to trigger events in the past.
+ *
+ * @param data    The ticker's data
+ */
+void ticker_irq_handler(const ticker_data_t *const data);
+
+/** Remove an event from the queue
+ *
+ * @param data The ticker's data
+ * @param obj  The event's queue to be removed
+ */
+void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj);
+
+/** Insert an event from the queue
+ *
+ * @param data      The ticker's data
+ * @param obj       The event's queue to be removed
+ * @param timestamp The event's timestamp
+ * @param id        The event object
+ */
+void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
+
+/** Read the current ticker's timestamp
+ *
+ * @param data The ticker's data
+ * @return The current timestamp
+ */
+timestamp_t ticker_read(const ticker_data_t *const data);
+
+/** Read the next event's timestamp
+ *
+ * @param data The ticker's data
+ * @return 1 if timestamp is pending event, 0 if there's no event pending
+ */
+int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/toolchain.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_TOOLCHAIN_H
+#define MBED_TOOLCHAIN_H
+
+#if defined(TOOLCHAIN_ARM)
+#include <rt_sys.h>
+#endif
+
+#ifndef FILEHANDLE
+typedef int FILEHANDLE;
+#endif
+
+#if defined (__ICCARM__)
+#   define WEAK     __weak
+#   define PACKED   __packed
+#else
+#   define WEAK     __attribute__((weak))
+#   define PACKED   __attribute__((packed))
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/us_ticker_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,78 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_US_TICKER_API_H
+#define MBED_US_TICKER_API_H
+
+#include <stdint.h>
+#include "ticker_api.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * \defgroup UsTicker Microseconds Ticker Functions
+ * @{
+ */
+
+/** Get ticker's data
+ *
+ * @return The low power ticker data
+ */
+const ticker_data_t* get_us_ticker_data(void);
+
+
+/** The wrapper for ticker_irq_handler, to pass us ticker's data
+ *
+ */
+void us_ticker_irq_handler(void);
+
+/* HAL us ticker */
+
+/** Initialize the ticker
+ *
+ */
+void us_ticker_init(void);
+
+/** Read the current counter
+ *
+ * @return The current timer's counter value in microseconds
+ */
+uint32_t us_ticker_read(void);
+
+/** Set interrupt for specified timestamp
+ *
+ * @param timestamp The time in microseconds to be set
+ */
+void us_ticker_set_interrupt(timestamp_t timestamp);
+
+/** Disable us ticker interrupt
+ *
+ */
+void us_ticker_disable_interrupt(void);
+
+/** Clear us ticker interrupt
+ *
+ */
+void us_ticker_clear_interrupt(void);
+
+/**@}*/
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_head/wait_api.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_WAIT_API_H
+#define MBED_WAIT_API_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** Generic wait functions.
+ *
+ * These provide simple NOP type wait capabilities.
+ *
+ * Example:
+ * @code
+ * #include "mbed.h"
+ *
+ * DigitalOut heartbeat(LED1);
+ *
+ * int main() {
+ *     while (1) {
+ *         heartbeat = 1;
+ *         wait(0.5);
+ *         heartbeat = 0;
+ *         wait(0.5);
+ *     }
+ * }
+ */
+
+/** Waits for a number of seconds, with microsecond resolution (within
+ *  the accuracy of single precision floating point).
+ *
+ *  @param s number of seconds to wait
+ */
+void wait(float s);
+
+/** Waits a number of milliseconds.
+ *
+ *  @param ms the whole number of milliseconds to wait
+ */
+void wait_ms(int ms);
+
+/** Waits a number of microseconds.
+ *
+ *  @param us the whole number of microseconds to wait
+ */
+void wait_us(int us);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/BusIn.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusIn.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusIn::BusIn(PinName pins[16]) {
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusIn::~BusIn() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+int BusIn::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+void BusIn::mode(PinMode pull) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+}
+
+#ifdef MBED_OPERATORS
+BusIn::operator int() {
+    return read();
+}
+
+DigitalIn& BusIn::operator[] (int index) {
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+#endif
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/BusInOut.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,115 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusInOut.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusInOut::BusInOut(PinName pins[16]) {
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusInOut::~BusInOut() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusInOut::write(int value) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+}
+
+int BusInOut::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+void BusInOut::output() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->output();
+        }
+    }
+}
+
+void BusInOut::input() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->input();
+        }
+    }
+}
+
+void BusInOut::mode(PinMode pull) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->mode(pull);
+        }
+    }
+}
+
+#ifdef MBED_OPERATORS
+BusInOut& BusInOut::operator= (int v) {
+    write(v);
+    return *this;
+}
+
+BusInOut& BusInOut::operator= (BusInOut& rhs) {
+    write(rhs.read());
+    return *this;
+}
+
+DigitalInOut& BusInOut::operator[] (int index) {
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+BusInOut::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/BusOut.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,91 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "BusOut.h"
+#include "mbed_assert.h"
+
+namespace mbed {
+
+BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
+    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
+
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusOut::BusOut(PinName pins[16]) {
+    _nc_mask = 0;
+    for (int i=0; i<16; i++) {
+        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
+        if (pins[i] != NC) {
+            _nc_mask |= (1 << i);
+        }
+    }
+}
+
+BusOut::~BusOut() {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            delete _pin[i];
+        }
+    }
+}
+
+void BusOut::write(int value) {
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            _pin[i]->write((value >> i) & 1);
+        }
+    }
+}
+
+int BusOut::read() {
+    int v = 0;
+    for (int i=0; i<16; i++) {
+        if (_pin[i] != 0) {
+            v |= _pin[i]->read() << i;
+        }
+    }
+    return v;
+}
+
+#ifdef MBED_OPERATORS
+BusOut& BusOut::operator= (int v) {
+    write(v);
+    return *this;
+}
+
+BusOut& BusOut::operator= (BusOut& rhs) {
+    write(rhs.read());
+    return *this;
+}
+
+DigitalOut& BusOut::operator[] (int index) {
+    MBED_ASSERT(index >= 0 && index <= 16);
+    MBED_ASSERT(_pin[index]);
+    return *_pin[index];
+}
+
+BusOut::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/CAN.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,86 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "CAN.h"
+
+#if DEVICE_CAN
+
+#include "cmsis.h"
+
+namespace mbed {
+
+CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
+    can_init(&_can, rd, td);
+    can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
+}
+
+CAN::~CAN() {
+    can_irq_free(&_can);
+    can_free(&_can);
+}
+
+int CAN::frequency(int f) {
+    return can_frequency(&_can, f);
+}
+
+int CAN::write(CANMessage msg) {
+    return can_write(&_can, msg, 0);
+}
+
+int CAN::read(CANMessage &msg, int handle) {
+    return can_read(&_can, &msg, handle);
+}
+
+void CAN::reset() {
+    can_reset(&_can);
+}
+
+unsigned char CAN::rderror() {
+    return can_rderror(&_can);
+}
+
+unsigned char CAN::tderror() {
+    return can_tderror(&_can);
+}
+
+void CAN::monitor(bool silent) {
+    can_monitor(&_can, (silent) ? 1 : 0);
+}
+
+int CAN::mode(Mode mode) {
+    return can_mode(&_can, (CanMode)mode);
+}
+
+int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
+    return can_filter(&_can, id, mask, format, handle);
+}
+
+void CAN::attach(void (*fptr)(void), IrqType type) {
+    if (fptr) {
+        _irq[(CanIrqType)type].attach(fptr);
+        can_irq_set(&_can, (CanIrqType)type, 1);
+    } else {
+        can_irq_set(&_can, (CanIrqType)type, 0);
+    }
+}
+
+void CAN::_irq_handler(uint32_t id, CanIrqType type) {
+    CAN *handler = (CAN*)id;
+    handler->_irq[type].call();
+}
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/CallChain.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,90 @@
+#include "CallChain.h"
+#include "cmsis.h"
+
+namespace mbed {
+
+CallChain::CallChain(int size) : _chain(), _size(size), _elements(0) {
+    _chain = new pFunctionPointer_t[size]();
+}
+
+CallChain::~CallChain() {
+    clear();
+    delete _chain;
+}
+
+pFunctionPointer_t CallChain::add(void (*function)(void)) {
+    return common_add(new FunctionPointer(function));
+}
+
+pFunctionPointer_t CallChain::add_front(void (*function)(void)) {
+    return common_add_front(new FunctionPointer(function));
+}
+
+int CallChain::size() const {
+    return _elements;
+}
+
+pFunctionPointer_t CallChain::get(int i) const {
+    if (i < 0 || i >= _elements)
+        return NULL;
+    return _chain[i];
+}
+
+int CallChain::find(pFunctionPointer_t f) const {
+    for (int i = 0; i < _elements; i++)
+        if (f == _chain[i])
+            return i;
+    return -1;
+}
+
+void CallChain::clear() {
+    for(int i = 0; i < _elements; i ++) {
+        delete _chain[i];
+        _chain[i] = NULL;
+    }
+    _elements = 0;
+}
+
+bool CallChain::remove(pFunctionPointer_t f) {
+    int i;
+
+    if ((i = find(f)) == -1)
+        return false;
+    if (i != _elements - 1)
+        memmove(_chain + i, _chain + i + 1, (_elements - i - 1) * sizeof(pFunctionPointer_t));
+    delete f;
+    _elements --;
+    return true;
+}
+
+void CallChain::call() {
+    for(int i = 0; i < _elements; i++)
+        _chain[i]->call();
+}
+
+void CallChain::_check_size() {
+    if (_elements < _size)
+        return;
+    _size = (_size < 4) ? 4 : _size + 4;
+    pFunctionPointer_t* new_chain = new pFunctionPointer_t[_size]();
+    memcpy(new_chain, _chain, _elements * sizeof(pFunctionPointer_t));
+    delete _chain;
+    _chain = new_chain;
+}
+
+pFunctionPointer_t CallChain::common_add(pFunctionPointer_t pf) {
+    _check_size();
+    _chain[_elements] = pf;
+    _elements ++;
+    return pf;
+}
+
+pFunctionPointer_t CallChain::common_add_front(pFunctionPointer_t pf) {
+    _check_size();
+    memmove(_chain + 1, _chain, _elements * sizeof(pFunctionPointer_t));
+    _chain[0] = pf;
+    _elements ++;
+    return pf;
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/Ethernet.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ethernet.h"
+
+#if DEVICE_ETHERNET
+
+#include "ethernet_api.h"
+
+namespace mbed {
+
+Ethernet::Ethernet() {
+    ethernet_init();
+}
+
+Ethernet::~Ethernet() {
+    ethernet_free();
+}
+
+int Ethernet::write(const char *data, int size) {
+    return ethernet_write(data, size);
+}
+
+int Ethernet::send() {
+    return ethernet_send();
+}
+
+int Ethernet::receive() {
+    return ethernet_receive();
+}
+
+int Ethernet::read(char *data, int size) {
+    return ethernet_read(data, size);
+}
+
+void Ethernet::address(char *mac) {
+    return ethernet_address(mac);
+}
+
+int Ethernet::link() {
+    return ethernet_link();
+}
+
+void Ethernet::set_link(Mode mode) {
+    int speed = -1;
+    int duplex = 0;
+
+    switch(mode) {
+        case AutoNegotiate : speed = -1; duplex = 0; break;
+        case HalfDuplex10  : speed = 0;  duplex = 0; break;
+        case FullDuplex10  : speed = 0;  duplex = 1; break;
+        case HalfDuplex100 : speed = 1;  duplex = 0; break;
+        case FullDuplex100 : speed = 1;  duplex = 1; break;
+    }
+
+    ethernet_set_link(speed, duplex);
+}
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/FileBase.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,82 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileBase.h"
+
+namespace mbed {
+
+FileBase *FileBase::_head = NULL;
+
+FileBase::FileBase(const char *name, PathType t) : _next(NULL),
+                                                   _name(name),
+                                                   _path_type(t) {
+    if (name != NULL) {
+        // put this object at head of the list
+        _next = _head;
+        _head = this;
+    } else {
+        _next = NULL;
+    }
+}
+
+FileBase::~FileBase() {
+    if (_name != NULL) {
+        // remove this object from the list
+        if (_head == this) { // first in the list, so just drop me
+            _head = _next;
+        } else {             // find the object before me, then drop me
+            FileBase *p = _head;
+            while (p->_next != this) {
+                p = p->_next;
+            }
+            p->_next = _next;
+        }
+    }
+}
+
+FileBase *FileBase::lookup(const char *name, unsigned int len) {
+    FileBase *p = _head;
+    while (p != NULL) {
+        /* Check that p->_name matches name and is the correct length */
+        if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
+            return p;
+        }
+        p = p->_next;
+    }
+    return NULL;
+}
+
+FileBase *FileBase::get(int n) {
+    FileBase *p = _head;
+    int m = 0;
+    while (p != NULL) {
+        if (m == n) return p;
+
+        m++;
+        p = p->_next;
+    }
+    return NULL;
+}
+
+const char* FileBase::getName(void) {
+    return _name;
+}
+
+PathType FileBase::getPathType(void) {
+    return _path_type;
+}
+
+} // namespace mbed
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/FileLike.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,28 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileLike.h"
+
+namespace mbed {
+
+FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
+
+}
+
+FileLike::~FileLike() {
+
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/FilePath.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,76 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FilePath.h"
+
+namespace mbed {
+
+FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
+    if ((file_path[0] != '/') || (file_path[1] == 0)) return;
+
+    const char* file_system = &file_path[1];
+    file_name = file_system;
+    int len = 0;
+    while (true) {
+        char c = *file_name;
+        if (c == '/') { // end of object name
+            file_name++; // point to one char after the '/'
+            break;
+        }
+        if (c == 0) { // end of object name, with no filename
+            break;
+        }
+        len++;
+        file_name++;
+    }
+
+    fb = FileBase::lookup(file_system, len);
+}
+
+const char* FilePath::fileName(void) {
+    return file_name;
+}
+
+bool FilePath::isFileSystem(void) {
+    if (NULL == fb)
+        return false;
+    return (fb->getPathType() == FileSystemPathType);
+}
+
+FileSystemLike* FilePath::fileSystem(void) {
+    if (isFileSystem()) {
+        return (FileSystemLike*)fb;
+    }
+    return NULL;
+}
+
+bool FilePath::isFile(void) {
+    if (NULL == fb)
+        return false;
+    return (fb->getPathType() == FilePathType);
+}
+
+FileLike* FilePath::file(void) {
+    if (isFile()) {
+        return (FileLike*)fb;
+    }
+    return NULL;
+}
+
+bool FilePath::exists(void) {
+    return fb != NULL;
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/FileSystemLike.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "FileSystemLike.h"
+
+namespace mbed {
+
+class BaseDirHandle : public DirHandle {
+public:
+    /*
+      We keep track of our current location as the n'th object in the
+      FileSystemLike list. Using a Base* instead would cause problems if that
+      object were to be destroyed between readdirs.
+      Using this method does mean though that destroying/creating objects can
+      give unusual results from readdir.
+    */
+    off_t n;
+    struct dirent cur_entry;
+
+    BaseDirHandle() : n(0), cur_entry() {
+    }
+
+    virtual int closedir() {
+        delete this;
+        return 0;
+    }
+
+    virtual struct dirent *readdir() {
+        FileBase *ptr = FileBase::get(n);
+        if (ptr == NULL) return NULL;
+
+        /* Increment n, so next readdir gets the next item */
+        n++;
+
+        /* Setup cur entry and return a pointer to it */
+        std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
+        return &cur_entry;
+    }
+
+    virtual off_t telldir() {
+        return n;
+    }
+
+    virtual void seekdir(off_t offset) {
+        n = offset;
+    }
+
+    virtual void rewinddir() {
+        n = 0;
+    }
+};
+
+FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
+
+}
+
+FileSystemLike::~FileSystemLike() {
+
+}
+
+DirHandle *FileSystemLike::opendir() {
+    return new BaseDirHandle();
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/InterruptIn.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,85 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "InterruptIn.h"
+
+#if DEVICE_INTERRUPTIN
+
+namespace mbed {
+
+InterruptIn::InterruptIn(PinName pin) : gpio(),
+                                        gpio_irq(),
+                                        _rise(),
+                                        _fall() {
+    gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
+    gpio_init_in(&gpio, pin);
+}
+
+InterruptIn::~InterruptIn() {
+    gpio_irq_free(&gpio_irq);
+}
+
+int InterruptIn::read() {
+    return gpio_read(&gpio);
+}
+
+void InterruptIn::mode(PinMode pull) {
+    gpio_mode(&gpio, pull);
+}
+
+void InterruptIn::rise(void (*fptr)(void)) {
+    if (fptr) {
+        _rise.attach(fptr);
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
+    } else {
+        gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
+    }
+}
+
+void InterruptIn::fall(void (*fptr)(void)) {
+    if (fptr) {
+        _fall.attach(fptr);
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
+    } else {
+        gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
+    }
+}
+
+void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
+    InterruptIn *handler = (InterruptIn*)id;
+    switch (event) {
+        case IRQ_RISE: handler->_rise.call(); break;
+        case IRQ_FALL: handler->_fall.call(); break;
+        case IRQ_NONE: break;
+    }
+}
+
+void InterruptIn::enable_irq() {
+    gpio_irq_enable(&gpio_irq);
+}
+
+void InterruptIn::disable_irq() {
+    gpio_irq_disable(&gpio_irq);
+}
+
+#ifdef MBED_OPERATORS
+InterruptIn::operator int() {
+    return read();
+}
+#endif
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/InterruptManager.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,93 @@
+#include "cmsis.h"
+#if defined(NVIC_NUM_VECTORS)
+
+#include "InterruptManager.h"
+#include <string.h>
+
+#define CHAIN_INITIAL_SIZE    4
+
+namespace mbed {
+
+typedef void (*pvoidf)(void);
+
+InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
+
+InterruptManager* InterruptManager::get() {
+    if (NULL == _instance)
+        _instance = new InterruptManager();
+    return _instance;
+}
+
+InterruptManager::InterruptManager() {
+    memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
+}
+
+void InterruptManager::destroy() {
+    // Not a good idea to call this unless NO interrupt at all
+    // is under the control of the handler; otherwise, a system crash
+    // is very likely to occur
+    if (NULL != _instance) {
+        delete _instance;
+        _instance = (InterruptManager*)NULL;
+    }
+}
+
+InterruptManager::~InterruptManager() {
+    for(int i = 0; i < NVIC_NUM_VECTORS; i++)
+        if (NULL != _chains[i])
+            delete _chains[i];
+}
+
+bool InterruptManager::must_replace_vector(IRQn_Type irq) {
+    int irq_pos = get_irq_index(irq);
+
+    if (NULL == _chains[irq_pos]) {
+        _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
+        _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
+        return true;
+    }
+    return false;
+}
+
+pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
+    int irq_pos = get_irq_index(irq);
+    bool change = must_replace_vector(irq);
+
+    pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
+    if (change)
+        NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
+    return pf;
+}
+
+bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
+    int irq_pos = get_irq_index(irq);
+
+    if (NULL == _chains[irq_pos])
+        return false;
+    if (!_chains[irq_pos]->remove(handler))
+        return false;
+    // If there's a single function left in the chain, swith the interrupt vector
+    // to call that function directly. This way we save both time and space.
+    if (_chains[irq_pos]->size() == 1 && NULL != _chains[irq_pos]->get(0)->get_function()) {
+        NVIC_SetVector(irq, (uint32_t)_chains[irq_pos]->get(0)->get_function());
+        delete _chains[irq_pos];
+        _chains[irq_pos] = (CallChain*) NULL;
+    }
+    return true;
+}
+
+void InterruptManager::irq_helper() {
+    _chains[__get_IPSR()]->call();
+}
+
+int InterruptManager::get_irq_index(IRQn_Type irq) {
+    return (int)irq + NVIC_USER_IRQ_OFFSET;
+}
+
+void InterruptManager::static_irq_helper() {
+    InterruptManager::get()->irq_helper();
+}
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/LocalFileSystem.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,223 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "LocalFileSystem.h"
+
+#if DEVICE_LOCALFILESYSTEM
+
+#include "semihost_api.h"
+#include <string.h>
+#include <stdio.h>
+
+namespace mbed {
+
+/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
+typedef struct {
+    unsigned char  hr;   /* Hours    [0..23]                  */
+    unsigned char  min;  /* Minutes  [0..59]                  */
+    unsigned char  sec;  /* Seconds  [0..59]                  */
+    unsigned char  day;  /* Day      [1..31]                  */
+    unsigned char  mon;  /* Month    [1..12]                  */
+    unsigned short year; /* Year     [1980..2107]             */
+} FTIME;
+
+typedef struct {         /* File Search info record           */
+    char  name[32];      /* File name                         */
+    long  size;          /* File size in bytes                */
+    int   fileID;        /* System File Identification        */
+    FTIME create_time;   /* Date & time file was created      */
+    FTIME write_time;    /* Date & time of last write         */
+} XFINFO;
+
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
+#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
+
+static int xffind (const char *pattern, XFINFO *info) {
+    unsigned param[4];
+
+    param[0] = (unsigned long)pattern;
+    param[1] = (unsigned long)strlen(pattern);
+    param[2] = (unsigned long)info;
+    param[3] = (unsigned long)sizeof(XFINFO);
+
+    return __semihost(USR_XFFIND, param);
+}
+
+#define OPEN_R          0
+#define OPEN_B          1
+#define OPEN_PLUS       2
+#define OPEN_W          4
+#define OPEN_A          8
+#define OPEN_INVALID   -1
+
+int posix_to_semihost_open_flags(int flags) {
+    /* POSIX flags -> semihosting open mode */
+    int openmode;
+    if (flags & O_RDWR) {
+        /* a plus mode */
+        openmode = OPEN_PLUS;
+        if (flags & O_APPEND) {
+            openmode |= OPEN_A;
+        } else if (flags & O_TRUNC) {
+            openmode |= OPEN_W;
+        } else {
+            openmode |= OPEN_R;
+        }
+    } else if (flags & O_WRONLY) {
+        /* write or append */
+        if (flags & O_APPEND) {
+            openmode = OPEN_A;
+        } else {
+            openmode = OPEN_W;
+        }
+    } else if (flags == O_RDONLY) {
+        /* read mode */
+        openmode = OPEN_R;
+    } else {
+        /* invalid flags */
+        openmode = OPEN_INVALID;
+    }
+
+    return openmode;
+}
+
+FILEHANDLE local_file_open(const char* name, int flags) {
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return (FILEHANDLE)NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return (FILEHANDLE)NULL;
+    }
+
+    return fh;
+}
+
+LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) {
+}
+
+int LocalFileHandle::close() {
+    int retval = semihost_close(_fh);
+    delete this;
+    return retval;
+}
+
+ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
+    ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
+    n = length - n; // number of characters written
+    pos += n;
+    return n;
+}
+
+ssize_t LocalFileHandle::read(void *buffer, size_t length) {
+    ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
+    n = length - n; // number of characters read
+    pos += n;
+    return n;
+}
+
+int LocalFileHandle::isatty() {
+    return semihost_istty(_fh);
+}
+
+off_t LocalFileHandle::lseek(off_t position, int whence) {
+    if (whence == SEEK_CUR) {
+        position += pos;
+    } else if (whence == SEEK_END) {
+        position += semihost_flen(_fh);
+    } /* otherwise SEEK_SET, so position is fine */
+
+    /* Always seems to return -1, so just ignore for now. */
+    semihost_seek(_fh, position);
+    pos = position;
+    return position;
+}
+
+int LocalFileHandle::fsync() {
+    return semihost_ensure(_fh);
+}
+
+off_t LocalFileHandle::flen() {
+    return semihost_flen(_fh);
+}
+
+class LocalDirHandle : public DirHandle {
+
+public:
+    struct dirent cur_entry;
+    XFINFO info;
+
+    LocalDirHandle() : cur_entry(), info() {
+    }
+
+    virtual int closedir() {
+        delete this;
+        return 0;
+    }
+
+    virtual struct dirent *readdir() {
+        if (xffind("*", &info)!=0) {
+            return NULL;
+        }
+        memcpy(cur_entry.d_name, info.name, sizeof(info.name));
+        return &cur_entry;
+    }
+
+    virtual void rewinddir() {
+        info.fileID = 0;
+    }
+
+    virtual off_t telldir() {
+        return info.fileID;
+    }
+
+    virtual void seekdir(off_t offset) {
+        info.fileID = offset;
+    }
+};
+
+FileHandle *LocalFileSystem::open(const char* name, int flags) {
+    /* reject filenames with / in them */
+    for (const char *tmp = name; *tmp; tmp++) {
+        if (*tmp == '/') {
+            return NULL;
+        }
+    }
+
+    int openmode = posix_to_semihost_open_flags(flags);
+    if (openmode == OPEN_INVALID) {
+        return NULL;
+    }
+
+    FILEHANDLE fh = semihost_open(name, openmode);
+    if (fh == -1) {
+        return NULL;
+    }
+    return new LocalFileHandle(fh);
+}
+
+int LocalFileSystem::remove(const char *filename) {
+    return semihost_remove(filename);
+}
+
+DirHandle *LocalFileSystem::opendir(const char *name) {
+    return new LocalDirHandle();
+}
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/RawSerial.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,67 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "RawSerial.h"
+#include "wait_api.h"
+#include <cstdarg>
+
+#if DEVICE_SERIAL
+
+#define STRING_STACK_LIMIT    120
+
+namespace mbed {
+
+RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
+}
+
+int RawSerial::getc() {
+    return _base_getc();
+}
+
+int RawSerial::putc(int c) {
+    return _base_putc(c);
+}
+
+int RawSerial::puts(const char *str) {
+    while (*str)
+        putc(*str ++);
+    return 0;
+}
+
+// Experimental support for printf in RawSerial. No Stream inheritance
+// means we can't call printf() directly, so we use sprintf() instead.
+// We only call malloc() for the sprintf() buffer if the buffer
+// length is above a certain threshold, otherwise we use just the stack.
+int RawSerial::printf(const char *format, ...) {
+    std::va_list arg;
+    va_start(arg, format);
+    int len = vsnprintf(NULL, 0, format, arg);
+    if (len < STRING_STACK_LIMIT) {
+        char temp[STRING_STACK_LIMIT];
+        vsprintf(temp, format, arg);
+        puts(temp);
+    } else {
+        char *temp = new char[len + 1];
+        vsprintf(temp, format, arg);
+        puts(temp);
+        delete[] temp;
+    }
+    va_end(arg);
+    return len;
+}
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/SPI.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,180 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SPI.h"
+
+#if DEVICE_SPI
+
+namespace mbed {
+
+#if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
+CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
+#endif
+
+SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
+        _spi(),
+#if DEVICE_SPI_ASYNCH
+        _irq(this),
+        _usage(DMA_USAGE_NEVER),
+#endif
+        _bits(8),
+        _mode(0),
+        _hz(1000000) {
+    spi_init(&_spi, mosi, miso, sclk, ssel);
+    spi_format(&_spi, _bits, _mode, 0);
+    spi_frequency(&_spi, _hz);
+}
+
+void SPI::format(int bits, int mode) {
+    _bits = bits;
+    _mode = mode;
+    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+    aquire();
+}
+
+void SPI::frequency(int hz) {
+    _hz = hz;
+    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
+    aquire();
+}
+
+SPI* SPI::_owner = NULL;
+
+// ignore the fact there are multiple physical spis, and always update if it wasnt us last
+void SPI::aquire() {
+     if (_owner != this) {
+        spi_format(&_spi, _bits, _mode, 0);
+        spi_frequency(&_spi, _hz);
+        _owner = this;
+    }
+}
+
+int SPI::write(int value) {
+    aquire();
+    return spi_master_write(&_spi, value);
+}
+
+#if DEVICE_SPI_ASYNCH
+
+int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+    if (spi_active(&_spi)) {
+        return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+    }
+    start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
+    return 0;
+}
+
+void SPI::abort_transfer()
+{
+    spi_abort_asynch(&_spi);
+#if TRANSACTION_QUEUE_SIZE_SPI
+    dequeue_transaction();
+#endif
+}
+
+
+void SPI::clear_transfer_buffer()
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+    _transaction_buffer.reset();
+#endif
+}
+
+void SPI::abort_all_transfers()
+{
+    clear_transfer_buffer();
+    abort_transfer();
+}
+
+int SPI::set_dma_usage(DMAUsage usage)
+{
+    if (spi_active(&_spi)) {
+        return -1;
+    }
+    _usage = usage;
+    return  0;
+}
+
+int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+#if TRANSACTION_QUEUE_SIZE_SPI
+    transaction_t t;
+
+    t.tx_buffer = const_cast<void *>(tx_buffer);
+    t.tx_length = tx_length;
+    t.rx_buffer = rx_buffer;
+    t.rx_length = rx_length;
+    t.event = event;
+    t.callback = callback;
+    t.width = bit_width;
+    Transaction<SPI> transaction(this, t);
+    if (_transaction_buffer.full()) {
+        return -1; // the buffer is full
+    } else {
+        _transaction_buffer.push(transaction);
+        return 0;
+    }
+#else
+    return -1;
+#endif
+}
+
+void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
+{
+    aquire();
+    _callback = callback;
+    _irq.callback(&SPI::irq_handler_asynch);
+    spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
+}
+
+#if TRANSACTION_QUEUE_SIZE_SPI
+
+void SPI::start_transaction(transaction_t *data)
+{
+    start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
+}
+
+void SPI::dequeue_transaction()
+{
+    Transaction<SPI> t;
+    if (_transaction_buffer.pop(t)) {
+        SPI* obj = t.get_object();
+        transaction_t* data = t.get_transaction();
+        obj->start_transaction(data);
+    }
+}
+
+#endif
+
+void SPI::irq_handler_asynch(void)
+{
+    int event = spi_irq_handler_asynch(&_spi);
+    if (_callback && (event & SPI_EVENT_ALL)) {
+        _callback.call(event & SPI_EVENT_ALL);
+    }
+#if TRANSACTION_QUEUE_SIZE_SPI
+    if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
+        // SPI peripheral is free (event happend), dequeue transaction
+        dequeue_transaction();
+    }
+#endif
+}
+
+#endif
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/Serial.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,36 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Serial.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+Serial::Serial(PinName tx, PinName rx, const char *name) : SerialBase(tx, rx), Stream(name) {
+}
+
+int Serial::_getc() {
+    return _base_getc();
+}
+
+int Serial::_putc(int c) {
+    return _base_putc(c);
+}
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/SerialBase.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,212 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "SerialBase.h"
+#include "wait_api.h"
+
+#if DEVICE_SERIAL
+
+namespace mbed {
+
+SerialBase::SerialBase(PinName tx, PinName rx) :
+#if DEVICE_SERIAL_ASYNCH
+                                                 _thunk_irq(this), _tx_usage(DMA_USAGE_NEVER),
+                                                 _rx_usage(DMA_USAGE_NEVER),
+#endif
+                                                _serial(), _baud(9600) {
+    serial_init(&_serial, tx, rx);
+    serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
+}
+
+void SerialBase::baud(int baudrate) {
+    serial_baud(&_serial, baudrate);
+    _baud = baudrate;
+}
+
+void SerialBase::format(int bits, Parity parity, int stop_bits) {
+    serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
+}
+
+int SerialBase::readable() {
+    return serial_readable(&_serial);
+}
+
+
+int SerialBase::writeable() {
+    return serial_writable(&_serial);
+}
+
+void SerialBase::attach(void (*fptr)(void), IrqType type) {
+    if (fptr) {
+        _irq[type].attach(fptr);
+        serial_irq_set(&_serial, (SerialIrq)type, 1);
+    } else {
+        serial_irq_set(&_serial, (SerialIrq)type, 0);
+    }
+}
+
+void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
+    SerialBase *handler = (SerialBase*)id;
+    handler->_irq[irq_type].call();
+}
+
+int SerialBase::_base_getc() {
+    return serial_getc(&_serial);
+}
+
+int SerialBase::_base_putc(int c) {
+    serial_putc(&_serial, c);
+    return c;
+}
+
+void SerialBase::send_break() {
+  // Wait for 1.5 frames before clearing the break condition
+  // This will have different effects on our platforms, but should
+  // ensure that we keep the break active for at least one frame.
+  // We consider a full frame (1 start bit + 8 data bits bits +
+  // 1 parity bit + 2 stop bits = 12 bits) for computation.
+  // One bit time (in us) = 1000000/_baud
+  // Twelve bits: 12000000/baud delay
+  // 1.5 frames: 18000000/baud delay
+  serial_break_set(&_serial);
+  wait_us(18000000/_baud);
+  serial_break_clear(&_serial);
+}
+
+#if DEVICE_SERIAL_FC
+void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
+    FlowControl flow_type = (FlowControl)type;
+    switch(type) {
+        case RTS:
+            serial_set_flow_control(&_serial, flow_type, flow1, NC);
+            break;
+
+        case CTS:
+            serial_set_flow_control(&_serial, flow_type, NC, flow1);
+            break;
+
+        case RTSCTS:
+        case Disabled:
+            serial_set_flow_control(&_serial, flow_type, flow1, flow2);
+            break;
+
+        default:
+            break;
+    }
+}
+#endif
+
+#if DEVICE_SERIAL_ASYNCH
+
+int SerialBase::write(const uint8_t *buffer, int length, const event_callback_t& callback, int event)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_write((void *)buffer, length, 8, callback, event);
+    return 0;
+}
+
+int SerialBase::write(const uint16_t *buffer, int length, const event_callback_t& callback, int event)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_write((void *)buffer, length, 16, callback, event);
+    return 0;
+}
+
+void SerialBase::start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event)
+{
+    _tx_callback = callback;
+
+    _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+    serial_tx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, _tx_usage);
+}
+
+void SerialBase::abort_write(void)
+{
+    serial_tx_abort_asynch(&_serial);
+}
+
+void SerialBase::abort_read(void)
+{
+    serial_rx_abort_asynch(&_serial);
+}
+
+int SerialBase::set_dma_usage_tx(DMAUsage usage)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1;
+    }
+    _tx_usage = usage;
+    return 0;
+}
+
+int SerialBase::set_dma_usage_rx(DMAUsage usage)
+{
+    if (serial_tx_active(&_serial)) {
+        return -1;
+    }
+    _rx_usage = usage;
+    return 0;
+}
+
+int SerialBase::read(uint8_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    if (serial_rx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_read((void*)buffer, length, 8, callback, event, char_match);
+    return 0;
+}
+
+
+int SerialBase::read(uint16_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    if (serial_rx_active(&_serial)) {
+        return -1; // transaction ongoing
+    }
+    start_read((void*)buffer, length, 16, callback, event, char_match);
+    return 0;
+}
+
+
+void SerialBase::start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match)
+{
+    _rx_callback = callback;
+    _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
+    serial_rx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, char_match, _rx_usage);
+}
+
+void SerialBase::interrupt_handler_asynch(void)
+{
+    int event = serial_irq_handler_asynch(&_serial);
+    int rx_event = event & SERIAL_EVENT_RX_MASK;
+    if (_rx_callback && rx_event) {
+        _rx_callback.call(rx_event);
+    }
+
+    int tx_event = event & SERIAL_EVENT_TX_MASK;
+    if (_tx_callback && tx_event) {
+        _tx_callback.call(tx_event);
+    }
+}
+
+#endif
+
+} // namespace mbed
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/Stream.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,111 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Stream.h"
+
+#include <cstdarg>
+
+namespace mbed {
+
+Stream::Stream(const char *name) : FileLike(name), _file(NULL) {
+    /* open ourselves */
+    char buf[12]; /* :0x12345678 + null byte */
+    std::sprintf(buf, ":%p", this);
+    _file = std::fopen(buf, "w+");
+    mbed_set_unbuffered_stream(_file);
+}
+
+Stream::~Stream() {
+    fclose(_file);
+}
+
+int Stream::putc(int c) {
+    fflush(_file);
+    return std::fputc(c, _file);
+}
+int Stream::puts(const char *s) {
+    fflush(_file);
+    return std::fputs(s, _file);
+}
+int Stream::getc() {
+    fflush(_file);
+    return mbed_getc(_file);   
+}
+char* Stream::gets(char *s, int size) {
+    fflush(_file);
+    return mbed_gets(s,size,_file);
+}
+
+int Stream::close() {
+    return 0;
+}
+
+ssize_t Stream::write(const void* buffer, size_t length) {
+    const char* ptr = (const char*)buffer;
+    const char* end = ptr + length;
+    while (ptr != end) {
+        if (_putc(*ptr++) == EOF) {
+            break;
+        }
+    }
+    return ptr - (const char*)buffer;
+}
+
+ssize_t Stream::read(void* buffer, size_t length) {
+    char* ptr = (char*)buffer;
+    char* end = ptr + length;
+    while (ptr != end) {
+        int c = _getc();
+        if (c==EOF) break;
+        *ptr++ = c;
+    }
+    return ptr - (const char*)buffer;
+}
+
+off_t Stream::lseek(off_t offset, int whence) {
+    return 0;
+}
+
+int Stream::isatty() {
+    return 0;
+}
+
+int Stream::fsync() {
+    return 0;
+}
+
+off_t Stream::flen() {
+    return 0;
+}
+
+int Stream::printf(const char* format, ...) {
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfprintf(_file, format, arg);
+    va_end(arg);
+    return r;
+}
+
+int Stream::scanf(const char* format, ...) {
+    std::va_list arg;
+    va_start(arg, format);
+    fflush(_file);
+    int r = vfscanf(_file, format, arg);
+    va_end(arg);
+    return r;
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/Ticker.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,40 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Ticker.h"
+
+#include "TimerEvent.h"
+#include "FunctionPointer.h"
+#include "ticker_api.h"
+
+namespace mbed {
+
+void Ticker::detach() {
+    remove();
+    _function.attach(0);
+}
+
+void Ticker::setup(timestamp_t t) {
+    remove();
+    _delay = t;
+    insert(_delay + ticker_read(_ticker_data));
+}
+
+void Ticker::handler() {
+    insert(event.timestamp + _delay);
+    _function.call();
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/Timeout.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,24 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timeout.h"
+
+namespace mbed {
+
+void Timeout::handler() {
+    _function.call();
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/Timer.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "Timer.h"
+#include "ticker_api.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()) {
+    reset();
+}
+
+Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data) {
+    reset();
+}
+
+void Timer::start() {
+    if (!_running) {
+        _start = ticker_read(_ticker_data);
+        _running = 1;
+    }
+}
+
+void Timer::stop() {
+    _time += slicetime();
+    _running = 0;
+}
+
+int Timer::read_us() {
+    return _time + slicetime();
+}
+
+float Timer::read() {
+    return (float)read_us() / 1000000.0f;
+}
+
+int Timer::read_ms() {
+    return read_us() / 1000;
+}
+
+int Timer::slicetime() {
+    if (_running) {
+        return ticker_read(_ticker_data) - _start;
+    } else {
+        return 0;
+    }
+}
+
+void Timer::reset() {
+    _start = ticker_read(_ticker_data);
+    _time = 0;
+}
+
+#ifdef MBED_OPERATORS
+Timer::operator float() {
+    return read();
+}
+#endif
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/TimerEvent.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,51 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "TimerEvent.h"
+#include "cmsis.h"
+
+#include <stddef.h>
+#include "ticker_api.h"
+#include "us_ticker_api.h"
+
+namespace mbed {
+
+TimerEvent::TimerEvent() : event(), _ticker_data(get_us_ticker_data()) {
+    ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data) {
+    ticker_set_handler(_ticker_data, (&TimerEvent::irq));
+}
+
+void TimerEvent::irq(uint32_t id) {
+    TimerEvent *timer_event = (TimerEvent*)id;
+    timer_event->handler();
+}
+
+TimerEvent::~TimerEvent() {
+    remove();
+}
+
+// insert in to linked list
+void TimerEvent::insert(timestamp_t timestamp) {
+    ticker_insert_event(_ticker_data, &event, timestamp, (uint32_t)this);
+}
+
+void TimerEvent::remove() {
+    ticker_remove_event(_ticker_data, &event);
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/analogin_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,185 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogin_api.h"
+
+#if DEVICE_ANALOGIN
+
+#include "wait_api.h"
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+ADC_HandleTypeDef AdcHandle;
+
+int adc_inited = 0;
+
+void analogin_init(analogin_t *obj, PinName pin)
+{
+    // Get the peripheral name from the pin and assign it to the object
+    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
+    MBED_ASSERT(obj->adc != (ADCName)NC);
+
+    // Get the pin function and assign the used channel to the object
+    uint32_t function = pinmap_function(pin, PinMap_ADC);
+    MBED_ASSERT(function != (uint32_t)NC);
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Configure GPIO
+    pinmap_pinout(pin, PinMap_ADC);
+
+    // Save pin number for the read function
+    obj->pin = pin;
+
+    // The ADC initialization is done once
+    if (adc_inited == 0) {
+        adc_inited = 1;
+
+        AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+
+        // Enable ADC clock
+        __ADC1_CLK_ENABLE();
+
+        // Configure ADC
+        AdcHandle.Init.OversamplingMode      = DISABLE;
+        AdcHandle.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV1;
+        AdcHandle.Init.Resolution            = ADC_RESOLUTION12b;
+        AdcHandle.Init.SamplingTime          = ADC_SAMPLETIME_41CYCLES_5;
+        AdcHandle.Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD;
+        AdcHandle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
+        AdcHandle.Init.ContinuousConvMode    = DISABLE;
+        AdcHandle.Init.DiscontinuousConvMode = DISABLE;
+        AdcHandle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIG_EDGE_NONE;
+        AdcHandle.Init.ExternalTrigConv      = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here
+        AdcHandle.Init.DMAContinuousRequests = DISABLE;
+        AdcHandle.Init.EOCSelection          = EOC_SINGLE_CONV;
+        AdcHandle.Init.Overrun               = OVR_DATA_OVERWRITTEN;
+        AdcHandle.Init.LowPowerAutoWait      = ENABLE;
+        AdcHandle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz
+        AdcHandle.Init.LowPowerAutoPowerOff  = DISABLE;
+
+        if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
+            error("Cannot initialize ADC");
+        }
+
+        // Calibration
+        HAL_ADCEx_Calibration_Start(&AdcHandle, ADC_SINGLE_ENDED);
+
+        __HAL_ADC_ENABLE(&AdcHandle);
+    }
+}
+
+static inline uint16_t adc_read(analogin_t *obj)
+{
+    ADC_ChannelConfTypeDef sConfig = {0};
+
+    AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
+
+    // Configure ADC channel
+    switch (obj->channel) {
+        case 0:
+            sConfig.Channel = ADC_CHANNEL_0;
+            break;
+        case 1:
+            sConfig.Channel = ADC_CHANNEL_1;
+            break;
+        case 2:
+            sConfig.Channel = ADC_CHANNEL_2;
+            break;
+        case 3:
+            sConfig.Channel = ADC_CHANNEL_3;
+            break;
+        case 4:
+            sConfig.Channel = ADC_CHANNEL_4;
+            break;
+        case 5:
+            sConfig.Channel = ADC_CHANNEL_5;
+            break;
+        case 6:
+            sConfig.Channel = ADC_CHANNEL_6;
+            break;
+        case 7:
+            sConfig.Channel = ADC_CHANNEL_7;
+            break;
+        case 8:
+            sConfig.Channel = ADC_CHANNEL_8;
+            break;
+        case 9:
+            sConfig.Channel = ADC_CHANNEL_9;
+            break;
+        case 10:
+            sConfig.Channel = ADC_CHANNEL_10;
+            break;
+        case 11:
+            sConfig.Channel = ADC_CHANNEL_11;
+            break;
+        case 12:
+            sConfig.Channel = ADC_CHANNEL_12;
+            break;
+        case 13:
+            sConfig.Channel = ADC_CHANNEL_13;
+            break;
+        case 14:
+            sConfig.Channel = ADC_CHANNEL_14;
+            break;
+        case 15:
+            sConfig.Channel = ADC_CHANNEL_15;
+            break;
+        default:
+            return 0;
+    }
+
+    ADC1->CHSELR = 0; // [TODO] Workaround. To be removed after Cube driver is corrected.
+    HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
+
+    HAL_ADC_Start(&AdcHandle); // Start conversion
+
+    // Wait end of conversion and get value
+    if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
+        return (HAL_ADC_GetValue(&AdcHandle));
+    } else {
+        return 0;
+    }
+}
+
+uint16_t analogin_read_u16(analogin_t *obj)
+{
+    uint16_t value = adc_read(obj);
+    // 12-bit to 16-bit conversion
+    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
+    return value;
+}
+
+float analogin_read(analogin_t *obj)
+{
+    uint16_t value = adc_read(obj);
+    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/analogout_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,168 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "mbed_assert.h"
+#include "analogout_api.h"
+
+#if DEVICE_ANALOGOUT
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+#define DAC_RANGE (0xFFF) // 12 bits
+
+static DAC_HandleTypeDef DacHandle;
+
+// These variables are used for the "free" function
+static int channel1_used = 0;
+static int channel2_used = 0;
+
+void analogout_init(dac_t *obj, PinName pin)
+{
+    DAC_ChannelConfTypeDef sConfig;
+
+    // Get the peripheral name from the pin and assign it to the object
+    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
+    MBED_ASSERT(obj->dac != (DACName)NC);
+
+    // Get the pin function and assign the used channel to the object
+    uint32_t function = pinmap_function(pin, PinMap_DAC);
+    MBED_ASSERT(function != (uint32_t)NC);
+    obj->channel = STM_PIN_CHANNEL(function);
+
+    // Configure GPIO
+    pinmap_pinout(pin, PinMap_DAC);
+
+    // Save the pin for future use
+    obj->pin = pin;
+
+    // Enable DAC clock
+    __DAC_CLK_ENABLE();
+
+    // Configure DAC
+    DacHandle.Instance = DAC;
+
+    sConfig.DAC_Trigger      = DAC_TRIGGER_NONE;
+    sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
+
+#if defined(DAC_CHANNEL_2)
+    if (obj->channel == 2) {
+        if (HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2) != HAL_OK) {
+            error("Cannot configure DAC channel 2");
+        }
+        channel2_used = 1;
+    } else
+#endif
+    {
+        // channel 1 per default
+        if (HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1) != HAL_OK) {
+            error("Cannot configure DAC channel 1");
+        }
+        obj->channel = 1;
+        channel1_used = 1;
+    }
+
+    analogout_write_u16(obj, 0);
+}
+
+void analogout_free(dac_t *obj)
+{
+    // Reset DAC and disable clock
+    if (obj->channel == 1) channel1_used = 0;
+    if (obj->channel == 2) channel2_used = 0;
+
+    if ((channel1_used == 0) && (channel2_used == 0)) {
+        __DAC_FORCE_RESET();
+        __DAC_RELEASE_RESET();
+        __DAC_CLK_DISABLE();
+    }
+
+    // Configure GPIO
+    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+static inline void dac_write(dac_t *obj, uint16_t value)
+{
+    if (obj->channel == 1) {
+        HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value);
+        HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1);
+    }
+#if defined(DAC_CHANNEL_2)
+    if (obj->channel == 2) {
+        HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value);
+        HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2);
+    }
+#endif
+}
+
+static inline int dac_read(dac_t *obj)
+{
+    if (obj->channel == 1) {
+        return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1);
+    }
+#if defined(DAC_CHANNEL_2)
+    if (obj->channel == 2) {
+        return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2);
+    }
+#endif
+    return 0;
+}
+
+void analogout_write(dac_t *obj, float value)
+{
+    if (value < 0.0f) {
+        dac_write(obj, 0); // Min value
+    } else if (value > 1.0f) {
+        dac_write(obj, (uint16_t)DAC_RANGE); // Max value
+    } else {
+        dac_write(obj, (uint16_t)(value * (float)DAC_RANGE));
+    }
+}
+
+void analogout_write_u16(dac_t *obj, uint16_t value)
+{
+    if (value > (uint16_t)DAC_RANGE) {
+        dac_write(obj, (uint16_t)DAC_RANGE); // Max value
+    } else {
+        dac_write(obj, value);
+    }
+}
+
+float analogout_read(dac_t *obj)
+{
+    uint32_t value = dac_read(obj);
+    return (float)((float)value * (1.0f / (float)DAC_RANGE));
+}
+
+uint16_t analogout_read_u16(dac_t *obj)
+{
+    return (uint16_t)dac_read(obj);
+}
+
+#endif // DEVICE_ANALOGOUT

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/assert.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,22 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "mbed_assert.h"
+#include "mbed_error.h"
+
+void mbed_assert_internal(const char *expr, const char *file, int line)
+{
+    error("mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/board.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,59 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "toolchain.h"
+#include "mbed_interface.h"
+
+WEAK void mbed_die(void) {
+#if !defined (NRF51_H) && !defined(TARGET_EFM32)
+	__disable_irq();	// dont allow interrupts to disturb the flash pattern
+#endif
+#if   (DEVICE_ERROR_RED == 1)
+    gpio_t led_red; gpio_init_out(&led_red, LED_RED);
+#elif (DEVICE_ERROR_PATTERN == 1)
+    gpio_t led_1; gpio_init_out(&led_1, LED1);
+    gpio_t led_2; gpio_init_out(&led_2, LED2);
+    gpio_t led_3; gpio_init_out(&led_3, LED3);
+    gpio_t led_4; gpio_init_out(&led_4, LED4);
+#endif
+
+    while (1) {
+#if   (DEVICE_ERROR_RED == 1)
+        gpio_write(&led_red, 1);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+        gpio_write(&led_1, 1);
+        gpio_write(&led_2, 0);
+        gpio_write(&led_3, 0);
+        gpio_write(&led_4, 1);
+#endif
+
+        wait_ms(150);
+
+#if   (DEVICE_ERROR_RED == 1)
+        gpio_write(&led_red, 0);
+
+#elif (DEVICE_ERROR_PATTERN == 1)
+        gpio_write(&led_1, 0);
+        gpio_write(&led_2, 1);
+        gpio_write(&led_3, 1);
+        gpio_write(&led_4, 0);
+#endif
+
+        wait_ms(150);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/error.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,33 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdlib.h>
+#include <stdarg.h>
+#include "device.h"
+#include "toolchain.h"
+#include "mbed_error.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+
+WEAK void error(const char* format, ...) {
+#if DEVICE_STDIO_MESSAGES
+    va_list arg;
+    va_start(arg, format);
+    vfprintf(stderr, format, arg);
+    va_end(arg);
+#endif
+    exit(1);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/gpio.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,61 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "gpio_api.h"
+
+static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
+{
+    gpio_init(gpio, pin);
+    if (pin != NC) {
+        gpio_dir(gpio, PIN_INPUT);
+        gpio_mode(gpio, mode);
+    }
+}
+
+static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
+{
+    gpio_init(gpio, pin);
+    if (pin != NC) {
+        gpio_write(gpio, value);
+        gpio_dir(gpio, PIN_OUTPUT);
+        gpio_mode(gpio, mode);
+    }
+}
+
+void gpio_init_in(gpio_t* gpio, PinName pin) {
+    gpio_init_in_ex(gpio, pin, PullDefault);
+}
+
+void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
+    _gpio_init_in(gpio, pin, mode);
+}
+
+void gpio_init_out(gpio_t* gpio, PinName pin) {
+    gpio_init_out_ex(gpio, pin, 0);
+}
+
+void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
+    _gpio_init_out(gpio, pin, PullNone, value);
+}
+
+void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
+    if (direction == PIN_INPUT) {
+        _gpio_init_in(gpio, pin, mode);
+        if (pin != NC)
+            gpio_write(gpio, value); // we prepare the value in case it is switched later
+    } else {
+        _gpio_init_out(gpio, pin, mode, value);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/gpio_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "gpio_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+uint32_t gpio_set(PinName pin)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+
+    pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
+}
+
+void gpio_init(gpio_t *obj, PinName pin)
+{
+    obj->pin = pin;
+    if (pin == (PinName)NC)
+        return;
+
+    uint32_t port_index = STM_PORT(pin);
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+    // Fill GPIO object structure for future use
+    obj->mask    = gpio_set(pin);
+    obj->reg_in  = &gpio->IDR;
+    obj->reg_set = &gpio->BSRR;
+    obj->reg_clr = &gpio->BRR;
+}
+
+void gpio_mode(gpio_t *obj, PinMode mode)
+{
+    pin_mode(obj->pin, mode);
+}
+
+void gpio_dir(gpio_t *obj, PinDirection direction)
+{
+    MBED_ASSERT(obj->pin != (PinName)NC);
+    if (direction == PIN_OUTPUT) {
+        pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+    } else { // PIN_INPUT
+        pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/gpio_irq_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,267 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include <stddef.h>
+#include "cmsis.h"
+#include "gpio_irq_api.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+
+#define EDGE_NONE (0)
+#define EDGE_RISE (1)
+#define EDGE_FALL (2)
+#define EDGE_BOTH (3)
+
+// Number of EXTI irq vectors (EXTI0_1, EXTI2_3, EXTI4_15)
+#define CHANNEL_NUM (3)
+
+// Max pins for one line (max with EXTI4_15)
+#define MAX_PIN_LINE (12)
+
+typedef struct gpio_channel {
+    uint32_t pin_mask;                   // bitmask representing which pins are configured for receiving interrupts
+    uint32_t channel_ids[MAX_PIN_LINE];  // mbed "gpio_irq_t gpio_irq" field of instance
+    uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
+    uint32_t channel_pin[MAX_PIN_LINE];  // pin number in port group
+} gpio_channel_t;
+
+static gpio_channel_t channels[CHANNEL_NUM] = {
+    {.pin_mask = 0},
+    {.pin_mask = 0},
+    {.pin_mask = 0}
+};
+
+// Used to return the index for channels array.
+static uint32_t pin_base_nr[16] = {
+    // EXTI0_1
+    0, // pin 0
+    1, // pin 1
+    // EXTI2_3
+    0, // pin 2
+    1, // pin 3
+    // EXTI4_15
+    0, // pin 4
+    1, // pin 5
+    2, // pin 6
+    3, // pin 7
+    4, // pin 8
+    5, // pin 9
+    6, // pin 10
+    7, // pin 11
+    8, // pin 12
+    9, // pin 13
+    10, // pin 14
+    11  // pin 15
+};
+
+static gpio_irq_handler irq_handler;
+
+static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
+{
+    gpio_channel_t *gpio_channel = &channels[irq_index];
+    uint32_t gpio_idx;
+
+    for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
+        uint32_t current_mask = (1 << gpio_idx);
+
+        if (gpio_channel->pin_mask & current_mask) {
+            // Retrieve the gpio and pin that generate the irq
+            GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
+            uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
+
+            // Clear interrupt flag
+            if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
+                __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
+
+                if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
+
+                // Check which edge has generated the irq
+                if ((gpio->IDR & pin) == 0) {
+                    irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
+                } else  {
+                    irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
+                }
+            }
+        }
+    }
+}
+
+// EXTI lines 0 to 1
+static void gpio_irq0(void)
+{
+    handle_interrupt_in(0, 2);
+}
+
+// EXTI lines 2 to 3
+static void gpio_irq1(void)
+{
+    handle_interrupt_in(1, 2);
+}
+
+// EXTI lines 4 to 15
+static void gpio_irq2(void)
+{
+    handle_interrupt_in(2, 12);
+}
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
+{
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+    uint32_t irq_index;
+    gpio_channel_t *gpio_channel;
+    uint32_t gpio_idx;
+
+    if (pin == NC) return -1;
+
+    uint32_t port_index = STM_PORT(pin);
+    uint32_t pin_index  = STM_PIN(pin);
+
+    // Select irq number and interrupt routine
+    if ((pin_index == 0) || (pin_index == 1)) {
+        irq_n = EXTI0_1_IRQn;
+        vector = (uint32_t)&gpio_irq0;
+        irq_index = 0;
+    } else if ((pin_index == 2) || (pin_index == 3)) {
+        irq_n = EXTI2_3_IRQn;
+        vector = (uint32_t)&gpio_irq1;
+        irq_index = 1;
+    } else if ((pin_index > 3) && (pin_index < 16)) {
+        irq_n = EXTI4_15_IRQn;
+        vector = (uint32_t)&gpio_irq2;
+        irq_index = 2;
+    } else {
+        error("InterruptIn error: pin not supported.\n");
+        return -1;
+    }
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+
+    // Configure GPIO
+    pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
+
+    // Enable EXTI interrupt
+    NVIC_SetVector(irq_n, vector);
+    NVIC_EnableIRQ(irq_n);
+
+    // Save informations for future use
+    obj->irq_n = irq_n;
+    obj->irq_index = irq_index;
+    obj->event = EDGE_NONE;
+    obj->pin = pin;
+
+    gpio_channel = &channels[irq_index];
+    gpio_idx = pin_base_nr[pin_index];
+    gpio_channel->pin_mask |= (1 << gpio_idx);
+    gpio_channel->channel_ids[gpio_idx] = id;
+    gpio_channel->channel_gpio[gpio_idx] = gpio_add;
+    gpio_channel->channel_pin[gpio_idx] = pin_index;
+
+    irq_handler = handler;
+
+    return 0;
+}
+
+void gpio_irq_free(gpio_irq_t *obj)
+{
+    gpio_channel_t *gpio_channel = &channels[obj->irq_index];
+    uint32_t pin_index  = STM_PIN(obj->pin);
+    uint32_t gpio_idx = pin_base_nr[pin_index];
+
+    gpio_channel->pin_mask &= ~(1 << gpio_idx);
+    gpio_channel->channel_ids[gpio_idx] = 0;
+    gpio_channel->channel_gpio[gpio_idx] = 0;
+    gpio_channel->channel_pin[gpio_idx] = 0;
+
+    // Disable EXTI line
+    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    obj->event = EDGE_NONE;
+}
+
+void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
+{
+    uint32_t mode = STM_MODE_IT_EVT_RESET;
+    uint32_t pull = GPIO_NOPULL;
+
+    if (enable) {
+        if (event == IRQ_RISE) {
+            if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+                mode = STM_MODE_IT_RISING_FALLING;
+                obj->event = EDGE_BOTH;
+            } else { // NONE or RISE
+                mode = STM_MODE_IT_RISING;
+                obj->event = EDGE_RISE;
+            }
+        }
+        if (event == IRQ_FALL) {
+            if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+                mode = STM_MODE_IT_RISING_FALLING;
+                obj->event = EDGE_BOTH;
+            } else { // NONE or FALL
+                mode = STM_MODE_IT_FALLING;
+                obj->event = EDGE_FALL;
+            }
+        }
+    } else { // Disable
+        if (event == IRQ_RISE) {
+            if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
+                mode = STM_MODE_IT_FALLING;
+                obj->event = EDGE_FALL;
+            } else { // NONE or RISE
+                mode = STM_MODE_IT_EVT_RESET;
+                obj->event = EDGE_NONE;
+            }
+        }
+        if (event == IRQ_FALL) {
+            if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
+                mode = STM_MODE_IT_RISING;
+                obj->event = EDGE_RISE;
+            } else { // NONE or FALL
+                mode = STM_MODE_IT_EVT_RESET;
+                obj->event = EDGE_NONE;
+            }
+        }
+    }
+
+    pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
+}
+
+void gpio_irq_enable(gpio_irq_t *obj)
+{
+    NVIC_EnableIRQ(obj->irq_n);
+}
+
+void gpio_irq_disable(gpio_irq_t *obj)
+{
+    NVIC_DisableIRQ(obj->irq_n);
+    obj->event = EDGE_NONE;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/lp_ticker_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,45 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "lp_ticker_api.h"
+
+#if DEVICE_LOWPOWERTIMER
+
+static ticker_event_queue_t events;
+
+static const ticker_interface_t lp_interface = {
+    .init = lp_ticker_init,
+    .read = lp_ticker_read,
+    .disable_interrupt = lp_ticker_disable_interrupt,
+    .clear_interrupt = lp_ticker_clear_interrupt,
+    .set_interrupt = lp_ticker_set_interrupt,
+};
+
+static const ticker_data_t lp_data = {
+    .interface = &lp_interface,
+    .queue = &events,
+};
+
+const ticker_data_t* get_lp_ticker_data(void)
+{
+    return &lp_data;
+}
+
+void lp_ticker_irq_handler(void)
+{
+    ticker_irq_handler(&lp_data);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/mbed_interface.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stdio.h>
+#include "mbed_interface.h"
+
+#include "gpio_api.h"
+#include "wait_api.h"
+#include "semihost_api.h"
+#include "mbed_error.h"
+#include "toolchain.h"
+
+#if DEVICE_SEMIHOST
+
+// return true if a debugger is attached, indicating mbed interface is connected
+int mbed_interface_connected(void) {
+    return semihost_connected();
+}
+
+int mbed_interface_reset(void) {
+    if (mbed_interface_connected()) {
+        semihost_reset();
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+WEAK int mbed_interface_uid(char *uid) {
+    if (mbed_interface_connected()) {
+        return semihost_uid(uid); // Returns 0 if successful, -1 on failure
+    } else {
+        uid[0] = 0;
+        return -1;
+    }
+}
+
+int mbed_interface_disconnect(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_disabledebug()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+int mbed_interface_powerdown(void) {
+    int res;
+    if (mbed_interface_connected()) {
+        if ((res = semihost_powerdown()) != 0)
+            return res;
+        while (mbed_interface_connected());
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+// for backward compatibility
+void mbed_reset(void) {
+    mbed_interface_reset();
+}
+
+WEAK int mbed_uid(char *uid) {
+    return mbed_interface_uid(uid);
+}
+#endif
+
+WEAK void mbed_mac_address(char *mac) {
+#if DEVICE_SEMIHOST
+    char uid[DEVICE_ID_LENGTH + 1];
+    int i;
+
+    // if we have a UID, extract the MAC
+    if (mbed_interface_uid(uid) == 0) {
+        char *p = uid;
+#if defined(DEVICE_MAC_OFFSET)
+        p += DEVICE_MAC_OFFSET;
+#endif
+        for (i=0; i<6; i++) {
+            int byte;
+            sscanf(p, "%2x", &byte);
+            mac[i] = byte;
+            p += 2;
+        }
+        mac[0] &= ~0x01;    // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
+    } else {  // else return a default MAC
+#endif
+        mac[0] = 0x00;
+        mac[1] = 0x02;
+        mac[2] = 0xF7;
+        mac[3] = 0xF0;
+        mac[4] = 0x00;
+        mac[5] = 0x00;
+#if DEVICE_SEMIHOST
+    }
+#endif
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/mbed_overrides.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,35 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include "cmsis.h"
+
+// This function is called after RAM initialization and before main.
+void mbed_sdk_init()
+{
+    // Update the SystemCoreClock variable.
+    SystemCoreClockUpdate();
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/pinmap.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,150 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "pinmap.h"
+#include "PortNames.h"
+#include "mbed_error.h"
+
+// GPIO mode look-up table
+// Warning: order must be the same as the one defined in PinNames.h !!!
+static const uint32_t gpio_mode[13] = {
+    0x00000000, //  0 = GPIO_MODE_INPUT
+    0x00000001, //  1 = GPIO_MODE_OUTPUT_PP
+    0x00000011, //  2 = GPIO_MODE_OUTPUT_OD
+    0x00000002, //  3 = GPIO_MODE_AF_PP
+    0x00000012, //  4 = GPIO_MODE_AF_OD
+    0x00000003, //  5 = GPIO_MODE_ANALOG
+    0x10110000, //  6 = GPIO_MODE_IT_RISING
+    0x10210000, //  7 = GPIO_MODE_IT_FALLING
+    0x10310000, //  8 = GPIO_MODE_IT_RISING_FALLING
+    0x10120000, //  9 = GPIO_MODE_EVT_RISING
+    0x10220000, // 10 = GPIO_MODE_EVT_FALLING
+    0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING
+    0x10000000  // 12 = Reset IT and EVT (not in STM32Cube HAL)
+};
+
+// Enable GPIO clock and return GPIO base address
+uint32_t Set_GPIO_Clock(uint32_t port_idx)
+{
+    uint32_t gpio_add = 0;
+    switch (port_idx) {
+        case PortA:
+            gpio_add = GPIOA_BASE;
+            __GPIOA_CLK_ENABLE();
+            break;
+        case PortB:
+            gpio_add = GPIOB_BASE;
+            __GPIOB_CLK_ENABLE();
+            break;
+#if defined(GPIOC_BASE)
+        case PortC:
+            gpio_add = GPIOC_BASE;
+            __GPIOC_CLK_ENABLE();
+            break;
+#endif
+#if defined(GPIOD_BASE)
+        case PortD:
+            gpio_add = GPIOD_BASE;
+            __GPIOD_CLK_ENABLE();
+            break;
+#endif
+#if defined(GPIOH_BASE)
+        case PortH:
+            gpio_add = GPIOH_BASE;
+            __GPIOH_CLK_ENABLE();
+            break;
+#endif
+        default:
+            error("Pinmap error: wrong port number.");
+            break;
+    }
+    return gpio_add;
+}
+
+/**
+ * Configure pin (mode, speed, output type and pull-up/pull-down)
+ */
+void pin_function(PinName pin, int data)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    // Get the pin informations
+    uint32_t mode  = STM_PIN_MODE(data);
+    uint32_t pupd  = STM_PIN_PUPD(data);
+    uint32_t afnum = STM_PIN_AFNUM(data);
+
+    uint32_t port_index = STM_PORT(pin);
+    uint32_t pin_index  = STM_PIN(pin);
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+    // Configure GPIO
+    GPIO_InitTypeDef GPIO_InitStructure;
+    GPIO_InitStructure.Pin       = (uint32_t)(1 << pin_index);
+    GPIO_InitStructure.Mode      = gpio_mode[mode];
+    GPIO_InitStructure.Pull      = pupd;
+    GPIO_InitStructure.Speed     = GPIO_SPEED_HIGH;
+    GPIO_InitStructure.Alternate = afnum;
+    HAL_GPIO_Init(gpio, &GPIO_InitStructure);
+
+    // [TODO] Disconnect JTAG-DP + SW-DP signals.
+    // Warning: Need to reconnect under reset
+    //if ((pin == PA_13) || (pin == PA_14)) {
+    //
+    //}
+    //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
+    //
+    //}
+}
+
+/**
+ * Configure pin pull-up/pull-down
+ */
+void pin_mode(PinName pin, PinMode mode)
+{
+    MBED_ASSERT(pin != (PinName)NC);
+    uint32_t port_index = STM_PORT(pin);
+    uint32_t pin_index  = STM_PIN(pin);
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+    // Configure pull-up/pull-down resistors
+    uint32_t pupd = (uint32_t)mode;
+    if (pupd > 2)
+    {
+        pupd = 0; // Open-drain = No pull-up/No pull-down
+    }
+    gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPD0 << (pin_index * 2)));
+    gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2));
+
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/pinmap_common.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "pinmap.h"
+#include "mbed_error.h"
+
+void pinmap_pinout(PinName pin, const PinMap *map) {
+    if (pin == NC)
+        return;
+
+    while (map->pin != NC) {
+        if (map->pin == pin) {
+            pin_function(pin, map->function);
+
+            pin_mode(pin, PullNone);
+            return;
+        }
+        map++;
+    }
+    error("could not pinout");
+}
+
+uint32_t pinmap_merge(uint32_t a, uint32_t b) {
+    // both are the same (inc both NC)
+    if (a == b)
+        return a;
+
+    // one (or both) is not connected
+    if (a == (uint32_t)NC)
+        return b;
+    if (b == (uint32_t)NC)
+        return a;
+
+    // mis-match error case
+    error("pinmap mis-match");
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
+    while (map->pin != NC) {
+        if (map->pin == pin)
+            return map->peripheral;
+        map++;
+    }
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
+    uint32_t peripheral = (uint32_t)NC;
+
+    if (pin == (PinName)NC)
+        return (uint32_t)NC;
+    peripheral = pinmap_find_peripheral(pin, map);
+    if ((uint32_t)NC == peripheral) // no mapping available
+        error("pinmap not found for peripheral");
+    return peripheral;
+}
+
+uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
+    while (map->pin != NC) {
+        if (map->pin == pin)
+            return map->function;
+        map++;
+    }
+    return (uint32_t)NC;
+}
+
+uint32_t pinmap_function(PinName pin, const PinMap* map) {
+    uint32_t function = (uint32_t)NC;
+
+    if (pin == (PinName)NC)
+        return (uint32_t)NC;
+    function = pinmap_find_function(pin, map);
+    if ((uint32_t)NC == function) // no mapping available
+        error("pinmap not found for function");
+    return function;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/port_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,103 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "port_api.h"
+#include "pinmap.h"
+#include "gpio_api.h"
+#include "mbed_error.h"
+
+#if DEVICE_PORTIN || DEVICE_PORTOUT
+
+extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
+
+// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
+// low nibble  = pin number
+PinName port_pin(PortName port, int pin_n)
+{
+    return (PinName)(pin_n + (port << 4));
+}
+
+void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
+{
+    uint32_t port_index = (uint32_t)port;
+
+    // Enable GPIO clock
+    uint32_t gpio_add = Set_GPIO_Clock(port_index);
+    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
+
+    // Fill PORT object structure for future use
+    obj->port      = port;
+    obj->mask      = mask;
+    obj->direction = dir;
+    obj->reg_in    = &gpio->IDR;
+    obj->reg_out   = &gpio->ODR;
+
+    port_dir(obj, dir);
+}
+
+void port_dir(port_t *obj, PinDirection dir)
+{
+    uint32_t i;
+    obj->direction = dir;
+    for (i = 0; i < 16; i++) { // Process all pins
+        if (obj->mask & (1 << i)) { // If the pin is used
+            if (dir == PIN_OUTPUT) {
+                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
+            } else { // PIN_INPUT
+                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+            }
+        }
+    }
+}
+
+void port_mode(port_t *obj, PinMode mode)
+{
+    uint32_t i;
+    for (i = 0; i < 16; i++) { // Process all pins
+        if (obj->mask & (1 << i)) { // If the pin is used
+            pin_mode(port_pin(obj->port, i), mode);
+        }
+    }
+}
+
+void port_write(port_t *obj, int value)
+{
+    *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
+}
+
+int port_read(port_t *obj)
+{
+    if (obj->direction == PIN_OUTPUT) {
+        return (*obj->reg_out & obj->mask);
+    } else { // PIN_INPUT
+        return (*obj->reg_in & obj->mask);
+    }
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/retarget.cpp	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,569 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "platform.h"
+#include "FileHandle.h"
+#include "FileSystemLike.h"
+#include "FilePath.h"
+#include "serial_api.h"
+#include "toolchain.h"
+#include "semihost_api.h"
+#include "mbed_interface.h"
+#if DEVICE_STDIO_MESSAGES
+#include <stdio.h>
+#endif
+#include <errno.h>
+
+#if defined(__ARMCC_VERSION)
+#   include <rt_sys.h>
+#   define PREFIX(x)    _sys##x
+#   define OPEN_MAX     _SYS_OPEN
+#   ifdef __MICROLIB
+#       pragma import(__use_full_stdio)
+#   endif
+
+#elif defined(__ICCARM__)
+#   include <yfuns.h>
+#   define PREFIX(x)        _##x
+#   define OPEN_MAX         16
+
+#   define STDIN_FILENO     0
+#   define STDOUT_FILENO    1
+#   define STDERR_FILENO    2
+
+#else
+#   include <sys/stat.h>
+#   include <sys/unistd.h>
+#   include <sys/syslimits.h>
+#   define PREFIX(x)    x
+#endif
+
+using namespace mbed;
+
+#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+// Before version 5.03, we were using a patched version of microlib with proper names
+extern const char __stdin_name[]  = ":tt";
+extern const char __stdout_name[] = ":tt";
+extern const char __stderr_name[] = ":tt";
+
+#else
+extern const char __stdin_name[]  = "/stdin";
+extern const char __stdout_name[] = "/stdout";
+extern const char __stderr_name[] = "/stderr";
+#endif
+
+/* newlib has the filehandle field in the FILE struct as a short, so
+ * we can't just return a Filehandle* from _open and instead have to
+ * put it in a filehandles array and return the index into that array
+ * (or rather index+3, as filehandles 0-2 are stdin/out/err).
+ */
+static FileHandle *filehandles[OPEN_MAX];
+
+FileHandle::~FileHandle() {
+    /* Remove all open filehandles for this */
+    for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == this) {
+            filehandles[fh_i] = NULL;
+        }
+    }
+}
+
+#if DEVICE_SERIAL
+extern int stdio_uart_inited;
+extern serial_t stdio_uart;
+#endif
+
+static void init_serial() {
+#if DEVICE_SERIAL
+    if (stdio_uart_inited) return;
+    serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
+#endif
+}
+
+static inline int openmode_to_posix(int openmode) {
+    int posix = openmode;
+#ifdef __ARMCC_VERSION
+    if (openmode & OPEN_PLUS) {
+        posix = O_RDWR;
+    } else if(openmode & OPEN_W) {
+        posix = O_WRONLY;
+    } else if(openmode & OPEN_A) {
+        posix = O_WRONLY|O_APPEND;
+    } else {
+        posix = O_RDONLY;
+    }
+    /* a, w, a+, w+ all create if file does not already exist */
+    if (openmode & (OPEN_A|OPEN_W)) {
+        posix |= O_CREAT;
+    }
+    /* w and w+ truncate */
+    if (openmode & OPEN_W) {
+        posix |= O_TRUNC;
+    }
+#elif defined(__ICCARM__)
+    switch (openmode & _LLIO_RDWRMASK) {
+        case _LLIO_RDONLY: posix = O_RDONLY; break;
+        case _LLIO_WRONLY: posix = O_WRONLY; break;
+        case _LLIO_RDWR  : posix = O_RDWR  ; break;
+    }
+    if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
+    if (openmode & _LLIO_APPEND) posix |= O_APPEND;
+    if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
+#endif
+    return posix;
+}
+
+extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
+    #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
+    // Before version 5.03, we were using a patched version of microlib with proper names
+    // This is the workaround that the microlib author suggested us
+    static int n = 0;
+    if (!std::strcmp(name, ":tt")) return n++;
+
+    #else
+    /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
+     */
+    if (std::strcmp(name, __stdin_name) == 0) {
+        init_serial();
+        return 0;
+    } else if (std::strcmp(name, __stdout_name) == 0) {
+        init_serial();
+        return 1;
+    } else if (std::strcmp(name, __stderr_name) == 0) {
+        init_serial();
+        return 2;
+    }
+    #endif
+
+    // find the first empty slot in filehandles
+    unsigned int fh_i;
+    for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
+        if (filehandles[fh_i] == NULL) break;
+    }
+    if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
+        return -1;
+    }
+
+    FileHandle *res;
+
+    /* FILENAME: ":0x12345678" describes a FileLike* */
+    if (name[0] == ':') {
+        void *p;
+        sscanf(name, ":%p", &p);
+        res = (FileHandle*)p;
+
+    /* FILENAME: "/file_system/file_name" */
+    } else {
+        FilePath path(name);
+
+        if (!path.exists())
+            return -1;
+        else if (path.isFile()) {
+            res = path.file();
+        } else {
+            FileSystemLike *fs = path.fileSystem();
+            if (fs == NULL) return -1;
+            int posix_mode = openmode_to_posix(openmode);
+            res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
+        }
+    }
+
+    if (res == NULL) return -1;
+    filehandles[fh_i] = res;
+
+    return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
+}
+
+extern "C" int PREFIX(_close)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    filehandles[fh-3] = NULL;
+    if (fhc == NULL) return -1;
+
+    return fhc->close();
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __write (int        fh, const unsigned char *buffer, size_t length) {
+#else
+extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes written
+    if (fh < 3) {
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+        for (unsigned int i = 0; i < length; i++) {
+            serial_putc(&stdio_uart, buffer[i]);
+        }
+#endif
+        n = length;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) return -1;
+
+        n = fhc->write(buffer, length);
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#if defined(__ICCARM__)
+extern "C" size_t    __read (int        fh, unsigned char *buffer, size_t       length) {
+#else
+extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
+#endif
+    int n; // n is the number of bytes read
+    if (fh < 3) {
+        // only read a character at a time from stdin
+#if DEVICE_SERIAL
+        if (!stdio_uart_inited) init_serial();
+        *buffer = serial_getc(&stdio_uart);
+#endif
+        n = 1;
+    } else {
+        FileHandle* fhc = filehandles[fh-3];
+        if (fhc == NULL) return -1;
+
+        n = fhc->read(buffer, length);
+    }
+#ifdef __ARMCC_VERSION
+    return length-n;
+#else
+    return n;
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_istty)(FILEHANDLE fh)
+#else
+extern "C" int _isatty(FILEHANDLE fh)
+#endif
+{
+    /* stdin, stdout and stderr should be tty */
+    if (fh < 3) return 1;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->isatty();
+}
+
+extern "C"
+#if defined(__ARMCC_VERSION)
+int _sys_seek(FILEHANDLE fh, long position)
+#elif defined(__ICCARM__)
+long __lseek(int fh, long offset, int whence)
+#else
+int _lseek(FILEHANDLE fh, int offset, int whence)
+#endif
+{
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+#if defined(__ARMCC_VERSION)
+    return fhc->lseek(position, SEEK_SET);
+#else
+    return fhc->lseek(offset, whence);
+#endif
+}
+
+#ifdef __ARMCC_VERSION
+extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->fsync();
+}
+
+extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
+    if (fh < 3) return 0;
+
+    FileHandle* fhc = filehandles[fh-3];
+    if (fhc == NULL) return -1;
+
+    return fhc->flen();
+}
+#endif
+
+
+#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
+extern "C" int _fstat(int fd, struct stat *st) {
+    if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
+        st->st_mode = S_IFCHR;
+        return  0;
+    }
+
+    errno = EBADF;
+    return -1;
+}
+#endif
+
+namespace std {
+extern "C" int remove(const char *path) {
+    FilePath fp(path);
+    FileSystemLike *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    return fs->remove(fp.fileName());
+}
+
+extern "C" int rename(const char *oldname, const char *newname) {
+    FilePath fpOld(oldname);
+    FilePath fpNew(newname);
+    FileSystemLike *fsOld = fpOld.fileSystem();
+    FileSystemLike *fsNew = fpNew.fileSystem();
+
+    /* rename only if both files are on the same FS */
+    if (fsOld != fsNew || fsOld == NULL) return -1;
+
+    return fsOld->rename(fpOld.fileName(), fpNew.fileName());
+}
+
+extern "C" char *tmpnam(char *s) {
+    return NULL;
+}
+
+extern "C" FILE *tmpfile() {
+    return NULL;
+}
+} // namespace std
+
+#ifdef __ARMCC_VERSION
+extern "C" char *_sys_command_string(char *cmd, int len) {
+    return NULL;
+}
+#endif
+
+extern "C" DIR *opendir(const char *path) {
+    /* root dir is FileSystemLike */
+    if (path[0] == '/' && path[1] == 0) {
+        return FileSystemLike::opendir();
+    }
+
+    FilePath fp(path);
+    FileSystemLike* fs = fp.fileSystem();
+    if (fs == NULL) return NULL;
+
+    return fs->opendir(fp.fileName());
+}
+
+extern "C" struct dirent *readdir(DIR *dir) {
+    return dir->readdir();
+}
+
+extern "C" int closedir(DIR *dir) {
+    return dir->closedir();
+}
+
+extern "C" void rewinddir(DIR *dir) {
+    dir->rewinddir();
+}
+
+extern "C" off_t telldir(DIR *dir) {
+    return dir->telldir();
+}
+
+extern "C" void seekdir(DIR *dir, off_t off) {
+    dir->seekdir(off);
+}
+
+extern "C" int mkdir(const char *path, mode_t mode) {
+    FilePath fp(path);
+    FileSystemLike *fs = fp.fileSystem();
+    if (fs == NULL) return -1;
+
+    return fs->mkdir(fp.fileName(), mode);
+}
+
+#if defined(TOOLCHAIN_GCC)
+/* prevents the exception handling name demangling code getting pulled in */
+#include "mbed_error.h"
+namespace __gnu_cxx {
+    void __verbose_terminate_handler() {
+        error("Exception");
+    }
+}
+extern "C" WEAK void __cxa_pure_virtual(void);
+extern "C" WEAK void __cxa_pure_virtual(void) {
+    exit(1);
+}
+
+#endif
+
+// ****************************************************************************
+// mbed_main is a function that is called before main()
+// mbed_sdk_init() is also a function that is called before main(), but unlike
+// mbed_main(), it is not meant for user code, but for the SDK itself to perform
+// initializations before main() is called.
+
+extern "C" WEAK void mbed_main(void);
+extern "C" WEAK void mbed_main(void) {
+}
+
+extern "C" WEAK void mbed_sdk_init(void);
+extern "C" WEAK void mbed_sdk_init(void) {
+}
+
+#if defined(TOOLCHAIN_ARM)
+extern "C" int $Super$$main(void);
+
+extern "C" int $Sub$$main(void) {
+    mbed_sdk_init();
+    mbed_main();
+    return $Super$$main();
+}
+#elif defined(TOOLCHAIN_GCC)
+extern "C" int __real_main(void);
+
+extern "C" int __wrap_main(void) {
+    mbed_sdk_init();
+    mbed_main();
+    return __real_main();
+}
+#elif defined(TOOLCHAIN_IAR)
+// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent
+// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting
+// 'main' to another symbol looses the original 'main' symbol. However, its startup
+// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
+// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
+extern "C" void __iar_argc_argv() {
+    mbed_sdk_init();
+    mbed_main();
+}
+#endif
+
+// Provide implementation of _sbrk (low-level dynamic memory allocation
+// routine) for GCC_ARM which compares new heap pointer with MSP instead of
+// SP.  This make it compatible with RTX RTOS thread stacks.
+#if defined(TOOLCHAIN_GCC_ARM)
+// Linker defined symbol used by _sbrk to indicate where heap should start.
+extern "C" int __end__;
+
+#if defined(TARGET_CORTEX_A)
+extern "C" uint32_t  __HeapLimit;
+#endif
+
+// Turn off the errno macro and use actual global variable instead.
+#undef errno
+extern "C" int errno;
+
+// For ARM7 only
+register unsigned char * stack_ptr __asm ("sp");
+
+// Dynamic memory allocation related syscall.
+extern "C" caddr_t _sbrk(int incr) {
+    static unsigned char* heap = (unsigned char*)&__end__;
+    unsigned char*        prev_heap = heap;
+    unsigned char*        new_heap = heap + incr;
+
+#if defined(TARGET_ARM7)
+    if (new_heap >= stack_ptr) {
+#elif defined(TARGET_CORTEX_A)
+    if (new_heap >= (unsigned char*)&__HeapLimit) {     /* __HeapLimit is end of heap section */
+#else
+    if (new_heap >= (unsigned char*)__get_MSP()) {
+#endif
+        errno = ENOMEM;
+        return (caddr_t)-1;
+    }
+
+    heap = new_heap;
+    return (caddr_t) prev_heap;
+}
+#endif
+
+
+#ifdef TOOLCHAIN_GCC_CW
+// TODO: Ideally, we would like to define directly "_ExitProcess"
+extern "C" void mbed_exit(int return_code) {
+#elif defined TOOLCHAIN_GCC_ARM
+extern "C" void _exit(int return_code) {
+#else
+namespace std {
+extern "C" void exit(int return_code) {
+#endif
+
+#if DEVICE_STDIO_MESSAGES
+    fflush(stdout);
+    fflush(stderr);
+#endif
+
+#if DEVICE_SEMIHOST
+    if (mbed_interface_connected()) {
+        semihost_exit();
+    }
+#endif
+    if (return_code) {
+        mbed_die();
+    }
+
+    while (1);
+}
+
+#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CW)
+} //namespace std
+#endif
+
+
+namespace mbed {
+
+void mbed_set_unbuffered_stream(FILE *_file) {
+#if defined (__ICCARM__)
+    char buf[2];
+    std::setvbuf(_file,buf,_IONBF,NULL);    
+#else
+    setbuf(_file, NULL);
+#endif
+}
+
+int mbed_getc(FILE *_file){
+#if defined (__ICCARM__)
+    /*This is only valid for unbuffered streams*/
+    int res = std::fgetc(_file);
+    if (res>=0){
+        _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+        _file->_Rend = _file->_Wend;
+        _file->_Next = _file->_Wend;
+    }    
+    return res;
+#else    
+    return std::fgetc(_file);
+#endif   
+}
+
+char* mbed_gets(char*s, int size, FILE *_file){
+#if defined (__ICCARM__)
+    /*This is only valid for unbuffered streams*/
+    char *str = fgets(s,size,_file);
+    if (str!=NULL){
+        _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
+        _file->_Rend = _file->_Wend;
+        _file->_Next = _file->_Wend;
+    }
+    return str;
+#else    
+    return std::fgets(s,size,_file);
+#endif
+}
+
+} // namespace mbed

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/rtc_time.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,89 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "rtc_api.h"
+
+#include <time.h>
+#include "rtc_time.h"
+#include "us_ticker_api.h"
+
+#if DEVICE_RTC
+static void (*_rtc_init)(void) = rtc_init;
+static int (*_rtc_isenabled)(void) = rtc_isenabled;
+static time_t (*_rtc_read)(void) = rtc_read;
+static void (*_rtc_write)(time_t t) = rtc_write;
+#else
+static void (*_rtc_init)(void) = NULL;
+static int (*_rtc_isenabled)(void) = NULL;
+static time_t (*_rtc_read)(void) = NULL;
+static void (*_rtc_write)(time_t t) = NULL;
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+#if defined (__ICCARM__)
+time_t __time32(time_t *timer)
+#else
+time_t time(time_t *timer)
+#endif
+
+{
+    if (_rtc_isenabled != NULL) {
+        if (!(_rtc_isenabled())) {
+            set_time(0);
+        }
+    }
+    
+    time_t t = 0;
+    if (_rtc_read != NULL) {
+        t = _rtc_read();
+    }
+
+    if (timer != NULL) {
+        *timer = t;
+    }
+    return t;
+}
+
+void set_time(time_t t) {
+    if (_rtc_init != NULL) {
+        _rtc_init();
+    }
+    if (_rtc_write != NULL) {
+        _rtc_write(t);
+    }
+}
+
+clock_t clock() {
+    clock_t t = us_ticker_read();
+    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
+    return t;
+}
+
+void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
+    __disable_irq();
+    _rtc_read = read_rtc;
+    _rtc_write = write_rtc;
+    _rtc_init = init_rtc;
+    _rtc_isenabled = isenabled_rtc;
+    __enable_irq();
+}
+
+
+
+#ifdef __cplusplus
+}
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/semihost_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,162 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "cmsis.h"
+#include "semihost_api.h"
+
+#include <stdint.h>
+#include <string.h>
+
+#if DEVICE_SEMIHOST
+
+// ARM Semihosting Commands
+#define SYS_OPEN   (0x1)
+#define SYS_CLOSE  (0x2)
+#define SYS_WRITE  (0x5)
+#define SYS_READ   (0x6)
+#define SYS_ISTTY  (0x9)
+#define SYS_SEEK   (0xa)
+#define SYS_ENSURE (0xb)
+#define SYS_FLEN   (0xc)
+#define SYS_REMOVE (0xe)
+#define SYS_RENAME (0xf)
+#define SYS_EXIT   (0x18)
+
+// mbed Semihosting Commands
+#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
+#define USR_XFFIND      (RESERVED_FOR_USER_APPLICATIONS + 0)
+#define USR_UID      (RESERVED_FOR_USER_APPLICATIONS + 1)
+#define USR_RESET     (RESERVED_FOR_USER_APPLICATIONS + 2)
+#define USR_VBUS     (RESERVED_FOR_USER_APPLICATIONS + 3)
+#define USR_POWERDOWN     (RESERVED_FOR_USER_APPLICATIONS + 4)
+#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
+
+#if DEVICE_LOCALFILESYSTEM
+FILEHANDLE semihost_open(const char* name, int openmode) {
+    uint32_t args[3];
+    args[0] = (uint32_t)name;
+    args[1] = (uint32_t)openmode;
+    args[2] = (uint32_t)strlen(name);
+    return __semihost(SYS_OPEN, args);
+}
+
+int semihost_close(FILEHANDLE fh) {
+    return __semihost(SYS_CLOSE, &fh);
+}
+
+int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
+    if (length == 0) return 0;
+
+    uint32_t args[3];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)buffer;
+    args[2] = (uint32_t)length;
+    return __semihost(SYS_WRITE, args);
+}
+
+int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
+    uint32_t args[3];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)buffer;
+    args[2] = (uint32_t)length;
+    return __semihost(SYS_READ, args);
+}
+
+int semihost_istty(FILEHANDLE fh) {
+    return __semihost(SYS_ISTTY, &fh);
+}
+
+int semihost_seek(FILEHANDLE fh, long position) {
+    uint32_t args[2];
+    args[0] = (uint32_t)fh;
+    args[1] = (uint32_t)position;
+    return __semihost(SYS_SEEK, args);
+}
+
+int semihost_ensure(FILEHANDLE fh) {
+    return __semihost(SYS_ENSURE, &fh);
+}
+
+long semihost_flen(FILEHANDLE fh) {
+    return __semihost(SYS_FLEN, &fh);
+}
+
+int semihost_remove(const char *name) {
+    uint32_t args[2];
+    args[0] = (uint32_t)name;
+    args[1] = (uint32_t)strlen(name);
+    return __semihost(SYS_REMOVE, args);
+}
+
+int semihost_rename(const char *old_name, const char *new_name) {
+    uint32_t args[4];
+    args[0] = (uint32_t)old_name;
+    args[1] = (uint32_t)strlen(old_name);
+    args[0] = (uint32_t)new_name;
+    args[1] = (uint32_t)strlen(new_name);
+    return __semihost(SYS_RENAME, args);
+}
+#endif
+
+int semihost_exit(void) {
+    uint32_t args[4];
+    return __semihost(SYS_EXIT, args);
+}
+
+int semihost_uid(char *uid) {
+    uint32_t args[2];
+    args[0] = (uint32_t)uid;
+    args[1] = DEVICE_ID_LENGTH + 1;
+    return __semihost(USR_UID, &args);
+}
+
+int semihost_reset(void) {
+    // Does not normally return, however if used with older firmware versions
+    // that do not support this call it will return -1.
+    return __semihost(USR_RESET, NULL);
+}
+
+int semihost_vbus(void) {
+    return __semihost(USR_VBUS, NULL);
+}
+
+int semihost_powerdown(void) {
+    return __semihost(USR_POWERDOWN, NULL);
+}
+
+#if DEVICE_DEBUG_AWARENESS
+
+int semihost_connected(void) {
+    return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
+}
+
+#else
+// These processors cannot know if the interface is connect, assume so:
+static int is_debugger_attached = 1;
+
+int semihost_connected(void) {
+    return is_debugger_attached;
+}
+#endif
+
+int semihost_disabledebug(void) {
+#if !(DEVICE_DEBUG_AWARENESS)
+    is_debugger_attached = 0;
+#endif
+    return __semihost(USR_DISABLEDEBUG, NULL);
+}
+
+#endif
+

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/serial_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,409 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "serial_api.h"
+
+#if DEVICE_SERIAL
+
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include <string.h>
+#include "PeripheralPins.h"
+
+#define UART_NUM (5)
+
+static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0};
+
+static uart_irq_handler irq_handler;
+
+UART_HandleTypeDef UartHandle;
+
+int stdio_uart_inited = 0;
+serial_t stdio_uart;
+
+static void init_uart(serial_t *obj)
+{
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+    if (obj->uart == LPUART_1) {
+        UartHandle.Init.BaudRate = obj->baudrate >> 1;
+    } else {
+        UartHandle.Init.BaudRate = obj->baudrate;
+    }
+    UartHandle.Init.WordLength = obj->databits;
+    UartHandle.Init.StopBits   = obj->stopbits;
+    UartHandle.Init.Parity     = obj->parity;
+    UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
+
+    if (obj->pin_rx == NC) {
+        UartHandle.Init.Mode = UART_MODE_TX;
+    } else if (obj->pin_tx == NC) {
+        UartHandle.Init.Mode = UART_MODE_RX;
+    } else {
+        UartHandle.Init.Mode = UART_MODE_TX_RX;
+    }
+
+    // Disable the reception overrun detection
+    UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT;
+    UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
+
+    if (HAL_UART_Init(&UartHandle) != HAL_OK) {
+        error("Cannot initialize UART");
+    }
+}
+
+void serial_init(serial_t *obj, PinName tx, PinName rx)
+{
+    // Determine the UART to use (UART_1, UART_2, ...)
+    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
+    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
+
+    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
+    obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
+    MBED_ASSERT(obj->uart != (UARTName)NC);
+
+    // Enable UART clock
+    if (obj->uart == UART_1) {
+        __HAL_RCC_USART1_CLK_ENABLE();
+        obj->index = 0;
+    }
+
+    if (obj->uart == UART_2) {
+        __HAL_RCC_USART2_CLK_ENABLE();
+        obj->index = 1;
+    }
+
+    if (obj->uart == LPUART_1) {
+        __HAL_RCC_LPUART1_CLK_ENABLE();
+        obj->index = 2;
+    }
+
+#if defined(USART4_BASE)
+    if (obj->uart == UART_4) {
+        __HAL_RCC_USART4_CLK_ENABLE();
+        obj->index = 3;
+    }
+#endif
+
+#if defined(USART5_BASE)
+    if (obj->uart == UART_5) {
+        __HAL_RCC_USART5_CLK_ENABLE();
+        obj->index = 4;
+    }
+#endif
+
+    // Configure the UART pins
+    pinmap_pinout(tx, PinMap_UART_TX);
+    pinmap_pinout(rx, PinMap_UART_RX);
+    if (tx != NC) {
+        pin_mode(tx, PullUp);
+    }
+    if (rx != NC) {
+        pin_mode(rx, PullUp);
+    }
+
+    // Configure UART
+    obj->baudrate = 9600;
+    obj->databits = UART_WORDLENGTH_8B;
+    obj->stopbits = UART_STOPBITS_1;
+    obj->parity   = UART_PARITY_NONE;
+    obj->pin_tx   = tx;
+    obj->pin_rx   = rx;
+
+    init_uart(obj);
+
+    // For stdio management
+    if (obj->uart == STDIO_UART) {
+        stdio_uart_inited = 1;
+        memcpy(&stdio_uart, obj, sizeof(serial_t));
+    }
+}
+
+void serial_free(serial_t *obj)
+{
+    // Reset UART and disable clock
+    if (obj->uart == UART_1) {
+        __HAL_RCC_USART1_FORCE_RESET();
+        __HAL_RCC_USART1_RELEASE_RESET();
+        __HAL_RCC_USART1_CLK_DISABLE();
+    }
+
+    if (obj->uart == UART_2) {
+        __HAL_RCC_USART2_FORCE_RESET();
+        __HAL_RCC_USART2_RELEASE_RESET();
+        __HAL_RCC_USART2_CLK_DISABLE();
+    }
+
+    if (obj->uart == LPUART_1) {
+        __HAL_RCC_LPUART1_FORCE_RESET();
+        __HAL_RCC_LPUART1_RELEASE_RESET();
+        __HAL_RCC_LPUART1_CLK_DISABLE();
+    }
+
+#if defined(USART4_BASE)
+    if (obj->uart == UART_4) {
+        __HAL_RCC_USART4_FORCE_RESET();
+        __HAL_RCC_USART4_RELEASE_RESET();
+        __HAL_RCC_USART4_CLK_DISABLE();
+    }
+#endif
+
+#if defined(USART5_BASE)
+    if (obj->uart == UART_5) {
+        __HAL_RCC_USART5_FORCE_RESET();
+        __HAL_RCC_USART5_RELEASE_RESET();
+        __HAL_RCC_USART5_CLK_DISABLE();
+    }
+#endif
+
+    // Configure GPIOs
+    pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+
+    serial_irq_ids[obj->index] = 0;
+}
+
+void serial_baud(serial_t *obj, int baudrate)
+{
+    obj->baudrate = baudrate;
+    init_uart(obj);
+}
+
+void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
+{
+    if (data_bits == 9) {
+        obj->databits = UART_WORDLENGTH_9B;
+    } else {
+        obj->databits = UART_WORDLENGTH_8B;
+    }
+
+    switch (parity) {
+        case ParityOdd:
+        case ParityForced0:
+            obj->parity = UART_PARITY_ODD;
+            break;
+        case ParityEven:
+        case ParityForced1:
+            obj->parity = UART_PARITY_EVEN;
+            break;
+        default: // ParityNone
+            obj->parity = UART_PARITY_NONE;
+            break;
+    }
+
+    if (stop_bits == 2) {
+        obj->stopbits = UART_STOPBITS_2;
+    } else {
+        obj->stopbits = UART_STOPBITS_1;
+    }
+
+    init_uart(obj);
+}
+
+/******************************************************************************
+ * INTERRUPTS HANDLING
+ ******************************************************************************/
+
+static void uart_irq(UARTName name, int id)
+{
+    UartHandle.Instance = (USART_TypeDef *)name;
+    if (serial_irq_ids[id] != 0) {
+        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
+            irq_handler(serial_irq_ids[id], TxIrq);
+            __HAL_UART_CLEAR_IT(&UartHandle, UART_CLEAR_TCF);
+        }
+        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
+            irq_handler(serial_irq_ids[id], RxIrq);
+            volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit
+        }
+    }
+}
+
+static void uart1_irq(void)
+{
+    uart_irq(UART_1, 0);
+}
+
+static void uart2_irq(void)
+{
+    uart_irq(UART_2, 1);
+}
+
+static void lpuart1_irq(void)
+{
+    uart_irq(LPUART_1, 2);
+}
+
+#if defined(USART4_BASE)
+static void uart4_irq(void)
+{
+    uart_irq(UART_4, 3);
+}
+#endif
+
+#if defined(USART5_BASE)
+static void uart5_irq(void)
+{
+    uart_irq(UART_5, 4);
+}
+#endif
+
+void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
+{
+    irq_handler = handler;
+    serial_irq_ids[obj->index] = id;
+}
+
+void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
+{
+    IRQn_Type irq_n = (IRQn_Type)0;
+    uint32_t vector = 0;
+
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+
+    if (obj->uart == UART_1) {
+        irq_n = USART1_IRQn;
+        vector = (uint32_t)&uart1_irq;
+    }
+
+    if (obj->uart == UART_2) {
+        irq_n = USART2_IRQn;
+        vector = (uint32_t)&uart2_irq;
+    }
+
+    if (obj->uart == LPUART_1) {
+        irq_n = RNG_LPUART1_IRQn;
+        vector = (uint32_t)&lpuart1_irq;
+    }
+
+#if defined(USART4_BASE)
+    if (obj->uart == UART_4) {
+        irq_n = USART4_5_IRQn;
+        vector = (uint32_t)&uart4_irq;
+    }
+#endif
+
+#if defined(USART5_BASE)
+    if (obj->uart == UART_5) {
+        irq_n = USART4_5_IRQn;
+        vector = (uint32_t)&uart5_irq;
+    }
+#endif
+
+    if (enable) {
+
+        if (irq == RxIrq) {
+            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
+        } else { // TxIrq
+            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
+        }
+
+        NVIC_SetVector(irq_n, vector);
+        NVIC_EnableIRQ(irq_n);
+
+    } else { // disable
+
+        int all_disabled = 0;
+
+        if (irq == RxIrq) {
+            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
+            // Check if TxIrq is disabled too
+            if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1;
+        } else { // TxIrq
+            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC);
+            // Check if RxIrq is disabled too
+            if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
+        }
+
+        if (all_disabled) NVIC_DisableIRQ(irq_n);
+
+    }
+}
+
+/******************************************************************************
+ * READ/WRITE
+ ******************************************************************************/
+
+int serial_getc(serial_t *obj)
+{
+    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+    while (!serial_readable(obj));
+    return (int)(uart->RDR & (uint32_t)0xFF);
+}
+
+void serial_putc(serial_t *obj, int c)
+{
+    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
+    while (!serial_writable(obj));
+    uart->TDR = (uint32_t)(c & (uint32_t)0xFF);
+}
+
+int serial_readable(serial_t *obj)
+{
+    int status;
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    // Check if data is received
+    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
+    return status;
+}
+
+int serial_writable(serial_t *obj)
+{
+    int status;
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    // Check if data is transmitted
+    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
+    return status;
+}
+
+void serial_clear(serial_t *obj)
+{
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    __HAL_UART_CLEAR_IT(&UartHandle, UART_CLEAR_TCF);
+    __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST);
+}
+
+void serial_pinout_tx(PinName tx)
+{
+    pinmap_pinout(tx, PinMap_UART_TX);
+}
+
+void serial_break_set(serial_t *obj)
+{
+    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
+    __HAL_UART_SEND_REQ(&UartHandle, UART_SENDBREAK_REQUEST);
+}
+
+void serial_break_clear(serial_t *obj)
+{
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/sleep.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,63 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "sleep_api.h"
+
+#if DEVICE_SLEEP
+
+#include "cmsis.h"
+
+static TIM_HandleTypeDef TimMasterHandle;
+
+void sleep(void)
+{
+    TimMasterHandle.Instance = TIM21;
+
+    // Disable HAL tick interrupt
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE));
+
+    // Request to enter SLEEP mode
+    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
+
+    // Enable HAL tick interrupt
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE));
+}
+
+void deepsleep(void)
+{
+
+
+    // Request to enter STOP mode with regulator in low power mode
+    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
+
+    // After wake-up from STOP reconfigure the PLL
+    SetSysClock();
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/spi_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,268 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "mbed_assert.h"
+#include "spi_api.h"
+
+#if DEVICE_SPI
+
+#include <math.h>
+#include "cmsis.h"
+#include "pinmap.h"
+#include "mbed_error.h"
+#include "PeripheralPins.h"
+
+static SPI_HandleTypeDef SpiHandle;
+
+static void init_spi(spi_t *obj)
+{
+    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+
+    __HAL_SPI_DISABLE(&SpiHandle);
+
+    SpiHandle.Init.Mode              = obj->mode;
+    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
+    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
+    SpiHandle.Init.CLKPhase          = obj->cpha;
+    SpiHandle.Init.CLKPolarity       = obj->cpol;
+    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
+    SpiHandle.Init.CRCPolynomial     = 7;
+    SpiHandle.Init.DataSize          = obj->bits;
+    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
+    SpiHandle.Init.NSS               = obj->nss;
+    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
+
+    if (HAL_SPI_Init(&SpiHandle) != HAL_OK) {
+        error("Cannot initialize SPI");
+    }
+
+    __HAL_SPI_ENABLE(&SpiHandle);
+}
+
+void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
+{
+    // Determine the SPI to use
+    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
+    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
+    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
+    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
+
+    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
+    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
+
+    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
+    MBED_ASSERT(obj->spi != (SPIName)NC);
+
+    // Enable SPI clock
+    if (obj->spi == SPI_1) {
+        __SPI1_CLK_ENABLE();
+    }
+    if (obj->spi == SPI_2) {
+        __SPI2_CLK_ENABLE();
+    }
+
+    // Configure the SPI pins
+    pinmap_pinout(mosi, PinMap_SPI_MOSI);
+    pinmap_pinout(miso, PinMap_SPI_MISO);
+    pinmap_pinout(sclk, PinMap_SPI_SCLK);
+
+    // Save new values
+    obj->bits = SPI_DATASIZE_8BIT;
+    obj->cpol = SPI_POLARITY_LOW;
+    obj->cpha = SPI_PHASE_1EDGE;
+    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
+
+    obj->pin_miso = miso;
+    obj->pin_mosi = mosi;
+    obj->pin_sclk = sclk;
+    obj->pin_ssel = ssel;
+
+    if (ssel != NC) {
+        pinmap_pinout(ssel, PinMap_SPI_SSEL);
+    } else {
+        obj->nss = SPI_NSS_SOFT;
+    }
+
+    init_spi(obj);
+}
+
+void spi_free(spi_t *obj)
+{
+    // Reset SPI and disable clock
+    if (obj->spi == SPI_1) {
+        __SPI1_FORCE_RESET();
+        __SPI1_RELEASE_RESET();
+        __SPI1_CLK_DISABLE();
+    }
+
+    if (obj->spi == SPI_2) {
+        __SPI2_FORCE_RESET();
+        __SPI2_RELEASE_RESET();
+        __SPI2_CLK_DISABLE();
+    }
+
+    // Configure GPIO
+    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
+}
+
+void spi_format(spi_t *obj, int bits, int mode, int slave)
+{
+    // Save new values
+    if (bits == 16) {
+        obj->bits = SPI_DATASIZE_16BIT;
+    } else {
+        obj->bits = SPI_DATASIZE_8BIT;
+    }
+
+    switch (mode) {
+        case 0:
+            obj->cpol = SPI_POLARITY_LOW;
+            obj->cpha = SPI_PHASE_1EDGE;
+            break;
+        case 1:
+            obj->cpol = SPI_POLARITY_LOW;
+            obj->cpha = SPI_PHASE_2EDGE;
+            break;
+        case 2:
+            obj->cpol = SPI_POLARITY_HIGH;
+            obj->cpha = SPI_PHASE_1EDGE;
+            break;
+        default:
+            obj->cpol = SPI_POLARITY_HIGH;
+            obj->cpha = SPI_PHASE_2EDGE;
+            break;
+    }
+
+    if (obj->nss != SPI_NSS_SOFT) {
+        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
+    }
+
+    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
+
+    init_spi(obj);
+}
+
+void spi_frequency(spi_t *obj, int hz)
+{
+    // Note: The frequencies are obtained with SPI1 clock = 32 MHz (APB2 clock)
+    if (hz < 250000) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz
+    } else if ((hz >= 250000) && (hz < 500000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz
+    } else if ((hz >= 500000) && (hz < 1000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz
+    } else if ((hz >= 1000000) && (hz < 2000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz
+    } else if ((hz >= 2000000) && (hz < 4000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz
+    } else if ((hz >= 4000000) && (hz < 8000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz
+    } else if ((hz >= 8000000) && (hz < 16000000)) {
+        obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz
+    } else { // >= 16000000
+        obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz
+    }
+
+    init_spi(obj);
+}
+
+static inline int ssp_readable(spi_t *obj)
+{
+    int status;
+    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+    // Check if data is received
+    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
+    return status;
+}
+
+static inline int ssp_writeable(spi_t *obj)
+{
+    int status;
+    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+    // Check if data is transmitted
+    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
+    return status;
+}
+
+static inline void ssp_write(spi_t *obj, int value)
+{
+    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+    while (!ssp_writeable(obj));
+    spi->DR = (uint16_t)value;
+}
+
+static inline int ssp_read(spi_t *obj)
+{
+    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+    while (!ssp_readable(obj));
+    return (int)spi->DR;
+}
+
+static inline int ssp_busy(spi_t *obj)
+{
+    int status;
+    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
+    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
+    return status;
+}
+
+int spi_master_write(spi_t *obj, int value)
+{
+    ssp_write(obj, value);
+    return ssp_read(obj);
+}
+
+int spi_slave_receive(spi_t *obj)
+{
+    return (ssp_readable(obj) ? 1 : 0);
+};
+
+int spi_slave_read(spi_t *obj)
+{
+    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+    while (!ssp_readable(obj));
+    return (int)spi->DR;
+}
+
+void spi_slave_write(spi_t *obj, int value)
+{
+    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
+    while (!ssp_writeable(obj));
+    spi->DR = (uint16_t)value;
+}
+
+int spi_busy(spi_t *obj)
+{
+    return ssp_busy(obj);
+}
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/ticker_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,135 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include <stddef.h>
+#include "ticker_api.h"
+#include "cmsis.h"
+
+void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler) {
+    data->interface->init();
+
+    data->queue->event_handler = handler;
+}
+
+void ticker_irq_handler(const ticker_data_t *const data) {
+    data->interface->clear_interrupt();
+
+    /* Go through all the pending TimerEvents */
+    while (1) {
+        if (data->queue->head == NULL) {
+            // There are no more TimerEvents left, so disable matches.
+            data->interface->disable_interrupt();
+            return;
+        }
+
+        if ((int)(data->queue->head->timestamp - data->interface->read()) <= 0) {
+            // This event was in the past:
+            //      point to the following one and execute its handler
+            ticker_event_t *p = data->queue->head;
+            data->queue->head = data->queue->head->next;
+            if (data->queue->event_handler != NULL) {
+                (*data->queue->event_handler)(p->id); // NOTE: the handler can set new events
+            }
+            /* Note: We continue back to examining the head because calling the
+             * event handler may have altered the chain of pending events. */
+        } else {
+            // This event and the following ones in the list are in the future:
+            //      set it as next interrupt and return
+            data->interface->set_interrupt(data->queue->head->timestamp);
+            return;
+        }
+    }
+}
+
+void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id) {
+    /* disable interrupts for the duration of the function */
+    __disable_irq();
+
+    // initialise our data
+    obj->timestamp = timestamp;
+    obj->id = id;
+
+    /* Go through the list until we either reach the end, or find
+       an element this should come before (which is possibly the
+       head). */
+    ticker_event_t *prev = NULL, *p = data->queue->head;
+    while (p != NULL) {
+        /* check if we come before p */
+        if ((int)(timestamp - p->timestamp) < 0) {
+            break;
+        }
+        /* go to the next element */
+        prev = p;
+        p = p->next;
+    }
+    /* if prev is NULL we're at the head */
+    if (prev == NULL) {
+        data->queue->head = obj;
+        data->interface->set_interrupt(timestamp);
+    } else {
+        prev->next = obj;
+    }
+    /* if we're at the end p will be NULL, which is correct */
+    obj->next = p;
+
+    __enable_irq();
+}
+
+void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj) {
+    __disable_irq();
+
+    // remove this object from the list
+    if (data->queue->head == obj) {
+        // first in the list, so just drop me
+        data->queue->head = obj->next;
+        if (data->queue->head == NULL) {
+            data->interface->disable_interrupt();
+        } else {
+            data->interface->set_interrupt(data->queue->head->timestamp);
+        }
+    } else {
+        // find the object before me, then drop me
+        ticker_event_t* p = data->queue->head;
+        while (p != NULL) {
+            if (p->next == obj) {
+                p->next = obj->next;
+                break;
+            }
+            p = p->next;
+        }
+    }
+
+    __enable_irq();
+}
+
+timestamp_t ticker_read(const ticker_data_t *const data)
+{
+    return data->interface->read();
+}
+
+int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp)
+{
+    int ret = 0;
+
+    /* if head is NULL, there are no pending events */
+    __disable_irq();
+    if (data->queue->head != NULL) {
+        *timestamp = data->queue->head->timestamp;
+        ret = 1;
+    }
+    __enable_irq();
+
+    return ret;
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/us_ticker.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#include <stddef.h>
+#include "us_ticker_api.h"
+#include "PeripheralNames.h"
+
+// Timer selection
+#define TIM_MST TIM21
+
+static TIM_HandleTypeDef TimMasterHandle;
+static int us_ticker_inited = 0;
+
+volatile uint32_t SlaveCounter = 0;
+volatile uint32_t oc_int_part = 0;
+volatile uint16_t oc_rem_part = 0;
+
+void set_compare(uint16_t count)
+{
+    TimMasterHandle.Instance = TIM_MST;
+    // Set new output compare value
+    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count);
+    // Enable IT
+    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_init(void)
+{
+    if (us_ticker_inited) return;
+    us_ticker_inited = 1;
+
+    HAL_InitTick(0); // The passed value is not used
+}
+
+uint32_t us_ticker_read()
+{
+    uint32_t counter, counter2;
+    if (!us_ticker_inited) us_ticker_init();
+    // A situation might appear when Master overflows right after Slave is read and before the
+    // new (overflowed) value of Master is read. Which would make the code below consider the
+    // previous (incorrect) value of Slave and the new value of Master, which would return a
+    // value in the past. Avoid this by computing consecutive values of the timer until they
+    // are properly ordered.
+    counter = (uint32_t)(SlaveCounter << 16);
+    counter += TIM_MST->CNT;
+    while (1) {
+        counter2 = (uint32_t)(SlaveCounter << 16);
+        counter2 += TIM_MST->CNT;
+        if (counter2 > counter) {
+            break;
+        }
+        counter = counter2;
+    }
+    return counter2;
+}
+
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+    int delta = (int)((uint32_t)timestamp - us_ticker_read());
+    uint16_t cval = TIM_MST->CNT;
+
+    if (delta <= 0) { // This event was in the past
+        us_ticker_irq_handler();
+    } else {
+        oc_int_part = (uint32_t)(delta >> 16);
+        oc_rem_part = (uint16_t)(delta & 0xFFFF);
+        if (oc_rem_part <= (0xFFFF - cval)) {
+            set_compare(cval + oc_rem_part);
+            oc_rem_part = 0;
+        } else {
+            set_compare(0xFFFF);
+            oc_rem_part = oc_rem_part - (0xFFFF - cval);
+        }
+    }
+}
+
+void us_ticker_disable_interrupt(void)
+{
+    TimMasterHandle.Instance = TIM_MST;
+    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
+}
+
+void us_ticker_clear_interrupt(void)
+{
+    TimMasterHandle.Instance = TIM_MST;
+    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
+        __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
+    }
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/us_ticker_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,41 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2015 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "us_ticker_api.h"
+
+static ticker_event_queue_t events;
+
+static const ticker_interface_t us_interface = {
+    .init = us_ticker_init,
+    .read = us_ticker_read,
+    .disable_interrupt = us_ticker_disable_interrupt,
+    .clear_interrupt = us_ticker_clear_interrupt,
+    .set_interrupt = us_ticker_set_interrupt,
+};
+
+static const ticker_data_t us_data = {
+    .interface = &us_interface,
+    .queue = &events,
+};
+
+const ticker_data_t* get_us_ticker_data(void)
+{
+    return &us_data;
+}
+
+void us_ticker_irq_handler(void)
+{
+    ticker_irq_handler(&us_data);
+}

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/api_source/wait_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,30 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2013 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ *     http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "wait_api.h"
+#include "us_ticker_api.h"
+
+void wait(float s) {
+    wait_us(s * 1000000.0f);
+}
+
+void wait_ms(int ms) {
+    wait_us(ms * 1000);
+}
+
+void wait_us(int us) {
+    uint32_t start = us_ticker_read();
+    while ((us_ticker_read() - start) < (uint32_t)us);
+}

--- a/common/BusIn.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,82 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusIn.h"
-#include "mbed_assert.h"
-
-namespace mbed {
-
-BusIn::BusIn(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
-    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
-    _nc_mask = 0;
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
-        if (pins[i] != NC) {
-            _nc_mask |= (1 << i);
-        }
-    }
-}
-
-BusIn::BusIn(PinName pins[16]) {
-    _nc_mask = 0;
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalIn(pins[i]) : 0;
-        if (pins[i] != NC) {
-            _nc_mask |= (1 << i);
-        }
-    }
-}
-
-BusIn::~BusIn() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            delete _pin[i];
-        }
-    }
-}
-
-int BusIn::read() {
-    int v = 0;
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            v |= _pin[i]->read() << i;
-        }
-    }
-    return v;
-}
-
-void BusIn::mode(PinMode pull) {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->mode(pull);
-        }
-    }
-}
-
-#ifdef MBED_OPERATORS
-BusIn::operator int() {
-    return read();
-}
-
-DigitalIn& BusIn::operator[] (int index) {
-    MBED_ASSERT(index >= 0 && index <= 16);
-    MBED_ASSERT(_pin[index]);
-    return *_pin[index];
-}
-
-#endif
-
-} // namespace mbed

--- a/common/BusInOut.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,115 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusInOut.h"
-#include "mbed_assert.h"
-
-namespace mbed {
-
-BusInOut::BusInOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
-    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
-    _nc_mask = 0;
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
-        if (pins[i] != NC) {
-            _nc_mask |= (1 << i);
-        }
-    }
-}
-
-BusInOut::BusInOut(PinName pins[16]) {
-    _nc_mask = 0;
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalInOut(pins[i]) : 0;
-        if (pins[i] != NC) {
-            _nc_mask |= (1 << i);
-        }
-    }
-}
-
-BusInOut::~BusInOut() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            delete _pin[i];
-        }
-    }
-}
-
-void BusInOut::write(int value) {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->write((value >> i) & 1);
-        }
-    }
-}
-
-int BusInOut::read() {
-    int v = 0;
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            v |= _pin[i]->read() << i;
-        }
-    }
-    return v;
-}
-
-void BusInOut::output() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->output();
-        }
-    }
-}
-
-void BusInOut::input() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->input();
-        }
-    }
-}
-
-void BusInOut::mode(PinMode pull) {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->mode(pull);
-        }
-    }
-}
-
-#ifdef MBED_OPERATORS
-BusInOut& BusInOut::operator= (int v) {
-    write(v);
-    return *this;
-}
-
-BusInOut& BusInOut::operator= (BusInOut& rhs) {
-    write(rhs.read());
-    return *this;
-}
-
-DigitalInOut& BusInOut::operator[] (int index) {
-    MBED_ASSERT(index >= 0 && index <= 16);
-    MBED_ASSERT(_pin[index]);
-    return *_pin[index];
-}
-
-BusInOut::operator int() {
-    return read();
-}
-#endif
-
-} // namespace mbed

--- a/common/BusOut.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,91 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "BusOut.h"
-#include "mbed_assert.h"
-
-namespace mbed {
-
-BusOut::BusOut(PinName p0, PinName p1, PinName p2, PinName p3, PinName p4, PinName p5, PinName p6, PinName p7, PinName p8, PinName p9, PinName p10, PinName p11, PinName p12, PinName p13, PinName p14, PinName p15) {
-    PinName pins[16] = {p0, p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15};
-
-    _nc_mask = 0;
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
-        if (pins[i] != NC) {
-            _nc_mask |= (1 << i);
-        }
-    }
-}
-
-BusOut::BusOut(PinName pins[16]) {
-    _nc_mask = 0;
-    for (int i=0; i<16; i++) {
-        _pin[i] = (pins[i] != NC) ? new DigitalOut(pins[i]) : 0;
-        if (pins[i] != NC) {
-            _nc_mask |= (1 << i);
-        }
-    }
-}
-
-BusOut::~BusOut() {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            delete _pin[i];
-        }
-    }
-}
-
-void BusOut::write(int value) {
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            _pin[i]->write((value >> i) & 1);
-        }
-    }
-}
-
-int BusOut::read() {
-    int v = 0;
-    for (int i=0; i<16; i++) {
-        if (_pin[i] != 0) {
-            v |= _pin[i]->read() << i;
-        }
-    }
-    return v;
-}
-
-#ifdef MBED_OPERATORS
-BusOut& BusOut::operator= (int v) {
-    write(v);
-    return *this;
-}
-
-BusOut& BusOut::operator= (BusOut& rhs) {
-    write(rhs.read());
-    return *this;
-}
-
-DigitalOut& BusOut::operator[] (int index) {
-    MBED_ASSERT(index >= 0 && index <= 16);
-    MBED_ASSERT(_pin[index]);
-    return *_pin[index];
-}
-
-BusOut::operator int() {
-    return read();
-}
-#endif
-
-} // namespace mbed

--- a/common/CAN.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,86 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "CAN.h"
-
-#if DEVICE_CAN
-
-#include "cmsis.h"
-
-namespace mbed {
-
-CAN::CAN(PinName rd, PinName td) : _can(), _irq() {
-    can_init(&_can, rd, td);
-    can_irq_init(&_can, (&CAN::_irq_handler), (uint32_t)this);
-}
-
-CAN::~CAN() {
-    can_irq_free(&_can);
-    can_free(&_can);
-}
-
-int CAN::frequency(int f) {
-    return can_frequency(&_can, f);
-}
-
-int CAN::write(CANMessage msg) {
-    return can_write(&_can, msg, 0);
-}
-
-int CAN::read(CANMessage &msg, int handle) {
-    return can_read(&_can, &msg, handle);
-}
-
-void CAN::reset() {
-    can_reset(&_can);
-}
-
-unsigned char CAN::rderror() {
-    return can_rderror(&_can);
-}
-
-unsigned char CAN::tderror() {
-    return can_tderror(&_can);
-}
-
-void CAN::monitor(bool silent) {
-    can_monitor(&_can, (silent) ? 1 : 0);
-}
-
-int CAN::mode(Mode mode) {
-    return can_mode(&_can, (CanMode)mode);
-}
-
-int CAN::filter(unsigned int id, unsigned int mask, CANFormat format, int handle) {
-    return can_filter(&_can, id, mask, format, handle);
-}
-
-void CAN::attach(void (*fptr)(void), IrqType type) {
-    if (fptr) {
-        _irq[(CanIrqType)type].attach(fptr);
-        can_irq_set(&_can, (CanIrqType)type, 1);
-    } else {
-        can_irq_set(&_can, (CanIrqType)type, 0);
-    }
-}
-
-void CAN::_irq_handler(uint32_t id, CanIrqType type) {
-    CAN *handler = (CAN*)id;
-    handler->_irq[type].call();
-}
-
-} // namespace mbed
-
-#endif

--- a/common/CallChain.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,90 +0,0 @@
-#include "CallChain.h"
-#include "cmsis.h"
-
-namespace mbed {
-
-CallChain::CallChain(int size) : _chain(), _size(size), _elements(0) {
-    _chain = new pFunctionPointer_t[size]();
-}
-
-CallChain::~CallChain() {
-    clear();
-    delete _chain;
-}
-
-pFunctionPointer_t CallChain::add(void (*function)(void)) {
-    return common_add(new FunctionPointer(function));
-}
-
-pFunctionPointer_t CallChain::add_front(void (*function)(void)) {
-    return common_add_front(new FunctionPointer(function));
-}
-
-int CallChain::size() const {
-    return _elements;
-}
-
-pFunctionPointer_t CallChain::get(int i) const {
-    if (i < 0 || i >= _elements)
-        return NULL;
-    return _chain[i];
-}
-
-int CallChain::find(pFunctionPointer_t f) const {
-    for (int i = 0; i < _elements; i++)
-        if (f == _chain[i])
-            return i;
-    return -1;
-}
-
-void CallChain::clear() {
-    for(int i = 0; i < _elements; i ++) {
-        delete _chain[i];
-        _chain[i] = NULL;
-    }
-    _elements = 0;
-}
-
-bool CallChain::remove(pFunctionPointer_t f) {
-    int i;
-
-    if ((i = find(f)) == -1)
-        return false;
-    if (i != _elements - 1)
-        memmove(_chain + i, _chain + i + 1, (_elements - i - 1) * sizeof(pFunctionPointer_t));
-    delete f;
-    _elements --;
-    return true;
-}
-
-void CallChain::call() {
-    for(int i = 0; i < _elements; i++)
-        _chain[i]->call();
-}
-
-void CallChain::_check_size() {
-    if (_elements < _size)
-        return;
-    _size = (_size < 4) ? 4 : _size + 4;
-    pFunctionPointer_t* new_chain = new pFunctionPointer_t[_size]();
-    memcpy(new_chain, _chain, _elements * sizeof(pFunctionPointer_t));
-    delete _chain;
-    _chain = new_chain;
-}
-
-pFunctionPointer_t CallChain::common_add(pFunctionPointer_t pf) {
-    _check_size();
-    _chain[_elements] = pf;
-    _elements ++;
-    return pf;
-}
-
-pFunctionPointer_t CallChain::common_add_front(pFunctionPointer_t pf) {
-    _check_size();
-    memmove(_chain + 1, _chain, _elements * sizeof(pFunctionPointer_t));
-    _chain[0] = pf;
-    _elements ++;
-    return pf;
-}
-
-} // namespace mbed

--- a/common/Ethernet.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,73 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Ethernet.h"
-
-#if DEVICE_ETHERNET
-
-#include "ethernet_api.h"
-
-namespace mbed {
-
-Ethernet::Ethernet() {
-    ethernet_init();
-}
-
-Ethernet::~Ethernet() {
-    ethernet_free();
-}
-
-int Ethernet::write(const char *data, int size) {
-    return ethernet_write(data, size);
-}
-
-int Ethernet::send() {
-    return ethernet_send();
-}
-
-int Ethernet::receive() {
-    return ethernet_receive();
-}
-
-int Ethernet::read(char *data, int size) {
-    return ethernet_read(data, size);
-}
-
-void Ethernet::address(char *mac) {
-    return ethernet_address(mac);
-}
-
-int Ethernet::link() {
-    return ethernet_link();
-}
-
-void Ethernet::set_link(Mode mode) {
-    int speed = -1;
-    int duplex = 0;
-
-    switch(mode) {
-        case AutoNegotiate : speed = -1; duplex = 0; break;
-        case HalfDuplex10  : speed = 0;  duplex = 0; break;
-        case FullDuplex10  : speed = 0;  duplex = 1; break;
-        case HalfDuplex100 : speed = 1;  duplex = 0; break;
-        case FullDuplex100 : speed = 1;  duplex = 1; break;
-    }
-
-    ethernet_set_link(speed, duplex);
-}
-
-} // namespace mbed
-
-#endif

--- a/common/FileBase.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,82 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileBase.h"
-
-namespace mbed {
-
-FileBase *FileBase::_head = NULL;
-
-FileBase::FileBase(const char *name, PathType t) : _next(NULL),
-                                                   _name(name),
-                                                   _path_type(t) {
-    if (name != NULL) {
-        // put this object at head of the list
-        _next = _head;
-        _head = this;
-    } else {
-        _next = NULL;
-    }
-}
-
-FileBase::~FileBase() {
-    if (_name != NULL) {
-        // remove this object from the list
-        if (_head == this) { // first in the list, so just drop me
-            _head = _next;
-        } else {             // find the object before me, then drop me
-            FileBase *p = _head;
-            while (p->_next != this) {
-                p = p->_next;
-            }
-            p->_next = _next;
-        }
-    }
-}
-
-FileBase *FileBase::lookup(const char *name, unsigned int len) {
-    FileBase *p = _head;
-    while (p != NULL) {
-        /* Check that p->_name matches name and is the correct length */
-        if (p->_name != NULL && std::strncmp(p->_name, name, len) == 0 && std::strlen(p->_name) == len) {
-            return p;
-        }
-        p = p->_next;
-    }
-    return NULL;
-}
-
-FileBase *FileBase::get(int n) {
-    FileBase *p = _head;
-    int m = 0;
-    while (p != NULL) {
-        if (m == n) return p;
-
-        m++;
-        p = p->_next;
-    }
-    return NULL;
-}
-
-const char* FileBase::getName(void) {
-    return _name;
-}
-
-PathType FileBase::getPathType(void) {
-    return _path_type;
-}
-
-} // namespace mbed
-

--- a/common/FileLike.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,28 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileLike.h"
-
-namespace mbed {
-
-FileLike::FileLike(const char *name) : FileHandle(), FileBase(name, FilePathType) {
-
-}
-
-FileLike::~FileLike() {
-
-}
-
-} // namespace mbed

--- a/common/FilePath.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FilePath.h"
-
-namespace mbed {
-
-FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
-    if ((file_path[0] != '/') || (file_path[1] == 0)) return;
-
-    const char* file_system = &file_path[1];
-    file_name = file_system;
-    int len = 0;
-    while (true) {
-        char c = *file_name;
-        if (c == '/') { // end of object name
-            file_name++; // point to one char after the '/'
-            break;
-        }
-        if (c == 0) { // end of object name, with no filename
-            break;
-        }
-        len++;
-        file_name++;
-    }
-
-    fb = FileBase::lookup(file_system, len);
-}
-
-const char* FilePath::fileName(void) {
-    return file_name;
-}
-
-bool FilePath::isFileSystem(void) {
-    if (NULL == fb)
-        return false;
-    return (fb->getPathType() == FileSystemPathType);
-}
-
-FileSystemLike* FilePath::fileSystem(void) {
-    if (isFileSystem()) {
-        return (FileSystemLike*)fb;
-    }
-    return NULL;
-}
-
-bool FilePath::isFile(void) {
-    if (NULL == fb)
-        return false;
-    return (fb->getPathType() == FilePathType);
-}
-
-FileLike* FilePath::file(void) {
-    if (isFile()) {
-        return (FileLike*)fb;
-    }
-    return NULL;
-}
-
-bool FilePath::exists(void) {
-    return fb != NULL;
-}
-
-} // namespace mbed

--- a/common/FileSystemLike.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "FileSystemLike.h"
-
-namespace mbed {
-
-class BaseDirHandle : public DirHandle {
-public:
-    /*
-      We keep track of our current location as the n'th object in the
-      FileSystemLike list. Using a Base* instead would cause problems if that
-      object were to be destroyed between readdirs.
-      Using this method does mean though that destroying/creating objects can
-      give unusual results from readdir.
-    */
-    off_t n;
-    struct dirent cur_entry;
-
-    BaseDirHandle() : n(0), cur_entry() {
-    }
-
-    virtual int closedir() {
-        delete this;
-        return 0;
-    }
-
-    virtual struct dirent *readdir() {
-        FileBase *ptr = FileBase::get(n);
-        if (ptr == NULL) return NULL;
-
-        /* Increment n, so next readdir gets the next item */
-        n++;
-
-        /* Setup cur entry and return a pointer to it */
-        std::strncpy(cur_entry.d_name, ptr->getName(), NAME_MAX);
-        return &cur_entry;
-    }
-
-    virtual off_t telldir() {
-        return n;
-    }
-
-    virtual void seekdir(off_t offset) {
-        n = offset;
-    }
-
-    virtual void rewinddir() {
-        n = 0;
-    }
-};
-
-FileSystemLike::FileSystemLike(const char *name) : FileBase(name, FileSystemPathType) {
-
-}
-
-FileSystemLike::~FileSystemLike() {
-
-}
-
-DirHandle *FileSystemLike::opendir() {
-    return new BaseDirHandle();
-}
-
-} // namespace mbed

--- a/common/I2C.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,128 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "I2C.h"
-
-#if DEVICE_I2C
-
-namespace mbed {
-
-I2C *I2C::_owner = NULL;
-
-I2C::I2C(PinName sda, PinName scl) :
-#if DEVICE_I2C_ASYNCH
-                                     _irq(this), _usage(DMA_USAGE_NEVER),
-#endif
-                                      _i2c(), _hz(100000) {
-    // The init function also set the frequency to 100000
-    i2c_init(&_i2c, sda, scl);
-
-    // Used to avoid unnecessary frequency updates
-    _owner = this;
-}
-
-void I2C::frequency(int hz) {
-    _hz = hz;
-
-    // We want to update the frequency even if we are already the bus owners
-    i2c_frequency(&_i2c, _hz);
-
-    // Updating the frequency of the bus we become the owners of it
-    _owner = this;
-}
-
-void I2C::aquire() {
-    if (_owner != this) {
-        i2c_frequency(&_i2c, _hz);
-        _owner = this;
-    }
-}
-
-// write - Master Transmitter Mode
-int I2C::write(int address, const char* data, int length, bool repeated) {
-    aquire();
-
-    int stop = (repeated) ? 0 : 1;
-    int written = i2c_write(&_i2c, address, data, length, stop);
-
-    return length != written;
-}
-
-int I2C::write(int data) {
-    return i2c_byte_write(&_i2c, data);
-}
-
-// read - Master Reciever Mode
-int I2C::read(int address, char* data, int length, bool repeated) {
-    aquire();
-
-    int stop = (repeated) ? 0 : 1;
-    int read = i2c_read(&_i2c, address, data, length, stop);
-
-    return length != read;
-}
-
-int I2C::read(int ack) {
-    if (ack) {
-        return i2c_byte_read(&_i2c, 0);
-    } else {
-        return i2c_byte_read(&_i2c, 1);
-    }
-}
-
-void I2C::start(void) {
-    i2c_start(&_i2c);
-}
-
-void I2C::stop(void) {
-    i2c_stop(&_i2c);
-}
-
-#if DEVICE_I2C_ASYNCH
-
-int I2C::transfer(int address, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, const event_callback_t& callback, int event, bool repeated)
-{
-    if (i2c_active(&_i2c)) {
-        return -1; // transaction ongoing
-    }
-    aquire();
-
-    _callback = callback;
-    int stop = (repeated) ? 0 : 1;
-    _irq.callback(&I2C::irq_handler_asynch);
-    i2c_transfer_asynch(&_i2c, (void *)tx_buffer, tx_length, (void *)rx_buffer, rx_length, address, stop, _irq.entry(), event, _usage);
-    return 0;
-}
-
-void I2C::abort_transfer(void)
-{
-    i2c_abort_asynch(&_i2c);
-}
-
-void I2C::irq_handler_asynch(void)
-{
-    int event = i2c_irq_handler_asynch(&_i2c);
-    if (_callback && event) {
-        _callback.call(event);
-    }
-
-}
-
-
-#endif
-
-} // namespace mbed
-
-#endif

--- a/common/I2CSlave.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "I2CSlave.h"
-
-#if DEVICE_I2CSLAVE
-
-namespace mbed {
-
-I2CSlave::I2CSlave(PinName sda, PinName scl) : _i2c() {
-    i2c_init(&_i2c, sda, scl);
-    i2c_frequency(&_i2c, 100000);
-    i2c_slave_mode(&_i2c, 1);
-}
-
-void I2CSlave::frequency(int hz) {
-    i2c_frequency(&_i2c, hz);
-}
-
-void I2CSlave::address(int address) {
-    int addr = (address & 0xFF) | 1;
-    i2c_slave_address(&_i2c, 0, addr, 0);
-}
-
-int I2CSlave::receive(void) {
-    return i2c_slave_receive(&_i2c);
-}
-
-int I2CSlave::read(char *data, int length) {
-    return i2c_slave_read(&_i2c, data, length) != length;
-}
-
-int I2CSlave::read(void) {
-    return i2c_byte_read(&_i2c, 0);
-}
-
-int I2CSlave::write(const char *data, int length) {
-    return i2c_slave_write(&_i2c, data, length) != length;
-}
-
-int I2CSlave::write(int data) {
-    return i2c_byte_write(&_i2c, data);
-}
-
-void I2CSlave::stop(void) {
-    i2c_stop(&_i2c);
-}
-
-}
-
-#endif

--- a/common/InterruptIn.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,85 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "InterruptIn.h"
-
-#if DEVICE_INTERRUPTIN
-
-namespace mbed {
-
-InterruptIn::InterruptIn(PinName pin) : gpio(),
-                                        gpio_irq(),
-                                        _rise(),
-                                        _fall() {
-    gpio_irq_init(&gpio_irq, pin, (&InterruptIn::_irq_handler), (uint32_t)this);
-    gpio_init_in(&gpio, pin);
-}
-
-InterruptIn::~InterruptIn() {
-    gpio_irq_free(&gpio_irq);
-}
-
-int InterruptIn::read() {
-    return gpio_read(&gpio);
-}
-
-void InterruptIn::mode(PinMode pull) {
-    gpio_mode(&gpio, pull);
-}
-
-void InterruptIn::rise(void (*fptr)(void)) {
-    if (fptr) {
-        _rise.attach(fptr);
-        gpio_irq_set(&gpio_irq, IRQ_RISE, 1);
-    } else {
-        gpio_irq_set(&gpio_irq, IRQ_RISE, 0);
-    }
-}
-
-void InterruptIn::fall(void (*fptr)(void)) {
-    if (fptr) {
-        _fall.attach(fptr);
-        gpio_irq_set(&gpio_irq, IRQ_FALL, 1);
-    } else {
-        gpio_irq_set(&gpio_irq, IRQ_FALL, 0);
-    }
-}
-
-void InterruptIn::_irq_handler(uint32_t id, gpio_irq_event event) {
-    InterruptIn *handler = (InterruptIn*)id;
-    switch (event) {
-        case IRQ_RISE: handler->_rise.call(); break;
-        case IRQ_FALL: handler->_fall.call(); break;
-        case IRQ_NONE: break;
-    }
-}
-
-void InterruptIn::enable_irq() {
-    gpio_irq_enable(&gpio_irq);
-}
-
-void InterruptIn::disable_irq() {
-    gpio_irq_disable(&gpio_irq);
-}
-
-#ifdef MBED_OPERATORS
-InterruptIn::operator int() {
-    return read();
-}
-#endif
-
-} // namespace mbed
-
-#endif

--- a/common/InterruptManager.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,93 +0,0 @@
-#include "cmsis.h"
-#if defined(NVIC_NUM_VECTORS)
-
-#include "InterruptManager.h"
-#include <string.h>
-
-#define CHAIN_INITIAL_SIZE    4
-
-namespace mbed {
-
-typedef void (*pvoidf)(void);
-
-InterruptManager* InterruptManager::_instance = (InterruptManager*)NULL;
-
-InterruptManager* InterruptManager::get() {
-    if (NULL == _instance)
-        _instance = new InterruptManager();
-    return _instance;
-}
-
-InterruptManager::InterruptManager() {
-    memset(_chains, 0, NVIC_NUM_VECTORS * sizeof(CallChain*));
-}
-
-void InterruptManager::destroy() {
-    // Not a good idea to call this unless NO interrupt at all
-    // is under the control of the handler; otherwise, a system crash
-    // is very likely to occur
-    if (NULL != _instance) {
-        delete _instance;
-        _instance = (InterruptManager*)NULL;
-    }
-}
-
-InterruptManager::~InterruptManager() {
-    for(int i = 0; i < NVIC_NUM_VECTORS; i++)
-        if (NULL != _chains[i])
-            delete _chains[i];
-}
-
-bool InterruptManager::must_replace_vector(IRQn_Type irq) {
-    int irq_pos = get_irq_index(irq);
-
-    if (NULL == _chains[irq_pos]) {
-        _chains[irq_pos] = new CallChain(CHAIN_INITIAL_SIZE);
-        _chains[irq_pos]->add((pvoidf)NVIC_GetVector(irq));
-        return true;
-    }
-    return false;
-}
-
-pFunctionPointer_t InterruptManager::add_common(void (*function)(void), IRQn_Type irq, bool front) {
-    int irq_pos = get_irq_index(irq);
-    bool change = must_replace_vector(irq);
-
-    pFunctionPointer_t pf = front ? _chains[irq_pos]->add_front(function) : _chains[irq_pos]->add(function);
-    if (change)
-        NVIC_SetVector(irq, (uint32_t)&InterruptManager::static_irq_helper);
-    return pf;
-}
-
-bool InterruptManager::remove_handler(pFunctionPointer_t handler, IRQn_Type irq) {
-    int irq_pos = get_irq_index(irq);
-
-    if (NULL == _chains[irq_pos])
-        return false;
-    if (!_chains[irq_pos]->remove(handler))
-        return false;
-    // If there's a single function left in the chain, swith the interrupt vector
-    // to call that function directly. This way we save both time and space.
-    if (_chains[irq_pos]->size() == 1 && NULL != _chains[irq_pos]->get(0)->get_function()) {
-        NVIC_SetVector(irq, (uint32_t)_chains[irq_pos]->get(0)->get_function());
-        delete _chains[irq_pos];
-        _chains[irq_pos] = (CallChain*) NULL;
-    }
-    return true;
-}
-
-void InterruptManager::irq_helper() {
-    _chains[__get_IPSR()]->call();
-}
-
-int InterruptManager::get_irq_index(IRQn_Type irq) {
-    return (int)irq + NVIC_USER_IRQ_OFFSET;
-}
-
-void InterruptManager::static_irq_helper() {
-    InterruptManager::get()->irq_helper();
-}
-
-} // namespace mbed
-
-#endif

--- a/common/LocalFileSystem.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,223 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "LocalFileSystem.h"
-
-#if DEVICE_LOCALFILESYSTEM
-
-#include "semihost_api.h"
-#include <string.h>
-#include <stdio.h>
-
-namespace mbed {
-
-/* Extension to FINFO type defined in RTL.h (in Keil RL) - adds 'create time'. */
-typedef struct {
-    unsigned char  hr;   /* Hours    [0..23]                  */
-    unsigned char  min;  /* Minutes  [0..59]                  */
-    unsigned char  sec;  /* Seconds  [0..59]                  */
-    unsigned char  day;  /* Day      [1..31]                  */
-    unsigned char  mon;  /* Month    [1..12]                  */
-    unsigned short year; /* Year     [1980..2107]             */
-} FTIME;
-
-typedef struct {         /* File Search info record           */
-    char  name[32];      /* File name                         */
-    long  size;          /* File size in bytes                */
-    int   fileID;        /* System File Identification        */
-    FTIME create_time;   /* Date & time file was created      */
-    FTIME write_time;    /* Date & time of last write         */
-} XFINFO;
-
-#define RESERVED_FOR_USER_APPLICATIONS (0x100) /* 0x100 - 0x1ff */
-#define USR_XFFIND (RESERVED_FOR_USER_APPLICATIONS + 0)
-
-static int xffind (const char *pattern, XFINFO *info) {
-    unsigned param[4];
-
-    param[0] = (unsigned long)pattern;
-    param[1] = (unsigned long)strlen(pattern);
-    param[2] = (unsigned long)info;
-    param[3] = (unsigned long)sizeof(XFINFO);
-
-    return __semihost(USR_XFFIND, param);
-}
-
-#define OPEN_R          0
-#define OPEN_B          1
-#define OPEN_PLUS       2
-#define OPEN_W          4
-#define OPEN_A          8
-#define OPEN_INVALID   -1
-
-int posix_to_semihost_open_flags(int flags) {
-    /* POSIX flags -> semihosting open mode */
-    int openmode;
-    if (flags & O_RDWR) {
-        /* a plus mode */
-        openmode = OPEN_PLUS;
-        if (flags & O_APPEND) {
-            openmode |= OPEN_A;
-        } else if (flags & O_TRUNC) {
-            openmode |= OPEN_W;
-        } else {
-            openmode |= OPEN_R;
-        }
-    } else if (flags & O_WRONLY) {
-        /* write or append */
-        if (flags & O_APPEND) {
-            openmode = OPEN_A;
-        } else {
-            openmode = OPEN_W;
-        }
-    } else if (flags == O_RDONLY) {
-        /* read mode */
-        openmode = OPEN_R;
-    } else {
-        /* invalid flags */
-        openmode = OPEN_INVALID;
-    }
-
-    return openmode;
-}
-
-FILEHANDLE local_file_open(const char* name, int flags) {
-    int openmode = posix_to_semihost_open_flags(flags);
-    if (openmode == OPEN_INVALID) {
-        return (FILEHANDLE)NULL;
-    }
-
-    FILEHANDLE fh = semihost_open(name, openmode);
-    if (fh == -1) {
-        return (FILEHANDLE)NULL;
-    }
-
-    return fh;
-}
-
-LocalFileHandle::LocalFileHandle(FILEHANDLE fh) : _fh(fh), pos(0) {
-}
-
-int LocalFileHandle::close() {
-    int retval = semihost_close(_fh);
-    delete this;
-    return retval;
-}
-
-ssize_t LocalFileHandle::write(const void *buffer, size_t length) {
-    ssize_t n = semihost_write(_fh, (const unsigned char*)buffer, length, 0); // number of characters not written
-    n = length - n; // number of characters written
-    pos += n;
-    return n;
-}
-
-ssize_t LocalFileHandle::read(void *buffer, size_t length) {
-    ssize_t n = semihost_read(_fh, (unsigned char*)buffer, length, 0); // number of characters not read
-    n = length - n; // number of characters read
-    pos += n;
-    return n;
-}
-
-int LocalFileHandle::isatty() {
-    return semihost_istty(_fh);
-}
-
-off_t LocalFileHandle::lseek(off_t position, int whence) {
-    if (whence == SEEK_CUR) {
-        position += pos;
-    } else if (whence == SEEK_END) {
-        position += semihost_flen(_fh);
-    } /* otherwise SEEK_SET, so position is fine */
-
-    /* Always seems to return -1, so just ignore for now. */
-    semihost_seek(_fh, position);
-    pos = position;
-    return position;
-}
-
-int LocalFileHandle::fsync() {
-    return semihost_ensure(_fh);
-}
-
-off_t LocalFileHandle::flen() {
-    return semihost_flen(_fh);
-}
-
-class LocalDirHandle : public DirHandle {
-
-public:
-    struct dirent cur_entry;
-    XFINFO info;
-
-    LocalDirHandle() : cur_entry(), info() {
-    }
-
-    virtual int closedir() {
-        delete this;
-        return 0;
-    }
-
-    virtual struct dirent *readdir() {
-        if (xffind("*", &info)!=0) {
-            return NULL;
-        }
-        memcpy(cur_entry.d_name, info.name, sizeof(info.name));
-        return &cur_entry;
-    }
-
-    virtual void rewinddir() {
-        info.fileID = 0;
-    }
-
-    virtual off_t telldir() {
-        return info.fileID;
-    }
-
-    virtual void seekdir(off_t offset) {
-        info.fileID = offset;
-    }
-};
-
-FileHandle *LocalFileSystem::open(const char* name, int flags) {
-    /* reject filenames with / in them */
-    for (const char *tmp = name; *tmp; tmp++) {
-        if (*tmp == '/') {
-            return NULL;
-        }
-    }
-
-    int openmode = posix_to_semihost_open_flags(flags);
-    if (openmode == OPEN_INVALID) {
-        return NULL;
-    }
-
-    FILEHANDLE fh = semihost_open(name, openmode);
-    if (fh == -1) {
-        return NULL;
-    }
-    return new LocalFileHandle(fh);
-}
-
-int LocalFileSystem::remove(const char *filename) {
-    return semihost_remove(filename);
-}
-
-DirHandle *LocalFileSystem::opendir(const char *name) {
-    return new LocalDirHandle();
-}
-
-} // namespace mbed
-
-#endif

--- a/common/RawSerial.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,67 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "RawSerial.h"
-#include "wait_api.h"
-#include <cstdarg>
-
-#if DEVICE_SERIAL
-
-#define STRING_STACK_LIMIT    120
-
-namespace mbed {
-
-RawSerial::RawSerial(PinName tx, PinName rx) : SerialBase(tx, rx) {
-}
-
-int RawSerial::getc() {
-    return _base_getc();
-}
-
-int RawSerial::putc(int c) {
-    return _base_putc(c);
-}
-
-int RawSerial::puts(const char *str) {
-    while (*str)
-        putc(*str ++);
-    return 0;
-}
-
-// Experimental support for printf in RawSerial. No Stream inheritance
-// means we can't call printf() directly, so we use sprintf() instead.
-// We only call malloc() for the sprintf() buffer if the buffer
-// length is above a certain threshold, otherwise we use just the stack.
-int RawSerial::printf(const char *format, ...) {
-    std::va_list arg;
-    va_start(arg, format);
-    int len = vsnprintf(NULL, 0, format, arg);
-    if (len < STRING_STACK_LIMIT) {
-        char temp[STRING_STACK_LIMIT];
-        vsprintf(temp, format, arg);
-        puts(temp);
-    } else {
-        char *temp = new char[len + 1];
-        vsprintf(temp, format, arg);
-        puts(temp);
-        delete[] temp;
-    }
-    va_end(arg);
-    return len;
-}
-
-} // namespace mbed
-
-#endif

--- a/common/SPI.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,180 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "SPI.h"
-
-#if DEVICE_SPI
-
-namespace mbed {
-
-#if DEVICE_SPI_ASYNCH && TRANSACTION_QUEUE_SIZE_SPI
-CircularBuffer<Transaction<SPI>, TRANSACTION_QUEUE_SIZE_SPI> SPI::_transaction_buffer;
-#endif
-
-SPI::SPI(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
-        _spi(),
-#if DEVICE_SPI_ASYNCH
-        _irq(this),
-        _usage(DMA_USAGE_NEVER),
-#endif
-        _bits(8),
-        _mode(0),
-        _hz(1000000) {
-    spi_init(&_spi, mosi, miso, sclk, ssel);
-    spi_format(&_spi, _bits, _mode, 0);
-    spi_frequency(&_spi, _hz);
-}
-
-void SPI::format(int bits, int mode) {
-    _bits = bits;
-    _mode = mode;
-    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
-    aquire();
-}
-
-void SPI::frequency(int hz) {
-    _hz = hz;
-    SPI::_owner = NULL; // Not that elegant, but works. rmeyer
-    aquire();
-}
-
-SPI* SPI::_owner = NULL;
-
-// ignore the fact there are multiple physical spis, and always update if it wasnt us last
-void SPI::aquire() {
-     if (_owner != this) {
-        spi_format(&_spi, _bits, _mode, 0);
-        spi_frequency(&_spi, _hz);
-        _owner = this;
-    }
-}
-
-int SPI::write(int value) {
-    aquire();
-    return spi_master_write(&_spi, value);
-}
-
-#if DEVICE_SPI_ASYNCH
-
-int SPI::transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
-{
-    if (spi_active(&_spi)) {
-        return queue_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
-    }
-    start_transfer(tx_buffer, tx_length, rx_buffer, rx_length, bit_width, callback, event);
-    return 0;
-}
-
-void SPI::abort_transfer()
-{
-    spi_abort_asynch(&_spi);
-#if TRANSACTION_QUEUE_SIZE_SPI
-    dequeue_transaction();
-#endif
-}
-
-
-void SPI::clear_transfer_buffer()
-{
-#if TRANSACTION_QUEUE_SIZE_SPI
-    _transaction_buffer.reset();
-#endif
-}
-
-void SPI::abort_all_transfers()
-{
-    clear_transfer_buffer();
-    abort_transfer();
-}
-
-int SPI::set_dma_usage(DMAUsage usage)
-{
-    if (spi_active(&_spi)) {
-        return -1;
-    }
-    _usage = usage;
-    return  0;
-}
-
-int SPI::queue_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
-{
-#if TRANSACTION_QUEUE_SIZE_SPI
-    transaction_t t;
-
-    t.tx_buffer = const_cast<void *>(tx_buffer);
-    t.tx_length = tx_length;
-    t.rx_buffer = rx_buffer;
-    t.rx_length = rx_length;
-    t.event = event;
-    t.callback = callback;
-    t.width = bit_width;
-    Transaction<SPI> transaction(this, t);
-    if (_transaction_buffer.full()) {
-        return -1; // the buffer is full
-    } else {
-        _transaction_buffer.push(transaction);
-        return 0;
-    }
-#else
-    return -1;
-#endif
-}
-
-void SPI::start_transfer(const void *tx_buffer, int tx_length, void *rx_buffer, int rx_length, unsigned char bit_width, const event_callback_t& callback, int event)
-{
-    aquire();
-    _callback = callback;
-    _irq.callback(&SPI::irq_handler_asynch);
-    spi_master_transfer(&_spi, tx_buffer, tx_length, rx_buffer, rx_length, bit_width, _irq.entry(), event , _usage);
-}
-
-#if TRANSACTION_QUEUE_SIZE_SPI
-
-void SPI::start_transaction(transaction_t *data)
-{
-    start_transfer(data->tx_buffer, data->tx_length, data->rx_buffer, data->rx_length, data->width, data->callback, data->event);
-}
-
-void SPI::dequeue_transaction()
-{
-    Transaction<SPI> t;
-    if (_transaction_buffer.pop(t)) {
-        SPI* obj = t.get_object();
-        transaction_t* data = t.get_transaction();
-        obj->start_transaction(data);
-    }
-}
-
-#endif
-
-void SPI::irq_handler_asynch(void)
-{
-    int event = spi_irq_handler_asynch(&_spi);
-    if (_callback && (event & SPI_EVENT_ALL)) {
-        _callback.call(event & SPI_EVENT_ALL);
-    }
-#if TRANSACTION_QUEUE_SIZE_SPI
-    if (event & (SPI_EVENT_ALL | SPI_EVENT_INTERNAL_TRANSFER_COMPLETE)) {
-        // SPI peripheral is free (event happend), dequeue transaction
-        dequeue_transaction();
-    }
-#endif
-}
-
-#endif
-
-} // namespace mbed
-
-#endif

--- a/common/SPISlave.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,58 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "SPISlave.h"
-
-#if DEVICE_SPISLAVE
-
-namespace mbed {
-
-SPISlave::SPISlave(PinName mosi, PinName miso, PinName sclk, PinName ssel) :
-    _spi(),
-    _bits(8),
-    _mode(0),
-    _hz(1000000)
- {
-    spi_init(&_spi, mosi, miso, sclk, ssel);
-    spi_format(&_spi, _bits, _mode, 1);
-    spi_frequency(&_spi, _hz);
-}
-
-void SPISlave::format(int bits, int mode) {
-    _bits = bits;
-    _mode = mode;
-    spi_format(&_spi, _bits, _mode, 1);
-}
-
-void SPISlave::frequency(int hz) {
-    _hz = hz;
-    spi_frequency(&_spi, _hz);
-}
-
-int SPISlave::receive(void) {
-    return(spi_slave_receive(&_spi));
-}
-
-int SPISlave::read(void) {
-    return(spi_slave_read(&_spi));
-}
-
-void SPISlave::reply(int value) {
-    spi_slave_write(&_spi, value);
-}
-
-} // namespace mbed
-
-#endif

--- a/common/Serial.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,36 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Serial.h"
-#include "wait_api.h"
-
-#if DEVICE_SERIAL
-
-namespace mbed {
-
-Serial::Serial(PinName tx, PinName rx, const char *name) : SerialBase(tx, rx), Stream(name) {
-}
-
-int Serial::_getc() {
-    return _base_getc();
-}
-
-int Serial::_putc(int c) {
-    return _base_putc(c);
-}
-
-} // namespace mbed
-
-#endif

--- a/common/SerialBase.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,212 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "SerialBase.h"
-#include "wait_api.h"
-
-#if DEVICE_SERIAL
-
-namespace mbed {
-
-SerialBase::SerialBase(PinName tx, PinName rx) :
-#if DEVICE_SERIAL_ASYNCH
-                                                 _thunk_irq(this), _tx_usage(DMA_USAGE_NEVER),
-                                                 _rx_usage(DMA_USAGE_NEVER),
-#endif
-                                                _serial(), _baud(9600) {
-    serial_init(&_serial, tx, rx);
-    serial_irq_handler(&_serial, SerialBase::_irq_handler, (uint32_t)this);
-}
-
-void SerialBase::baud(int baudrate) {
-    serial_baud(&_serial, baudrate);
-    _baud = baudrate;
-}
-
-void SerialBase::format(int bits, Parity parity, int stop_bits) {
-    serial_format(&_serial, bits, (SerialParity)parity, stop_bits);
-}
-
-int SerialBase::readable() {
-    return serial_readable(&_serial);
-}
-
-
-int SerialBase::writeable() {
-    return serial_writable(&_serial);
-}
-
-void SerialBase::attach(void (*fptr)(void), IrqType type) {
-    if (fptr) {
-        _irq[type].attach(fptr);
-        serial_irq_set(&_serial, (SerialIrq)type, 1);
-    } else {
-        serial_irq_set(&_serial, (SerialIrq)type, 0);
-    }
-}
-
-void SerialBase::_irq_handler(uint32_t id, SerialIrq irq_type) {
-    SerialBase *handler = (SerialBase*)id;
-    handler->_irq[irq_type].call();
-}
-
-int SerialBase::_base_getc() {
-    return serial_getc(&_serial);
-}
-
-int SerialBase::_base_putc(int c) {
-    serial_putc(&_serial, c);
-    return c;
-}
-
-void SerialBase::send_break() {
-  // Wait for 1.5 frames before clearing the break condition
-  // This will have different effects on our platforms, but should
-  // ensure that we keep the break active for at least one frame.
-  // We consider a full frame (1 start bit + 8 data bits bits +
-  // 1 parity bit + 2 stop bits = 12 bits) for computation.
-  // One bit time (in us) = 1000000/_baud
-  // Twelve bits: 12000000/baud delay
-  // 1.5 frames: 18000000/baud delay
-  serial_break_set(&_serial);
-  wait_us(18000000/_baud);
-  serial_break_clear(&_serial);
-}
-
-#if DEVICE_SERIAL_FC
-void SerialBase::set_flow_control(Flow type, PinName flow1, PinName flow2) {
-    FlowControl flow_type = (FlowControl)type;
-    switch(type) {
-        case RTS:
-            serial_set_flow_control(&_serial, flow_type, flow1, NC);
-            break;
-
-        case CTS:
-            serial_set_flow_control(&_serial, flow_type, NC, flow1);
-            break;
-
-        case RTSCTS:
-        case Disabled:
-            serial_set_flow_control(&_serial, flow_type, flow1, flow2);
-            break;
-
-        default:
-            break;
-    }
-}
-#endif
-
-#if DEVICE_SERIAL_ASYNCH
-
-int SerialBase::write(const uint8_t *buffer, int length, const event_callback_t& callback, int event)
-{
-    if (serial_tx_active(&_serial)) {
-        return -1; // transaction ongoing
-    }
-    start_write((void *)buffer, length, 8, callback, event);
-    return 0;
-}
-
-int SerialBase::write(const uint16_t *buffer, int length, const event_callback_t& callback, int event)
-{
-    if (serial_tx_active(&_serial)) {
-        return -1; // transaction ongoing
-    }
-    start_write((void *)buffer, length, 16, callback, event);
-    return 0;
-}
-
-void SerialBase::start_write(const void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event)
-{
-    _tx_callback = callback;
-
-    _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
-    serial_tx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, _tx_usage);
-}
-
-void SerialBase::abort_write(void)
-{
-    serial_tx_abort_asynch(&_serial);
-}
-
-void SerialBase::abort_read(void)
-{
-    serial_rx_abort_asynch(&_serial);
-}
-
-int SerialBase::set_dma_usage_tx(DMAUsage usage)
-{
-    if (serial_tx_active(&_serial)) {
-        return -1;
-    }
-    _tx_usage = usage;
-    return 0;
-}
-
-int SerialBase::set_dma_usage_rx(DMAUsage usage)
-{
-    if (serial_tx_active(&_serial)) {
-        return -1;
-    }
-    _rx_usage = usage;
-    return 0;
-}
-
-int SerialBase::read(uint8_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
-{
-    if (serial_rx_active(&_serial)) {
-        return -1; // transaction ongoing
-    }
-    start_read((void*)buffer, length, 8, callback, event, char_match);
-    return 0;
-}
-
-
-int SerialBase::read(uint16_t *buffer, int length, const event_callback_t& callback, int event, unsigned char char_match)
-{
-    if (serial_rx_active(&_serial)) {
-        return -1; // transaction ongoing
-    }
-    start_read((void*)buffer, length, 16, callback, event, char_match);
-    return 0;
-}
-
-
-void SerialBase::start_read(void *buffer, int buffer_size, char buffer_width, const event_callback_t& callback, int event, unsigned char char_match)
-{
-    _rx_callback = callback;
-    _thunk_irq.callback(&SerialBase::interrupt_handler_asynch);
-    serial_rx_asynch(&_serial, buffer, buffer_size, buffer_width, _thunk_irq.entry(), event, char_match, _rx_usage);
-}
-
-void SerialBase::interrupt_handler_asynch(void)
-{
-    int event = serial_irq_handler_asynch(&_serial);
-    int rx_event = event & SERIAL_EVENT_RX_MASK;
-    if (_rx_callback && rx_event) {
-        _rx_callback.call(rx_event);
-    }
-
-    int tx_event = event & SERIAL_EVENT_TX_MASK;
-    if (_tx_callback && tx_event) {
-        _tx_callback.call(tx_event);
-    }
-}
-
-#endif
-
-} // namespace mbed
-
-#endif

--- a/common/Stream.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,111 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Stream.h"
-
-#include <cstdarg>
-
-namespace mbed {
-
-Stream::Stream(const char *name) : FileLike(name), _file(NULL) {
-    /* open ourselves */
-    char buf[12]; /* :0x12345678 + null byte */
-    std::sprintf(buf, ":%p", this);
-    _file = std::fopen(buf, "w+");
-    mbed_set_unbuffered_stream(_file);
-}
-
-Stream::~Stream() {
-    fclose(_file);
-}
-
-int Stream::putc(int c) {
-    fflush(_file);
-    return std::fputc(c, _file);
-}
-int Stream::puts(const char *s) {
-    fflush(_file);
-    return std::fputs(s, _file);
-}
-int Stream::getc() {
-    fflush(_file);
-    return mbed_getc(_file);   
-}
-char* Stream::gets(char *s, int size) {
-    fflush(_file);
-    return mbed_gets(s,size,_file);
-}
-
-int Stream::close() {
-    return 0;
-}
-
-ssize_t Stream::write(const void* buffer, size_t length) {
-    const char* ptr = (const char*)buffer;
-    const char* end = ptr + length;
-    while (ptr != end) {
-        if (_putc(*ptr++) == EOF) {
-            break;
-        }
-    }
-    return ptr - (const char*)buffer;
-}
-
-ssize_t Stream::read(void* buffer, size_t length) {
-    char* ptr = (char*)buffer;
-    char* end = ptr + length;
-    while (ptr != end) {
-        int c = _getc();
-        if (c==EOF) break;
-        *ptr++ = c;
-    }
-    return ptr - (const char*)buffer;
-}
-
-off_t Stream::lseek(off_t offset, int whence) {
-    return 0;
-}
-
-int Stream::isatty() {
-    return 0;
-}
-
-int Stream::fsync() {
-    return 0;
-}
-
-off_t Stream::flen() {
-    return 0;
-}
-
-int Stream::printf(const char* format, ...) {
-    std::va_list arg;
-    va_start(arg, format);
-    fflush(_file);
-    int r = vfprintf(_file, format, arg);
-    va_end(arg);
-    return r;
-}
-
-int Stream::scanf(const char* format, ...) {
-    std::va_list arg;
-    va_start(arg, format);
-    fflush(_file);
-    int r = vfscanf(_file, format, arg);
-    va_end(arg);
-    return r;
-}
-
-} // namespace mbed

--- a/common/Ticker.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,40 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Ticker.h"
-
-#include "TimerEvent.h"
-#include "FunctionPointer.h"
-#include "ticker_api.h"
-
-namespace mbed {
-
-void Ticker::detach() {
-    remove();
-    _function.attach(0);
-}
-
-void Ticker::setup(timestamp_t t) {
-    remove();
-    _delay = t;
-    insert(_delay + ticker_read(_ticker_data));
-}
-
-void Ticker::handler() {
-    insert(event.timestamp + _delay);
-    _function.call();
-}
-
-} // namespace mbed

--- a/common/Timeout.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,24 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Timeout.h"
-
-namespace mbed {
-
-void Timeout::handler() {
-    _function.call();
-}
-
-} // namespace mbed

--- a/common/Timer.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,73 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "Timer.h"
-#include "ticker_api.h"
-#include "us_ticker_api.h"
-
-namespace mbed {
-
-Timer::Timer() : _running(), _start(), _time(), _ticker_data(get_us_ticker_data()) {
-    reset();
-}
-
-Timer::Timer(const ticker_data_t *data) : _running(), _start(), _time(), _ticker_data(data) {
-    reset();
-}
-
-void Timer::start() {
-    if (!_running) {
-        _start = ticker_read(_ticker_data);
-        _running = 1;
-    }
-}
-
-void Timer::stop() {
-    _time += slicetime();
-    _running = 0;
-}
-
-int Timer::read_us() {
-    return _time + slicetime();
-}
-
-float Timer::read() {
-    return (float)read_us() / 1000000.0f;
-}
-
-int Timer::read_ms() {
-    return read_us() / 1000;
-}
-
-int Timer::slicetime() {
-    if (_running) {
-        return ticker_read(_ticker_data) - _start;
-    } else {
-        return 0;
-    }
-}
-
-void Timer::reset() {
-    _start = ticker_read(_ticker_data);
-    _time = 0;
-}
-
-#ifdef MBED_OPERATORS
-Timer::operator float() {
-    return read();
-}
-#endif
-
-} // namespace mbed

--- a/common/TimerEvent.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,51 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "TimerEvent.h"
-#include "cmsis.h"
-
-#include <stddef.h>
-#include "ticker_api.h"
-#include "us_ticker_api.h"
-
-namespace mbed {
-
-TimerEvent::TimerEvent() : event(), _ticker_data(get_us_ticker_data()) {
-    ticker_set_handler(_ticker_data, (&TimerEvent::irq));
-}
-
-TimerEvent::TimerEvent(const ticker_data_t *data) : event(), _ticker_data(data) {
-    ticker_set_handler(_ticker_data, (&TimerEvent::irq));
-}
-
-void TimerEvent::irq(uint32_t id) {
-    TimerEvent *timer_event = (TimerEvent*)id;
-    timer_event->handler();
-}
-
-TimerEvent::~TimerEvent() {
-    remove();
-}
-
-// insert in to linked list
-void TimerEvent::insert(timestamp_t timestamp) {
-    ticker_insert_event(_ticker_data, &event, timestamp, (uint32_t)this);
-}
-
-void TimerEvent::remove() {
-    ticker_remove_event(_ticker_data, &event);
-}
-
-} // namespace mbed

--- a/common/assert.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,22 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "mbed_assert.h"
-#include "mbed_error.h"
-
-void mbed_assert_internal(const char *expr, const char *file, int line)
-{
-    error("mbed assertation failed: %s, file: %s, line %d \n", expr, file, line);
-}

--- a/common/board.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,59 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-#include "wait_api.h"
-#include "toolchain.h"
-#include "mbed_interface.h"
-
-WEAK void mbed_die(void) {
-#if !defined (NRF51_H) && !defined(TARGET_EFM32)
-	__disable_irq();	// dont allow interrupts to disturb the flash pattern
-#endif
-#if   (DEVICE_ERROR_RED == 1)
-    gpio_t led_red; gpio_init_out(&led_red, LED_RED);
-#elif (DEVICE_ERROR_PATTERN == 1)
-    gpio_t led_1; gpio_init_out(&led_1, LED1);
-    gpio_t led_2; gpio_init_out(&led_2, LED2);
-    gpio_t led_3; gpio_init_out(&led_3, LED3);
-    gpio_t led_4; gpio_init_out(&led_4, LED4);
-#endif
-
-    while (1) {
-#if   (DEVICE_ERROR_RED == 1)
-        gpio_write(&led_red, 1);
-
-#elif (DEVICE_ERROR_PATTERN == 1)
-        gpio_write(&led_1, 1);
-        gpio_write(&led_2, 0);
-        gpio_write(&led_3, 0);
-        gpio_write(&led_4, 1);
-#endif
-
-        wait_ms(150);
-
-#if   (DEVICE_ERROR_RED == 1)
-        gpio_write(&led_red, 0);
-
-#elif (DEVICE_ERROR_PATTERN == 1)
-        gpio_write(&led_1, 0);
-        gpio_write(&led_2, 1);
-        gpio_write(&led_3, 1);
-        gpio_write(&led_4, 0);
-#endif
-
-        wait_ms(150);
-    }
-}

--- a/common/error.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,33 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stdlib.h>
-#include <stdarg.h>
-#include "device.h"
-#include "toolchain.h"
-#include "mbed_error.h"
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#endif
-
-WEAK void error(const char* format, ...) {
-#if DEVICE_STDIO_MESSAGES
-    va_list arg;
-    va_start(arg, format);
-    vfprintf(stderr, format, arg);
-    va_end(arg);
-#endif
-    exit(1);
-}

--- a/common/gpio.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,61 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "gpio_api.h"
-
-static inline void _gpio_init_in(gpio_t* gpio, PinName pin, PinMode mode)
-{
-    gpio_init(gpio, pin);
-    if (pin != NC) {
-        gpio_dir(gpio, PIN_INPUT);
-        gpio_mode(gpio, mode);
-    }
-}
-
-static inline void _gpio_init_out(gpio_t* gpio, PinName pin, PinMode mode, int value)
-{
-    gpio_init(gpio, pin);
-    if (pin != NC) {
-        gpio_write(gpio, value);
-        gpio_dir(gpio, PIN_OUTPUT);
-        gpio_mode(gpio, mode);
-    }
-}
-
-void gpio_init_in(gpio_t* gpio, PinName pin) {
-    gpio_init_in_ex(gpio, pin, PullDefault);
-}
-
-void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode) {
-    _gpio_init_in(gpio, pin, mode);
-}
-
-void gpio_init_out(gpio_t* gpio, PinName pin) {
-    gpio_init_out_ex(gpio, pin, 0);
-}
-
-void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value) {
-    _gpio_init_out(gpio, pin, PullNone, value);
-}
-
-void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value) {
-    if (direction == PIN_INPUT) {
-        _gpio_init_in(gpio, pin, mode);
-        if (pin != NC)
-            gpio_write(gpio, value); // we prepare the value in case it is switched later
-    } else {
-        _gpio_init_out(gpio, pin, mode, value);
-    }
-}

--- a/common/lp_ticker_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "lp_ticker_api.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-static ticker_event_queue_t events;
-
-static const ticker_interface_t lp_interface = {
-    .init = lp_ticker_init,
-    .read = lp_ticker_read,
-    .disable_interrupt = lp_ticker_disable_interrupt,
-    .clear_interrupt = lp_ticker_clear_interrupt,
-    .set_interrupt = lp_ticker_set_interrupt,
-};
-
-static const ticker_data_t lp_data = {
-    .interface = &lp_interface,
-    .queue = &events,
-};
-
-const ticker_data_t* get_lp_ticker_data(void)
-{
-    return &lp_data;
-}
-
-void lp_ticker_irq_handler(void)
-{
-    ticker_irq_handler(&lp_data);
-}
-
-#endif

--- a/common/mbed_interface.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stdio.h>
-#include "mbed_interface.h"
-
-#include "gpio_api.h"
-#include "wait_api.h"
-#include "semihost_api.h"
-#include "mbed_error.h"
-#include "toolchain.h"
-
-#if DEVICE_SEMIHOST
-
-// return true if a debugger is attached, indicating mbed interface is connected
-int mbed_interface_connected(void) {
-    return semihost_connected();
-}
-
-int mbed_interface_reset(void) {
-    if (mbed_interface_connected()) {
-        semihost_reset();
-        return 0;
-    } else {
-        return -1;
-    }
-}
-
-WEAK int mbed_interface_uid(char *uid) {
-    if (mbed_interface_connected()) {
-        return semihost_uid(uid); // Returns 0 if successful, -1 on failure
-    } else {
-        uid[0] = 0;
-        return -1;
-    }
-}
-
-int mbed_interface_disconnect(void) {
-    int res;
-    if (mbed_interface_connected()) {
-        if ((res = semihost_disabledebug()) != 0)
-            return res;
-        while (mbed_interface_connected());
-        return 0;
-    } else {
-        return -1;
-    }
-}
-
-int mbed_interface_powerdown(void) {
-    int res;
-    if (mbed_interface_connected()) {
-        if ((res = semihost_powerdown()) != 0)
-            return res;
-        while (mbed_interface_connected());
-        return 0;
-    } else {
-        return -1;
-    }
-}
-
-// for backward compatibility
-void mbed_reset(void) {
-    mbed_interface_reset();
-}
-
-WEAK int mbed_uid(char *uid) {
-    return mbed_interface_uid(uid);
-}
-#endif
-
-WEAK void mbed_mac_address(char *mac) {
-#if DEVICE_SEMIHOST
-    char uid[DEVICE_ID_LENGTH + 1];
-    int i;
-
-    // if we have a UID, extract the MAC
-    if (mbed_interface_uid(uid) == 0) {
-        char *p = uid;
-#if defined(DEVICE_MAC_OFFSET)
-        p += DEVICE_MAC_OFFSET;
-#endif
-        for (i=0; i<6; i++) {
-            int byte;
-            sscanf(p, "%2x", &byte);
-            mac[i] = byte;
-            p += 2;
-        }
-        mac[0] &= ~0x01;    // reset the IG bit in the address; see IEE 802.3-2002, Section 3.2.3(b)
-    } else {  // else return a default MAC
-#endif
-        mac[0] = 0x00;
-        mac[1] = 0x02;
-        mac[2] = 0xF7;
-        mac[3] = 0xF0;
-        mac[4] = 0x00;
-        mac[5] = 0x00;
-#if DEVICE_SEMIHOST
-    }
-#endif
-}

--- a/common/pinmap_common.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,89 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "pinmap.h"
-#include "mbed_error.h"
-
-void pinmap_pinout(PinName pin, const PinMap *map) {
-    if (pin == NC)
-        return;
-
-    while (map->pin != NC) {
-        if (map->pin == pin) {
-            pin_function(pin, map->function);
-
-            pin_mode(pin, PullNone);
-            return;
-        }
-        map++;
-    }
-    error("could not pinout");
-}
-
-uint32_t pinmap_merge(uint32_t a, uint32_t b) {
-    // both are the same (inc both NC)
-    if (a == b)
-        return a;
-
-    // one (or both) is not connected
-    if (a == (uint32_t)NC)
-        return b;
-    if (b == (uint32_t)NC)
-        return a;
-
-    // mis-match error case
-    error("pinmap mis-match");
-    return (uint32_t)NC;
-}
-
-uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map) {
-    while (map->pin != NC) {
-        if (map->pin == pin)
-            return map->peripheral;
-        map++;
-    }
-    return (uint32_t)NC;
-}
-
-uint32_t pinmap_peripheral(PinName pin, const PinMap* map) {
-    uint32_t peripheral = (uint32_t)NC;
-
-    if (pin == (PinName)NC)
-        return (uint32_t)NC;
-    peripheral = pinmap_find_peripheral(pin, map);
-    if ((uint32_t)NC == peripheral) // no mapping available
-        error("pinmap not found for peripheral");
-    return peripheral;
-}
-
-uint32_t pinmap_find_function(PinName pin, const PinMap* map) {
-    while (map->pin != NC) {
-        if (map->pin == pin)
-            return map->function;
-        map++;
-    }
-    return (uint32_t)NC;
-}
-
-uint32_t pinmap_function(PinName pin, const PinMap* map) {
-    uint32_t function = (uint32_t)NC;
-
-    if (pin == (PinName)NC)
-        return (uint32_t)NC;
-    function = pinmap_find_function(pin, map);
-    if ((uint32_t)NC == function) // no mapping available
-        error("pinmap not found for function");
-    return function;
-}

--- a/common/retarget.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,569 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "platform.h"
-#include "FileHandle.h"
-#include "FileSystemLike.h"
-#include "FilePath.h"
-#include "serial_api.h"
-#include "toolchain.h"
-#include "semihost_api.h"
-#include "mbed_interface.h"
-#if DEVICE_STDIO_MESSAGES
-#include <stdio.h>
-#endif
-#include <errno.h>
-
-#if defined(__ARMCC_VERSION)
-#   include <rt_sys.h>
-#   define PREFIX(x)    _sys##x
-#   define OPEN_MAX     _SYS_OPEN
-#   ifdef __MICROLIB
-#       pragma import(__use_full_stdio)
-#   endif
-
-#elif defined(__ICCARM__)
-#   include <yfuns.h>
-#   define PREFIX(x)        _##x
-#   define OPEN_MAX         16
-
-#   define STDIN_FILENO     0
-#   define STDOUT_FILENO    1
-#   define STDERR_FILENO    2
-
-#else
-#   include <sys/stat.h>
-#   include <sys/unistd.h>
-#   include <sys/syslimits.h>
-#   define PREFIX(x)    x
-#endif
-
-using namespace mbed;
-
-#if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
-// Before version 5.03, we were using a patched version of microlib with proper names
-extern const char __stdin_name[]  = ":tt";
-extern const char __stdout_name[] = ":tt";
-extern const char __stderr_name[] = ":tt";
-
-#else
-extern const char __stdin_name[]  = "/stdin";
-extern const char __stdout_name[] = "/stdout";
-extern const char __stderr_name[] = "/stderr";
-#endif
-
-/* newlib has the filehandle field in the FILE struct as a short, so
- * we can't just return a Filehandle* from _open and instead have to
- * put it in a filehandles array and return the index into that array
- * (or rather index+3, as filehandles 0-2 are stdin/out/err).
- */
-static FileHandle *filehandles[OPEN_MAX];
-
-FileHandle::~FileHandle() {
-    /* Remove all open filehandles for this */
-    for (unsigned int fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
-        if (filehandles[fh_i] == this) {
-            filehandles[fh_i] = NULL;
-        }
-    }
-}
-
-#if DEVICE_SERIAL
-extern int stdio_uart_inited;
-extern serial_t stdio_uart;
-#endif
-
-static void init_serial() {
-#if DEVICE_SERIAL
-    if (stdio_uart_inited) return;
-    serial_init(&stdio_uart, STDIO_UART_TX, STDIO_UART_RX);
-#endif
-}
-
-static inline int openmode_to_posix(int openmode) {
-    int posix = openmode;
-#ifdef __ARMCC_VERSION
-    if (openmode & OPEN_PLUS) {
-        posix = O_RDWR;
-    } else if(openmode & OPEN_W) {
-        posix = O_WRONLY;
-    } else if(openmode & OPEN_A) {
-        posix = O_WRONLY|O_APPEND;
-    } else {
-        posix = O_RDONLY;
-    }
-    /* a, w, a+, w+ all create if file does not already exist */
-    if (openmode & (OPEN_A|OPEN_W)) {
-        posix |= O_CREAT;
-    }
-    /* w and w+ truncate */
-    if (openmode & OPEN_W) {
-        posix |= O_TRUNC;
-    }
-#elif defined(__ICCARM__)
-    switch (openmode & _LLIO_RDWRMASK) {
-        case _LLIO_RDONLY: posix = O_RDONLY; break;
-        case _LLIO_WRONLY: posix = O_WRONLY; break;
-        case _LLIO_RDWR  : posix = O_RDWR  ; break;
-    }
-    if (openmode & _LLIO_CREAT ) posix |= O_CREAT;
-    if (openmode & _LLIO_APPEND) posix |= O_APPEND;
-    if (openmode & _LLIO_TRUNC ) posix |= O_TRUNC;
-#endif
-    return posix;
-}
-
-extern "C" FILEHANDLE PREFIX(_open)(const char* name, int openmode) {
-    #if defined(__MICROLIB) && (__ARMCC_VERSION>5030000)
-    // Before version 5.03, we were using a patched version of microlib with proper names
-    // This is the workaround that the microlib author suggested us
-    static int n = 0;
-    if (!std::strcmp(name, ":tt")) return n++;
-
-    #else
-    /* Use the posix convention that stdin,out,err are filehandles 0,1,2.
-     */
-    if (std::strcmp(name, __stdin_name) == 0) {
-        init_serial();
-        return 0;
-    } else if (std::strcmp(name, __stdout_name) == 0) {
-        init_serial();
-        return 1;
-    } else if (std::strcmp(name, __stderr_name) == 0) {
-        init_serial();
-        return 2;
-    }
-    #endif
-
-    // find the first empty slot in filehandles
-    unsigned int fh_i;
-    for (fh_i = 0; fh_i < sizeof(filehandles)/sizeof(*filehandles); fh_i++) {
-        if (filehandles[fh_i] == NULL) break;
-    }
-    if (fh_i >= sizeof(filehandles)/sizeof(*filehandles)) {
-        return -1;
-    }
-
-    FileHandle *res;
-
-    /* FILENAME: ":0x12345678" describes a FileLike* */
-    if (name[0] == ':') {
-        void *p;
-        sscanf(name, ":%p", &p);
-        res = (FileHandle*)p;
-
-    /* FILENAME: "/file_system/file_name" */
-    } else {
-        FilePath path(name);
-
-        if (!path.exists())
-            return -1;
-        else if (path.isFile()) {
-            res = path.file();
-        } else {
-            FileSystemLike *fs = path.fileSystem();
-            if (fs == NULL) return -1;
-            int posix_mode = openmode_to_posix(openmode);
-            res = fs->open(path.fileName(), posix_mode); /* NULL if fails */
-        }
-    }
-
-    if (res == NULL) return -1;
-    filehandles[fh_i] = res;
-
-    return fh_i + 3; // +3 as filehandles 0-2 are stdin/out/err
-}
-
-extern "C" int PREFIX(_close)(FILEHANDLE fh) {
-    if (fh < 3) return 0;
-
-    FileHandle* fhc = filehandles[fh-3];
-    filehandles[fh-3] = NULL;
-    if (fhc == NULL) return -1;
-
-    return fhc->close();
-}
-
-#if defined(__ICCARM__)
-extern "C" size_t    __write (int        fh, const unsigned char *buffer, size_t length) {
-#else
-extern "C" int PREFIX(_write)(FILEHANDLE fh, const unsigned char *buffer, unsigned int length, int mode) {
-#endif
-    int n; // n is the number of bytes written
-    if (fh < 3) {
-#if DEVICE_SERIAL
-        if (!stdio_uart_inited) init_serial();
-        for (unsigned int i = 0; i < length; i++) {
-            serial_putc(&stdio_uart, buffer[i]);
-        }
-#endif
-        n = length;
-    } else {
-        FileHandle* fhc = filehandles[fh-3];
-        if (fhc == NULL) return -1;
-
-        n = fhc->write(buffer, length);
-    }
-#ifdef __ARMCC_VERSION
-    return length-n;
-#else
-    return n;
-#endif
-}
-
-#if defined(__ICCARM__)
-extern "C" size_t    __read (int        fh, unsigned char *buffer, size_t       length) {
-#else
-extern "C" int PREFIX(_read)(FILEHANDLE fh, unsigned char *buffer, unsigned int length, int mode) {
-#endif
-    int n; // n is the number of bytes read
-    if (fh < 3) {
-        // only read a character at a time from stdin
-#if DEVICE_SERIAL
-        if (!stdio_uart_inited) init_serial();
-        *buffer = serial_getc(&stdio_uart);
-#endif
-        n = 1;
-    } else {
-        FileHandle* fhc = filehandles[fh-3];
-        if (fhc == NULL) return -1;
-
-        n = fhc->read(buffer, length);
-    }
-#ifdef __ARMCC_VERSION
-    return length-n;
-#else
-    return n;
-#endif
-}
-
-#ifdef __ARMCC_VERSION
-extern "C" int PREFIX(_istty)(FILEHANDLE fh)
-#else
-extern "C" int _isatty(FILEHANDLE fh)
-#endif
-{
-    /* stdin, stdout and stderr should be tty */
-    if (fh < 3) return 1;
-
-    FileHandle* fhc = filehandles[fh-3];
-    if (fhc == NULL) return -1;
-
-    return fhc->isatty();
-}
-
-extern "C"
-#if defined(__ARMCC_VERSION)
-int _sys_seek(FILEHANDLE fh, long position)
-#elif defined(__ICCARM__)
-long __lseek(int fh, long offset, int whence)
-#else
-int _lseek(FILEHANDLE fh, int offset, int whence)
-#endif
-{
-    if (fh < 3) return 0;
-
-    FileHandle* fhc = filehandles[fh-3];
-    if (fhc == NULL) return -1;
-
-#if defined(__ARMCC_VERSION)
-    return fhc->lseek(position, SEEK_SET);
-#else
-    return fhc->lseek(offset, whence);
-#endif
-}
-
-#ifdef __ARMCC_VERSION
-extern "C" int PREFIX(_ensure)(FILEHANDLE fh) {
-    if (fh < 3) return 0;
-
-    FileHandle* fhc = filehandles[fh-3];
-    if (fhc == NULL) return -1;
-
-    return fhc->fsync();
-}
-
-extern "C" long PREFIX(_flen)(FILEHANDLE fh) {
-    if (fh < 3) return 0;
-
-    FileHandle* fhc = filehandles[fh-3];
-    if (fhc == NULL) return -1;
-
-    return fhc->flen();
-}
-#endif
-
-
-#if !defined(__ARMCC_VERSION) && !defined(__ICCARM__)
-extern "C" int _fstat(int fd, struct stat *st) {
-    if ((STDOUT_FILENO == fd) || (STDERR_FILENO == fd) || (STDIN_FILENO == fd)) {
-        st->st_mode = S_IFCHR;
-        return  0;
-    }
-
-    errno = EBADF;
-    return -1;
-}
-#endif
-
-namespace std {
-extern "C" int remove(const char *path) {
-    FilePath fp(path);
-    FileSystemLike *fs = fp.fileSystem();
-    if (fs == NULL) return -1;
-
-    return fs->remove(fp.fileName());
-}
-
-extern "C" int rename(const char *oldname, const char *newname) {
-    FilePath fpOld(oldname);
-    FilePath fpNew(newname);
-    FileSystemLike *fsOld = fpOld.fileSystem();
-    FileSystemLike *fsNew = fpNew.fileSystem();
-
-    /* rename only if both files are on the same FS */
-    if (fsOld != fsNew || fsOld == NULL) return -1;
-
-    return fsOld->rename(fpOld.fileName(), fpNew.fileName());
-}
-
-extern "C" char *tmpnam(char *s) {
-    return NULL;
-}
-
-extern "C" FILE *tmpfile() {
-    return NULL;
-}
-} // namespace std
-
-#ifdef __ARMCC_VERSION
-extern "C" char *_sys_command_string(char *cmd, int len) {
-    return NULL;
-}
-#endif
-
-extern "C" DIR *opendir(const char *path) {
-    /* root dir is FileSystemLike */
-    if (path[0] == '/' && path[1] == 0) {
-        return FileSystemLike::opendir();
-    }
-
-    FilePath fp(path);
-    FileSystemLike* fs = fp.fileSystem();
-    if (fs == NULL) return NULL;
-
-    return fs->opendir(fp.fileName());
-}
-
-extern "C" struct dirent *readdir(DIR *dir) {
-    return dir->readdir();
-}
-
-extern "C" int closedir(DIR *dir) {
-    return dir->closedir();
-}
-
-extern "C" void rewinddir(DIR *dir) {
-    dir->rewinddir();
-}
-
-extern "C" off_t telldir(DIR *dir) {
-    return dir->telldir();
-}
-
-extern "C" void seekdir(DIR *dir, off_t off) {
-    dir->seekdir(off);
-}
-
-extern "C" int mkdir(const char *path, mode_t mode) {
-    FilePath fp(path);
-    FileSystemLike *fs = fp.fileSystem();
-    if (fs == NULL) return -1;
-
-    return fs->mkdir(fp.fileName(), mode);
-}
-
-#if defined(TOOLCHAIN_GCC)
-/* prevents the exception handling name demangling code getting pulled in */
-#include "mbed_error.h"
-namespace __gnu_cxx {
-    void __verbose_terminate_handler() {
-        error("Exception");
-    }
-}
-extern "C" WEAK void __cxa_pure_virtual(void);
-extern "C" WEAK void __cxa_pure_virtual(void) {
-    exit(1);
-}
-
-#endif
-
-// ****************************************************************************
-// mbed_main is a function that is called before main()
-// mbed_sdk_init() is also a function that is called before main(), but unlike
-// mbed_main(), it is not meant for user code, but for the SDK itself to perform
-// initializations before main() is called.
-
-extern "C" WEAK void mbed_main(void);
-extern "C" WEAK void mbed_main(void) {
-}
-
-extern "C" WEAK void mbed_sdk_init(void);
-extern "C" WEAK void mbed_sdk_init(void) {
-}
-
-#if defined(TOOLCHAIN_ARM)
-extern "C" int $Super$$main(void);
-
-extern "C" int $Sub$$main(void) {
-    mbed_sdk_init();
-    mbed_main();
-    return $Super$$main();
-}
-#elif defined(TOOLCHAIN_GCC)
-extern "C" int __real_main(void);
-
-extern "C" int __wrap_main(void) {
-    mbed_sdk_init();
-    mbed_main();
-    return __real_main();
-}
-#elif defined(TOOLCHAIN_IAR)
-// IAR doesn't have the $Super/$Sub mechanism of armcc, nor something equivalent
-// to ld's --wrap. It does have a --redirect, but that doesn't help, since redirecting
-// 'main' to another symbol looses the original 'main' symbol. However, its startup
-// code will call a function to setup argc and argv (__iar_argc_argv) if it is defined.
-// Since mbed doesn't use argc/argv, we use this function to call our mbed_main.
-extern "C" void __iar_argc_argv() {
-    mbed_sdk_init();
-    mbed_main();
-}
-#endif
-
-// Provide implementation of _sbrk (low-level dynamic memory allocation
-// routine) for GCC_ARM which compares new heap pointer with MSP instead of
-// SP.  This make it compatible with RTX RTOS thread stacks.
-#if defined(TOOLCHAIN_GCC_ARM)
-// Linker defined symbol used by _sbrk to indicate where heap should start.
-extern "C" int __end__;
-
-#if defined(TARGET_CORTEX_A)
-extern "C" uint32_t  __HeapLimit;
-#endif
-
-// Turn off the errno macro and use actual global variable instead.
-#undef errno
-extern "C" int errno;
-
-// For ARM7 only
-register unsigned char * stack_ptr __asm ("sp");
-
-// Dynamic memory allocation related syscall.
-extern "C" caddr_t _sbrk(int incr) {
-    static unsigned char* heap = (unsigned char*)&__end__;
-    unsigned char*        prev_heap = heap;
-    unsigned char*        new_heap = heap + incr;
-
-#if defined(TARGET_ARM7)
-    if (new_heap >= stack_ptr) {
-#elif defined(TARGET_CORTEX_A)
-    if (new_heap >= (unsigned char*)&__HeapLimit) {     /* __HeapLimit is end of heap section */
-#else
-    if (new_heap >= (unsigned char*)__get_MSP()) {
-#endif
-        errno = ENOMEM;
-        return (caddr_t)-1;
-    }
-
-    heap = new_heap;
-    return (caddr_t) prev_heap;
-}
-#endif
-
-
-#ifdef TOOLCHAIN_GCC_CW
-// TODO: Ideally, we would like to define directly "_ExitProcess"
-extern "C" void mbed_exit(int return_code) {
-#elif defined TOOLCHAIN_GCC_ARM
-extern "C" void _exit(int return_code) {
-#else
-namespace std {
-extern "C" void exit(int return_code) {
-#endif
-
-#if DEVICE_STDIO_MESSAGES
-    fflush(stdout);
-    fflush(stderr);
-#endif
-
-#if DEVICE_SEMIHOST
-    if (mbed_interface_connected()) {
-        semihost_exit();
-    }
-#endif
-    if (return_code) {
-        mbed_die();
-    }
-
-    while (1);
-}
-
-#if !defined(TOOLCHAIN_GCC_ARM) && !defined(TOOLCHAIN_GCC_CW)
-} //namespace std
-#endif
-
-
-namespace mbed {
-
-void mbed_set_unbuffered_stream(FILE *_file) {
-#if defined (__ICCARM__)
-    char buf[2];
-    std::setvbuf(_file,buf,_IONBF,NULL);    
-#else
-    setbuf(_file, NULL);
-#endif
-}
-
-int mbed_getc(FILE *_file){
-#if defined (__ICCARM__)
-    /*This is only valid for unbuffered streams*/
-    int res = std::fgetc(_file);
-    if (res>=0){
-        _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
-        _file->_Rend = _file->_Wend;
-        _file->_Next = _file->_Wend;
-    }    
-    return res;
-#else    
-    return std::fgetc(_file);
-#endif   
-}
-
-char* mbed_gets(char*s, int size, FILE *_file){
-#if defined (__ICCARM__)
-    /*This is only valid for unbuffered streams*/
-    char *str = fgets(s,size,_file);
-    if (str!=NULL){
-        _file->_Mode = (unsigned short)(_file->_Mode & ~ 0x1000);/* Unset read mode */
-        _file->_Rend = _file->_Wend;
-        _file->_Next = _file->_Wend;
-    }
-    return str;
-#else    
-    return std::fgets(s,size,_file);
-#endif
-}
-
-} // namespace mbed

--- a/common/rtc_time.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,89 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "rtc_api.h"
-
-#include <time.h>
-#include "rtc_time.h"
-#include "us_ticker_api.h"
-
-#if DEVICE_RTC
-static void (*_rtc_init)(void) = rtc_init;
-static int (*_rtc_isenabled)(void) = rtc_isenabled;
-static time_t (*_rtc_read)(void) = rtc_read;
-static void (*_rtc_write)(time_t t) = rtc_write;
-#else
-static void (*_rtc_init)(void) = NULL;
-static int (*_rtc_isenabled)(void) = NULL;
-static time_t (*_rtc_read)(void) = NULL;
-static void (*_rtc_write)(time_t t) = NULL;
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#if defined (__ICCARM__)
-time_t __time32(time_t *timer)
-#else
-time_t time(time_t *timer)
-#endif
-
-{
-    if (_rtc_isenabled != NULL) {
-        if (!(_rtc_isenabled())) {
-            set_time(0);
-        }
-    }
-    
-    time_t t = 0;
-    if (_rtc_read != NULL) {
-        t = _rtc_read();
-    }
-
-    if (timer != NULL) {
-        *timer = t;
-    }
-    return t;
-}
-
-void set_time(time_t t) {
-    if (_rtc_init != NULL) {
-        _rtc_init();
-    }
-    if (_rtc_write != NULL) {
-        _rtc_write(t);
-    }
-}
-
-clock_t clock() {
-    clock_t t = us_ticker_read();
-    t /= 1000000 / CLOCKS_PER_SEC; // convert to processor time
-    return t;
-}
-
-void attach_rtc(time_t (*read_rtc)(void), void (*write_rtc)(time_t), void (*init_rtc)(void), int (*isenabled_rtc)(void)) {
-    __disable_irq();
-    _rtc_read = read_rtc;
-    _rtc_write = write_rtc;
-    _rtc_init = init_rtc;
-    _rtc_isenabled = isenabled_rtc;
-    __enable_irq();
-}
-
-
-
-#ifdef __cplusplus
-}
-#endif

--- a/common/semihost_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,162 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "cmsis.h"
-#include "semihost_api.h"
-
-#include <stdint.h>
-#include <string.h>
-
-#if DEVICE_SEMIHOST
-
-// ARM Semihosting Commands
-#define SYS_OPEN   (0x1)
-#define SYS_CLOSE  (0x2)
-#define SYS_WRITE  (0x5)
-#define SYS_READ   (0x6)
-#define SYS_ISTTY  (0x9)
-#define SYS_SEEK   (0xa)
-#define SYS_ENSURE (0xb)
-#define SYS_FLEN   (0xc)
-#define SYS_REMOVE (0xe)
-#define SYS_RENAME (0xf)
-#define SYS_EXIT   (0x18)
-
-// mbed Semihosting Commands
-#define RESERVED_FOR_USER_APPLICATIONS (0x100) // 0x100 - 0x1ff
-#define USR_XFFIND      (RESERVED_FOR_USER_APPLICATIONS + 0)
-#define USR_UID      (RESERVED_FOR_USER_APPLICATIONS + 1)
-#define USR_RESET     (RESERVED_FOR_USER_APPLICATIONS + 2)
-#define USR_VBUS     (RESERVED_FOR_USER_APPLICATIONS + 3)
-#define USR_POWERDOWN     (RESERVED_FOR_USER_APPLICATIONS + 4)
-#define USR_DISABLEDEBUG (RESERVED_FOR_USER_APPLICATIONS + 5)
-
-#if DEVICE_LOCALFILESYSTEM
-FILEHANDLE semihost_open(const char* name, int openmode) {
-    uint32_t args[3];
-    args[0] = (uint32_t)name;
-    args[1] = (uint32_t)openmode;
-    args[2] = (uint32_t)strlen(name);
-    return __semihost(SYS_OPEN, args);
-}
-
-int semihost_close(FILEHANDLE fh) {
-    return __semihost(SYS_CLOSE, &fh);
-}
-
-int semihost_write(FILEHANDLE fh, const unsigned char* buffer, unsigned int length, int mode) {
-    if (length == 0) return 0;
-
-    uint32_t args[3];
-    args[0] = (uint32_t)fh;
-    args[1] = (uint32_t)buffer;
-    args[2] = (uint32_t)length;
-    return __semihost(SYS_WRITE, args);
-}
-
-int semihost_read(FILEHANDLE fh, unsigned char* buffer, unsigned int length, int mode) {
-    uint32_t args[3];
-    args[0] = (uint32_t)fh;
-    args[1] = (uint32_t)buffer;
-    args[2] = (uint32_t)length;
-    return __semihost(SYS_READ, args);
-}
-
-int semihost_istty(FILEHANDLE fh) {
-    return __semihost(SYS_ISTTY, &fh);
-}
-
-int semihost_seek(FILEHANDLE fh, long position) {
-    uint32_t args[2];
-    args[0] = (uint32_t)fh;
-    args[1] = (uint32_t)position;
-    return __semihost(SYS_SEEK, args);
-}
-
-int semihost_ensure(FILEHANDLE fh) {
-    return __semihost(SYS_ENSURE, &fh);
-}
-
-long semihost_flen(FILEHANDLE fh) {
-    return __semihost(SYS_FLEN, &fh);
-}
-
-int semihost_remove(const char *name) {
-    uint32_t args[2];
-    args[0] = (uint32_t)name;
-    args[1] = (uint32_t)strlen(name);
-    return __semihost(SYS_REMOVE, args);
-}
-
-int semihost_rename(const char *old_name, const char *new_name) {
-    uint32_t args[4];
-    args[0] = (uint32_t)old_name;
-    args[1] = (uint32_t)strlen(old_name);
-    args[0] = (uint32_t)new_name;
-    args[1] = (uint32_t)strlen(new_name);
-    return __semihost(SYS_RENAME, args);
-}
-#endif
-
-int semihost_exit(void) {
-    uint32_t args[4];
-    return __semihost(SYS_EXIT, args);
-}
-
-int semihost_uid(char *uid) {
-    uint32_t args[2];
-    args[0] = (uint32_t)uid;
-    args[1] = DEVICE_ID_LENGTH + 1;
-    return __semihost(USR_UID, &args);
-}
-
-int semihost_reset(void) {
-    // Does not normally return, however if used with older firmware versions
-    // that do not support this call it will return -1.
-    return __semihost(USR_RESET, NULL);
-}
-
-int semihost_vbus(void) {
-    return __semihost(USR_VBUS, NULL);
-}
-
-int semihost_powerdown(void) {
-    return __semihost(USR_POWERDOWN, NULL);
-}
-
-#if DEVICE_DEBUG_AWARENESS
-
-int semihost_connected(void) {
-    return (CoreDebug->DHCSR & CoreDebug_DHCSR_C_DEBUGEN_Msk) ? 1 : 0;
-}
-
-#else
-// These processors cannot know if the interface is connect, assume so:
-static int is_debugger_attached = 1;
-
-int semihost_connected(void) {
-    return is_debugger_attached;
-}
-#endif
-
-int semihost_disabledebug(void) {
-#if !(DEVICE_DEBUG_AWARENESS)
-    is_debugger_attached = 0;
-#endif
-    return __semihost(USR_DISABLEDEBUG, NULL);
-}
-
-#endif
-

--- a/common/ticker_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,135 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include <stddef.h>
-#include "ticker_api.h"
-#include "cmsis.h"
-
-void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler) {
-    data->interface->init();
-
-    data->queue->event_handler = handler;
-}
-
-void ticker_irq_handler(const ticker_data_t *const data) {
-    data->interface->clear_interrupt();
-
-    /* Go through all the pending TimerEvents */
-    while (1) {
-        if (data->queue->head == NULL) {
-            // There are no more TimerEvents left, so disable matches.
-            data->interface->disable_interrupt();
-            return;
-        }
-
-        if ((int)(data->queue->head->timestamp - data->interface->read()) <= 0) {
-            // This event was in the past:
-            //      point to the following one and execute its handler
-            ticker_event_t *p = data->queue->head;
-            data->queue->head = data->queue->head->next;
-            if (data->queue->event_handler != NULL) {
-                (*data->queue->event_handler)(p->id); // NOTE: the handler can set new events
-            }
-            /* Note: We continue back to examining the head because calling the
-             * event handler may have altered the chain of pending events. */
-        } else {
-            // This event and the following ones in the list are in the future:
-            //      set it as next interrupt and return
-            data->interface->set_interrupt(data->queue->head->timestamp);
-            return;
-        }
-    }
-}
-
-void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id) {
-    /* disable interrupts for the duration of the function */
-    __disable_irq();
-
-    // initialise our data
-    obj->timestamp = timestamp;
-    obj->id = id;
-
-    /* Go through the list until we either reach the end, or find
-       an element this should come before (which is possibly the
-       head). */
-    ticker_event_t *prev = NULL, *p = data->queue->head;
-    while (p != NULL) {
-        /* check if we come before p */
-        if ((int)(timestamp - p->timestamp) < 0) {
-            break;
-        }
-        /* go to the next element */
-        prev = p;
-        p = p->next;
-    }
-    /* if prev is NULL we're at the head */
-    if (prev == NULL) {
-        data->queue->head = obj;
-        data->interface->set_interrupt(timestamp);
-    } else {
-        prev->next = obj;
-    }
-    /* if we're at the end p will be NULL, which is correct */
-    obj->next = p;
-
-    __enable_irq();
-}
-
-void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj) {
-    __disable_irq();
-
-    // remove this object from the list
-    if (data->queue->head == obj) {
-        // first in the list, so just drop me
-        data->queue->head = obj->next;
-        if (data->queue->head == NULL) {
-            data->interface->disable_interrupt();
-        } else {
-            data->interface->set_interrupt(data->queue->head->timestamp);
-        }
-    } else {
-        // find the object before me, then drop me
-        ticker_event_t* p = data->queue->head;
-        while (p != NULL) {
-            if (p->next == obj) {
-                p->next = obj->next;
-                break;
-            }
-            p = p->next;
-        }
-    }
-
-    __enable_irq();
-}
-
-timestamp_t ticker_read(const ticker_data_t *const data)
-{
-    return data->interface->read();
-}
-
-int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp)
-{
-    int ret = 0;
-
-    /* if head is NULL, there are no pending events */
-    __disable_irq();
-    if (data->queue->head != NULL) {
-        *timestamp = data->queue->head->timestamp;
-        ret = 1;
-    }
-    __enable_irq();
-
-    return ret;
-}

--- a/common/us_ticker_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,41 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "us_ticker_api.h"
-
-static ticker_event_queue_t events;
-
-static const ticker_interface_t us_interface = {
-    .init = us_ticker_init,
-    .read = us_ticker_read,
-    .disable_interrupt = us_ticker_disable_interrupt,
-    .clear_interrupt = us_ticker_clear_interrupt,
-    .set_interrupt = us_ticker_set_interrupt,
-};
-
-static const ticker_data_t us_data = {
-    .interface = &us_interface,
-    .queue = &events,
-};
-
-const ticker_data_t* get_us_ticker_data(void)
-{
-    return &us_data;
-}
-
-void us_ticker_irq_handler(void)
-{
-    ticker_irq_handler(&us_data);
-}

--- a/common/wait_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "wait_api.h"
-#include "us_ticker_api.h"
-
-void wait(float s) {
-    wait_us(s * 1000000.0f);
-}
-
-void wait_ms(int ms) {
-    wait_us(ms * 1000);
-}
-
-void wait_us(int us) {
-    uint32_t start = us_ticker_read();
-    while ((us_ticker_read() - start) < (uint32_t)us);
-}

--- a/hal/analogin_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,39 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGIN_API_H
-#define MBED_ANALOGIN_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct analogin_s analogin_t;
-
-void     analogin_init    (analogin_t *obj, PinName pin);
-float    analogin_read    (analogin_t *obj);
-uint16_t analogin_read_u16(analogin_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/analogout_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ANALOGOUT_API_H
-#define MBED_ANALOGOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_ANALOGOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct dac_s dac_t;
-
-void     analogout_init     (dac_t *obj, PinName pin);
-void     analogout_free     (dac_t *obj);
-void     analogout_write    (dac_t *obj, float value);
-void     analogout_write_u16(dac_t *obj, uint16_t value);
-float    analogout_read     (dac_t *obj);
-uint16_t analogout_read_u16 (dac_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/buffer.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2014-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_BUFFER_H
-#define MBED_BUFFER_H
-
-#include <stddef.h>
-
-/** Generic buffer structure
- */
-typedef struct buffer_s {
-    void    *buffer; /**< the pointer to a buffer */
-    size_t   length; /**< the buffer length */
-    size_t   pos;    /**< actual buffer position */
-    uint8_t  width;  /**< The buffer unit width (8, 16, 32, 64), used for proper *buffer casting */
-} buffer_t;
-
-#endif

--- a/hal/can_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,80 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_CAN_API_H
-#define MBED_CAN_API_H
-
-#include "device.h"
-
-#if DEVICE_CAN
-
-#include "PinNames.h"
-#include "PeripheralNames.h"
-#include "can_helper.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    IRQ_RX,
-    IRQ_TX,
-    IRQ_ERROR,
-    IRQ_OVERRUN,
-    IRQ_WAKEUP,
-    IRQ_PASSIVE,
-    IRQ_ARB,
-    IRQ_BUS,
-    IRQ_READY
-} CanIrqType;
-
-
-typedef enum {
-    MODE_RESET,
-    MODE_NORMAL,
-    MODE_SILENT,
-    MODE_TEST_LOCAL,
-    MODE_TEST_GLOBAL,
-    MODE_TEST_SILENT
-} CanMode;
-
-typedef void (*can_irq_handler)(uint32_t id, CanIrqType type);
-
-typedef struct can_s can_t;
-
-void          can_init     (can_t *obj, PinName rd, PinName td);
-void          can_free     (can_t *obj);
-int           can_frequency(can_t *obj, int hz);
-
-void          can_irq_init (can_t *obj, can_irq_handler handler, uint32_t id);
-void          can_irq_free (can_t *obj);
-void          can_irq_set  (can_t *obj, CanIrqType irq, uint32_t enable);
-
-int           can_write    (can_t *obj, CAN_Message, int cc);
-int           can_read     (can_t *obj, CAN_Message *msg, int handle);
-int           can_mode     (can_t *obj, CanMode mode);
-int           can_filter(can_t *obj, uint32_t id, uint32_t mask, CANFormat format, int32_t handle);
-void          can_reset    (can_t *obj);
-unsigned char can_rderror  (can_t *obj);
-unsigned char can_tderror  (can_t *obj);
-void          can_monitor  (can_t *obj, int silent);
-
-#ifdef __cplusplus
-};
-#endif
-
-#endif    // MBED_CAN_API_H
-
-#endif

--- a/hal/dma_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2014-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_DMA_API_H
-#define MBED_DMA_API_H
-
-#include <stdint.h>
-
-#define DMA_ERROR_OUT_OF_CHANNELS (-1)
-
-typedef enum {
-    DMA_USAGE_NEVER,
-    DMA_USAGE_OPPORTUNISTIC,
-    DMA_USAGE_ALWAYS,
-    DMA_USAGE_TEMPORARY_ALLOCATED,
-    DMA_USAGE_ALLOCATED
-} DMAUsage;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void dma_init(void);
-
-int dma_channel_allocate(uint32_t capabilities);
-
-int dma_channel_free(int channelid);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/hal/ethernet_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_ETHERNET_API_H
-#define MBED_ETHERNET_API_H
-
-#include "device.h"
-
-#if DEVICE_ETHERNET
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// Connection constants
-
-int ethernet_init(void);
-void ethernet_free(void);
-
-// write size bytes from data to ethernet buffer
-// return num bytes written
-// or -1 if size is too big
-int ethernet_write(const char *data, int size);
-
-// send ethernet write buffer, returning the packet size sent
-int ethernet_send(void);
-
-// recieve from ethernet buffer, returning packet size, or 0 if no packet
-int ethernet_receive(void);
-
-// read size bytes in to data, return actual num bytes read (0..size)
-// if data == NULL, throw the bytes away
-int ethernet_read(char *data, int size);
-
-// get the ethernet address
-void ethernet_address(char *mac);
-
-// see if the link is up
-int ethernet_link(void);
-
-// force link settings
-void ethernet_set_link(int speed, int duplex);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif
-

--- a/hal/gpio_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,57 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_API_H
-#define MBED_GPIO_API_H
-
-#include "device.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/* Set the given pin as GPIO
- * @param pin The pin to be set as GPIO
- * @return The GPIO port mask for this pin
- **/
-uint32_t gpio_set(PinName pin);
-
-/* Checks if gpio object is connected (pin was not initialized with NC)
- * @param pin The pin to be set as GPIO
- * @return 0 if port is initialized with NC
- **/
-int gpio_is_connected(const gpio_t *obj);
-
-/* GPIO object */
-void gpio_init(gpio_t *obj, PinName pin);
-
-void gpio_mode (gpio_t *obj, PinMode mode);
-void gpio_dir  (gpio_t *obj, PinDirection direction);
-
-void gpio_write(gpio_t *obj, int value);
-int  gpio_read (gpio_t *obj);
-
-// the following set of functions are generic and are implemented in the common gpio.c file
-void gpio_init_in(gpio_t* gpio, PinName pin);
-void gpio_init_in_ex(gpio_t* gpio, PinName pin, PinMode mode);
-void gpio_init_out(gpio_t* gpio, PinName pin);
-void gpio_init_out_ex(gpio_t* gpio, PinName pin, int value);
-void gpio_init_inout(gpio_t* gpio, PinName pin, PinDirection direction, PinMode mode, int value);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/hal/gpio_irq_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_GPIO_IRQ_API_H
-#define MBED_GPIO_IRQ_API_H
-
-#include "device.h"
-
-#if DEVICE_INTERRUPTIN
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    IRQ_NONE,
-    IRQ_RISE,
-    IRQ_FALL
-} gpio_irq_event;
-
-typedef struct gpio_irq_s gpio_irq_t;
-
-typedef void (*gpio_irq_handler)(uint32_t id, gpio_irq_event event);
-
-int  gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id);
-void gpio_irq_free(gpio_irq_t *obj);
-void gpio_irq_set (gpio_irq_t *obj, gpio_irq_event event, uint32_t enable);
-void gpio_irq_enable(gpio_irq_t *obj);
-void gpio_irq_disable(gpio_irq_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/i2c_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,223 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_I2C_API_H
-#define MBED_I2C_API_H
-
-#include "device.h"
-#include "buffer.h"
-
-#if DEVICE_I2C
-
-/**
- * @defgroup I2CEvents I2C Events Macros
- *
- * @{
- */
-#define I2C_EVENT_ERROR               (1 << 1)
-#define I2C_EVENT_ERROR_NO_SLAVE      (1 << 2)
-#define I2C_EVENT_TRANSFER_COMPLETE   (1 << 3)
-#define I2C_EVENT_TRANSFER_EARLY_NACK (1 << 4)
-#define I2C_EVENT_ALL                 (I2C_EVENT_ERROR |  I2C_EVENT_TRANSFER_COMPLETE | I2C_EVENT_ERROR_NO_SLAVE | I2C_EVENT_TRANSFER_EARLY_NACK)
-
-/**@}*/
-
-#if DEVICE_I2C_ASYNCH
-/** Asynch i2c hal structure
- */
-typedef struct {
-    struct i2c_s    i2c;     /**< Target specific i2c structure */
-    struct buffer_s tx_buff; /**< Tx buffer */
-    struct buffer_s rx_buff; /**< Rx buffer */
-} i2c_t;
-
-#else
-/** Non-asynch i2c hal structure
- */
-typedef struct i2c_s i2c_t;
-
-#endif
-
-enum {
-  I2C_ERROR_NO_SLAVE = -1,
-  I2C_ERROR_BUS_BUSY = -2
-};
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup GeneralI2C I2C Configuration Functions
- * @{
- */
-
-/** Initialize the I2C peripheral. It sets the default parameters for I2C
- *  peripheral, and configure its specifieds pins.
- *  @param obj  The i2c object
- *  @param sda  The sda pin
- *  @param scl  The scl pin
- */
-void i2c_init(i2c_t *obj, PinName sda, PinName scl);
-
-/** Configure the I2C frequency.
- *  @param obj The i2c object
- *  @param hz  Frequency in Hz
- */
-void i2c_frequency(i2c_t *obj, int hz);
-
-/** Send START command.
- *  @param obj The i2c object
- */
-int  i2c_start(i2c_t *obj);
-
-/** Send STOP command.
- *  @param obj The i2c object
- */
-int  i2c_stop(i2c_t *obj);
-
-/** Blocking reading data.
- *  @param obj     The i2c object
- *  @param address 7-bit address (last bit is 1)
- *  @param data    The buffer for receiving
- *  @param length  Number of bytes to read
- *  @param stop    Stop to be generated after the transfer is done
- *  @return Number of read bytes
- */
-int  i2c_read(i2c_t *obj, int address, char *data, int length, int stop);
-
-/** Blocking sending data.
- *  @param obj     The i2c object
- *  @param address 7-bit address (last bit is 0)
- *  @param data    The buffer for sending
- *  @param length  Number of bytes to wrte
- *  @param stop    Stop to be generated after the transfer is done
- *  @return Number of written bytes
- */
-int  i2c_write(i2c_t *obj, int address, const char *data, int length, int stop);
-
-/** Reset I2C peripheral. TODO: The action here. Most of the implementation sends stop().
- *  @param obj The i2c object
- */
-void i2c_reset(i2c_t *obj);
-
-/** Read one byte.
- *  @param obj The i2c object
- *  @param last Acknoledge
- *  @return The read byte
- */
-int  i2c_byte_read(i2c_t *obj, int last);
-
-/** Write one byte.
- *  @param obj The i2c object
- *  @param data Byte to be written
- *  @return 1 if NAK was received, 0 if ACK was received, 2 for timeout.
- */
-int  i2c_byte_write(i2c_t *obj, int data);
-
-/**@}*/
-
-#if DEVICE_I2CSLAVE
-
-/**
- * \defgroup SynchI2C Synchronous I2C Hardware Abstraction Layer for slave
- * @{
- */
-
-/** Configure I2C as slave or master.
- *  @param obj The I2C object
- *  @return non-zero if a value is available
- */
-void i2c_slave_mode(i2c_t *obj, int enable_slave);
-
-/** Check to see if the I2C slave has been addressed.
- *  @param obj The I2C object
- *  @return The status - 1 - read addresses, 2 - write to all slaves,
- *         3 write addressed, 0 - the slave has not been addressed
- */
-int  i2c_slave_receive(i2c_t *obj);
-
-/** Configure I2C as slave or master.
- *  @param obj The I2C object
- *  @return non-zero if a value is available
- */
-int  i2c_slave_read(i2c_t *obj, char *data, int length);
-
-/** Configure I2C as slave or master.
- *  @param obj The I2C object
- *  @return non-zero if a value is available
- */
-int  i2c_slave_write(i2c_t *obj, const char *data, int length);
-
-/** Configure I2C address.
- *  @param obj     The I2C object
- *  @param idx     Currently not used
- *  @param address The address to be set
- *  @param mask    Currently not used
- */
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask);
-
-#endif
-
-/**@}*/
-
-#if DEVICE_I2C_ASYNCH
-
-/**
- * \defgroup AsynchI2C Asynchronous I2C Hardware Abstraction Layer
- * @{
- */
-
-/** Start i2c asynchronous transfer.
- *  @param obj       The I2C object
- *  @param tx        The buffer to send
- *  @param tx_length The number of words to transmit
- *  @param rx        The buffer to receive
- *  @param rx_length The number of words to receive
- *  @param address   The address to be set - 7bit or 9 bit
- *  @param stop      If true, stop will be generated after the transfer is done
- *  @param handler   The I2C IRQ handler to be set
- *  @param hint      DMA hint usage
- */
-void i2c_transfer_asynch(i2c_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint32_t address, uint32_t stop, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** The asynchronous IRQ handler
- *  @param obj The I2C object which holds the transfer information
- *  @return event flags if a transfer termination condition was met or 0 otherwise.
- */
-uint32_t i2c_irq_handler_asynch(i2c_t *obj);
-
-/** Attempts to determine if I2C peripheral is already in use.
- *  @param obj The I2C object
- *  @return non-zero if the I2C module is active or zero if it is not
- */
-uint8_t i2c_active(i2c_t *obj);
-
-/** Abort ongoing asynchronous transaction.
- *  @param obj The I2C object
- */
-void i2c_abort_asynch(i2c_t *obj);
-
-#endif
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/lp_ticker_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,82 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_LPTICKER_API_H
-#define MBED_LPTICKER_API_H
-
-#include "device.h"
-
-#if DEVICE_LOWPOWERTIMER
-
-#include "ticker_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup LpTicker Low Power Ticker Functions
- * @{
- */
-
-/** Get low power ticker's data
- *
- * @return The low power ticker data
- */
-const ticker_data_t* get_lp_ticker_data(void);
-
-/** The wrapper for ticker_irq_handler, to pass lp ticker's data
- *
- */
-void lp_ticker_irq_handler(void);
-
-/* HAL lp ticker */
-
-/** Initialize the low power ticker
- *
- */
-void lp_ticker_init(void);
-
-/** Read the current counter
- *
- * @return The current timer's counter value in microseconds
- */
-uint32_t lp_ticker_read(void);
-
-/** Set interrupt for specified timestamp
- *
- * @param timestamp The time in microseconds to be set
- */
-void lp_ticker_set_interrupt(timestamp_t timestamp);
-
-/** Disable low power ticker interrupt
- *
- */
-void lp_ticker_disable_interrupt(void);
-
-/** Clear the low power ticker interrupt
- *
- */
-void lp_ticker_clear_interrupt(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/pinmap.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PINMAP_H
-#define MBED_PINMAP_H
-
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName pin;
-    int peripheral;
-    int function;
-} PinMap;
-
-void pin_function(PinName pin, int function);
-void pin_mode    (PinName pin, PinMode mode);
-
-uint32_t pinmap_peripheral(PinName pin, const PinMap* map);
-uint32_t pinmap_function(PinName pin, const PinMap* map);
-uint32_t pinmap_merge     (uint32_t a, uint32_t b);
-void     pinmap_pinout    (PinName pin, const PinMap *map);
-uint32_t pinmap_find_peripheral(PinName pin, const PinMap* map);
-uint32_t pinmap_find_function(PinName pin, const PinMap* map);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/hal/port_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PORTMAP_H
-#define MBED_PORTMAP_H
-
-#include "device.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct port_s port_t;
-
-PinName port_pin(PortName port, int pin_n);
-
-void port_init (port_t *obj, PortName port, int mask, PinDirection dir);
-void port_mode (port_t *obj, PinMode mode);
-void port_dir  (port_t *obj, PinDirection dir);
-void port_write(port_t *obj, int value);
-int  port_read (port_t *obj);
-
-#ifdef __cplusplus
-}
-#endif
-#endif
-
-#endif

--- a/hal/pwmout_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,49 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_PWMOUT_API_H
-#define MBED_PWMOUT_API_H
-
-#include "device.h"
-
-#if DEVICE_PWMOUT
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct pwmout_s pwmout_t;
-
-void pwmout_init         (pwmout_t* obj, PinName pin);
-void pwmout_free         (pwmout_t* obj);
-
-void  pwmout_write       (pwmout_t* obj, float percent);
-float pwmout_read        (pwmout_t* obj);
-
-void pwmout_period       (pwmout_t* obj, float seconds);
-void pwmout_period_ms    (pwmout_t* obj, int ms);
-void pwmout_period_us    (pwmout_t* obj, int us);
-
-void pwmout_pulsewidth   (pwmout_t* obj, float seconds);
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms);
-void pwmout_pulsewidth_us(pwmout_t* obj, int us);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/rtc_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,42 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_RTC_API_H
-#define MBED_RTC_API_H
-
-#include "device.h"
-
-#if DEVICE_RTC
-
-#include <time.h>
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void rtc_init(void);
-void rtc_free(void);
-int rtc_isenabled(void);
-
-time_t rtc_read(void);
-void rtc_write(time_t t);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/serial_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,302 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SERIAL_API_H
-#define MBED_SERIAL_API_H
-
-#include "device.h"
-#include "buffer.h"
-#include "dma_api.h"
-
-#if DEVICE_SERIAL
-
-#define SERIAL_EVENT_TX_SHIFT (2)
-#define SERIAL_EVENT_RX_SHIFT (8)
-
-#define SERIAL_EVENT_TX_MASK (0x00FC)
-#define SERIAL_EVENT_RX_MASK (0x3F00)
-
-#define SERIAL_EVENT_ERROR (1 << 1)
-
-/**
- * @defgroup SerialTXEvents Serial TX Events Macros
- *
- * @{
- */
-#define SERIAL_EVENT_TX_COMPLETE (1 << (SERIAL_EVENT_TX_SHIFT + 0))
-#define SERIAL_EVENT_TX_ALL      (SERIAL_EVENT_TX_COMPLETE)
-/**@}*/
-
-/**
- * @defgroup SerialRXEvents Serial RX Events Macros
- *
- * @{
- */
-#define SERIAL_EVENT_RX_COMPLETE        (1 << (SERIAL_EVENT_RX_SHIFT + 0))
-#define SERIAL_EVENT_RX_OVERRUN_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 1))
-#define SERIAL_EVENT_RX_FRAMING_ERROR   (1 << (SERIAL_EVENT_RX_SHIFT + 2))
-#define SERIAL_EVENT_RX_PARITY_ERROR    (1 << (SERIAL_EVENT_RX_SHIFT + 3))
-#define SERIAL_EVENT_RX_OVERFLOW        (1 << (SERIAL_EVENT_RX_SHIFT + 4))
-#define SERIAL_EVENT_RX_CHARACTER_MATCH (1 << (SERIAL_EVENT_RX_SHIFT + 5))
-#define SERIAL_EVENT_RX_ALL             (SERIAL_EVENT_RX_OVERFLOW | SERIAL_EVENT_RX_PARITY_ERROR | \
-                                         SERIAL_EVENT_RX_FRAMING_ERROR | SERIAL_EVENT_RX_OVERRUN_ERROR | \
-                                         SERIAL_EVENT_RX_COMPLETE | SERIAL_EVENT_RX_CHARACTER_MATCH)
-/**@}*/
-
-#define SERIAL_RESERVED_CHAR_MATCH (255)
-
-typedef enum {
-    ParityNone = 0,
-    ParityOdd = 1,
-    ParityEven = 2,
-    ParityForced1 = 3,
-    ParityForced0 = 4
-} SerialParity;
-
-typedef enum {
-    RxIrq,
-    TxIrq
-} SerialIrq;
-
-typedef enum {
-    FlowControlNone,
-    FlowControlRTS,
-    FlowControlCTS,
-    FlowControlRTSCTS
-} FlowControl;
-
-typedef void (*uart_irq_handler)(uint32_t id, SerialIrq event);
-
-#if DEVICE_SERIAL_ASYNCH
-/** Asynch serial hal structure
- */
-typedef struct {
-    struct serial_s serial;  /**< Target specific serial structure */
-    struct buffer_s tx_buff; /**< Tx buffer */
-    struct buffer_s rx_buff; /**< Rx buffer */
-    uint8_t char_match;      /**< Character to be matched */
-    uint8_t char_found;      /**< State of the matched character */
-} serial_t;
-
-#else
-/** Non-asynch serial hal structure
- */
-typedef struct serial_s serial_t;
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup GeneralSerial Serial Configuration Functions
- * @{
- */
-
-/** Initialize the serial peripheral. It sets the default parameters for serial
- *  peripheral, and configure its specifieds pins.
- *
- * @param obj The serial object
- * @param tx  The TX pin
- * @param rx  The RX pin
- */
-void serial_init(serial_t *obj, PinName tx, PinName rx);
-
-/** Release the serial peripheral, not currently invoked. It requires further
- *  resource management.
- *
- * @param obj The serial object
- */
-void serial_free(serial_t *obj);
-
-/** Configure the baud rate
- *
- * @param obj      The serial object
- * @param baudrate The baud rate to be configured
- */
-void serial_baud(serial_t *obj, int baudrate);
-
-/** Configure the format. Set the number of bits, parity and the number of stop bits
- *
- * @param obj       The serial object
- * @param data_bits The number of data bits
- * @param parity    The parity
- * @param stop_bits The number of stop bits
- */
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits);
-
-/** The serial interrupt handler registration.
- *
- * @param obj     The serial object
- * @param handler The interrupt handler which will be invoked when interrupt fires.
- * @param id      The SerialBase object
- */
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id);
-
-/** Configure serial interrupt. This function is used for word-approach
- *
- * @param obj    The serial object
- * @param irq    The serial IRQ type (RX or TX)
- * @param enable Set to non-zero to enable events, or zero to disable them
- */
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable);
-
-/** Get character. This is a blocking call, waiting for a character
- *
- * @param obj The serial object
- */
-int  serial_getc(serial_t *obj);
-
-/** Put a character. This is a blocking call, waiting for a peripheral to be available
- *  for writing
- *
- * @param obj The serial object
- * @param c   The character to be sent
- */
-void serial_putc(serial_t *obj, int c);
-
-/** Check if the serial peripheral is readable
- *
- * @param obj The serial object
- * @return Non-zero value if a character can be read, 0 if nothing to read.
- */
-int  serial_readable(serial_t *obj);
-
-/** Check if the serial peripheral is writable
- *
- * @param obj The serial object
- * @return Non-zero value if a character can be written, 0 otherwise.
- */
-int  serial_writable(serial_t *obj);
-
-/** Clear the serial peripheral
- *
- * @param obj The serial object
- */
-void serial_clear(serial_t *obj);
-
-/** Set the break
- *
- * @param obj The serial object
- */
-void serial_break_set(serial_t *obj);
-
-/** Clear the break
- *
- * @param obj The serial object
- */
-void serial_break_clear(serial_t *obj);
-
-/** Configure the TX pin for UART function.
- *
- * @param tx The pin used for TX
- */
-void serial_pinout_tx(PinName tx);
-
-/** Configure the serial for the flow control. It sets flow control in the hardware
- *  if a serial peripheral supports it, otherwise software emulation is used.
- *
- * @param obj    The serial object
- * @param type   The type of the flow control. Look at the available FlowControl types.
- * @param rxflow The tx pin
- * @param txflow The rx pin
- */
-void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow);
-
-#if DEVICE_SERIAL_ASYNCH
-
-/**@}*/
-
-/**
- * \defgroup AsynchSerial Asynchronous Serial Hardware Abstraction Layer
- * @{
- */
-
-/** Begin asynchronous TX transfer. The used buffer is specified in the serial object,
- *  tx_buff
- *
- * @param obj       The serial object
- * @param tx        The buffer for sending
- * @param tx_length The number of words to transmit
- * @param tx_width  The bit width of buffer word
- * @param handler   The serial handler
- * @param event     The logical OR of events to be registered
- * @param hint      A suggestion for how to use DMA with this transfer
- * @return Returns number of data transfered, or 0 otherwise
- */
-int serial_tx_asynch(serial_t *obj, const void *tx, size_t tx_length, uint8_t tx_width, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** Begin asynchronous RX transfer (enable interrupt for data collecting)
- *  The used buffer is specified in the serial object - rx_buff
- *
- * @param obj        The serial object
- * @param rx         The buffer for sending
- * @param rx_length  The number of words to transmit
- * @param rx_width   The bit width of buffer word
- * @param handler    The serial handler
- * @param event      The logical OR of events to be registered
- * @param handler    The serial handler
- * @param char_match A character in range 0-254 to be matched
- * @param hint       A suggestion for how to use DMA with this transfer
- */
-void serial_rx_asynch(serial_t *obj, void *rx, size_t rx_length, uint8_t rx_width, uint32_t handler, uint32_t event, uint8_t char_match, DMAUsage hint);
-
-/** Attempts to determine if the serial peripheral is already in use for TX
- *
- * @param obj The serial object
- * @return Non-zero if the RX transaction is ongoing, 0 otherwise
- */
-uint8_t serial_tx_active(serial_t *obj);
-
-/** Attempts to determine if the serial peripheral is already in use for RX
- *
- * @param obj The serial object
- * @return Non-zero if the RX transaction is ongoing, 0 otherwise
- */
-uint8_t serial_rx_active(serial_t *obj);
-
-/** The asynchronous TX and RX handler.
- *
- * @param obj The serial object
- * @return Returns event flags if a RX transfer termination condition was met or 0 otherwise
- */
-int serial_irq_handler_asynch(serial_t *obj);
-
-/** Abort the ongoing TX transaction. It disables the enabled interupt for TX and
- *  flush TX hardware buffer if TX FIFO is used
- *
- * @param obj The serial object
- */
-void serial_tx_abort_asynch(serial_t *obj);
-
-/** Abort the ongoing RX transaction It disables the enabled interrupt for RX and
- *  flush RX hardware buffer if RX FIFO is used
- *
- * @param obj The serial object
- */
-void serial_rx_abort_asynch(serial_t *obj);
-
-/**@}*/
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/sleep_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,64 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SLEEP_API_H
-#define MBED_SLEEP_API_H
-
-#include "device.h"
-
-#if DEVICE_SLEEP
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Send the microcontroller to sleep
- *
- * The processor is setup ready for sleep, and sent to sleep using __WFI(). In this mode, the
- * system clock to the core is stopped until a reset or an interrupt occurs. This eliminates
- * dynamic power used by the processor, memory systems and buses. The processor, peripheral and
- * memory state are maintained, and the peripherals continue to work and can generate interrupts.
- *
- * The processor can be woken up by any internal peripheral interrupt or external pin interrupt.
- *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-void sleep(void);
-
-/** Send the microcontroller to deep sleep
- *
- * This processor is setup ready for deep sleep, and sent to sleep using __WFI(). This mode
- * has the same sleep features as sleep plus it powers down peripherals and clocks. All state
- * is still maintained.
- *
- * The processor can only be woken up by an external interrupt on a pin or a watchdog timer.
- *
- * @note
- *  The mbed interface semihosting is disconnected as part of going to sleep, and can not be restored.
- * Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
- * able to access the LocalFileSystem
- */
-void deepsleep(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
-#endif

--- a/hal/spi_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,213 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2013 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_SPI_API_H
-#define MBED_SPI_API_H
-
-#include "device.h"
-#include "dma_api.h"
-#include "buffer.h"
-
-#if DEVICE_SPI
-
-#define SPI_EVENT_ERROR       (1 << 1)
-#define SPI_EVENT_COMPLETE    (1 << 2)
-#define SPI_EVENT_RX_OVERFLOW (1 << 3)
-#define SPI_EVENT_ALL         (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
-
-#define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // internal flag to report an event occurred
-
-#define SPI_FILL_WORD         (0xFFFF)
-
-#if DEVICE_SPI_ASYNCH
-/** Asynch spi hal structure
- */
-typedef struct {
-    struct spi_s spi;        /**< Target specific spi structure */
-    struct buffer_s tx_buff; /**< Tx buffer */
-    struct buffer_s rx_buff; /**< Rx buffer */
-} spi_t;
-
-#else
-/** Non-asynch spi hal structure
- */
-typedef struct spi_s spi_t;
-
-#endif
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup GeneralSPI SPI Configuration Functions
- * @{
- */
-
-/** Initialize the SPI peripheral
- *
- * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
- * @param[out] obj  The SPI object to initialize
- * @param[in]  mosi The pin to use for MOSI
- * @param[in]  miso The pin to use for MISO
- * @param[in]  sclk The pin to use for SCLK
- * @param[in]  ssel The pin to use for SSEL
- */
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
-
-/** Release a SPI object
- *
- * TODO: spi_free is currently unimplemented
- * This will require reference counting at the C++ level to be safe
- *
- * Return the pins owned by the SPI object to their reset state
- * Disable the SPI peripheral
- * Disable the SPI clock
- * @param[in] obj The SPI object to deinitialize
- */
-void spi_free(spi_t *obj);
-
-/** Configure the SPI format
- *
- * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode
- * @param[in,out] obj   The SPI object to configure
- * @param[in]     bits  The number of bits per frame
- * @param[in]     mode  The SPI mode (clock polarity, phase, and shift direction)
- * @param[in]     slave Zero for master mode or non-zero for slave mode
- */
-void spi_format(spi_t *obj, int bits, int mode, int slave);
-
-/** Set the SPI baud rate
- *
- * Actual frequency may differ from the desired frequency due to available dividers and bus clock
- * Configures the SPI peripheral's baud rate
- * @param[in,out] obj The SPI object to configure
- * @param[in]     hz  The baud rate in Hz
- */
-void spi_frequency(spi_t *obj, int hz);
-
-/**@}*/
-/**
- * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
- * @{
- */
-
-/** Write a byte out in master mode and receive a value
- *
- * @param[in] obj   The SPI peripheral to use for sending
- * @param[in] value The value to send
- * @return Returns the value received during send
- */
-int  spi_master_write(spi_t *obj, int value);
-
-/** Check if a value is available to read
- *
- * @param[in] obj The SPI peripheral to check
- * @return non-zero if a value is available
- */
-int  spi_slave_receive(spi_t *obj);
-
-/** Get a received value out of the SPI receive buffer in slave mode
- *
- * Blocks until a value is available
- * @param[in] obj The SPI peripheral to read
- * @return The value received
- */
-int  spi_slave_read(spi_t *obj);
-
-/** Write a value to the SPI peripheral in slave mode
- *
- * Blocks until the SPI peripheral can be written to
- * @param[in] obj   The SPI peripheral to write
- * @param[in] value The value to write
- */
-void spi_slave_write(spi_t *obj, int value);
-
-/** Checks if the specified SPI peripheral is in use
- *
- * @param[in] obj The SPI peripheral to check
- * @return non-zero if the peripheral is currently transmitting
- */
-int  spi_busy(spi_t *obj);
-
-/** Get the module number
- *
- * @param[in] obj The SPI peripheral to check
- * @return The module number
- */
-uint8_t spi_get_module(spi_t *obj);
-
-/**@}*/
-
-#if DEVICE_SPI_ASYNCH
-/**
- * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
- * @{
- */
-
-/** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
- *
- * @param[in] obj       The SPI object which holds the transfer information
- * @param[in] tx        The buffer to send
- * @param[in] tx_length The number of words to transmit
- * @param[in] rx        The buffer to receive
- * @param[in] rx_length The number of words to receive
- * @param[in] bit_width The bit width of buffer words
- * @param[in] event     The logical OR of events to be registered
- * @param[in] handler   SPI interrupt handler
- * @param[in] hint      A suggestion for how to use DMA with this transfer
- */
-void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
-
-/** The asynchronous IRQ handler
- *
- * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
- * conditions, such as buffer overflows or transfer complete.
- * @param[in] obj     The SPI object which holds the transfer information
- * @return event flags if a transfer termination condition was met or 0 otherwise.
- */
-uint32_t spi_irq_handler_asynch(spi_t *obj);
-
-/** Attempts to determine if the SPI peripheral is already in use.
- *
- * If a temporary DMA channel has been allocated, peripheral is in use.
- * If a permanent DMA channel has been allocated, check if the DMA channel is in use.  If not, proceed as though no DMA
- * channel were allocated.
- * If no DMA channel is allocated, check whether tx and rx buffers have been assigned.  For each assigned buffer, check
- * if the corresponding buffer position is less than the buffer length.  If buffers do not indicate activity, check if
- * there are any bytes in the FIFOs.
- * @param[in] obj The SPI object to check for activity
- * @return non-zero if the SPI port is active or zero if it is not.
- */
-uint8_t spi_active(spi_t *obj);
-
-/** Abort an SPI transfer
- *
- * @param obj The SPI peripheral to stop
- */
-void spi_abort_asynch(spi_t *obj);
-
-
-#endif
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif // __cplusplus
-
-#endif // SPI_DEVICE
-
-#endif // MBED_SPI_API_H

--- a/hal/ticker_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,108 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_TICKER_API_H
-#define MBED_TICKER_API_H
-
-#include "device.h"
-
-typedef uint32_t timestamp_t;
-
-/** Ticker's event structure
- */
-typedef struct ticker_event_s {
-    timestamp_t            timestamp; /**< Event's timestamp */
-    uint32_t               id;        /**< TimerEvent object */
-    struct ticker_event_s *next;      /**< Next event in the queue */
-} ticker_event_t;
-
-typedef void (*ticker_event_handler)(uint32_t id);
-
-/** Ticker's interface structure - required API for a ticker
- */
-typedef struct {
-    void (*init)(void);                           /**< Init function */
-    uint32_t (*read)(void);                       /**< Read function */
-    void (*disable_interrupt)(void);              /**< Disable interrupt function */
-    void (*clear_interrupt)(void);                /**< Clear interrupt function */
-    void (*set_interrupt)(timestamp_t timestamp); /**< Set interrupt function */
-} ticker_interface_t;
-
-/** Tickers events queue structure
- */
-typedef struct {
-    ticker_event_handler event_handler; /**< Event handler */
-    ticker_event_t *head;               /**< A pointer to head */
-} ticker_event_queue_t;
-
-/** Tickers data structure
- */
-typedef struct {
-    const ticker_interface_t *interface; /**< Ticker's interface */
-    ticker_event_queue_t *queue;         /**< Ticker's events queue */
-} ticker_data_t;
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/** Initialize a ticker and sets the event handler
- *
- * @param data    The ticker's data
- * @param handler A handler to be set
- */
-void ticker_set_handler(const ticker_data_t *const data, ticker_event_handler handler);
-
-/** Irq handler which goes through the events to trigger events in the past.
- *
- * @param data    The ticker's data
- */
-void ticker_irq_handler(const ticker_data_t *const data);
-
-/** Remove an event from the queue
- *
- * @param data The ticker's data
- * @param obj  The event's queue to be removed
- */
-void ticker_remove_event(const ticker_data_t *const data, ticker_event_t *obj);
-
-/** Insert an event from the queue
- *
- * @param data      The ticker's data
- * @param obj       The event's queue to be removed
- * @param timestamp The event's timestamp
- * @param id        The event object
- */
-void ticker_insert_event(const ticker_data_t *const data, ticker_event_t *obj, timestamp_t timestamp, uint32_t id);
-
-/** Read the current ticker's timestamp
- *
- * @param data The ticker's data
- * @return The current timestamp
- */
-timestamp_t ticker_read(const ticker_data_t *const data);
-
-/** Read the next event's timestamp
- *
- * @param data The ticker's data
- * @return 1 if timestamp is pending event, 0 if there's no event pending
- */
-int ticker_get_next_timestamp(const ticker_data_t *const data, timestamp_t *timestamp);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/hal/us_ticker_api.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,78 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2015 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- *     http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#ifndef MBED_US_TICKER_API_H
-#define MBED_US_TICKER_API_H
-
-#include <stdint.h>
-#include "ticker_api.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-/**
- * \defgroup UsTicker Microseconds Ticker Functions
- * @{
- */
-
-/** Get ticker's data
- *
- * @return The low power ticker data
- */
-const ticker_data_t* get_us_ticker_data(void);
-
-
-/** The wrapper for ticker_irq_handler, to pass us ticker's data
- *
- */
-void us_ticker_irq_handler(void);
-
-/* HAL us ticker */
-
-/** Initialize the ticker
- *
- */
-void us_ticker_init(void);
-
-/** Read the current counter
- *
- * @return The current timer's counter value in microseconds
- */
-uint32_t us_ticker_read(void);
-
-/** Set interrupt for specified timestamp
- *
- * @param timestamp The time in microseconds to be set
- */
-void us_ticker_set_interrupt(timestamp_t timestamp);
-
-/** Disable us ticker interrupt
- *
- */
-void us_ticker_disable_interrupt(void);
-
-/** Clear us ticker interrupt
- *
- */
-void us_ticker_clear_interrupt(void);
-
-/**@}*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM32L0/PeripheralPins.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,66 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#ifndef MBED_PERIPHERALPINS_H
+#define MBED_PERIPHERALPINS_H
+
+#include "pinmap.h"
+#include "PeripheralNames.h"
+
+//*** ADC ***
+
+extern const PinMap PinMap_ADC[];
+
+//*** DAC ***
+
+extern const PinMap PinMap_DAC[];
+
+//*** I2C ***
+
+extern const PinMap PinMap_I2C_SDA[];
+extern const PinMap PinMap_I2C_SCL[];
+
+//*** PWM ***
+
+extern const PinMap PinMap_PWM[];
+
+//*** SERIAL ***
+
+extern const PinMap PinMap_UART_TX[];
+extern const PinMap PinMap_UART_RX[];
+
+//*** SPI ***
+
+extern const PinMap PinMap_SPI_MOSI[];
+extern const PinMap PinMap_SPI_MISO[];
+extern const PinMap PinMap_SPI_SCLK[];
+extern const PinMap PinMap_SPI_SSEL[];
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralNames.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+    DAC_1 = (int)DAC_BASE
+} DACName;
+
+typedef enum {
+    UART_1   = (int)USART1_BASE,
+    UART_2   = (int)USART2_BASE,
+    LPUART_1 = (int)LPUART1_BASE
+} UARTName;
+
+#define STDIO_UART_TX  PA_2
+#define STDIO_UART_RX  PA_3
+#define STDIO_UART     UART_2
+
+typedef enum {
+    SPI_1 = (int)SPI1_BASE,
+    SPI_2 = (int)SPI2_BASE
+} SPIName;
+
+typedef enum {
+    I2C_1 = (int)I2C1_BASE,
+    I2C_2 = (int)I2C2_BASE
+} I2CName;
+
+typedef enum {
+    PWM_2  = (int)TIM2_BASE,
+    PWM_21 = (int)TIM21_BASE,
+    PWM_22 = (int)TIM22_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralPins.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,170 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+
+// =====
+// Note: Commented lines are alternative possibilities which are not used per default.
+//       If you change them, you will have also to modify the corresponding xxx_api.c file
+//       for pwmout, analogin, analogout, ...
+// =====
+
+//*** ADC ***
+
+const PinMap PinMap_ADC[] = {
+    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+    {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+    {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+    {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+    {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+    {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+    {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+    {NC,   NC,    0}
+};
+
+//*** DAC ***
+
+const PinMap PinMap_DAC[] = {
+    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // DAC_OUT
+    {NC,   NC,    0}
+};
+
+//*** I2C ***
+
+const PinMap PinMap_I2C_SDA[] = {
+    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
+    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_I2C_SCL[] = {
+    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
+    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
+    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
+    {NC,    NC,    0}
+};
+
+//*** PWM ***
+
+// TIM21 cannot be used because already used by the us_ticker
+const PinMap PinMap_PWM[] = {
+    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1
+    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
+//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
+//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
+//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
+//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4 - used by STDIO RX
+    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used also to drive the LED
+    {PA_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
+    {PA_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
+    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
+    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
+    {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
+    {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
+    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
+    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
+//  {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1
+//  {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2
+    {PC_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 1, 0)}, // TIM22_CH1
+    {PC_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 2, 0)}, // TIM22_CH2
+    {NC,    NC,     0}
+};
+
+//*** SERIAL ***
+
+const PinMap PinMap_UART_TX[] = {
+    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
+    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PC_4,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
+    {PC_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
+    {NC,    NC,       0}
+};
+
+const PinMap PinMap_UART_RX[] = {
+    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
+    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
+    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
+    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
+    {PC_5,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
+    {PC_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
+    {NC,    NC,      0}
+};
+
+//*** SPI ***
+
+const PinMap PinMap_SPI_MOSI[] = {
+    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_MISO[] = {
+    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SCLK[] = {
+    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {NC,    NC,    0}
+};
+
+const PinMap PinMap_SPI_SSEL[] = {
+    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
+    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
+    {NC,    NC,    0}
+};

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PinNames.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,194 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
+                                                ((PUPD  & 0x07) << 4) |\
+                                                ((AFNUM & 0x0F) << 7)))
+
+#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
+                                                                       ((PUPD     & 0x07) <<  4) |\
+                                                                       ((AFNUM    & 0x0F) <<  7) |\
+                                                                       ((CHANNEL  & 0x0F) << 11) |\
+                                                                       ((INVERTED & 0x01) << 15)))
+
+#define STM_PIN_MODE(X)     (((X) >>  0) & 0x0F)
+#define STM_PIN_PUPD(X)     (((X) >>  4) & 0x07)
+#define STM_PIN_AFNUM(X)    (((X) >>  7) & 0x0F)
+#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
+#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
+
+#define STM_MODE_INPUT              (0)
+#define STM_MODE_OUTPUT_PP          (1)
+#define STM_MODE_OUTPUT_OD          (2)
+#define STM_MODE_AF_PP              (3)
+#define STM_MODE_AF_OD              (4)
+#define STM_MODE_ANALOG             (5)
+#define STM_MODE_IT_RISING          (6)
+#define STM_MODE_IT_FALLING         (7)
+#define STM_MODE_IT_RISING_FALLING  (8)
+#define STM_MODE_EVT_RISING         (9)
+#define STM_MODE_EVT_FALLING        (10)
+#define STM_MODE_EVT_RISING_FALLING (11)
+#define STM_MODE_IT_EVT_RESET       (12)
+
+// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
+// Low nibble  = pin number
+#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
+#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
+
+typedef enum {
+    PIN_INPUT,
+    PIN_OUTPUT
+} PinDirection;
+
+typedef enum {
+    PA_0  = 0x00,
+    PA_1  = 0x01,
+    PA_2  = 0x02,
+    PA_3  = 0x03,
+    PA_4  = 0x04,
+    PA_5  = 0x05,
+    PA_6  = 0x06,
+    PA_7  = 0x07,
+    PA_8  = 0x08,
+    PA_9  = 0x09,
+    PA_10 = 0x0A,
+    PA_11 = 0x0B,
+    PA_12 = 0x0C,
+    PA_13 = 0x0D,
+    PA_14 = 0x0E,
+    PA_15 = 0x0F,
+
+    PB_0  = 0x10,
+    PB_1  = 0x11,
+    PB_2  = 0x12,
+    PB_3  = 0x13,
+    PB_4  = 0x14,
+    PB_5  = 0x15,
+    PB_6  = 0x16,
+    PB_7  = 0x17,
+    PB_8  = 0x18,
+    PB_9  = 0x19,
+    PB_10 = 0x1A,
+    PB_11 = 0x1B,
+    PB_12 = 0x1C,
+    PB_13 = 0x1D,
+    PB_14 = 0x1E,
+    PB_15 = 0x1F,
+
+    PC_0  = 0x20,
+    PC_1  = 0x21,
+    PC_2  = 0x22,
+    PC_3  = 0x23,
+    PC_4  = 0x24,
+    PC_5  = 0x25,
+    PC_6  = 0x26,
+    PC_7  = 0x27,
+    PC_8  = 0x28,
+    PC_9  = 0x29,
+    PC_10 = 0x2A,
+    PC_11 = 0x2B,
+    PC_12 = 0x2C,
+    PC_13 = 0x2D,
+    PC_14 = 0x2E,
+    PC_15 = 0x2F,
+
+    PD_2  = 0x32,
+
+    PH_0  = 0x70,
+    PH_1  = 0x71,
+
+    // Arduino connector namings
+    A0          = PA_0,
+    A1          = PA_1,
+    A2          = PA_4,
+    A3          = PB_0,
+    A4          = PC_1,
+    A5          = PC_0,
+    D0          = PA_3,
+    D1          = PA_2,
+    D2          = PA_10,
+    D3          = PB_3,
+    D4          = PB_5,
+    D5          = PB_4,
+    D6          = PB_10,
+    D7          = PA_8,
+    D8          = PA_9,
+    D9          = PC_7,
+    D10         = PB_6,
+    D11         = PA_7,
+    D12         = PA_6,
+    D13         = PA_5,
+    D14         = PB_9,
+    D15         = PB_8,
+
+    // Generic signals namings
+    LED1        = PA_5,
+    LED2        = PA_5,
+    LED3        = PA_5,
+    LED4        = PA_5,
+    USER_BUTTON = PC_13,
+    SERIAL_TX   = PA_2,
+    SERIAL_RX   = PA_3,
+    USBTX       = PA_2,
+    USBRX       = PA_3,
+    I2C_SCL     = PB_8,
+    I2C_SDA     = PB_9,
+    SPI_MOSI    = PA_7,
+    SPI_MISO    = PA_6,
+    SPI_SCK     = PA_5,
+    SPI_CS      = PB_6,
+    PWM_OUT     = PB_3,
+
+    // Not connected
+    NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+    PullNone  = 0,
+    PullUp    = 1,
+    PullDown  = 2,
+    OpenDrain = 3,
+    PullDefault = PullNone
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PortNames.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,48 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PORTNAMES_H
+#define MBED_PORTNAMES_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+    PortA = 0,
+    PortB = 1,
+    PortC = 2,
+    PortD = 3,
+    PortH = 7
+} PortName;
+
+#ifdef __cplusplus
+}
+#endif
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,70 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_DEVICE_H
+#define MBED_DEVICE_H
+
+#define DEVICE_PORTIN           1
+#define DEVICE_PORTOUT          1
+#define DEVICE_PORTINOUT        1
+
+#define DEVICE_INTERRUPTIN      1
+
+#define DEVICE_ANALOGIN         1
+#define DEVICE_ANALOGOUT        1
+
+#define DEVICE_SERIAL           1
+
+#define DEVICE_I2C              1
+#define DEVICE_I2CSLAVE         1
+
+#define DEVICE_SPI              1
+#define DEVICE_SPISLAVE         1
+
+#define DEVICE_RTC              1
+
+#define DEVICE_PWMOUT           1
+
+#define DEVICE_SLEEP            1
+
+//=======================================
+
+#define DEVICE_SEMIHOST         0
+#define DEVICE_LOCALFILESYSTEM  0
+#define DEVICE_ID_LENGTH       24
+
+#define DEVICE_DEBUG_AWARENESS  0
+
+#define DEVICE_STDIO_MESSAGES   1
+
+#define DEVICE_ERROR_RED        0
+
+#include "objects.h"
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,113 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2015, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_OBJECTS_H
+#define MBED_OBJECTS_H
+
+#include "cmsis.h"
+#include "PortNames.h"
+#include "PeripheralNames.h"
+#include "PinNames.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+struct gpio_irq_s {
+    IRQn_Type irq_n;
+    uint32_t irq_index;
+    uint32_t event;
+    PinName pin;
+};
+
+struct port_s {
+    PortName port;
+    uint32_t mask;
+    PinDirection direction;
+    __IO uint32_t *reg_in;
+    __IO uint32_t *reg_out;
+};
+
+struct analogin_s {
+    ADCName adc;
+    PinName pin;
+    uint32_t channel;
+};
+
+struct dac_s {
+    DACName dac;
+    PinName pin;
+    uint32_t channel;
+};
+
+struct serial_s {
+    UARTName uart;
+    int index; // Used by irq
+    uint32_t baudrate;
+    uint32_t databits;
+    uint32_t stopbits;
+    uint32_t parity;
+    PinName  pin_tx;
+    PinName  pin_rx;
+};
+
+struct spi_s {
+    SPIName spi;
+    uint32_t bits;
+    uint32_t cpol;
+    uint32_t cpha;
+    uint32_t mode;
+    uint32_t nss;
+    uint32_t br_presc;
+    PinName  pin_miso;
+    PinName  pin_mosi;
+    PinName  pin_sclk;
+    PinName  pin_ssel;
+};
+
+struct i2c_s {
+    I2CName  i2c;
+};
+
+struct pwmout_s {
+    PWMName pwm;
+    PinName pin;
+    uint32_t period;
+    uint32_t pulse;
+    uint32_t channel;
+    uint32_t inverted;
+};
+
+#include "gpio_object.h"
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif

--- /dev/null	Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM32L0/TARGET_NUCLEO_L053R8/rtc_api.c	Tue Sep 27 09:40:53 2016 +0000
@@ -0,0 +1,203 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ *    this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ *    this list of conditions and the following disclaimer in the documentation
+ *    and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ *    may be used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#include "rtc_api.h"
+
+#if DEVICE_RTC
+
+#include "mbed_error.h"
+
+static int rtc_inited = 0;
+
+static RTC_HandleTypeDef RtcHandle;
+
+void rtc_init(void)
+{
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    uint32_t rtc_freq = 0;
+
+    if (rtc_inited) return;
+    rtc_inited = 1;
+
+    RtcHandle.Instance = RTC;
+
+    // Enable Power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
+
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+
+    // Enable LSE Oscillator
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
+    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
+        // Connect LSE to RTC
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
+        rtc_freq = LSE_VALUE;
+    } else {
+        // Enable LSI clock
+        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
+        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
+        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+            error("RTC error: LSI clock initialization failed.");
+        }
+        // Connect LSI to RTC
+        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
+        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
+        // This value is LSI typical value. To be measured precisely using a timer input capture for example.
+        rtc_freq = 32000;
+    }
+
+    // Enable RTC
+    __HAL_RCC_RTC_ENABLE();
+
+    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
+    RtcHandle.Init.AsynchPrediv   = 127;
+    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
+    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
+    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
+    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
+
+    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
+        error("RTC error: RTC initialization failed.");
+    }
+}
+
+void rtc_free(void)
+{
+    // Enable Power clock
+    __PWR_CLK_ENABLE();
+
+    // Enable access to Backup domain
+    HAL_PWR_EnableBkUpAccess();
+
+    // Reset Backup domain
+    __HAL_RCC_BACKUPRESET_FORCE();
+    __HAL_RCC_BACKUPRESET_RELEASE();
+
+    // Disable access to Backup domain
+    HAL_PWR_DisableBkUpAccess();
+
+    // Disable LSI and LSE clocks
+    RCC_OscInitTypeDef RCC_OscInitStruct;
+    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
+    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
+    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
+    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
+    HAL_RCC_OscConfig(&RCC_OscInitStruct);
+
+    rtc_inited = 0;
+}
+
+int rtc_isenabled(void)
+{
+    return rtc_inited;
+}
+
+/*
+ RTC Registers
+   RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
+   RTC_Month   1=january, 2=february, ..., 12=december
+   RTC_Date    day of the month 1-31
+   RTC_Year    year 0-99
+ struct tm
+   tm_sec      seconds after the minute 0-61
+   tm_min      minutes after the hour 0-59
+   tm_hour     hours since midnight 0-23
+   tm_mday     day of the month 1-31
+   tm_mon      months since January 0-11
+   tm_year     years since 1900
+   tm_wday     days since Sunday 0-6
+   tm_yday     days since January 1 0-365
+   tm_isdst    Daylight Saving Time flag
+*/
+time_t rtc_read(void)
+{
+    RTC_DateTypeDef dateStruct;
+    RTC_TimeTypeDef timeStruct;
+    struct tm timeinfo;
+
+    RtcHandle.Instance = RTC;
+
+    // Read actual date and time
+    // Warning: the time must be read first!
+    HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+    HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+
+    // Setup a tm structure based on the RTC
+    timeinfo.tm_wday = dateStruct.WeekDay;
+    timeinfo.tm_mon  = dateStruct.Month - 1;
+    timeinfo.tm_mday = dateStruct.Date;
+    timeinfo.tm_year = dateStruct.Year + 100;
+    timeinfo.tm_hour = timeStruct.Hours;
+    timeinfo.tm_min  = timeStruct.Minutes;
+    timeinfo.tm_sec  = timeStruct.Seconds;
+
+    // Convert to timestamp
+    time_t t = mktime(&timeinfo);
+
+    return t;
+}
+
+void rtc_write(time_t t)
+{
+    RTC_DateTypeDef dateStruct;
+    RTC_TimeTypeDef timeStruct;
+
+    RtcHandle.Instance = RTC;
+
+    // Convert the time into a tm
+    struct tm *timeinfo = localtime(&t);
+
+    // Fill RTC structures
+    dateStruct.WeekDay        = timeinfo->tm_wday;
+    dateStruct.Month          = timeinfo->tm_mon + 1;
+    dateStruct.Date           = timeinfo->tm_mday;
+    dateStruct.Year           = timeinfo->tm_year - 100;
+    timeStruct.Hours          = timeinfo->tm_hour;
+    timeStruct.Minutes        = timeinfo->tm_min;
+    timeStruct.Seconds        = timeinfo->tm_sec;
+    timeStruct.TimeFormat     = RTC_HOURFORMAT12_PM;
+    timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
+    timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
+
+    // Change the RTC current date/time
+    HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
+    HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
+}
+
+#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_MICRO/startup_stm32l053xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,242 +0,0 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.2.0
-;* Date               : 06-February-2015
-;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-                
-Stack_Mem       SPACE   Stack_Size
-__initial_sp    EQU     0x20002000 ; Top of RAM
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000400
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit    EQU (__initial_sp - Stack_Size)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_MICRO/stm32l053c8.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L053C8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
-LR_IROM1 0x08000000 0x10000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x10000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x2000-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_MICRO/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_STD/startup_stm32l053xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,215 +0,0 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.2.0
-;* Date               : 06-February-2015
-;* Description        : STM32l053xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>
-;*******************************************************************************
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-
-__initial_sp    EQU     0x20002000 ; Top of RAM
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler
-LPTIM1_IRQHandler
-TIM2_IRQHandler
-TIM6_DAC_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_STD/stm32l053c8.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,44 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L053C8: 64KB FLASH (0x10000) + 8KB RAM (0x2000)
-LR_IROM1 0x08000000 0x10000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x10000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x2000-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_ARM_STD/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_GCC_ARM/STM32L053X8.ld	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 64k
-  RAM (rwx) : ORIGIN = 0x200000C0, LENGTH = 8K - 0xC0
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_GCC_ARM/startup_stm32l053xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,299 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l053xx.s
-  * @author    MCD Application Team
-  * @version   V1.2.0
-  * @date      06-February-2015
-  * @brief     STM32L053xx Devices vector table for Atollic TrueSTUDIO toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2]
-  adds r2, r2, #4
-
-
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-  //bl __libc_init_array
-/* Call the application's entry point.*/
-  //bl  main
-  bl _start
-
-LoopForever:
-    b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     0                                 /* Reserved                     */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     0                                 /* Reserved                     */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     0               				          /* Reserved                     */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     0                                 /* Reserved                     */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
-  .word     LCD_IRQHandler                    /* LCD                          */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      DebugMon_Handler
-   .thumb_set DebugMon_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      RNG_LPUART1_IRQHandler
-   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      LCD_IRQHandler
-   .thumb_set LCD_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_IAR/startup_stm32l053xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,332 +0,0 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.2.0
-;* Date               : 06-February-2015
-;* Description        : STM32L053xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler                ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/TOOLCHAIN_IAR/stm32l053xx.icf	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* [ROM = 64kb = 0x10000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0800FFFF;
-
-/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x200000C0;
-define symbol __region_RAM_end__      = 0x20001FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x500;
-define symbol __size_heap__   = 0x1000;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/cmsis.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32l0xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/cmsis_nvic.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    uint32_t *vectors = (uint32_t *)SCB->VTOR;
-    uint32_t i;
-
-    // Copy and switch to dynamic vectors if the first time called
-    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = vectors;
-        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
-    }
-    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/cmsis_nvic.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
-// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-#define NVIC_NUM_VECTORS      48
-#define NVIC_USER_IRQ_OFFSET  16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/hal_tick.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,145 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.c
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-#include "hal_tick.h"
-
-TIM_HandleTypeDef TimMasterHandle;
-uint32_t PreviousVal = 0;
-
-void us_ticker_irq_handler(void);
-void set_compare(uint16_t count);
-
-extern volatile uint32_t SlaveCounter;
-extern volatile uint32_t oc_int_part;
-extern volatile uint16_t oc_rem_part;
-
-void timer_irq_handler(void) {
-    uint16_t cval = TIM_MST->CNT;
-
-    TimMasterHandle.Instance = TIM_MST;
-
-    // Clear Update interrupt flag
-    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
-        __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE);
-        SlaveCounter++;
-    }
-
-    // Channel 1 for mbed timeout
-    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
-        __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
-        if (oc_rem_part > 0) {
-            set_compare(oc_rem_part); // Finish the remaining time left
-            oc_rem_part = 0;
-        } else {
-            if (oc_int_part > 0) {
-                set_compare(0xFFFF);
-                oc_rem_part = cval; // To finish the counter loop the next time
-                oc_int_part--;
-            } else {
-                us_ticker_irq_handler();
-            }
-        }
-    }
-
-    // Channel 2 for HAL tick
-    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
-        __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC2);
-        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
-        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
-            // Increment HAL variable
-            HAL_IncTick();
-            // Prepare next interrupt
-            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
-            PreviousVal = val;
-        }
-    }
-}
-
-// Reconfigure the HAL tick using a standard timer instead of systick.
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
-    // Enable timer clock
-    TIM_MST_RCC;
-
-    // Reset timer
-    TIM_MST_RESET_ON;
-    TIM_MST_RESET_OFF;
-
-    // Update the SystemCoreClock variable
-    SystemCoreClockUpdate();
-
-    // Configure time base
-    TimMasterHandle.Instance = TIM_MST;
-    TimMasterHandle.Init.Period        = 0xFFFFFFFF;
-    TimMasterHandle.Init.Prescaler     = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
-    TimMasterHandle.Init.ClockDivision = 0;
-    TimMasterHandle.Init.CounterMode   = TIM_COUNTERMODE_UP;
-    HAL_TIM_Base_Init(&TimMasterHandle);
-
-    // Configure output compare channel 1 for mbed timeout (enabled later when used)
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
-
-    // Configure output compare channel 2 for HAL tick
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
-    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
-    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
-
-    // Configure interrupts
-    // Update interrupt used for 32-bit counter
-    // Output compare channel 1 interrupt for mbed timeout
-    // Output compare channel 2 interrupt for HAL tick
-    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
-    NVIC_EnableIRQ(TIM_MST_IRQ);
-
-    // Enable interrupts
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick
-
-    // Enable timer
-    HAL_TIM_Base_Start(&TimMasterHandle);
-
-    return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/hal_tick.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.h
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32l0xx.h"
-#include "cmsis_nvic.h"
-   
-#define TIM_MST      TIM21
-#define TIM_MST_IRQ  TIM21_IRQn
-#define TIM_MST_RCC  __TIM21_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l053xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,4189 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l053xx.h
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l053xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l053xx
-  * @{
-  */
-    
-#ifndef __STM32L053xx_H
-#define __STM32L053xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1 /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l053xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
-  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t  IDR;        /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  uint32_t      RESERVED0[6];  /*!<                                                                     0x14-0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  uint32_t      RESERVED1;     /*!<                                                                          0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FW_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;     /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;     /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;       /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;      /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;    /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;    /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;     /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;      /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;      /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;      /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  __IO uint32_t RCR;      /*!< TIM  repetition counter register,             Address offset: 0x30 */
-  __IO uint32_t CCR1;     /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;     /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;     /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;     /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  __IO uint32_t BDTR;     /*!< TIM break and dead-time register,             Address offset: 0x44 */
-  __IO uint32_t DCR;      /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;     /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;       /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-  
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE             ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_END              ((uint32_t)0x0800FFFF) /*!< FLASH end address in the alias region */
-#define DATA_EEPROM_BASE       ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_END        ((uint32_t)0x080807FF) /*!< DATA EEPROM end address in the alias region */
-#define SRAM_BASE              ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE            ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
-#define LCD_BASE              (APBPERIPH_BASE + 0x00002400)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001C)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400)
-#define FW_BASE               (APBPERIPH_BASE + 0x00011C00)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FF80000)        /*!< FLASH Option Bytes base address */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FW                  ((FW_TypeDef *) FW_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL                       ((uint32_t)0x00000800)     /*!< End of calibration flag */
-#define ADC_ISR_AWD                         ((uint32_t)0x00000080)     /*!< Analog watchdog flag */
-#define ADC_ISR_OVR                         ((uint32_t)0x00000010)     /*!< Overrun flag */
-#define ADC_ISR_EOSEQ                       ((uint32_t)0x00000008)     /*!< End of Sequence flag */
-#define ADC_ISR_EOC                         ((uint32_t)0x00000004)     /*!< End of Conversion */
-#define ADC_ISR_EOSMP                       ((uint32_t)0x00000002)     /*!< End of sampling flag */
-#define ADC_ISR_ADRDY                       ((uint32_t)0x00000001)     /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE                     ((uint32_t)0x00000800)     /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE                       ((uint32_t)0x00000080)     /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE                       ((uint32_t)0x00000010)     /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE                     ((uint32_t)0x00000008)     /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE                       ((uint32_t)0x00000004)     /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE                     ((uint32_t)0x00000002)     /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE                     ((uint32_t)0x00000001)     /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL                        ((uint32_t)0x80000000)     /*!< ADC calibration */
-#define ADC_CR_ADVREGEN                     ((uint32_t)0x10000000)     /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP                        ((uint32_t)0x00000010)     /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART                      ((uint32_t)0x00000004)     /*!< ADC start of conversion */
-#define ADC_CR_ADDIS                        ((uint32_t)0x00000002)     /*!< ADC disable command */
-#define ADC_CR_ADEN                         ((uint32_t)0x00000001)     /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH                     ((uint32_t)0x7C000000)     /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0                   ((uint32_t)0x04000000)     /*!< Bit 0 */
-#define ADC_CFGR1_AWDCH_1                   ((uint32_t)0x08000000)     /*!< Bit 1 */
-#define ADC_CFGR1_AWDCH_2                   ((uint32_t)0x10000000)     /*!< Bit 2 */
-#define ADC_CFGR1_AWDCH_3                   ((uint32_t)0x20000000)     /*!< Bit 3 */
-#define ADC_CFGR1_AWDCH_4                   ((uint32_t)0x40000000)     /*!< Bit 4 */
-#define ADC_CFGR1_AWDEN                     ((uint32_t)0x00800000)     /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL                    ((uint32_t)0x00400000)     /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN                    ((uint32_t)0x00010000)     /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF                    ((uint32_t)0x00008000)     /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT                      ((uint32_t)0x00004000)     /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT                      ((uint32_t)0x00002000)     /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD                    ((uint32_t)0x00001000)     /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN                     ((uint32_t)0x00000C00)     /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0                   ((uint32_t)0x00000400)     /*!< Bit 0 */
-#define ADC_CFGR1_EXTEN_1                   ((uint32_t)0x00000800)     /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL                    ((uint32_t)0x000001C0)     /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0                  ((uint32_t)0x00000040)     /*!< Bit 0 */
-#define ADC_CFGR1_EXTSEL_1                  ((uint32_t)0x00000080)     /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL_2                  ((uint32_t)0x00000100)     /*!< Bit 2 */
-#define ADC_CFGR1_ALIGN                     ((uint32_t)0x00000020)     /*!< Data Alignment */
-#define ADC_CFGR1_RES                       ((uint32_t)0x00000018)     /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0                     ((uint32_t)0x00000008)     /*!< Bit 0 */
-#define ADC_CFGR1_RES_1                     ((uint32_t)0x00000010)     /*!< Bit 1 */
-#define ADC_CFGR1_SCANDIR                   ((uint32_t)0x00000004)     /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG                    ((uint32_t)0x00000002)     /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN                     ((uint32_t)0x00000001)     /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS                      ((uint32_t)0x80000200)     /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS                      ((uint32_t)0x000001E0)     /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0                    ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define ADC_CFGR2_OVSS_1                    ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define ADC_CFGR2_OVSS_2                    ((uint32_t)0x00000080)     /*!< Bit 2 */
-#define ADC_CFGR2_OVSS_3                    ((uint32_t)0x00000100)     /*!< Bit 3 */
-#define ADC_CFGR2_OVSR                      ((uint32_t)0x0000001C)     /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0                    ((uint32_t)0x00000004)     /*!< Bit 0 */
-#define ADC_CFGR2_OVSR_1                    ((uint32_t)0x00000008)     /*!< Bit 1 */
-#define ADC_CFGR2_OVSR_2                    ((uint32_t)0x00000010)     /*!< Bit 2 */
-#define ADC_CFGR2_OVSE                      ((uint32_t)0x00000001)     /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE                    ((uint32_t)0xC0000000)     /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0                  ((uint32_t)0x40000000)     /*!< Bit 0 */
-#define ADC_CFGR2_CKMODE_1                  ((uint32_t)0x80000000)     /*!< Bit 1 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP                        ((uint32_t)0x00000007)     /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0                      ((uint32_t)0x00000001)     /*!< Bit 0 */
-#define ADC_SMPR_SMP_1                      ((uint32_t)0x00000002)     /*!< Bit 1 */
-#define ADC_SMPR_SMP_2                      ((uint32_t)0x00000004)     /*!< Bit 2 */
-
-/* Bit names aliases maintained for legacy */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT                           ((uint32_t)0x0FFF0000)     /*!< Analog watchdog high threshold */
-#define ADC_TR_LT                           ((uint32_t)0x00000FFF)     /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL18                  ((uint32_t)0x00040000)     /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17                  ((uint32_t)0x00020000)     /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16                  ((uint32_t)0x00010000)     /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15                  ((uint32_t)0x00008000)     /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14                  ((uint32_t)0x00004000)     /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13                  ((uint32_t)0x00002000)     /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12                  ((uint32_t)0x00001000)     /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11                  ((uint32_t)0x00000800)     /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10                  ((uint32_t)0x00000400)     /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9                   ((uint32_t)0x00000200)     /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8                   ((uint32_t)0x00000100)     /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7                   ((uint32_t)0x00000080)     /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6                   ((uint32_t)0x00000040)     /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5                   ((uint32_t)0x00000020)     /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4                   ((uint32_t)0x00000010)     /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3                   ((uint32_t)0x00000008)     /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2                   ((uint32_t)0x00000004)     /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1                   ((uint32_t)0x00000002)     /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0                   ((uint32_t)0x00000001)     /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA                         ((uint32_t)0x0000FFFF)     /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT                 ((uint32_t)0x0000007F)     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN                       ((uint32_t)0x02000000)     /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN                      ((uint32_t)0x01000000)     /*!< Voltage battery enable */
-#define ADC_CCR_TSEN                        ((uint32_t)0x00800000)     /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN                      ((uint32_t)0x00400000)     /*!< Vrefint enable */
-#define ADC_CCR_PRESC                       ((uint32_t)0x003C0000)     /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0                     ((uint32_t)0x00040000)     /*!< Bit 0 */
-#define ADC_CCR_PRESC_1                     ((uint32_t)0x00080000)     /*!< Bit 1 */
-#define ADC_CCR_PRESC_2                     ((uint32_t)0x00100000)     /*!< Bit 2 */
-#define ADC_CCR_PRESC_3                     ((uint32_t)0x00200000)     /*!< Bit 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN                ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL            ((uint32_t)0x00000030) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INNSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1WM                ((uint32_t)0x00000100) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1         ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY          ((uint32_t)0x00008000) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE             ((uint32_t)0x40000000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK              ((uint32_t)0x80000000) /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN                ((uint32_t)0x00000001) /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED             ((uint32_t)0x000C0008) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL            ((uint32_t)0x00100070) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0          ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INNSEL_1          ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INNSEL_2          ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_COMP2INPSEL            ((uint32_t)0x00000700) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0          ((uint32_t)0x00000100) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_1          ((uint32_t)0x00000200) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_2          ((uint32_t)0x00000400) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2LPTIM1IN2         ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2POLARITY          ((uint32_t)0x00008000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE             ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK              ((uint32_t)0x80000000) /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN                ((uint32_t)0x00000001) /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY          ((uint32_t)0x00008000) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE          ((uint32_t)0x40000000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK              ((uint32_t)0x80000000) /*!< COMPx lock */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR                         ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE                     ((uint32_t)0x00000018) /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0                   ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
-#define CRC_CR_POLYSIZE_1                   ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
-#define CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< Bit 0 */
-#define CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< Bit 1 */
-#define CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
-#define CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
-#define CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
-#define CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
-
-#define CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
-#define CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
-
-#define CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
-#define CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
-#define CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
-#define CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
-#define CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag             */
-#define CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!< DAC channel1 DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!< DAC channel1 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)        /*!< DAC channel1 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR                   ((uint16_t)0x00000FFF)        /*!< DAC channel1 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG                       ((uint32_t)0x00000007)        /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP        ((uint32_t)0x00200000)        /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP        ((uint32_t)0x00400000)        /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP     ((uint32_t)0x80000000)        /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP       ((uint32_t)0x00000020)        /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP       ((uint32_t)0x00000004)        /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
-#define DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
-#define DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
-#define DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
-#define DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
-
-#define DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
-#define DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
-
-#define DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
-#define DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
-
-#define DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S                       ((uint32_t)0x0000000F)          /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S                       ((uint32_t)0x000000F0)          /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S                       ((uint32_t)0x00000F00)          /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S                       ((uint32_t)0x0000F000)          /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S                       ((uint32_t)0x000F0000)          /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S                       ((uint32_t)0x00F00000)          /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S                       ((uint32_t)0x0F000000)          /*!< Channel 7 Selection */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
-#define EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
-#define EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
-#define EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
-#define EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
-#define EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
-#define EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
-#define EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
-#define EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
-#define EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
-#define EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
-#define EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
-#define EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
-#define EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
-#define EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
-#define EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
-#define EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
-#define EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
-#define EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
-#define EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
-#define EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
-#define EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF                 ((uint32_t)0x00000020)        /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ                  ((uint32_t)0x00000040)        /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
-#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
-#define FLASH_PECR_FIX                       ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
-#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY                ((uint32_t)0x00080000)        /*!< Half array mode */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
-#define FLASH_SR_HVOFF                      ((uint32_t)0x00000004)        /*!< End of high voltage */
-#define FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protection error */
-#define FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
-#define FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option Valid error */
-#define FLASH_SR_RDERR                      ((uint32_t)0x00002000)        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR                 ((uint32_t)0x00010000)        /*!< Not Zero error */
-#define FLASH_SR_FWWERR                     ((uint32_t)0x00020000)        /*!< Write/Errase operation aborted */
-
-/* alias maintained for legacy */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT                   ((uint32_t)0x000000FF)        /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD                   ((uint32_t)0x00000100)        /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV                  ((uint32_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW                  ((uint32_t)0x00100000)        /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP                ((uint32_t)0x00200000)        /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY               ((uint32_t)0x00400000)        /*!< nRST_STDBY */
-#define FLASH_OPTR_USER                     ((uint32_t)0x00700000)        /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1                    ((uint32_t)0x80000000)        /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP                      ((uint32_t)0x0000FFFF)        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODE0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODE0_1        ((uint32_t)0x00000002)
-#define GPIO_MODER_MODE1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODE1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODE1_1        ((uint32_t)0x00000008)
-#define GPIO_MODER_MODE2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODE2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODE2_1        ((uint32_t)0x00000020)
-#define GPIO_MODER_MODE3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODE3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODE3_1        ((uint32_t)0x00000080)
-#define GPIO_MODER_MODE4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODE4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODE4_1        ((uint32_t)0x00000200)
-#define GPIO_MODER_MODE5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODE5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODE5_1        ((uint32_t)0x00000800)
-#define GPIO_MODER_MODE6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODE6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODE6_1        ((uint32_t)0x00002000)
-#define GPIO_MODER_MODE7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODE7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODE7_1        ((uint32_t)0x00008000)
-#define GPIO_MODER_MODE8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODE8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODE8_1        ((uint32_t)0x00020000)
-#define GPIO_MODER_MODE9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODE9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODE9_1        ((uint32_t)0x00080000)
-#define GPIO_MODER_MODE10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODE10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODE10_1       ((uint32_t)0x00200000)
-#define GPIO_MODER_MODE11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODE11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODE11_1       ((uint32_t)0x00800000)
-#define GPIO_MODER_MODE12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODE12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODE12_1       ((uint32_t)0x02000000)
-#define GPIO_MODER_MODE13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODE13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODE13_1       ((uint32_t)0x08000000)
-#define GPIO_MODER_MODE14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODE14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODE14_1       ((uint32_t)0x20000000)
-#define GPIO_MODER_MODE15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODE15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODE15_1       ((uint32_t)0x80000000)
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0          ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1          ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2          ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3          ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4          ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5          ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6          ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7          ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8          ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9          ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10         ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11         ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12         ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13         ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14         ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15         ((uint32_t)0x00008000)
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEED0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEED0_1   ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEED1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEED1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEED1_1   ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEED2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEED2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEED2_1   ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEED3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEED3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEED3_1   ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEED4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEED4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEED4_1   ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEED5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEED5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEED5_1   ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEED6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEED6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEED6_1   ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEED7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEED7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEED7_1   ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEED8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEED8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEED8_1   ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEED9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEED9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEED9_1   ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEED10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEED10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEED10_1  ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEED11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEED11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEED11_1  ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEED12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEED12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEED12_1  ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEED13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEED13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEED13_1  ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEED14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEED14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEED14_1  ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEED15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEED15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEED15_1  ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPD0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPD0_1        ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPD1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPD1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPD1_1        ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPD2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPD2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPD2_1        ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPD3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPD3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPD3_1        ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPD4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPD4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPD4_1        ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPD5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPD5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPD5_1        ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPD6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPD6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPD6_1        ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPD7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPD7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPD7_1        ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPD8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPD8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPD8_1        ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPD9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPD9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPD9_1        ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPD10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPD10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPD10_1       ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPD11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPD11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPD11_1       ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPD12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPD12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPD12_1       ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPD13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPD13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPD13_1       ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPD14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPD14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPD14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPD15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPD15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPD15_1       ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0              ((uint32_t)0x00000001)
-#define GPIO_IDR_ID1              ((uint32_t)0x00000002)
-#define GPIO_IDR_ID2              ((uint32_t)0x00000004)
-#define GPIO_IDR_ID3              ((uint32_t)0x00000008)
-#define GPIO_IDR_ID4              ((uint32_t)0x00000010)
-#define GPIO_IDR_ID5              ((uint32_t)0x00000020)
-#define GPIO_IDR_ID6              ((uint32_t)0x00000040)
-#define GPIO_IDR_ID7              ((uint32_t)0x00000080)
-#define GPIO_IDR_ID8              ((uint32_t)0x00000100)
-#define GPIO_IDR_ID9              ((uint32_t)0x00000200)
-#define GPIO_IDR_ID10             ((uint32_t)0x00000400)
-#define GPIO_IDR_ID11             ((uint32_t)0x00000800)
-#define GPIO_IDR_ID12             ((uint32_t)0x00001000)
-#define GPIO_IDR_ID13             ((uint32_t)0x00002000)
-#define GPIO_IDR_ID14             ((uint32_t)0x00004000)
-#define GPIO_IDR_ID15             ((uint32_t)0x00008000)
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0              ((uint32_t)0x00000001)
-#define GPIO_ODR_OD1              ((uint32_t)0x00000002)
-#define GPIO_ODR_OD2              ((uint32_t)0x00000004)
-#define GPIO_ODR_OD3              ((uint32_t)0x00000008)
-#define GPIO_ODR_OD4              ((uint32_t)0x00000010)
-#define GPIO_ODR_OD5              ((uint32_t)0x00000020)
-#define GPIO_ODR_OD6              ((uint32_t)0x00000040)
-#define GPIO_ODR_OD7              ((uint32_t)0x00000080)
-#define GPIO_ODR_OD8              ((uint32_t)0x00000100)
-#define GPIO_ODR_OD9              ((uint32_t)0x00000200)
-#define GPIO_ODR_OD10             ((uint32_t)0x00000400)
-#define GPIO_ODR_OD11             ((uint32_t)0x00000800)
-#define GPIO_ODR_OD12             ((uint32_t)0x00001000)
-#define GPIO_ODR_OD13             ((uint32_t)0x00002000)
-#define GPIO_ODR_OD14             ((uint32_t)0x00004000)
-#define GPIO_ODR_OD15             ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0            ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1            ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2            ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3            ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4            ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5            ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6            ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7            ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8            ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9            ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10           ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11           ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12           ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13           ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14           ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15           ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0            ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1            ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2            ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3            ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4            ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5            ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6            ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7            ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8            ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9            ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10           ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11           ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12           ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13           ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14           ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15           ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0            ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1            ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2            ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3            ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4            ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5            ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6            ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7            ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8            ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9            ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10           ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11           ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12           ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13           ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14           ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15           ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK            ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0             ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1             ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2             ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3             ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4             ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5             ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6             ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7             ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8             ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9             ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10            ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11            ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12            ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13            ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14            ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15            ((uint32_t)0x00008000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
-#define I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
-#define I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
-#define I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
-#define I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
-#define I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
-#define I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
-#define I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
-#define I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
-#define I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
-#define I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
-#define I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
-#define I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
-#define I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
-#define I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
-#define I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
-#define I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
-#define I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
-#define I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY                         ((uint32_t)0x0000FFFF)       /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR                          ((uint32_t)0x00000007)       /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        ((uint32_t)0x00000001)       /*!< Bit 0 */
-#define IWDG_PR_PR_1                        ((uint32_t)0x00000002)       /*!< Bit 1 */
-#define IWDG_PR_PR_2                        ((uint32_t)0x00000004)       /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL                         ((uint32_t)0x00000FFF)       /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU                         ((uint32_t)0x00000001)       /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU                         ((uint32_t)0x00000002)       /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU                         ((uint32_t)0x00000004)       /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN                       ((uint32_t)0x00000FFF)       /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */
-#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */
-#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */
-#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */
-
-#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */
-#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */
-#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */
-
-#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */
-#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */
-#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */
-#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */
-
-#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */
-#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */
-#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM                         ((uint32_t)0x00000001)            /*!< Compare match */
-#define LPTIM_ISR_ARRM                         ((uint32_t)0x00000002)            /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG                      ((uint32_t)0x00000004)            /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK                        ((uint32_t)0x00000008)            /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK                        ((uint32_t)0x00000010)            /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP                           ((uint32_t)0x00000020)            /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN                         ((uint32_t)0x00000040)            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF                       ((uint32_t)0x00000001)            /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF                       ((uint32_t)0x00000002)            /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF                    ((uint32_t)0x00000004)            /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF                      ((uint32_t)0x00000008)            /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE                       ((uint32_t)0x00000001)            /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE                       ((uint32_t)0x00000002)            /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE                    ((uint32_t)0x00000004)            /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE                      ((uint32_t)0x00000008)            /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL                       ((uint32_t)0x00000001)             /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL                       ((uint32_t)0x00000006)             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0                     ((uint32_t)0x00000002)             /*!< Bit 0 */
-#define LPTIM_CFGR_CKPOL_1                     ((uint32_t)0x00000004)             /*!< Bit 1 */
-
-#define LPTIM_CFGR_CKFLT                       ((uint32_t)0x00000018)             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0                     ((uint32_t)0x00000008)             /*!< Bit 0 */
-#define LPTIM_CFGR_CKFLT_1                     ((uint32_t)0x00000010)             /*!< Bit 1 */
-
-#define LPTIM_CFGR_TRGFLT                      ((uint32_t)0x000000C0)             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0                    ((uint32_t)0x00000040)             /*!< Bit 0 */
-#define LPTIM_CFGR_TRGFLT_1                    ((uint32_t)0x00000080)             /*!< Bit 1 */
-
-#define LPTIM_CFGR_PRESC                       ((uint32_t)0x00000E00)             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0                     ((uint32_t)0x00000200)             /*!< Bit 0 */
-#define LPTIM_CFGR_PRESC_1                     ((uint32_t)0x00000400)             /*!< Bit 1 */
-#define LPTIM_CFGR_PRESC_2                     ((uint32_t)0x00000800)             /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGSEL                     ((uint32_t)0x0000E000)             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0                   ((uint32_t)0x00002000)             /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGSEL_1                   ((uint32_t)0x00004000)             /*!< Bit 1 */
-#define LPTIM_CFGR_TRIGSEL_2                   ((uint32_t)0x00008000)             /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGEN                      ((uint32_t)0x00060000)             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0                    ((uint32_t)0x00020000)             /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGEN_1                    ((uint32_t)0x00040000)             /*!< Bit 1 */
-
-#define LPTIM_CFGR_TIMOUT                      ((uint32_t)0x00080000)             /*!< Timout enable */
-#define LPTIM_CFGR_WAVE                        ((uint32_t)0x00100000)             /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL                      ((uint32_t)0x00200000)             /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD                     ((uint32_t)0x00400000)             /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE                   ((uint32_t)0x00800000)             /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC                         ((uint32_t)0x01000000)             /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE                        ((uint32_t)0x00000001)             /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT                       ((uint32_t)0x00000002)             /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT                       ((uint32_t)0x00000004)             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP                          ((uint32_t)0x0000FFFF)             /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR                          ((uint32_t)0x0000FFFF)             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT                          ((uint32_t)0x0000FFFF)             /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD                         ((uint32_t)0x00FFFF00)        /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG                         ((uint32_t)0x003FFF00)        /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD                       ((uint32_t)0x00FFFF00)        /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG                       ((uint32_t)0x003FFF00)        /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD                        ((uint32_t)0x0000FFC0)        /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG                        ((uint32_t)0x0000FFC0)        /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA                           ((uint32_t)0x00000001)         /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS                           ((uint32_t)0x00000002)         /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE                           ((uint32_t)0x00000004)         /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR                       ((uint32_t)0x00000001)     /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag */
-#define PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
-
-#define PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP                          ((uint32_t)0x00000200)     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU                          ((uint32_t)0x00000400)     /*!< Fast wakeup */
-
-#define PWR_CR_VOS                          ((uint32_t)0x00001800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        ((uint32_t)0x00000800)     /*!< Bit 0 */
-#define PWR_CR_VOS_1                        ((uint32_t)0x00001000)     /*!< Bit 1 */
-#define PWR_CR_DSEEKOFF                     ((uint32_t)0x00002000)     /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN                        ((uint32_t)0x00004000)     /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag */
-#define PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag */
-#define PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF                 ((uint32_t)0x00000008)     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF                        ((uint32_t)0x00000010)     /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF                      ((uint32_t)0x00000020)     /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1                       ((uint32_t)0x00000100)     /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2                       ((uint32_t)0x00000200)     /*!< Enable WKUP pin 2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON                     ((uint32_t)0x00000002)        /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY                       ((uint32_t)0x00000004)        /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN                     ((uint32_t)0x00000008)        /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF                      ((uint32_t)0x00000010)        /*!< Internal High Speed clock divider flag */
-#define RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON                     ((uint32_t)0x00080000)        /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE                       ((uint32_t)0x00300000)        /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                     ((uint32_t)0x00100000)        /*!< RTC/LCD prescaler Bit 0 */
-#define RCC_CR_RTCPRE_1                     ((uint32_t)0x00200000)        /*!< RTC/LCD prescaler Bit 1 */
-#define RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON                   ((uint32_t)0x00000001)        /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY                  ((uint32_t)0x00000002)        /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48CAL                  ((uint32_t)0x0000FF00)        /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK                   ((uint32_t)0x00008000)        /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
-#define RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
-
-#define RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL                     ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define RCC_CFGR_MCOSEL_3                   ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
-#define RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
-#define RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
-#define RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE                   ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE                   ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE                   ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE                   ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE                   ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE                   ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE                 ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_LSECSSIE                   ((uint32_t)0x00000080)        /*!< LSE CSS Interrupt Enable */
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF                    ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF                    ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF                    ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF                    ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF                    ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF                    ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF                  ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_LSECSSF                    ((uint32_t)0x00000080)        /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSF                       ((uint32_t)0x00000100)        /*!< Clock Security System Interrupt flag */
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC                    ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC                    ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC                    ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC                    ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC                    ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC                    ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC                  ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_LSECSSC                    ((uint32_t)0x00000080)        /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSC                       ((uint32_t)0x00000100)        /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOHRST                ((uint32_t)0x00000080)        /*!< GPIO port H reset */
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x00000001)        /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST                  ((uint32_t)0x00000100)        /*!< Memory interface reset reset */
-#define RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00010000)        /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST                  ((uint32_t)0x00100000)        /*!< RNG reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_TIM21RST               ((uint32_t)0x00000004)        /*!< TIM21 clock reset */
-#define RCC_APB2RSTR_TIM22RST               ((uint32_t)0x00000020)        /*!< TIM22 clock reset */
-#define RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
-#define RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD clock reset */
-#define RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_LPUART1RST             ((uint32_t)0x00040000)        /*!< LPUART1 clock reset */
-#define RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
-#define RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
-#define RCC_APB1RSTR_LPTIM1RST              ((uint32_t)0x80000000)        /*!< LPTIM1 clock reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOHEN                  ((uint32_t)0x00000080)        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN                    ((uint32_t)0x00000100)        /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN                    ((uint32_t)0x00010000)        /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN                    ((uint32_t)0x00100000)        /*!< RNG clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN                 ((uint32_t)0x00000004)        /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN                 ((uint32_t)0x00000020)        /*!< TIM22 clock enable */
-#define RCC_APB2ENR_MIFIEN                  ((uint32_t)0x00000080)        /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN               ((uint32_t)0x00040000)        /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
-#define RCC_APB1ENR_LPTIM1EN                ((uint32_t)0x80000000)        /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_GPIOASMEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              ((uint32_t)0x00000080)        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMA1SMEN               ((uint32_t)0x00000001)        /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN                ((uint32_t)0x00000100)        /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN               ((uint32_t)0x00000200)        /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN                ((uint32_t)0x00010000)        /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN                ((uint32_t)0x00100000)        /*!< RNG clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN            ((uint32_t)0x00000001)        /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN             ((uint32_t)0x00000004)        /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN             ((uint32_t)0x00000020)        /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADC1SMEN              ((uint32_t)0x00000200)        /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN              ((uint32_t)0x00001000)        /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN            ((uint32_t)0x00004000)        /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            ((uint32_t)0x00400000)        /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN              ((uint32_t)0x00004000)        /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN            ((uint32_t)0x00020000)        /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN           ((uint32_t)0x00040000)        /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN              ((uint32_t)0x00200000)        /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN              ((uint32_t)0x00400000)        /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN               ((uint32_t)0x08000000)        /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN                ((uint32_t)0x10000000)       /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN               ((uint32_t)0x20000000)        /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN            ((uint32_t)0x80000000)        /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL                 ((uint32_t)0x00000003)        /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0               ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define RCC_CCIPR_USART1SEL_1               ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL                 ((uint32_t)0x0000000C)        /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0               ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define RCC_CCIPR_USART2SEL_1               ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL                ((uint32_t)0x0000C00)         /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0              ((uint32_t)0x0000400)         /*!< Bit 0 */
-#define RCC_CCIPR_LPUART1SEL_1              ((uint32_t)0x0000800)         /*!< Bit 1 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL                   ((uint32_t)0x00003000)        /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0                 ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define RCC_CCIPR_I2C1SEL_1                 ((uint32_t)0x00002000)        /*!< Bit 1 */
-
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL                 ((uint32_t)0x000C0000)        /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0               ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define RCC_CCIPR_LPTIM1SEL_1               ((uint32_t)0x00080000)        /*!< Bit 1 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL                  ((uint32_t)0x04000000)        /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Bit name alias maintained for legacy */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON                       ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY                      ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP                      ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV                      ((uint32_t)0x00001800)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define RCC_CSR_LSEDRV_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-                                             
-#define RCC_CSR_LSECSSON                    ((uint32_t)0x00002000)        /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD                     ((uint32_t)0x00004000)        /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL                      ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define RCC_CSR_RTCSEL_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)        /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE                  ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI                  ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE                  ((uint32_t)0x00030000)        /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN                       ((uint32_t)0x00040000)        /*!< RTC clock enable */
-#define RCC_CSR_RTCRST                      ((uint32_t)0x00080000)        /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF                        ((uint32_t)0x00800000)        /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF                      ((uint32_t)0x01000000)        /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
-#define RNG_CR_IE                            ((uint32_t)0x00000008)
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TR_HT                            ((uint32_t)0x00300000)        /*!<  */
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)        /*!<  */
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TR_ST                            ((uint32_t)0x00000070)        /*!<  */
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)        /*!<  */
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)        /*!<  */
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)        /*!<  */
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)        /*!<  */
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)        /*!<  */
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)        /*!<  */
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)        /*!<  */
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)        /*!<  */
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)        /*!<  */
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)        /*!<  */
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)        /*!<  */
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)        /*!<  */
-#define RTC_DR_MT                            ((uint32_t)0x00001000)        /*!<  */
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)        /*!<  */
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)        /*!<  */
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)        /*!<  */
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)        /*!<  */
-#define RTC_DR_DT                            ((uint32_t)0x00000030)        /*!<  */
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)        /*!<  */
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)        /*!<  */
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)        /*!<  */
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)        /*!<  */
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)        /*!<  */
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)        /*!<  */
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)        /*!<  */
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_CR_POL                           ((uint32_t)0x00100000)        /*!<  */
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)        /*!<  */
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)        /*!<  */
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)        /*!<  */
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)        /*!<  */
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)        /*!<  */
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)        /*!<  */
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)        /*!<  */
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)        /*!<  */
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)        /*!<  */
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)        /*!<  */
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)        /*!<  */
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)        /*!<  */
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)        /*!<  */
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)        /*!<  */
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)        /*!<  */
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)        /*!<  */
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)        /*!<  */
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)        /*!<  */
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)        /*!<  */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)        /*!<  */
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)        /*!<  */
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)        /*!<  */
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)        /*!<  */
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)        /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)        /*!<  */
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)        /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)        /*!<  */
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)        /*!<  */
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)        /*!<  */
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)        /*!<  */
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)        /*!<  */
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)        /*!<  */
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)        /*!<  */
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)        /*!<  */
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)        /*!<  */
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)        /*!<  */
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)        /*!<  */
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)        /*!<  */
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)        /*!<  */
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)        /*!<  */
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)        /*!<  */
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)        /*!<  */
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)        /*!<  */
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)        /*!<  */
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)        /*!<  */
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)        /*!<  */
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)        /*!<  */
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)        /*!<  */
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)        /*!<  */
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)        /*!<  */
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)        /*!<  */
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)        /*!<  */
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)        /*!<  */
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)        /*!<  */
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)        /*!<  */
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)        /*!<  */
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)        /*!<  */
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)        /*!<  */
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)        /*!<  */
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)        /*!<  */
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)        /*!<  */
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)        /*!<  */
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)        /*!<  */
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)        /*!<  */
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)        /*!<  */
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)        /*!<  */
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)        /*!<  */
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)        /*!<  */
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)        /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)        /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)        /*!<  */
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)        /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)        /*!<  */
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)        /*!<  */
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)        /*!<  */
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)        /*!<  */
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)        /*!<  */
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)        /*!<  */
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CAL_CALP                         ((uint32_t)0x00008000)        /*!<  */
-#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)        /*!<  */
-#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)        /*!<  */
-#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)        /*!<  */
-#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)        /*!<  */
-#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)        /*!<  */
-#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)        /*!<  */
-#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)        /*!<  */
-#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)        /*!<  */
-#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)        /*!<  */
-#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)        /*!<  */
-#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)        /*!<  */
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP2MF                   ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE              ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TAMPCR_TAMP2IE                   ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TAMPCR_TAMP1MF                   ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE              ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TAMPCR_TAMP1IE                   ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS                 ((uint32_t)0x00008000)        /*!<  */
-#define RTC_TAMPCR_TAMPPRCH                  ((uint32_t)0x00006000)        /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0                ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_1                ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TAMPCR_TAMPFLT                   ((uint32_t)0x00001800)        /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0                 ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TAMPCR_TAMPFLT_1                 ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TAMPCR_TAMPFREQ                  ((uint32_t)0x00000700)        /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0                ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_1                ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_2                ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TAMPCR_TAMPTS                    ((uint32_t)0x00000080)        /*!<  */
-#define RTC_TAMPCR_TAMP2TRG                  ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TAMPCR_TAMP2E                    ((uint32_t)0x00000008)        /*!<  */
-#define RTC_TAMPCR_TAMPIE                    ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TAMPCR_TAMP1TRG                  ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TAMPCR_TAMP1E                    ((uint32_t)0x00000001)        /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP                       ((uint32_t)0x00000002)        /*!<  */
-#define RTC_OR_ALARMOUTTYPE                  ((uint32_t)0x00000001)        /*!<  */
-
-/* Bit names aliases maintained for legacy */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!< Clock Phase */
-#define SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!< Clock Polarity */
-#define SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!< Master Selection */
-#define SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!< Bit 0 */
-#define SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!< Bit 1 */
-#define SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!< Bit 2 */
-#define SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!< Frame Format */
-#define SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!< Internal slave select */
-#define SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!< Software slave management */
-#define SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!< Receive only */
-#define SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)            /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)            /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE                        ((uint32_t)0x00000004)            /*!< SS Output Enable */
-#define SPI_CR2_FRF                         ((uint32_t)0x00000010)            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE                       ((uint32_t)0x00000020)            /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)            /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE                       ((uint32_t)0x00000080)            /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE                         ((uint32_t)0x00000001)            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE                          ((uint32_t)0x00000002)            /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE                       ((uint32_t)0x00000004)            /*!< Channel side */
-#define SPI_SR_UDR                          ((uint32_t)0x00000008)            /*!< Underrun flag */
-#define SPI_SR_CRCERR                       ((uint32_t)0x00000010)            /*!< CRC Error flag */
-#define SPI_SR_MODF                         ((uint32_t)0x00000020)            /*!< Mode fault */
-#define SPI_SR_OVR                          ((uint32_t)0x00000040)            /*!< Overrun flag */
-#define SPI_SR_BSY                          ((uint32_t)0x00000080)            /*!< Busy flag */
-#define SPI_SR_FRE                          ((uint32_t)0x00000100)            /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
-#define SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_BOOT_MODE              ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MOD_0             ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */
-#define SYSCFG_CFGR1_BOOT_MODE_1            ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN                ((uint32_t)0x00000001) /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA                   ((uint32_t)0x0000000E) /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0                 ((uint32_t)0x00000002)
-#define SYSCFG_CFGR2_CAPA_1                 ((uint32_t)0x00000004)
-#define SYSCFG_CFGR2_CAPA_2                 ((uint32_t)0x00000008)
-#define SYSCFG_CFGR2_I2C_PB6_FMP            ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP            ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP            ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP            ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP               ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP               ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000005) /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000050) /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300) /*!< PD[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000) /*!< PC[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002) /*!< PC[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020) /*!< PC[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200) /*!< PC[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000) /*!< PC[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002) /*!< PC[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020) /*!< PC[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200) /*!< PC[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000) /*!< PC[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002) /*!< PC[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020) /*!< PC[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200) /*!< PC[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000) /*!< PC[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT               ((uint32_t)0x00000001) /*!< Vref Enable bit*/
-#define SYSCFG_CFGR3_VREF_OUT                 ((uint32_t)0x00000030) /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0               ((uint32_t)0x00000010) /*!< Bit 0 */
-#define SYSCFG_CFGR3_VREF_OUT_1               ((uint32_t)0x00000020) /*!< Bit 1 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC        ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC         ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP     ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48              ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */
-#define SYSCFG_CFGR3_VREFINT_RDYF             ((uint32_t)0x40000000) /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK                 ((uint32_t)0x80000000) /*!< CFGR3 lock bit */
-
-/* Bit names aliases maintained for legacy */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_REF_HSI48_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_ADC_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN                         ((uint32_t)0x00000001)            /*!<Counter enable */
-#define TIM_CR1_UDIS                        ((uint32_t)0x00000002)            /*!<Update disable */
-#define TIM_CR1_URS                         ((uint32_t)0x00000004)            /*!<Update request source */
-#define TIM_CR1_OPM                         ((uint32_t)0x00000008)            /*!<One pulse mode */
-#define TIM_CR1_DIR                         ((uint32_t)0x00000010)            /*!<Direction */
-
-#define TIM_CR1_CMS                         ((uint32_t)0x00000060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       ((uint32_t)0x00000020)            /*!<Bit 0 */
-#define TIM_CR1_CMS_1                       ((uint32_t)0x00000040)            /*!<Bit 1 */
-
-#define TIM_CR1_ARPE                        ((uint32_t)0x00000080)            /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD                         ((uint32_t)0x00000300)            /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_CR1_CKD_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCPC                        ((uint32_t)0x00000001)            /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS                        ((uint32_t)0x00000004)            /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
-#define TIM_CR2_OIS1                        ((uint32_t)0x00000100)            /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N                       ((uint32_t)0x00000200)            /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2                        ((uint32_t)0x00000400)            /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N                       ((uint32_t)0x00000800)            /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3                        ((uint32_t)0x00001000)            /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N                       ((uint32_t)0x00002000)            /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4                        ((uint32_t)0x00004000)            /*!<Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS                        ((uint32_t)0x00000007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-
-#define TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
-#define TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE                        ((uint32_t)0x00000001)            /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE                      ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE                      ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE                      ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE                        ((uint32_t)0x00000040)            /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE                        ((uint32_t)0x00000100)            /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE                      ((uint32_t)0x00000200)            /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE                      ((uint32_t)0x00001000)            /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE                        ((uint32_t)0x00004000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF                        ((uint32_t)0x00000020)            /*!<COM interrupt Flag */
-#define TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF                          ((uint32_t)0x00000080)            /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG                          ((uint32_t)0x00000001)               /*!<Update Generation */
-#define TIM_EGR_CC1G                        ((uint32_t)0x00000002)               /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G                        ((uint32_t)0x00000004)               /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G                        ((uint32_t)0x00000008)               /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G                        ((uint32_t)0x00000010)               /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG                        ((uint32_t)0x00000020)               /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG                          ((uint32_t)0x00000040)               /*!<Trigger Generation */
-#define TIM_EGR_BG                          ((uint32_t)0x00000080)               /*!<Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M                      ((uint32_t)0x00000070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M                      ((uint32_t)0x00007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC                    ((uint32_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F                      ((uint32_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC                    ((uint32_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F                      ((uint32_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE                      ((uint32_t)0x00000040)            /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT                         ((uint32_t)0x0000FFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC                         ((uint32_t)0x0000FFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR                         ((uint32_t)0x0000FFFF)            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define TIM_RCR_REP                         ((uint32_t)0x000000FF)            /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define TIM_BDTR_DTG                        ((uint32_t)0x000000FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_BDTR_DTG_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM_BDTR_DTG_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define TIM_BDTR_DTG_3                      ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define TIM_BDTR_DTG_4                      ((uint32_t)0x00000010)            /*!<Bit 4 */
-#define TIM_BDTR_DTG_5                      ((uint32_t)0x00000020)            /*!<Bit 5 */
-#define TIM_BDTR_DTG_6                      ((uint32_t)0x00000040)            /*!<Bit 6 */
-#define TIM_BDTR_DTG_7                      ((uint32_t)0x00000080)            /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK                       ((uint32_t)0x00000300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0                     ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1                     ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI                       ((uint32_t)0x00000400)            /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR                       ((uint32_t)0x00000800)            /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE                        ((uint32_t)0x00001000)            /*!<Break enable */
-#define TIM_BDTR_BKP                        ((uint32_t)0x00002000)            /*!<Break Polarity */
-#define TIM_BDTR_AOE                        ((uint32_t)0x00004000)            /*!<Automatic Output enable */
-#define TIM_BDTR_MOE                        ((uint32_t)0x00008000)            /*!<Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA                         ((uint32_t)0x0000001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_DCR_DBA_1                       ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM_DCR_DBA_2                       ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define TIM_DCR_DBA_3                       ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define TIM_DCR_DBA_4                       ((uint32_t)0x00000010)            /*!<Bit 4 */
-
-#define TIM_DCR_DBL                         ((uint32_t)0x00001F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_DCR_DBL_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define TIM_DCR_DBL_2                       ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define TIM_DCR_DBL_3                       ((uint32_t)0x00000800)            /*!<Bit 3 */
-#define TIM_DCR_DBL_4                       ((uint32_t)0x00001000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB                       ((uint32_t)0x0000FFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP                     ((uint32_t)0x00000007)            /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0                   ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM2_OR_ETR_RMP_1                   ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM2_OR_ETR_RMP_2                   ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define TIM2_OR_TI4_RMP                     ((uint32_t)0x0000018)             /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0                   ((uint32_t)0x00000008)            /*!<Bit 0 */
-#define TIM2_OR_TI4_RMP_1                   ((uint32_t)0x00000010)            /*!<Bit 1 */
-
-#define TIM21_OR_ETR_RMP                    ((uint32_t)0x00000003)            /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM21_OR_ETR_RMP_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP                    ((uint32_t)0x0000001C)            /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define TIM21_OR_TI1_RMP_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP_2                  ((uint32_t)0x00000010)            /*!<Bit 2 */
-#define TIM21_OR_TI2_RMP                    ((uint32_t)0x00000020)            /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP                    ((uint32_t)0x00000003)            /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM22_OR_ETR_RMP_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM22_OR_TI1_RMP                    ((uint32_t)0x0000000C)            /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define TIM22_OR_TI1_RMP_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE                         ((uint32_t)0x00000001)            /*!<Touch sensing controller enable */
-#define TSC_CR_START                        ((uint32_t)0x00000002)            /*!<Start acquisition */
-#define TSC_CR_AM                           ((uint32_t)0x00000004)            /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL                      ((uint32_t)0x00000008)            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF                        ((uint32_t)0x00000010)            /*!<IO default mode */
-
-#define TSC_CR_MCV                          ((uint32_t)0x000000E0)            /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0                        ((uint32_t)0x00000020)            /*!<Bit 0 */
-#define TSC_CR_MCV_1                        ((uint32_t)0x00000040)            /*!<Bit 1 */
-#define TSC_CR_MCV_2                        ((uint32_t)0x00000080)            /*!<Bit 2 */
-
-#define TSC_CR_PGPSC                        ((uint32_t)0x00007000)            /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0                      ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TSC_CR_PGPSC_1                      ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TSC_CR_PGPSC_2                      ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define TSC_CR_SSPSC                        ((uint32_t)0x00008000)            /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE                          ((uint32_t)0x00010000)            /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD                          ((uint32_t)0x00FE0000)            /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0                        ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define TSC_CR_SSD_1                        ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define TSC_CR_SSD_2                        ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define TSC_CR_SSD_3                        ((uint32_t)0x00100000)            /*!<Bit 3 */
-#define TSC_CR_SSD_4                        ((uint32_t)0x00200000)            /*!<Bit 4 */
-#define TSC_CR_SSD_5                        ((uint32_t)0x00400000)            /*!<Bit 5 */
-#define TSC_CR_SSD_6                        ((uint32_t)0x00800000)            /*!<Bit 6 */
-
-#define TSC_CR_CTPL                         ((uint32_t)0x0F000000)            /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0                       ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define TSC_CR_CTPL_1                       ((uint32_t)0x02000000)            /*!<Bit 1 */
-#define TSC_CR_CTPL_2                       ((uint32_t)0x04000000)            /*!<Bit 2 */
-#define TSC_CR_CTPL_3                       ((uint32_t)0x08000000)            /*!<Bit 3 */
-
-#define TSC_CR_CTPH                         ((uint32_t)0xF0000000)            /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0                       ((uint32_t)0x10000000)            /*!<Bit 0 */
-#define TSC_CR_CTPH_1                       ((uint32_t)0x20000000)            /*!<Bit 1 */
-#define TSC_CR_CTPH_2                       ((uint32_t)0x40000000)            /*!<Bit 2 */
-#define TSC_CR_CTPH_3                       ((uint32_t)0x80000000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE                       ((uint32_t)0x00000001)            /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE                       ((uint32_t)0x00000002)            /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC                       ((uint32_t)0x00000001)            /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC                       ((uint32_t)0x00000002)            /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF                        ((uint32_t)0x00000001)            /*!<End of acquisition flag */
-#define TSC_ISR_MCEF                        ((uint32_t)0x00000002)            /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1                   ((uint32_t)0x00000001)            /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2                   ((uint32_t)0x00000002)            /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3                   ((uint32_t)0x00000004)            /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4                   ((uint32_t)0x00000008)            /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1                   ((uint32_t)0x00000010)            /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2                   ((uint32_t)0x00000020)            /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3                   ((uint32_t)0x00000040)            /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4                   ((uint32_t)0x00000080)            /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1                   ((uint32_t)0x00000100)            /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2                   ((uint32_t)0x00000200)            /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3                   ((uint32_t)0x00000400)            /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4                   ((uint32_t)0x00000800)            /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1                   ((uint32_t)0x00001000)            /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2                   ((uint32_t)0x00002000)            /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3                   ((uint32_t)0x00004000)            /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4                   ((uint32_t)0x00008000)            /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1                   ((uint32_t)0x00010000)            /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2                   ((uint32_t)0x00020000)            /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3                   ((uint32_t)0x00040000)            /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4                   ((uint32_t)0x00080000)            /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1                   ((uint32_t)0x00100000)            /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2                   ((uint32_t)0x00200000)            /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3                   ((uint32_t)0x00400000)            /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4                   ((uint32_t)0x00800000)            /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1                   ((uint32_t)0x01000000)            /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2                   ((uint32_t)0x02000000)            /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3                   ((uint32_t)0x04000000)            /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4                   ((uint32_t)0x08000000)            /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1                   ((uint32_t)0x10000000)            /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2                   ((uint32_t)0x20000000)            /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3                   ((uint32_t)0x40000000)            /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4                   ((uint32_t)0x80000000)            /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E                      ((uint32_t)0x00000001)            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E                      ((uint32_t)0x00000002)            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E                      ((uint32_t)0x00000004)            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E                      ((uint32_t)0x00000008)            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E                      ((uint32_t)0x00000010)            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E                      ((uint32_t)0x00000020)            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E                      ((uint32_t)0x00000040)            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E                      ((uint32_t)0x00000080)            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S                      ((uint32_t)0x00010000)            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S                      ((uint32_t)0x00020000)            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S                      ((uint32_t)0x00040000)            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S                      ((uint32_t)0x00080000)            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S                      ((uint32_t)0x00100000)            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S                      ((uint32_t)0x00200000)            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S                      ((uint32_t)0x00400000)            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S                      ((uint32_t)0x00800000)            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT                      ((uint32_t)0x00003FFF)            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
-#define USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
-#define USART_CR1_M                         ((uint32_t)0x10001000)            /*!< Word length */
-#define USART_CR1_M_0                       ((uint32_t)0x00001000)            /*!< Word length - Bit 0 */
-#define USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
-#define USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
-#define USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
-#define USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
-#define USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
-#define USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
-#define USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
-#define USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
-#define USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
-#define USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
-#define USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
-#define USART_CR1_M_1                       ((uint32_t)0x10000000)            /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-#define USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-#define USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-#define USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
-#define USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
-#define USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
-#define USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
-#define USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
-#define USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
-#define USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
-#define USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
-#define USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
-#define USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
-#define USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM                     ((uint32_t)0x00800000)            /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION              ((uint32_t)0x0000000F)            /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA              ((uint32_t)0x0000FFF0)            /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC                      ((uint32_t)0x000000FF)            /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT                       ((uint32_t)0x0000FF00)            /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ                     ((uint32_t)0x00000001)            /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ                     ((uint32_t)0x00000002)            /*!< Send Break Request */
-#define USART_RQR_MMRQ                      ((uint32_t)0x00000004)            /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ                     ((uint32_t)0x00000008)            /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ                     ((uint32_t)0x00000010)            /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
-#define USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
-#define USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
-#define USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
-#define USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
-#define USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
-#define USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
-#define USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
-#define USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
-#define USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
-#define USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF                       ((uint32_t)0x00000004)            /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR                       ((uint32_t)0x000001FF)            /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR                       ((uint32_t)0x000001FF)            /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                             ((uint32_t)0x40005C00)      /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR                          ((uint32_t)0x40006000)      /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                         ((uint16_t)0x8000)          /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                      ((uint16_t)0x4000)          /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                         ((uint16_t)0x2000)          /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                        ((uint16_t)0x1000)          /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                        ((uint16_t)0x0800)          /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                       ((uint16_t)0x0400)          /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                         ((uint16_t)0x0200)          /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                        ((uint16_t)0x0100)          /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                       ((uint16_t)0x0080)          /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                         ((uint16_t)0x0010)          /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                       ((uint16_t)0x000F)          /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                        ((uint16_t)0x8000)          /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                     ((uint16_t)0x4000)          /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                        ((uint16_t)0x2000)          /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                       ((uint16_t)0x1000)          /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                       ((uint16_t)0x0800)          /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                      ((uint16_t)0x0400)          /*!< RESET Mask   */
-#define USB_CNTR_SOFM                        ((uint16_t)0x0200)          /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                       ((uint16_t)0x0100)          /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                      ((uint16_t)0x0080)          /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                    ((uint16_t)0x0020)          /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                      ((uint16_t)0x0010)          /*!< RESUME request */
-#define USB_CNTR_FSUSP                       ((uint16_t)0x0008)          /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                      ((uint16_t)0x0004)          /*!< Low-power MODE */
-#define USB_CNTR_PDWN                        ((uint16_t)0x0002)          /*!< Power DoWN */
-#define USB_CNTR_FRES                        ((uint16_t)0x0001)          /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                        ((uint16_t)0x8000)          /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                      ((uint16_t)0x0080)          /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                        ((uint16_t)0x0040)          /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                        ((uint16_t)0x0020)          /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                       ((uint16_t)0x0010)          /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                        ((uint16_t)0x0008)          /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                        ((uint16_t)0x0004)          /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                       ((uint16_t)0x0002)          /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                       ((uint16_t)0x0001)          /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                      ((uint16_t)0x00F0)          /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                   ((uint16_t)0x0008)          /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                    ((uint16_t)0x0002)          /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                     ((uint16_t)0x0001)          /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                         ((uint16_t)0x8000)          /*!< status of D+ data line */
-#define USB_FNR_RXDM                         ((uint16_t)0x4000)          /*!< status of D- data line */
-#define USB_FNR_LCK                          ((uint16_t)0x2000)          /*!< LoCKed */
-#define USB_FNR_LSOF                         ((uint16_t)0x1800)          /*!< Lost SOF */
-#define USB_FNR_FN                           ((uint16_t)0x07FF)          /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                         ((uint8_t)0x80)             /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                        ((uint8_t)0x7F)             /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                        ((uint16_t)0x8000)          /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                       ((uint16_t)0x4000)          /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                        ((uint16_t)0x3000)          /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                         ((uint16_t)0x0800)          /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                       ((uint16_t)0x0600)          /*!<  EndPoint TYPE */
-#define USB_EP_KIND                          ((uint16_t)0x0100)          /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                        ((uint16_t)0x0080)          /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                       ((uint16_t)0x0040)          /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                        ((uint16_t)0x0030)          /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                     ((uint16_t)0x000F)          /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                     ((uint16_t)0x0600)          /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                          ((uint16_t)0x0000)          /*!< EndPoint BULK */
-#define USB_EP_CONTROL                       ((uint16_t)0x0200)          /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                   ((uint16_t)0x0400)          /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                     ((uint16_t)0x0600)          /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)               /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                        ((uint16_t)0x0000)          /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                      ((uint16_t)0x0010)          /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                        ((uint16_t)0x0020)          /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                      ((uint16_t)0x0030)          /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                       ((uint16_t)0x0010)          /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                       ((uint16_t)0x0020)          /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                        ((uint16_t)0x0000)          /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                      ((uint16_t)0x1000)          /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                        ((uint16_t)0x2000)          /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                      ((uint16_t)0x3000)          /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                       ((uint16_t)0x1000)          /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                       ((uint16_t)0x2000)          /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T                           ((uint32_t)0x0000007F)      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0                          ((uint32_t)0x00000001)      /*!< Bit 0 */
-#define WWDG_CR_T1                          ((uint32_t)0x00000002)      /*!< Bit 1 */
-#define WWDG_CR_T2                          ((uint32_t)0x00000004)      /*!< Bit 2 */
-#define WWDG_CR_T3                          ((uint32_t)0x00000008)      /*!< Bit 3 */
-#define WWDG_CR_T4                          ((uint32_t)0x00000010)      /*!< Bit 4 */
-#define WWDG_CR_T5                          ((uint32_t)0x00000020)      /*!< Bit 5 */
-#define WWDG_CR_T6                          ((uint32_t)0x00000040)      /*!< Bit 6 */
-
-#define WWDG_CR_WDGA                        ((uint32_t)0x00000080)      /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W                          ((uint32_t)0x0000007F)      /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0                         ((uint32_t)0x00000001)      /*!< Bit 0 */
-#define WWDG_CFR_W1                         ((uint32_t)0x00000002)      /*!< Bit 1 */
-#define WWDG_CFR_W2                         ((uint32_t)0x00000004)      /*!< Bit 2 */
-#define WWDG_CFR_W3                         ((uint32_t)0x00000008)      /*!< Bit 3 */
-#define WWDG_CFR_W4                         ((uint32_t)0x00000010)      /*!< Bit 4 */
-#define WWDG_CFR_W5                         ((uint32_t)0x00000020)      /*!< Bit 5 */
-#define WWDG_CFR_W6                         ((uint32_t)0x00000040)      /*!< Bit 6 */
-                                                                         
-#define WWDG_CFR_WDGTB                      ((uint32_t)0x00000180)      /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0                     ((uint32_t)0x00000080)      /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1                     ((uint32_t)0x00000100)      /*!< Bit 1 */
-
-#define WWDG_CFR_EWI                        ((uint32_t)0x00000200)      /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF                        ((uint32_t)0x00000001)      /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE)  ((INSTANCE) == I2C1)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : Advanced-control timers *****************/
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM6))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)   ((INSTANCE) == TIM2)
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)    ((INSTANCE) == TIM2)
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE)  ((INSTANCE) == TIM2)
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == LPUART1))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                                  ((INSTANCE) == USART2) || \
-                                                  ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L053xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/stm32l0xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,233 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx.h
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L0xx devices.            
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx
-  * @{
-  */
-    
-#ifndef __STM32L0xx_H
-#define __STM32L0xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-   
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32L0)
-#define STM32L0
-#endif /* STM32L0 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \
- && !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
-  /* #define STM32L051xx */   /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
-  /* #define STM32L052xx */   /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
-#define STM32L053xx           /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
-  /* #define STM32L061xx */   /*!< */
-  /* #define STM32L062xx */   /*!< STM32L062K8 */
-  /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 */ 
-  /* #define STM32L071xx */   /*!< */
-  /* #define STM32L072xx */   /*!< */
-  /* #define STM32L073xx */   /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
-  /* #define STM32L081xx */   /*!< */
-  /* #define STM32L082xx */   /*!< */
-  /* #define STM32L083xx */   /*!< */ 
-#endif
-   
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V1.2.0
-  */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32L0xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32L031xx)
-  #include "stm32l031xx.h"
-#elif defined(STM32L041xx)
-  #include "stm32l041xx.h"
-#elif defined(STM32L051xx)
-  #include "stm32l051xx.h"
-#elif defined(STM32L052xx)
-  #include "stm32l052xx.h"
-#elif defined(STM32L053xx)
-  #include "stm32l053xx.h"
-#elif defined(STM32L062xx)
-  #include "stm32l062xx.h"
-#elif defined(STM32L063xx)
-  #include "stm32l063xx.h"
-#elif defined(STM32L061xx)
-  #include "stm32l061xx.h"
-#elif defined(STM32L071xx)
-  #include "stm32l071xx.h"
-#elif defined(STM32L072xx)
-  #include "stm32l072xx.h"
-#elif defined(STM32L073xx)
-  #include "stm32l073xx.h"
-#elif defined(STM32L082xx)
-  #include "stm32l082xx.h"
-#elif defined(STM32L083xx)
-  #include "stm32l083xx.h"
-#elif defined(STM32L081xx)
-  #include "stm32l081xx.h"
-#else
- #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */ 
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l0xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L0xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,469 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *-----------------------------------------------------------------------------  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-#include "hal_tick.h"
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-   
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{    
-/*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400C;
- 
-  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6;
-  
-  /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
-  
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIER = 0x00000000;
-  
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-  /* Configure the Cube driver */
-  SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
-  HAL_Init();
-
-  /* Configure the System clock source, PLL Multiplier and Divider factors,
-     AHB/APBx prescalers and Flash settings */
-  SetSysClock();
-
-  /* Reset the timer to avoid issues after the RAM initialization */
-  TIM_MST_RESET_ON;
-  TIM_MST_RESET_OFF;
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable_2[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-  // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
- 
-  /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-  // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/system_stm32l0xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.h
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L0XX_H
-#define __SYSTEM_STM32L0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L0xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L0xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L0XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/startup_stm32l053xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,332 +0,0 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
-;* File Name          : startup_stm32l053xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.2.0
-;* Date               : 06-February-2015
-;* Description        : STM32L053xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     0                              ; Reserved
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     0                              ; Reserved
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     0                              ; Reserved
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler                ; TIM21
-                DCD     0                              ; Reserved
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/TOOLCHAIN_IAR/stm32l053xx.icf	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* [ROM = 64kb = 0x10000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0800FFFF;
-
-/* [RAM = 8kb = 0x2000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x200000C0;
-define symbol __region_RAM_end__      = 0x20001FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x500;
-define symbol __size_heap__   = 0x1000;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/startup_stm32l073xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,252 +0,0 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
-;* File Name          : startup_stm32l073xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.2.0
-;* Date               : 06-February-2015
-;* Description        : STM32l073xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-                
-Stack_Mem       SPACE   Stack_Size
-__initial_sp    EQU     0x20005000 ; Top of RAM
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000400
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit    EQU (__initial_sp - Stack_Size)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  USART4_5_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-USART4_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/stm32l073xz.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
-LR_IROM1 0x08000000 0x10000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x30000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_MICRO/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/startup_stm32l073xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,225 +0,0 @@
-;******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
-;* File Name          : startup_stm32l073xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.2.0
-;* Date               : 06-February-2015
-;* Description        : STM32l073xx Devices vector table for MDK-ARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == Reset_Handler
-;*                      - Set the vector table entries with the exceptions ISR address
-;*                      - Branches to __main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;* <<< Use Configuration Wizard in Context Menu >>>   
-;*******************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-
-__initial_sp    EQU     0x20005000 ; Top of RAM
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC and CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler routine
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler                 [WEAK]
-        IMPORT  __main
-        IMPORT  SystemInit  
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                    [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler              [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                    [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler               [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler                 [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler                [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler                [WEAK]
-                EXPORT  PVD_IRQHandler                 [WEAK]
-                EXPORT  RTC_IRQHandler                 [WEAK]
-                EXPORT  FLASH_IRQHandler               [WEAK]
-                EXPORT  RCC_CRS_IRQHandler             [WEAK]
-                EXPORT  EXTI0_1_IRQHandler             [WEAK]
-                EXPORT  EXTI2_3_IRQHandler             [WEAK]
-                EXPORT  EXTI4_15_IRQHandler            [WEAK]
-                EXPORT  TSC_IRQHandler                  [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler       [WEAK]
-                EXPORT  DMA1_Channel2_3_IRQHandler     [WEAK]
-                EXPORT  DMA1_Channel4_5_6_7_IRQHandler [WEAK]
-                EXPORT  ADC1_COMP_IRQHandler           [WEAK]
-                EXPORT  LPTIM1_IRQHandler              [WEAK]
-                EXPORT  USART4_5_IRQHandler            [WEAK]
-                EXPORT  TIM2_IRQHandler                [WEAK]
-                EXPORT  TIM3_IRQHandler                [WEAK]
-                EXPORT  TIM6_DAC_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler                [WEAK]
-                EXPORT  TIM21_IRQHandler               [WEAK]
-                EXPORT  TIM22_IRQHandler               [WEAK]
-                EXPORT  I2C1_IRQHandler                [WEAK]
-                EXPORT  I2C2_IRQHandler                [WEAK]
-                EXPORT  I2C3_IRQHandler                [WEAK]
-                EXPORT  SPI1_IRQHandler                [WEAK]
-                EXPORT  SPI2_IRQHandler                [WEAK]
-                EXPORT  USART1_IRQHandler              [WEAK]
-                EXPORT  USART2_IRQHandler              [WEAK]
-                EXPORT  RNG_LPUART1_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler                 [WEAK]
-                EXPORT  USB_IRQHandler                 [WEAK]
-
-
-WWDG_IRQHandler
-PVD_IRQHandler
-RTC_IRQHandler
-FLASH_IRQHandler
-RCC_CRS_IRQHandler
-EXTI0_1_IRQHandler
-EXTI2_3_IRQHandler
-EXTI4_15_IRQHandler
-TSC_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_3_IRQHandler
-DMA1_Channel4_5_6_7_IRQHandler
-ADC1_COMP_IRQHandler 
-LPTIM1_IRQHandler
-USART4_5_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM6_DAC_IRQHandler
-TIM7_IRQHandler
-TIM21_IRQHandler
-TIM22_IRQHandler
-I2C1_IRQHandler
-I2C2_IRQHandler
-I2C3_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-RNG_LPUART1_IRQHandler
-LCD_IRQHandler
-USB_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END
-
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/stm32l073xz.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L073RZ: 192KB FLASH (0x30000) + 20KB RAM (0x5000)
-LR_IROM1 0x08000000 0x10000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x30000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0xC0) (0x5000-0xC0)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_ARM_STD/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_GCC_ARM/STM32L073XZ.ld	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 192k
-  RAM (rwx) : ORIGIN = 0x200000C0, LENGTH = 20K - 0xC0
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_GCC_ARM/startup_stm32l073xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,311 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l073xx.s
-  * @author    MCD Application Team
-  * @version   V1.2.0
-  * @date      06-February-2015
-  * @brief     STM32L073xx Devices vector table for Atollic TrueSTUDIO toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M0+ processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m0plus
-  .fpu softvfp
-  .thumb
-
-.global  g_pfnVectors
-.global  Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word  _sidata
-/* start address for the .data section. defined in linker script */
-.word  _sdata
-/* end address for the .data section. defined in linker script */
-.word  _edata
-/* start address for the .bss section. defined in linker script */
-.word  _sbss
-/* end address for the .bss section. defined in linker script */
-.word  _ebss
-
-    .section  .text.Reset_Handler
-  .weak  Reset_Handler
-  .type  Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs  r1, #0
-  b  LoopCopyDataInit
-
-CopyDataInit:
-  ldr  r3, =_sidata
-  ldr  r3, [r3, r1]
-  str  r3, [r0, r1]
-  adds  r1, r1, #4
-
-LoopCopyDataInit:
-  ldr  r0, =_sdata
-  ldr  r3, =_edata
-  adds  r2, r0, r1
-  cmp  r2, r3
-  bcc  CopyDataInit
-  ldr  r2, =_sbss
-  b  LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs  r3, #0
-  str  r3, [r2]
-  adds r2, r2, #4
-
-
-LoopFillZerobss:
-  ldr  r3, = _ebss
-  cmp  r2, r3
-  bcc  FillZerobss
-
-/* Call the clock system intitialization function.*/
-  bl  SystemInit
-/* Call static constructors */
-  //bl __libc_init_array
-/* Call the application's entry point.*/
-  //bl  main
-  bl _start
-
-LoopForever:
-  b LoopForever
-
-
-.size  Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section  .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b  Infinite_Loop
-  .size  Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M0.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section  .isr_vector,"a",%progbits
-  .type  g_pfnVectors, %object
-  .size  g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word  _estack
-  .word  Reset_Handler
-  .word  NMI_Handler
-  .word  HardFault_Handler
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  0
-  .word  SVC_Handler
-  .word  DebugMon_Handler
-  .word  0
-  .word  PendSV_Handler
-  .word  SysTick_Handler
-  .word     WWDG_IRQHandler                   /* Window WatchDog              */
-  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */
-  .word     RTC_IRQHandler                    /* RTC through the EXTI line     */
-  .word     FLASH_IRQHandler                  /* FLASH                        */
-  .word     RCC_CRS_IRQHandler                /* RCC and CRS                  */
-  .word     EXTI0_1_IRQHandler                /* EXTI Line 0 and 1            */
-  .word     EXTI2_3_IRQHandler                /* EXTI Line 2 and 3            */
-  .word     EXTI4_15_IRQHandler               /* EXTI Line 4 to 15            */
-  .word     TSC_IRQHandler                     /* TSC                           */
-  .word     DMA1_Channel1_IRQHandler          /* DMA1 Channel 1               */
-  .word     DMA1_Channel2_3_IRQHandler        /* DMA1 Channel 2 and Channel 3 */
-  .word     DMA1_Channel4_5_6_7_IRQHandler    /* DMA1 Channel 4, Channel 5, Channel 6 and Channel 7*/
-  .word     ADC1_COMP_IRQHandler              /* ADC1, COMP1 and COMP2        */
-  .word     LPTIM1_IRQHandler                 /* LPTIM1                       */
-  .word     USART4_5_IRQHandler               /* USART4 and USART 5           */
-  .word     TIM2_IRQHandler                   /* TIM2                         */
-  .word     TIM3_IRQHandler                   /* TIM3                         */
-  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC                 */
-  .word     TIM7_IRQHandler 				          /* TIM7                         */
-  .word     0              					          /* Reserved                     */
-  .word     TIM21_IRQHandler                  /* TIM21                        */
-  .word     I2C3_IRQHandler                   /* I2C3                         */
-  .word     TIM22_IRQHandler                  /* TIM22                        */
-  .word     I2C1_IRQHandler                   /* I2C1                         */
-  .word     I2C2_IRQHandler                   /* I2C2                         */
-  .word     SPI1_IRQHandler                   /* SPI1                         */
-  .word     SPI2_IRQHandler                   /* SPI2                         */
-  .word     USART1_IRQHandler                 /* USART1                       */
-  .word     USART2_IRQHandler                 /* USART2                       */
-  .word     RNG_LPUART1_IRQHandler            /* RNG and LPUART1              */
-  .word     LCD_IRQHandler                    /* LCD                          */
-  .word     USB_IRQHandler                    /* USB                          */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-   .weak      NMI_Handler
-   .thumb_set NMI_Handler,Default_Handler
-
-   .weak      HardFault_Handler
-   .thumb_set HardFault_Handler,Default_Handler
-
-   .weak      SVC_Handler
-   .thumb_set SVC_Handler,Default_Handler
-
-   .weak      DebugMon_Handler
-   .thumb_set DebugMon_Handler,Default_Handler
-
-   .weak      PendSV_Handler
-   .thumb_set PendSV_Handler,Default_Handler
-
-   .weak      SysTick_Handler
-   .thumb_set SysTick_Handler,Default_Handler
-
-   .weak      WWDG_IRQHandler
-   .thumb_set WWDG_IRQHandler,Default_Handler
-
-   .weak      PVD_IRQHandler
-   .thumb_set PVD_IRQHandler,Default_Handler
-
-   .weak      RTC_IRQHandler
-   .thumb_set RTC_IRQHandler,Default_Handler
-
-   .weak      FLASH_IRQHandler
-   .thumb_set FLASH_IRQHandler,Default_Handler
-
-   .weak      RCC_CRS_IRQHandler
-   .thumb_set RCC_CRS_IRQHandler,Default_Handler
-
-   .weak      EXTI0_1_IRQHandler
-   .thumb_set EXTI0_1_IRQHandler,Default_Handler
-
-   .weak      EXTI2_3_IRQHandler
-   .thumb_set EXTI2_3_IRQHandler,Default_Handler
-
-   .weak      EXTI4_15_IRQHandler
-   .thumb_set EXTI4_15_IRQHandler,Default_Handler
-
-   .weak      TSC_IRQHandler
-   .thumb_set TSC_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel1_IRQHandler
-   .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel2_3_IRQHandler
-   .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler
-
-   .weak      DMA1_Channel4_5_6_7_IRQHandler
-   .thumb_set DMA1_Channel4_5_6_7_IRQHandler,Default_Handler
-
-   .weak      ADC1_COMP_IRQHandler
-   .thumb_set ADC1_COMP_IRQHandler,Default_Handler
-
-   .weak      LPTIM1_IRQHandler
-   .thumb_set LPTIM1_IRQHandler,Default_Handler
-
-   .weak      USART4_5_IRQHandler
-   .thumb_set USART4_5_IRQHandler,Default_Handler
-
-   .weak      TIM2_IRQHandler
-   .thumb_set TIM2_IRQHandler,Default_Handler
-
-   .weak      TIM3_IRQHandler
-   .thumb_set TIM3_IRQHandler,Default_Handler
-
-   .weak      TIM6_DAC_IRQHandler
-   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
-
-   .weak      TIM7_IRQHandler
-   .thumb_set TIM7_IRQHandler,Default_Handler
-
-   .weak      TIM21_IRQHandler
-   .thumb_set TIM21_IRQHandler,Default_Handler
-
-   .weak      I2C3_IRQHandler
-   .thumb_set I2C3_IRQHandler,Default_Handler
-
-   .weak      TIM22_IRQHandler
-   .thumb_set TIM22_IRQHandler,Default_Handler
-
-   .weak      I2C1_IRQHandler
-   .thumb_set I2C1_IRQHandler,Default_Handler
-
-   .weak      I2C2_IRQHandler
-   .thumb_set I2C2_IRQHandler,Default_Handler
-
-   .weak      SPI1_IRQHandler
-   .thumb_set SPI1_IRQHandler,Default_Handler
-
-   .weak      SPI2_IRQHandler
-   .thumb_set SPI2_IRQHandler,Default_Handler
-
-   .weak      USART1_IRQHandler
-   .thumb_set USART1_IRQHandler,Default_Handler
-
-   .weak      USART2_IRQHandler
-   .thumb_set USART2_IRQHandler,Default_Handler
-
-   .weak      RNG_LPUART1_IRQHandler
-   .thumb_set RNG_LPUART1_IRQHandler,Default_Handler
-
-   .weak      LCD_IRQHandler
-   .thumb_set LCD_IRQHandler,Default_Handler
-
-   .weak      USB_IRQHandler
-   .thumb_set USB_IRQHandler,Default_Handler
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_IAR/startup_stm32l073xx.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,354 +0,0 @@
-;/******************** (C) COPYRIGHT 2015 STMicroelectronics ********************
-;* File Name          : startup_stm32l073xx.s
-;* Author             : MCD Application Team
-;* Version            : V1.2.0
-;* Date               : 06-February-2015
-;* Description        : STM32L073xx Ultra Low Power Devices vector 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == _iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M0+ processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;* 
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************/
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-                DCD     WWDG_IRQHandler                ; Window Watchdog
-                DCD     PVD_IRQHandler                 ; PVD through EXTI Line detect
-                DCD     RTC_IRQHandler                 ; RTC through EXTI Line
-                DCD     FLASH_IRQHandler               ; FLASH
-                DCD     RCC_CRS_IRQHandler             ; RCC_CRS
-                DCD     EXTI0_1_IRQHandler             ; EXTI Line 0 and 1
-                DCD     EXTI2_3_IRQHandler             ; EXTI Line 2 and 3
-                DCD     EXTI4_15_IRQHandler            ; EXTI Line 4 to 15
-                DCD     TSC_IRQHandler                 ; TSC
-                DCD     DMA1_Channel1_IRQHandler       ; DMA1 Channel 1
-                DCD     DMA1_Channel2_3_IRQHandler     ; DMA1 Channel 2 and Channel 3
-                DCD     DMA1_Channel4_5_6_7_IRQHandler ; DMA1 Channel 4, Channel 5, Channel 6 and Channel 7
-                DCD     ADC1_COMP_IRQHandler           ; ADC1, COMP1 and COMP2 
-                DCD     LPTIM1_IRQHandler              ; LPTIM1
-                DCD     USART4_5_IRQHandler            ; USART4 and USART5
-                DCD     TIM2_IRQHandler                ; TIM2
-                DCD     TIM3_IRQHandler                ; TIM3
-                DCD     TIM6_DAC_IRQHandler            ; TIM6 and DAC
-                DCD     TIM7_IRQHandler                ; TIM7
-                DCD     0                              ; Reserved
-                DCD     TIM21_IRQHandler               ; TIM21
-                DCD     I2C3_IRQHandler                ; I2C3
-                DCD     TIM22_IRQHandler               ; TIM22
-                DCD     I2C1_IRQHandler                ; I2C1
-                DCD     I2C2_IRQHandler                ; I2C2
-                DCD     SPI1_IRQHandler                ; SPI1
-                DCD     SPI2_IRQHandler                ; SPI2
-                DCD     USART1_IRQHandler              ; USART1
-                DCD     USART2_IRQHandler              ; USART2
-                DCD     RNG_LPUART1_IRQHandler         ; RNG and LPUART1
-                DCD     LCD_IRQHandler                 ; LCD
-                DCD     USB_IRQHandler                 ; USB
-                
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:NOROOT:REORDER(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-HardFault_Handler
-        B HardFault_Handler
-       
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-                
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-                
-        PUBWEAK RTC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RTC_IRQHandler
-        B RTC_IRQHandler
-        
-                
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-                
-        PUBWEAK RCC_CRS_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RCC_CRS_IRQHandler
-        B RCC_CRS_IRQHandler
-        
-                
-        PUBWEAK EXTI0_1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI0_1_IRQHandler
-        B EXTI0_1_IRQHandler
-        
-                
-        PUBWEAK EXTI2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI2_3_IRQHandler
-        B EXTI2_3_IRQHandler
-        
-                
-        PUBWEAK EXTI4_15_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-EXTI4_15_IRQHandler
-        B EXTI4_15_IRQHandler
-        
-                
-        PUBWEAK TSC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TSC_IRQHandler
-        B TSC_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel2_3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel2_3_IRQHandler
-        B DMA1_Channel2_3_IRQHandler
-        
-                
-        PUBWEAK DMA1_Channel4_5_6_7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-DMA1_Channel4_5_6_7_IRQHandler
-        B DMA1_Channel4_5_6_7_IRQHandler
-        
-                
-        PUBWEAK ADC1_COMP_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-ADC1_COMP_IRQHandler
-        B ADC1_COMP_IRQHandler
-        
-                 
-        PUBWEAK LPTIM1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LPTIM1_IRQHandler
-        B LPTIM1_IRQHandler
-        
-                 
-        PUBWEAK USART4_5_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART4_5_IRQHandler
-        B USART4_5_IRQHandler
-        
-                
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-                
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-                
-        PUBWEAK TIM6_DAC_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM6_DAC_IRQHandler
-        B TIM6_DAC_IRQHandler
-                
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-        
-        PUBWEAK TIM21_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM21_IRQHandler
-        B TIM21_IRQHandler
-
-        PUBWEAK I2C3_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C3_IRQHandler
-        B I2C3_IRQHandler
-
-        PUBWEAK TIM22_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-TIM22_IRQHandler
-        B TIM22_IRQHandler
-        
-
-        PUBWEAK I2C1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C1_IRQHandler
-        B I2C1_IRQHandler
-        
-                
-        PUBWEAK I2C2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-I2C2_IRQHandler
-        B I2C2_IRQHandler
-        
-                
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-                
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-                
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-                
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-
-        PUBWEAK RNG_LPUART1_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-RNG_LPUART1_IRQHandler
-        B RNG_LPUART1_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-
-        PUBWEAK USB_IRQHandler
-        SECTION .text:CODE:NOROOT:REORDER(1)
-USB_IRQHandler
-        B USB_IRQHandler
-        
-        END
-;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/TOOLCHAIN_IAR/stm32l073xx.icf	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* [ROM = 192kb = 0x30000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0802FFFF;
-
-/* [RAM = 20kb = 0x5000] Vector table dynamic copy: 48 vectors = 192 bytes (0xC0) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x200000BF; /* Aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x200000C0;
-define symbol __region_RAM_end__      = 0x20004FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x500;
-define symbol __size_heap__   = 0x1000;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/cmsis.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32l0xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/cmsis_nvic.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    uint32_t *vectors = (uint32_t *)SCB->VTOR;
-    uint32_t i;
-
-    // Copy and switch to dynamic vectors if the first time called
-    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = vectors;
-        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
-    }
-    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/cmsis_nvic.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,54 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 32 vectors = 128 bytes from 0x40 to 0xBF
-// Total: 48 vectors = 192 bytes (0xC0) to be reserved in RAM
-#define NVIC_NUM_VECTORS      48
-#define NVIC_USER_IRQ_OFFSET  16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/hal_tick.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,145 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.c
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-#include "hal_tick.h"
-
-TIM_HandleTypeDef TimMasterHandle;
-uint32_t PreviousVal = 0;
-
-void us_ticker_irq_handler(void);
-void set_compare(uint16_t count);
-
-extern volatile uint32_t SlaveCounter;
-extern volatile uint32_t oc_int_part;
-extern volatile uint16_t oc_rem_part;
-
-void timer_irq_handler(void) {
-    uint16_t cval = TIM_MST->CNT;
-
-    TimMasterHandle.Instance = TIM_MST;
-
-    // Clear Update interrupt flag
-    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE) == SET) {
-        __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_UPDATE);
-        SlaveCounter++;
-    }
-
-    // Channel 1 for mbed timeout
-    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
-        __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
-        if (oc_rem_part > 0) {
-            set_compare(oc_rem_part); // Finish the remaining time left
-            oc_rem_part = 0;
-        } else {
-            if (oc_int_part > 0) {
-                set_compare(0xFFFF);
-                oc_rem_part = cval; // To finish the counter loop the next time
-                oc_int_part--;
-            } else {
-                us_ticker_irq_handler();
-            }
-        }
-    }
-
-    // Channel 2 for HAL tick
-    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC2) == SET) {
-        __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC2);
-        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
-        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
-            // Increment HAL variable
-            HAL_IncTick();
-            // Prepare next interrupt
-            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
-            PreviousVal = val;
-        }
-    }
-}
-
-// Reconfigure the HAL tick using a standard timer instead of systick.
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
-    // Enable timer clock
-    TIM_MST_RCC;
-
-    // Reset timer
-    TIM_MST_RESET_ON;
-    TIM_MST_RESET_OFF;
-
-    // Update the SystemCoreClock variable
-    SystemCoreClockUpdate();
-
-    // Configure time base
-    TimMasterHandle.Instance = TIM_MST;
-    TimMasterHandle.Init.Period        = 0xFFFFFFFF;
-    TimMasterHandle.Init.Prescaler     = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
-    TimMasterHandle.Init.ClockDivision = 0;
-    TimMasterHandle.Init.CounterMode   = TIM_COUNTERMODE_UP;
-    HAL_TIM_Base_Init(&TimMasterHandle);
-
-    // Configure output compare channel 1 for mbed timeout (enabled later when used)
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
-
-    // Configure output compare channel 2 for HAL tick
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
-    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
-    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
-
-    // Configure interrupts
-    // Update interrupt used for 32-bit counter
-    // Output compare channel 1 interrupt for mbed timeout
-    // Output compare channel 2 interrupt for HAL tick
-    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
-    NVIC_EnableIRQ(TIM_MST_IRQ);
-
-    // Enable interrupts
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_UPDATE); // For 32-bit counter
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2); // For HAL tick
-
-    // Enable timer
-    HAL_TIM_Base_Start(&TimMasterHandle);
-
-    return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/hal_tick.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.h
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32l0xx.h"
-#include "cmsis_nvic.h"
-   
-#define TIM_MST      TIM21
-#define TIM_MST_IRQ  TIM21_IRQn
-#define TIM_MST_RCC  __TIM21_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON   __TIM21_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM21_RELEASE_RESET()
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l073xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,4381 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l073xx.h
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for stm32l073xx devices.  
-  *          
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral's registers hardware
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l073xx
-  * @{
-  */
-    
-#ifndef __STM32L073xx_H
-#define __STM32L073xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-/** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals 
-  */
-#define __CM0PLUS_REV             0 /*!< Core Revision r0p0                            */
-#define __MPU_PRESENT             1 /*!< STM32L0xx  provides an MPU                    */
-#define __VTOR_PRESENT            1 /*!< Vector  Table  Register supported             */
-#define __NVIC_PRIO_BITS          2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
-#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used  */
-
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-   
-/**
- * @brief stm32l073xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
-/*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M0 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  HardFault_IRQn              = -13,    /*!< 3 Cortex-M0+ Hard Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M0+ SV Call Interrupt                         */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M0+ Pend SV Interrupt                         */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M0+ System Tick Interrupt                     */
-
-/******  STM32L-0 specific Interrupt Numbers *********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detect Interrupt                  */
-  RTC_IRQn                    = 2,      /*!< RTC through EXTI Line Interrupt                         */
-  FLASH_IRQn                  = 3,      /*!< FLASH Interrupt                                         */
-  RCC_CRS_IRQn                = 4,      /*!< RCC and CRS Interrupts                                  */
-  EXTI0_1_IRQn                = 5,      /*!< EXTI Line 0 and 1 Interrupts                            */
-  EXTI2_3_IRQn                = 6,      /*!< EXTI Line 2 and 3 Interrupts                            */
-  EXTI4_15_IRQn               = 7,      /*!< EXTI Line 4 to 15 Interrupts                            */
-  TSC_IRQn                    = 8,      /*!< TSC Interrupt                                           */
-  DMA1_Channel1_IRQn          = 9,      /*!< DMA1 Channel 1 Interrupt                                */
-  DMA1_Channel2_3_IRQn        = 10,     /*!< DMA1 Channel 2 and Channel 3 Interrupts                 */
-  DMA1_Channel4_5_6_7_IRQn    = 11,     /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
-  ADC1_COMP_IRQn              = 12,     /*!< ADC1, COMP1 and COMP2 Interrupts                        */
-  LPTIM1_IRQn                 = 13,     /*!< LPTIM1 Interrupt                                        */
-  USART4_5_IRQn               = 14,     /*!< USART4 and USART5 Interrupt                             */
-  TIM2_IRQn                   = 15,     /*!< TIM2 Interrupt                                          */
-  TIM3_IRQn                   = 16,     /*!< TIM3 Interrupt                                          */
-  TIM6_DAC_IRQn               = 17,     /*!< TIM6 and DAC Interrupts                                 */
-  TIM7_IRQn                   = 18,     /*!< TIM7 Interrupt                                          */
-  TIM21_IRQn                  = 20,     /*!< TIM21 Interrupt                                         */
-  I2C3_IRQn                   = 21,     /*!< I2C3 Interrupt                                          */
-  TIM22_IRQn                  = 22,     /*!< TIM22 Interrupt                                         */
-  I2C1_IRQn                   = 23,     /*!< I2C1 Interrupt                                          */
-  I2C2_IRQn                   = 24,     /*!< I2C2 Interrupt                                          */
-  SPI1_IRQn                   = 25,     /*!< SPI1 Interrupt                                          */
-  SPI2_IRQn                   = 26,     /*!< SPI2 Interrupt                                          */
-  USART1_IRQn                 = 27,     /*!< USART1 Interrupt                                        */
-  USART2_IRQn                 = 28,     /*!< USART2 Interrupt                                        */
-  RNG_LPUART1_IRQn            = 29,     /*!< RNG and LPUART1 Interrupts                              */
-  LCD_IRQn                    = 30,     /*!< LCD Interrupt                                           */
-  USB_IRQn                    = 31,     /*!< USB global Interrupt                                    */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm0plus.h"
-#include "system_stm32l0xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter  
-  */
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< ADC Interrupt and Status register,                          Address offset:0x00 */
-  __IO uint32_t IER;          /*!< ADC Interrupt Enable register,                              Address offset:0x04 */
-  __IO uint32_t CR;           /*!< ADC Control register,                                       Address offset:0x08 */
-  __IO uint32_t CFGR1;        /*!< ADC Configuration register 1,                               Address offset:0x0C */
-  __IO uint32_t CFGR2;        /*!< ADC Configuration register 2,                               Address offset:0x10 */
-  __IO uint32_t SMPR;         /*!< ADC Sampling time register,                                 Address offset:0x14 */
-  uint32_t   RESERVED1;       /*!< Reserved,                                                                  0x18 */
-  uint32_t   RESERVED2;       /*!< Reserved,                                                                  0x1C */
-  __IO uint32_t TR;           /*!< ADC watchdog threshold register,                            Address offset:0x20 */
-  uint32_t   RESERVED3;       /*!< Reserved,                                                                  0x24 */
-  __IO uint32_t CHSELR;       /*!< ADC channel selection register,                             Address offset:0x28 */
-  uint32_t   RESERVED4[5];    /*!< Reserved,                                                                  0x2C */
-  __IO uint32_t DR;           /*!< ADC data register,                                          Address offset:0x40 */
-  uint32_t   RESERVED5[28];   /*!< Reserved,                                                           0x44 - 0xB0 */
-  __IO uint32_t CALFACT;      /*!< ADC data register,                                          Address offset:0xB4 */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CCR;
-} ADC_Common_TypeDef;
-
-
-/**
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;     /*!< COMP comparator control and status register, Address offset: 0x18 */
-} COMP_TypeDef;
-
-
-/** 
-  * @brief CRC calculation unit 
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;          /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t  IDR;        /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;          /*!< CRC Control register,                        Address offset: 0x08 */
-  uint32_t      RESERVED2;   /*!< Reserved,                                                    0x0C */
-  __IO uint32_t INIT;        /*!< Initial CRC value register,                  Address offset: 0x10 */
-  __IO uint32_t POL;         /*!< CRC polynomial register,                     Address offset: 0x14 */
-} CRC_TypeDef;
-
-/**
-  * @brief Clock Recovery System 
-  */
-
-typedef struct 
-{
-__IO uint32_t CR;     /*!< CRS ccontrol register,              Address offset: 0x00 */
-__IO uint32_t CFGR;   /*!< CRS configuration register,         Address offset: 0x04 */
-__IO uint32_t ISR;    /*!< CRS interrupt and status register,  Address offset: 0x08 */
-__IO uint32_t ICR;    /*!< CRS interrupt flag clear register,  Address offset: 0x0C */
-} CRS_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< DAC control register,                                    Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;       /*!< DAC software trigger register,                           Address offset: 0x04 */
-  __IO uint32_t DHR12R1;       /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
-  __IO uint32_t DHR12L1;       /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
-  __IO uint32_t DHR8R1;        /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
-  __IO uint32_t DHR12R2;       /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
-  __IO uint32_t DHR12L2;       /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
-  __IO uint32_t DHR8R2;        /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
-  __IO uint32_t DHR12RD;       /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
-  __IO uint32_t DHR12LD;       /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
-  __IO uint32_t DHR8RD;        /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
-  __IO uint32_t DOR1;          /*!< DAC channel1 data output register,                       Address offset: 0x2C */
-  __IO uint32_t DOR2;          /*!< DAC channel2 data output register,                       Address offset: 0x30 */
-  __IO uint32_t SR;            /*!< DAC status register,                                     Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;                                                                  
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t CSELR;        /*!< DMA channel selection register,              Address offset: 0xA8 */
-} DMA_Request_TypeDef;                                                          
-                                                                                
-/**                                                                             
-  * @brief External Interrupt/Event Controller                                  
-  */                                                                            
-                                                                                
-typedef struct                                                                  
-{                                                                               
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-}EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;           /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;          /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;        /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;        /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;       /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;       /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;            /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OPTR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR;          /*!< Write protection register,                   Address offset: 0x20 */
-  __IO uint32_t RESERVED1[23]; /*!< Reserved1,                                   Address offset: 0x24 */
-  __IO uint32_t WRPR2;         /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;               /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;              /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;             /*!< write protection Bytes 0 and 1          Address offset: 0x08 */
-  __IO uint32_t WRP23;             /*!< write protection Bytes 2 and 3          Address offset: 0x0C */
-  __IO uint32_t WRP45;             /*!< write protection Bytes 4 and 5          Address offset: 0x10 */
-} OB_TypeDef;
-  
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00 */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04 */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08 */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10 */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14 */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18 */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28 */
-}GPIO_TypeDef;
-
-/** 
-  * @brief LPTIMIMER
-  */
-typedef struct
-{
-  __IO uint32_t ISR;      /*!< LPTIM Interrupt and Status register,             Address offset: 0x00 */
-  __IO uint32_t ICR;      /*!< LPTIM Interrupt Clear register,                  Address offset: 0x04 */
-  __IO uint32_t IER;      /*!< LPTIM Interrupt Enable register,                 Address offset: 0x08 */
-  __IO uint32_t CFGR;     /*!< LPTIM Configuration register,                    Address offset: 0x0C */
-  __IO uint32_t CR;       /*!< LPTIM Control register,                          Address offset: 0x10 */
-  __IO uint32_t CMP;      /*!< LPTIM Compare register,                          Address offset: 0x14 */
-  __IO uint32_t ARR;      /*!< LPTIM Autoreload register,                       Address offset: 0x18 */
-  __IO uint32_t CNT;      /*!< LPTIM Counter register,                          Address offset: 0x1C */
-} LPTIM_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t CFGR1;         /*!< SYSCFG configuration register 1,                    Address offset: 0x00 */
-  __IO uint32_t CFGR2;         /*!< SYSCFG configuration register 2,                    Address offset: 0x04 */
-  __IO uint32_t EXTICR[4];     /*!< SYSCFG external interrupt configuration register,   Address offset: 0x14-0x08 */
-       uint32_t RESERVED[2];   /*!< Reserved,                                           0x18-0x1C */
-  __IO uint32_t CFGR3;         /*!< SYSCFG configuration register 3,                    Address offset: 0x20 */       
-} SYSCFG_TypeDef;
-
-
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< I2C Control register 1,            Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< I2C Control register 2,            Address offset: 0x04 */
-  __IO uint32_t OAR1;     /*!< I2C Own address 1 register,        Address offset: 0x08 */
-  __IO uint32_t OAR2;     /*!< I2C Own address 2 register,        Address offset: 0x0C */
-  __IO uint32_t TIMINGR;  /*!< I2C Timing register,               Address offset: 0x10 */
-  __IO uint32_t TIMEOUTR; /*!< I2C Timeout register,              Address offset: 0x14 */
-  __IO uint32_t ISR;      /*!< I2C Interrupt and status register, Address offset: 0x18 */
-  __IO uint32_t ICR;      /*!< I2C Interrupt clear register,      Address offset: 0x1C */
-  __IO uint32_t PECR;     /*!< I2C PEC register,                  Address offset: 0x20 */
-  __IO uint32_t RXDR;     /*!< I2C Receive data register,         Address offset: 0x24 */
-  __IO uint32_t TXDR;     /*!< I2C Transmit data register,        Address offset: 0x28 */
-}I2C_TypeDef;
-
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
-  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
-  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
-  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
-  __IO uint32_t WINR; /*!< IWDG Window register,    Address offset: 0x10 */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,              Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,        Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,               Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                          Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief MIFARE Firewall
-  */
-
-typedef struct
-{
-  __IO uint32_t CSSA;     /*!< Code Segment Start Address register,               Address offset: 0x00 */
-  __IO uint32_t CSL;      /*!< Code Segment Length register,                      Address offset: 0x04 */
-  __IO uint32_t NVDSSA;   /*!< NON volatile data Segment Start Address register,  Address offset: 0x08 */
-  __IO uint32_t NVDSL;    /*!< NON volatile data Segment Length register,         Address offset: 0x0C */
-  __IO uint32_t VDSSA ;   /*!< Volatile data Segment Start Address register,      Address offset: 0x10 */
-  __IO uint32_t VDSL ;    /*!< Volatile data Segment Length register,             Address offset: 0x14 */
-  __IO uint32_t LSSA ;    /*!< Library Segment Start Address register,            Address offset: 0x18 */
-  __IO uint32_t LSL ;     /*!< Library Segment Length register,                   Address offset: 0x1C */
-  __IO uint32_t CR ;      /*!< Configuration  register,                           Address offset: 0x20 */
- 
-} FW_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CRRCR;         /*!< RCC Clock recovery RC register,                               Address offset: 0x08 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x0C */
-  __IO uint32_t CIER;          /*!< RCC Clock interrupt enable register,                          Address offset: 0x10 */
-  __IO uint32_t CIFR;          /*!< RCC Clock interrupt flag register,                            Address offset: 0x14 */
-  __IO uint32_t CICR;          /*!< RCC Clock interrupt clear register,                           Address offset: 0x18 */
-  __IO uint32_t IOPRSTR;       /*!< RCC IO port reset register,                                   Address offset: 0x1C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x20 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x24 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x28 */
-  __IO uint32_t IOPENR;        /*!< RCC Clock IO port enable register,                            Address offset: 0x2C */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x30 */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral enable register,                          Address offset: 0x34 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral enable register,                          Address offset: 0x38 */
-  __IO uint32_t IOPSMENR;      /*!< RCC IO port clock enable in sleep mode register,              Address offset: 0x3C */
-  __IO uint32_t AHBSMENR;      /*!< RCC AHB peripheral clock enable in sleep mode register,       Address offset: 0x40 */
-  __IO uint32_t APB2SMENR;     /*!< RCC APB2 peripheral clock enable in sleep mode register,      Address offset: 0x44 */
-  __IO uint32_t APB1SMENR;     /*!< RCC APB1 peripheral clock enable in sleep mode register,      Address offset: 0x48 */
-  __IO uint32_t CCIPR;         /*!< RCC clock configuration register,                             Address offset: 0x4C */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x50 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Random numbers generator
-  */
-typedef struct 
-{
-  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
-  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
-  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
-} RNG_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-       uint32_t RESERVED;   /*!< Reserved,                                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RTC calibration register,                                  Address offset: 0x3C */
-  __IO uint32_t TAMPCR;     /*!< RTC tamper configuration register,                         Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  __IO uint32_t OR;         /*!< RTC option register,                                       Address offset  0x4C */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-} RTC_TypeDef;
-
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-  
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< SPI Control register 1 (not used in I2S mode),       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< SPI Control register 2,                              Address offset: 0x04 */
-  __IO uint32_t SR;       /*!< SPI Status register,                                 Address offset: 0x08 */
-  __IO uint32_t DR;       /*!< SPI data register,                                   Address offset: 0x0C */
-  __IO uint32_t CRCPR;    /*!< SPI CRC polynomial register (not used in I2S mode),  Address offset: 0x10 */
-  __IO uint32_t RXCRCR;   /*!< SPI Rx CRC register (not used in I2S mode),          Address offset: 0x14 */
-  __IO uint32_t TXCRCR;   /*!< SPI Tx CRC register (not used in I2S mode),          Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;  /*!< SPI_I2S configuration register,                      Address offset: 0x1C */
-  __IO uint32_t I2SPR;    /*!< SPI_I2S prescaler register,                          Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;      /*!< TIM control register 1,                       Address offset: 0x00 */
-  __IO uint32_t CR2;      /*!< TIM control register 2,                       Address offset: 0x04 */
-  __IO uint32_t SMCR;     /*!< TIM slave Mode Control register,              Address offset: 0x08 */
-  __IO uint32_t DIER;     /*!< TIM DMA/interrupt enable register,            Address offset: 0x0C */
-  __IO uint32_t SR;       /*!< TIM status register,                          Address offset: 0x10 */
-  __IO uint32_t EGR;      /*!< TIM event generation register,                Address offset: 0x14 */
-  __IO uint32_t CCMR1;    /*!< TIM  capture/compare mode register 1,         Address offset: 0x18 */
-  __IO uint32_t CCMR2;    /*!< TIM  capture/compare mode register 2,         Address offset: 0x1C */
-  __IO uint32_t CCER;     /*!< TIM capture/compare enable register,          Address offset: 0x20 */
-  __IO uint32_t CNT;      /*!< TIM counter register,                         Address offset: 0x24 */
-  __IO uint32_t PSC;      /*!< TIM prescaler register,                       Address offset: 0x28 */
-  __IO uint32_t ARR;      /*!< TIM auto-reload register,                     Address offset: 0x2C */
-  __IO uint32_t RCR;      /*!< TIM  repetition counter register,             Address offset: 0x30 */
-  __IO uint32_t CCR1;     /*!< TIM capture/compare register 1,               Address offset: 0x34 */
-  __IO uint32_t CCR2;     /*!< TIM capture/compare register 2,               Address offset: 0x38 */
-  __IO uint32_t CCR3;     /*!< TIM capture/compare register 3,               Address offset: 0x3C */
-  __IO uint32_t CCR4;     /*!< TIM capture/compare register 4,               Address offset: 0x40 */
-  __IO uint32_t BDTR;     /*!< TIM break and dead-time register,             Address offset: 0x44 */
-  __IO uint32_t DCR;      /*!< TIM DMA control register,                     Address offset: 0x48 */
-  __IO uint32_t DMAR;     /*!< TIM DMA address for full transfer register,   Address offset: 0x4C */
-  __IO uint32_t OR;       /*!< TIM option register,                          Address offset: 0x50 */
-} TIM_TypeDef;
-
-/**
-  * @brief Touch Sensing Controller (TSC)
-  */
-typedef struct
-{
-  __IO uint32_t CR;            /*!< TSC control register,                     Address offset: 0x00 */
-  __IO uint32_t IER;           /*!< TSC interrupt enable register,            Address offset: 0x04 */
-  __IO uint32_t ICR;           /*!< TSC interrupt clear register,             Address offset: 0x08 */
-  __IO uint32_t ISR;           /*!< TSC interrupt status register,            Address offset: 0x0C */
-  __IO uint32_t IOHCR;         /*!< TSC I/O hysteresis control register,      Address offset: 0x10 */
-  uint32_t      RESERVED1;     /*!< Reserved,                                 Address offset: 0x14 */
-  __IO uint32_t IOASCR;        /*!< TSC I/O analog switch control register,   Address offset: 0x18 */
-  uint32_t      RESERVED2;     /*!< Reserved,                                 Address offset: 0x1C */
-  __IO uint32_t IOSCR;         /*!< TSC I/O sampling control register,        Address offset: 0x20 */
-  uint32_t      RESERVED3;     /*!< Reserved,                                 Address offset: 0x24 */
-  __IO uint32_t IOCCR;         /*!< TSC I/O channel control register,         Address offset: 0x28 */
-  uint32_t      RESERVED4;     /*!< Reserved,                                 Address offset: 0x2C */
-  __IO uint32_t IOGCSR;        /*!< TSC I/O group control status register,    Address offset: 0x30 */
-  __IO uint32_t IOGXCR[8];     /*!< TSC I/O group x counter register,         Address offset: 0x34-50 */
-} TSC_TypeDef;
-
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
-  
-typedef struct
-{
-  __IO uint32_t CR1;    /*!< USART Control register 1,                 Address offset: 0x00 */ 
-  __IO uint32_t CR2;    /*!< USART Control register 2,                 Address offset: 0x04 */ 
-  __IO uint32_t CR3;    /*!< USART Control register 3,                 Address offset: 0x08 */
-  __IO uint32_t BRR;    /*!< USART Baud rate register,                 Address offset: 0x0C */  
-  __IO uint32_t GTPR;   /*!< USART Guard time and prescaler register,  Address offset: 0x10 */
-  __IO uint32_t RTOR;   /*!< USART Receiver Time Out register,         Address offset: 0x14 */  
-  __IO uint32_t RQR;    /*!< USART Request register,                   Address offset: 0x18 */
-  __IO uint32_t ISR;    /*!< USART Interrupt and status register,      Address offset: 0x1C */
-  __IO uint32_t ICR;    /*!< USART Interrupt flag Clear register,      Address offset: 0x20 */
-  __IO uint32_t RDR;    /*!< USART Receive Data register,              Address offset: 0x24 */
-  __IO uint32_t TDR;    /*!< USART Transmit Data register,             Address offset: 0x28 */
-} USART_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-  __IO uint16_t LPMCSR;          /*!< LPM Control and Status register,        Address offset: 0x54 */
-  __IO uint16_t RESERVEDD;       /*!< Reserved */       
-  __IO uint16_t BCDR;            /*!< Battery Charging detector register,     Address offset: 0x58 */
-  __IO uint16_t RESERVEDE;       /*!< Reserved */       
-} USB_TypeDef;
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE             ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
-#define FLASH_BANK2_BASE       ((uint32_t)0x08018000) /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END        ((uint32_t)0x08017FFF) /*!< Program end FLASH BANK1 address */
-#define FLASH_BANK2_END        ((uint32_t)0x0802FFFF) /*!< Program end FLASH BANK2 address */
-#define DATA_EEPROM_BASE       ((uint32_t)0x08080000) /*!< DATA_EEPROM base address in the alias region */
-#define DATA_EEPROM_BANK2_BASE ((uint32_t)0x08080C00) /*!< DATA EEPROM BANK2 base address in the alias region */
-#define DATA_EEPROM_BANK1_END  ((uint32_t)0x08080BFF) /*!< Program end DATA EEPROM BANK1 address */
-#define DATA_EEPROM_BANK2_END  ((uint32_t)0x080817FF) /*!< Program end DATA EEPROM BANK2 address */
-#define SRAM_BASE              ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
-#define PERIPH_BASE            ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
-
-/*!< Peripheral memory map */
-#define APBPERIPH_BASE        PERIPH_BASE
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
-#define IOPPERIPH_BASE        (PERIPH_BASE + 0x10000000)
-
-#define TIM2_BASE             (APBPERIPH_BASE + 0x00000000)
-#define TIM3_BASE             (APBPERIPH_BASE + 0x00000400)
-#define TIM6_BASE             (APBPERIPH_BASE + 0x00001000)
-#define TIM7_BASE             (APBPERIPH_BASE + 0x00001400)
-#define LCD_BASE              (APBPERIPH_BASE + 0x00002400)
-#define RTC_BASE              (APBPERIPH_BASE + 0x00002800)
-#define WWDG_BASE             (APBPERIPH_BASE + 0x00002C00)
-#define IWDG_BASE             (APBPERIPH_BASE + 0x00003000)
-#define SPI2_BASE             (APBPERIPH_BASE + 0x00003800)
-#define USART2_BASE           (APBPERIPH_BASE + 0x00004400)
-#define LPUART1_BASE          (APBPERIPH_BASE + 0x00004800)
-#define USART4_BASE           (APBPERIPH_BASE + 0x00004C00)
-#define USART5_BASE           (APBPERIPH_BASE + 0x00005000)
-#define I2C1_BASE             (APBPERIPH_BASE + 0x00005400)
-#define I2C2_BASE             (APBPERIPH_BASE + 0x00005800)
-#define CRS_BASE              (APBPERIPH_BASE + 0x00006C00)
-#define PWR_BASE              (APBPERIPH_BASE + 0x00007000)
-#define DAC_BASE              (APBPERIPH_BASE + 0x00007400)
-#define LPTIM1_BASE           (APBPERIPH_BASE + 0x00007C00)
-#define I2C3_BASE             (APBPERIPH_BASE + 0x00007800)
-
-#define SYSCFG_BASE           (APBPERIPH_BASE + 0x00010000)
-#define COMP1_BASE            (APBPERIPH_BASE + 0x00010018)
-#define COMP2_BASE            (APBPERIPH_BASE + 0x0001001C)
-#define EXTI_BASE             (APBPERIPH_BASE + 0x00010400)
-#define TIM21_BASE            (APBPERIPH_BASE + 0x00010800)
-#define TIM22_BASE            (APBPERIPH_BASE + 0x00011400)
-#define FW_BASE               (APBPERIPH_BASE + 0x00011C00)
-#define ADC1_BASE             (APBPERIPH_BASE + 0x00012400)
-#define ADC_BASE              (APBPERIPH_BASE + 0x00012708)
-#define SPI1_BASE             (APBPERIPH_BASE + 0x00013000)
-#define USART1_BASE           (APBPERIPH_BASE + 0x00013800)
-#define DBGMCU_BASE           (APBPERIPH_BASE + 0x00015800)
-
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00000000)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
-#define DMA1_CSELR_BASE       (DMA1_BASE + 0x000000A8)
-
-
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00001000)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FF80000)        /*!< FLASH Option Bytes base address */
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
-#define TSC_BASE              (AHBPERIPH_BASE + 0x00004000)
-#define RNG_BASE              (AHBPERIPH_BASE + 0x00005000)
-
-#define GPIOA_BASE            (IOPPERIPH_BASE + 0x00000000)
-#define GPIOB_BASE            (IOPPERIPH_BASE + 0x00000400)
-#define GPIOC_BASE            (IOPPERIPH_BASE + 0x00000800)
-#define GPIOD_BASE            (IOPPERIPH_BASE + 0x00000C00)
-#define GPIOE_BASE            (IOPPERIPH_BASE + 0x00001000)
-#define GPIOH_BASE            (IOPPERIPH_BASE + 0x00001C00)
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define LPUART1             ((USART_TypeDef *) LPUART1_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
-#define CRS                 ((CRS_TypeDef *) CRS_BASE)
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define LPTIM1              ((LPTIM_TypeDef *) LPTIM1_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define USART4              ((USART_TypeDef *) USART4_BASE)
-#define USART5              ((USART_TypeDef *) USART5_BASE)
-
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP1_BASE)
-#define COMP2               ((COMP_TypeDef *) COMP2_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM21               ((TIM_TypeDef *) TIM21_BASE)
-#define TIM22               ((TIM_TypeDef *) TIM22_BASE)
-#define FW                  ((FW_TypeDef *) FW_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA1_CSELR          ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
-
-
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define TSC                 ((TSC_TypeDef *) TSC_BASE)
-#define RNG                 ((RNG_TypeDef *) RNG_BASE)
-
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-
-#define USB                 ((USB_TypeDef *) USB_BASE)
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-  
-  /** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for ADC_ISR register  ******************/
-#define ADC_ISR_EOCAL                       ((uint32_t)0x00000800)     /*!< End of calibration flag */
-#define ADC_ISR_AWD                         ((uint32_t)0x00000080)     /*!< Analog watchdog flag */
-#define ADC_ISR_OVR                         ((uint32_t)0x00000010)     /*!< Overrun flag */
-#define ADC_ISR_EOSEQ                       ((uint32_t)0x00000008)     /*!< End of Sequence flag */
-#define ADC_ISR_EOC                         ((uint32_t)0x00000004)     /*!< End of Conversion */
-#define ADC_ISR_EOSMP                       ((uint32_t)0x00000002)     /*!< End of sampling flag */
-#define ADC_ISR_ADRDY                       ((uint32_t)0x00000001)     /*!< ADC Ready */
-
-/* Old EOSEQ bit definition, maintained for legacy purpose */
-#define ADC_ISR_EOS                          ADC_ISR_EOSEQ
-
-/********************  Bits definition for ADC_IER register  ******************/
-#define ADC_IER_EOCALIE                     ((uint32_t)0x00000800)     /*!< Enf Of Calibration interrupt enable */
-#define ADC_IER_AWDIE                       ((uint32_t)0x00000080)     /*!< Analog Watchdog interrupt enable */
-#define ADC_IER_OVRIE                       ((uint32_t)0x00000010)     /*!< Overrun interrupt enable */
-#define ADC_IER_EOSEQIE                     ((uint32_t)0x00000008)     /*!< End of Sequence of conversion interrupt enable */
-#define ADC_IER_EOCIE                       ((uint32_t)0x00000004)     /*!< End of Conversion interrupt enable */
-#define ADC_IER_EOSMPIE                     ((uint32_t)0x00000002)     /*!< End of sampling interrupt enable */
-#define ADC_IER_ADRDYIE                     ((uint32_t)0x00000001)     /*!< ADC Ready interrupt enable */
-
-/* Old EOSEQIE bit definition, maintained for legacy purpose */
-#define ADC_IER_EOSIE                        ADC_IER_EOSEQIE
-
-/********************  Bits definition for ADC_CR register  *******************/
-#define ADC_CR_ADCAL                        ((uint32_t)0x80000000)     /*!< ADC calibration */
-#define ADC_CR_ADVREGEN                     ((uint32_t)0x10000000)     /*!< ADC Voltage Regulator Enable */
-#define ADC_CR_ADSTP                        ((uint32_t)0x00000010)     /*!< ADC stop of conversion command */
-#define ADC_CR_ADSTART                      ((uint32_t)0x00000004)     /*!< ADC start of conversion */
-#define ADC_CR_ADDIS                        ((uint32_t)0x00000002)     /*!< ADC disable command */
-#define ADC_CR_ADEN                         ((uint32_t)0x00000001)     /*!< ADC enable control */ /*####   TBV  */
-
-/*******************  Bits definition for ADC_CFGR1 register  *****************/
-#define ADC_CFGR1_AWDCH                     ((uint32_t)0x7C000000)     /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define ADC_CFGR1_AWDCH_0                   ((uint32_t)0x04000000)     /*!< Bit 0 */
-#define ADC_CFGR1_AWDCH_1                   ((uint32_t)0x08000000)     /*!< Bit 1 */
-#define ADC_CFGR1_AWDCH_2                   ((uint32_t)0x10000000)     /*!< Bit 2 */
-#define ADC_CFGR1_AWDCH_3                   ((uint32_t)0x20000000)     /*!< Bit 3 */
-#define ADC_CFGR1_AWDCH_4                   ((uint32_t)0x40000000)     /*!< Bit 4 */
-#define ADC_CFGR1_AWDEN                     ((uint32_t)0x00800000)     /*!< Analog watchdog enable on regular channels */
-#define ADC_CFGR1_AWDSGL                    ((uint32_t)0x00400000)     /*!< Enable the watchdog on a single channel or on all channels  */
-#define ADC_CFGR1_DISCEN                    ((uint32_t)0x00010000)     /*!< Discontinuous mode on regular channels */
-#define ADC_CFGR1_AUTOFF                    ((uint32_t)0x00008000)     /*!< ADC auto power off */
-#define ADC_CFGR1_WAIT                      ((uint32_t)0x00004000)     /*!< ADC wait conversion mode */
-#define ADC_CFGR1_CONT                      ((uint32_t)0x00002000)     /*!< Continuous Conversion */
-#define ADC_CFGR1_OVRMOD                    ((uint32_t)0x00001000)     /*!< Overrun mode */
-#define ADC_CFGR1_EXTEN                     ((uint32_t)0x00000C00)     /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define ADC_CFGR1_EXTEN_0                   ((uint32_t)0x00000400)     /*!< Bit 0 */
-#define ADC_CFGR1_EXTEN_1                   ((uint32_t)0x00000800)     /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL                    ((uint32_t)0x000001C0)     /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
-#define ADC_CFGR1_EXTSEL_0                  ((uint32_t)0x00000040)     /*!< Bit 0 */
-#define ADC_CFGR1_EXTSEL_1                  ((uint32_t)0x00000080)     /*!< Bit 1 */
-#define ADC_CFGR1_EXTSEL_2                  ((uint32_t)0x00000100)     /*!< Bit 2 */
-#define ADC_CFGR1_ALIGN                     ((uint32_t)0x00000020)     /*!< Data Alignment */
-#define ADC_CFGR1_RES                       ((uint32_t)0x00000018)     /*!< RES[1:0] bits (Resolution) */
-#define ADC_CFGR1_RES_0                     ((uint32_t)0x00000008)     /*!< Bit 0 */
-#define ADC_CFGR1_RES_1                     ((uint32_t)0x00000010)     /*!< Bit 1 */
-#define ADC_CFGR1_SCANDIR                   ((uint32_t)0x00000004)     /*!< Sequence scan direction */
-#define ADC_CFGR1_DMACFG                    ((uint32_t)0x00000002)     /*!< Direct memory access configuration */
-#define ADC_CFGR1_DMAEN                     ((uint32_t)0x00000001)     /*!< Direct memory access enable */
-
-/* Old WAIT bit definition, maintained for legacy purpose */
-#define ADC_CFGR1_AUTDLY                    ADC_CFGR1_WAIT
-
-/*******************  Bits definition for ADC_CFGR2 register  *****************/
-#define ADC_CFGR2_TOVS                      ((uint32_t)0x80000200)     /*!< Triggered Oversampling */
-#define ADC_CFGR2_OVSS                      ((uint32_t)0x000001E0)     /*!< OVSS [3:0] bits (Oversampling shift) */
-#define ADC_CFGR2_OVSS_0                    ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define ADC_CFGR2_OVSS_1                    ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define ADC_CFGR2_OVSS_2                    ((uint32_t)0x00000080)     /*!< Bit 2 */
-#define ADC_CFGR2_OVSS_3                    ((uint32_t)0x00000100)     /*!< Bit 3 */
-#define ADC_CFGR2_OVSR                      ((uint32_t)0x0000001C)     /*!< OVSR  [2:0] bits (Oversampling ratio) */
-#define ADC_CFGR2_OVSR_0                    ((uint32_t)0x00000004)     /*!< Bit 0 */
-#define ADC_CFGR2_OVSR_1                    ((uint32_t)0x00000008)     /*!< Bit 1 */
-#define ADC_CFGR2_OVSR_2                    ((uint32_t)0x00000010)     /*!< Bit 2 */
-#define ADC_CFGR2_OVSE                      ((uint32_t)0x00000001)     /*!< Oversampler Enable */
-#define ADC_CFGR2_CKMODE                    ((uint32_t)0xC0000000)     /*!< CKMODE [1:0] bits (ADC clock mode) */
-#define ADC_CFGR2_CKMODE_0                  ((uint32_t)0x40000000)     /*!< Bit 0 */
-#define ADC_CFGR2_CKMODE_1                  ((uint32_t)0x80000000)     /*!< Bit 1 */
-
-
-/******************  Bit definition for ADC_SMPR register  ********************/
-#define ADC_SMPR_SMP                        ((uint32_t)0x00000007)     /*!< SMPR[2:0] bits (Sampling time selection) */
-#define ADC_SMPR_SMP_0                      ((uint32_t)0x00000001)     /*!< Bit 0 */
-#define ADC_SMPR_SMP_1                      ((uint32_t)0x00000002)     /*!< Bit 1 */
-#define ADC_SMPR_SMP_2                      ((uint32_t)0x00000004)     /*!< Bit 2 */
-
-/* Bit names aliases maintained for legacy */
-#define ADC_SMPR_SMPR                       ADC_SMPR_SMP
-#define ADC_SMPR_SMPR_0                     ADC_SMPR_SMP_0
-#define ADC_SMPR_SMPR_1                     ADC_SMPR_SMP_1
-#define ADC_SMPR_SMPR_2                     ADC_SMPR_SMP_2
-
-/*******************  Bit definition for ADC_TR register  ********************/
-#define ADC_TR_HT                           ((uint32_t)0x0FFF0000)     /*!< Analog watchdog high threshold */
-#define ADC_TR_LT                           ((uint32_t)0x00000FFF)     /*!< Analog watchdog low threshold */
-
-/******************  Bit definition for ADC_CHSELR register  ******************/
-#define ADC_CHSELR_CHSEL18                  ((uint32_t)0x00040000)     /*!< Channel 18 selection */
-#define ADC_CHSELR_CHSEL17                  ((uint32_t)0x00020000)     /*!< Channel 17 selection */
-#define ADC_CHSELR_CHSEL16                  ((uint32_t)0x00010000)     /*!< Channel 16 selection */
-#define ADC_CHSELR_CHSEL15                  ((uint32_t)0x00008000)     /*!< Channel 15 selection */
-#define ADC_CHSELR_CHSEL14                  ((uint32_t)0x00004000)     /*!< Channel 14 selection */
-#define ADC_CHSELR_CHSEL13                  ((uint32_t)0x00002000)     /*!< Channel 13 selection */
-#define ADC_CHSELR_CHSEL12                  ((uint32_t)0x00001000)     /*!< Channel 12 selection */
-#define ADC_CHSELR_CHSEL11                  ((uint32_t)0x00000800)     /*!< Channel 11 selection */
-#define ADC_CHSELR_CHSEL10                  ((uint32_t)0x00000400)     /*!< Channel 10 selection */
-#define ADC_CHSELR_CHSEL9                   ((uint32_t)0x00000200)     /*!< Channel 9 selection */
-#define ADC_CHSELR_CHSEL8                   ((uint32_t)0x00000100)     /*!< Channel 8 selection */
-#define ADC_CHSELR_CHSEL7                   ((uint32_t)0x00000080)     /*!< Channel 7 selection */
-#define ADC_CHSELR_CHSEL6                   ((uint32_t)0x00000040)     /*!< Channel 6 selection */
-#define ADC_CHSELR_CHSEL5                   ((uint32_t)0x00000020)     /*!< Channel 5 selection */
-#define ADC_CHSELR_CHSEL4                   ((uint32_t)0x00000010)     /*!< Channel 4 selection */
-#define ADC_CHSELR_CHSEL3                   ((uint32_t)0x00000008)     /*!< Channel 3 selection */
-#define ADC_CHSELR_CHSEL2                   ((uint32_t)0x00000004)     /*!< Channel 2 selection */
-#define ADC_CHSELR_CHSEL1                   ((uint32_t)0x00000002)     /*!< Channel 1 selection */
-#define ADC_CHSELR_CHSEL0                   ((uint32_t)0x00000001)     /*!< Channel 0 selection */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define ADC_DR_DATA                         ((uint32_t)0x0000FFFF)     /*!< Regular data */
-
-/********************  Bit definition for ADC_CALFACT register  ********************/
-#define ADC_CALFACT_CALFACT                 ((uint32_t)0x0000007F)     /*!< Calibration factor */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define ADC_CCR_LFMEN                       ((uint32_t)0x02000000)     /*!< Low Frequency Mode enable */
-#define ADC_CCR_VLCDEN                      ((uint32_t)0x01000000)     /*!< Voltage battery enable */
-#define ADC_CCR_TSEN                        ((uint32_t)0x00800000)     /*!< Temperature sensore enable */
-#define ADC_CCR_VREFEN                      ((uint32_t)0x00400000)     /*!< Vrefint enable */
-#define ADC_CCR_PRESC                       ((uint32_t)0x003C0000)     /*!< PRESC  [3:0] bits (ADC prescaler) */
-#define ADC_CCR_PRESC_0                     ((uint32_t)0x00040000)     /*!< Bit 0 */
-#define ADC_CCR_PRESC_1                     ((uint32_t)0x00080000)     /*!< Bit 1 */
-#define ADC_CCR_PRESC_2                     ((uint32_t)0x00100000)     /*!< Bit 2 */
-#define ADC_CCR_PRESC_3                     ((uint32_t)0x00200000)     /*!< Bit 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-/*************  Bit definition for COMP_CSR register (COMP1 and COMP2)  **************/
-/* COMP1 bits definition */
-#define COMP_CSR_COMP1EN                ((uint32_t)0x00000001) /*!< COMP1 enable */
-#define COMP_CSR_COMP1INNSEL            ((uint32_t)0x00000030) /*!< COMP1 inverting input select */
-#define COMP_CSR_COMP1INNSEL_0          ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
-#define COMP_CSR_COMP1INNSEL_1          ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
-#define COMP_CSR_COMP1WM                ((uint32_t)0x00000100) /*!< Comparators window mode enable */
-#define COMP_CSR_COMP1LPTIM1IN1         ((uint32_t)0x00001000) /*!< COMP1 LPTIM1 IN1 connection */
-#define COMP_CSR_COMP1POLARITY          ((uint32_t)0x00008000) /*!< COMP1 output polarity */
-#define COMP_CSR_COMP1VALUE             ((uint32_t)0x40000000) /*!< COMP1 output level */
-#define COMP_CSR_COMP1LOCK              ((uint32_t)0x80000000) /*!< COMP1 lock */
-/* COMP2 bits definition */
-#define COMP_CSR_COMP2EN                ((uint32_t)0x00000001) /*!< COMP2 enable */
-#define COMP_CSR_COMP2SPEED             ((uint32_t)0x000C0008) /*!< COMP2 power mode */
-#define COMP_CSR_COMP2INNSEL            ((uint32_t)0x00100070) /*!< COMP2 inverting input select */
-#define COMP_CSR_COMP2INNSEL_0          ((uint32_t)0x00100010) /*!< COMP2 inverting input select bit 0 */
-#define COMP_CSR_COMP2INNSEL_1          ((uint32_t)0x00200020) /*!< COMP2 inverting input select bit 1 */
-#define COMP_CSR_COMP2INNSEL_2          ((uint32_t)0x00400040) /*!< COMP2 inverting input select bit 2 */
-#define COMP_CSR_COMP2INPSEL            ((uint32_t)0x00000700) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_0          ((uint32_t)0x00000100) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_1          ((uint32_t)0x00000200) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2INPSEL_2          ((uint32_t)0x00000400) /*!< COMPx non inverting input select */
-#define COMP_CSR_COMP2LPTIM1IN2         ((uint32_t)0x00001000) /*!< COMP2 LPTIM1 IN2 connection */
-#define COMP_CSR_COMP2POLARITY          ((uint32_t)0x00008000) /*!< COMP2 output polarity */
-#define COMP_CSR_COMP2VALUE             ((uint32_t)0x40000000) /*!< COMP2 output level */
-#define COMP_CSR_COMP2LOCK              ((uint32_t)0x80000000) /*!< COMP2 lock */
-
-/**********************  Bit definition for COMP_CSR register common  ****************/
-#define COMP_CSR_COMPxEN                ((uint32_t)0x00000001) /*!< COMPx enable */
-#define COMP_CSR_COMPxPOLARITY          ((uint32_t)0x00008000) /*!< COMPx output polarity */
-#define COMP_CSR_COMPxOUTVALUE          ((uint32_t)0x40000000) /*!< COMPx output level */
-#define COMP_CSR_COMPxLOCK              ((uint32_t)0x80000000) /*!< COMPx lock */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for CRC_DR register  *********************/
-#define CRC_DR_DR                           ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define CRC_IDR_IDR                         ((uint32_t)0x000000FF) /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define CRC_CR_RESET                        ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
-#define CRC_CR_POLYSIZE                     ((uint32_t)0x00000018) /*!< Polynomial size bits */
-#define CRC_CR_POLYSIZE_0                   ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
-#define CRC_CR_POLYSIZE_1                   ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
-#define CRC_CR_REV_IN                       ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
-#define CRC_CR_REV_IN_0                     ((uint32_t)0x00000020) /*!< Bit 0 */
-#define CRC_CR_REV_IN_1                     ((uint32_t)0x00000040) /*!< Bit 1 */
-#define CRC_CR_REV_OUT                      ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
-
-/*******************  Bit definition for CRC_INIT register  *******************/
-#define CRC_INIT_INIT                       ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
-
-/*******************  Bit definition for CRC_POL register  ********************/
-#define CRC_POL_POL                         ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          CRS Clock Recovery System                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRS_CR register  *********************/
-#define CRS_CR_SYNCOKIE                     ((uint32_t)0x00000001) /* SYNC event OK interrupt enable        */
-#define CRS_CR_SYNCWARNIE                   ((uint32_t)0x00000002) /* SYNC warning interrupt enable         */
-#define CRS_CR_ERRIE                        ((uint32_t)0x00000004) /* SYNC error interrupt enable           */
-#define CRS_CR_ESYNCIE                      ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
-#define CRS_CR_CEN                          ((uint32_t)0x00000020) /* Frequency error counter enable        */
-#define CRS_CR_AUTOTRIMEN                   ((uint32_t)0x00000040) /* Automatic trimming enable             */
-#define CRS_CR_SWSYNC                       ((uint32_t)0x00000080) /* A Software SYNC event is generated    */
-#define CRS_CR_TRIM                         ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming      */
-
-/*******************  Bit definition for CRS_CFGR register  *********************/
-#define CRS_CFGR_RELOAD                     ((uint32_t)0x0000FFFF) /* Counter reload value               */
-#define CRS_CFGR_FELIM                      ((uint32_t)0x00FF0000) /* Frequency error limit              */
-
-#define CRS_CFGR_SYNCDIV                    ((uint32_t)0x07000000) /* SYNC divider                       */
-#define CRS_CFGR_SYNCDIV_0                  ((uint32_t)0x01000000) /* Bit 0                              */
-#define CRS_CFGR_SYNCDIV_1                  ((uint32_t)0x02000000) /* Bit 1                              */
-#define CRS_CFGR_SYNCDIV_2                  ((uint32_t)0x04000000) /* Bit 2                              */
-
-#define CRS_CFGR_SYNCSRC                    ((uint32_t)0x30000000) /* SYNC signal source selection       */
-#define CRS_CFGR_SYNCSRC_0                  ((uint32_t)0x10000000) /* Bit 0                              */
-#define CRS_CFGR_SYNCSRC_1                  ((uint32_t)0x20000000) /* Bit 1                              */
-
-#define CRS_CFGR_SYNCPOL                    ((uint32_t)0x80000000) /* SYNC polarity selection            */
-  
-/*******************  Bit definition for CRS_ISR register  *********************/
-#define CRS_ISR_SYNCOKF                     ((uint32_t)0x00000001) /* SYNC event OK flag             */
-#define CRS_ISR_SYNCWARNF                   ((uint32_t)0x00000002) /* SYNC warning                   */
-#define CRS_ISR_ERRF                        ((uint32_t)0x00000004) /* SYNC error flag                */
-#define CRS_ISR_ESYNCF                      ((uint32_t)0x00000008) /* Expected SYNC flag             */
-#define CRS_ISR_SYNCERR                     ((uint32_t)0x00000100) /* SYNC error                     */
-#define CRS_ISR_SYNCMISS                    ((uint32_t)0x00000200) /* SYNC missed                    */
-#define CRS_ISR_TRIMOVF                     ((uint32_t)0x00000400) /* Trimming overflow or underflow */
-#define CRS_ISR_FEDIR                       ((uint32_t)0x00008000) /* Frequency error direction      */
-#define CRS_ISR_FECAP                       ((uint32_t)0xFFFF0000) /* Frequency error capture        */
-
-/*******************  Bit definition for CRS_ICR register  *********************/
-#define CRS_ICR_SYNCOKC                     ((uint32_t)0x00000001) /* SYNC event OK clear flag     */
-#define CRS_ICR_SYNCWARNC                   ((uint32_t)0x00000002) /* SYNC warning clear flag      */
-#define CRS_ICR_ERRC                        ((uint32_t)0x00000004) /* Error clear flag             */
-#define CRS_ICR_ESYNCC                      ((uint32_t)0x00000008) /* Expected SYNC clear flag     */
-
-/******************************************************************************/
-/*                                                                            */
-/*                 Digital to Analog Converter (DAC)                          */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for DAC_CR register  ********************/
-#define DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!< DAC channel1 enable */
-#define DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!< DAC channel1 output buffer disable */
-#define DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!< DAC channel1 Trigger enable */
-
-#define DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-#define DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!< Bit 2 */
-#define DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!< Bit 3 */
-
-#define DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!< DAC channel1 DMA enable */
-#define DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!< DAC channel1 DMA Underrun interrupt enable */
-
-#define DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!< DAC channel2 enable */
-#define DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!< DAC channel2 output buffer disable */
-#define DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!< DAC channel2 Trigger enable */
-
-#define DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!< Bit 0 */
-#define DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!< Bit 1 */
-#define DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!< Bit 2 */
-
-#define DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!< Bit 0 */
-#define DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!< Bit 1 */
-
-#define DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!< DAC channel2 DMA enabled */
-#define DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!< DAC channel12DMA Underrun interrupt enable */
-
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!< DAC channel1 software trigger */
-#define DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x00000002)        /*!< DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)        /*!< DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define DAC_DHR12R2_DACC2DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define DAC_DHR12L2_DACC2DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define DAC_DHR8R2_DACC2DHR                 ((uint32_t)0x000000FF)        /*!< DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!< DAC channel1 12-bit Right aligned data */
-#define DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!< DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!< DAC channel1 12-bit Left aligned data */
-#define DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!< DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x000000FF)        /*!< DAC channel1 8-bit Right aligned data */
-#define DAC_DHR8RD_DACC2DHR                 ((uint32_t)0x0000FF00)        /*!< DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define DAC_DOR1_DACC1DOR                   ((uint16_t)0x00000FFF)        /*!< DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define DAC_DOR2_DACC2DOR                   ((uint32_t)0x00000FFF)        /*!< DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!< DAC channel1 DMA underrun flag */
-#define DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!< DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define DBGMCU_IDCODE_DIV_ID                ((uint32_t)0x0000F000)        /*!< Division Identifier */
-#define DBGMCU_IDCODE_MCD_DIV_ID            ((uint32_t)0x00006000)        /*!< MCD divsion ID is 6 */
-#define DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define DBGMCU_CR_DBG                       ((uint32_t)0x00000007)        /*!< Debug mode mask */
-#define DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
-#define DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-#define DBGMCU_APB1_FZ_DBG_TIM2_STOP        ((uint32_t)0x00000001)        /*!< TIM2 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM3_STOP        ((uint32_t)0x00000002)
-#define DBGMCU_APB1_FZ_DBG_TIM6_STOP        ((uint32_t)0x00000010)        /*!< TIM6 counter stopped when core is halted */
-#define DBGMCU_APB1_FZ_DBG_TIM7_STOP        ((uint32_t)0x00000020)
-#define DBGMCU_APB1_FZ_DBG_RTC_STOP         ((uint32_t)0x00000400)        /*!< RTC Calendar frozen when core is halted */
-#define DBGMCU_APB1_FZ_DBG_WWDG_STOP        ((uint32_t)0x00000800)        /*!< Debug Window Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_IWDG_STOP        ((uint32_t)0x00001000)        /*!< Debug Independent Watchdog stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C1_STOP        ((uint32_t)0x00200000)        /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C2_STOP        ((uint32_t)0x00400000)        /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_I2C3_STOP        ((uint32_t)0x00800000)        /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
-#define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP     ((uint32_t)0x80000000)        /*!< LPTIM1 counter stopped when core is halted */
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-#define DBGMCU_APB2_FZ_DBG_TIM22_STOP       ((uint32_t)0x00000020)        /*!< TIM22 counter stopped when core is halted */
-#define DBGMCU_APB2_FZ_DBG_TIM21_STOP       ((uint32_t)0x00000004)        /*!< TIM21 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag    */
-#define DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag   */
-#define DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag       */
-#define DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag      */
-#define DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag    */
-#define DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag   */
-#define DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag       */
-#define DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag      */
-#define DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag    */
-#define DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag   */
-#define DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag       */
-#define DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag      */
-#define DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag    */
-#define DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag   */
-#define DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag       */
-#define DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag      */
-#define DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag    */
-#define DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag   */
-#define DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag       */
-#define DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag      */
-#define DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear    */
-#define DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear       */
-#define DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear      */
-#define DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear    */
-#define DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear       */
-#define DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear      */
-#define DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear    */
-#define DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear       */
-#define DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear      */
-#define DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear    */
-#define DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear       */
-#define DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear      */
-#define DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear    */
-#define DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear   */
-#define DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear       */
-#define DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear      */
-#define DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  ********************/
-#define DMA_CCR_EN                          ((uint32_t)0x00000001)        /*!< Channel enable                      */
-#define DMA_CCR_TCIE                        ((uint32_t)0x00000002)        /*!< Transfer complete interrupt enable  */
-#define DMA_CCR_HTIE                        ((uint32_t)0x00000004)        /*!< Half Transfer interrupt enable      */
-#define DMA_CCR_TEIE                        ((uint32_t)0x00000008)        /*!< Transfer error interrupt enable     */
-#define DMA_CCR_DIR                         ((uint32_t)0x00000010)        /*!< Data transfer direction             */
-#define DMA_CCR_CIRC                        ((uint32_t)0x00000020)        /*!< Circular mode                       */
-#define DMA_CCR_PINC                        ((uint32_t)0x00000040)        /*!< Peripheral increment mode           */
-#define DMA_CCR_MINC                        ((uint32_t)0x00000080)        /*!< Memory increment mode               */
-
-#define DMA_CCR_PSIZE                       ((uint32_t)0x00000300)        /*!< PSIZE[1:0] bits (Peripheral size)   */
-#define DMA_CCR_PSIZE_0                     ((uint32_t)0x00000100)        /*!< Bit 0                               */
-#define DMA_CCR_PSIZE_1                     ((uint32_t)0x00000200)        /*!< Bit 1                               */
-
-#define DMA_CCR_MSIZE                       ((uint32_t)0x00000C00)        /*!< MSIZE[1:0] bits (Memory size)       */
-#define DMA_CCR_MSIZE_0                     ((uint32_t)0x00000400)        /*!< Bit 0                               */
-#define DMA_CCR_MSIZE_1                     ((uint32_t)0x00000800)        /*!< Bit 1                               */
-
-#define DMA_CCR_PL                          ((uint32_t)0x00003000)        /*!< PL[1:0] bits(Channel Priority level)*/
-#define DMA_CCR_PL_0                        ((uint32_t)0x00001000)        /*!< Bit 0                               */
-#define DMA_CCR_PL_1                        ((uint32_t)0x00002000)        /*!< Bit 1                               */
-
-#define DMA_CCR_MEM2MEM                     ((uint32_t)0x00004000)        /*!< Memory to memory mode               */
-
-/******************  Bit definition for DMA_CNDTR register  *******************/
-#define DMA_CNDTR_NDT                       ((uint32_t)0x0000FFFF)        /*!< Number of data to Transfer          */
-
-/******************  Bit definition for DMA_CPAR register  ********************/
-#define DMA_CPAR_PA                         ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address                  */
-
-/******************  Bit definition for DMA_CMAR register  ********************/
-#define DMA_CMAR_MA                         ((uint32_t)0xFFFFFFFF)        /*!< Memory Address                      */
-
-
-/*******************  Bit definition for DMA_CSELR register  *******************/
-#define DMA_CSELR_C1S                       ((uint32_t)0x0000000F)          /*!< Channel 1 Selection */ 
-#define DMA_CSELR_C2S                       ((uint32_t)0x000000F0)          /*!< Channel 2 Selection */ 
-#define DMA_CSELR_C3S                       ((uint32_t)0x00000F00)          /*!< Channel 3 Selection */ 
-#define DMA_CSELR_C4S                       ((uint32_t)0x0000F000)          /*!< Channel 4 Selection */ 
-#define DMA_CSELR_C5S                       ((uint32_t)0x000F0000)          /*!< Channel 5 Selection */ 
-#define DMA_CSELR_C6S                       ((uint32_t)0x00F00000)          /*!< Channel 6 Selection */ 
-#define DMA_CSELR_C7S                       ((uint32_t)0x0F000000)          /*!< Channel 7 Selection */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                 External Interrupt/Event Controller (EXTI)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define EXTI_IMR_IM0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0  */
-#define EXTI_IMR_IM1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1  */
-#define EXTI_IMR_IM2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2  */
-#define EXTI_IMR_IM3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3  */
-#define EXTI_IMR_IM4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4  */
-#define EXTI_IMR_IM5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5  */
-#define EXTI_IMR_IM6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6  */
-#define EXTI_IMR_IM7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7  */
-#define EXTI_IMR_IM8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8  */
-#define EXTI_IMR_IM9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9  */
-#define EXTI_IMR_IM10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define EXTI_IMR_IM11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define EXTI_IMR_IM12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define EXTI_IMR_IM13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define EXTI_IMR_IM14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define EXTI_IMR_IM15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define EXTI_IMR_IM16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define EXTI_IMR_IM17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define EXTI_IMR_IM18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define EXTI_IMR_IM19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define EXTI_IMR_IM20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define EXTI_IMR_IM21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define EXTI_IMR_IM22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define EXTI_IMR_IM23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-#define EXTI_IMR_IM24                       ((uint32_t)0x01000000)        /*!< Interrupt Mask on line 24 */
-#define EXTI_IMR_IM25                       ((uint32_t)0x02000000)        /*!< Interrupt Mask on line 25 */
-#define EXTI_IMR_IM26                       ((uint32_t)0x04000000)        /*!< Interrupt Mask on line 26 */
-#define EXTI_IMR_IM28                       ((uint32_t)0x10000000)        /*!< Interrupt Mask on line 28 */
-#define EXTI_IMR_IM29                       ((uint32_t)0x20000000)        /*!< Interrupt Mask on line 29 */
-
-/******************  Bit definition for EXTI_EMR register  ********************/
-#define EXTI_EMR_EM0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0  */
-#define EXTI_EMR_EM1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1  */
-#define EXTI_EMR_EM2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2  */
-#define EXTI_EMR_EM3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3  */
-#define EXTI_EMR_EM4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4  */
-#define EXTI_EMR_EM5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5  */
-#define EXTI_EMR_EM6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6  */
-#define EXTI_EMR_EM7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7  */
-#define EXTI_EMR_EM8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8  */
-#define EXTI_EMR_EM9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9  */
-#define EXTI_EMR_EM10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define EXTI_EMR_EM11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define EXTI_EMR_EM12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define EXTI_EMR_EM13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define EXTI_EMR_EM14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define EXTI_EMR_EM15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define EXTI_EMR_EM16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define EXTI_EMR_EM17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define EXTI_EMR_EM18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define EXTI_EMR_EM19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define EXTI_EMR_EM20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define EXTI_EMR_EM21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define EXTI_EMR_EM22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define EXTI_EMR_EM23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-#define EXTI_EMR_EM24                       ((uint32_t)0x01000000)        /*!< Event Mask on line 24 */
-#define EXTI_EMR_EM25                       ((uint32_t)0x02000000)        /*!< Event Mask on line 25 */
-#define EXTI_EMR_EM26                       ((uint32_t)0x04000000)        /*!< Event Mask on line 26 */
-#define EXTI_EMR_EM28                       ((uint32_t)0x10000000)        /*!< Event Mask on line 28 */
-#define EXTI_EMR_EM29                       ((uint32_t)0x20000000)        /*!< Event Mask on line 29 */
-
-/*******************  Bit definition for EXTI_RTSR register  ******************/
-#define EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-
-/*******************  Bit definition for EXTI_FTSR register *******************/
-#define EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-
-/******************* Bit definition for EXTI_SWIER register *******************/
-#define EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0  */
-#define EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1  */
-#define EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2  */
-#define EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3  */
-#define EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4  */
-#define EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5  */
-#define EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6  */
-#define EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7  */
-#define EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8  */
-#define EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9  */
-#define EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-
-/******************  Bit definition for EXTI_PR register  *********************/
-#define EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0  */
-#define EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1  */
-#define EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2  */
-#define EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3  */
-#define EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4  */
-#define EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5  */
-#define EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6  */
-#define EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7  */
-#define EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8  */
-#define EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9  */
-#define EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
-#define EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
-#define EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
-#define EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
-#define EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
-#define EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
-#define EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
-#define EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
-#define EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
-#define EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
-#define EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
-#define EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      FLASH and Option Bytes Registers                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< LATENCY bit (Latency) */
-#define FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
-#define FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
-#define FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
-#define FLASH_ACR_DISAB_BUF                 ((uint32_t)0x00000020)        /*!< Disable Buffer */
-#define FLASH_ACR_PRE_READ                  ((uint32_t)0x00000040)        /*!< Pre-read data address */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
-#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
-#define FLASH_PECR_FIX                       ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
-#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK                ((uint32_t)0x00008000)        /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */
-#define FLASH_PECR_HALF_ARRAY                ((uint32_t)0x00080000)        /*!< Half array mode */
-#define FLASH_PECR_NZDISABLE                 ((uint32_t)0x00400000)        /*!< Non-Zero check disable */
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
-#define FLASH_SR_HVOFF                      ((uint32_t)0x00000004)        /*!< End of high voltage */
-#define FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
-
-#define FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protection error */
-#define FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
-#define FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
-#define FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option Valid error */
-#define FLASH_SR_RDERR                      ((uint32_t)0x00002000)        /*!< Read protected error */
-#define FLASH_SR_NOTZEROERR                 ((uint32_t)0x00010000)        /*!< Not Zero error */
-#define FLASH_SR_FWWERR                     ((uint32_t)0x00020000)        /*!< Write/Errase operation aborted */
-
-/* alias maintained for legacy */
-#define FLASH_SR_FWWER                      FLASH_SR_FWWERR
-#define FLASH_SR_ENHV                       FLASH_SR_HVOFF
-#define FLASH_SR_ENDHV                      FLASH_SR_HVOFF
-
-/******************  Bit definition for FLASH_OPTR register  *******************/
-#define FLASH_OPTR_RDPROT                   ((uint32_t)0x000000FF)        /*!< Read Protection */
-#define FLASH_OPTR_WPRMOD                   ((uint32_t)0x00000100)        /*!< Selection of protection mode of WPR bits */
-#define FLASH_OPTR_BOR_LEV                  ((uint32_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define FLASH_OPTR_IWDG_SW                  ((uint32_t)0x00100000)        /*!< IWDG_SW */
-#define FLASH_OPTR_nRST_STOP                ((uint32_t)0x00200000)        /*!< nRST_STOP */
-#define FLASH_OPTR_nRST_STDBY               ((uint32_t)0x00400000)        /*!< nRST_STDBY */
-#define FLASH_OPTR_BFB2                     ((uint32_t)0x00800000)        /*!< BFB2 */
-#define FLASH_OPTR_USER                     ((uint32_t)0x00700000)        /*!< User Option Bytes */
-#define FLASH_OPTR_BOOT1                    ((uint32_t)0x80000000)        /*!< BOOT1 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define FLASH_WRPR_WRP                      ((uint32_t)0x0000FFFF)        /*!< Write Protection bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       General Purpose IOs (GPIO)                           */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODE0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODE0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODE0_1        ((uint32_t)0x00000002)
-#define GPIO_MODER_MODE1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODE1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODE1_1        ((uint32_t)0x00000008)
-#define GPIO_MODER_MODE2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODE2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODE2_1        ((uint32_t)0x00000020)
-#define GPIO_MODER_MODE3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODE3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODE3_1        ((uint32_t)0x00000080)
-#define GPIO_MODER_MODE4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODE4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODE4_1        ((uint32_t)0x00000200)
-#define GPIO_MODER_MODE5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODE5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODE5_1        ((uint32_t)0x00000800)
-#define GPIO_MODER_MODE6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODE6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODE6_1        ((uint32_t)0x00002000)
-#define GPIO_MODER_MODE7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODE7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODE7_1        ((uint32_t)0x00008000)
-#define GPIO_MODER_MODE8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODE8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODE8_1        ((uint32_t)0x00020000)
-#define GPIO_MODER_MODE9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODE9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODE9_1        ((uint32_t)0x00080000)
-#define GPIO_MODER_MODE10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODE10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODE10_1       ((uint32_t)0x00200000)
-#define GPIO_MODER_MODE11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODE11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODE11_1       ((uint32_t)0x00800000)
-#define GPIO_MODER_MODE12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODE12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODE12_1       ((uint32_t)0x02000000)
-#define GPIO_MODER_MODE13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODE13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODE13_1       ((uint32_t)0x08000000)
-#define GPIO_MODER_MODE14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODE14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODE14_1       ((uint32_t)0x20000000)
-#define GPIO_MODER_MODE15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODE15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODE15_1       ((uint32_t)0x80000000)
-
-/******************  Bit definition for GPIO_OTYPER register  *****************/
-#define GPIO_OTYPER_OT_0          ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1          ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2          ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3          ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4          ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5          ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6          ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7          ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8          ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9          ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10         ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11         ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12         ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13         ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14         ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15         ((uint32_t)0x00008000)
-
-/****************  Bit definition for GPIO_OSPEEDR register  ******************/
-#define GPIO_OSPEEDER_OSPEED0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEED0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEED0_1   ((uint32_t)0x00000002)
-#define GPIO_OSPEEDER_OSPEED1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEED1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEED1_1   ((uint32_t)0x00000008)
-#define GPIO_OSPEEDER_OSPEED2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEED2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEED2_1   ((uint32_t)0x00000020)
-#define GPIO_OSPEEDER_OSPEED3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEED3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEED3_1   ((uint32_t)0x00000080)
-#define GPIO_OSPEEDER_OSPEED4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEED4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEED4_1   ((uint32_t)0x00000200)
-#define GPIO_OSPEEDER_OSPEED5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEED5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEED5_1   ((uint32_t)0x00000800)
-#define GPIO_OSPEEDER_OSPEED6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEED6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEED6_1   ((uint32_t)0x00002000)
-#define GPIO_OSPEEDER_OSPEED7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEED7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEED7_1   ((uint32_t)0x00008000)
-#define GPIO_OSPEEDER_OSPEED8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEED8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEED8_1   ((uint32_t)0x00020000)
-#define GPIO_OSPEEDER_OSPEED9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEED9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEED9_1   ((uint32_t)0x00080000)
-#define GPIO_OSPEEDER_OSPEED10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEED10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEED10_1  ((uint32_t)0x00200000)
-#define GPIO_OSPEEDER_OSPEED11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEED11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEED11_1  ((uint32_t)0x00800000)
-#define GPIO_OSPEEDER_OSPEED12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEED12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEED12_1  ((uint32_t)0x02000000)
-#define GPIO_OSPEEDER_OSPEED13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEED13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEED13_1  ((uint32_t)0x08000000)
-#define GPIO_OSPEEDER_OSPEED14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEED14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEED14_1  ((uint32_t)0x20000000)
-#define GPIO_OSPEEDER_OSPEED15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEED15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEED15_1  ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_PUPDR register ******************/
-#define GPIO_PUPDR_PUPD0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPD0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPD0_1        ((uint32_t)0x00000002)
-#define GPIO_PUPDR_PUPD1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPD1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPD1_1        ((uint32_t)0x00000008)
-#define GPIO_PUPDR_PUPD2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPD2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPD2_1        ((uint32_t)0x00000020)
-#define GPIO_PUPDR_PUPD3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPD3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPD3_1        ((uint32_t)0x00000080)
-#define GPIO_PUPDR_PUPD4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPD4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPD4_1        ((uint32_t)0x00000200)
-#define GPIO_PUPDR_PUPD5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPD5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPD5_1        ((uint32_t)0x00000800)
-#define GPIO_PUPDR_PUPD6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPD6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPD6_1        ((uint32_t)0x00002000)
-#define GPIO_PUPDR_PUPD7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPD7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPD7_1        ((uint32_t)0x00008000)
-#define GPIO_PUPDR_PUPD8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPD8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPD8_1        ((uint32_t)0x00020000)
-#define GPIO_PUPDR_PUPD9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPD9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPD9_1        ((uint32_t)0x00080000)
-#define GPIO_PUPDR_PUPD10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPD10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPD10_1       ((uint32_t)0x00200000)
-#define GPIO_PUPDR_PUPD11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPD11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPD11_1       ((uint32_t)0x00800000)
-#define GPIO_PUPDR_PUPD12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPD12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPD12_1       ((uint32_t)0x02000000)
-#define GPIO_PUPDR_PUPD13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPD13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPD13_1       ((uint32_t)0x08000000)
-#define GPIO_PUPDR_PUPD14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPD14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPD14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPD15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPD15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPD15_1       ((uint32_t)0x80000000)
-
-/*******************  Bit definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_ID0              ((uint32_t)0x00000001)
-#define GPIO_IDR_ID1              ((uint32_t)0x00000002)
-#define GPIO_IDR_ID2              ((uint32_t)0x00000004)
-#define GPIO_IDR_ID3              ((uint32_t)0x00000008)
-#define GPIO_IDR_ID4              ((uint32_t)0x00000010)
-#define GPIO_IDR_ID5              ((uint32_t)0x00000020)
-#define GPIO_IDR_ID6              ((uint32_t)0x00000040)
-#define GPIO_IDR_ID7              ((uint32_t)0x00000080)
-#define GPIO_IDR_ID8              ((uint32_t)0x00000100)
-#define GPIO_IDR_ID9              ((uint32_t)0x00000200)
-#define GPIO_IDR_ID10             ((uint32_t)0x00000400)
-#define GPIO_IDR_ID11             ((uint32_t)0x00000800)
-#define GPIO_IDR_ID12             ((uint32_t)0x00001000)
-#define GPIO_IDR_ID13             ((uint32_t)0x00002000)
-#define GPIO_IDR_ID14             ((uint32_t)0x00004000)
-#define GPIO_IDR_ID15             ((uint32_t)0x00008000)
-
-/******************  Bit definition for GPIO_ODR register  ********************/
-#define GPIO_ODR_OD0              ((uint32_t)0x00000001)
-#define GPIO_ODR_OD1              ((uint32_t)0x00000002)
-#define GPIO_ODR_OD2              ((uint32_t)0x00000004)
-#define GPIO_ODR_OD3              ((uint32_t)0x00000008)
-#define GPIO_ODR_OD4              ((uint32_t)0x00000010)
-#define GPIO_ODR_OD5              ((uint32_t)0x00000020)
-#define GPIO_ODR_OD6              ((uint32_t)0x00000040)
-#define GPIO_ODR_OD7              ((uint32_t)0x00000080)
-#define GPIO_ODR_OD8              ((uint32_t)0x00000100)
-#define GPIO_ODR_OD9              ((uint32_t)0x00000200)
-#define GPIO_ODR_OD10             ((uint32_t)0x00000400)
-#define GPIO_ODR_OD11             ((uint32_t)0x00000800)
-#define GPIO_ODR_OD12             ((uint32_t)0x00001000)
-#define GPIO_ODR_OD13             ((uint32_t)0x00002000)
-#define GPIO_ODR_OD14             ((uint32_t)0x00004000)
-#define GPIO_ODR_OD15             ((uint32_t)0x00008000)
-
-/****************** Bit definition for GPIO_BSRR register  ********************/
-#define GPIO_BSRR_BS_0            ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1            ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2            ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3            ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4            ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5            ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6            ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7            ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8            ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9            ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10           ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11           ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12           ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13           ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14           ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15           ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0            ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1            ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2            ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3            ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4            ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5            ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6            ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7            ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8            ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9            ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10           ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11           ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12           ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13           ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14           ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15           ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0            ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1            ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2            ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3            ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4            ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5            ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6            ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7            ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8            ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9            ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10           ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11           ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12           ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13           ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14           ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15           ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK            ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0             ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1             ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2             ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3             ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4             ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5             ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6             ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7             ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8             ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9             ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10            ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11            ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12            ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13            ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14            ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15            ((uint32_t)0x00008000)
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  *******************/
-#define I2C_CR1_PE                          ((uint32_t)0x00000001)        /*!< Peripheral enable */
-#define I2C_CR1_TXIE                        ((uint32_t)0x00000002)        /*!< TX interrupt enable */
-#define I2C_CR1_RXIE                        ((uint32_t)0x00000004)        /*!< RX interrupt enable */
-#define I2C_CR1_ADDRIE                      ((uint32_t)0x00000008)        /*!< Address match interrupt enable */
-#define I2C_CR1_NACKIE                      ((uint32_t)0x00000010)        /*!< NACK received interrupt enable */
-#define I2C_CR1_STOPIE                      ((uint32_t)0x00000020)        /*!< STOP detection interrupt enable */
-#define I2C_CR1_TCIE                        ((uint32_t)0x00000040)        /*!< Transfer complete interrupt enable */
-#define I2C_CR1_ERRIE                       ((uint32_t)0x00000080)        /*!< Errors interrupt enable */
-#define I2C_CR1_DFN                         ((uint32_t)0x00000F00)        /*!< Digital noise filter */
-#define I2C_CR1_ANFOFF                      ((uint32_t)0x00001000)        /*!< Analog noise filter OFF */
-#define I2C_CR1_TXDMAEN                     ((uint32_t)0x00004000)        /*!< DMA transmission requests enable */
-#define I2C_CR1_RXDMAEN                     ((uint32_t)0x00008000)        /*!< DMA reception requests enable */
-#define I2C_CR1_SBC                         ((uint32_t)0x00010000)        /*!< Slave byte control */
-#define I2C_CR1_NOSTRETCH                   ((uint32_t)0x00020000)        /*!< Clock stretching disable */
-#define I2C_CR1_WUPEN                       ((uint32_t)0x00040000)        /*!< Wakeup from STOP enable */
-#define I2C_CR1_GCEN                        ((uint32_t)0x00080000)        /*!< General call enable */
-#define I2C_CR1_SMBHEN                      ((uint32_t)0x00100000)        /*!< SMBus host address enable */
-#define I2C_CR1_SMBDEN                      ((uint32_t)0x00200000)        /*!< SMBus device default address enable */
-#define I2C_CR1_ALERTEN                     ((uint32_t)0x00400000)        /*!< SMBus alert enable */
-#define I2C_CR1_PECEN                       ((uint32_t)0x00800000)        /*!< PEC enable */
-
-/******************  Bit definition for I2C_CR2 register  ********************/
-#define I2C_CR2_SADD                        ((uint32_t)0x000003FF)        /*!< Slave address (master mode) */
-#define I2C_CR2_RD_WRN                      ((uint32_t)0x00000400)        /*!< Transfer direction (master mode) */
-#define I2C_CR2_ADD10                       ((uint32_t)0x00000800)        /*!< 10-bit addressing mode (master mode) */
-#define I2C_CR2_HEAD10R                     ((uint32_t)0x00001000)        /*!< 10-bit address header only read direction (master mode) */
-#define I2C_CR2_START                       ((uint32_t)0x00002000)        /*!< START generation */
-#define I2C_CR2_STOP                        ((uint32_t)0x00004000)        /*!< STOP generation (master mode) */
-#define I2C_CR2_NACK                        ((uint32_t)0x00008000)        /*!< NACK generation (slave mode) */
-#define I2C_CR2_NBYTES                      ((uint32_t)0x00FF0000)        /*!< Number of bytes */
-#define I2C_CR2_RELOAD                      ((uint32_t)0x01000000)        /*!< NBYTES reload mode */
-#define I2C_CR2_AUTOEND                     ((uint32_t)0x02000000)        /*!< Automatic end mode (master mode) */
-#define I2C_CR2_PECBYTE                     ((uint32_t)0x04000000)        /*!< Packet error checking byte */
-
-/*******************  Bit definition for I2C_OAR1 register  ******************/
-#define I2C_OAR1_OA1                        ((uint32_t)0x000003FF)        /*!< Interface own address 1 */
-#define I2C_OAR1_OA1MODE                    ((uint32_t)0x00000400)        /*!< Own address 1 10-bit mode */
-#define I2C_OAR1_OA1EN                      ((uint32_t)0x00008000)        /*!< Own address 1 enable */
-
-/*******************  Bit definition for I2C_OAR2 register  ******************/
-#define I2C_OAR2_OA2                        ((uint32_t)0x000000FE)        /*!< Interface own address 2 */
-#define I2C_OAR2_OA2MSK                     ((uint32_t)0x00000700)        /*!< Own address 2 masks */
-#define I2C_OAR2_OA2EN                      ((uint32_t)0x00008000)        /*!< Own address 2 enable */
-
-/*******************  Bit definition for I2C_TIMINGR register *******************/
-#define I2C_TIMINGR_SCLL                    ((uint32_t)0x000000FF)        /*!< SCL low period (master mode) */
-#define I2C_TIMINGR_SCLH                    ((uint32_t)0x0000FF00)        /*!< SCL high period (master mode) */
-#define I2C_TIMINGR_SDADEL                  ((uint32_t)0x000F0000)        /*!< Data hold time */
-#define I2C_TIMINGR_SCLDEL                  ((uint32_t)0x00F00000)        /*!< Data setup time */
-#define I2C_TIMINGR_PRESC                   ((uint32_t)0xF0000000)        /*!< Timings prescaler */
-
-/******************* Bit definition for I2C_TIMEOUTR register *******************/
-#define I2C_TIMEOUTR_TIMEOUTA               ((uint32_t)0x00000FFF)        /*!< Bus timeout A */
-#define I2C_TIMEOUTR_TIDLE                  ((uint32_t)0x00001000)        /*!< Idle clock timeout detection */
-#define I2C_TIMEOUTR_TIMOUTEN               ((uint32_t)0x00008000)        /*!< Clock timeout enable */
-#define I2C_TIMEOUTR_TIMEOUTB               ((uint32_t)0x0FFF0000)        /*!< Bus timeout B*/
-#define I2C_TIMEOUTR_TEXTEN                 ((uint32_t)0x80000000)        /*!< Extended clock timeout enable */
-
-/******************  Bit definition for I2C_ISR register  *********************/
-#define I2C_ISR_TXE                         ((uint32_t)0x00000001)        /*!< Transmit data register empty */
-#define I2C_ISR_TXIS                        ((uint32_t)0x00000002)        /*!< Transmit interrupt status */
-#define I2C_ISR_RXNE                        ((uint32_t)0x00000004)        /*!< Receive data register not empty */
-#define I2C_ISR_ADDR                        ((uint32_t)0x00000008)        /*!< Address matched (slave mode)*/
-#define I2C_ISR_NACKF                       ((uint32_t)0x00000010)        /*!< NACK received flag */
-#define I2C_ISR_STOPF                       ((uint32_t)0x00000020)        /*!< STOP detection flag */
-#define I2C_ISR_TC                          ((uint32_t)0x00000040)        /*!< Transfer complete (master mode) */
-#define I2C_ISR_TCR                         ((uint32_t)0x00000080)        /*!< Transfer complete reload */
-#define I2C_ISR_BERR                        ((uint32_t)0x00000100)        /*!< Bus error */
-#define I2C_ISR_ARLO                        ((uint32_t)0x00000200)        /*!< Arbitration lost */
-#define I2C_ISR_OVR                         ((uint32_t)0x00000400)        /*!< Overrun/Underrun */
-#define I2C_ISR_PECERR                      ((uint32_t)0x00000800)        /*!< PEC error in reception */
-#define I2C_ISR_TIMEOUT                     ((uint32_t)0x00001000)        /*!< Timeout or Tlow detection flag */
-#define I2C_ISR_ALERT                       ((uint32_t)0x00002000)        /*!< SMBus alert */
-#define I2C_ISR_BUSY                        ((uint32_t)0x00008000)        /*!< Bus busy */
-#define I2C_ISR_DIR                         ((uint32_t)0x00010000)        /*!< Transfer direction (slave mode) */
-#define I2C_ISR_ADDCODE                     ((uint32_t)0x00FE0000)        /*!< Address match code (slave mode) */
-
-/******************  Bit definition for I2C_ICR register  *********************/
-#define I2C_ICR_ADDRCF                      ((uint32_t)0x00000008)        /*!< Address matched clear flag */
-#define I2C_ICR_NACKCF                      ((uint32_t)0x00000010)        /*!< NACK clear flag */
-#define I2C_ICR_STOPCF                      ((uint32_t)0x00000020)        /*!< STOP detection clear flag */
-#define I2C_ICR_BERRCF                      ((uint32_t)0x00000100)        /*!< Bus error clear flag */
-#define I2C_ICR_ARLOCF                      ((uint32_t)0x00000200)        /*!< Arbitration lost clear flag */
-#define I2C_ICR_OVRCF                       ((uint32_t)0x00000400)        /*!< Overrun/Underrun clear flag */
-#define I2C_ICR_PECCF                       ((uint32_t)0x00000800)        /*!< PAC error clear flag */
-#define I2C_ICR_TIMOUTCF                    ((uint32_t)0x00001000)        /*!< Timeout clear flag */
-#define I2C_ICR_ALERTCF                     ((uint32_t)0x00002000)        /*!< Alert clear flag */
-
-/******************  Bit definition for I2C_PECR register  *********************/
-#define I2C_PECR_PEC                        ((uint32_t)0x000000FF)       /*!< PEC register */
-
-/******************  Bit definition for I2C_RXDR register  *********************/
-#define I2C_RXDR_RXDATA                     ((uint32_t)0x000000FF)       /*!< 8-bit receive data */
-
-/******************  Bit definition for I2C_TXDR register  *********************/
-#define I2C_TXDR_TXDATA                     ((uint32_t)0x000000FF)       /*!< 8-bit transmit data */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_KR_KEY                         ((uint32_t)0x0000FFFF)       /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define IWDG_PR_PR                          ((uint32_t)0x00000007)       /*!< PR[2:0] (Prescaler divider) */
-#define IWDG_PR_PR_0                        ((uint32_t)0x00000001)       /*!< Bit 0 */
-#define IWDG_PR_PR_1                        ((uint32_t)0x00000002)       /*!< Bit 1 */
-#define IWDG_PR_PR_2                        ((uint32_t)0x00000004)       /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define IWDG_RLR_RL                         ((uint32_t)0x00000FFF)       /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define IWDG_SR_PVU                         ((uint32_t)0x00000001)       /*!< Watchdog prescaler value update */
-#define IWDG_SR_RVU                         ((uint32_t)0x00000002)       /*!< Watchdog counter reload value update */
-#define IWDG_SR_WVU                         ((uint32_t)0x00000004)       /*!< Watchdog counter window value update */
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define IWDG_WINR_WIN                       ((uint32_t)0x00000FFF)       /*!< Watchdog counter window value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */
-#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */
-#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */
-#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */
-
-#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */
-#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */
-#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */
-
-#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */
-#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */
-#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */
-#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */
-
-#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */
-#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */
-#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Low Power Timer (LPTTIM)                           */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for LPTIM_ISR register  *******************/
-#define LPTIM_ISR_CMPM                         ((uint32_t)0x00000001)            /*!< Compare match */
-#define LPTIM_ISR_ARRM                         ((uint32_t)0x00000002)            /*!< Autoreload match */
-#define LPTIM_ISR_EXTTRIG                      ((uint32_t)0x00000004)            /*!< External trigger edge event */
-#define LPTIM_ISR_CMPOK                        ((uint32_t)0x00000008)            /*!< Compare register update OK */
-#define LPTIM_ISR_ARROK                        ((uint32_t)0x00000010)            /*!< Autoreload register update OK */
-#define LPTIM_ISR_UP                           ((uint32_t)0x00000020)            /*!< Counter direction change down to up */
-#define LPTIM_ISR_DOWN                         ((uint32_t)0x00000040)            /*!< Counter direction change up to down */
-
-/******************  Bit definition for LPTIM_ICR register  *******************/
-#define LPTIM_ICR_CMPMCF                       ((uint32_t)0x00000001)            /*!< Compare match Clear Flag */
-#define LPTIM_ICR_ARRMCF                       ((uint32_t)0x00000002)            /*!< Autoreload match Clear Flag */
-#define LPTIM_ICR_EXTTRIGCF                    ((uint32_t)0x00000004)            /*!< External trigger edge event Clear Flag */
-#define LPTIM_ICR_CMPOKCF                      ((uint32_t)0x00000008)            /*!< Compare register update OK Clear Flag */
-#define LPTIM_ICR_ARROKCF                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Clear Flag */
-#define LPTIM_ICR_UPCF                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Clear Flag */
-#define LPTIM_ICR_DOWNCF                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Clear Flag */
-
-/******************  Bit definition for LPTIM_IER register ********************/
-#define LPTIM_IER_CMPMIE                       ((uint32_t)0x00000001)            /*!< Compare match Interrupt Enable */
-#define LPTIM_IER_ARRMIE                       ((uint32_t)0x00000002)            /*!< Autoreload match Interrupt Enable */
-#define LPTIM_IER_EXTTRIGIE                    ((uint32_t)0x00000004)            /*!< External trigger edge event Interrupt Enable */
-#define LPTIM_IER_CMPOKIE                      ((uint32_t)0x00000008)            /*!< Compare register update OK Interrupt Enable */
-#define LPTIM_IER_ARROKIE                      ((uint32_t)0x00000010)            /*!< Autoreload register update OK Interrupt Enable */
-#define LPTIM_IER_UPIE                         ((uint32_t)0x00000020)            /*!< Counter direction change down to up Interrupt Enable */
-#define LPTIM_IER_DOWNIE                       ((uint32_t)0x00000040)            /*!< Counter direction change up to down Interrupt Enable */
-
-/******************  Bit definition for LPTIM_CFGR register *******************/
-#define LPTIM_CFGR_CKSEL                       ((uint32_t)0x00000001)             /*!< Clock selector */
-
-#define LPTIM_CFGR_CKPOL                       ((uint32_t)0x00000006)             /*!< CKPOL[1:0] bits (Clock polarity) */
-#define LPTIM_CFGR_CKPOL_0                     ((uint32_t)0x00000002)             /*!< Bit 0 */
-#define LPTIM_CFGR_CKPOL_1                     ((uint32_t)0x00000004)             /*!< Bit 1 */
-
-#define LPTIM_CFGR_CKFLT                       ((uint32_t)0x00000018)             /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
-#define LPTIM_CFGR_CKFLT_0                     ((uint32_t)0x00000008)             /*!< Bit 0 */
-#define LPTIM_CFGR_CKFLT_1                     ((uint32_t)0x00000010)             /*!< Bit 1 */
-
-#define LPTIM_CFGR_TRGFLT                      ((uint32_t)0x000000C0)             /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
-#define LPTIM_CFGR_TRGFLT_0                    ((uint32_t)0x00000040)             /*!< Bit 0 */
-#define LPTIM_CFGR_TRGFLT_1                    ((uint32_t)0x00000080)             /*!< Bit 1 */
-
-#define LPTIM_CFGR_PRESC                       ((uint32_t)0x00000E00)             /*!< PRESC[2:0] bits (Clock prescaler) */
-#define LPTIM_CFGR_PRESC_0                     ((uint32_t)0x00000200)             /*!< Bit 0 */
-#define LPTIM_CFGR_PRESC_1                     ((uint32_t)0x00000400)             /*!< Bit 1 */
-#define LPTIM_CFGR_PRESC_2                     ((uint32_t)0x00000800)             /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGSEL                     ((uint32_t)0x0000E000)             /*!< TRIGSEL[2:0]] bits (Trigger selector) */
-#define LPTIM_CFGR_TRIGSEL_0                   ((uint32_t)0x00002000)             /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGSEL_1                   ((uint32_t)0x00004000)             /*!< Bit 1 */
-#define LPTIM_CFGR_TRIGSEL_2                   ((uint32_t)0x00008000)             /*!< Bit 2 */
-
-#define LPTIM_CFGR_TRIGEN                      ((uint32_t)0x00060000)             /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
-#define LPTIM_CFGR_TRIGEN_0                    ((uint32_t)0x00020000)             /*!< Bit 0 */
-#define LPTIM_CFGR_TRIGEN_1                    ((uint32_t)0x00040000)             /*!< Bit 1 */
-
-#define LPTIM_CFGR_TIMOUT                      ((uint32_t)0x00080000)             /*!< Timout enable */
-#define LPTIM_CFGR_WAVE                        ((uint32_t)0x00100000)             /*!< Waveform shape */
-#define LPTIM_CFGR_WAVPOL                      ((uint32_t)0x00200000)             /*!< Waveform shape polarity */
-#define LPTIM_CFGR_PRELOAD                     ((uint32_t)0x00400000)             /*!< Reg update mode */
-#define LPTIM_CFGR_COUNTMODE                   ((uint32_t)0x00800000)             /*!< Counter mode enable */
-#define LPTIM_CFGR_ENC                         ((uint32_t)0x01000000)             /*!< Encoder mode enable */
-
-/******************  Bit definition for LPTIM_CR register  ********************/
-#define LPTIM_CR_ENABLE                        ((uint32_t)0x00000001)             /*!< LPTIMer enable */
-#define LPTIM_CR_SNGSTRT                       ((uint32_t)0x00000002)             /*!< Timer start in single mode */
-#define LPTIM_CR_CNTSTRT                       ((uint32_t)0x00000004)             /*!< Timer start in continuous mode */
-
-/******************  Bit definition for LPTIM_CMP register  *******************/
-#define LPTIM_CMP_CMP                          ((uint32_t)0x0000FFFF)             /*!< Compare register */
-
-/******************  Bit definition for LPTIM_ARR register  *******************/
-#define LPTIM_ARR_ARR                          ((uint32_t)0x0000FFFF)             /*!< Auto reload register */
-
-/******************  Bit definition for LPTIM_CNT register  *******************/
-#define LPTIM_CNT_CNT                          ((uint32_t)0x0000FFFF)             /*!< Counter register */
-
-/******************************************************************************/
-/*                                                                            */
-/*                            MIFARE   Firewall                               */
-/*                                                                            */
-/******************************************************************************/
-
-/*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
-#define FW_CSSA_ADD                         ((uint32_t)0x00FFFF00)        /*!< Code Segment Start Address */ 
-#define FW_CSL_LENG                         ((uint32_t)0x003FFF00)        /*!< Code Segment Length        */  
-#define FW_NVDSSA_ADD                       ((uint32_t)0x00FFFF00)        /*!< Non Volatile Dat Segment Start Address */ 
-#define FW_NVDSL_LENG                       ((uint32_t)0x003FFF00)        /*!< Non Volatile Data Segment Length */ 
-#define FW_VDSSA_ADD                        ((uint32_t)0x0000FFC0)        /*!< Volatile Data Segment Start Address */ 
-#define FW_VDSL_LENG                        ((uint32_t)0x0000FFC0)        /*!< Volatile Data Segment Length */ 
-
-/**************************Bit definition for CR register *********************/
-#define FW_CR_FPA                           ((uint32_t)0x00000001)         /*!< Firewall Pre Arm*/ 
-#define FW_CR_VDS                           ((uint32_t)0x00000002)         /*!< Volatile Data Sharing*/ 
-#define FW_CR_VDE                           ((uint32_t)0x00000004)         /*!< Volatile Data Execution*/ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define PWR_CR_LPSDSR                       ((uint32_t)0x00000001)     /*!< Low-power deepsleep/sleep/low power run */
-#define PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep */
-#define PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag */
-#define PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag */
-#define PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable */
-
-#define PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
-
-#define PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection */
-#define PWR_CR_ULP                          ((uint32_t)0x00000200)     /*!< Ultra Low Power mode */
-#define PWR_CR_FWU                          ((uint32_t)0x00000400)     /*!< Fast wakeup */
-
-#define PWR_CR_VOS                          ((uint32_t)0x00001800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define PWR_CR_VOS_0                        ((uint32_t)0x00000800)     /*!< Bit 0 */
-#define PWR_CR_VOS_1                        ((uint32_t)0x00001000)     /*!< Bit 1 */
-#define PWR_CR_DSEEKOFF                     ((uint32_t)0x00002000)     /*!< Deep Sleep mode with EEPROM kept Off */
-#define PWR_CR_LPRUN                        ((uint32_t)0x00004000)     /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag */
-#define PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag */
-#define PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output */
-#define PWR_CSR_VREFINTRDYF                 ((uint32_t)0x00000008)     /*!< Internal voltage reference (VREFINT) ready flag */
-#define PWR_CSR_VOSF                        ((uint32_t)0x00000010)     /*!< Voltage Scaling select flag */
-#define PWR_CSR_REGLPF                      ((uint32_t)0x00000020)     /*!< Regulator LP flag */
-
-#define PWR_CSR_EWUP1                       ((uint32_t)0x00000100)     /*!< Enable WKUP pin 1 */
-#define PWR_CSR_EWUP2                       ((uint32_t)0x00000200)     /*!< Enable WKUP pin 2 */
-#define PWR_CSR_EWUP3                       ((uint32_t)0x00000400)     /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Reset and Clock Control                            */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RCC_CR register  ********************/
-#define RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define RCC_CR_HSIKERON                     ((uint32_t)0x00000002)        /*!< Internal High Speed clock enable for some IPs Kernel */
-#define RCC_CR_HSIRDY                       ((uint32_t)0x00000004)        /*!< Internal High Speed clock ready flag */
-#define RCC_CR_HSIDIVEN                     ((uint32_t)0x00000008)        /*!< Internal High Speed clock divider enable */
-#define RCC_CR_HSIDIVF                      ((uint32_t)0x00000010)        /*!< Internal High Speed clock divider flag */
-#define RCC_CR_HSIOUTEN                     ((uint32_t)0x00000020)        /*!< Internal High Speed clock out enable */
-#define RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
-#define RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
-#define RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-#define RCC_CR_CSSHSEON                     ((uint32_t)0x00080000)        /*!< HSE Clock Security System enable */
-#define RCC_CR_RTCPRE                       ((uint32_t)0x00300000)        /*!< RTC/LCD prescaler [1:0] bits */
-#define RCC_CR_RTCPRE_0                     ((uint32_t)0x00100000)        /*!< RTC/LCD prescaler Bit 0 */
-#define RCC_CR_RTCPRE_1                     ((uint32_t)0x00200000)        /*!< RTC/LCD prescaler Bit 1 */
-#define RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
-#define RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
-
-#define RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
-#define RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
-#define RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CRRCR register  *****************/
-#define RCC_CRRCR_HSI48ON                   ((uint32_t)0x00000001)        /*!< HSI 48MHz clock enable */
-#define RCC_CRRCR_HSI48RDY                  ((uint32_t)0x00000002)        /*!< HSI 48MHz clock ready flag */
-#define RCC_CRRCR_HSI48DIV6OUTEN            ((uint32_t)0x00000004)        /*!< HSI 48MHz DIV6 out enable */
-#define RCC_CRRCR_HSI48CAL                  ((uint32_t)0x0000FF00)        /*!< HSI 48MHz clock Calibration */
-
-/*******************  Bit definition for RCC_CFGR register  *******************/
-/*!< SW configuration */
-#define RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-#define RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
-#define RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
-#define RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
-#define RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
-
-/*!< SWS configuration */
-#define RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-#define RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
-#define RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
-#define RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
-
-/*!< HPRE configuration */
-#define RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-#define RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-/*!< PPRE1 configuration */
-#define RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-/*!< PPRE2 configuration */
-#define RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-#define RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-#define RCC_CFGR_STOPWUCK                   ((uint32_t)0x00008000)        /*!< Wake Up from Stop Clock selection */
-
-/*!< PLL entry clock source*/
-#define RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
-#define RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-#define RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
-#define RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
-#define RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
-#define RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
-#define RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
-#define RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
-#define RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
-#define RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
-#define RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
-#define RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
-
-#define RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
-#define RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
-#define RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
-
-/*!< MCO configuration */
-#define RCC_CFGR_MCOSEL                     ((uint32_t)0x0F000000)        /*!< MCO[3:0] bits (Microcontroller Clock Output) */
-#define RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define RCC_CFGR_MCOSEL_3                   ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected as MCO source */
-#define RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
-#define RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
-#define RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
-#define RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
-#define RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
-#define RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
-#define RCC_CFGR_MCO_HSI48                  ((uint32_t)0x08000000)        /*!< HSI48 clock selected as MCO source */
-
-#define RCC_CFGR_MCO_PRE                    ((uint32_t)0x70000000)        /*!< MCO prescaler */
-#define RCC_CFGR_MCO_PRE_1                  ((uint32_t)0x00000000)        /*!< MCO is divided by 1 */
-#define RCC_CFGR_MCO_PRE_2                  ((uint32_t)0x10000000)        /*!< MCO is divided by 2 */
-#define RCC_CFGR_MCO_PRE_4                  ((uint32_t)0x20000000)        /*!< MCO is divided by 4 */
-#define RCC_CFGR_MCO_PRE_8                  ((uint32_t)0x30000000)        /*!< MCO is divided by 8 */
-#define RCC_CFGR_MCO_PRE_16                 ((uint32_t)0x40000000)        /*!< MCO is divided by 16 */
-
-/*!<******************  Bit definition for RCC_CIER register  ********************/
-#define RCC_CIER_LSIRDYIE                   ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt Enable */
-#define RCC_CIER_LSERDYIE                   ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt Enable */
-#define RCC_CIER_HSIRDYIE                   ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt Enable */
-#define RCC_CIER_HSERDYIE                   ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt Enable */
-#define RCC_CIER_PLLRDYIE                   ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt Enable */
-#define RCC_CIER_MSIRDYIE                   ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt Enable */
-#define RCC_CIER_HSI48RDYIE                 ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt Enable */
-#define RCC_CIER_LSECSSIE                   ((uint32_t)0x00000080)        /*!< LSE CSS Interrupt Enable */
-
-/*!<******************  Bit definition for RCC_CIFR register  ********************/
-#define RCC_CIFR_LSIRDYF                    ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define RCC_CIFR_LSERDYF                    ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define RCC_CIFR_HSIRDYF                    ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define RCC_CIFR_HSERDYF                    ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define RCC_CIFR_PLLRDYF                    ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define RCC_CIFR_MSIRDYF                    ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
-#define RCC_CIFR_HSI48RDYF                  ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt flag */
-#define RCC_CIFR_LSECSSF                    ((uint32_t)0x00000080)        /*!< LSE Clock Security System Interrupt flag */
-#define RCC_CIFR_CSSF                       ((uint32_t)0x00000100)        /*!< Clock Security System Interrupt flag */
-
-/*!<******************  Bit definition for RCC_CICR register  ********************/
-#define RCC_CICR_LSIRDYC                    ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt Clear */
-#define RCC_CICR_LSERDYC                    ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt Clear */
-#define RCC_CICR_HSIRDYC                    ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt Clear */
-#define RCC_CICR_HSERDYC                    ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt Clear */
-#define RCC_CICR_PLLRDYC                    ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt Clear */
-#define RCC_CICR_MSIRDYC                    ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt Clear */
-#define RCC_CICR_HSI48RDYC                  ((uint32_t)0x00000040)        /*!< HSI48 Ready Interrupt Clear */
-#define RCC_CICR_LSECSSC                    ((uint32_t)0x00000080)        /*!< LSE Clock Security System Interrupt Clear */
-#define RCC_CICR_CSSC                       ((uint32_t)0x00000100)        /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_IOPRSTR register  ******************/
-#define RCC_IOPRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
-#define RCC_IOPRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
-#define RCC_IOPRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
-#define RCC_IOPRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
-#define RCC_IOPRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */
-#define RCC_IOPRSTR_GPIOHRST                ((uint32_t)0x00000080)        /*!< GPIO port H reset */
-
-/******************  Bit definition for RCC_AHBRST register  ******************/
-#define RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x00000001)        /*!< DMA1 reset */
-#define RCC_AHBRSTR_MIFRST                  ((uint32_t)0x00000100)        /*!< Memory interface reset reset */
-#define RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
-#define RCC_AHBRSTR_TSCRST                  ((uint32_t)0x00010000)        /*!< TSC reset */
-#define RCC_AHBRSTR_RNGRST                  ((uint32_t)0x00100000)        /*!< RNG reset */
-
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< SYSCFG clock reset */
-#define RCC_APB2RSTR_TIM21RST               ((uint32_t)0x00000004)        /*!< TIM21 clock reset */
-#define RCC_APB2RSTR_TIM22RST               ((uint32_t)0x00000020)        /*!< TIM22 clock reset */
-#define RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 clock reset */
-#define RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 clock reset */
-#define RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 clock reset */
-#define RCC_APB2RSTR_DBGMCURST              ((uint32_t)0x00400000)        /*!< DBGMCU clock reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 clock reset */
-#define RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 clock reset */
-#define RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 clock reset */
-#define RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 clock reset */
-#define RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD clock reset */
-#define RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog clock reset */
-#define RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI2 clock reset */
-#define RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 clock reset */
-#define RCC_APB1RSTR_LPUART1RST             ((uint32_t)0x00040000)        /*!< LPUART1 clock reset */
-#define RCC_APB1RSTR_USART4RST              ((uint32_t)0x00080000)        /*!< USART4 clock reset */
-#define RCC_APB1RSTR_USART5RST              ((uint32_t)0x00100000)        /*!< USART5 clock reset */
-#define RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 clock reset */
-#define RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 clock reset */
-#define RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB clock reset */
-#define RCC_APB1RSTR_CRSRST                 ((uint32_t)0x08000000)        /*!< CRS clock reset */
-#define RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< PWR clock reset */
-#define RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC clock reset */
-#define RCC_APB1RSTR_I2C3RST                ((uint32_t)0x40000000)        /*!< I2C 3 clock reset */
-#define RCC_APB1RSTR_LPTIM1RST              ((uint32_t)0x80000000)        /*!< LPTIM1 clock reset */
-
-/*****************  Bit definition for RCC_IOPENR register  ******************/
-#define RCC_IOPENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
-#define RCC_IOPENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
-#define RCC_IOPENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
-#define RCC_IOPENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
-#define RCC_IOPENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */
-#define RCC_IOPENR_GPIOHEN                  ((uint32_t)0x00000080)        /*!< GPIO port H clock enable */
-
-/*****************  Bit definition for RCC_AHBENR register  ******************/
-#define RCC_AHBENR_DMA1EN                   ((uint32_t)0x00000001)        /*!< DMA1 clock enable */
-#define RCC_AHBENR_MIFEN                    ((uint32_t)0x00000100)        /*!< NVM interface clock enable bit */
-#define RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
-#define RCC_AHBENR_TSCEN                    ((uint32_t)0x00010000)        /*!< TSC clock enable */
-#define RCC_AHBENR_RNGEN                    ((uint32_t)0x00100000)        /*!< RNG clock enable */
-
-/*****************  Bit definition for RCC_APB2ENR register  ******************/
-#define RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)        /*!< SYSCFG clock enable */
-#define RCC_APB2ENR_TIM21EN                 ((uint32_t)0x00000004)        /*!< TIM21 clock enable */
-#define RCC_APB2ENR_TIM22EN                 ((uint32_t)0x00000020)        /*!< TIM22 clock enable */
-#define RCC_APB2ENR_MIFIEN                  ((uint32_t)0x00000080)        /*!< MiFare Firewall clock enable */
-#define RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)        /*!< ADC1 clock enable */
-#define RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)        /*!< SPI1 clock enable */
-#define RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)        /*!< USART1 clock enable */
-#define RCC_APB2ENR_DBGMCUEN                ((uint32_t)0x00400000)        /*!< DBGMCU clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enable */
-#define RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
-#define RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */
-#define RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI2 clock enable */
-#define RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART2 clock enable */
-#define RCC_APB1ENR_LPUART1EN               ((uint32_t)0x00040000)        /*!< LPUART1 clock enable */
-#define RCC_APB1ENR_USART4EN                ((uint32_t)0x00080000)        /*!< USART4 clock enable */
-#define RCC_APB1ENR_USART5EN                ((uint32_t)0x00100000)        /*!< USART5 clock enable */
-#define RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C1 clock enable */
-#define RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C2 clock enable */
-#define RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
-#define RCC_APB1ENR_CRSEN                   ((uint32_t)0x08000000)        /*!< CRS clock enable */
-#define RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< PWR clock enable */
-#define RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC clock enable */
-#define RCC_APB1ENR_I2C3EN                  ((uint32_t)0x40000000)        /*!< I2C3 clock enable */
-#define RCC_APB1ENR_LPTIM1EN                ((uint32_t)0x80000000)        /*!< LPTIM1 clock enable */
-
-/******************  Bit definition for RCC_IOPSMENR register  ****************/
-#define RCC_IOPSMENR_GPIOASMEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOBSMEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOCSMEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIODSMEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOESMEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */
-#define RCC_IOPSMENR_GPIOHSMEN              ((uint32_t)0x00000080)        /*!< GPIO port H clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_AHBSMENR register  ******************/
-#define RCC_AHBSMENR_DMA1SMEN               ((uint32_t)0x00000001)        /*!< DMA1 clock enabled in sleep mode */
-#define RCC_AHBSMENR_MIFSMEN                ((uint32_t)0x00000100)        /*!< NVM interface clock enable during sleep mode */
-#define RCC_AHBSMENR_SRAMSMEN               ((uint32_t)0x00000200)        /*!< SRAM clock enabled in sleep mode */
-#define RCC_AHBSMENR_CRCSMEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
-#define RCC_AHBSMENR_TSCSMEN                ((uint32_t)0x00010000)        /*!< TSC clock enabled in sleep mode */
-#define RCC_AHBSMENR_RNGSMEN                ((uint32_t)0x00100000)        /*!< RNG clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB2SMENR register  ******************/
-#define RCC_APB2SMENR_SYSCFGSMEN            ((uint32_t)0x00000001)        /*!< SYSCFG clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM21SMEN             ((uint32_t)0x00000004)        /*!< TIM21 clock enabled in sleep mode */
-#define RCC_APB2SMENR_TIM22SMEN             ((uint32_t)0x00000020)        /*!< TIM22 clock enabled in sleep mode */
-#define RCC_APB2SMENR_ADC1SMEN              ((uint32_t)0x00000200)        /*!< ADC1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_SPI1SMEN              ((uint32_t)0x00001000)        /*!< SPI1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_USART1SMEN            ((uint32_t)0x00004000)        /*!< USART1 clock enabled in sleep mode */
-#define RCC_APB2SMENR_DBGMCUSMEN            ((uint32_t)0x00400000)        /*!< DBGMCU clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1SMENR register  ******************/
-#define RCC_APB1SMENR_TIM2SMEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM3SMEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM6SMEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
-#define RCC_APB1SMENR_TIM7SMEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LCDSMEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */
-#define RCC_APB1SMENR_WWDGSMEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
-#define RCC_APB1SMENR_SPI2SMEN              ((uint32_t)0x00004000)        /*!< SPI2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART2SMEN            ((uint32_t)0x00020000)        /*!< USART2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPUART1SMEN           ((uint32_t)0x00040000)        /*!< LPUART1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART4SMEN            ((uint32_t)0x00080000)        /*!< USART4 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USART5SMEN            ((uint32_t)0x00100000)        /*!< USART5 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C1SMEN              ((uint32_t)0x00200000)        /*!< I2C1 clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C2SMEN              ((uint32_t)0x00400000)        /*!< I2C2 clock enabled in sleep mode */
-#define RCC_APB1SMENR_USBSMEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
-#define RCC_APB1SMENR_CRSSMEN               ((uint32_t)0x08000000)        /*!< CRS clock enabled in sleep mode */
-#define RCC_APB1SMENR_PWRSMEN                ((uint32_t)0x10000000)       /*!< PWR clock enabled in sleep mode */
-#define RCC_APB1SMENR_DACSMEN               ((uint32_t)0x20000000)        /*!< DAC clock enabled in sleep mode */
-#define RCC_APB1SMENR_I2C3SMEN              ((uint32_t)0x40000000)        /*!< I2C3 clock enabled in sleep mode */
-#define RCC_APB1SMENR_LPTIM1SMEN            ((uint32_t)0x80000000)        /*!< LPTIM1 clock enabled in sleep mode */
-
-/*******************  Bit definition for RCC_CCIPR register  *******************/
-/*!< USART1 Clock source selection */
-#define RCC_CCIPR_USART1SEL                 ((uint32_t)0x00000003)        /*!< USART1SEL[1:0] bits */
-#define RCC_CCIPR_USART1SEL_0               ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define RCC_CCIPR_USART1SEL_1               ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-/*!< USART2 Clock source selection */
-#define RCC_CCIPR_USART2SEL                 ((uint32_t)0x0000000C)        /*!< USART2SEL[1:0] bits */
-#define RCC_CCIPR_USART2SEL_0               ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define RCC_CCIPR_USART2SEL_1               ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-/*!< LPUART1 Clock source selection */ 
-#define RCC_CCIPR_LPUART1SEL                ((uint32_t)0x0000C00)         /*!< LPUART1SEL[1:0] bits */
-#define RCC_CCIPR_LPUART1SEL_0              ((uint32_t)0x0000400)         /*!< Bit 0 */
-#define RCC_CCIPR_LPUART1SEL_1              ((uint32_t)0x0000800)         /*!< Bit 1 */
-
-/*!< I2C1 Clock source selection */
-#define RCC_CCIPR_I2C1SEL                   ((uint32_t)0x00003000)        /*!< I2C1SEL [1:0] bits */
-#define RCC_CCIPR_I2C1SEL_0                 ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define RCC_CCIPR_I2C1SEL_1                 ((uint32_t)0x00002000)        /*!< Bit 1 */
-
-/*!< I2C3 Clock source selection */
-#define RCC_CCIPR_I2C3SEL                   ((uint32_t)0x00030000)        /*!< I2C3SEL [1:0] bits */
-#define RCC_CCIPR_I2C3SEL_0                 ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define RCC_CCIPR_I2C3SEL_1                 ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-/*!< LPTIM1 Clock source selection */ 
-#define RCC_CCIPR_LPTIM1SEL                 ((uint32_t)0x000C0000)        /*!< LPTIM1SEL [1:0] bits */
-#define RCC_CCIPR_LPTIM1SEL_0               ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define RCC_CCIPR_LPTIM1SEL_1               ((uint32_t)0x00080000)        /*!< Bit 1 */
-
-/*!< HSI48 Clock source selection */ 
-#define RCC_CCIPR_HSI48SEL                  ((uint32_t)0x04000000)        /*!< HSI48 RC clock source selection bit for USB and RNG*/
-
-/* Bit name alias maintained for legacy */
-#define RCC_CCIPR_HSI48MSEL                 RCC_CCIPR_HSI48SEL
-
-/*******************  Bit definition for RCC_CSR register  *******************/
-#define RCC_CSR_LSION                       ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define RCC_CSR_LSIRDY                      ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-
-#define RCC_CSR_LSEON                       ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
-#define RCC_CSR_LSERDY                      ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
-#define RCC_CSR_LSEBYP                      ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
-                                             
-#define RCC_CSR_LSEDRV                      ((uint32_t)0x00001800)        /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
-#define RCC_CSR_LSEDRV_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define RCC_CSR_LSEDRV_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-                                             
-#define RCC_CSR_LSECSSON                    ((uint32_t)0x00002000)        /*!< External Low Speed oscillator CSS Enable */
-#define RCC_CSR_LSECSSD                     ((uint32_t)0x00004000)        /*!< External Low Speed oscillator CSS Detected */
-                                             
-/*!< RTC congiguration */                    
-#define RCC_CSR_RTCSEL                      ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define RCC_CSR_RTCSEL_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define RCC_CSR_RTCSEL_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */
-                                             
-#define RCC_CSR_RTCSEL_NOCLOCK              ((uint32_t)0x00000000)        /*!< No clock */
-#define RCC_CSR_RTCSEL_LSE                  ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_LSI                  ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
-#define RCC_CSR_RTCSEL_HSE                  ((uint32_t)0x00030000)        /*!< HSE oscillator clock used as RTC clock */
-                                             
-#define RCC_CSR_RTCEN                       ((uint32_t)0x00040000)        /*!< RTC clock enable */
-#define RCC_CSR_RTCRST                      ((uint32_t)0x00080000)        /*!< RTC software reset  */
-
-#define RCC_CSR_RMVF                        ((uint32_t)0x00800000)        /*!< Remove reset flag */
-#define RCC_CSR_FWRSTF                      ((uint32_t)0x01000000)        /*!< Mifare Firewall reset flag */
-#define RCC_CSR_OBL                         ((uint32_t)0x02000000)        /*!< OBL reset flag */
-#define RCC_CSR_PINRSTF                     ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define RCC_CSR_PORRSTF                     ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define RCC_CSR_SFTRSTF                     ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define RCC_CSR_IWDGRSTF                    ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define RCC_CSR_WWDGRSTF                    ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define RCC_CSR_LPWRRSTF                    ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                                    RNG                                     */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RNG_CR register  *******************/
-#define RNG_CR_RNGEN                         ((uint32_t)0x00000004)
-#define RNG_CR_IE                            ((uint32_t)0x00000008)
-
-/********************  Bits definition for RNG_SR register  *******************/
-#define RNG_SR_DRDY                          ((uint32_t)0x00000001)
-#define RNG_SR_CECS                          ((uint32_t)0x00000002)
-#define RNG_SR_SECS                          ((uint32_t)0x00000004)
-#define RNG_SR_CEIS                          ((uint32_t)0x00000020)
-#define RNG_SR_SEIS                          ((uint32_t)0x00000040)
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TR_HT                            ((uint32_t)0x00300000)        /*!<  */
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)        /*!<  */
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TR_ST                            ((uint32_t)0x00000070)        /*!<  */
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)        /*!<  */
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)        /*!<  */
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)        /*!<  */
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)        /*!<  */
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)        /*!<  */
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)        /*!<  */
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)        /*!<  */
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)        /*!<  */
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)        /*!<  */
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)        /*!<  */
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)        /*!<  */
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)        /*!<  */
-#define RTC_DR_MT                            ((uint32_t)0x00001000)        /*!<  */
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)        /*!<  */
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)        /*!<  */
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)        /*!<  */
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)        /*!<  */
-#define RTC_DR_DT                            ((uint32_t)0x00000030)        /*!<  */
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)        /*!<  */
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)        /*!<  */
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)        /*!<  */
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)        /*!<  */
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)        /*!<  */
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)        /*!<  */
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)        /*!<  */
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_CR_POL                           ((uint32_t)0x00100000)        /*!<  */
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)        /*!<  */
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)        /*!<  */
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)        /*!<  */
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)        /*!<  */
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)        /*!<  */
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)        /*!<  */
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)        /*!<  */
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)        /*!<  */
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)        /*!<  */
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)        /*!<  */
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)        /*!<  */
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)        /*!<  */
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)        /*!<  */
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)        /*!<  */
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)        /*!<  */
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)        /*!<  */
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)        /*!<  */
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)        /*!<  */
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)        /*!<  */
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)        /*!<  */
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)        /*!<  */
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)        /*!<  */
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)        /*!<  */
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)        /*!<  */
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)        /*!<  */
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)        /*!<  */
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)        /*!<  */
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)        /*!<  */
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)        /*!<  */
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)        /*!<  */
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)        /*!<  */
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)        /*!<  */
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)        /*!<  */
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)        /*!<  */
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)        /*!<  */
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)        /*!<  */
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)        /*!<  */
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)        /*!<  */
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)        /*!<  */
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)        /*!<  */
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)        /*!<  */
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)        /*!<  */
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)        /*!<  */
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)        /*!<  */
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)        /*!<  */
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)        /*!<  */
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)        /*!<  */
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)        /*!<  */
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)        /*!<  */
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)        /*!<  */
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)        /*!<  */
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)        /*!<  */
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)        /*!<  */
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)        /*!<  */
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)        /*!<  */
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)        /*!<  */
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)        /*!<  */
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)        /*!<  */
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)        /*!<  */
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)        /*!<  */
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)        /*!<  */
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)        /*!<  */
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)        /*!<  */
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)        /*!<  */
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)        /*!<  */
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)        /*!<  */
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)        /*!<  */
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)        /*!<  */
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)        /*!<  */
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)        /*!<  */
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)        /*!<  */
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)        /*!<  */
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)        /*!<  */
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)        /*!<  */
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)        /*!<  */
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)        /*!<  */
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)        /*!<  */
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)        /*!<  */
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)        /*!<  */
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)        /*!<  */
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)        /*!<  */
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)        /*!<  */
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)        /*!<  */
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)        /*!<  */
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)        /*!<  */
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)        /*!<  */
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)        /*!<  */
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)        /*!<  */
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)        /*!<  */
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)        /*!<  */
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)        /*!<  */
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)        /*!<  */
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)        /*!<  */
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)        /*!<  */
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)        /*!<  */
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)        /*!<  */
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)        /*!<  */
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)        /*!<  */
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)        /*!<  */
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CAL_CALP                         ((uint32_t)0x00008000)        /*!<  */
-#define RTC_CAL_CALW8                        ((uint32_t)0x00004000)        /*!<  */
-#define RTC_CAL_CALW16                       ((uint32_t)0x00002000)        /*!<  */
-#define RTC_CAL_CALM                         ((uint32_t)0x000001FF)        /*!<  */
-#define RTC_CAL_CALM_0                       ((uint32_t)0x00000001)        /*!<  */
-#define RTC_CAL_CALM_1                       ((uint32_t)0x00000002)        /*!<  */
-#define RTC_CAL_CALM_2                       ((uint32_t)0x00000004)        /*!<  */
-#define RTC_CAL_CALM_3                       ((uint32_t)0x00000008)        /*!<  */
-#define RTC_CAL_CALM_4                       ((uint32_t)0x00000010)        /*!<  */
-#define RTC_CAL_CALM_5                       ((uint32_t)0x00000020)        /*!<  */
-#define RTC_CAL_CALM_6                       ((uint32_t)0x00000040)        /*!<  */
-#define RTC_CAL_CALM_7                       ((uint32_t)0x00000080)        /*!<  */
-#define RTC_CAL_CALM_8                       ((uint32_t)0x00000100)        /*!<  */
-
-/********************  Bits definition for RTC_TAMPCR register  ****************/
-#define RTC_TAMPCR_TAMP3MF                   ((uint32_t)0x01000000)        /*!<  */
-#define RTC_TAMPCR_TAMP3NOERASE              ((uint32_t)0x00800000)        /*!<  */
-#define RTC_TAMPCR_TAMP3IE                   ((uint32_t)0x00400000)        /*!<  */
-#define RTC_TAMPCR_TAMP2MF                   ((uint32_t)0x00200000)        /*!<  */
-#define RTC_TAMPCR_TAMP2NOERASE              ((uint32_t)0x00100000)        /*!<  */
-#define RTC_TAMPCR_TAMP2IE                   ((uint32_t)0x00080000)        /*!<  */
-#define RTC_TAMPCR_TAMP1MF                   ((uint32_t)0x00040000)        /*!<  */
-#define RTC_TAMPCR_TAMP1NOERASE              ((uint32_t)0x00020000)        /*!<  */
-#define RTC_TAMPCR_TAMP1IE                   ((uint32_t)0x00010000)        /*!<  */
-#define RTC_TAMPCR_TAMPPUDIS                 ((uint32_t)0x00008000)        /*!<  */
-#define RTC_TAMPCR_TAMPPRCH                  ((uint32_t)0x00006000)        /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_0                ((uint32_t)0x00002000)        /*!<  */
-#define RTC_TAMPCR_TAMPPRCH_1                ((uint32_t)0x00004000)        /*!<  */
-#define RTC_TAMPCR_TAMPFLT                   ((uint32_t)0x00001800)        /*!<  */
-#define RTC_TAMPCR_TAMPFLT_0                 ((uint32_t)0x00000800)        /*!<  */
-#define RTC_TAMPCR_TAMPFLT_1                 ((uint32_t)0x00001000)        /*!<  */
-#define RTC_TAMPCR_TAMPFREQ                  ((uint32_t)0x00000700)        /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_0                ((uint32_t)0x00000100)        /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_1                ((uint32_t)0x00000200)        /*!<  */
-#define RTC_TAMPCR_TAMPFREQ_2                ((uint32_t)0x00000400)        /*!<  */
-#define RTC_TAMPCR_TAMPTS                    ((uint32_t)0x00000080)        /*!<  */
-#define RTC_TAMPCR_TAMP3TRG                  ((uint32_t)0x00000040)        /*!<  */
-#define RTC_TAMPCR_TAMP3E                    ((uint32_t)0x00000020)        /*!<  */
-#define RTC_TAMPCR_TAMP2TRG                  ((uint32_t)0x00000010)        /*!<  */
-#define RTC_TAMPCR_TAMP2E                    ((uint32_t)0x00000008)        /*!<  */
-#define RTC_TAMPCR_TAMPIE                    ((uint32_t)0x00000004)        /*!<  */
-#define RTC_TAMPCR_TAMP1TRG                  ((uint32_t)0x00000002)        /*!<  */
-#define RTC_TAMPCR_TAMP1E                    ((uint32_t)0x00000001)        /*!<  */
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_OR register  ****************/
-#define RTC_OR_OUT_RMP                       ((uint32_t)0x00000002)        /*!<  */
-#define RTC_OR_ALARMOUTTYPE                  ((uint32_t)0x00000001)        /*!<  */
-
-/* Bit names aliases maintained for legacy */
-#define RTC_OR_RTC_OUT_RMP                   RTC_OR_OUT_RMP
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)        /*!<  */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Serial Peripheral Interface (SPI)                   */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!< Clock Phase */
-#define SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!< Clock Polarity */
-#define SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!< Master Selection */
-#define SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!< Bit 0 */
-#define SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!< Bit 1 */
-#define SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!< Bit 2 */
-#define SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!< SPI Enable */
-#define SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!< Frame Format */
-#define SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!< Internal slave select */
-#define SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!< Software slave management */
-#define SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!< Receive only */
-#define SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!< Data Frame Format */
-#define SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!< Transmit CRC next */
-#define SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!< Hardware CRC calculation enable */
-#define SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!< Output enable in bidirectional mode */
-#define SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)            /*!< Rx Buffer DMA Enable */
-#define SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)            /*!< Tx Buffer DMA Enable */
-#define SPI_CR2_SSOE                        ((uint32_t)0x00000004)            /*!< SS Output Enable */
-#define SPI_CR2_FRF                         ((uint32_t)0x00000010)            /*!< Frame Format Enable */
-#define SPI_CR2_ERRIE                       ((uint32_t)0x00000020)            /*!< Error Interrupt Enable */
-#define SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)            /*!< RX buffer Not Empty Interrupt Enable */
-#define SPI_CR2_TXEIE                       ((uint32_t)0x00000080)            /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define SPI_SR_RXNE                         ((uint32_t)0x00000001)            /*!< Receive buffer Not Empty */
-#define SPI_SR_TXE                          ((uint32_t)0x00000002)            /*!< Transmit buffer Empty */
-#define SPI_SR_CHSIDE                       ((uint32_t)0x00000004)            /*!< Channel side */
-#define SPI_SR_UDR                          ((uint32_t)0x00000008)            /*!< Underrun flag */
-#define SPI_SR_CRCERR                       ((uint32_t)0x00000010)            /*!< CRC Error flag */
-#define SPI_SR_MODF                         ((uint32_t)0x00000020)            /*!< Mode fault */
-#define SPI_SR_OVR                          ((uint32_t)0x00000040)            /*!< Overrun flag */
-#define SPI_SR_BSY                          ((uint32_t)0x00000080)            /*!< Busy flag */
-#define SPI_SR_FRE                          ((uint32_t)0x00000100)            /*!< TI frame format error */  
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
-#define SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
-#define SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity */
-#define SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization */
-#define SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable */
-#define SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
-#define SPI_I2SCFGR_ASTRTEN                 ((uint32_t)0x000001000)           /*!<Asynchronous start enable */
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler */
-#define SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_CFGR1 register  ****************/
-#define SYSCFG_CFGR1_MEM_MODE               ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_CFGR1_MEM_MODE_0             ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
-#define SYSCFG_CFGR1_MEM_MODE_1             ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
-#define SYSCFG_CFGR1_BOOT_MODE              ((uint32_t)0x00000300) /*!< SYSCFG_Boot mode Config */
-#define SYSCFG_CFGR1_BOOT_MOD_0             ((uint32_t)0x00000100) /*!< SYSCFG_Boot mode Config Bit 0 */
-#define SYSCFG_CFGR1_BOOT_MODE_1            ((uint32_t)0x00000200) /*!< SYSCFG_Boot mode Config Bit 1 */
-
-/*****************  Bit definition for SYSCFG_CFGR2 register  ****************/
-#define SYSCFG_CFGR2_FWDISEN                ((uint32_t)0x00000001) /*!< Firewall disable bit */
-#define SYSCFG_CFGR2_CAPA                   ((uint32_t)0x0000003E) /*!< Connection of internal Vlcd rail to external capacitors */
-#define SYSCFG_CFGR2_CAPA_0                 ((uint32_t)0x00000002)
-#define SYSCFG_CFGR2_CAPA_1                 ((uint32_t)0x00000004)
-#define SYSCFG_CFGR2_CAPA_2                 ((uint32_t)0x00000008)
-#define SYSCFG_CFGR2_CAPA_3                 ((uint32_t)0x00000010)
-#define SYSCFG_CFGR2_CAPA_4                 ((uint32_t)0x00000020)
-#define SYSCFG_CFGR2_I2C_PB6_FMP            ((uint32_t)0x00000100) /*!< I2C PB6 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB7_FMP            ((uint32_t)0x00000200) /*!< I2C PB7 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB8_FMP            ((uint32_t)0x00000400) /*!< I2C PB8 Fast mode plus */
-#define SYSCFG_CFGR2_I2C_PB9_FMP            ((uint32_t)0x00000800) /*!< I2C PB9 Fast mode plus */
-#define SYSCFG_CFGR2_I2C1_FMP               ((uint32_t)0x00001000) /*!< I2C1 Fast mode plus */
-#define SYSCFG_CFGR2_I2C2_FMP               ((uint32_t)0x00002000) /*!< I2C2 Fast mode plus */
-#define SYSCFG_CFGR2_I2C3_FMP               ((uint32_t)0x00004000) /*!< I2C3 Fast mode plus */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000005) /*!< PH[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000050) /*!< PH[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400) /*!< PE[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000) /*!< PE[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004) /*!< PE[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040) /*!< PE[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400) /*!< PE[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000) /*!< PE[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004) /*!< PE[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PH         ((uint32_t)0x00000050) /*!< PH[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PH        ((uint32_t)0x00000500) /*!< PH[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000) /*!< PE[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004) /*!< PE[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040) /*!< PE[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400) /*!< PE[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000) /*!< PE[15] pin */
-
-
-/*****************  Bit definition for SYSCFG_CFGR3 register  ****************/
-#define SYSCFG_CFGR3_EN_VREFINT               ((uint32_t)0x00000001) /*!< Vref Enable bit*/
-#define SYSCFG_CFGR3_VREF_OUT                 ((uint32_t)0x00000030) /*!< Verf_ADC connection bit */
-#define SYSCFG_CFGR3_VREF_OUT_0               ((uint32_t)0x00000010) /*!< Bit 0 */
-#define SYSCFG_CFGR3_VREF_OUT_1               ((uint32_t)0x00000020) /*!< Bit 1 */
-#define SYSCFG_CFGR3_ENBUF_VREFINT_ADC        ((uint32_t)0x00000100) /*!< VREFINT reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUF_SENSOR_ADC         ((uint32_t)0x00000200) /*!< Sensor reference for ADC enable bit */
-#define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP     ((uint32_t)0x00001000) /*!< VREFINT reference for comparator 2 enable bit */
-#define SYSCFG_CFGR3_ENREF_HSI48              ((uint32_t)0x00002000) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
-#define SYSCFG_CFGR3_REF_HSI48_RDYF           ((uint32_t)0x04000000) /*!< VREFINT for 48 MHz RC oscillator ready flag */
-#define SYSCFG_CFGR3_SENSOR_ADC_RDYF          ((uint32_t)0x08000000) /*!< Sensor for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_ADC_RDYF         ((uint32_t)0x10000000) /*!< VREFINT for ADC ready flag */
-#define SYSCFG_CFGR3_VREFINT_COMP_RDYF        ((uint32_t)0x20000000) /*!< VREFINT for comparator ready flag */
-#define SYSCFG_CFGR3_VREFINT_RDYF             ((uint32_t)0x40000000) /*!< VREFINT ready flag */
-#define SYSCFG_CFGR3_REF_LOCK                 ((uint32_t)0x80000000) /*!< CFGR3 lock bit */
-
-/* Bit names aliases maintained for legacy */
-
-#define SYSCFG_CFGR3_EN_BGAP                  SYSCFG_CFGR3_EN_VREFINT
-#define SYSCFG_CFGR3_ENBUF_BGAP_ADC           SYSCFG_CFGR3_ENBUF_VREFINT_ADC
-#define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP        SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
-#define SYSCFG_CFGR3_ENREF_RC48MHz            SYSCFG_CFGR3_ENREF_HSI48
-#define SYSCFG_CFGR3_REF_RC48MHz_RDYF         SYSCFG_CFGR3_REF_HSI48_RDYF
-#define SYSCFG_VREFINT_ADC_RDYF               SYSCFG_CFGR3_VREFINT_ADC_RDYF
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define TIM_CR1_CEN                         ((uint32_t)0x00000001)            /*!<Counter enable */
-#define TIM_CR1_UDIS                        ((uint32_t)0x00000002)            /*!<Update disable */
-#define TIM_CR1_URS                         ((uint32_t)0x00000004)            /*!<Update request source */
-#define TIM_CR1_OPM                         ((uint32_t)0x00000008)            /*!<One pulse mode */
-#define TIM_CR1_DIR                         ((uint32_t)0x00000010)            /*!<Direction */
-
-#define TIM_CR1_CMS                         ((uint32_t)0x00000060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define TIM_CR1_CMS_0                       ((uint32_t)0x00000020)            /*!<Bit 0 */
-#define TIM_CR1_CMS_1                       ((uint32_t)0x00000040)            /*!<Bit 1 */
-
-#define TIM_CR1_ARPE                        ((uint32_t)0x00000080)            /*!<Auto-reload preload enable */
-
-#define TIM_CR1_CKD                         ((uint32_t)0x00000300)            /*!<CKD[1:0] bits (clock division) */
-#define TIM_CR1_CKD_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_CR1_CKD_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define TIM_CR2_CCPC                        ((uint32_t)0x00000001)            /*!<Capture/Compare Preloaded Control */
-#define TIM_CR2_CCUS                        ((uint32_t)0x00000004)            /*!<Capture/Compare Control Update Selection */
-#define TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */
-
-#define TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
-#define TIM_CR2_OIS1                        ((uint32_t)0x00000100)            /*!<Output Idle state 1 (OC1 output) */
-#define TIM_CR2_OIS1N                       ((uint32_t)0x00000200)            /*!<Output Idle state 1 (OC1N output) */
-#define TIM_CR2_OIS2                        ((uint32_t)0x00000400)            /*!<Output Idle state 2 (OC2 output) */
-#define TIM_CR2_OIS2N                       ((uint32_t)0x00000800)            /*!<Output Idle state 2 (OC2N output) */
-#define TIM_CR2_OIS3                        ((uint32_t)0x00001000)            /*!<Output Idle state 3 (OC3 output) */
-#define TIM_CR2_OIS3N                       ((uint32_t)0x00002000)            /*!<Output Idle state 3 (OC3N output) */
-#define TIM_CR2_OIS4                        ((uint32_t)0x00004000)            /*!<Output Idle state 4 (OC4 output) */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define TIM_SMCR_SMS                        ((uint32_t)0x00000007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-
-#define TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
-
-#define TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
-#define TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */
-
-#define TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */
-
-#define TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
-#define TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define TIM_DIER_UIE                        ((uint32_t)0x00000001)            /*!<Update interrupt enable */
-#define TIM_DIER_CC1IE                      ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt enable */
-#define TIM_DIER_CC2IE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt enable */
-#define TIM_DIER_CC3IE                      ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt enable */
-#define TIM_DIER_CC4IE                      ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt enable */
-#define TIM_DIER_TIE                        ((uint32_t)0x00000040)            /*!<Trigger interrupt enable */
-#define TIM_DIER_UDE                        ((uint32_t)0x00000100)            /*!<Update DMA request enable */
-#define TIM_DIER_CC1DE                      ((uint32_t)0x00000200)            /*!<Capture/Compare 1 DMA request enable */
-#define TIM_DIER_CC2DE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 2 DMA request enable */
-#define TIM_DIER_CC3DE                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 DMA request enable */
-#define TIM_DIER_CC4DE                      ((uint32_t)0x00001000)            /*!<Capture/Compare 4 DMA request enable */
-#define TIM_DIER_TDE                        ((uint32_t)0x00004000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
-#define TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
-#define TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
-#define TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
-#define TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
-#define TIM_SR_COMIF                        ((uint32_t)0x00000020)            /*!<COM interrupt Flag */
-#define TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
-#define TIM_SR_BIF                          ((uint32_t)0x00000080)            /*!<Break interrupt Flag */
-#define TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define TIM_EGR_UG                          ((uint32_t)0x00000001)               /*!<Update Generation */
-#define TIM_EGR_CC1G                        ((uint32_t)0x00000002)               /*!<Capture/Compare 1 Generation */
-#define TIM_EGR_CC2G                        ((uint32_t)0x00000004)               /*!<Capture/Compare 2 Generation */
-#define TIM_EGR_CC3G                        ((uint32_t)0x00000008)               /*!<Capture/Compare 3 Generation */
-#define TIM_EGR_CC4G                        ((uint32_t)0x00000010)               /*!<Capture/Compare 4 Generation */
-#define TIM_EGR_COMG                        ((uint32_t)0x00000020)               /*!<Capture/Compare Control Update Generation */
-#define TIM_EGR_TG                          ((uint32_t)0x00000040)               /*!<Trigger Generation */
-#define TIM_EGR_BG                          ((uint32_t)0x00000080)               /*!<Break Generation */
-
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
-#define TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */
-
-#define TIM_CCMR1_OC1M                      ((uint32_t)0x00000070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */
-
-#define TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
-#define TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */
-
-#define TIM_CCMR1_OC2M                      ((uint32_t)0x00007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
-#define TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */
-
-#define TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */
-
-#define TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
-#define TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
-
-#define TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define TIM_CCMR2_IC3PSC                    ((uint32_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define TIM_CCMR2_IC3F                      ((uint32_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define TIM_CCMR2_IC3F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define TIM_CCMR2_IC3F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define TIM_CCMR2_IC3F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define TIM_CCMR2_IC3F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define TIM_CCMR2_IC4PSC                    ((uint32_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define TIM_CCMR2_IC4F                      ((uint32_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define TIM_CCMR2_IC4F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TIM_CCMR2_IC4F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TIM_CCMR2_IC4F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define TIM_CCMR2_IC4F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
-#define TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
-#define TIM_CCER_CC1NE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 1 Complementary output enable */
-#define TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
-#define TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
-#define TIM_CCER_CC2NE                      ((uint32_t)0x00000040)            /*!<Capture/Compare 2 Complementary output enable */
-#define TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
-#define TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
-#define TIM_CCER_CC3NE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 3 Complementary output enable */
-#define TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
-#define TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
-#define TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define TIM_CNT_CNT                         ((uint32_t)0x0000FFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define TIM_PSC_PSC                         ((uint32_t)0x0000FFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define TIM_ARR_ARR                         ((uint32_t)0x0000FFFF)            /*!<actual auto-reload Value */
-
-/*******************  Bit definition for TIM_RCR register  ********************/
-#define TIM_RCR_REP                         ((uint32_t)0x000000FF)            /*!<Repetition Counter Value */
-
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define TIM_CCR1_CCR1                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define TIM_CCR2_CCR2                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define TIM_CCR3_CCR3                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define TIM_CCR4_CCR4                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_BDTR register  *******************/
-#define TIM_BDTR_DTG                        ((uint32_t)0x000000FF)            /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
-#define TIM_BDTR_DTG_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_BDTR_DTG_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM_BDTR_DTG_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define TIM_BDTR_DTG_3                      ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define TIM_BDTR_DTG_4                      ((uint32_t)0x00000010)            /*!<Bit 4 */
-#define TIM_BDTR_DTG_5                      ((uint32_t)0x00000020)            /*!<Bit 5 */
-#define TIM_BDTR_DTG_6                      ((uint32_t)0x00000040)            /*!<Bit 6 */
-#define TIM_BDTR_DTG_7                      ((uint32_t)0x00000080)            /*!<Bit 7 */
-
-#define TIM_BDTR_LOCK                       ((uint32_t)0x00000300)            /*!<LOCK[1:0] bits (Lock Configuration) */
-#define TIM_BDTR_LOCK_0                     ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_BDTR_LOCK_1                     ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define TIM_BDTR_OSSI                       ((uint32_t)0x00000400)            /*!<Off-State Selection for Idle mode */
-#define TIM_BDTR_OSSR                       ((uint32_t)0x00000800)            /*!<Off-State Selection for Run mode */
-#define TIM_BDTR_BKE                        ((uint32_t)0x00001000)            /*!<Break enable */
-#define TIM_BDTR_BKP                        ((uint32_t)0x00002000)            /*!<Break Polarity */
-#define TIM_BDTR_AOE                        ((uint32_t)0x00004000)            /*!<Automatic Output enable */
-#define TIM_BDTR_MOE                        ((uint32_t)0x00008000)            /*!<Main Output enable */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define TIM_DCR_DBA                         ((uint32_t)0x0000001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define TIM_DCR_DBA_0                       ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM_DCR_DBA_1                       ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM_DCR_DBA_2                       ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define TIM_DCR_DBA_3                       ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define TIM_DCR_DBA_4                       ((uint32_t)0x00000010)            /*!<Bit 4 */
-
-#define TIM_DCR_DBL                         ((uint32_t)0x00001F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define TIM_DCR_DBL_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define TIM_DCR_DBL_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define TIM_DCR_DBL_2                       ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define TIM_DCR_DBL_3                       ((uint32_t)0x00000800)            /*!<Bit 3 */
-#define TIM_DCR_DBL_4                       ((uint32_t)0x00001000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define TIM_DMAR_DMAB                       ((uint32_t)0x0000FFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define TIM2_OR_ETR_RMP                     ((uint32_t)0x00000007)            /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
-#define TIM2_OR_ETR_RMP_0                   ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM2_OR_ETR_RMP_1                   ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM2_OR_ETR_RMP_2                   ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define TIM2_OR_TI4_RMP                     ((uint32_t)0x0000018)             /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
-#define TIM2_OR_TI4_RMP_0                   ((uint32_t)0x00000008)            /*!<Bit 0 */
-#define TIM2_OR_TI4_RMP_1                   ((uint32_t)0x00000010)            /*!<Bit 1 */
-
-#define TIM21_OR_ETR_RMP                    ((uint32_t)0x00000003)            /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
-#define TIM21_OR_ETR_RMP_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM21_OR_ETR_RMP_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP                    ((uint32_t)0x0000001C)            /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
-#define TIM21_OR_TI1_RMP_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define TIM21_OR_TI1_RMP_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-#define TIM21_OR_TI1_RMP_2                  ((uint32_t)0x00000010)            /*!<Bit 2 */
-#define TIM21_OR_TI2_RMP                    ((uint32_t)0x00000020)            /*!<TI2_RMP bit (TIM21 Input 2 remap) */
-
-#define TIM22_OR_ETR_RMP                    ((uint32_t)0x00000003)            /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
-#define TIM22_OR_ETR_RMP_0                  ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM22_OR_ETR_RMP_1                  ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM22_OR_TI1_RMP                    ((uint32_t)0x0000000C)            /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
-#define TIM22_OR_TI1_RMP_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define TIM22_OR_TI1_RMP_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define TIM3_OR_ETR_RMP                     ((uint32_t)0x00000003)            /*!<ETR_RMP[1:0] bits (TIM3 ETR remap) */
-#define TIM3_OR_ETR_RMP_0                   ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define TIM3_OR_ETR_RMP_1                   ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define TIM3_OR_TI1_RMP                     ((uint32_t)0x00000004)            /*!<TI1_RMP[2] bit                      */
-#define TIM3_OR_TI2_RMP                     ((uint32_t)0x00000008)            /*!<TI2_RMP[3] bit                      */
-#define TIM3_OR_TI4_RMP                     ((uint32_t)0x00000010)            /*!<TI4_RMP[4] bit                      */
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Touch Sensing Controller (TSC)                    */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for TSC_CR register  *********************/
-#define TSC_CR_TSCE                         ((uint32_t)0x00000001)            /*!<Touch sensing controller enable */
-#define TSC_CR_START                        ((uint32_t)0x00000002)            /*!<Start acquisition */
-#define TSC_CR_AM                           ((uint32_t)0x00000004)            /*!<Acquisition mode */
-#define TSC_CR_SYNCPOL                      ((uint32_t)0x00000008)            /*!<Synchronization pin polarity */
-#define TSC_CR_IODEF                        ((uint32_t)0x00000010)            /*!<IO default mode */
-
-#define TSC_CR_MCV                          ((uint32_t)0x000000E0)            /*!<MCV[2:0] bits (Max Count Value) */
-#define TSC_CR_MCV_0                        ((uint32_t)0x00000020)            /*!<Bit 0 */
-#define TSC_CR_MCV_1                        ((uint32_t)0x00000040)            /*!<Bit 1 */
-#define TSC_CR_MCV_2                        ((uint32_t)0x00000080)            /*!<Bit 2 */
-
-#define TSC_CR_PGPSC                        ((uint32_t)0x00007000)            /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
-#define TSC_CR_PGPSC_0                      ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define TSC_CR_PGPSC_1                      ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define TSC_CR_PGPSC_2                      ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define TSC_CR_SSPSC                        ((uint32_t)0x00008000)            /*!<Spread Spectrum Prescaler */
-#define TSC_CR_SSE                          ((uint32_t)0x00010000)            /*!<Spread Spectrum Enable */
-
-#define TSC_CR_SSD                          ((uint32_t)0x00FE0000)            /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
-#define TSC_CR_SSD_0                        ((uint32_t)0x00020000)            /*!<Bit 0 */
-#define TSC_CR_SSD_1                        ((uint32_t)0x00040000)            /*!<Bit 1 */
-#define TSC_CR_SSD_2                        ((uint32_t)0x00080000)            /*!<Bit 2 */
-#define TSC_CR_SSD_3                        ((uint32_t)0x00100000)            /*!<Bit 3 */
-#define TSC_CR_SSD_4                        ((uint32_t)0x00200000)            /*!<Bit 4 */
-#define TSC_CR_SSD_5                        ((uint32_t)0x00400000)            /*!<Bit 5 */
-#define TSC_CR_SSD_6                        ((uint32_t)0x00800000)            /*!<Bit 6 */
-
-#define TSC_CR_CTPL                         ((uint32_t)0x0F000000)            /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
-#define TSC_CR_CTPL_0                       ((uint32_t)0x01000000)            /*!<Bit 0 */
-#define TSC_CR_CTPL_1                       ((uint32_t)0x02000000)            /*!<Bit 1 */
-#define TSC_CR_CTPL_2                       ((uint32_t)0x04000000)            /*!<Bit 2 */
-#define TSC_CR_CTPL_3                       ((uint32_t)0x08000000)            /*!<Bit 3 */
-
-#define TSC_CR_CTPH                         ((uint32_t)0xF0000000)            /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
-#define TSC_CR_CTPH_0                       ((uint32_t)0x10000000)            /*!<Bit 0 */
-#define TSC_CR_CTPH_1                       ((uint32_t)0x20000000)            /*!<Bit 1 */
-#define TSC_CR_CTPH_2                       ((uint32_t)0x40000000)            /*!<Bit 2 */
-#define TSC_CR_CTPH_3                       ((uint32_t)0x80000000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TSC_IER register  ********************/
-#define TSC_IER_EOAIE                       ((uint32_t)0x00000001)            /*!<End of acquisition interrupt enable */
-#define TSC_IER_MCEIE                       ((uint32_t)0x00000002)            /*!<Max count error interrupt enable */
-
-/*******************  Bit definition for TSC_ICR register  ********************/
-#define TSC_ICR_EOAIC                       ((uint32_t)0x00000001)            /*!<End of acquisition interrupt clear */
-#define TSC_ICR_MCEIC                       ((uint32_t)0x00000002)            /*!<Max count error interrupt clear */
-
-/*******************  Bit definition for TSC_ISR register  ********************/
-#define TSC_ISR_EOAF                        ((uint32_t)0x00000001)            /*!<End of acquisition flag */
-#define TSC_ISR_MCEF                        ((uint32_t)0x00000002)            /*!<Max count error flag */
-
-/*******************  Bit definition for TSC_IOHCR register  ******************/
-#define TSC_IOHCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
-#define TSC_IOHCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
-
-/*******************  Bit definition for TSC_IOASCR register  *****************/
-#define TSC_IOASCR_G1_IO1                   ((uint32_t)0x00000001)            /*!<GROUP1_IO1 analog switch enable */
-#define TSC_IOASCR_G1_IO2                   ((uint32_t)0x00000002)            /*!<GROUP1_IO2 analog switch enable */
-#define TSC_IOASCR_G1_IO3                   ((uint32_t)0x00000004)            /*!<GROUP1_IO3 analog switch enable */
-#define TSC_IOASCR_G1_IO4                   ((uint32_t)0x00000008)            /*!<GROUP1_IO4 analog switch enable */
-#define TSC_IOASCR_G2_IO1                   ((uint32_t)0x00000010)            /*!<GROUP2_IO1 analog switch enable */
-#define TSC_IOASCR_G2_IO2                   ((uint32_t)0x00000020)            /*!<GROUP2_IO2 analog switch enable */
-#define TSC_IOASCR_G2_IO3                   ((uint32_t)0x00000040)            /*!<GROUP2_IO3 analog switch enable */
-#define TSC_IOASCR_G2_IO4                   ((uint32_t)0x00000080)            /*!<GROUP2_IO4 analog switch enable */
-#define TSC_IOASCR_G3_IO1                   ((uint32_t)0x00000100)            /*!<GROUP3_IO1 analog switch enable */
-#define TSC_IOASCR_G3_IO2                   ((uint32_t)0x00000200)            /*!<GROUP3_IO2 analog switch enable */
-#define TSC_IOASCR_G3_IO3                   ((uint32_t)0x00000400)            /*!<GROUP3_IO3 analog switch enable */
-#define TSC_IOASCR_G3_IO4                   ((uint32_t)0x00000800)            /*!<GROUP3_IO4 analog switch enable */
-#define TSC_IOASCR_G4_IO1                   ((uint32_t)0x00001000)            /*!<GROUP4_IO1 analog switch enable */
-#define TSC_IOASCR_G4_IO2                   ((uint32_t)0x00002000)            /*!<GROUP4_IO2 analog switch enable */
-#define TSC_IOASCR_G4_IO3                   ((uint32_t)0x00004000)            /*!<GROUP4_IO3 analog switch enable */
-#define TSC_IOASCR_G4_IO4                   ((uint32_t)0x00008000)            /*!<GROUP4_IO4 analog switch enable */
-#define TSC_IOASCR_G5_IO1                   ((uint32_t)0x00010000)            /*!<GROUP5_IO1 analog switch enable */
-#define TSC_IOASCR_G5_IO2                   ((uint32_t)0x00020000)            /*!<GROUP5_IO2 analog switch enable */
-#define TSC_IOASCR_G5_IO3                   ((uint32_t)0x00040000)            /*!<GROUP5_IO3 analog switch enable */
-#define TSC_IOASCR_G5_IO4                   ((uint32_t)0x00080000)            /*!<GROUP5_IO4 analog switch enable */
-#define TSC_IOASCR_G6_IO1                   ((uint32_t)0x00100000)            /*!<GROUP6_IO1 analog switch enable */
-#define TSC_IOASCR_G6_IO2                   ((uint32_t)0x00200000)            /*!<GROUP6_IO2 analog switch enable */
-#define TSC_IOASCR_G6_IO3                   ((uint32_t)0x00400000)            /*!<GROUP6_IO3 analog switch enable */
-#define TSC_IOASCR_G6_IO4                   ((uint32_t)0x00800000)            /*!<GROUP6_IO4 analog switch enable */
-#define TSC_IOASCR_G7_IO1                   ((uint32_t)0x01000000)            /*!<GROUP7_IO1 analog switch enable */
-#define TSC_IOASCR_G7_IO2                   ((uint32_t)0x02000000)            /*!<GROUP7_IO2 analog switch enable */
-#define TSC_IOASCR_G7_IO3                   ((uint32_t)0x04000000)            /*!<GROUP7_IO3 analog switch enable */
-#define TSC_IOASCR_G7_IO4                   ((uint32_t)0x08000000)            /*!<GROUP7_IO4 analog switch enable */
-#define TSC_IOASCR_G8_IO1                   ((uint32_t)0x10000000)            /*!<GROUP8_IO1 analog switch enable */
-#define TSC_IOASCR_G8_IO2                   ((uint32_t)0x20000000)            /*!<GROUP8_IO2 analog switch enable */
-#define TSC_IOASCR_G8_IO3                   ((uint32_t)0x40000000)            /*!<GROUP8_IO3 analog switch enable */
-#define TSC_IOASCR_G8_IO4                   ((uint32_t)0x80000000)            /*!<GROUP8_IO4 analog switch enable */
-
-/*******************  Bit definition for TSC_IOSCR register  ******************/
-#define TSC_IOSCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 sampling mode */
-#define TSC_IOSCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 sampling mode */
-#define TSC_IOSCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 sampling mode */
-#define TSC_IOSCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 sampling mode */
-#define TSC_IOSCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 sampling mode */
-#define TSC_IOSCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 sampling mode */
-#define TSC_IOSCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 sampling mode */
-#define TSC_IOSCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 sampling mode */
-#define TSC_IOSCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 sampling mode */
-#define TSC_IOSCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 sampling mode */
-#define TSC_IOSCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 sampling mode */
-#define TSC_IOSCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 sampling mode */
-#define TSC_IOSCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 sampling mode */
-#define TSC_IOSCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 sampling mode */
-#define TSC_IOSCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 sampling mode */
-#define TSC_IOSCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 sampling mode */
-#define TSC_IOSCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 sampling mode */
-#define TSC_IOSCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 sampling mode */
-#define TSC_IOSCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 sampling mode */
-#define TSC_IOSCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 sampling mode */
-#define TSC_IOSCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 sampling mode */
-#define TSC_IOSCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 sampling mode */
-#define TSC_IOSCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 sampling mode */
-#define TSC_IOSCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 sampling mode */
-#define TSC_IOSCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 sampling mode */
-#define TSC_IOSCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 sampling mode */
-#define TSC_IOSCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 sampling mode */
-#define TSC_IOSCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 sampling mode */
-#define TSC_IOSCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 sampling mode */
-#define TSC_IOSCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 sampling mode */
-#define TSC_IOSCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 sampling mode */
-#define TSC_IOSCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 sampling mode */
-
-/*******************  Bit definition for TSC_IOCCR register  ******************/
-#define TSC_IOCCR_G1_IO1                    ((uint32_t)0x00000001)            /*!<GROUP1_IO1 channel mode */
-#define TSC_IOCCR_G1_IO2                    ((uint32_t)0x00000002)            /*!<GROUP1_IO2 channel mode */
-#define TSC_IOCCR_G1_IO3                    ((uint32_t)0x00000004)            /*!<GROUP1_IO3 channel mode */
-#define TSC_IOCCR_G1_IO4                    ((uint32_t)0x00000008)            /*!<GROUP1_IO4 channel mode */
-#define TSC_IOCCR_G2_IO1                    ((uint32_t)0x00000010)            /*!<GROUP2_IO1 channel mode */
-#define TSC_IOCCR_G2_IO2                    ((uint32_t)0x00000020)            /*!<GROUP2_IO2 channel mode */
-#define TSC_IOCCR_G2_IO3                    ((uint32_t)0x00000040)            /*!<GROUP2_IO3 channel mode */
-#define TSC_IOCCR_G2_IO4                    ((uint32_t)0x00000080)            /*!<GROUP2_IO4 channel mode */
-#define TSC_IOCCR_G3_IO1                    ((uint32_t)0x00000100)            /*!<GROUP3_IO1 channel mode */
-#define TSC_IOCCR_G3_IO2                    ((uint32_t)0x00000200)            /*!<GROUP3_IO2 channel mode */
-#define TSC_IOCCR_G3_IO3                    ((uint32_t)0x00000400)            /*!<GROUP3_IO3 channel mode */
-#define TSC_IOCCR_G3_IO4                    ((uint32_t)0x00000800)            /*!<GROUP3_IO4 channel mode */
-#define TSC_IOCCR_G4_IO1                    ((uint32_t)0x00001000)            /*!<GROUP4_IO1 channel mode */
-#define TSC_IOCCR_G4_IO2                    ((uint32_t)0x00002000)            /*!<GROUP4_IO2 channel mode */
-#define TSC_IOCCR_G4_IO3                    ((uint32_t)0x00004000)            /*!<GROUP4_IO3 channel mode */
-#define TSC_IOCCR_G4_IO4                    ((uint32_t)0x00008000)            /*!<GROUP4_IO4 channel mode */
-#define TSC_IOCCR_G5_IO1                    ((uint32_t)0x00010000)            /*!<GROUP5_IO1 channel mode */
-#define TSC_IOCCR_G5_IO2                    ((uint32_t)0x00020000)            /*!<GROUP5_IO2 channel mode */
-#define TSC_IOCCR_G5_IO3                    ((uint32_t)0x00040000)            /*!<GROUP5_IO3 channel mode */
-#define TSC_IOCCR_G5_IO4                    ((uint32_t)0x00080000)            /*!<GROUP5_IO4 channel mode */
-#define TSC_IOCCR_G6_IO1                    ((uint32_t)0x00100000)            /*!<GROUP6_IO1 channel mode */
-#define TSC_IOCCR_G6_IO2                    ((uint32_t)0x00200000)            /*!<GROUP6_IO2 channel mode */
-#define TSC_IOCCR_G6_IO3                    ((uint32_t)0x00400000)            /*!<GROUP6_IO3 channel mode */
-#define TSC_IOCCR_G6_IO4                    ((uint32_t)0x00800000)            /*!<GROUP6_IO4 channel mode */
-#define TSC_IOCCR_G7_IO1                    ((uint32_t)0x01000000)            /*!<GROUP7_IO1 channel mode */
-#define TSC_IOCCR_G7_IO2                    ((uint32_t)0x02000000)            /*!<GROUP7_IO2 channel mode */
-#define TSC_IOCCR_G7_IO3                    ((uint32_t)0x04000000)            /*!<GROUP7_IO3 channel mode */
-#define TSC_IOCCR_G7_IO4                    ((uint32_t)0x08000000)            /*!<GROUP7_IO4 channel mode */
-#define TSC_IOCCR_G8_IO1                    ((uint32_t)0x10000000)            /*!<GROUP8_IO1 channel mode */
-#define TSC_IOCCR_G8_IO2                    ((uint32_t)0x20000000)            /*!<GROUP8_IO2 channel mode */
-#define TSC_IOCCR_G8_IO3                    ((uint32_t)0x40000000)            /*!<GROUP8_IO3 channel mode */
-#define TSC_IOCCR_G8_IO4                    ((uint32_t)0x80000000)            /*!<GROUP8_IO4 channel mode */
-
-/*******************  Bit definition for TSC_IOGCSR register  *****************/
-#define TSC_IOGCSR_G1E                      ((uint32_t)0x00000001)            /*!<Analog IO GROUP1 enable */
-#define TSC_IOGCSR_G2E                      ((uint32_t)0x00000002)            /*!<Analog IO GROUP2 enable */
-#define TSC_IOGCSR_G3E                      ((uint32_t)0x00000004)            /*!<Analog IO GROUP3 enable */
-#define TSC_IOGCSR_G4E                      ((uint32_t)0x00000008)            /*!<Analog IO GROUP4 enable */
-#define TSC_IOGCSR_G5E                      ((uint32_t)0x00000010)            /*!<Analog IO GROUP5 enable */
-#define TSC_IOGCSR_G6E                      ((uint32_t)0x00000020)            /*!<Analog IO GROUP6 enable */
-#define TSC_IOGCSR_G7E                      ((uint32_t)0x00000040)            /*!<Analog IO GROUP7 enable */
-#define TSC_IOGCSR_G8E                      ((uint32_t)0x00000080)            /*!<Analog IO GROUP8 enable */
-#define TSC_IOGCSR_G1S                      ((uint32_t)0x00010000)            /*!<Analog IO GROUP1 status */
-#define TSC_IOGCSR_G2S                      ((uint32_t)0x00020000)            /*!<Analog IO GROUP2 status */
-#define TSC_IOGCSR_G3S                      ((uint32_t)0x00040000)            /*!<Analog IO GROUP3 status */
-#define TSC_IOGCSR_G4S                      ((uint32_t)0x00080000)            /*!<Analog IO GROUP4 status */
-#define TSC_IOGCSR_G5S                      ((uint32_t)0x00100000)            /*!<Analog IO GROUP5 status */
-#define TSC_IOGCSR_G6S                      ((uint32_t)0x00200000)            /*!<Analog IO GROUP6 status */
-#define TSC_IOGCSR_G7S                      ((uint32_t)0x00400000)            /*!<Analog IO GROUP7 status */
-#define TSC_IOGCSR_G8S                      ((uint32_t)0x00800000)            /*!<Analog IO GROUP8 status */
-
-/*******************  Bit definition for TSC_IOGXCR register  *****************/
-#define TSC_IOGXCR_CNT                      ((uint32_t)0x00003FFF)            /*!<CNT[13:0] bits (Counter value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bit definition for USART_CR1 register  *******************/
-#define USART_CR1_UE                        ((uint32_t)0x00000001)            /*!< USART Enable */
-#define USART_CR1_UESM                      ((uint32_t)0x00000002)            /*!< USART Enable in STOP Mode */
-#define USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< TXE Interrupt Enable */
-#define USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Receiver Wakeup method */
-#define USART_CR1_M                         ((uint32_t)0x10001000)            /*!< Word length */
-#define USART_CR1_M_0                       ((uint32_t)0x00001000)            /*!< Word length - Bit 0 */
-#define USART_CR1_MME                       ((uint32_t)0x00002000)            /*!< Mute Mode Enable */
-#define USART_CR1_CMIE                      ((uint32_t)0x00004000)            /*!< Character match interrupt enable */
-#define USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit or 16-bit mode */
-#define USART_CR1_DEDT                      ((uint32_t)0x001F0000)            /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
-#define USART_CR1_DEDT_0                    ((uint32_t)0x00010000)            /*!< Bit 0 */
-#define USART_CR1_DEDT_1                    ((uint32_t)0x00020000)            /*!< Bit 1 */
-#define USART_CR1_DEDT_2                    ((uint32_t)0x00040000)            /*!< Bit 2 */
-#define USART_CR1_DEDT_3                    ((uint32_t)0x00080000)            /*!< Bit 3 */
-#define USART_CR1_DEDT_4                    ((uint32_t)0x00100000)            /*!< Bit 4 */
-#define USART_CR1_DEAT                      ((uint32_t)0x03E00000)            /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
-#define USART_CR1_DEAT_0                    ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define USART_CR1_DEAT_1                    ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define USART_CR1_DEAT_2                    ((uint32_t)0x00800000)            /*!< Bit 2 */
-#define USART_CR1_DEAT_3                    ((uint32_t)0x01000000)            /*!< Bit 3 */
-#define USART_CR1_DEAT_4                    ((uint32_t)0x02000000)            /*!< Bit 4 */
-#define USART_CR1_RTOIE                     ((uint32_t)0x04000000)            /*!< Receive Time Out interrupt enable */
-#define USART_CR1_EOBIE                     ((uint32_t)0x08000000)            /*!< End of Block interrupt enable */
-#define USART_CR1_M_1                       ((uint32_t)0x10000000)            /*!< Word length - Bit 1 */
-/******************  Bit definition for USART_CR2 register  *******************/
-#define USART_CR2_ADDM7                     ((uint32_t)0x00000010)            /*!< 7-bit or 4-bit Address Detection */
-#define USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-#define USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-#define USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-#define USART_CR2_SWAP                      ((uint32_t)0x00008000)            /*!< SWAP TX/RX pins */
-#define USART_CR2_RXINV                     ((uint32_t)0x00010000)            /*!< RX pin active level inversion */
-#define USART_CR2_TXINV                     ((uint32_t)0x00020000)            /*!< TX pin active level inversion */
-#define USART_CR2_DATAINV                   ((uint32_t)0x00040000)            /*!< Binary data inversion */
-#define USART_CR2_MSBFIRST                  ((uint32_t)0x00080000)            /*!< Most Significant Bit First */
-#define USART_CR2_ABREN                     ((uint32_t)0x00100000)            /*!< Auto Baud-Rate Enable*/
-#define USART_CR2_ABRMODE                   ((uint32_t)0x00600000)            /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
-#define USART_CR2_ABRMODE_0                 ((uint32_t)0x00200000)            /*!< Bit 0 */
-#define USART_CR2_ABRMODE_1                 ((uint32_t)0x00400000)            /*!< Bit 1 */
-#define USART_CR2_RTOEN                     ((uint32_t)0x00800000)            /*!< Receiver Time-Out enable */
-#define USART_CR2_ADD                       ((uint32_t)0xFF000000)            /*!< Address of the USART node */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< SmartCard NACK enable */
-#define USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< SmartCard mode enable */
-#define USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-#define USART_CR3_OVRDIS                    ((uint32_t)0x00001000)            /*!< Overrun Disable */
-#define USART_CR3_DDRE                      ((uint32_t)0x00002000)            /*!< DMA Disable on Reception Error */
-#define USART_CR3_DEM                       ((uint32_t)0x00004000)            /*!< Driver Enable Mode */
-#define USART_CR3_DEP                       ((uint32_t)0x00008000)            /*!< Driver Enable Polarity Selection */
-#define USART_CR3_SCARCNT                   ((uint32_t)0x000E0000)            /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
-#define USART_CR3_SCARCNT_0                 ((uint32_t)0x00020000)            /*!< Bit 0 */
-#define USART_CR3_SCARCNT_1                 ((uint32_t)0x00040000)            /*!< Bit 1 */
-#define USART_CR3_SCARCNT_2                 ((uint32_t)0x00080000)            /*!< Bit 2 */
-#define USART_CR3_WUS                       ((uint32_t)0x00300000)            /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
-#define USART_CR3_WUS_0                     ((uint32_t)0x00100000)            /*!< Bit 0 */
-#define USART_CR3_WUS_1                     ((uint32_t)0x00200000)            /*!< Bit 1 */
-#define USART_CR3_WUFIE                     ((uint32_t)0x00400000)            /*!< Wake Up Interrupt Enable */
-#define USART_CR3_UCESM                     ((uint32_t)0x00800000)            /*!< Clock Enable in Stop mode */ 
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define USART_BRR_DIV_FRACTION              ((uint32_t)0x0000000F)            /*!< Fraction of USARTDIV */
-#define USART_BRR_DIV_MANTISSA              ((uint32_t)0x0000FFF0)            /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define USART_GTPR_PSC                      ((uint32_t)0x000000FF)            /*!< PSC[7:0] bits (Prescaler value) */
-#define USART_GTPR_GT                       ((uint32_t)0x0000FF00)            /*!< GT[7:0] bits (Guard time value) */
-
-
-/*******************  Bit definition for USART_RTOR register  *****************/
-#define USART_RTOR_RTO                      ((uint32_t)0x00FFFFFF)            /*!< Receiver Time Out Value */
-#define USART_RTOR_BLEN                     ((uint32_t)0xFF000000)            /*!< Block Length */
-
-/*******************  Bit definition for USART_RQR register  ******************/
-#define USART_RQR_ABRRQ                     ((uint32_t)0x00000001)            /*!< Auto-Baud Rate Request */
-#define USART_RQR_SBKRQ                     ((uint32_t)0x00000002)            /*!< Send Break Request */
-#define USART_RQR_MMRQ                      ((uint32_t)0x00000004)            /*!< Mute Mode Request */
-#define USART_RQR_RXFRQ                     ((uint32_t)0x00000008)            /*!< Receive Data flush Request */
-#define USART_RQR_TXFRQ                     ((uint32_t)0x00000010)            /*!< Transmit data flush Request */
-
-/*******************  Bit definition for USART_ISR register  ******************/
-#define USART_ISR_PE                        ((uint32_t)0x00000001)            /*!< Parity Error */
-#define USART_ISR_FE                        ((uint32_t)0x00000002)            /*!< Framing Error */
-#define USART_ISR_NE                        ((uint32_t)0x00000004)            /*!< Noise detected Flag */
-#define USART_ISR_ORE                       ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define USART_ISR_IDLE                      ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define USART_ISR_RXNE                      ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define USART_ISR_TC                        ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define USART_ISR_TXE                       ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define USART_ISR_LBD                       ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define USART_ISR_CTSIF                     ((uint32_t)0x00000200)            /*!< CTS interrupt flag */
-#define USART_ISR_CTS                       ((uint32_t)0x00000400)            /*!< CTS flag */
-#define USART_ISR_RTOF                      ((uint32_t)0x00000800)            /*!< Receiver Time Out */
-#define USART_ISR_EOBF                      ((uint32_t)0x00001000)            /*!< End Of Block Flag */
-#define USART_ISR_ABRE                      ((uint32_t)0x00004000)            /*!< Auto-Baud Rate Error */
-#define USART_ISR_ABRF                      ((uint32_t)0x00008000)            /*!< Auto-Baud Rate Flag */
-#define USART_ISR_BUSY                      ((uint32_t)0x00010000)            /*!< Busy Flag */
-#define USART_ISR_CMF                       ((uint32_t)0x00020000)            /*!< Character Match Flag */
-#define USART_ISR_SBKF                      ((uint32_t)0x00040000)            /*!< Send Break Flag */
-#define USART_ISR_RWU                       ((uint32_t)0x00080000)            /*!< Receive Wake Up from mute mode Flag */
-#define USART_ISR_WUF                       ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Flag */
-#define USART_ISR_TEACK                     ((uint32_t)0x00200000)            /*!< Transmit Enable Acknowledge Flag */
-#define USART_ISR_REACK                     ((uint32_t)0x00400000)            /*!< Receive Enable Acknowledge Flag */
-
-/*******************  Bit definition for USART_ICR register  ******************/
-#define USART_ICR_PECF                      ((uint32_t)0x00000001)            /*!< Parity Error Clear Flag */
-#define USART_ICR_FECF                      ((uint32_t)0x00000002)            /*!< Framing Error Clear Flag */
-#define USART_ICR_NCF                       ((uint32_t)0x00000004)            /*!< Noise detected Clear Flag */
-#define USART_ICR_ORECF                     ((uint32_t)0x00000008)            /*!< OverRun Error Clear Flag */
-#define USART_ICR_IDLECF                    ((uint32_t)0x00000010)            /*!< IDLE line detected Clear Flag */
-#define USART_ICR_TCCF                      ((uint32_t)0x00000040)            /*!< Transmission Complete Clear Flag */
-#define USART_ICR_LBDCF                     ((uint32_t)0x00000100)            /*!< LIN Break Detection Clear Flag */
-#define USART_ICR_CTSCF                     ((uint32_t)0x00000200)            /*!< CTS Interrupt Clear Flag */
-#define USART_ICR_RTOCF                     ((uint32_t)0x00000800)            /*!< Receiver Time Out Clear Flag */
-#define USART_ICR_EOBCF                     ((uint32_t)0x00001000)            /*!< End Of Block Clear Flag */
-#define USART_ICR_CMCF                      ((uint32_t)0x00020000)            /*!< Character Match Clear Flag */
-#define USART_ICR_WUCF                      ((uint32_t)0x00100000)            /*!< Wake Up from stop mode Clear Flag */
-
-/*******************  Bit definition for USART_RDR register  ******************/
-#define USART_RDR_RDR                       ((uint32_t)0x000001FF)            /*!< RDR[8:0] bits (Receive Data value) */
-
-/*******************  Bit definition for USART_TDR register  ******************/
-#define USART_TDR_TDR                       ((uint32_t)0x000001FF)            /*!< TDR[8:0] bits (Transmit Data value) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         USB Device General registers                       */
-/*                                                                            */
-/******************************************************************************/
-#define USB_BASE                             ((uint32_t)0x40005C00)      /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR                          ((uint32_t)0x40006000)      /*!< USB_IP Packet Memory Area base address */
-                                             
-#define USB_CNTR                             (USB_BASE + 0x40)           /*!< Control register */
-#define USB_ISTR                             (USB_BASE + 0x44)           /*!< Interrupt status register */
-#define USB_FNR                              (USB_BASE + 0x48)           /*!< Frame number register */
-#define USB_DADDR                            (USB_BASE + 0x4C)           /*!< Device address register */
-#define USB_BTABLE                           (USB_BASE + 0x50)           /*!< Buffer Table address register */
-#define USB_LPMCSR                           (USB_BASE + 0x54)           /*!< LPM Control and Status register */
-#define USB_BCDR                             (USB_BASE + 0x58)           /*!< Battery Charging detector register*/
-
-/****************************  ISTR interrupt events  *************************/
-#define USB_ISTR_CTR                         ((uint16_t)0x8000)          /*!< Correct TRansfer (clear-only bit) */
-#define USB_ISTR_PMAOVR                      ((uint16_t)0x4000)          /*!< DMA OVeR/underrun (clear-only bit) */
-#define USB_ISTR_ERR                         ((uint16_t)0x2000)          /*!< ERRor (clear-only bit) */
-#define USB_ISTR_WKUP                        ((uint16_t)0x1000)          /*!< WaKe UP (clear-only bit) */
-#define USB_ISTR_SUSP                        ((uint16_t)0x0800)          /*!< SUSPend (clear-only bit) */
-#define USB_ISTR_RESET                       ((uint16_t)0x0400)          /*!< RESET (clear-only bit) */
-#define USB_ISTR_SOF                         ((uint16_t)0x0200)          /*!< Start Of Frame (clear-only bit) */
-#define USB_ISTR_ESOF                        ((uint16_t)0x0100)          /*!< Expected Start Of Frame (clear-only bit) */
-#define USB_ISTR_L1REQ                       ((uint16_t)0x0080)          /*!< LPM L1 state request  */
-#define USB_ISTR_DIR                         ((uint16_t)0x0010)          /*!< DIRection of transaction (read-only bit)  */
-#define USB_ISTR_EP_ID                       ((uint16_t)0x000F)          /*!< EndPoint IDentifier (read-only bit)  */
-
-#define USB_CLR_CTR                          (~USB_ISTR_CTR)             /*!< clear Correct TRansfer bit */
-#define USB_CLR_PMAOVR                       (~USB_ISTR_PMAOVR)          /*!< clear DMA OVeR/underrun bit*/
-#define USB_CLR_ERR                          (~USB_ISTR_ERR)             /*!< clear ERRor bit */
-#define USB_CLR_WKUP                         (~USB_ISTR_WKUP)            /*!< clear WaKe UP bit */
-#define USB_CLR_SUSP                         (~USB_ISTR_SUSP)            /*!< clear SUSPend bit */
-#define USB_CLR_RESET                        (~USB_ISTR_RESET)           /*!< clear RESET bit */
-#define USB_CLR_SOF                          (~USB_ISTR_SOF)             /*!< clear Start Of Frame bit */
-#define USB_CLR_ESOF                         (~USB_ISTR_ESOF)            /*!< clear Expected Start Of Frame bit */
-#define USB_CLR_L1REQ                        (~USB_ISTR_L1REQ)           /*!< clear LPM L1  bit */
-/*************************  CNTR control register bits definitions  ***********/
-#define USB_CNTR_CTRM                        ((uint16_t)0x8000)          /*!< Correct TRansfer Mask */
-#define USB_CNTR_PMAOVRM                     ((uint16_t)0x4000)          /*!< DMA OVeR/underrun Mask */
-#define USB_CNTR_ERRM                        ((uint16_t)0x2000)          /*!< ERRor Mask */
-#define USB_CNTR_WKUPM                       ((uint16_t)0x1000)          /*!< WaKe UP Mask */
-#define USB_CNTR_SUSPM                       ((uint16_t)0x0800)          /*!< SUSPend Mask */
-#define USB_CNTR_RESETM                      ((uint16_t)0x0400)          /*!< RESET Mask   */
-#define USB_CNTR_SOFM                        ((uint16_t)0x0200)          /*!< Start Of Frame Mask */
-#define USB_CNTR_ESOFM                       ((uint16_t)0x0100)          /*!< Expected Start Of Frame Mask */
-#define USB_CNTR_L1REQM                      ((uint16_t)0x0080)          /*!< LPM L1 state request interrupt mask */
-#define USB_CNTR_L1RESUME                    ((uint16_t)0x0020)          /*!< LPM L1 Resume request */
-#define USB_CNTR_RESUME                      ((uint16_t)0x0010)          /*!< RESUME request */
-#define USB_CNTR_FSUSP                       ((uint16_t)0x0008)          /*!< Force SUSPend */
-#define USB_CNTR_LPMODE                      ((uint16_t)0x0004)          /*!< Low-power MODE */
-#define USB_CNTR_PDWN                        ((uint16_t)0x0002)          /*!< Power DoWN */
-#define USB_CNTR_FRES                        ((uint16_t)0x0001)          /*!< Force USB RESet */
-/*************************  BCDR control register bits definitions  ***********/
-#define USB_BCDR_DPPU                        ((uint16_t)0x8000)          /*!< DP Pull-up Enable */  
-#define USB_BCDR_PS2DET                      ((uint16_t)0x0080)          /*!< PS2 port or proprietary charger detected */  
-#define USB_BCDR_SDET                        ((uint16_t)0x0040)          /*!< Secondary detection (SD) status */  
-#define USB_BCDR_PDET                        ((uint16_t)0x0020)          /*!< Primary detection (PD) status */ 
-#define USB_BCDR_DCDET                       ((uint16_t)0x0010)          /*!< Data contact detection (DCD) status */ 
-#define USB_BCDR_SDEN                        ((uint16_t)0x0008)          /*!< Secondary detection (SD) mode enable */ 
-#define USB_BCDR_PDEN                        ((uint16_t)0x0004)          /*!< Primary detection (PD) mode enable */  
-#define USB_BCDR_DCDEN                       ((uint16_t)0x0002)          /*!< Data contact detection (DCD) mode enable */
-#define USB_BCDR_BCDEN                       ((uint16_t)0x0001)          /*!< Battery charging detector (BCD) enable */
-/***************************  LPM register bits definitions  ******************/
-#define USB_LPMCSR_BESL                      ((uint16_t)0x00F0)          /*!< BESL value received with last ACKed LPM Token  */ 
-#define USB_LPMCSR_REMWAKE                   ((uint16_t)0x0008)          /*!< bRemoteWake value received with last ACKed LPM Token */ 
-#define USB_LPMCSR_LPMACK                    ((uint16_t)0x0002)          /*!< LPM Token acknowledge enable*/
-#define USB_LPMCSR_LMPEN                     ((uint16_t)0x0001)          /*!< LPM support enable  */
-/********************  FNR Frame Number Register bit definitions   ************/
-#define USB_FNR_RXDP                         ((uint16_t)0x8000)          /*!< status of D+ data line */
-#define USB_FNR_RXDM                         ((uint16_t)0x4000)          /*!< status of D- data line */
-#define USB_FNR_LCK                          ((uint16_t)0x2000)          /*!< LoCKed */
-#define USB_FNR_LSOF                         ((uint16_t)0x1800)          /*!< Lost SOF */
-#define USB_FNR_FN                           ((uint16_t)0x07FF)          /*!< Frame Number */
-/********************  DADDR Device ADDRess bit definitions    ****************/
-#define USB_DADDR_EF                         ((uint8_t)0x80)             /*!< USB device address Enable Function */
-#define USB_DADDR_ADD                        ((uint8_t)0x7F)             /*!< USB device address */
-/******************************  Endpoint register    *************************/
-#define USB_EP0R                              USB_BASE                   /*!< endpoint 0 register address */
-#define USB_EP1R                             (USB_BASE + 0x04)           /*!< endpoint 1 register address */
-#define USB_EP2R                             (USB_BASE + 0x08)           /*!< endpoint 2 register address */
-#define USB_EP3R                             (USB_BASE + 0x0C)           /*!< endpoint 3 register address */
-#define USB_EP4R                             (USB_BASE + 0x10)           /*!< endpoint 4 register address */
-#define USB_EP5R                             (USB_BASE + 0x14)           /*!< endpoint 5 register address */
-#define USB_EP6R                             (USB_BASE + 0x18)           /*!< endpoint 6 register address */
-#define USB_EP7R                             (USB_BASE + 0x1C)           /*!< endpoint 7 register address */
-/* bit positions */ 
-#define USB_EP_CTR_RX                        ((uint16_t)0x8000)          /*!<  EndPoint Correct TRansfer RX */
-#define USB_EP_DTOG_RX                       ((uint16_t)0x4000)          /*!<  EndPoint Data TOGGLE RX */
-#define USB_EPRX_STAT                        ((uint16_t)0x3000)          /*!<  EndPoint RX STATus bit field */
-#define USB_EP_SETUP                         ((uint16_t)0x0800)          /*!<  EndPoint SETUP */
-#define USB_EP_T_FIELD                       ((uint16_t)0x0600)          /*!<  EndPoint TYPE */
-#define USB_EP_KIND                          ((uint16_t)0x0100)          /*!<  EndPoint KIND */
-#define USB_EP_CTR_TX                        ((uint16_t)0x0080)          /*!<  EndPoint Correct TRansfer TX */
-#define USB_EP_DTOG_TX                       ((uint16_t)0x0040)          /*!<  EndPoint Data TOGGLE TX */
-#define USB_EPTX_STAT                        ((uint16_t)0x0030)          /*!<  EndPoint TX STATus bit field */
-#define USB_EPADDR_FIELD                     ((uint16_t)0x000F)          /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                         /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define USB_EP_TYPE_MASK                     ((uint16_t)0x0600)          /*!< EndPoint TYPE Mask */
-#define USB_EP_BULK                          ((uint16_t)0x0000)          /*!< EndPoint BULK */
-#define USB_EP_CONTROL                       ((uint16_t)0x0200)          /*!< EndPoint CONTROL */
-#define USB_EP_ISOCHRONOUS                   ((uint16_t)0x0400)          /*!< EndPoint ISOCHRONOUS */
-#define USB_EP_INTERRUPT                     ((uint16_t)0x0600)          /*!< EndPoint INTERRUPT */
-#define USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)               /*!< EP_KIND EndPoint KIND */
-                                                                         /*!< STAT_TX[1:0] STATus for TX transfer */
-#define USB_EP_TX_DIS                        ((uint16_t)0x0000)          /*!< EndPoint TX DISabled */
-#define USB_EP_TX_STALL                      ((uint16_t)0x0010)          /*!< EndPoint TX STALLed */
-#define USB_EP_TX_NAK                        ((uint16_t)0x0020)          /*!< EndPoint TX NAKed */
-#define USB_EP_TX_VALID                      ((uint16_t)0x0030)          /*!< EndPoint TX VALID */
-#define USB_EPTX_DTOG1                       ((uint16_t)0x0010)          /*!< EndPoint TX Data TOGgle bit1 */
-#define USB_EPTX_DTOG2                       ((uint16_t)0x0020)          /*!< EndPoint TX Data TOGgle bit2 */
-#define USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                         /*!< STAT_RX[1:0] STATus for RX transfer */
-#define USB_EP_RX_DIS                        ((uint16_t)0x0000)          /*!< EndPoint RX DISabled */
-#define USB_EP_RX_STALL                      ((uint16_t)0x1000)          /*!< EndPoint RX STALLed */
-#define USB_EP_RX_NAK                        ((uint16_t)0x2000)          /*!< EndPoint RX NAKed */
-#define USB_EP_RX_VALID                      ((uint16_t)0x3000)          /*!< EndPoint RX VALID */
-#define USB_EPRX_DTOG1                       ((uint16_t)0x1000)          /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOG2                       ((uint16_t)0x2000)          /*!< EndPoint RX Data TOGgle bit1 */
-#define USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define WWDG_CR_T                           ((uint32_t)0x0000007F)      /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define WWDG_CR_T0                          ((uint32_t)0x00000001)      /*!< Bit 0 */
-#define WWDG_CR_T1                          ((uint32_t)0x00000002)      /*!< Bit 1 */
-#define WWDG_CR_T2                          ((uint32_t)0x00000004)      /*!< Bit 2 */
-#define WWDG_CR_T3                          ((uint32_t)0x00000008)      /*!< Bit 3 */
-#define WWDG_CR_T4                          ((uint32_t)0x00000010)      /*!< Bit 4 */
-#define WWDG_CR_T5                          ((uint32_t)0x00000020)      /*!< Bit 5 */
-#define WWDG_CR_T6                          ((uint32_t)0x00000040)      /*!< Bit 6 */
-
-#define WWDG_CR_WDGA                        ((uint32_t)0x00000080)      /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define WWDG_CFR_W                          ((uint32_t)0x0000007F)      /*!< W[6:0] bits (7-bit window value) */
-#define WWDG_CFR_W0                         ((uint32_t)0x00000001)      /*!< Bit 0 */
-#define WWDG_CFR_W1                         ((uint32_t)0x00000002)      /*!< Bit 1 */
-#define WWDG_CFR_W2                         ((uint32_t)0x00000004)      /*!< Bit 2 */
-#define WWDG_CFR_W3                         ((uint32_t)0x00000008)      /*!< Bit 3 */
-#define WWDG_CFR_W4                         ((uint32_t)0x00000010)      /*!< Bit 4 */
-#define WWDG_CFR_W5                         ((uint32_t)0x00000020)      /*!< Bit 5 */
-#define WWDG_CFR_W6                         ((uint32_t)0x00000040)      /*!< Bit 6 */
-                                                                         
-#define WWDG_CFR_WDGTB                      ((uint32_t)0x00000180)      /*!< WDGTB[1:0] bits (Timer Base) */
-#define WWDG_CFR_WDGTB0                     ((uint32_t)0x00000080)      /*!< Bit 0 */
-#define WWDG_CFR_WDGTB1                     ((uint32_t)0x00000100)      /*!< Bit 1 */
-
-#define WWDG_CFR_EWI                        ((uint32_t)0x00000200)      /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define WWDG_SR_EWIF                        ((uint32_t)0x00000001)      /*!< Early Wakeup Interrupt Flag */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-
-/******************************* ADC Instances ********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************* COMP Instances *******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                       ((INSTANCE) == COMP2))
-
-/******************************* CRC Instances ********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/******************************* DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/******************************* DMA Instances *********************************/
-#define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
-                                              ((INSTANCE) == DMA1_Stream1) || \
-                                              ((INSTANCE) == DMA1_Stream2) || \
-                                              ((INSTANCE) == DMA1_Stream3) || \
-                                              ((INSTANCE) == DMA1_Stream4) || \
-                                              ((INSTANCE) == DMA1_Stream5) || \
-                                              ((INSTANCE) == DMA1_Stream6) || \
-                                              ((INSTANCE) == DMA1_Stream7))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2) || \
-                                       ((INSTANCE) == I2C3))
-
-/******************************** I2S Instances *******************************/
-#define IS_I2S_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == SPI2)
-
-/******************************* RNG Instances ********************************/
-#define IS_RNG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RNG)
-
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SMBUS Instances *****************************/
-#define IS_SMBUS_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                     ((INSTANCE) == I2C3))
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2))
-
-/****************** LPTIM Instances : All supported instances *****************/
-#define IS_LPTIM_INSTANCE(INSTANCE)       ((INSTANCE) == LPTIM1)
-
-/****************** TIM Instances : All supported instances *******************/
-#define IS_TIM_INSTANCE(INSTANCE)       (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)   || \
-                                         ((INSTANCE) == TIM6)   || \
-                                         ((INSTANCE) == TIM7)   || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/************* TIM Instances : at least 1 capture/compare channel *************/
-#define IS_TIM_CC1_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21) || \
-                                         ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 2 capture/compare channels *************/
-#define IS_TIM_CC2_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2)  || \
-                                        ((INSTANCE) == TIM3)  || \
-                                        ((INSTANCE) == TIM21) || \
-                                        ((INSTANCE) == TIM22))
-
-/************ TIM Instances : at least 3 capture/compare channels *************/
-#define IS_TIM_CC3_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/************ TIM Instances : at least 4 capture/compare channels *************/
-#define IS_TIM_CC4_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/******************** TIM Instances : Advanced-control timers *****************/
-
-/******************* TIM Instances : Timer input XOR function *****************/
-#define IS_TIM_XOR_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                        ((INSTANCE) == TIM3))
-
-/****************** TIM Instances : DMA requests generation (UDE) *************/
-#define IS_TIM_DMA_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3) || \
-                                            ((INSTANCE) == TIM6) || \
-                                            ((INSTANCE) == TIM7))
-
-/************ TIM Instances : DMA requests generation (CCxDE) *****************/
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE)  (((INSTANCE) == TIM2) || \
-                                           ((INSTANCE) == TIM3))
-
-/************ TIM Instances : DMA requests generation (COMDE) *****************/
-#define IS_TIM_CCDMA_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2) || \
-                                            (INSTANCE) == TIM3))
-
-/******************** TIM Instances : DMA burst feature ***********************/
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
-                                            ((INSTANCE) == TIM3))
-
-/****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
-#define IS_TIM_MASTER_INSTANCE(INSTANCE)   (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM6)  || \
-                                            ((INSTANCE) == TIM7)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE)    (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/********************** TIM Instances : 32 bit Counter ************************/
-
-/***************** TIM Instances : external trigger input availabe ************/
-#define IS_TIM_ETR_INSTANCE(INSTANCE)      (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM21) || \
-                                            ((INSTANCE) == TIM22))
-
-/****************** TIM Instances : remapping capability **********************/
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)   || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM21)  || \
-                                         ((INSTANCE) == TIM22))
-
-/******************* TIM Instances : output(s) available **********************/
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-   (((((INSTANCE) == TIM2) ||                  \
-      ((INSTANCE) == TIM3))                    \
-     &&                                        \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-     ||                                        \
-     (((INSTANCE) == TIM21) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2)))          \
-     ||                                        \
-     (((INSTANCE) == TIM22) &&                 \
-      (((CHANNEL) == TIM_CHANNEL_1) ||         \
-       ((CHANNEL) == TIM_CHANNEL_2))))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART4) || \
-                                    ((INSTANCE) == USART5) || \
-                                    ((INSTANCE) == LPUART1))
-
-/******************** USART Instances : Synchronous mode **********************/
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART4) || \
-                                     ((INSTANCE) == USART5))
-
-/****************** USART Instances : Auto Baud Rate detection ****************/
-
-#define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                                            ((INSTANCE) == USART2))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART4) || \
-                                                 ((INSTANCE) == USART5) || \
-                                                 ((INSTANCE) == LPUART1))
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)    (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2))
-
-/******************** UART Instances : Wake-up from Stop mode **********************/
-
-#define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                      ((INSTANCE) == USART2) || \
-                                                      ((INSTANCE) == LPUART1))
-
-/****************** UART Instances : Hardware Flow control ********************/
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART4) || \
-                                           ((INSTANCE) == USART5) || \
-                                           ((INSTANCE) == LPUART1))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2))
-
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L0xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L0 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-#define LPUART1_IRQn                   RNG_LPUART1_IRQn
-#define AES_LPUART1_IRQn               RNG_LPUART1_IRQn
-#define AES_RNG_LPUART1_IRQn           RNG_LPUART1_IRQn
-#define TIM6_IRQn                      TIM6_DAC_IRQn
-#define RCC_IRQn                       RCC_CRS_IRQn
-
-/* Aliases for __IRQHandler */
-#define LPUART1_IRQHandler             RNG_LPUART1_IRQHandler
-#define AES_LPUART1_IRQHandler         RNG_LPUART1_IRQHandler
-#define AES_RNG_LPUART1_IRQHandler     RNG_LPUART1_IRQHandler
-#define TIM6_IRQHandler                TIM6_DAC_IRQHandler
-#define RCC_IRQHandler                 RCC_CRS_IRQHandler
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L073xx_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/stm32l0xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,233 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l0xx.h
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L0xx devices.            
-  *            
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *           - Configuration section that allows to select:
-  *              - The device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx
-  * @{
-  */
-    
-#ifndef __STM32L0xx_H
-#define __STM32L0xx_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-   
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/**
-  * @brief STM32 Family
-  */
-#if !defined (STM32L0)
-#define STM32L0
-#endif /* STM32L0 */
-
-/* Uncomment the line below according to the target STM32 device used in your
-   application 
-  */
-
-#if !defined (STM32L051xx) && !defined (STM32L052xx) && !defined (STM32L053xx) && !defined (STM32L061xx) && !defined (STM32L062xx) && !defined (STM32L063xx) \
- && !defined (STM32L071xx) && !defined (STM32L072xx) && !defined (STM32L073xx) && !defined (STM32L081xx) && !defined (STM32L082xx) && !defined (STM32L083xx)
-  /* #define STM32L051xx */   /*!< STM32L051K8, STM32L051C6, STM32L051C8, STM32L051R6, STM32L051R8 Devices */
-  /* #define STM32L052xx */   /*!< STM32L052K6, STM32L052K8, STM32L052C6, STM32L052C8, STM32L052R6, STM32L052R8 Devices */
-  /* #define STM32L053xx */   /*!< STM32L053C6, STM32L053C8, STM32L053R6, STM32L053R8 Devices */
-  /* #define STM32L061xx */   /*!< */
-  /* #define STM32L062xx */   /*!< STM32L062K8 */
-  /* #define STM32L063xx */   /*!< STM32L063C8, STM32L063R8 */ 
-  /* #define STM32L071xx */   /*!< */
-  /* #define STM32L072xx */   /*!< */
-#define STM32L073xx           /*!< STM32L073V8, STM32L073VB, STM32L073RB, STM32L073VZ, STM32L073RZ Devices */
-  /* #define STM32L081xx */   /*!< */
-  /* #define STM32L082xx */   /*!< */
-  /* #define STM32L083xx */   /*!< */ 
-#endif
-   
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V1.2.0
-  */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB1   (0x02) /*!< [23:16] sub1 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L0xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32L0xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
-                                             
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32L031xx)
-  #include "stm32l031xx.h"
-#elif defined(STM32L041xx)
-  #include "stm32l041xx.h"
-#elif defined(STM32L051xx)
-  #include "stm32l051xx.h"
-#elif defined(STM32L052xx)
-  #include "stm32l052xx.h"
-#elif defined(STM32L053xx)
-  #include "stm32l053xx.h"
-#elif defined(STM32L062xx)
-  #include "stm32l062xx.h"
-#elif defined(STM32L063xx)
-  #include "stm32l063xx.h"
-#elif defined(STM32L061xx)
-  #include "stm32l061xx.h"
-#elif defined(STM32L071xx)
-  #include "stm32l071xx.h"
-#elif defined(STM32L072xx)
-  #include "stm32l072xx.h"
-#elif defined(STM32L073xx)
-  #include "stm32l073xx.h"
-#elif defined(STM32L082xx)
-  #include "stm32l082xx.h"
-#elif defined(STM32L083xx)
-  #include "stm32l083xx.h"
-#elif defined(STM32L081xx)
-  #include "stm32l081xx.h"
-#else
- #error "Please select first the target STM32L0xx device used in your application (in stm32l0xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */ 
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macro
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l0xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L0xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,469 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.c
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l0xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | YES
-  *-----------------------------------------------------------------------------  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L0xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l0xx.h"
-#include "hal_tick.h"
-
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-   
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Defines
-  * @{
-  */
-/************************* Miscellaneous Configuration ************************/
-
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
-                                   This value must be a multiple of 0x200. */
-/******************************************************************************/
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000;
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t PLLMulTable_2[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{    
-/*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t) 0x88FF400C;
- 
-  /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xFEF6FFF6;
-  
-  /*!< Reset HSI48ON  bit */
-  RCC->CRRCR &= (uint32_t)0xFFFFFFFE;
-  
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIER = 0x00000000;
-  
-  /* Configure the Vector Table location add offset address ------------------*/
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
-#endif
-
-  /* Configure the Cube driver */
-  SystemCoreClock = 8000000; // At this stage the HSI is used as system clock
-  HAL_Init();
-
-  /* Configure the System clock source, PLL Multiplier and Divider factors,
-     AHB/APBx prescalers and Flash settings */
-  SetSysClock();
-
-  /* Reset the timer to avoid issues after the RAM initialization */
-  TIM_MST_RESET_ON;
-  TIM_MST_RESET_OFF;
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable_2[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-  // PLLCLK = (8 MHz * 8)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_8;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-  //  HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
- 
-  /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  RCC_OscInitStruct.HSI48State          = RCC_HSI48_ON; /* For USB and RNG clock */
-  // PLLCLK = (16 MHz * 4)/2 = 32 MHz
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLLMUL_4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLLDIV_2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/system_stm32l0xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l0xx.h
-  * @author  MCD Application Team
-  * @version V1.2.0
-  * @date    06-February-2015
-  * @brief   CMSIS Cortex-M0+ Device Peripheral Access Layer System Header File.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l0xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L0XX_H
-#define __SYSTEM_STM32L0XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L0xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L0xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L0xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L0XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

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-    <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: &quot;Arial&quot;,&quot;sans-serif&quot;; color: black;">Copyright
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-
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-            <div style="text-align: justify;">
-            <div style="text-align: justify;"><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:</span><br>
-            </font>
-            <ol><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Redistributions
-in binary form must reproduce the above copyright notice, this list of
-conditions and the following disclaimer in </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">the documentation and/or other materials provided with the distribution.</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span></font></li><li><font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
-                </font>
-              </li></ol>
-            <font size="-1"><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">&nbsp;&nbsp;&nbsp;&nbsp;&nbsp;&nbsp; from this software without specific prior written permission.</span><br>
-            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"></span><br>
-            <span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
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-            </div>
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-    complete documentation on </span><span style="font-size: 10pt; font-family: &quot;Verdana&quot;,&quot;sans-serif&quot;;">STM32<span style="color: black;">
-    Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
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--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/startup_stm32l152xc.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,325 +0,0 @@
-; STM32L152RC Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-                
-Stack_Mem       SPACE   Stack_Size
-__initial_sp    EQU     0x20008000 ; Top of RAM (32 KB)
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000400
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit    EQU (__initial_sp - Stack_Size)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/stm32l152rc.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L152RC: 256KB FLASH + 32KB SRAM
-LR_IROM1 0x08000000 0x40000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x124) (0x8000-0x124)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_MICRO/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/startup_stm32l152xc.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,298 +0,0 @@
-; STM32L152RC Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-__initial_sp    EQU     0x20008000 ; Top of RAM (32 KB)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/stm32l152rc.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L152RC: 256KB FLASH + 32KB SRAM
-LR_IROM1 0x08000000 0x40000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x124) (0x8000-0x124)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_ARM_STD/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/STM32L152XC.ld	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,156 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  /* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
-   * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
-   */
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k
-  RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_GCC_ARM/startup_stm32l152xc.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,421 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xc.s
-  * @author    MCD Application Team
-  * @version   V2.0.0
-  * @date      5-September-2014
-  * @brief     STM32L152XC Devices vector table for 
-  *            Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
-
-LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
-  bcc CopyDataInit
-  ldr r2, =_sbss
-  b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs r3, #0
-  str r3, [r2], #4
-
-LoopFillZerobss:
-  ldr r3, = _ebss
-  cmp r2, r3
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XE devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/startup_stm32l152xc.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,536 +0,0 @@
-;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xc.s
-;* Author             : MCD Application Team
-;* Version            : V1.0.0
-;* Date               : 5-September-2014
-;* Description        : STM32L152XC Devices vector for EWARM toolchain. 
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler
-
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/TOOLCHAIN_IAR/stm32l152xc.icf	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,30 +0,0 @@
-/* [ROM = 256kb = 0x40000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0803FFFF;
-
-/* [RAM = 32kb = 0x8000] Vector table dynamic copy: 73 vectors = 292 bytes (0x124) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x20000127; /* Add 4 more bytes to be aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x20000128;
-define symbol __region_RAM_end__      = 0x20007FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-define symbol __size_cstack__ = 0x800;
-define symbol __size_heap__   = 0x800;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32l1xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    uint32_t *vectors = (uint32_t *)SCB->VTOR;
-    uint32_t i;
-
-    // Copy and switch to dynamic vectors if the first time called
-    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = vectors;
-        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
-    }
-    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/cmsis_nvic.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// STM32L152RC
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123
-// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM
-#define NVIC_NUM_VECTORS      73
-#define NVIC_USER_IRQ_OFFSET  16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.c
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-#include "hal_tick.h"
-
-TIM_HandleTypeDef TimMasterHandle;
-uint32_t PreviousVal = 0;
-
-void us_ticker_irq_handler(void);
-
-void timer_irq_handler(void) {
-    // Channel 1 for mbed timeout
-    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
-        us_ticker_irq_handler();
-    }
-
-    // Channel 2 for HAL tick
-    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
-        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
-        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
-        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
-            // Increment HAL variable
-            HAL_IncTick();
-            // Prepare next interrupt
-            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
-            PreviousVal = val;
-#if 0 // For DEBUG only
-            HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
-#endif
-        }
-    }
-}
-
-// Reconfigure the HAL tick using a standard timer instead of systick.
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
-    // Enable timer clock
-    TIM_MST_RCC;
-
-    // Reset timer
-    TIM_MST_RESET_ON;
-    TIM_MST_RESET_OFF;
-
-    // Update the SystemCoreClock variable
-    SystemCoreClockUpdate();
-
-    // Configure time base
-    TimMasterHandle.Instance = TIM_MST;
-    TimMasterHandle.Init.Period            = 0xFFFFFFFF;
-    TimMasterHandle.Init.Prescaler         = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
-    TimMasterHandle.Init.ClockDivision     = 0;
-    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
-    HAL_TIM_OC_Init(&TimMasterHandle);
-
-    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
-    NVIC_EnableIRQ(TIM_MST_IRQ);
-
-    // Channel 1 for mbed timeout
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
-
-    // Channel 2 for HAL tick
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
-    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
-    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
-
-#if 0 // For DEBUG only
-    __GPIOB_CLK_ENABLE();
-    GPIO_InitTypeDef GPIO_InitStruct;
-    GPIO_InitStruct.Pin = GPIO_PIN_6;
-    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-    GPIO_InitStruct.Pull = GPIO_PULLUP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-#endif
-
-    return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/hal_tick.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.h
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32l1xx.h"
-#include "cmsis_nvic.h"
-   
-#define TIM_MST      TIM5
-#define TIM_MST_IRQ  TIM5_IRQn
-#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l152xc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,5793 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xc.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xc
-  * @{
-  */
-    
-#ifndef __STM32L152xC_H
-#define __STM32L152xC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200 /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< COMP comparator control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control/status register,                     Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x18                                                                  */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     ((uint32_t)(FLASH_BASE + 0x80000))  /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          ((uint32_t)0x22000000)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             ((uint32_t)0x0803FFFF)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      ((uint32_t)0x08081FFF)              /*!< FLASH EEPROM end address (8KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5C)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FF80000)    /*!< FLASH Option Bytes base address */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001C)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058)
-#define DBGMCU_BASE           ((uint32_t)0xE0042000)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define COMP                ((COMP_TypeDef *) COMP_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
-#define RI                  ((RI_TypeDef *) RI_BASE)
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!< Overrun flag */
-#define  ADC_SR_ADONS                        ((uint32_t)0x00000040)        /*!< ADC ON status */
-#define  ADC_SR_RCNR                         ((uint32_t)0x00000100)        /*!< Regular channel not ready flag */
-#define  ADC_SR_JCNR                         ((uint32_t)0x00000200)        /*!< Injected channel not ready flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
-
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
-
-#define  ADC_CR1_PDD                         ((uint32_t)0x00010000)        /*!< Power Down during Delay phase */
-#define  ADC_CR1_PDI                         ((uint32_t)0x00020000)        /*!< Power Down during Idle phase */
-
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
-
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!< RES[1:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
-
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)        /*!< Overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
-#define  ADC_CR2_CFG                         ((uint32_t)0x00000004)        /*!< ADC Configuration */
-
-#define  ADC_CR2_DELS                        ((uint32_t)0x00000070)        /*!< DELS[2:0] bits (Delay selection) */
-#define  ADC_CR2_DELS_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  ADC_CR2_DELS_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  ADC_CR2_DELS_2                      ((uint32_t)0x00000040)        /*!< Bit 2 */
-
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!< DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!< End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
-
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!< Start Conversion of injected channels */
-
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!< Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP20                     ((uint32_t)0x00000007)        /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
-#define  ADC_SMPR1_SMP20_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP20_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP20_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP21                     ((uint32_t)0x00000038)        /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
-#define  ADC_SMPR1_SMP21_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP21_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP21_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP22                     ((uint32_t)0x000001C0)        /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
-#define  ADC_SMPR1_SMP22_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP22_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP22_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP23                     ((uint32_t)0x00000E00)        /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
-#define  ADC_SMPR1_SMP23_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP23_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP23_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP24                     ((uint32_t)0x00007000)        /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
-#define  ADC_SMPR1_SMP24_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP24_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP24_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP25                     ((uint32_t)0x00038000)        /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
-#define  ADC_SMPR1_SMP25_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP25_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP25_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP26                     ((uint32_t)0x001C0000)        /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
-#define  ADC_SMPR1_SMP26_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP26_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP26_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP27                     ((uint32_t)0x00E00000)        /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
-#define  ADC_SMPR1_SMP27_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP27_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP27_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP28                     ((uint32_t)0x07000000)        /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
-#define  ADC_SMPR1_SMP28_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP28_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP28_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP29                     ((uint32_t)0x38000000)        /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
-#define  ADC_SMPR1_SMP29_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP29_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP29_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR2_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR2_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR2_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR2_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR2_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR2_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR2_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP18                     ((uint32_t)0x07000000)        /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR2_SMP18_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP18_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP18_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP19                     ((uint32_t)0x38000000)        /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
-#define  ADC_SMPR2_SMP19_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP19_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP19_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define  ADC_SMPR3_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR3_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
- 
-#define  ADC_SMPR3_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR3_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR3_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR3_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR3_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR3_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR3_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR3_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR3_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR3_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)         /*!< Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_L                          ((uint32_t)0x01F00000)        /*!< L[4:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR1_L_4                        ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ28                       ((uint32_t)0x000F8000)        /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
-#define  ADC_SQR1_SQ28_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ28_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ28_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ28_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ28_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ27                       ((uint32_t)0x00007C00)        /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
-#define  ADC_SQR1_SQ27_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ27_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ27_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ27_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ27_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ26                       ((uint32_t)0x000003E0)        /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
-#define  ADC_SQR1_SQ26_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ26_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ26_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ26_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ26_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ25                       ((uint32_t)0x0000001F)        /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
-#define  ADC_SQR1_SQ25_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ25_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ25_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ25_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ25_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ19                       ((uint32_t)0x0000001F)        /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
-#define  ADC_SQR2_SQ19_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ19_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ19_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ19_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ19_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ20                       ((uint32_t)0x000003E0)        /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
-#define  ADC_SQR2_SQ20_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ20_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ20_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ20_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ20_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ21                       ((uint32_t)0x00007C00)        /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
-#define  ADC_SQR2_SQ21_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ21_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ21_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ21_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ21_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ22                       ((uint32_t)0x000F8000)        /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
-#define  ADC_SQR2_SQ22_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ22_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ22_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ22_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ22_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ23                       ((uint32_t)0x01F00000)        /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
-#define  ADC_SQR2_SQ23_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ23_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ23_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ23_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ23_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ24                       ((uint32_t)0x3E000000)        /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
-#define  ADC_SQR2_SQ24_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ24_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ24_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ24_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ24_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR3_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR3_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR3_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR3_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ17                       ((uint32_t)0x01F00000)        /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
-#define  ADC_SQR3_SQ17_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ17_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ17_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ17_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ17_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ18                       ((uint32_t)0x3E000000)        /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
-#define  ADC_SQR3_SQ18_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ18_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ18_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ18_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ18_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define  ADC_SQR4_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR4_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR4_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR4_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ10                        ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR4_SQ10_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ10_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ10_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ10_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ10_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ11                        ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR4_SQ11_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ11_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ11_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ11_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ11_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ12                        ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR4_SQ12_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ12_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ12_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ12_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ12_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define  ADC_SQR5_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR5_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR5_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR5_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR5_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR5_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR5_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!< ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!< ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!< ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!< ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!< ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020)        /*!< ADC1 overrun  flag */
-#define  ADC_CSR_ADONS1                      ((uint32_t)0x00000040)        /*!< ADON status of ADC1 */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!< ADC prescaler*/
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */ 
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define  COMP_CSR_10KPU                      ((uint32_t)0x00000001)        /*!< 10K pull-up resistor */
-#define  COMP_CSR_400KPU                     ((uint32_t)0x00000002)        /*!< 400K pull-up resistor */
-#define  COMP_CSR_10KPD                      ((uint32_t)0x00000004)        /*!< 10K pull-down resistor */
-#define  COMP_CSR_400KPD                     ((uint32_t)0x00000008)        /*!< 400K pull-down resistor */
-#define  COMP_CSR_CMP1EN                     ((uint32_t)0x00000010)        /*!< Comparator 1 enable */
-#define  COMP_CSR_CMP1OUT                    ((uint32_t)0x00000080)        /*!< Comparator 1 output */
-
-#define  COMP_CSR_SPEED                      ((uint32_t)0x00001000)        /*!< Comparator 2 speed */
-#define  COMP_CSR_CMP2OUT                    ((uint32_t)0x00002000)        /*!< Comparator 2 ouput */
-#define  COMP_CSR_VREFOUTEN                  ((uint32_t)0x00010000)        /*!< Comparator Vref Enable */
-#define  COMP_CSR_WNDWE                      ((uint32_t)0x00020000)        /*!< Window mode enable */
-#define  COMP_CSR_INSEL                      ((uint32_t)0x001C0000)        /*!< INSEL[2:0] Inversion input Selection */
-#define  COMP_CSR_INSEL_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  COMP_CSR_INSEL_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  COMP_CSR_INSEL_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  COMP_CSR_OUTSEL                     ((uint32_t)0x00E00000)        /*!< OUTSEL[2:0] comparator 2 output redirection */
-#define  COMP_CSR_OUTSEL_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  COMP_CSR_OUTSEL_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  COMP_CSR_OUTSEL_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  COMP_CSR_FCH3                       ((uint32_t)0x04000000)        /*!< Bit 26 */
-#define  COMP_CSR_FCH8                       ((uint32_t)0x08000000)        /*!< Bit 27 */
-#define  COMP_CSR_RCH13                      ((uint32_t)0x10000000)        /*!< Bit 28 */
-
-#define  COMP_CSR_CAIE                       ((uint32_t)0x20000000)        /*!< Bit 29 */
-#define  COMP_CSR_CAIF                       ((uint32_t)0x40000000)        /*!< Bit 30 */
-#define  COMP_CSR_TSUSP                      ((uint32_t)0x80000000)        /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD                     ((uint32_t)0x00000001)        /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1                     ((uint32_t)0x00000002)        /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1                     ((uint32_t)0x00000004)        /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1                     ((uint32_t)0x00000008)        /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1                     ((uint32_t)0x00000010)        /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L                  ((uint32_t)0x00000020)        /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H                  ((uint32_t)0x00000040)        /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM                    ((uint32_t)0x00000080)        /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD                     ((uint32_t)0x00000100)        /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2                     ((uint32_t)0x00000200)        /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2                     ((uint32_t)0x00000400)        /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2                     ((uint32_t)0x00000800)        /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2                     ((uint32_t)0x00001000)        /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L                  ((uint32_t)0x00002000)        /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H                  ((uint32_t)0x00004000)        /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM                    ((uint32_t)0x00008000)        /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1                   ((uint32_t)0x01000000)        /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2                   ((uint32_t)0x02000000)        /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2                     ((uint32_t)0x08000000)        /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE                  ((uint32_t)0x10000000)        /*!< Power range selection */
-#define OPAMP_CSR_OPA1CALOUT                 ((uint32_t)0x20000000)        /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT                 ((uint32_t)0x40000000)        /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW    ((uint32_t)0x0000001F)        /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH   ((uint32_t)0x000003E0)        /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW    ((uint32_t)0x00007C00)        /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH   ((uint32_t)0x000F8000)        /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER                    ((uint32_t)0x80000000)        /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  ((uint32_t)0x0000001F)        /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0)        /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  ((uint32_t)0x00007C00)        /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000)        /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)        /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0x000000FF)               /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001)        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Interrupt enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x00000002)        /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0x0000FF00)        /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint_t)0x00000FFF)          /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP             ((uint32_t)0x00000001)   /*!< TIM2 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP             ((uint32_t)0x00000002)   /*!< TIM3 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP             ((uint32_t)0x00000004)   /*!< TIM4 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP             ((uint32_t)0x00000008)   /*!< TIM5 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP             ((uint32_t)0x00000010)   /*!< TIM6 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP             ((uint32_t)0x00000020)   /*!< TIM7 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP              ((uint32_t)0x00000400)   /*!< RTC Counter stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP             ((uint32_t)0x00000800)   /*!< Debug Window Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP             ((uint32_t)0x00001000)   /*!< Debug Independent Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< SMBUS timeout mode stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)   /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP             ((uint32_t)0x00000004)   /*!< TIM9 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP            ((uint32_t)0x00000008)   /*!< TIM10 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP            ((uint32_t)0x00000010)   /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define  DMA_CCR_EN                         ((uint32_t)0x00000001)            /*!< Channel enable*/
-#define  DMA_CCR_TCIE                       ((uint32_t)0x00000002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR_HTIE                       ((uint32_t)0x00000004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR_TEIE                       ((uint32_t)0x00000008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR_DIR                        ((uint32_t)0x00000010)            /*!< Data transfer direction */
-#define  DMA_CCR_CIRC                       ((uint32_t)0x00000020)            /*!< Circular mode */
-#define  DMA_CCR_PINC                       ((uint32_t)0x00000040)            /*!< Peripheral increment mode */
-#define  DMA_CCR_MINC                       ((uint32_t)0x00000080)            /*!< Memory increment mode */
-
-#define  DMA_CCR_PSIZE                      ((uint32_t)0x00000300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR_PSIZE_0                    ((uint32_t)0x00000100)            /*!< Bit 0 */
-#define  DMA_CCR_PSIZE_1                    ((uint32_t)0x00000200)            /*!< Bit 1 */
-
-#define  DMA_CCR_MSIZE                      ((uint32_t)0x00000C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR_MSIZE_0                    ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  DMA_CCR_MSIZE_1                    ((uint32_t)0x00000800)            /*!< Bit 1 */
-
-#define  DMA_CCR_PL                         ((uint32_t)0x00003000)            /*!< PL[1:0] bits(Channel Priority level) */
-#define  DMA_CCR_PL_0                       ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  DMA_CCR_PL_1                       ((uint32_t)0x00002000)            /*!< Bit 1 */
-
-#define  DMA_CCR_MEM2MEM                    ((uint32_t)0x00004000)            /*!< Memory to memory mode */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define  DMA_CNDTR1_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define  DMA_CNDTR2_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define  DMA_CNDTR3_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define  DMA_CNDTR4_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define  DMA_CNDTR5_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define  DMA_CNDTR6_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define  DMA_CNDTR7_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)            /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)            /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
-#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< Latency */
-#define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_ACC64                     ((uint32_t)0x00000004)        /*!< Access 64 bits */
-#define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
-#define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
-#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
-#define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
-#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
-#define  FLASH_SR_ENDHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */
-#define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
-
-#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protected error */
-#define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
-#define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
-#define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option validity error */
-#define  FLASH_SR_OPTVERRUSR                 ((uint32_t)0x00001000)        /*!< Option User validity error */
-#define  FLASH_SR_RDERR                      ((uint32_t)0x00002000)        /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_RDPRT                     ((uint32_t)0x000000FF)        /*!< Read Protection */
-#define  FLASH_OBR_SPRMOD                    ((uint32_t)0x00000100)        /*!< Selection of protection mode of WPRi bits */
-#define  FLASH_OBR_BOR_LEV                   ((uint32_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define  FLASH_OBR_USER                      ((uint32_t)0x00700000)        /*!< User Option Bytes */
-#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00100000)        /*!< IWDG_SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00200000)        /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00400000)        /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR1_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
-#define  FLASH_WRPR2_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
-
-#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
-
-#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
-
-#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
-
-#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
-
-#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
-
-#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
-
-#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
-
-#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
-
-#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
-
-#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
-
-#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
-
-#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
-
-#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
-
-#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
-
-#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
-
-#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
-
-#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
-
-#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
-
-#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
-
-#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
-
-#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
-
-#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
-
-#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
-
-#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
-
-#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
-
-#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
-
-#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
-
-#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
-
-#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
-
-#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
-
-#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
-
-#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
-
-#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
-
-#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
-
-#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
-
-#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
-
-#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
-
-#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
-
-#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
-
-#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
-
-#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
-
-#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
-
-#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
-
-#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)            /*!< Peripheral Enable */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)            /*!< SMBus Mode */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)            /*!< SMBus Type */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)            /*!< ARP Enable */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)            /*!< PEC Enable */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)            /*!< General Call Enable */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)            /*!< Clock Stretching Disable (Slave mode) */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100)            /*!< Start Generation */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200)            /*!< Stop Generation */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400)            /*!< Acknowledge Enable */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800)            /*!< Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000)            /*!< Packet Error Checking */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)            /*!< SMBus Alert */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)            /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)            /*!< Bit 5 */
-
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)            /*!< Error Interrupt Enable */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)            /*!< Event Interrupt Enable */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)            /*!< Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)            /*!< DMA Requests Enable */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000)            /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)            /*!< Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)            /*!< Interface Address */
-
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)            /*!< Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)            /*!< Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)            /*!< Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)            /*!< Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)            /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)               /*!< Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)               /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FF)               /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001)            /*!< Start Bit (Master mode) */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)            /*!< Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004)            /*!< Byte Transfer Finished */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)            /*!< 10-bit header sent (Master mode) */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)            /*!< Stop detection (Slave mode) */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)            /*!< Data Register not Empty (receivers) */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080)            /*!< Data Register Empty (transmitters) */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100)            /*!< Bus Error */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)            /*!< Arbitration Lost (master mode) */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400)            /*!< Acknowledge Failure */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800)            /*!< Overrun/Underrun */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)            /*!< PEC Error in reception */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)            /*!< Timeout or Tlow Error */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)            /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001)            /*!< Master/Slave */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)            /*!< Bus Busy */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004)            /*!< Transmitter/Receiver */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)            /*!< General Call Address (Slave mode) */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)            /*!< SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)            /*!< SMBus Host Header (Slave mode) */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)            /*!< Dual Flag (Slave mode) */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)            /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)            /*!< Fast Mode Duty Cycle */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000)            /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0x0000FFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x00000007)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x00000001)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x00000002)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x00000004)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x00000FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x00000001)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint32_t)0x00000002)               /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */
-#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */
-
-#define LCD_CR_MUX_SEG             ((uint32_t)0x00000080)     /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */
-#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */
-#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */
-
-#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */
-#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */
-#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */
-
-#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */
-#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */
-#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */
-#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */
-
-#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */
-#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */
-#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPSDSR                       ((uint32_t)0x00000001)     /*!< Low-power deepsleep/sleep/low power run */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection */
-#define  PWR_CR_ULP                          ((uint32_t)0x00000200)     /*!< Ultra Low Power mode */
-#define  PWR_CR_FWU                          ((uint32_t)0x00000400)     /*!< Fast wakeup */
-
-#define  PWR_CR_VOS                          ((uint32_t)0x00001800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00000800)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00001000)     /*!< Bit 1 */
-#define  PWR_CR_LPRUN                        ((uint32_t)0x00004000)     /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output */
-#define  PWR_CSR_VREFINTRDYF                 ((uint32_t)0x00000008)     /*!< Internal voltage reference (VREFINT) ready flag */
-#define  PWR_CSR_VOSF                        ((uint32_t)0x00000010)     /*!< Voltage Scaling select flag */
-#define  PWR_CSR_REGLPF                      ((uint32_t)0x00000020)     /*!< Regulator LP flag */
-
-#define  PWR_CSR_EWUP1                       ((uint32_t)0x00000100)     /*!< Enable WKUP pin 1 */
-#define  PWR_CSR_EWUP2                       ((uint32_t)0x00000200)     /*!< Enable WKUP pin 2 */
-#define  PWR_CSR_EWUP3                       ((uint32_t)0x00000400)     /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
-
-#define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
-#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-#define  RCC_CR_CSSON                        ((uint32_t)0x10000000)        /*!< Clock Security System enable */
-
-#define  RCC_CR_RTCPRE                       ((uint32_t)0x60000000)        /*!< RTC/LCD Prescaler */
-#define  RCC_CR_RTCPRE_0                     ((uint32_t)0x20000000)        /*!< Bit0 */
-#define  RCC_CR_RTCPRE_1                     ((uint32_t)0x40000000)        /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
-#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
-
-#define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
-#define  RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define  RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define  RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define  RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define  RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define  RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define  RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
-#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-/*!< SW configuration */
-#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
-
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
-
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
-#define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
-#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
-#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
-#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
-#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
-#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
-#define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
-#define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
-#define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
-#define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
-
-
-/*!< PLLDIV configuration */
-#define  RCC_CFGR_PLLDIV1                    ((uint32_t)0x00000000)        /*!< PLL clock output = CKVCO / 1 */
-#define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
-#define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
-#define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
-
-
-#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-/*!< MCO configuration */
-#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected */
-#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
-#define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
-#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
-#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
-#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
-#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
-
-#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000)        /*!< Bit 2 */
-
-/*!< MCO Prescaler configuration */
-#define  RCC_CFGR_MCO_DIV1                   ((uint32_t)0x00000000)        /*!< MCO Clock divided by 1 */
-#define  RCC_CFGR_MCO_DIV2                   ((uint32_t)0x10000000)        /*!< MCO Clock divided by 2 */
-#define  RCC_CFGR_MCO_DIV4                   ((uint32_t)0x20000000)        /*!< MCO Clock divided by 4 */
-#define  RCC_CFGR_MCO_DIV8                   ((uint32_t)0x30000000)        /*!< MCO Clock divided by 8 */
-#define  RCC_CFGR_MCO_DIV16                  ((uint32_t)0x40000000)        /*!< MCO Clock divided by 16 */
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
-#define  RCC_CIR_LSECSS                      ((uint32_t)0x00000040)        /*!< LSE CSS Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_MSIRDYIE                    ((uint32_t)0x00002000)        /*!< MSI Ready Interrupt Enable */
-#define  RCC_CIR_LSECSSIE                    ((uint32_t)0x00004000)        /*!< LSE CSS Interrupt Enable */
-
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_MSIRDYC                     ((uint32_t)0x00200000)        /*!< MSI Ready Interrupt Clear */
-#define  RCC_CIR_LSECSSC                     ((uint32_t)0x00400000)        /*!< LSE CSS Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
-#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
-#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
-#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
-#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */
-#define  RCC_AHBRSTR_GPIOHRST                ((uint32_t)0x00000020)        /*!< GPIO port H reset */
-#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
-#define  RCC_AHBRSTR_FLITFRST                ((uint32_t)0x00008000)        /*!< FLITF reset */
-#define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x01000000)        /*!< DMA1 reset */
-#define  RCC_AHBRSTR_DMA2RST                 ((uint32_t)0x02000000)        /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< System Configuration SYSCFG reset */
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00000004)        /*!< TIM9 reset */
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00000008)        /*!< TIM10 reset */
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00000010)        /*!< TIM11 reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
-#define  RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
-#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
-#define  RCC_APB1RSTR_COMPRST                ((uint32_t)0x80000000)        /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
-#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
-#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
-#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
-#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */
-#define  RCC_AHBENR_GPIOHEN                  ((uint32_t)0x00000020)        /*!< GPIO port H clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00008000)        /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x01000000)        /*!< DMA1 clock enable */
-#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x02000000)        /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enable */
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00000004)         /*!< TIM9 interface clock enable */
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00000008)         /*!< TIM10 interface clock enable */
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC1 clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
-#define  RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
-#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
-#define  RCC_APB1ENR_COMPEN                  ((uint32_t)0x80000000)        /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define  RCC_AHBLPENR_GPIOALPEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOBLPEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOCLPEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIODLPEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOELPEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOHLPEN              ((uint32_t)0x00000020)        /*!< GPIO port H clock enabled in sleep mode */
-#define  RCC_AHBLPENR_CRCLPEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
-#define  RCC_AHBLPENR_FLITFLPEN              ((uint32_t)0x00008000)        /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define  RCC_AHBLPENR_SRAMLPEN               ((uint32_t)0x00010000)        /*!< SRAM clock enabled in sleep mode */
-#define  RCC_AHBLPENR_DMA1LPEN               ((uint32_t)0x01000000)        /*!< DMA1 clock enabled in sleep mode */
-#define  RCC_AHBLPENR_DMA2LPEN               ((uint32_t)0x02000000)        /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00000004)         /*!< TIM9 interface clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00000008)         /*!< TIM10 interface clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enabled in sleep mode */
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000200)         /*!< ADC1 clock enabled in sleep mode */
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)         /*!< SPI1 clock enabled in sleep mode */
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00004000)         /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)        /*!< Timer 4 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)        /*!< Timer 5 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_LCDLPEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)        /*!< SPI 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)        /*!< SPI 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)        /*!< USART 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)        /*!< USART 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)        /*!< I2C 1 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)        /*!< I2C 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USBLPEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)        /*!< Power interface clock enabled in sleep mode */
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)        /*!< DAC interface clock enabled in sleep mode */
-#define  RCC_APB1LPENR_COMPLPEN              ((uint32_t)0x80000000)        /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define  RCC_CSR_LSION                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                     ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-
-#define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
-#define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
-#define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_CSR_LSECSSON                   ((uint32_t)0x00000800)        /*!< External Low Speed oscillator CSS Enable */
-#define  RCC_CSR_LSECSSD                    ((uint32_t)0x00001000)        /*!< External Low Speed oscillator CSS Detected */
-
-#define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define  RCC_CSR_RTCEN                      ((uint32_t)0x00400000)        /*!< RTC clock enable */
-#define  RCC_CSR_RTCRST                     ((uint32_t)0x00800000)        /*!< RTC reset  */
- 
-#define  RCC_CSR_RMVF                       ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_OBLRSTF                    ((uint32_t)0x02000000)        /*!< Option Bytes Loader reset flag */
-#define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
-#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!< Master Selection */
-
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!< Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!< Receive only */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!< Data Frame Format */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)               /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)               /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)               /*!< SS Output Enable */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)               /*!< Frame format */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)               /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)               /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)               /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)               /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002)               /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)               /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008)               /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)               /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020)               /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040)               /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080)               /*!< Busy flag */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100)               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
-#define SYSCFG_MEMRMP_BOOT_MODE         ((uint32_t)0x00000300) /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       ((uint32_t)0x00000200) /*!< Bit 1 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU               ((uint32_t)0x00000001) /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000005) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000006) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000007) /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000050) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000060) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000070) /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000500) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000600) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000700) /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00003000) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00004000) /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000006) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000007) /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000060) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000070) /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000600) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000700) /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00006000) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00007000) /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000006) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000007) /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000060) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000070) /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000600) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000700) /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00006000) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00007000) /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000006) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000007) /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000060) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000070) /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000600) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000700) /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00006000) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00007000) /*!< PG[15] pin */
- 
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define  RI_ICR_IC1OS                    ((uint32_t)0x0000000F) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define  RI_ICR_IC1OS_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ICR_IC1OS_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ICR_IC1OS_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ICR_IC1OS_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define  RI_ICR_IC2OS                    ((uint32_t)0x000000F0) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define  RI_ICR_IC2OS_0                  ((uint32_t)0x00000010) /*!< Bit 0 */
-#define  RI_ICR_IC2OS_1                  ((uint32_t)0x00000020) /*!< Bit 1 */
-#define  RI_ICR_IC2OS_2                  ((uint32_t)0x00000040) /*!< Bit 2 */
-#define  RI_ICR_IC2OS_3                  ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define  RI_ICR_IC3OS                    ((uint32_t)0x00000F00) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define  RI_ICR_IC3OS_0                  ((uint32_t)0x00000100) /*!< Bit 0 */
-#define  RI_ICR_IC3OS_1                  ((uint32_t)0x00000200) /*!< Bit 1 */
-#define  RI_ICR_IC3OS_2                  ((uint32_t)0x00000400) /*!< Bit 2 */
-#define  RI_ICR_IC3OS_3                  ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define  RI_ICR_IC4OS                    ((uint32_t)0x0000F000) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define  RI_ICR_IC4OS_0                  ((uint32_t)0x00001000) /*!< Bit 0 */
-#define  RI_ICR_IC4OS_1                  ((uint32_t)0x00002000) /*!< Bit 1 */
-#define  RI_ICR_IC4OS_2                  ((uint32_t)0x00004000) /*!< Bit 2 */
-#define  RI_ICR_IC4OS_3                  ((uint32_t)0x00008000) /*!< Bit 3 */
-
-#define  RI_ICR_TIM                     ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
-#define  RI_ICR_TIM_0                   ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_ICR_TIM_1                   ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define  RI_ICR_IC1                     ((uint32_t)0x00040000) /*!< Input capture 1 */
-#define  RI_ICR_IC2                     ((uint32_t)0x00080000) /*!< Input capture 2 */
-#define  RI_ICR_IC3                     ((uint32_t)0x00100000) /*!< Input capture 3 */
-#define  RI_ICR_IC4                     ((uint32_t)0x00200000) /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define  RI_ASCR1_CH                    ((uint32_t)0x7BFDFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define  RI_ASCR1_CH_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASCR1_CH_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASCR1_CH_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASCR1_CH_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASCR1_CH_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASCR1_CH_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASCR1_CH_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASCR1_CH_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASCR1_CH_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASCR1_CH_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASCR1_CH_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASCR1_CH_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASCR1_CH_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASCR1_CH_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASCR1_CH_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASCR1_CH_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-#define  RI_ASCR1_CH_31                 ((uint32_t)0x00010000) /*!< Bit 16 */
-#define  RI_ASCR1_CH_18                 ((uint32_t)0x00040000) /*!< Bit 18 */
-#define  RI_ASCR1_CH_19                 ((uint32_t)0x00080000) /*!< Bit 19 */
-#define  RI_ASCR1_CH_20                 ((uint32_t)0x00100000) /*!< Bit 20 */
-#define  RI_ASCR1_CH_21                 ((uint32_t)0x00200000) /*!< Bit 21 */
-#define  RI_ASCR1_CH_22                 ((uint32_t)0x00400000) /*!< Bit 22 */
-#define  RI_ASCR1_CH_23                 ((uint32_t)0x00800000) /*!< Bit 23 */
-#define  RI_ASCR1_CH_24                 ((uint32_t)0x01000000) /*!< Bit 24 */
-#define  RI_ASCR1_CH_25                 ((uint32_t)0x02000000) /*!< Bit 25 */
-#define  RI_ASCR1_VCOMP                 ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
-#define  RI_ASCR1_CH_27                 ((uint32_t)0x00400000) /*!< Bit 27 */
-#define  RI_ASCR1_CH_28                 ((uint32_t)0x00800000) /*!< Bit 28 */
-#define  RI_ASCR1_CH_29                 ((uint32_t)0x01000000) /*!< Bit 29 */
-#define  RI_ASCR1_CH_30                 ((uint32_t)0x02000000) /*!< Bit 30 */
-#define  RI_ASCR1_SCM                   ((uint32_t)0x80000000) /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define  RI_ASCR2_GR10_1                ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
-#define  RI_ASCR2_GR10_2                ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
-#define  RI_ASCR2_GR10_3                ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
-#define  RI_ASCR2_GR10_4                ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
-#define  RI_ASCR2_GR6_1                 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
-#define  RI_ASCR2_GR6_2                 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
-#define  RI_ASCR2_GR5_1                 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
-#define  RI_ASCR2_GR5_2                 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
-#define  RI_ASCR2_GR5_3                 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
-#define  RI_ASCR2_GR4_1                 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
-#define  RI_ASCR2_GR4_2                 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
-#define  RI_ASCR2_GR4_3                 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
-#define  RI_ASCR2_GR4_4                 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
-#define  RI_ASCR2_CH0b                  ((uint32_t)0x00010000) /*!< CH0b selection bit */
-#define  RI_ASCR2_GR6_3                 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
-#define  RI_ASCR2_GR6_4                 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define  RI_HYSCR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
-#define  RI_HYSCR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR1_PB                   ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
-#define  RI_HYSCR1_PB_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR1_PB_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR1_PB_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR1_PB_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR1_PB_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR1_PB_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR1_PB_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR1_PB_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR1_PB_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR1_PB_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR1_PB_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR1_PB_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR1_PB_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR1_PB_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR1_PB_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR1_PB_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define  RI_HYSCR2_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
-#define  RI_HYSCR2_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR2_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR2_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR2_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR2_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR2_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR2_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR2_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR2_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR2_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR2_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR2_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR2_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR2_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR2_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR2_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR2_PD                   ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
-#define  RI_HYSCR2_PD_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR2_PD_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR2_PD_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR2_PD_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR2_PD_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR2_PD_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR2_PD_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR2_PD_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR2_PD_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR2_PD_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR2_PD_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR2_PD_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR2_PD_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR2_PD_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR2_PD_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR2_PD_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define  RI_HYSCR3_PE                   ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
-#define  RI_HYSCR3_PE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR3_PE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR3_PE_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR3_PE_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR3_PE_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR3_PE_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR3_PE_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR3_PE_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR3_PE_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR3_PE_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR3_PE_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR3_PE_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR3_PE_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR3_PE_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR3_PE_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR3_PE_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define  RI_ASMR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_ASMR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define  RI_CMR1_PA                    ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_CMR1_PA_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR1_PA_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR1_PA_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR1_PA_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR1_PA_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR1_PA_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR1_PA_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR1_PA_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR1_PA_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR1_PA_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR1_PA_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR1_PA_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR1_PA_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR1_PA_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR1_PA_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR1_PA_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define  RI_CICR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_CICR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define  RI_ASMR2_PB                   ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_ASMR2_PB_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR2_PB_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR2_PB_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR2_PB_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR2_PB_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR2_PB_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR2_PB_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR2_PB_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR2_PB_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR2_PB_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR2_PB_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR2_PB_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR2_PB_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR2_PB_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR2_PB_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR2_PB_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define  RI_CMR2_PB                    ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_CMR2_PB_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR2_PB_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR2_PB_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR2_PB_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR2_PB_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR2_PB_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR2_PB_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR2_PB_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR2_PB_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR2_PB_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR2_PB_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR2_PB_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR2_PB_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR2_PB_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR2_PB_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR2_PB_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define  RI_CICR2_PB                   ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_CICR2_PB_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR2_PB_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR2_PB_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR2_PB_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR2_PB_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR2_PB_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR2_PB_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR2_PB_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR2_PB_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR2_PB_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR2_PB_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR2_PB_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR2_PB_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR2_PB_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR2_PB_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR2_PB_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define  RI_ASMR3_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_ASMR3_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR3_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR3_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR3_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR3_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR3_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR3_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR3_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR3_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR3_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR3_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR3_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR3_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR3_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR3_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR3_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define  RI_CMR3_PC                    ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_CMR3_PC_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR3_PC_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR3_PC_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR3_PC_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR3_PC_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR3_PC_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR3_PC_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR3_PC_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR3_PC_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR3_PC_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR3_PC_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR3_PC_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR3_PC_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR3_PC_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR3_PC_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR3_PC_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define  RI_CICR3_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_CICR3_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR3_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR3_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR3_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR3_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR3_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR3_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR3_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR3_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR3_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR3_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR3_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR3_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR3_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR3_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR3_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x00000001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x00000002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint32_t)0x00000004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x00000008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint32_t)0x00000010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint32_t)0x00000060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x00000020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x00000040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint32_t)0x00000080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint32_t)0x00000300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x00000007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x00000001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_TIE                        ((uint32_t)0x00000040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_UDE                        ((uint32_t)0x00000100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x00000200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x00001000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint32_t)0x00004000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x00000001)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x00000002)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x00000004)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x00000008)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x00000010)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x00000040)               /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x00000070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x00007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0x0000FFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0x0000FFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0x0000FFFF)            /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x0000001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x00000010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint32_t)0x00001F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x00000800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x00001000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0x0000FFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define  TIM_OR_TI1RMP                       ((uint32_t)0x00000003)            /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define  TIM_OR_TI1RMP_0                     ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_OR_TI1RMP_1                     ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_OR_ETR_RMP                      ((uint32_t)0x00000004)            /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define  TIM_OR_TI1_RMP_RI                   ((uint32_t)0x00000008)            /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM9_OR_ITR1_RMP                    ((uint32_t)0x00000004)            /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM2_OR_ITR1_RMP                    ((uint32_t)0x00000001)            /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM3_OR_ITR2_RMP                    ((uint32_t)0x00000001)            /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x00000001)            /*!< Parity Error */
-#define  USART_SR_FE                         ((uint32_t)0x00000002)            /*!< Framing Error */
-#define  USART_SR_NE                         ((uint32_t)0x00000004)            /*!< Noise Error Flag */
-#define  USART_SR_ORE                        ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define  USART_SR_IDLE                       ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define  USART_SR_RXNE                       ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define  USART_SR_TXE                        ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define  USART_SR_CTS                        ((uint32_t)0x00000200)            /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x000001FF)            /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint32_t)0x0000000F)            /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint32_t)0x0000FFF0)            /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x00000001)            /*!< Send Break */
-#define  USART_CR1_RWU                       ((uint32_t)0x00000002)            /*!< Receiver wakeup */
-#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Wakeup method */
-#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
-#define  USART_CR1_UE                        ((uint32_t)0x00002000)            /*!< USART Enable */
-#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x0000000F)            /*!< Address of the USART node */
-#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-
-#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-
-#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< Smartcard NACK enable */
-#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< Smartcard mode enable */
-#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x000000FF)            /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x00000040)            /*!< Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x00000080)            /*!< Bit 7 */
-
-#define  USART_GTPR_GT                       ((uint32_t)0x0000FF00)            /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000C)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001C)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define  USB_EP_CTR_RX                        ((uint32_t)0x00008000)           /*!<  EndPoint Correct TRansfer RX */
-#define  USB_EP_DTOG_RX                       ((uint32_t)0x00004000)           /*!<  EndPoint Data TOGGLE RX */
-#define  USB_EPRX_STAT                        ((uint32_t)0x00003000)           /*!<  EndPoint RX STATus bit field */
-#define  USB_EP_SETUP                         ((uint32_t)0x00000800)           /*!<  EndPoint SETUP */
-#define  USB_EP_T_FIELD                       ((uint32_t)0x00000600)           /*!<  EndPoint TYPE */
-#define  USB_EP_KIND                          ((uint32_t)0x00000100)           /*!<  EndPoint KIND */
-#define  USB_EP_CTR_TX                        ((uint32_t)0x00000080)           /*!<  EndPoint Correct TRansfer TX */
-#define  USB_EP_DTOG_TX                       ((uint32_t)0x00000040)           /*!<  EndPoint Data TOGGLE TX */
-#define  USB_EPTX_STAT                        ((uint32_t)0x00000030)           /*!<  EndPoint TX STATus bit field */
-#define  USB_EPADDR_FIELD                     ((uint32_t)0x0000000F)           /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define  USB_EP_TYPE_MASK                     ((uint32_t)0x00000600)           /*!< EndPoint TYPE Mask */
-#define  USB_EP_BULK                          ((uint32_t)0x00000000)           /*!< EndPoint BULK */
-#define  USB_EP_CONTROL                       ((uint32_t)0x00000200)           /*!< EndPoint CONTROL */
-#define  USB_EP_ISOCHRONOUS                   ((uint32_t)0x00000400)           /*!< EndPoint ISOCHRONOUS */
-#define  USB_EP_INTERRUPT                     ((uint32_t)0x00000600)           /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define  USB_EP_TX_DIS                        ((uint32_t)0x00000000)           /*!< EndPoint TX DISabled */
-#define  USB_EP_TX_STALL                      ((uint32_t)0x00000010)           /*!< EndPoint TX STALLed */
-#define  USB_EP_TX_NAK                        ((uint32_t)0x00000020)           /*!< EndPoint TX NAKed */
-#define  USB_EP_TX_VALID                      ((uint32_t)0x00000030)           /*!< EndPoint TX VALID */
-#define  USB_EPTX_DTOG1                       ((uint32_t)0x00000010)           /*!< EndPoint TX Data TOGgle bit1 */
-#define  USB_EPTX_DTOG2                       ((uint32_t)0x00000020)           /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define  USB_EP_RX_DIS                        ((uint32_t)0x00000000)           /*!< EndPoint RX DISabled */
-#define  USB_EP_RX_STALL                      ((uint32_t)0x00001000)           /*!< EndPoint RX STALLed */
-#define  USB_EP_RX_NAK                        ((uint32_t)0x00002000)           /*!< EndPoint RX NAKed */
-#define  USB_EP_RX_VALID                      ((uint32_t)0x00003000)           /*!< EndPoint RX VALID */
-#define  USB_EPRX_DTOG1                       ((uint32_t)0x00001000)           /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOG2                       ((uint32_t)0x00002000)           /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define  USB_EP0R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP0R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP0R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP0R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP0R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP0R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP0R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP0R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP0R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP0R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP0R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP0R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP0R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP0R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP0R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP0R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define  USB_EP1R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP1R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP1R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP1R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP1R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP1R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP1R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP1R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP1R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP1R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP1R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP1R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP1R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP1R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP1R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP1R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define  USB_EP2R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP2R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP2R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP2R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP2R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP2R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP2R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP2R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP2R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP2R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP2R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP2R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP2R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP2R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP2R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP2R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define  USB_EP3R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP3R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP3R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP3R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP3R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP3R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP3R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP3R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP3R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP3R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP3R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP3R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP3R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP3R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP3R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP3R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define  USB_EP4R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP4R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP4R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP4R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP4R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP4R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP4R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP4R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP4R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP4R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP4R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP4R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP4R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP4R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP4R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP4R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define  USB_EP5R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP5R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP5R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP5R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP5R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP5R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP5R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP5R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP5R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP5R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP5R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP5R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP5R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP5R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP5R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP5R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define  USB_EP6R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP6R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP6R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP6R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP6R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP6R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP6R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP6R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP6R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP6R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP6R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP6R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP6R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP6R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP6R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP6R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define  USB_EP7R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP7R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP7R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP7R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP7R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP7R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP7R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP7R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP7R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP7R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP7R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP7R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP7R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP7R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP7R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP7R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004C)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define  USB_CNTR_FRES                       ((uint32_t)0x00000001)            /*!<Force USB Reset */
-#define  USB_CNTR_PDWN                       ((uint32_t)0x00000002)            /*!<Power down */
-#define  USB_CNTR_LP_MODE                    ((uint32_t)0x00000004)            /*!<Low-power mode */
-#define  USB_CNTR_FSUSP                      ((uint32_t)0x00000008)            /*!<Force suspend */
-#define  USB_CNTR_RESUME                     ((uint32_t)0x00000010)            /*!<Resume request */
-#define  USB_CNTR_ESOFM                      ((uint32_t)0x00000100)            /*!<Expected Start Of Frame Interrupt Mask */
-#define  USB_CNTR_SOFM                       ((uint32_t)0x00000200)            /*!<Start Of Frame Interrupt Mask */
-#define  USB_CNTR_RESETM                     ((uint32_t)0x00000400)            /*!<RESET Interrupt Mask */
-#define  USB_CNTR_SUSPM                      ((uint32_t)0x00000800)            /*!<Suspend mode Interrupt Mask */
-#define  USB_CNTR_WKUPM                      ((uint32_t)0x00001000)            /*!<Wakeup Interrupt Mask */
-#define  USB_CNTR_ERRM                       ((uint32_t)0x00002000)            /*!<Error Interrupt Mask */
-#define  USB_CNTR_PMAOVRM                    ((uint32_t)0x00004000)            /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define  USB_CNTR_CTRM                       ((uint32_t)0x00008000)            /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define  USB_ISTR_EP_ID                      ((uint32_t)0x0000000F)            /*!<Endpoint Identifier */
-#define  USB_ISTR_DIR                        ((uint32_t)0x00000010)            /*!<Direction of transaction */
-#define  USB_ISTR_ESOF                       ((uint32_t)0x00000100)            /*!<Expected Start Of Frame */
-#define  USB_ISTR_SOF                        ((uint32_t)0x00000200)            /*!<Start Of Frame */
-#define  USB_ISTR_RESET                      ((uint32_t)0x00000400)            /*!<USB RESET request */
-#define  USB_ISTR_SUSP                       ((uint32_t)0x00000800)            /*!<Suspend mode request */
-#define  USB_ISTR_WKUP                       ((uint32_t)0x00001000)            /*!<Wake up */
-#define  USB_ISTR_ERR                        ((uint32_t)0x00002000)            /*!<Error */
-#define  USB_ISTR_PMAOVRM                    ((uint32_t)0x00004000)            /*!<Packet Memory Area Over / Underrun */
-#define  USB_ISTR_CTR                        ((uint32_t)0x00008000)            /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define  USB_FNR_FN                          ((uint32_t)0x000007FF)            /*!<Frame Number */
-#define  USB_FNR_LSOF                        ((uint32_t)0x00001800)            /*!<Lost SOF */
-#define  USB_FNR_LCK                         ((uint32_t)0x00002000)            /*!<Locked */
-#define  USB_FNR_RXDM                        ((uint32_t)0x00004000)            /*!<Receive Data - Line Status */
-#define  USB_FNR_RXDP                        ((uint32_t)0x00008000)            /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define  USB_DADDR_ADD                       ((uint32_t)0x0000007F)               /*!<ADD[6:0] bits (Device Address) */
-#define  USB_DADDR_ADD0                      ((uint32_t)0x00000001)               /*!<Bit 0 */
-#define  USB_DADDR_ADD1                      ((uint32_t)0x00000002)               /*!<Bit 1 */
-#define  USB_DADDR_ADD2                      ((uint32_t)0x00000004)               /*!<Bit 2 */
-#define  USB_DADDR_ADD3                      ((uint32_t)0x00000008)               /*!<Bit 3 */
-#define  USB_DADDR_ADD4                      ((uint32_t)0x00000010)               /*!<Bit 4 */
-#define  USB_DADDR_ADD5                      ((uint32_t)0x00000020)               /*!<Bit 5 */
-#define  USB_DADDR_ADD6                      ((uint32_t)0x00000040)               /*!<Bit 6 */
-
-#define  USB_DADDR_EF                        ((uint32_t)0x00000080)               /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define  USB_BTABLE_BTABLE                   ((uint32_t)0x0000FFF8)            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define  USB_ADDR0_TX_ADDR0_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define  USB_ADDR1_TX_ADDR1_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define  USB_ADDR2_TX_ADDR2_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define  USB_ADDR3_TX_ADDR3_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define  USB_ADDR4_TX_ADDR4_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define  USB_ADDR5_TX_ADDR5_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define  USB_ADDR6_TX_ADDR6_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define  USB_ADDR7_TX_ADDR7_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define  USB_COUNT0_TX_COUNT0_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define  USB_COUNT1_TX_COUNT1_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define  USB_COUNT2_TX_COUNT2_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define  USB_COUNT3_TX_COUNT3_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define  USB_COUNT4_TX_COUNT4_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define  USB_COUNT5_TX_COUNT5_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define  USB_COUNT6_TX_COUNT6_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define  USB_COUNT7_TX_COUNT7_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint32_t)0x0000000003FF)        /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint32_t)0x000003FF0000)        /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define  USB_ADDR0_RX_ADDR0_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define  USB_ADDR1_RX_ADDR1_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define  USB_ADDR2_RX_ADDR2_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define  USB_ADDR3_RX_ADDR3_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define  USB_ADDR4_RX_ADDR4_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define  USB_ADDR5_RX_ADDR5_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define  USB_ADDR6_RX_ADDR6_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define  USB_ADDR7_RX_ADDR7_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define  USB_COUNT0_RX_COUNT0_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT0_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define  USB_COUNT1_RX_COUNT1_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT1_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define  USB_COUNT2_RX_COUNT2_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT2_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define  USB_COUNT3_RX_COUNT3_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT3_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define  USB_COUNT4_RX_COUNT4_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT4_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define  USB_COUNT5_RX_COUNT5_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT5_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define  USB_COUNT6_RX_COUNT6_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT6_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define  USB_COUNT7_RX_COUNT7_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT7_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x0000007F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x00000001)               /*!< Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x00000002)               /*!< Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x00000004)               /*!< Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x00000008)               /*!< Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x00000010)               /*!< Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x00000020)               /*!< Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x00000040)               /*!< Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint32_t)0x00000080)               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x0000007F)            /*!< W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x00000040)            /*!< Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x00000180)            /*!< WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x00000080)            /*!< Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x00000100)            /*!< Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint32_t)0x00000200)            /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x00000001)               /*!< Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        SystemTick (SysTick)                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*****************  Bit definition for SysTick_CTRL register  *****************/
-#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
-#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
-#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
-#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
-
-/*****************  Bit definition for SysTick_LOAD register  *****************/
-#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/*****************  Bit definition for SysTick_VAL register  ******************/
-#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
-
-/*****************  Bit definition for SysTick_CALIB register  ****************/
-#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
-#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
-#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/*                                                                            */
-/*               Nested Vectored Interrupt Controller (NVIC)                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for NVIC_ISER register  *******************/
-#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
-#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICER register  *******************/
-#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
-#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ISPR register  *******************/
-#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
-#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICPR register  *******************/
-#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
-#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_IABR register  *******************/
-#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
-#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_PRI0 register  *******************/
-#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
-#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
-#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
-#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
-
-/******************  Bit definition for NVIC_PRI1 register  *******************/
-#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
-#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
-#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
-#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
-
-/******************  Bit definition for NVIC_PRI2 register  *******************/
-#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
-#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
-#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
-#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
-
-/******************  Bit definition for NVIC_PRI3 register  *******************/
-#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
-#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
-#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
-#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
-
-/******************  Bit definition for NVIC_PRI4 register  *******************/
-#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
-#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
-#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
-#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
-
-/******************  Bit definition for NVIC_PRI5 register  *******************/
-#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
-#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
-#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
-#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
-
-/******************  Bit definition for NVIC_PRI6 register  *******************/
-#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
-#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
-#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
-#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
-
-/******************  Bit definition for NVIC_PRI7 register  *******************/
-#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
-#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
-#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
-#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
-
-/******************  Bit definition for SCB_CPUID register  *******************/
-#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
-#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
-#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
-#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
-#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
-
-/*******************  Bit definition for SCB_ICSR register  *******************/
-#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
-#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
-#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
-#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
-#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
-#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
-#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
-#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
-
-/*******************  Bit definition for SCB_VTOR register  *******************/
-#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
-#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
-
-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
-#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
-#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
-#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
-
-#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
-#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
-
-/* prority group configuration */
-#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
-#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/*******************  Bit definition for SCB_SCR register  ********************/
-#define  SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)               /*!< Sleep on exit bit */
-#define  SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)               /*!< Sleep deep bit */
-#define  SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)               /*!< Wake up from WFE */
-
-/********************  Bit definition for SCB_CCR register  *******************/
-#define  SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define  SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define  SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)            /*!< Trap for unaligned access */
-#define  SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)            /*!< Trap on Divide by 0 */
-#define  SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)            /*!< Handlers running at priority -1 and -2 */
-#define  SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/*******************  Bit definition for SCB_SHPR register ********************/
-#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/******************  Bit definition for SCB_SHCSR register  *******************/
-#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
-#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
-#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
-#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
-#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
-#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
-#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
-#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
-#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
-#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
-#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
-#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
-#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
-#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
-
-/*******************  Bit definition for SCB_CFSR register  *******************/
-/*!< MFSR */
-#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
-#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
-#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
-#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
-#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
-#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
-#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
-#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
-#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
-#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
-#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
-#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
-#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
-#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/*******************  Bit definition for SCB_HFSR register  *******************/
-#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
-#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
-
-/*******************  Bit definition for SCB_DFSR register  *******************/
-#define  SCB_DFSR_HALTED                     ((uint32_t)0x00000001)               /*!< Halt request flag */
-#define  SCB_DFSR_BKPT                       ((uint32_t)0x00000002)               /*!< BKPT flag */
-#define  SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)               /*!< Data Watchpoint and Trace (DWT) flag */
-#define  SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)               /*!< Vector catch flag */
-#define  SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)               /*!< External debug request flag */
-
-/*******************  Bit definition for SCB_MMFAR register  ******************/
-#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
-
-/*******************  Bit definition for SCB_BFAR register  *******************/
-#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
-
-/*******************  Bit definition for SCB_afsr register  *******************/
-#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-                                         
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xC_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,247 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *            - Configuration section that allows to select:
-  *              - The STM32L1xx device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx
-  * @{
-  */
-    
-#ifndef __STM32L1XX_H
-#define __STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/* Uncomment the line below according to the target STM32L device used in your 
-   application 
-  */
-
-#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \
-    !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \
-    !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \
-    !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE)
-  /* #define STM32L100xB  */   /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */
-  /* #define STM32L100xBA */   /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */
-  /* #define STM32L100xC  */   /*!< STM32L100RC Devices */
-  /* #define STM32L151xB  */   /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
-  /* #define STM32L151xBA */   /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ 
-  /* #define STM32L151xC  */   /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
-  /* #define STM32L151xCA */   /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
-  /* #define STM32L151xD  */   /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
-  /* #define STM32L151xE  */   /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
-  /* #define STM32L152xB  */   /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
-  /* #define STM32L152xBA */   /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
-#define STM32L152xC    /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
-  /* #define STM32L152xCA */   /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
-  /* #define STM32L152xD  */   /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */  
-  /* #define STM32L152xE  */   /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
-  /* #define STM32L162xC  */   /*!< STM32L162RC and STM32L162VC */
-  /* #define STM32L162xCA */   /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
-  /* #define STM32L162xD  */   /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
-  /* #define STM32L162xE  */   /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-  
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V2.0.0
-  */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32L1xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32L100xB)
-  #include "stm32l100xb.h"
-#elif defined(STM32L100xBA)
-  #include "stm32l100xba.h"
-#elif defined(STM32L100xC)
-  #include "stm32l100xc.h"
-#elif defined(STM32L151xB)
-  #include "stm32l151xb.h"
-#elif defined(STM32L151xBA)
-  #include "stm32l151xba.h"
-#elif defined(STM32L151xC)
-  #include "stm32l151xc.h"
-#elif defined(STM32L151xCA)
-  #include "stm32l151xca.h"
-#elif defined(STM32L151xD)
-  #include "stm32l151xd.h"
-#elif defined(STM32L151xE)
-  #include "stm32l151xe.h"
-#elif defined(STM32L152xB)
-  #include "stm32l152xb.h"
-#elif defined(STM32L152xBA)
-  #include "stm32l152xba.h"
-#elif defined(STM32L152xC)
-  #include "stm32l152xc.h"
-#elif defined(STM32L152xCA)
-  #include "stm32l152xca.h"
-#elif defined(STM32L152xD)
-  #include "stm32l152xd.h"
-#elif defined(STM32L152xE)
-  #include "stm32l152xe.h"
-#elif defined(STM32L162xC)
-  #include "stm32l162xc.h"
-#elif defined(STM32L162xCA)
-  #include "stm32l162xca.h"
-#elif defined(STM32L162xD)
-  #include "stm32l162xd.h"
-#elif defined(STM32L162xE)
-  #include "stm32l162xe.h"
-#else
- #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l1xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L1xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/stm32l1xx_hal_conf.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,291 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   HAL configuration template file. 
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l1xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CONF_H
-#define __STM32L1xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_COMP_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_LCD_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_OPAMP_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)500)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-   
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-   
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */          
-#define  TICK_INT_PRIORITY            ((uint32_t)0x000F)    /*!< tick interrupt priority */            
-#define  USE_RTOS                     0     
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     0
-#define  DATA_CACHE_ENABLE            0
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/*#define USE_FULL_ASSERT    1*/ 
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32l1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-  
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32l1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32l1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32l1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l1xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32l1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32l1xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32l1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32l1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32l1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32l1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */ 
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32l1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l1xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-   
-#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32l1xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */     
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */   
-   
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,607 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.c
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l1xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l1xx.h"
-#include "hal_tick.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM32L152D_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-  
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
-const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t)0x88FFC00C;
-  
-  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xEEFEFFFE;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-    
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-  /* Configure the Cube driver */
-  SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
-  HAL_Init();
-
-  /* Configure the System clock source, PLL Multiplier and Divider factors,
-     AHB/APBx prescalers and Flash settings */
-  SetSysClock();
-  
-  /* Reset the timer to avoid issues after the RAM initialization */
-  TIM_MST_RESET_ON;
-  TIM_MST_RESET_OFF;
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in SystemInit() function before jump to main.
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- +                       SRAM pins assignment                                   +
- +-------------------+--------------------+------------------+------------------+
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD15 <-> FSMC_D1  |--------------------+ 
- +-------------------+
-*/
-
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHBENR   = 0x000080D8;
-  
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A0A;
-  /* Configure PDx pins speed to 40 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 40 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC00F;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 40 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x00000C00;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 40 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*-- FSMC Configuration ------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHBENR    = 0x400080D8;
-
-  /* Configure and enable Bank1_SRAM3 */
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-/*
-  Bank1_SRAM3 is configured as follow:
-
-  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 3;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
-
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-*/
-  
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  if (__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL)
-    return 1;   // already on HSE PLL, could occur from deepsleep waking
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
-  // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
-  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
-  while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/system_stm32l1xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L1XX_H
-#define __SYSTEM_STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L1xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L1xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L1XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/startup_stm32l152xe.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,325 +0,0 @@
-; STM32L152RE Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-                
-Stack_Mem       SPACE   Stack_Size
-__initial_sp    EQU     0x20014000 ; Top of RAM (80 KB)
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000400
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit    EQU (__initial_sp - Stack_Size)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/stm32l152re.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L152RE: 512KB FLASH + 80KB SRAM
-LR_IROM1 0x08000000 0x80000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x80000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x124) (0x14000-0x124)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_MICRO/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/startup_stm32l152xe.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,298 +0,0 @@
-; STM32L152RE Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-__initial_sp    EQU     0x20014000 ; Top of RAM (80 KB)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     UART4_IRQHandler          ; UART4
-                DCD     UART5_IRQHandler          ; UART5
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     0                         ; Reserved
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]                                
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  UART4_IRQHandler           [WEAK]
-                EXPORT  UART5_IRQHandler           [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-UART4_IRQHandler
-UART5_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/stm32l152re.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2014, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L152RE: 512KB FLASH + 80KB SRAM
-LR_IROM1 0x08000000 0x80000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x80000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x124) (0x14000-0x124)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_ARM_STD/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/STM32L152XE.ld	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,156 +0,0 @@
-/* Linker script to configure memory regions. */
-MEMORY
-{
-  /* 512KB FLASH, 80KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
-   * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
-   */
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 512k
-  RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x14000-0x13C
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_GCC_ARM/startup_stm32l152xe.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,434 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l152xe.s
-  * @author    MCD Application Team
-  * @version   V2.0.0
-  * @date      5-September-2014
-  * @brief     STM32L152XE Devices vector table for 
-  *            Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-  ldr   r0, =_estack
-  mov   sp, r0          /* set stack pointer */
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
-
-LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
-  bcc CopyDataInit
-  ldr r2, =_sbss
-  b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs r3, #0
-  str r3, [r2], #4
-
-LoopFillZerobss:
-  ldr r3, = _ebss
-  cmp r2, r3
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-  //bl __libc_init_array
-/* Call the application's entry point.*/
-  //bl  main
-  bl _start
-
-LoopForever:
-  b LoopForever
-
-
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word LCD_IRQHandler  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word UART4_IRQHandler
-  .word UART5_IRQHandler
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L152XE devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak LCD_IRQHandler
-  .thumb_set LCD_IRQHandler,Default_Handler  
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak UART4_IRQHandler
-  .thumb_set UART4_IRQHandler,Default_Handler
-
-  .weak UART5_IRQHandler
-  .thumb_set UART5_IRQHandler,Default_Handler
-  
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/startup_stm32l152xe.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,546 +0,0 @@
-;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
-;* File Name          : startup_stm32l152xe.s
-;* Author             : MCD Application Team
-;* Version            : V2.0.0
-;* Date               : 5-September-2014
-;* Description        : STM32L152XE Devices vector for EWARM toolchain.
-;*                      This module performs:
-;*                      - Set the initial SP
-;*                      - Set the initial PC == __iar_program_start,
-;*                      - Set the vector table entries with the exceptions ISR 
-;*                        address.
-;*                      - Configure the system clock
-;*                      - Branches to main in the C library (which eventually
-;*                        calls main()).
-;*                      After Reset the Cortex-M3 processor is in Thread mode,
-;*                      priority is Privileged, and the Stack is set to Main.
-;********************************************************************************
-;*
-;* <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-;*
-;* Redistribution and use in source and binary forms, with or without modification,
-;* are permitted provided that the following conditions are met:
-;*   1. Redistributions of source code must retain the above copyright notice,
-;*      this list of conditions and the following disclaimer.
-;*   2. Redistributions in binary form must reproduce the above copyright notice,
-;*      this list of conditions and the following disclaimer in the documentation
-;*      and/or other materials provided with the distribution.
-;*   3. Neither the name of STMicroelectronics nor the names of its contributors
-;*      may be used to endorse or promote products derived from this software
-;*      without specific prior written permission.
-;*
-;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;*
-;*******************************************************************************
-;
-;
-; The modules in this file are included in the libraries, and may be replaced
-; by any user-defined modules that define the PUBLIC symbol _program_start or
-; a user defined start symbol.
-; To override the cstartup defined in the library, simply add your modified
-; version to the workbench project.
-;
-; The vector table is normally located at address 0.
-; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
-; The name "__vector_table" has special meaning for C-SPY:
-; it is where the SP start value is found, and the NVIC vector
-; table register (VTOR) is initialized to this address if != 0.
-;
-; Cortex-M version
-;
-
-        MODULE  ?cstartup
-
-        ;; Forward declaration of sections.
-        SECTION CSTACK:DATA:NOROOT(3)
-
-        SECTION .intvec:CODE:NOROOT(2)
-
-        EXTERN  __iar_program_start
-        EXTERN  SystemInit        
-        PUBLIC  __vector_table
-
-        DATA
-__vector_table
-        DCD     sfe(CSTACK)
-        DCD     Reset_Handler             ; Reset Handler
-
-        DCD     NMI_Handler               ; NMI Handler
-        DCD     HardFault_Handler         ; Hard Fault Handler
-        DCD     MemManage_Handler         ; MPU Fault Handler
-        DCD     BusFault_Handler          ; Bus Fault Handler
-        DCD     UsageFault_Handler        ; Usage Fault Handler
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     0                         ; Reserved
-        DCD     SVC_Handler               ; SVCall Handler
-        DCD     DebugMon_Handler          ; Debug Monitor Handler
-        DCD     0                         ; Reserved
-        DCD     PendSV_Handler            ; PendSV Handler
-        DCD     SysTick_Handler           ; SysTick Handler
-
-         ; External Interrupts
-        DCD     WWDG_IRQHandler           ; Window Watchdog
-        DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-        DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-        DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-        DCD     FLASH_IRQHandler          ; FLASH
-        DCD     RCC_IRQHandler            ; RCC
-        DCD     EXTI0_IRQHandler          ; EXTI Line 0
-        DCD     EXTI1_IRQHandler          ; EXTI Line 1
-        DCD     EXTI2_IRQHandler          ; EXTI Line 2
-        DCD     EXTI3_IRQHandler          ; EXTI Line 3
-        DCD     EXTI4_IRQHandler          ; EXTI Line 4
-        DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-        DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-        DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-        DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-        DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-        DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-        DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-        DCD     ADC1_IRQHandler           ; ADC1
-        DCD     USB_HP_IRQHandler         ; USB High Priority
-        DCD     USB_LP_IRQHandler         ; USB Low  Priority
-        DCD     DAC_IRQHandler            ; DAC
-        DCD     COMP_IRQHandler           ; COMP through EXTI Line
-        DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-        DCD     LCD_IRQHandler            ; LCD
-        DCD     TIM9_IRQHandler           ; TIM9
-        DCD     TIM10_IRQHandler          ; TIM10
-        DCD     TIM11_IRQHandler          ; TIM11
-        DCD     TIM2_IRQHandler           ; TIM2
-        DCD     TIM3_IRQHandler           ; TIM3
-        DCD     TIM4_IRQHandler           ; TIM4
-        DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-        DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-        DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-        DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-        DCD     SPI1_IRQHandler           ; SPI1
-        DCD     SPI2_IRQHandler           ; SPI2
-        DCD     USART1_IRQHandler         ; USART1
-        DCD     USART2_IRQHandler         ; USART2
-        DCD     USART3_IRQHandler         ; USART3
-        DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-        DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-        DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-        DCD     TIM6_IRQHandler           ; TIM6
-        DCD     TIM7_IRQHandler           ; TIM7
-        DCD     0                         ; Reserved
-        DCD     TIM5_IRQHandler           ; TIM5                
-        DCD     SPI3_IRQHandler           ; SPI3
-        DCD     UART4_IRQHandler          ; UART4
-        DCD     UART5_IRQHandler          ; UART5
-        DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-        DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-        DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-        DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-        DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-        DCD     0                         ; Reserved
-        DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition 
-        
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-;;
-;; Default interrupt handlers.
-;;
-        THUMB
-
-        PUBWEAK Reset_Handler
-        SECTION .text:CODE:REORDER:NOROOT(2)
-Reset_Handler
-        LDR     R0, =SystemInit
-        BLX     R0
-        LDR     R0, =__iar_program_start
-        BX      R0
-        
-        PUBWEAK NMI_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-NMI_Handler
-        B NMI_Handler
-        
-        
-        PUBWEAK HardFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-HardFault_Handler
-        B HardFault_Handler
-        
-        
-        PUBWEAK MemManage_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-MemManage_Handler
-        B MemManage_Handler
-        
-                
-        PUBWEAK BusFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-BusFault_Handler
-        B BusFault_Handler
-        
-        
-        PUBWEAK UsageFault_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UsageFault_Handler
-        B UsageFault_Handler
-        
-        
-        PUBWEAK SVC_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SVC_Handler
-        B SVC_Handler
-        
-        
-        PUBWEAK DebugMon_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DebugMon_Handler
-        B DebugMon_Handler
-        
-        
-        PUBWEAK PendSV_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PendSV_Handler
-        B PendSV_Handler
-        
-        
-        PUBWEAK SysTick_Handler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SysTick_Handler
-        B SysTick_Handler
-        
-        
-        PUBWEAK WWDG_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-WWDG_IRQHandler
-        B WWDG_IRQHandler
-        
-        
-        PUBWEAK PVD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-PVD_IRQHandler
-        B PVD_IRQHandler
-        
-        
-        PUBWEAK TAMPER_STAMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TAMPER_STAMP_IRQHandler
-        B TAMPER_STAMP_IRQHandler
-        
-        
-        PUBWEAK RTC_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_WKUP_IRQHandler
-        B RTC_WKUP_IRQHandler
-        
-        
-        PUBWEAK FLASH_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-FLASH_IRQHandler
-        B FLASH_IRQHandler
-        
-        
-        PUBWEAK RCC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RCC_IRQHandler
-        B RCC_IRQHandler
-        
-        
-        PUBWEAK EXTI0_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI0_IRQHandler
-        B EXTI0_IRQHandler
-        
-        
-        PUBWEAK EXTI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI1_IRQHandler
-        B EXTI1_IRQHandler
-        
-        
-        PUBWEAK EXTI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI2_IRQHandler
-        B EXTI2_IRQHandler
-        
-        
-        PUBWEAK EXTI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI3_IRQHandler
-        B EXTI3_IRQHandler
-        
-        
-        PUBWEAK EXTI4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI4_IRQHandler
-        B EXTI4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel1_IRQHandler
-        B DMA1_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel2_IRQHandler
-        B DMA1_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel3_IRQHandler
-        B DMA1_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel4_IRQHandler
-        B DMA1_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel5_IRQHandler
-        B DMA1_Channel5_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel6_IRQHandler
-        B DMA1_Channel6_IRQHandler
-        
-        
-        PUBWEAK DMA1_Channel7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA1_Channel7_IRQHandler
-        B DMA1_Channel7_IRQHandler
-        
-        
-        PUBWEAK ADC1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-ADC1_IRQHandler
-        B ADC1_IRQHandler
-        
-        
-        PUBWEAK USB_HP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_HP_IRQHandler
-        B USB_HP_IRQHandler
-        
-        
-        PUBWEAK USB_LP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_LP_IRQHandler
-        B USB_LP_IRQHandler
-        
-        
-        PUBWEAK DAC_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DAC_IRQHandler
-        B DAC_IRQHandler
-        
-        
-        PUBWEAK COMP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_IRQHandler
-        B COMP_IRQHandler
-        
-        
-        PUBWEAK EXTI9_5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI9_5_IRQHandler
-        B EXTI9_5_IRQHandler
-        
-        
-        PUBWEAK LCD_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-LCD_IRQHandler
-        B LCD_IRQHandler
-        
-        
-        PUBWEAK TIM9_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM9_IRQHandler
-        B TIM9_IRQHandler
-        
-        
-        PUBWEAK TIM10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM10_IRQHandler
-        B TIM10_IRQHandler
-        
-        
-        PUBWEAK TIM11_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM11_IRQHandler
-        B TIM11_IRQHandler
-        
-        
-        PUBWEAK TIM2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM2_IRQHandler
-        B TIM2_IRQHandler
-        
-        
-        PUBWEAK TIM3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM3_IRQHandler
-        B TIM3_IRQHandler
-        
-        
-        PUBWEAK TIM4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM4_IRQHandler
-        B TIM4_IRQHandler
-        
-        
-        PUBWEAK I2C1_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_EV_IRQHandler
-        B I2C1_EV_IRQHandler
-        
-        
-        PUBWEAK I2C1_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C1_ER_IRQHandler
-        B I2C1_ER_IRQHandler
-        
-        
-        PUBWEAK I2C2_EV_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_EV_IRQHandler
-        B I2C2_EV_IRQHandler
-        
-        
-        PUBWEAK I2C2_ER_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-I2C2_ER_IRQHandler
-        B I2C2_ER_IRQHandler
-        
-        
-        PUBWEAK SPI1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI1_IRQHandler
-        B SPI1_IRQHandler
-        
-        
-        PUBWEAK SPI2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI2_IRQHandler
-        B SPI2_IRQHandler
-        
-        
-        PUBWEAK USART1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART1_IRQHandler
-        B USART1_IRQHandler
-        
-        
-        PUBWEAK USART2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART2_IRQHandler
-        B USART2_IRQHandler
-        
-        
-        PUBWEAK USART3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USART3_IRQHandler
-        B USART3_IRQHandler
-        
-        
-        PUBWEAK EXTI15_10_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-EXTI15_10_IRQHandler
-        B EXTI15_10_IRQHandler
-        
-        
-        PUBWEAK RTC_Alarm_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-RTC_Alarm_IRQHandler
-        B RTC_Alarm_IRQHandler
-        
-        
-        PUBWEAK USB_FS_WKUP_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-USB_FS_WKUP_IRQHandler
-        B USB_FS_WKUP_IRQHandler
-        
-
-        PUBWEAK TIM6_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM6_IRQHandler
-        B TIM6_IRQHandler
-        
-
-        PUBWEAK TIM7_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM7_IRQHandler
-        B TIM7_IRQHandler
-
-        PUBWEAK TIM5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-TIM5_IRQHandler
-        B TIM5_IRQHandler
-
-        PUBWEAK SPI3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-SPI3_IRQHandler
-        B SPI3_IRQHandler
-        
-        
-        PUBWEAK UART4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART4_IRQHandler
-        B UART4_IRQHandler
-        
-        
-        PUBWEAK UART5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-UART5_IRQHandler
-        B UART5_IRQHandler
-
-        PUBWEAK DMA2_Channel1_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel1_IRQHandler
-        B DMA2_Channel1_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel2_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel2_IRQHandler
-        B DMA2_Channel2_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel3_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel3_IRQHandler
-        B DMA2_Channel3_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel4_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel4_IRQHandler
-        B DMA2_Channel4_IRQHandler
-        
-        
-        PUBWEAK DMA2_Channel5_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-DMA2_Channel5_IRQHandler
-        B DMA2_Channel5_IRQHandler
-
-
-        PUBWEAK COMP_ACQ_IRQHandler
-        SECTION .text:CODE:REORDER:NOROOT(1)
-COMP_ACQ_IRQHandler
-        B COMP_ACQ_IRQHandler                
-                
-        END
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/TOOLCHAIN_IAR/stm32l152xe.icf	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,31 +0,0 @@
-/* [ROM = 64kb = 0x10000] */
-define symbol __intvec_start__     = 0x08000000;
-define symbol __region_ROM_start__ = 0x08000000;
-define symbol __region_ROM_end__   = 0x0807FFFF;
-
-/* [RAM = 80kb = 0x14000] Vector table dynamic copy: 73 vectors = 292 bytes (0x124) to be reserved in RAM */
-define symbol __NVIC_start__          = 0x20000000;
-define symbol __NVIC_end__            = 0x20000127; /* Add 4 more bytes to be aligned on 8 bytes */
-define symbol __region_RAM_start__    = 0x20000128;
-define symbol __region_RAM_end__      = 0x20013FFF;
-
-/* Memory regions */
-define memory mem with size = 4G;
-define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
-define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
-
-/* Stack and Heap */
-/*Heap 1/4 of ram and stack 1/8*/
-define symbol __size_cstack__ = 0x2800;
-define symbol __size_heap__   = 0x5000;
-define block CSTACK    with alignment = 8, size = __size_cstack__   { };
-define block HEAP      with alignment = 8, size = __size_heap__     { };
-define block STACKHEAP with fixed order { block HEAP, block CSTACK };
-
-initialize by copy with packing = zeros { readwrite };
-do not initialize  { section .noinit };
-
-place at address mem:__intvec_start__ { readonly section .intvec };
-
-place in ROM_region   { readonly };
-place in RAM_region   { readwrite, block STACKHEAP };

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/cmsis.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32l1xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/cmsis_nvic.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    uint32_t *vectors = (uint32_t *)SCB->VTOR;
-    uint32_t i;
-
-    // Copy and switch to dynamic vectors if the first time called
-    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = vectors;
-        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
-    }
-    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/cmsis_nvic.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// STM32L152RE
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123
-// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM
-#define NVIC_NUM_VECTORS      73
-#define NVIC_USER_IRQ_OFFSET  16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/hal_tick.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.c
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-#include "hal_tick.h"
-
-TIM_HandleTypeDef TimMasterHandle;
-uint32_t PreviousVal = 0;
-
-void us_ticker_irq_handler(void);
-
-void timer_irq_handler(void) {
-    // Channel 1 for mbed timeout
-    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
-        us_ticker_irq_handler();
-    }
-
-    // Channel 2 for HAL tick
-    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
-        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
-        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
-        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
-            // Increment HAL variable
-            HAL_IncTick();
-            // Prepare next interrupt
-            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
-            PreviousVal = val;
-#if 0 // For DEBUG only
-            HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
-#endif
-        }
-    }
-}
-
-// Reconfigure the HAL tick using a standard timer instead of systick.
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
-    // Enable timer clock
-    TIM_MST_RCC;
-
-    // Reset timer
-    TIM_MST_RESET_ON;
-    TIM_MST_RESET_OFF;
-
-    // Update the SystemCoreClock variable
-    SystemCoreClockUpdate();
-
-    // Configure time base
-    TimMasterHandle.Instance = TIM_MST;
-    TimMasterHandle.Init.Period            = 0xFFFFFFFF;
-    TimMasterHandle.Init.Prescaler         = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
-    TimMasterHandle.Init.ClockDivision     = 0;
-    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
-    HAL_TIM_OC_Init(&TimMasterHandle);
-
-    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
-    NVIC_EnableIRQ(TIM_MST_IRQ);
-
-    // Channel 1 for mbed timeout
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
-
-    // Channel 2 for HAL tick
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
-    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
-    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
-
-#if 0 // For DEBUG only
-    __GPIOB_CLK_ENABLE();
-    GPIO_InitTypeDef GPIO_InitStruct;
-    GPIO_InitStruct.Pin = GPIO_PIN_6;
-    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-    GPIO_InitStruct.Pull = GPIO_PULLUP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-#endif
-
-    return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/hal_tick.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.h
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32l1xx.h"
-#include "cmsis_nvic.h"
-   
-#define TIM_MST      TIM5
-#define TIM_MST_IRQ  TIM5_IRQn
-#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l152xe.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,6016 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l152xe.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l152xe
-  * @{
-  */
-    
-#ifndef __STM32L152xE_H
-#define __STM32L152xE_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200 /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  LCD_IRQn                    = 24,     /*!< LCD Interrupt                                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  UART4_IRQn                  = 48,     /*!< UART4 global Interrupt                                  */
-  UART5_IRQn                  = 49,     /*!< UART5 global Interrupt                                  */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  __IO uint32_t SMPR0;        /*!< ADC sample time register 0,                  Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< COMP comparator control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-  __IO uint32_t WRPR3;        /*!< Write protection register 3,                 Address offset: 0x84 */
-  __IO uint32_t WRPR4;        /*!< Write protection register 4,                 Address offset: 0x88 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-  __IO uint32_t WRP89;            /*!< write protection register 8 9,          Address offset: 0x18 */
-  __IO uint32_t WRP1011;          /*!< write protection register 10 11,        Address offset: 0x1C */
-  uint32_t   RESERVED[24];        /*!< Reserved,                                    0x20 -> 0x7C    */
-  __IO uint32_t WRP1213;          /*!< write protection register 12 13,        Address offset: 0x80 */
-  __IO uint32_t WRP1415;          /*!< write protection register 14 15,        Address offset: 0x84 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control/status register,                     Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief LCD
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;        /*!< LCD control register,                           Address offset: 0x00 */
-  __IO uint32_t FCR;       /*!< LCD frame control register,                     Address offset: 0x04 */
-  __IO uint32_t SR;        /*!< LCD status register,                            Address offset: 0x08 */
-  __IO uint32_t CLR;       /*!< LCD clear register,                             Address offset: 0x0C */
-  uint32_t RESERVED;       /*!< Reserved,                                       Address offset: 0x10 */
-  __IO uint32_t RAM[16];   /*!< LCD display memory,                             Address offset: 0x14-0x50 */
-} LCD_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
-  __IO uint32_t HYSCR4;     /*!< RI Hysteresis control register,               Address offset: 0x18 */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
-  __IO uint32_t ASMR4;      /*!< RI Analog switch mode register 4,         Address offset: 0x40 */
-  __IO uint32_t CMR4;       /*!< RI Channel mask register 4,                   Address offset: 0x44 */
-  __IO uint32_t CICR4;      /*!< RI Channel Iden for capture register 4,  Address offset: 0x48 */
-  __IO uint32_t ASMR5;      /*!< RI Analog switch mode register 5,         Address offset: 0x4C */
-  __IO uint32_t CMR5;       /*!< RI Channel mask register 5,                   Address offset: 0x50 */
-  __IO uint32_t CICR5;      /*!< RI Channel Iden for capture register 5,  Address offset: 0x54 */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     ((uint32_t)(FLASH_BASE + 0x80000))  /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          ((uint32_t)0x22000000)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_BANK2_BASE      ((uint32_t)0x08040000)              /*!< FLASH BANK2 base address in the alias region */
-#define FLASH_BANK1_END       ((uint32_t)0x0803FFFF)              /*!< Program end FLASH BANK1 address  */
-#define FLASH_BANK2_END       ((uint32_t)0x0807FFFF)              /*!< Program end FLASH BANK2 address  */
-#define FLASH_EEPROM_END      ((uint32_t)0x08083FFF)              /*!< FLASH EEPROM end address (16KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400)
-#define LCD_BASE              (APB1PERIPH_BASE + 0x00002400)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800)
-#define UART4_BASE            (APB1PERIPH_BASE + 0x00004C00)
-#define UART5_BASE            (APB1PERIPH_BASE + 0x00005000)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5C)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400)
-#define GPIOF_BASE            (AHBPERIPH_BASE + 0x00001800)
-#define GPIOG_BASE            (AHBPERIPH_BASE + 0x00001C00)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FF80000)    /*!< FLASH Option Bytes base address */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001C)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058)
-#define DBGMCU_BASE           ((uint32_t)0xE0042000)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define LCD                 ((LCD_TypeDef *) LCD_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define UART4               ((USART_TypeDef *) UART4_BASE)
-#define UART5               ((USART_TypeDef *) UART5_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define COMP                ((COMP_TypeDef *) COMP_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
-#define RI                  ((RI_TypeDef *) RI_BASE)
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
-#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!< Overrun flag */
-#define  ADC_SR_ADONS                        ((uint32_t)0x00000040)        /*!< ADC ON status */
-#define  ADC_SR_RCNR                         ((uint32_t)0x00000100)        /*!< Regular channel not ready flag */
-#define  ADC_SR_JCNR                         ((uint32_t)0x00000200)        /*!< Injected channel not ready flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
-
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
-
-#define  ADC_CR1_PDD                         ((uint32_t)0x00010000)        /*!< Power Down during Delay phase */
-#define  ADC_CR1_PDI                         ((uint32_t)0x00020000)        /*!< Power Down during Idle phase */
-
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
-
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!< RES[1:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
-
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)        /*!< Overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
-#define  ADC_CR2_CFG                         ((uint32_t)0x00000004)        /*!< ADC Configuration */
-
-#define  ADC_CR2_DELS                        ((uint32_t)0x00000070)        /*!< DELS[2:0] bits (Delay selection) */
-#define  ADC_CR2_DELS_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  ADC_CR2_DELS_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  ADC_CR2_DELS_2                      ((uint32_t)0x00000040)        /*!< Bit 2 */
-
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!< DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!< End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
-
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!< Start Conversion of injected channels */
-
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!< Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP20                     ((uint32_t)0x00000007)        /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
-#define  ADC_SMPR1_SMP20_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP20_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP20_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP21                     ((uint32_t)0x00000038)        /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
-#define  ADC_SMPR1_SMP21_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP21_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP21_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP22                     ((uint32_t)0x000001C0)        /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
-#define  ADC_SMPR1_SMP22_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP22_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP22_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP23                     ((uint32_t)0x00000E00)        /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
-#define  ADC_SMPR1_SMP23_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP23_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP23_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP24                     ((uint32_t)0x00007000)        /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
-#define  ADC_SMPR1_SMP24_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP24_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP24_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP25                     ((uint32_t)0x00038000)        /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
-#define  ADC_SMPR1_SMP25_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP25_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP25_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP26                     ((uint32_t)0x001C0000)        /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
-#define  ADC_SMPR1_SMP26_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP26_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP26_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP27                     ((uint32_t)0x00E00000)        /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
-#define  ADC_SMPR1_SMP27_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP27_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP27_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP28                     ((uint32_t)0x07000000)        /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
-#define  ADC_SMPR1_SMP28_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP28_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP28_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP29                     ((uint32_t)0x38000000)        /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
-#define  ADC_SMPR1_SMP29_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP29_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP29_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR2_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR2_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR2_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR2_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR2_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR2_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR2_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP18                     ((uint32_t)0x07000000)        /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR2_SMP18_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP18_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP18_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP19                     ((uint32_t)0x38000000)        /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
-#define  ADC_SMPR2_SMP19_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP19_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP19_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define  ADC_SMPR3_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR3_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
- 
-#define  ADC_SMPR3_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR3_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR3_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR3_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR3_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR3_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR3_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR3_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR3_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR3_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)         /*!< Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_L                          ((uint32_t)0x01F00000)        /*!< L[4:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR1_L_4                        ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ28                       ((uint32_t)0x000F8000)        /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
-#define  ADC_SQR1_SQ28_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ28_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ28_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ28_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ28_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ27                       ((uint32_t)0x00007C00)        /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
-#define  ADC_SQR1_SQ27_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ27_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ27_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ27_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ27_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ26                       ((uint32_t)0x000003E0)        /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
-#define  ADC_SQR1_SQ26_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ26_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ26_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ26_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ26_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ25                       ((uint32_t)0x0000001F)        /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
-#define  ADC_SQR1_SQ25_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ25_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ25_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ25_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ25_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ19                       ((uint32_t)0x0000001F)        /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
-#define  ADC_SQR2_SQ19_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ19_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ19_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ19_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ19_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ20                       ((uint32_t)0x000003E0)        /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
-#define  ADC_SQR2_SQ20_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ20_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ20_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ20_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ20_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ21                       ((uint32_t)0x00007C00)        /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
-#define  ADC_SQR2_SQ21_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ21_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ21_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ21_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ21_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ22                       ((uint32_t)0x000F8000)        /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
-#define  ADC_SQR2_SQ22_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ22_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ22_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ22_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ22_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ23                       ((uint32_t)0x01F00000)        /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
-#define  ADC_SQR2_SQ23_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ23_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ23_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ23_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ23_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ24                       ((uint32_t)0x3E000000)        /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
-#define  ADC_SQR2_SQ24_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ24_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ24_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ24_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ24_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR3_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR3_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR3_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR3_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ17                       ((uint32_t)0x01F00000)        /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
-#define  ADC_SQR3_SQ17_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ17_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ17_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ17_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ17_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ18                       ((uint32_t)0x3E000000)        /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
-#define  ADC_SQR3_SQ18_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ18_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ18_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ18_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ18_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define  ADC_SQR4_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR4_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR4_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR4_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ10                        ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR4_SQ10_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ10_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ10_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ10_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ10_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ11                        ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR4_SQ11_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ11_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ11_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ11_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ11_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ12                        ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR4_SQ12_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ12_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ12_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ12_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ12_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define  ADC_SQR5_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR5_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR5_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR5_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR5_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR5_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR5_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-
-/******************  Bit definition for ADC_SMPR0 register  *******************/
-#define  ADC_SMPR0_SMP30                     ((uint32_t)0x00000007)        /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
-#define  ADC_SMPR0_SMP30_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR0_SMP30_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR0_SMP30_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
- 
-#define  ADC_SMPR0_SMP31                     ((uint32_t)0x00000038)        /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
-#define  ADC_SMPR0_SMP31_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR0_SMP31_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR0_SMP31_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!< ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!< ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!< ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!< ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!< ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020)        /*!< ADC1 overrun  flag */
-#define  ADC_CSR_ADONS1                      ((uint32_t)0x00000040)        /*!< ADON status of ADC1 */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!< ADC prescaler*/
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */ 
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define  COMP_CSR_10KPU                      ((uint32_t)0x00000001)        /*!< 10K pull-up resistor */
-#define  COMP_CSR_400KPU                     ((uint32_t)0x00000002)        /*!< 400K pull-up resistor */
-#define  COMP_CSR_10KPD                      ((uint32_t)0x00000004)        /*!< 10K pull-down resistor */
-#define  COMP_CSR_400KPD                     ((uint32_t)0x00000008)        /*!< 400K pull-down resistor */
-#define  COMP_CSR_CMP1EN                     ((uint32_t)0x00000010)        /*!< Comparator 1 enable */
-#define  COMP_CSR_SW1                        ((uint32_t)0x00000020)        /*!< SW1 analog switch enable */
-#define  COMP_CSR_CMP1OUT                    ((uint32_t)0x00000080)        /*!< Comparator 1 output */
-
-#define  COMP_CSR_SPEED                      ((uint32_t)0x00001000)        /*!< Comparator 2 speed */
-#define  COMP_CSR_CMP2OUT                    ((uint32_t)0x00002000)        /*!< Comparator 2 ouput */
-#define  COMP_CSR_VREFOUTEN                  ((uint32_t)0x00010000)        /*!< Comparator Vref Enable */
-#define  COMP_CSR_WNDWE                      ((uint32_t)0x00020000)        /*!< Window mode enable */
-#define  COMP_CSR_INSEL                      ((uint32_t)0x001C0000)        /*!< INSEL[2:0] Inversion input Selection */
-#define  COMP_CSR_INSEL_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  COMP_CSR_INSEL_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  COMP_CSR_INSEL_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  COMP_CSR_OUTSEL                     ((uint32_t)0x00E00000)        /*!< OUTSEL[2:0] comparator 2 output redirection */
-#define  COMP_CSR_OUTSEL_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  COMP_CSR_OUTSEL_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  COMP_CSR_OUTSEL_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  COMP_CSR_FCH3                       ((uint32_t)0x04000000)        /*!< Bit 26 */
-#define  COMP_CSR_FCH8                       ((uint32_t)0x08000000)        /*!< Bit 27 */
-#define  COMP_CSR_RCH13                      ((uint32_t)0x10000000)        /*!< Bit 28 */
-
-#define  COMP_CSR_CAIE                       ((uint32_t)0x20000000)        /*!< Bit 29 */
-#define  COMP_CSR_CAIF                       ((uint32_t)0x40000000)        /*!< Bit 30 */
-#define  COMP_CSR_TSUSP                      ((uint32_t)0x80000000)        /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD                     ((uint32_t)0x00000001)        /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1                     ((uint32_t)0x00000002)        /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1                     ((uint32_t)0x00000004)        /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1                     ((uint32_t)0x00000008)        /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1                     ((uint32_t)0x00000010)        /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L                  ((uint32_t)0x00000020)        /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H                  ((uint32_t)0x00000040)        /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM                    ((uint32_t)0x00000080)        /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD                     ((uint32_t)0x00000100)        /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2                     ((uint32_t)0x00000200)        /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2                     ((uint32_t)0x00000400)        /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2                     ((uint32_t)0x00000800)        /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2                     ((uint32_t)0x00001000)        /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L                  ((uint32_t)0x00002000)        /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H                  ((uint32_t)0x00004000)        /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM                    ((uint32_t)0x00008000)        /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1                   ((uint32_t)0x01000000)        /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2                   ((uint32_t)0x02000000)        /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2                     ((uint32_t)0x08000000)        /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE                  ((uint32_t)0x10000000)        /*!< Power range selection */
-#define OPAMP_CSR_OPA1CALOUT                 ((uint32_t)0x20000000)        /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT                 ((uint32_t)0x40000000)        /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW    ((uint32_t)0x0000001F)        /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH   ((uint32_t)0x000003E0)        /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW    ((uint32_t)0x00007C00)        /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH   ((uint32_t)0x000F8000)        /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER                    ((uint32_t)0x80000000)        /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  ((uint32_t)0x0000001F)        /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0)        /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  ((uint32_t)0x00007C00)        /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000)        /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)        /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0x000000FF)               /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001)        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Interrupt enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x00000002)        /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0x0000FF00)        /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint_t)0x00000FFF)          /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP             ((uint32_t)0x00000001)   /*!< TIM2 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP             ((uint32_t)0x00000002)   /*!< TIM3 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP             ((uint32_t)0x00000004)   /*!< TIM4 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP             ((uint32_t)0x00000008)   /*!< TIM5 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP             ((uint32_t)0x00000010)   /*!< TIM6 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP             ((uint32_t)0x00000020)   /*!< TIM7 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP              ((uint32_t)0x00000400)   /*!< RTC Counter stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP             ((uint32_t)0x00000800)   /*!< Debug Window Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP             ((uint32_t)0x00001000)   /*!< Debug Independent Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< SMBUS timeout mode stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)   /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP             ((uint32_t)0x00000004)   /*!< TIM9 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP            ((uint32_t)0x00000008)   /*!< TIM10 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP            ((uint32_t)0x00000010)   /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define  DMA_CCR_EN                         ((uint32_t)0x00000001)            /*!< Channel enable*/
-#define  DMA_CCR_TCIE                       ((uint32_t)0x00000002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR_HTIE                       ((uint32_t)0x00000004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR_TEIE                       ((uint32_t)0x00000008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR_DIR                        ((uint32_t)0x00000010)            /*!< Data transfer direction */
-#define  DMA_CCR_CIRC                       ((uint32_t)0x00000020)            /*!< Circular mode */
-#define  DMA_CCR_PINC                       ((uint32_t)0x00000040)            /*!< Peripheral increment mode */
-#define  DMA_CCR_MINC                       ((uint32_t)0x00000080)            /*!< Memory increment mode */
-
-#define  DMA_CCR_PSIZE                      ((uint32_t)0x00000300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR_PSIZE_0                    ((uint32_t)0x00000100)            /*!< Bit 0 */
-#define  DMA_CCR_PSIZE_1                    ((uint32_t)0x00000200)            /*!< Bit 1 */
-
-#define  DMA_CCR_MSIZE                      ((uint32_t)0x00000C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR_MSIZE_0                    ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  DMA_CCR_MSIZE_1                    ((uint32_t)0x00000800)            /*!< Bit 1 */
-
-#define  DMA_CCR_PL                         ((uint32_t)0x00003000)            /*!< PL[1:0] bits(Channel Priority level) */
-#define  DMA_CCR_PL_0                       ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  DMA_CCR_PL_1                       ((uint32_t)0x00002000)            /*!< Bit 1 */
-
-#define  DMA_CCR_MEM2MEM                    ((uint32_t)0x00004000)            /*!< Memory to memory mode */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define  DMA_CNDTR1_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define  DMA_CNDTR2_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define  DMA_CNDTR3_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define  DMA_CNDTR4_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define  DMA_CNDTR5_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define  DMA_CNDTR6_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define  DMA_CNDTR7_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)            /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)            /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
-#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< Latency */
-#define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_ACC64                     ((uint32_t)0x00000004)        /*!< Access 64 bits */
-#define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
-#define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
-#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
-#define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
-#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_PARALLBANK                ((uint32_t)0x00008000)        /*!< Parallel Bank mode */
-#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
-#define  FLASH_SR_ENDHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */
-#define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
-
-#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protected error */
-#define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
-#define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
-#define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option validity error */
-#define  FLASH_SR_OPTVERRUSR                 ((uint32_t)0x00001000)        /*!< Option User validity error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_RDPRT                     ((uint32_t)0x000000FF)        /*!< Read Protection */
-#define  FLASH_OBR_BOR_LEV                   ((uint32_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define  FLASH_OBR_USER                      ((uint32_t)0x00F00000)        /*!< User Option Bytes */
-#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00100000)        /*!< IWDG_SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00200000)        /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00400000)        /*!< nRST_STDBY */
-#define  FLASH_OBR_nRST_BFB2                 ((uint32_t)0x00800000)        /*!< BFB2 */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR1_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
-#define  FLASH_WRPR2_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */             
-#define  FLASH_WRPR3_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */ 
-#define  FLASH_WRPR4_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */ 
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
-
-#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
-
-#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
-
-#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
-
-#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
-
-#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
-
-#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
-
-#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
-
-#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
-
-#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
-
-#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
-
-#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
-
-#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
-
-#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
-
-#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
-
-#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
-
-#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
-
-#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
-
-#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
-
-#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
-
-#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
-
-#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
-
-#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
-
-#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
-
-#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
-
-#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
-
-#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
-
-#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
-
-#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
-
-#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
-
-#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
-
-#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
-
-#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
-
-#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
-
-#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
-
-#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
-
-#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
-
-#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
-
-#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
-
-#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
-
-#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
-
-#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
-
-#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
-
-#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
-
-#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)            /*!< Peripheral Enable */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)            /*!< SMBus Mode */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)            /*!< SMBus Type */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)            /*!< ARP Enable */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)            /*!< PEC Enable */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)            /*!< General Call Enable */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)            /*!< Clock Stretching Disable (Slave mode) */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100)            /*!< Start Generation */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200)            /*!< Stop Generation */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400)            /*!< Acknowledge Enable */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800)            /*!< Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000)            /*!< Packet Error Checking */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)            /*!< SMBus Alert */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)            /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)            /*!< Bit 5 */
-
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)            /*!< Error Interrupt Enable */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)            /*!< Event Interrupt Enable */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)            /*!< Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)            /*!< DMA Requests Enable */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000)            /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)            /*!< Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)            /*!< Interface Address */
-
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)            /*!< Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)            /*!< Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)            /*!< Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)            /*!< Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)            /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)               /*!< Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)               /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FF)               /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001)            /*!< Start Bit (Master mode) */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)            /*!< Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004)            /*!< Byte Transfer Finished */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)            /*!< 10-bit header sent (Master mode) */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)            /*!< Stop detection (Slave mode) */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)            /*!< Data Register not Empty (receivers) */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080)            /*!< Data Register Empty (transmitters) */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100)            /*!< Bus Error */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)            /*!< Arbitration Lost (master mode) */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400)            /*!< Acknowledge Failure */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800)            /*!< Overrun/Underrun */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)            /*!< PEC Error in reception */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)            /*!< Timeout or Tlow Error */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)            /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001)            /*!< Master/Slave */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)            /*!< Bus Busy */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004)            /*!< Transmitter/Receiver */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)            /*!< General Call Address (Slave mode) */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)            /*!< SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)            /*!< SMBus Host Header (Slave mode) */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)            /*!< Dual Flag (Slave mode) */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)            /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)            /*!< Fast Mode Duty Cycle */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000)            /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0x0000FFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x00000007)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x00000001)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x00000002)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x00000004)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x00000FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x00000001)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint32_t)0x00000002)               /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          LCD Controller (LCD)                              */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for LCD_CR register  *********************/
-#define LCD_CR_LCDEN               ((uint32_t)0x00000001)     /*!< LCD Enable Bit */
-#define LCD_CR_VSEL                ((uint32_t)0x00000002)     /*!< Voltage source selector Bit */
-
-#define LCD_CR_DUTY                ((uint32_t)0x0000001C)     /*!< DUTY[2:0] bits (Duty selector) */
-#define LCD_CR_DUTY_0              ((uint32_t)0x00000004)     /*!< Duty selector Bit 0 */
-#define LCD_CR_DUTY_1              ((uint32_t)0x00000008)     /*!< Duty selector Bit 1 */
-#define LCD_CR_DUTY_2              ((uint32_t)0x00000010)     /*!< Duty selector Bit 2 */
-
-#define LCD_CR_BIAS                ((uint32_t)0x00000060)     /*!< BIAS[1:0] bits (Bias selector) */
-#define LCD_CR_BIAS_0              ((uint32_t)0x00000020)     /*!< Bias selector Bit 0 */
-#define LCD_CR_BIAS_1              ((uint32_t)0x00000040)     /*!< Bias selector Bit 1 */
-
-#define LCD_CR_MUX_SEG             ((uint32_t)0x00000080)     /*!< Mux Segment Enable Bit */
-
-/*******************  Bit definition for LCD_FCR register  ********************/
-#define LCD_FCR_HD                 ((uint32_t)0x00000001)     /*!< High Drive Enable Bit */
-#define LCD_FCR_SOFIE              ((uint32_t)0x00000002)     /*!< Start of Frame Interrupt Enable Bit */
-#define LCD_FCR_UDDIE              ((uint32_t)0x00000008)     /*!< Update Display Done Interrupt Enable Bit */
-
-#define LCD_FCR_PON                ((uint32_t)0x00000070)     /*!< PON[2:0] bits (Puls ON Duration) */
-#define LCD_FCR_PON_0              ((uint32_t)0x00000010)     /*!< Bit 0 */
-#define LCD_FCR_PON_1              ((uint32_t)0x00000020)     /*!< Bit 1 */
-#define LCD_FCR_PON_2              ((uint32_t)0x00000040)     /*!< Bit 2 */
-
-#define LCD_FCR_DEAD               ((uint32_t)0x00000380)     /*!< DEAD[2:0] bits (DEAD Time) */
-#define LCD_FCR_DEAD_0             ((uint32_t)0x00000080)     /*!< Bit 0 */
-#define LCD_FCR_DEAD_1             ((uint32_t)0x00000100)     /*!< Bit 1 */
-#define LCD_FCR_DEAD_2             ((uint32_t)0x00000200)     /*!< Bit 2 */
-
-#define LCD_FCR_CC                 ((uint32_t)0x00001C00)     /*!< CC[2:0] bits (Contrast Control) */
-#define LCD_FCR_CC_0               ((uint32_t)0x00000400)     /*!< Bit 0 */
-#define LCD_FCR_CC_1               ((uint32_t)0x00000800)     /*!< Bit 1 */
-#define LCD_FCR_CC_2               ((uint32_t)0x00001000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINKF             ((uint32_t)0x0000E000)     /*!< BLINKF[2:0] bits (Blink Frequency) */
-#define LCD_FCR_BLINKF_0           ((uint32_t)0x00002000)     /*!< Bit 0 */
-#define LCD_FCR_BLINKF_1           ((uint32_t)0x00004000)     /*!< Bit 1 */
-#define LCD_FCR_BLINKF_2           ((uint32_t)0x00008000)     /*!< Bit 2 */
-
-#define LCD_FCR_BLINK              ((uint32_t)0x00030000)     /*!< BLINK[1:0] bits (Blink Enable) */
-#define LCD_FCR_BLINK_0            ((uint32_t)0x00010000)     /*!< Bit 0 */
-#define LCD_FCR_BLINK_1            ((uint32_t)0x00020000)     /*!< Bit 1 */
-
-#define LCD_FCR_DIV                ((uint32_t)0x003C0000)     /*!< DIV[3:0] bits (Divider) */
-#define LCD_FCR_PS                 ((uint32_t)0x03C00000)     /*!< PS[3:0] bits (Prescaler) */
-
-/*******************  Bit definition for LCD_SR register  *********************/
-#define LCD_SR_ENS                 ((uint32_t)0x00000001)     /*!< LCD Enabled Bit */
-#define LCD_SR_SOF                 ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Bit */
-#define LCD_SR_UDR                 ((uint32_t)0x00000004)     /*!< Update Display Request Bit */
-#define LCD_SR_UDD                 ((uint32_t)0x00000008)     /*!< Update Display Done Flag Bit */
-#define LCD_SR_RDY                 ((uint32_t)0x00000010)     /*!< Ready Flag Bit */
-#define LCD_SR_FCRSR               ((uint32_t)0x00000020)     /*!< LCD FCR Register Synchronization Flag Bit */
-
-/*******************  Bit definition for LCD_CLR register  ********************/
-#define LCD_CLR_SOFC               ((uint32_t)0x00000002)     /*!< Start Of Frame Flag Clear Bit */
-#define LCD_CLR_UDDC               ((uint32_t)0x00000008)     /*!< Update Display Done Flag Clear Bit */
-
-/*******************  Bit definition for LCD_RAM register  ********************/
-#define LCD_RAM_SEGMENT_DATA       ((uint32_t)0xFFFFFFFF)     /*!< Segment Data Bits */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPSDSR                       ((uint32_t)0x00000001)     /*!< Low-power deepsleep/sleep/low power run */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection */
-#define  PWR_CR_ULP                          ((uint32_t)0x00000200)     /*!< Ultra Low Power mode */
-#define  PWR_CR_FWU                          ((uint32_t)0x00000400)     /*!< Fast wakeup */
-
-#define  PWR_CR_VOS                          ((uint32_t)0x00001800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00000800)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00001000)     /*!< Bit 1 */
-#define  PWR_CR_LPRUN                        ((uint32_t)0x00004000)     /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output */
-#define  PWR_CSR_VREFINTRDYF                 ((uint32_t)0x00000008)     /*!< Internal voltage reference (VREFINT) ready flag */
-#define  PWR_CSR_VOSF                        ((uint32_t)0x00000010)     /*!< Voltage Scaling select flag */
-#define  PWR_CSR_REGLPF                      ((uint32_t)0x00000020)     /*!< Regulator LP flag */
-
-#define  PWR_CSR_EWUP1                       ((uint32_t)0x00000100)     /*!< Enable WKUP pin 1 */
-#define  PWR_CSR_EWUP2                       ((uint32_t)0x00000200)     /*!< Enable WKUP pin 2 */
-#define  PWR_CSR_EWUP3                       ((uint32_t)0x00000400)     /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
-
-#define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
-#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-#define  RCC_CR_CSSON                        ((uint32_t)0x10000000)        /*!< Clock Security System enable */
-
-#define  RCC_CR_RTCPRE                       ((uint32_t)0x60000000)        /*!< RTC/LCD Prescaler */
-#define  RCC_CR_RTCPRE_0                     ((uint32_t)0x20000000)        /*!< Bit0 */
-#define  RCC_CR_RTCPRE_1                     ((uint32_t)0x40000000)        /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
-#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
-
-#define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
-#define  RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define  RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define  RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define  RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define  RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define  RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define  RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
-#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-/*!< SW configuration */
-#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
-
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
-
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
-#define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
-#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
-#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
-#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
-#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
-#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
-#define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
-#define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
-#define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
-#define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
-
-
-/*!< PLLDIV configuration */
-#define  RCC_CFGR_PLLDIV1                    ((uint32_t)0x00000000)        /*!< PLL clock output = CKVCO / 1 */
-#define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
-#define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
-#define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
-
-
-#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-/*!< MCO configuration */
-#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected */
-#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
-#define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
-#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
-#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
-#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
-#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
-
-#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000)        /*!< Bit 2 */
-
-/*!< MCO Prescaler configuration */
-#define  RCC_CFGR_MCO_DIV1                   ((uint32_t)0x00000000)        /*!< MCO Clock divided by 1 */
-#define  RCC_CFGR_MCO_DIV2                   ((uint32_t)0x10000000)        /*!< MCO Clock divided by 2 */
-#define  RCC_CFGR_MCO_DIV4                   ((uint32_t)0x20000000)        /*!< MCO Clock divided by 4 */
-#define  RCC_CFGR_MCO_DIV8                   ((uint32_t)0x30000000)        /*!< MCO Clock divided by 8 */
-#define  RCC_CFGR_MCO_DIV16                  ((uint32_t)0x40000000)        /*!< MCO Clock divided by 16 */
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
-#define  RCC_CIR_LSECSS                      ((uint32_t)0x00000040)        /*!< LSE CSS Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_MSIRDYIE                    ((uint32_t)0x00002000)        /*!< MSI Ready Interrupt Enable */
-#define  RCC_CIR_LSECSSIE                    ((uint32_t)0x00004000)        /*!< LSE CSS Interrupt Enable */
-
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_MSIRDYC                     ((uint32_t)0x00200000)        /*!< MSI Ready Interrupt Clear */
-#define  RCC_CIR_LSECSSC                     ((uint32_t)0x00400000)        /*!< LSE CSS Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
-#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
-#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
-#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
-#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */
-#define  RCC_AHBRSTR_GPIOHRST                ((uint32_t)0x00000020)        /*!< GPIO port H reset */
-#define  RCC_AHBRSTR_GPIOFRST                ((uint32_t)0x00000040)        /*!< GPIO port F reset */
-#define  RCC_AHBRSTR_GPIOGRST                ((uint32_t)0x00000080)        /*!< GPIO port G reset */
-#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
-#define  RCC_AHBRSTR_FLITFRST                ((uint32_t)0x00008000)        /*!< FLITF reset */
-#define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x01000000)        /*!< DMA1 reset */
-#define  RCC_AHBRSTR_DMA2RST                 ((uint32_t)0x02000000)        /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< System Configuration SYSCFG reset */
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00000004)        /*!< TIM9 reset */
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00000008)        /*!< TIM10 reset */
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00000010)        /*!< TIM11 reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
-#define  RCC_APB1RSTR_LCDRST                 ((uint32_t)0x00000200)        /*!< LCD reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
-#define  RCC_APB1RSTR_UART4RST               ((uint32_t)0x00080000)        /*!< UART 4 reset */
-#define  RCC_APB1RSTR_UART5RST               ((uint32_t)0x00100000)        /*!< UART 5 reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
-#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
-#define  RCC_APB1RSTR_COMPRST                ((uint32_t)0x80000000)        /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
-#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
-#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
-#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
-#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */
-#define  RCC_AHBENR_GPIOHEN                  ((uint32_t)0x00000020)        /*!< GPIO port H clock enable */
-#define  RCC_AHBENR_GPIOFEN                  ((uint32_t)0x00000040)        /*!< GPIO port F clock enable */
-#define  RCC_AHBENR_GPIOGEN                  ((uint32_t)0x00000080)        /*!< GPIO port G clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00008000)        /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x01000000)        /*!< DMA1 clock enable */
-#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x02000000)        /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enable */
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00000004)         /*!< TIM9 interface clock enable */
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00000008)         /*!< TIM10 interface clock enable */
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC1 clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
-#define  RCC_APB1ENR_LCDEN                   ((uint32_t)0x00000200)        /*!< LCD clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
-#define  RCC_APB1ENR_UART4EN                 ((uint32_t)0x00080000)        /*!< UART 4 clock enable */
-#define  RCC_APB1ENR_UART5EN                 ((uint32_t)0x00100000)        /*!< UART 5 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
-#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
-#define  RCC_APB1ENR_COMPEN                  ((uint32_t)0x80000000)        /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define  RCC_AHBLPENR_GPIOALPEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOBLPEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOCLPEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIODLPEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOELPEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOHLPEN              ((uint32_t)0x00000020)        /*!< GPIO port H clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOFLPEN              ((uint32_t)0x00000040)        /*!< GPIO port F clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOGLPEN              ((uint32_t)0x00000080)        /*!< GPIO port G clock enabled in sleep mode */
-#define  RCC_AHBLPENR_CRCLPEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
-#define  RCC_AHBLPENR_FLITFLPEN              ((uint32_t)0x00008000)        /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define  RCC_AHBLPENR_SRAMLPEN               ((uint32_t)0x00010000)        /*!< SRAM clock enabled in sleep mode */
-#define  RCC_AHBLPENR_DMA1LPEN               ((uint32_t)0x01000000)        /*!< DMA1 clock enabled in sleep mode */
-#define  RCC_AHBLPENR_DMA2LPEN               ((uint32_t)0x02000000)        /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00000004)         /*!< TIM9 interface clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00000008)         /*!< TIM10 interface clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enabled in sleep mode */
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000200)         /*!< ADC1 clock enabled in sleep mode */
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)         /*!< SPI1 clock enabled in sleep mode */
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00004000)         /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)        /*!< Timer 4 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)        /*!< Timer 5 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_LCDLPEN               ((uint32_t)0x00000200)        /*!< LCD clock enabled in sleep mode */
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)        /*!< SPI 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)        /*!< SPI 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)        /*!< USART 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)        /*!< USART 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_UART4LPEN             ((uint32_t)0x00080000)        /*!< UART 4 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_UART5LPEN             ((uint32_t)0x00100000)        /*!< UART 5 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)        /*!< I2C 1 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)        /*!< I2C 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USBLPEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)        /*!< Power interface clock enabled in sleep mode */
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)        /*!< DAC interface clock enabled in sleep mode */
-#define  RCC_APB1LPENR_COMPLPEN              ((uint32_t)0x80000000)        /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define  RCC_CSR_LSION                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                     ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-
-#define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
-#define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
-#define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_CSR_LSECSSON                   ((uint32_t)0x00000800)        /*!< External Low Speed oscillator CSS Enable */
-#define  RCC_CSR_LSECSSD                    ((uint32_t)0x00001000)        /*!< External Low Speed oscillator CSS Detected */
-
-#define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define  RCC_CSR_RTCEN                      ((uint32_t)0x00400000)        /*!< RTC clock enable */
-#define  RCC_CSR_RTCRST                     ((uint32_t)0x00800000)        /*!< RTC reset  */
- 
-#define  RCC_CSR_RMVF                       ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_OBLRSTF                    ((uint32_t)0x02000000)        /*!< Option Bytes Loader reset flag */
-#define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
-#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!< Master Selection */
-
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!< Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!< Receive only */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!< Data Frame Format */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)               /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)               /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)               /*!< SS Output Enable */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)               /*!< Frame format */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)               /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)               /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)               /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)               /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002)               /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)               /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008)               /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)               /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020)               /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040)               /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080)               /*!< Busy flag */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100)               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
-#define SYSCFG_MEMRMP_BOOT_MODE         ((uint32_t)0x00000300) /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       ((uint32_t)0x00000200) /*!< Bit 1 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU               ((uint32_t)0x00000001) /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000005) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000006) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000007) /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000050) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000060) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000070) /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000500) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000600) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000700) /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00003000) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00004000) /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000006) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000007) /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000060) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000070) /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000600) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000700) /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00006000) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00007000) /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000006) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000007) /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000060) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000070) /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000600) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000700) /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00006000) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00007000) /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000006) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000007) /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000060) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000070) /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000600) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000700) /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00006000) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00007000) /*!< PG[15] pin */
- 
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define  RI_ICR_IC1OS                    ((uint32_t)0x0000000F) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define  RI_ICR_IC1OS_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ICR_IC1OS_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ICR_IC1OS_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ICR_IC1OS_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define  RI_ICR_IC2OS                    ((uint32_t)0x000000F0) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define  RI_ICR_IC2OS_0                  ((uint32_t)0x00000010) /*!< Bit 0 */
-#define  RI_ICR_IC2OS_1                  ((uint32_t)0x00000020) /*!< Bit 1 */
-#define  RI_ICR_IC2OS_2                  ((uint32_t)0x00000040) /*!< Bit 2 */
-#define  RI_ICR_IC2OS_3                  ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define  RI_ICR_IC3OS                    ((uint32_t)0x00000F00) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define  RI_ICR_IC3OS_0                  ((uint32_t)0x00000100) /*!< Bit 0 */
-#define  RI_ICR_IC3OS_1                  ((uint32_t)0x00000200) /*!< Bit 1 */
-#define  RI_ICR_IC3OS_2                  ((uint32_t)0x00000400) /*!< Bit 2 */
-#define  RI_ICR_IC3OS_3                  ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define  RI_ICR_IC4OS                    ((uint32_t)0x0000F000) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define  RI_ICR_IC4OS_0                  ((uint32_t)0x00001000) /*!< Bit 0 */
-#define  RI_ICR_IC4OS_1                  ((uint32_t)0x00002000) /*!< Bit 1 */
-#define  RI_ICR_IC4OS_2                  ((uint32_t)0x00004000) /*!< Bit 2 */
-#define  RI_ICR_IC4OS_3                  ((uint32_t)0x00008000) /*!< Bit 3 */
-
-#define  RI_ICR_TIM                     ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
-#define  RI_ICR_TIM_0                   ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_ICR_TIM_1                   ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define  RI_ICR_IC1                     ((uint32_t)0x00040000) /*!< Input capture 1 */
-#define  RI_ICR_IC2                     ((uint32_t)0x00080000) /*!< Input capture 2 */
-#define  RI_ICR_IC3                     ((uint32_t)0x00100000) /*!< Input capture 3 */
-#define  RI_ICR_IC4                     ((uint32_t)0x00200000) /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define  RI_ASCR1_CH                    ((uint32_t)0x7BFDFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define  RI_ASCR1_CH_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASCR1_CH_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASCR1_CH_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASCR1_CH_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASCR1_CH_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASCR1_CH_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASCR1_CH_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASCR1_CH_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASCR1_CH_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASCR1_CH_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASCR1_CH_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASCR1_CH_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASCR1_CH_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASCR1_CH_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASCR1_CH_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASCR1_CH_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-#define  RI_ASCR1_CH_31                 ((uint32_t)0x00010000) /*!< Bit 16 */
-#define  RI_ASCR1_CH_18                 ((uint32_t)0x00040000) /*!< Bit 18 */
-#define  RI_ASCR1_CH_19                 ((uint32_t)0x00080000) /*!< Bit 19 */
-#define  RI_ASCR1_CH_20                 ((uint32_t)0x00100000) /*!< Bit 20 */
-#define  RI_ASCR1_CH_21                 ((uint32_t)0x00200000) /*!< Bit 21 */
-#define  RI_ASCR1_CH_22                 ((uint32_t)0x00400000) /*!< Bit 22 */
-#define  RI_ASCR1_CH_23                 ((uint32_t)0x00800000) /*!< Bit 23 */
-#define  RI_ASCR1_CH_24                 ((uint32_t)0x01000000) /*!< Bit 24 */
-#define  RI_ASCR1_CH_25                 ((uint32_t)0x02000000) /*!< Bit 25 */
-#define  RI_ASCR1_VCOMP                 ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
-#define  RI_ASCR1_CH_27                 ((uint32_t)0x00400000) /*!< Bit 27 */
-#define  RI_ASCR1_CH_28                 ((uint32_t)0x00800000) /*!< Bit 28 */
-#define  RI_ASCR1_CH_29                 ((uint32_t)0x01000000) /*!< Bit 29 */
-#define  RI_ASCR1_CH_30                 ((uint32_t)0x02000000) /*!< Bit 30 */
-#define  RI_ASCR1_SCM                   ((uint32_t)0x80000000) /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define  RI_ASCR2_GR10_1                ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
-#define  RI_ASCR2_GR10_2                ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
-#define  RI_ASCR2_GR10_3                ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
-#define  RI_ASCR2_GR10_4                ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
-#define  RI_ASCR2_GR6_1                 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
-#define  RI_ASCR2_GR6_2                 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
-#define  RI_ASCR2_GR5_1                 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
-#define  RI_ASCR2_GR5_2                 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
-#define  RI_ASCR2_GR5_3                 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
-#define  RI_ASCR2_GR4_1                 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
-#define  RI_ASCR2_GR4_2                 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
-#define  RI_ASCR2_GR4_3                 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
-#define  RI_ASCR2_GR4_4                 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
-#define  RI_ASCR2_CH0b                  ((uint32_t)0x00010000) /*!< CH0b selection bit */
-#define  RI_ASCR2_CH1b                  ((uint32_t)0x00020000) /*!< CH1b selection bit */
-#define  RI_ASCR2_CH2b                  ((uint32_t)0x00040000) /*!< CH2b selection bit */
-#define  RI_ASCR2_CH3b                  ((uint32_t)0x00080000) /*!< CH3b selection bit */
-#define  RI_ASCR2_CH6b                  ((uint32_t)0x00100000) /*!< CH6b selection bit */
-#define  RI_ASCR2_CH7b                  ((uint32_t)0x00200000) /*!< CH7b selection bit */
-#define  RI_ASCR2_CH8b                  ((uint32_t)0x00400000) /*!< CH8b selection bit */
-#define  RI_ASCR2_CH9b                  ((uint32_t)0x00800000) /*!< CH9b selection bit */
-#define  RI_ASCR2_CH10b                 ((uint32_t)0x01000000) /*!< CH10b selection bit */
-#define  RI_ASCR2_CH11b                 ((uint32_t)0x02000000) /*!< CH11b selection bit */
-#define  RI_ASCR2_CH12b                 ((uint32_t)0x04000000) /*!< CH12b selection bit */
-#define  RI_ASCR2_GR6_3                 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
-#define  RI_ASCR2_GR6_4                 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define  RI_HYSCR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
-#define  RI_HYSCR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR1_PB                   ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
-#define  RI_HYSCR1_PB_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR1_PB_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR1_PB_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR1_PB_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR1_PB_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR1_PB_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR1_PB_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR1_PB_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR1_PB_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR1_PB_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR1_PB_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR1_PB_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR1_PB_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR1_PB_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR1_PB_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR1_PB_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define  RI_HYSCR2_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
-#define  RI_HYSCR2_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR2_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR2_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR2_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR2_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR2_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR2_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR2_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR2_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR2_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR2_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR2_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR2_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR2_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR2_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR2_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR2_PD                   ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
-#define  RI_HYSCR2_PD_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR2_PD_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR2_PD_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR2_PD_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR2_PD_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR2_PD_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR2_PD_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR2_PD_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR2_PD_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR2_PD_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR2_PD_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR2_PD_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR2_PD_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR2_PD_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR2_PD_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR2_PD_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define  RI_HYSCR3_PE                   ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
-#define  RI_HYSCR3_PE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR3_PE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR3_PE_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR3_PE_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR3_PE_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR3_PE_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR3_PE_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR3_PE_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR3_PE_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR3_PE_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR3_PE_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR3_PE_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR3_PE_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR3_PE_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR3_PE_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR3_PE_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-#define  RI_HYSCR3_PF                   ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
-#define  RI_HYSCR3_PF_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR3_PF_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR3_PF_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR3_PF_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR3_PF_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR3_PF_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR3_PF_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR3_PF_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR3_PF_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR3_PF_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR3_PF_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR3_PF_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR3_PF_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR3_PF_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR3_PF_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR3_PF_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR4 register  ********************/
-#define  RI_HYSCR4_PG                   ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
-#define  RI_HYSCR4_PG_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR4_PG_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR4_PG_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR4_PG_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR4_PG_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR4_PG_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR4_PG_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR4_PG_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR4_PG_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR4_PG_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR4_PG_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR4_PG_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR4_PG_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR4_PG_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR4_PG_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR4_PG_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define  RI_ASMR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_ASMR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define  RI_CMR1_PA                    ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_CMR1_PA_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR1_PA_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR1_PA_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR1_PA_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR1_PA_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR1_PA_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR1_PA_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR1_PA_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR1_PA_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR1_PA_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR1_PA_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR1_PA_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR1_PA_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR1_PA_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR1_PA_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR1_PA_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define  RI_CICR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_CICR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define  RI_ASMR2_PB                   ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_ASMR2_PB_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR2_PB_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR2_PB_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR2_PB_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR2_PB_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR2_PB_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR2_PB_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR2_PB_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR2_PB_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR2_PB_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR2_PB_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR2_PB_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR2_PB_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR2_PB_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR2_PB_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR2_PB_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define  RI_CMR2_PB                    ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_CMR2_PB_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR2_PB_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR2_PB_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR2_PB_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR2_PB_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR2_PB_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR2_PB_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR2_PB_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR2_PB_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR2_PB_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR2_PB_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR2_PB_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR2_PB_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR2_PB_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR2_PB_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR2_PB_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define  RI_CICR2_PB                   ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_CICR2_PB_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR2_PB_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR2_PB_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR2_PB_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR2_PB_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR2_PB_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR2_PB_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR2_PB_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR2_PB_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR2_PB_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR2_PB_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR2_PB_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR2_PB_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR2_PB_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR2_PB_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR2_PB_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define  RI_ASMR3_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_ASMR3_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR3_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR3_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR3_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR3_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR3_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR3_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR3_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR3_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR3_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR3_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR3_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR3_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR3_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR3_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR3_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define  RI_CMR3_PC                    ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_CMR3_PC_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR3_PC_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR3_PC_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR3_PC_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR3_PC_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR3_PC_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR3_PC_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR3_PC_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR3_PC_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR3_PC_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR3_PC_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR3_PC_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR3_PC_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR3_PC_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR3_PC_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR3_PC_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define  RI_CICR3_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_CICR3_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR3_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR3_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR3_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR3_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR3_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR3_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR3_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR3_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR3_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR3_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR3_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR3_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR3_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR3_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR3_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR4 register  ********************/
-#define  RI_ASMR4_PF                   ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
-#define  RI_ASMR4_PF_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR4_PF_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR4_PF_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR4_PF_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR4_PF_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR4_PF_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR4_PF_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR4_PF_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR4_PF_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR4_PF_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR4_PF_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR4_PF_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR4_PF_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR4_PF_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR4_PF_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR4_PF_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR4 register  ********************/
-#define  RI_CMR4_PF                    ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
-#define  RI_CMR4_PF_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR4_PF_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR4_PF_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR4_PF_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR4_PF_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR4_PF_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR4_PF_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR4_PF_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR4_PF_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR4_PF_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR4_PF_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR4_PF_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR4_PF_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR4_PF_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR4_PF_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR4_PF_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR4 register  ********************/
-#define  RI_CICR4_PF                   ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F selection */
-#define  RI_CICR4_PF_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR4_PF_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR4_PF_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR4_PF_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR4_PF_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR4_PF_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR4_PF_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR4_PF_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR4_PF_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR4_PF_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR4_PF_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR4_PF_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR4_PF_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR4_PF_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR4_PF_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR4_PF_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR5 register  ********************/
-#define  RI_ASMR5_PG                   ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
-#define  RI_ASMR5_PG_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR5_PG_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR5_PG_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR5_PG_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR5_PG_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR5_PG_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR5_PG_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR5_PG_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR5_PG_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR5_PG_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR5_PG_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR5_PG_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR5_PG_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR5_PG_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR5_PG_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR5_PG_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR5 register  ********************/
-#define  RI_CMR5_PG                    ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
-#define  RI_CMR5_PG_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR5_PG_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR5_PG_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR5_PG_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR5_PG_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR5_PG_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR5_PG_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR5_PG_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR5_PG_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR5_PG_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR5_PG_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR5_PG_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR5_PG_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR5_PG_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR5_PG_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR5_PG_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR5 register  ********************/
-#define  RI_CICR5_PG                   ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G selection */
-#define  RI_CICR5_PG_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR5_PG_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR5_PG_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR5_PG_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR5_PG_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR5_PG_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR5_PG_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR5_PG_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR5_PG_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR5_PG_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR5_PG_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR5_PG_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR5_PG_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR5_PG_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR5_PG_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR5_PG_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x00000001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x00000002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint32_t)0x00000004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x00000008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint32_t)0x00000010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint32_t)0x00000060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x00000020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x00000040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint32_t)0x00000080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint32_t)0x00000300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x00000007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x00000001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_TIE                        ((uint32_t)0x00000040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_UDE                        ((uint32_t)0x00000100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x00000200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x00001000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint32_t)0x00004000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x00000001)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x00000002)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x00000004)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x00000008)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x00000010)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x00000040)               /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x00000070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x00007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0x0000FFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0x0000FFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0x0000FFFF)            /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x0000001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x00000010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint32_t)0x00001F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x00000800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x00001000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0x0000FFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define  TIM_OR_TI1RMP                       ((uint32_t)0x00000003)            /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define  TIM_OR_TI1RMP_0                     ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_OR_TI1RMP_1                     ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_OR_ETR_RMP                      ((uint32_t)0x00000004)            /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define  TIM_OR_TI1_RMP_RI                   ((uint32_t)0x00000008)            /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM9_OR_ITR1_RMP                    ((uint32_t)0x00000004)            /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM2_OR_ITR1_RMP                    ((uint32_t)0x00000001)            /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM3_OR_ITR2_RMP                    ((uint32_t)0x00000001)            /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x00000001)            /*!< Parity Error */
-#define  USART_SR_FE                         ((uint32_t)0x00000002)            /*!< Framing Error */
-#define  USART_SR_NE                         ((uint32_t)0x00000004)            /*!< Noise Error Flag */
-#define  USART_SR_ORE                        ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define  USART_SR_IDLE                       ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define  USART_SR_RXNE                       ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define  USART_SR_TXE                        ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define  USART_SR_CTS                        ((uint32_t)0x00000200)            /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x000001FF)            /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint32_t)0x0000000F)            /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint32_t)0x0000FFF0)            /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x00000001)            /*!< Send Break */
-#define  USART_CR1_RWU                       ((uint32_t)0x00000002)            /*!< Receiver wakeup */
-#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Wakeup method */
-#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
-#define  USART_CR1_UE                        ((uint32_t)0x00002000)            /*!< USART Enable */
-#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x0000000F)            /*!< Address of the USART node */
-#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-
-#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-
-#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< Smartcard NACK enable */
-#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< Smartcard mode enable */
-#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x000000FF)            /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x00000040)            /*!< Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x00000080)            /*!< Bit 7 */
-
-#define  USART_GTPR_GT                       ((uint32_t)0x0000FF00)            /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000C)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001C)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define  USB_EP_CTR_RX                        ((uint32_t)0x00008000)           /*!<  EndPoint Correct TRansfer RX */
-#define  USB_EP_DTOG_RX                       ((uint32_t)0x00004000)           /*!<  EndPoint Data TOGGLE RX */
-#define  USB_EPRX_STAT                        ((uint32_t)0x00003000)           /*!<  EndPoint RX STATus bit field */
-#define  USB_EP_SETUP                         ((uint32_t)0x00000800)           /*!<  EndPoint SETUP */
-#define  USB_EP_T_FIELD                       ((uint32_t)0x00000600)           /*!<  EndPoint TYPE */
-#define  USB_EP_KIND                          ((uint32_t)0x00000100)           /*!<  EndPoint KIND */
-#define  USB_EP_CTR_TX                        ((uint32_t)0x00000080)           /*!<  EndPoint Correct TRansfer TX */
-#define  USB_EP_DTOG_TX                       ((uint32_t)0x00000040)           /*!<  EndPoint Data TOGGLE TX */
-#define  USB_EPTX_STAT                        ((uint32_t)0x00000030)           /*!<  EndPoint TX STATus bit field */
-#define  USB_EPADDR_FIELD                     ((uint32_t)0x0000000F)           /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define  USB_EP_TYPE_MASK                     ((uint32_t)0x00000600)           /*!< EndPoint TYPE Mask */
-#define  USB_EP_BULK                          ((uint32_t)0x00000000)           /*!< EndPoint BULK */
-#define  USB_EP_CONTROL                       ((uint32_t)0x00000200)           /*!< EndPoint CONTROL */
-#define  USB_EP_ISOCHRONOUS                   ((uint32_t)0x00000400)           /*!< EndPoint ISOCHRONOUS */
-#define  USB_EP_INTERRUPT                     ((uint32_t)0x00000600)           /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define  USB_EP_TX_DIS                        ((uint32_t)0x00000000)           /*!< EndPoint TX DISabled */
-#define  USB_EP_TX_STALL                      ((uint32_t)0x00000010)           /*!< EndPoint TX STALLed */
-#define  USB_EP_TX_NAK                        ((uint32_t)0x00000020)           /*!< EndPoint TX NAKed */
-#define  USB_EP_TX_VALID                      ((uint32_t)0x00000030)           /*!< EndPoint TX VALID */
-#define  USB_EPTX_DTOG1                       ((uint32_t)0x00000010)           /*!< EndPoint TX Data TOGgle bit1 */
-#define  USB_EPTX_DTOG2                       ((uint32_t)0x00000020)           /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define  USB_EP_RX_DIS                        ((uint32_t)0x00000000)           /*!< EndPoint RX DISabled */
-#define  USB_EP_RX_STALL                      ((uint32_t)0x00001000)           /*!< EndPoint RX STALLed */
-#define  USB_EP_RX_NAK                        ((uint32_t)0x00002000)           /*!< EndPoint RX NAKed */
-#define  USB_EP_RX_VALID                      ((uint32_t)0x00003000)           /*!< EndPoint RX VALID */
-#define  USB_EPRX_DTOG1                       ((uint32_t)0x00001000)           /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOG2                       ((uint32_t)0x00002000)           /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define  USB_EP0R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP0R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP0R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP0R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP0R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP0R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP0R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP0R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP0R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP0R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP0R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP0R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP0R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP0R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP0R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP0R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define  USB_EP1R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP1R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP1R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP1R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP1R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP1R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP1R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP1R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP1R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP1R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP1R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP1R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP1R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP1R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP1R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP1R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define  USB_EP2R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP2R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP2R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP2R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP2R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP2R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP2R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP2R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP2R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP2R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP2R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP2R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP2R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP2R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP2R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP2R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define  USB_EP3R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP3R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP3R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP3R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP3R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP3R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP3R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP3R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP3R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP3R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP3R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP3R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP3R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP3R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP3R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP3R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define  USB_EP4R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP4R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP4R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP4R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP4R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP4R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP4R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP4R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP4R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP4R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP4R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP4R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP4R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP4R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP4R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP4R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define  USB_EP5R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP5R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP5R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP5R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP5R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP5R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP5R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP5R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP5R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP5R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP5R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP5R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP5R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP5R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP5R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP5R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define  USB_EP6R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP6R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP6R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP6R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP6R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP6R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP6R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP6R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP6R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP6R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP6R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP6R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP6R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP6R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP6R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP6R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define  USB_EP7R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP7R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP7R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP7R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP7R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP7R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP7R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP7R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP7R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP7R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP7R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP7R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP7R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP7R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP7R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP7R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004C)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define  USB_CNTR_FRES                       ((uint32_t)0x00000001)            /*!<Force USB Reset */
-#define  USB_CNTR_PDWN                       ((uint32_t)0x00000002)            /*!<Power down */
-#define  USB_CNTR_LP_MODE                    ((uint32_t)0x00000004)            /*!<Low-power mode */
-#define  USB_CNTR_FSUSP                      ((uint32_t)0x00000008)            /*!<Force suspend */
-#define  USB_CNTR_RESUME                     ((uint32_t)0x00000010)            /*!<Resume request */
-#define  USB_CNTR_ESOFM                      ((uint32_t)0x00000100)            /*!<Expected Start Of Frame Interrupt Mask */
-#define  USB_CNTR_SOFM                       ((uint32_t)0x00000200)            /*!<Start Of Frame Interrupt Mask */
-#define  USB_CNTR_RESETM                     ((uint32_t)0x00000400)            /*!<RESET Interrupt Mask */
-#define  USB_CNTR_SUSPM                      ((uint32_t)0x00000800)            /*!<Suspend mode Interrupt Mask */
-#define  USB_CNTR_WKUPM                      ((uint32_t)0x00001000)            /*!<Wakeup Interrupt Mask */
-#define  USB_CNTR_ERRM                       ((uint32_t)0x00002000)            /*!<Error Interrupt Mask */
-#define  USB_CNTR_PMAOVRM                    ((uint32_t)0x00004000)            /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define  USB_CNTR_CTRM                       ((uint32_t)0x00008000)            /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define  USB_ISTR_EP_ID                      ((uint32_t)0x0000000F)            /*!<Endpoint Identifier */
-#define  USB_ISTR_DIR                        ((uint32_t)0x00000010)            /*!<Direction of transaction */
-#define  USB_ISTR_ESOF                       ((uint32_t)0x00000100)            /*!<Expected Start Of Frame */
-#define  USB_ISTR_SOF                        ((uint32_t)0x00000200)            /*!<Start Of Frame */
-#define  USB_ISTR_RESET                      ((uint32_t)0x00000400)            /*!<USB RESET request */
-#define  USB_ISTR_SUSP                       ((uint32_t)0x00000800)            /*!<Suspend mode request */
-#define  USB_ISTR_WKUP                       ((uint32_t)0x00001000)            /*!<Wake up */
-#define  USB_ISTR_ERR                        ((uint32_t)0x00002000)            /*!<Error */
-#define  USB_ISTR_PMAOVRM                    ((uint32_t)0x00004000)            /*!<Packet Memory Area Over / Underrun */
-#define  USB_ISTR_CTR                        ((uint32_t)0x00008000)            /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define  USB_FNR_FN                          ((uint32_t)0x000007FF)            /*!<Frame Number */
-#define  USB_FNR_LSOF                        ((uint32_t)0x00001800)            /*!<Lost SOF */
-#define  USB_FNR_LCK                         ((uint32_t)0x00002000)            /*!<Locked */
-#define  USB_FNR_RXDM                        ((uint32_t)0x00004000)            /*!<Receive Data - Line Status */
-#define  USB_FNR_RXDP                        ((uint32_t)0x00008000)            /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define  USB_DADDR_ADD                       ((uint32_t)0x0000007F)               /*!<ADD[6:0] bits (Device Address) */
-#define  USB_DADDR_ADD0                      ((uint32_t)0x00000001)               /*!<Bit 0 */
-#define  USB_DADDR_ADD1                      ((uint32_t)0x00000002)               /*!<Bit 1 */
-#define  USB_DADDR_ADD2                      ((uint32_t)0x00000004)               /*!<Bit 2 */
-#define  USB_DADDR_ADD3                      ((uint32_t)0x00000008)               /*!<Bit 3 */
-#define  USB_DADDR_ADD4                      ((uint32_t)0x00000010)               /*!<Bit 4 */
-#define  USB_DADDR_ADD5                      ((uint32_t)0x00000020)               /*!<Bit 5 */
-#define  USB_DADDR_ADD6                      ((uint32_t)0x00000040)               /*!<Bit 6 */
-
-#define  USB_DADDR_EF                        ((uint32_t)0x00000080)               /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define  USB_BTABLE_BTABLE                   ((uint32_t)0x0000FFF8)            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define  USB_ADDR0_TX_ADDR0_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define  USB_ADDR1_TX_ADDR1_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define  USB_ADDR2_TX_ADDR2_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define  USB_ADDR3_TX_ADDR3_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define  USB_ADDR4_TX_ADDR4_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define  USB_ADDR5_TX_ADDR5_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define  USB_ADDR6_TX_ADDR6_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define  USB_ADDR7_TX_ADDR7_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define  USB_COUNT0_TX_COUNT0_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define  USB_COUNT1_TX_COUNT1_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define  USB_COUNT2_TX_COUNT2_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define  USB_COUNT3_TX_COUNT3_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define  USB_COUNT4_TX_COUNT4_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define  USB_COUNT5_TX_COUNT5_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define  USB_COUNT6_TX_COUNT6_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define  USB_COUNT7_TX_COUNT7_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint32_t)0x0000000003FF)        /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint32_t)0x000003FF0000)        /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define  USB_ADDR0_RX_ADDR0_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define  USB_ADDR1_RX_ADDR1_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define  USB_ADDR2_RX_ADDR2_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define  USB_ADDR3_RX_ADDR3_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define  USB_ADDR4_RX_ADDR4_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define  USB_ADDR5_RX_ADDR5_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define  USB_ADDR6_RX_ADDR6_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define  USB_ADDR7_RX_ADDR7_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define  USB_COUNT0_RX_COUNT0_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT0_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define  USB_COUNT1_RX_COUNT1_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT1_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define  USB_COUNT2_RX_COUNT2_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT2_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define  USB_COUNT3_RX_COUNT3_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT3_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define  USB_COUNT4_RX_COUNT4_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT4_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define  USB_COUNT5_RX_COUNT5_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT5_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define  USB_COUNT6_RX_COUNT6_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT6_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define  USB_COUNT7_RX_COUNT7_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT7_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x0000007F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x00000001)               /*!< Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x00000002)               /*!< Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x00000004)               /*!< Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x00000008)               /*!< Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x00000010)               /*!< Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x00000020)               /*!< Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x00000040)               /*!< Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint32_t)0x00000080)               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x0000007F)            /*!< W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x00000040)            /*!< Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x00000180)            /*!< WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x00000080)            /*!< Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x00000100)            /*!< Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint32_t)0x00000200)            /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x00000001)               /*!< Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        SystemTick (SysTick)                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*****************  Bit definition for SysTick_CTRL register  *****************/
-#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
-#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
-#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
-#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
-
-/*****************  Bit definition for SysTick_LOAD register  *****************/
-#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/*****************  Bit definition for SysTick_VAL register  ******************/
-#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
-
-/*****************  Bit definition for SysTick_CALIB register  ****************/
-#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
-#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
-#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/*                                                                            */
-/*               Nested Vectored Interrupt Controller (NVIC)                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for NVIC_ISER register  *******************/
-#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
-#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICER register  *******************/
-#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
-#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ISPR register  *******************/
-#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
-#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICPR register  *******************/
-#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
-#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_IABR register  *******************/
-#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
-#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_PRI0 register  *******************/
-#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
-#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
-#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
-#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
-
-/******************  Bit definition for NVIC_PRI1 register  *******************/
-#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
-#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
-#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
-#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
-
-/******************  Bit definition for NVIC_PRI2 register  *******************/
-#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
-#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
-#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
-#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
-
-/******************  Bit definition for NVIC_PRI3 register  *******************/
-#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
-#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
-#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
-#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
-
-/******************  Bit definition for NVIC_PRI4 register  *******************/
-#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
-#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
-#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
-#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
-
-/******************  Bit definition for NVIC_PRI5 register  *******************/
-#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
-#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
-#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
-#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
-
-/******************  Bit definition for NVIC_PRI6 register  *******************/
-#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
-#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
-#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
-#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
-
-/******************  Bit definition for NVIC_PRI7 register  *******************/
-#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
-#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
-#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
-#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
-
-/******************  Bit definition for SCB_CPUID register  *******************/
-#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
-#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
-#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
-#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
-#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
-
-/*******************  Bit definition for SCB_ICSR register  *******************/
-#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
-#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
-#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
-#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
-#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
-#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
-#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
-#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
-
-/*******************  Bit definition for SCB_VTOR register  *******************/
-#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
-#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
-
-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
-#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
-#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
-#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
-
-#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
-#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
-
-/* prority group configuration */
-#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
-#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/*******************  Bit definition for SCB_SCR register  ********************/
-#define  SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)               /*!< Sleep on exit bit */
-#define  SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)               /*!< Sleep deep bit */
-#define  SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)               /*!< Wake up from WFE */
-
-/********************  Bit definition for SCB_CCR register  *******************/
-#define  SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define  SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define  SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)            /*!< Trap for unaligned access */
-#define  SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)            /*!< Trap on Divide by 0 */
-#define  SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)            /*!< Handlers running at priority -1 and -2 */
-#define  SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/*******************  Bit definition for SCB_SHPR register ********************/
-#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/******************  Bit definition for SCB_SHCSR register  *******************/
-#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
-#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
-#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
-#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
-#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
-#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
-#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
-#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
-#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
-#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
-#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
-#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
-#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
-#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
-
-/*******************  Bit definition for SCB_CFSR register  *******************/
-/*!< MFSR */
-#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
-#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
-#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
-#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
-#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
-#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
-#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
-#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
-#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
-#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
-#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
-#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
-#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
-#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/*******************  Bit definition for SCB_HFSR register  *******************/
-#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
-#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
-
-/*******************  Bit definition for SCB_DFSR register  *******************/
-#define  SCB_DFSR_HALTED                     ((uint32_t)0x00000001)               /*!< Halt request flag */
-#define  SCB_DFSR_BKPT                       ((uint32_t)0x00000002)               /*!< BKPT flag */
-#define  SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)               /*!< Data Watchpoint and Trace (DWT) flag */
-#define  SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)               /*!< Vector catch flag */
-#define  SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)               /*!< External debug request flag */
-
-/*******************  Bit definition for SCB_MMFAR register  ******************/
-#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
-
-/*******************  Bit definition for SCB_BFAR register  *******************/
-#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
-
-/*******************  Bit definition for SCB_afsr register  *******************/
-#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOF) || \
-                                        ((INSTANCE) == GPIOG) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-                                         
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3) || \
-                                                 ((INSTANCE) == UART4)  || \
-                                                 ((INSTANCE) == UART5))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3) || \
-                                          ((INSTANCE) == UART4)  || \
-                                          ((INSTANCE) == UART5)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3) || \
-                                    ((INSTANCE) == UART4)  || \
-                                    ((INSTANCE) == UART5))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3) || \
-                                                     ((INSTANCE) == UART4)  || \
-                                                     ((INSTANCE) == UART5)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-
-/****************************** LCD Instances ********************************/
-#define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L152xE_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,247 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *            - Configuration section that allows to select:
-  *              - The STM32L1xx device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx
-  * @{
-  */
-    
-#ifndef __STM32L1XX_H
-#define __STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-/* Uncomment the line below according to the target STM32L device used in your 
-   application 
-  */
-
-#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \
-    !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \
-    !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \
-    !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE)
-  /* #define STM32L100xB  */   /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */
-  /* #define STM32L100xBA */   /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */
-  /* #define STM32L100xC  */   /*!< STM32L100RC Devices */
-  /* #define STM32L151xB  */   /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
-  /* #define STM32L151xBA */   /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ 
-  /* #define STM32L151xC  */   /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
-  /* #define STM32L151xCA */   /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
-  /* #define STM32L151xD  */   /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
-  /* #define STM32L151xE  */   /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
-  /* #define STM32L152xB  */   /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
-  /* #define STM32L152xBA */   /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
-  /* #define STM32L152xC  */   /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
-  /* #define STM32L152xCA */   /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
-  /* #define STM32L152xD  */   /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */  
-#define STM32L152xE            /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
-  /* #define STM32L162xC  */   /*!< STM32L162RC and STM32L162VC */
-  /* #define STM32L162xCA */   /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
-  /* #define STM32L162xD  */   /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
-  /* #define STM32L162xE  */   /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-  
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V2.0.0
-  */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32L1xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32L100xB)
-  #include "stm32l100xb.h"
-#elif defined(STM32L100xBA)
-  #include "stm32l100xba.h"
-#elif defined(STM32L100xC)
-  #include "stm32l100xc.h"
-#elif defined(STM32L151xB)
-  #include "stm32l151xb.h"
-#elif defined(STM32L151xBA)
-  #include "stm32l151xba.h"
-#elif defined(STM32L151xC)
-  #include "stm32l151xc.h"
-#elif defined(STM32L151xCA)
-  #include "stm32l151xca.h"
-#elif defined(STM32L151xD)
-  #include "stm32l151xd.h"
-#elif defined(STM32L151xE)
-  #include "stm32l151xe.h"
-#elif defined(STM32L152xB)
-  #include "stm32l152xb.h"
-#elif defined(STM32L152xBA)
-  #include "stm32l152xba.h"
-#elif defined(STM32L152xC)
-  #include "stm32l152xc.h"
-#elif defined(STM32L152xCA)
-  #include "stm32l152xca.h"
-#elif defined(STM32L152xD)
-  #include "stm32l152xd.h"
-#elif defined(STM32L152xE)
-  #include "stm32l152xe.h"
-#elif defined(STM32L162xC)
-  #include "stm32l162xc.h"
-#elif defined(STM32L162xCA)
-  #include "stm32l162xca.h"
-#elif defined(STM32L162xD)
-  #include "stm32l162xd.h"
-#elif defined(STM32L162xE)
-  #include "stm32l162xe.h"
-#else
- #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l1xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L1xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/stm32l1xx_hal_conf.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,291 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   HAL configuration template file. 
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l1xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CONF_H
-#define __STM32L1xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_COMP_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_LCD_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_OPAMP_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)500)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-   
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-   
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */          
-#define  TICK_INT_PRIORITY            ((uint32_t)0x000F)    /*!< tick interrupt priority */            
-#define  USE_RTOS                     0     
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     0
-#define  DATA_CACHE_ENABLE            0
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/*#define USE_FULL_ASSERT    1*/ 
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32l1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-  
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32l1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32l1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32l1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l1xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32l1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32l1xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32l1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32l1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32l1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32l1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */ 
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32l1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l1xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-   
-#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32l1xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */     
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */   
-   
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,604 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.c
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l1xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC        | 3- PLL_HSI
-  *                                    | (external 8 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL        |
-  *                                    | (external 8 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 24                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l1xx.h"
-#include "hal_tick.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM32L152D_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-  
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
-const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t)0x88FFC00C;
-  
-  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xEEFEFFFE;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-    
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-  /* Configure the Cube driver */
-  SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
-  HAL_Init();
-
-  /* Configure the System clock source, PLL Multiplier and Divider factors,
-     AHB/APBx prescalers and Flash settings */
-  SetSysClock();
-  
-  /* Reset the timer to avoid issues after the RAM initialization */
-  TIM_MST_RESET_ON;
-  TIM_MST_RESET_OFF;
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in SystemInit() function before jump to main.
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- +                       SRAM pins assignment                                   +
- +-------------------+--------------------+------------------+------------------+
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD15 <-> FSMC_D1  |--------------------+ 
- +-------------------+
-*/
-
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHBENR   = 0x000080D8;
-  
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A0A;
-  /* Configure PDx pins speed to 40 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 40 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC00F;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 40 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x00000C00;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 40 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*-- FSMC Configuration ------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHBENR    = 0x400080D8;
-
-  /* Configure and enable Bank1_SRAM3 */
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-/*
-  Bank1_SRAM3 is configured as follow:
-
-  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 3;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
-
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-*/
-  
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  // SYSCLK = 24 MHz ((8 MHz * 6) / 2)
-  // USBCLK = 48 MHz (8 MHz * 6) --> USB OK
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 24 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 24 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 24 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
-  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
-  while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/system_stm32l1xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L1XX_H
-#define __SYSTEM_STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L1xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L1xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L1XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/startup_stm32l151xc.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,323 +0,0 @@
-; STM32L151RC Ultra Low Power High-density Devices vector table for MDK ARM_MICRO toolchain
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; Amount of memory (in bytes) allocated for Stack
-; Tailor this value to your application needs
-; <h> Stack Configuration
-;   <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Stack_Size      EQU     0x00000400
-
-                AREA    STACK, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __initial_sp
-                
-Stack_Mem       SPACE   Stack_Size
-__initial_sp    EQU     0x20008000 ; Top of RAM (32 KB)
-
-
-; <h> Heap Configuration
-;   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
-; </h>
-
-Heap_Size       EQU     0x00000200
-
-                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
-                EXPORT  __heap_base
-                EXPORT  __heap_limit
-                
-__heap_base
-Heap_Mem        SPACE   Heap_Size
-__heap_limit    EQU (__initial_sp - Stack_Size)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     AES_IRQHandler            ; AES
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  AES_IRQHandler             [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-AES_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/stm32l151rc.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L151RC: 256KB FLASH + 32KB SRAM
-LR_IROM1 0x08000000 0x40000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x124) (0x8000-0x124)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_MICRO/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/startup_stm32l151xc.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,296 +0,0 @@
-; STM32L151RC Ultra Low Power High-density Devices vector table for MDK ARM_STD toolchain
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-__initial_sp    EQU     0x2008000 ; Top of RAM (32 KB)
-
-                PRESERVE8
-                THUMB
-
-
-; Vector Table Mapped to Address 0 at Reset
-                AREA    RESET, DATA, READONLY
-                EXPORT  __Vectors
-                EXPORT  __Vectors_End
-                EXPORT  __Vectors_Size
-
-__Vectors       DCD     __initial_sp              ; Top of Stack
-                DCD     Reset_Handler             ; Reset Handler
-                DCD     NMI_Handler               ; NMI Handler
-                DCD     HardFault_Handler         ; Hard Fault Handler
-                DCD     MemManage_Handler         ; MPU Fault Handler
-                DCD     BusFault_Handler          ; Bus Fault Handler
-                DCD     UsageFault_Handler        ; Usage Fault Handler
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     SVC_Handler               ; SVCall Handler
-                DCD     DebugMon_Handler          ; Debug Monitor Handler
-                DCD     0                         ; Reserved
-                DCD     PendSV_Handler            ; PendSV Handler
-                DCD     SysTick_Handler           ; SysTick Handler
-
-                ; External Interrupts
-                DCD     WWDG_IRQHandler           ; Window Watchdog
-                DCD     PVD_IRQHandler            ; PVD through EXTI Line detect
-                DCD     TAMPER_STAMP_IRQHandler   ; Tamper and Time Stamp
-                DCD     RTC_WKUP_IRQHandler       ; RTC Wakeup
-                DCD     FLASH_IRQHandler          ; FLASH
-                DCD     RCC_IRQHandler            ; RCC
-                DCD     EXTI0_IRQHandler          ; EXTI Line 0
-                DCD     EXTI1_IRQHandler          ; EXTI Line 1
-                DCD     EXTI2_IRQHandler          ; EXTI Line 2
-                DCD     EXTI3_IRQHandler          ; EXTI Line 3
-                DCD     EXTI4_IRQHandler          ; EXTI Line 4
-                DCD     DMA1_Channel1_IRQHandler  ; DMA1 Channel 1
-                DCD     DMA1_Channel2_IRQHandler  ; DMA1 Channel 2
-                DCD     DMA1_Channel3_IRQHandler  ; DMA1 Channel 3
-                DCD     DMA1_Channel4_IRQHandler  ; DMA1 Channel 4
-                DCD     DMA1_Channel5_IRQHandler  ; DMA1 Channel 5
-                DCD     DMA1_Channel6_IRQHandler  ; DMA1 Channel 6
-                DCD     DMA1_Channel7_IRQHandler  ; DMA1 Channel 7
-                DCD     ADC1_IRQHandler           ; ADC1
-                DCD     USB_HP_IRQHandler         ; USB High Priority
-                DCD     USB_LP_IRQHandler         ; USB Low  Priority
-                DCD     DAC_IRQHandler            ; DAC
-                DCD     COMP_IRQHandler           ; COMP through EXTI Line
-                DCD     EXTI9_5_IRQHandler        ; EXTI Line 9..5
-                DCD     LCD_IRQHandler            ; LCD
-                DCD     TIM9_IRQHandler           ; TIM9
-                DCD     TIM10_IRQHandler          ; TIM10
-                DCD     TIM11_IRQHandler          ; TIM11
-                DCD     TIM2_IRQHandler           ; TIM2
-                DCD     TIM3_IRQHandler           ; TIM3
-                DCD     TIM4_IRQHandler           ; TIM4
-                DCD     I2C1_EV_IRQHandler        ; I2C1 Event
-                DCD     I2C1_ER_IRQHandler        ; I2C1 Error
-                DCD     I2C2_EV_IRQHandler        ; I2C2 Event
-                DCD     I2C2_ER_IRQHandler        ; I2C2 Error
-                DCD     SPI1_IRQHandler           ; SPI1
-                DCD     SPI2_IRQHandler           ; SPI2
-                DCD     USART1_IRQHandler         ; USART1
-                DCD     USART2_IRQHandler         ; USART2
-                DCD     USART3_IRQHandler         ; USART3
-                DCD     EXTI15_10_IRQHandler      ; EXTI Line 15..10
-                DCD     RTC_Alarm_IRQHandler      ; RTC Alarm through EXTI Line
-                DCD     USB_FS_WKUP_IRQHandler    ; USB FS Wakeup from suspend
-                DCD     TIM6_IRQHandler           ; TIM6
-                DCD     TIM7_IRQHandler           ; TIM7
-                DCD     0                         ; Reserved
-                DCD     TIM5_IRQHandler           ; TIM5
-                DCD     SPI3_IRQHandler           ; SPI3
-                DCD     0                         ; Reserved
-                DCD     0                         ; Reserved
-                DCD     DMA2_Channel1_IRQHandler  ; DMA2 Channel 1
-                DCD     DMA2_Channel2_IRQHandler  ; DMA2 Channel 2
-                DCD     DMA2_Channel3_IRQHandler  ; DMA2 Channel 3
-                DCD     DMA2_Channel4_IRQHandler  ; DMA2 Channel 4
-                DCD     DMA2_Channel5_IRQHandler  ; DMA2 Channel 5
-                DCD     AES_IRQHandler            ; AES
-                DCD     COMP_ACQ_IRQHandler       ; Comparator Channel Acquisition
-                
-__Vectors_End
-
-__Vectors_Size  EQU  __Vectors_End - __Vectors
-
-                AREA    |.text|, CODE, READONLY
-
-; Reset handler
-Reset_Handler    PROC
-                 EXPORT  Reset_Handler             [WEAK]
-     IMPORT  __main
-     IMPORT  SystemInit
-                 LDR     R0, =SystemInit
-                 BLX     R0
-                 LDR     R0, =__main
-                 BX      R0
-                 ENDP
-
-; Dummy Exception Handlers (infinite loops which can be modified)
-
-NMI_Handler     PROC
-                EXPORT  NMI_Handler                [WEAK]
-                B       .
-                ENDP
-HardFault_Handler\
-                PROC
-                EXPORT  HardFault_Handler          [WEAK]
-                B       .
-                ENDP
-MemManage_Handler\
-                PROC
-                EXPORT  MemManage_Handler          [WEAK]
-                B       .
-                ENDP
-BusFault_Handler\
-                PROC
-                EXPORT  BusFault_Handler           [WEAK]
-                B       .
-                ENDP
-UsageFault_Handler\
-                PROC
-                EXPORT  UsageFault_Handler         [WEAK]
-                B       .
-                ENDP
-SVC_Handler     PROC
-                EXPORT  SVC_Handler                [WEAK]
-                B       .
-                ENDP
-DebugMon_Handler\
-                PROC
-                EXPORT  DebugMon_Handler           [WEAK]
-                B       .
-                ENDP
-PendSV_Handler  PROC
-                EXPORT  PendSV_Handler             [WEAK]
-                B       .
-                ENDP
-SysTick_Handler PROC
-                EXPORT  SysTick_Handler            [WEAK]
-                B       .
-                ENDP
-
-Default_Handler PROC
-
-                EXPORT  WWDG_IRQHandler            [WEAK]
-                EXPORT  PVD_IRQHandler             [WEAK]
-                EXPORT  TAMPER_STAMP_IRQHandler    [WEAK]
-                EXPORT  RTC_WKUP_IRQHandler        [WEAK]
-                EXPORT  FLASH_IRQHandler           [WEAK]
-                EXPORT  RCC_IRQHandler             [WEAK]
-                EXPORT  EXTI0_IRQHandler           [WEAK]
-                EXPORT  EXTI1_IRQHandler           [WEAK]
-                EXPORT  EXTI2_IRQHandler           [WEAK]
-                EXPORT  EXTI3_IRQHandler           [WEAK]
-                EXPORT  EXTI4_IRQHandler           [WEAK]
-                EXPORT  DMA1_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel5_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel6_IRQHandler   [WEAK]
-                EXPORT  DMA1_Channel7_IRQHandler   [WEAK]
-                EXPORT  ADC1_IRQHandler            [WEAK]
-                EXPORT  USB_HP_IRQHandler          [WEAK]
-                EXPORT  USB_LP_IRQHandler          [WEAK]
-                EXPORT  DAC_IRQHandler             [WEAK]
-                EXPORT  COMP_IRQHandler            [WEAK]
-                EXPORT  EXTI9_5_IRQHandler         [WEAK]
-                EXPORT  LCD_IRQHandler             [WEAK]
-                EXPORT  TIM9_IRQHandler            [WEAK]
-                EXPORT  TIM10_IRQHandler           [WEAK]
-                EXPORT  TIM11_IRQHandler           [WEAK]
-                EXPORT  TIM2_IRQHandler            [WEAK]
-                EXPORT  TIM3_IRQHandler            [WEAK]
-                EXPORT  TIM4_IRQHandler            [WEAK]
-                EXPORT  I2C1_EV_IRQHandler         [WEAK]
-                EXPORT  I2C1_ER_IRQHandler         [WEAK]
-                EXPORT  I2C2_EV_IRQHandler         [WEAK]
-                EXPORT  I2C2_ER_IRQHandler         [WEAK]
-                EXPORT  SPI1_IRQHandler            [WEAK]
-                EXPORT  SPI2_IRQHandler            [WEAK]
-                EXPORT  USART1_IRQHandler          [WEAK]
-                EXPORT  USART2_IRQHandler          [WEAK]
-                EXPORT  USART3_IRQHandler          [WEAK]
-                EXPORT  EXTI15_10_IRQHandler       [WEAK]
-                EXPORT  RTC_Alarm_IRQHandler       [WEAK]
-                EXPORT  USB_FS_WKUP_IRQHandler     [WEAK]
-                EXPORT  TIM6_IRQHandler            [WEAK]
-                EXPORT  TIM7_IRQHandler            [WEAK]
-                EXPORT  TIM5_IRQHandler            [WEAK]
-                EXPORT  SPI3_IRQHandler            [WEAK]
-                EXPORT  DMA2_Channel1_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel2_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel3_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel4_IRQHandler   [WEAK]
-                EXPORT  DMA2_Channel5_IRQHandler   [WEAK]
-                EXPORT  AES_IRQHandler             [WEAK]
-                EXPORT  COMP_ACQ_IRQHandler        [WEAK]
-
-WWDG_IRQHandler
-PVD_IRQHandler
-TAMPER_STAMP_IRQHandler
-RTC_WKUP_IRQHandler
-FLASH_IRQHandler
-RCC_IRQHandler
-EXTI0_IRQHandler
-EXTI1_IRQHandler
-EXTI2_IRQHandler
-EXTI3_IRQHandler
-EXTI4_IRQHandler
-DMA1_Channel1_IRQHandler
-DMA1_Channel2_IRQHandler
-DMA1_Channel3_IRQHandler
-DMA1_Channel4_IRQHandler
-DMA1_Channel5_IRQHandler
-DMA1_Channel6_IRQHandler
-DMA1_Channel7_IRQHandler
-ADC1_IRQHandler
-USB_HP_IRQHandler
-USB_LP_IRQHandler
-DAC_IRQHandler
-COMP_IRQHandler
-EXTI9_5_IRQHandler
-LCD_IRQHandler
-TIM9_IRQHandler
-TIM10_IRQHandler
-TIM11_IRQHandler
-TIM2_IRQHandler
-TIM3_IRQHandler
-TIM4_IRQHandler
-I2C1_EV_IRQHandler
-I2C1_ER_IRQHandler
-I2C2_EV_IRQHandler
-I2C2_ER_IRQHandler
-SPI1_IRQHandler
-SPI2_IRQHandler
-USART1_IRQHandler
-USART2_IRQHandler
-USART3_IRQHandler
-EXTI15_10_IRQHandler
-RTC_Alarm_IRQHandler
-USB_FS_WKUP_IRQHandler
-TIM6_IRQHandler
-TIM7_IRQHandler
-TIM5_IRQHandler
-SPI3_IRQHandler
-DMA2_Channel1_IRQHandler
-DMA2_Channel2_IRQHandler
-DMA2_Channel3_IRQHandler
-DMA2_Channel4_IRQHandler
-DMA2_Channel5_IRQHandler
-AES_IRQHandler
-COMP_ACQ_IRQHandler
-
-                B       .
-
-                ENDP
-
-                ALIGN
-                END

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/stm32l151rc.sct	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,45 +0,0 @@
-; Scatter-Loading Description File
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-; Copyright (c) 2015, STMicroelectronics
-; All rights reserved.
-;
-; Redistribution and use in source and binary forms, with or without
-; modification, are permitted provided that the following conditions are met:
-;
-; 1. Redistributions of source code must retain the above copyright notice,
-;     this list of conditions and the following disclaimer.
-; 2. Redistributions in binary form must reproduce the above copyright notice,
-;    this list of conditions and the following disclaimer in the documentation
-;    and/or other materials provided with the distribution.
-; 3. Neither the name of STMicroelectronics nor the names of its contributors
-;    may be used to endorse or promote products derived from this software
-;    without specific prior written permission.
-;
-; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-; FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-; DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-; SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-; CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-; OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-; OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
-
-; STM32L151RC: 256KB FLASH + 32KB SRAM
-LR_IROM1 0x08000000 0x40000  {    ; load region size_region
-
-  ER_IROM1 0x08000000 0x40000  {  ; load address = execution address
-   *.o (RESET, +First)
-   *(InRoot$$Sections)
-   .ANY (+RO)
-  }
-
-  ; 73 vectors = 292 bytes (0x124) to be reserved in RAM
-  RW_IRAM1 (0x20000000+0x124) (0x8000-0x124)  {  ; RW data
-   .ANY (+RW +ZI)
-  }
-
-}
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_ARM_STD/sys.cpp	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,56 +0,0 @@
-/* mbed Microcontroller Library - stackheap
- * Setup a fixed single stack/heap memory model, 
- * between the top of the RW/ZI region and the stackpointer
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 
- *******************************************************************************
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif 
-
-#include <rt_misc.h>
-#include <stdint.h>
-
-extern char Image$$RW_IRAM1$$ZI$$Limit[];
-
-extern __value_in_regs struct __initial_stackheap __user_setup_stackheap(uint32_t R0, uint32_t R1, uint32_t R2, uint32_t R3) {
-    uint32_t zi_limit = (uint32_t)Image$$RW_IRAM1$$ZI$$Limit;
-    uint32_t sp_limit = __current_sp();
-
-    zi_limit = (zi_limit + 7) & ~0x7;    // ensure zi_limit is 8-byte aligned
-
-    struct __initial_stackheap r;
-    r.heap_base = zi_limit;
-    r.heap_limit = sp_limit;
-    return r;
-}
-
-#ifdef __cplusplus
-}
-#endif 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_GCC_ARM/STM32L151XC.ld	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,157 +0,0 @@
-/* Linker script to configure memory regions. */
-
-MEMORY
-{
-  /* 256KB FLASH, 32KB RAM, Reserve up till 0x13C. There are 0x73 vectors = 292
-   * bytes (0x124) in RAM. But all GCC scripts seem to require BootRAM @0x138
-   */
-  FLASH (rx) : ORIGIN = 0x08000000, LENGTH = 256k
-  RAM (rwx) : ORIGIN = 0x2000013C, LENGTH = 0x8000-0x13C
-}
-
-/* Linker script to place sections and symbol values. Should be used together
- * with other linker script that defines memory regions FLASH and RAM.
- * It references following symbols, which must be defined in code:
- *   Reset_Handler : Entry of reset handler
- *
- * It defines following symbols, which code can use without definition:
- *   __exidx_start
- *   __exidx_end
- *   __etext
- *   __data_start__
- *   __preinit_array_start
- *   __preinit_array_end
- *   __init_array_start
- *   __init_array_end
- *   __fini_array_start
- *   __fini_array_end
- *   __data_end__
- *   __bss_start__
- *   __bss_end__
- *   __end__
- *   end
- *   __HeapLimit
- *   __StackLimit
- *   __StackTop
- *   __stack
- *   _estack
- */
-ENTRY(Reset_Handler)
-
-SECTIONS
-{
-    .text :
-    {
-        KEEP(*(.isr_vector))
-        *(.text*)
-        KEEP(*(.init))
-        KEEP(*(.fini))
-
-        /* .ctors */
-        *crtbegin.o(.ctors)
-        *crtbegin?.o(.ctors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors)
-        *(SORT(.ctors.*))
-        *(.ctors)
-
-        /* .dtors */
-        *crtbegin.o(.dtors)
-        *crtbegin?.o(.dtors)
-        *(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors)
-        *(SORT(.dtors.*))
-        *(.dtors)
-
-        *(.rodata*)
-
-        KEEP(*(.eh_frame*))
-    } > FLASH
-
-    .ARM.extab : 
-    {
-        *(.ARM.extab* .gnu.linkonce.armextab.*)
-    } > FLASH
-
-    __exidx_start = .;
-    .ARM.exidx :
-    {
-        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
-    } > FLASH
-    __exidx_end = .;
-
-    __etext = .;
-    _sidata = .;
-
-    .data : AT (__etext)
-    {
-        __data_start__ = .;
-        _sdata = .;
-        *(vtable)
-        *(.data*)
-
-        . = ALIGN(4);
-        /* preinit data */
-        PROVIDE_HIDDEN (__preinit_array_start = .);
-        KEEP(*(.preinit_array))
-        PROVIDE_HIDDEN (__preinit_array_end = .);
-
-        . = ALIGN(4);
-        /* init data */
-        PROVIDE_HIDDEN (__init_array_start = .);
-        KEEP(*(SORT(.init_array.*)))
-        KEEP(*(.init_array))
-        PROVIDE_HIDDEN (__init_array_end = .);
-
-
-        . = ALIGN(4);
-        /* finit data */
-        PROVIDE_HIDDEN (__fini_array_start = .);
-        KEEP(*(SORT(.fini_array.*)))
-        KEEP(*(.fini_array))
-        PROVIDE_HIDDEN (__fini_array_end = .);
-
-        KEEP(*(.jcr*))
-        . = ALIGN(4);
-        /* All data end */
-        __data_end__ = .;
-        _edata = .;
-
-    } > RAM
-
-    .bss :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        _sbss = .;
-        *(.bss*)
-        *(COMMON)
-        . = ALIGN(4);
-        __bss_end__ = .;
-        _ebss = .;
-    } > RAM
-
-    .heap (COPY):
-    {
-        __end__ = .;
-        end = __end__;
-        *(.heap*)
-        __HeapLimit = .;
-    } > RAM
-
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (COPY):
-    {
-        *(.stack*)
-    } > RAM
-
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(RAM) + LENGTH(RAM);
-    _estack = __StackTop;
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    PROVIDE(__stack = __StackTop);
-
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/TOOLCHAIN_GCC_ARM/startup_stm32l151xc.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,418 +0,0 @@
-/**
-  ******************************************************************************
-  * @file      startup_stm32l151xc.s
-  * @author    MCD Application Team
-  * @version   V2.0.0
-  * @date      5-September-2014
-  * @brief     STM32L151XC Devices vector table for 
-  *            Atollic toolchain.
-  *            This module performs:
-  *                - Set the initial SP
-  *                - Set the initial PC == Reset_Handler,
-  *                - Set the vector table entries with the exceptions ISR address
-  *                - Configure the clock system
-  *                - Branches to main in the C library (which eventually
-  *                  calls main()).
-  *            After Reset the Cortex-M3 processor is in Thread mode,
-  *            priority is Privileged, and the Stack is set to Main.
-  ******************************************************************************
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-  .syntax unified
-  .cpu cortex-m3
-  .fpu softvfp
-  .thumb
-
-.global g_pfnVectors
-.global Default_Handler
-
-/* start address for the initialization values of the .data section.
-defined in linker script */
-.word _sidata
-/* start address for the .data section. defined in linker script */
-.word _sdata
-/* end address for the .data section. defined in linker script */
-.word _edata
-/* start address for the .bss section. defined in linker script */
-.word _sbss
-/* end address for the .bss section. defined in linker script */
-.word _ebss
-
-.equ  BootRAM, 0xF108F85F
-/**
- * @brief  This is the code that gets called when the processor first
- *          starts execution following a reset event. Only the absolutely
- *          necessary set is performed, after which the application
- *          supplied main() routine is called.
- * @param  None
- * @retval : None
-*/
-
-  .section .text.Reset_Handler
-  .weak Reset_Handler
-  .type Reset_Handler, %function
-Reset_Handler:
-
-/* Copy the data segment initializers from flash to SRAM */
-  movs r1, #0
-  b LoopCopyDataInit
-
-CopyDataInit:
-  ldr r3, =_sidata
-  ldr r3, [r3, r1]
-  str r3, [r0, r1]
-  adds r1, r1, #4
-
-LoopCopyDataInit:
-  ldr r0, =_sdata
-  ldr r3, =_edata
-  adds r2, r0, r1
-  cmp r2, r3
-  bcc CopyDataInit
-  ldr r2, =_sbss
-  b LoopFillZerobss
-/* Zero fill the bss segment. */
-FillZerobss:
-  movs r3, #0
-  str r3, [r2], #4
-
-LoopFillZerobss:
-  ldr r3, = _ebss
-  cmp r2, r3
-  bcc FillZerobss
-
-/* Call the clock system intitialization function.*/
-    bl  SystemInit
-/* Call static constructors */
-    bl __libc_init_array
-/* Call the application's entry point.*/
-  bl main
-  bx lr
-.size Reset_Handler, .-Reset_Handler
-
-/**
- * @brief  This is the code that gets called when the processor receives an
- *         unexpected interrupt.  This simply enters an infinite loop, preserving
- *         the system state for examination by a debugger.
- *
- * @param  None
- * @retval : None
-*/
-    .section .text.Default_Handler,"ax",%progbits
-Default_Handler:
-Infinite_Loop:
-  b Infinite_Loop
-  .size Default_Handler, .-Default_Handler
-/******************************************************************************
-*
-* The minimal vector table for a Cortex M3.  Note that the proper constructs
-* must be placed on this to ensure that it ends up at physical address
-* 0x0000.0000.
-*
-******************************************************************************/
-   .section .isr_vector,"a",%progbits
-  .type g_pfnVectors, %object
-  .size g_pfnVectors, .-g_pfnVectors
-
-
-g_pfnVectors:
-  .word _estack
-  .word Reset_Handler
-  .word NMI_Handler
-  .word HardFault_Handler
-  .word MemManage_Handler
-  .word BusFault_Handler
-  .word UsageFault_Handler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word SVC_Handler
-  .word DebugMon_Handler
-  .word 0
-  .word PendSV_Handler
-  .word SysTick_Handler
-  .word WWDG_IRQHandler
-  .word PVD_IRQHandler
-  .word TAMPER_STAMP_IRQHandler
-  .word RTC_WKUP_IRQHandler
-  .word FLASH_IRQHandler
-  .word RCC_IRQHandler
-  .word EXTI0_IRQHandler
-  .word EXTI1_IRQHandler
-  .word EXTI2_IRQHandler
-  .word EXTI3_IRQHandler
-  .word EXTI4_IRQHandler
-  .word DMA1_Channel1_IRQHandler
-  .word DMA1_Channel2_IRQHandler
-  .word DMA1_Channel3_IRQHandler
-  .word DMA1_Channel4_IRQHandler
-  .word DMA1_Channel5_IRQHandler
-  .word DMA1_Channel6_IRQHandler
-  .word DMA1_Channel7_IRQHandler
-  .word ADC1_IRQHandler
-  .word USB_HP_IRQHandler
-  .word USB_LP_IRQHandler
-  .word DAC_IRQHandler
-  .word COMP_IRQHandler
-  .word EXTI9_5_IRQHandler
-  .word 0  
-  .word TIM9_IRQHandler
-  .word TIM10_IRQHandler
-  .word TIM11_IRQHandler
-  .word TIM2_IRQHandler
-  .word TIM3_IRQHandler
-  .word TIM4_IRQHandler
-  .word I2C1_EV_IRQHandler
-  .word I2C1_ER_IRQHandler
-  .word I2C2_EV_IRQHandler
-  .word I2C2_ER_IRQHandler
-  .word SPI1_IRQHandler
-  .word SPI2_IRQHandler
-  .word USART1_IRQHandler
-  .word USART2_IRQHandler
-  .word USART3_IRQHandler
-  .word EXTI15_10_IRQHandler
-  .word RTC_Alarm_IRQHandler
-  .word USB_FS_WKUP_IRQHandler
-  .word TIM6_IRQHandler
-  .word TIM7_IRQHandler
-  .word 0
-  .word TIM5_IRQHandler
-  .word SPI3_IRQHandler
-  .word 0
-  .word 0
-  .word DMA2_Channel1_IRQHandler
-  .word DMA2_Channel2_IRQHandler
-  .word DMA2_Channel3_IRQHandler
-  .word DMA2_Channel4_IRQHandler
-  .word DMA2_Channel5_IRQHandler
-  .word 0
-  .word COMP_ACQ_IRQHandler
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word 0
-  .word BootRAM          /* @0x108. This is for boot in RAM mode for 
-                            STM32L151XC devices. */
-
-/*******************************************************************************
-*
-* Provide weak aliases for each Exception handler to the Default_Handler.
-* As they are weak aliases, any function with the same name will override
-* this definition.
-*
-*******************************************************************************/
-
-  .weak NMI_Handler
-  .thumb_set NMI_Handler,Default_Handler
-
-  .weak HardFault_Handler
-  .thumb_set HardFault_Handler,Default_Handler
-
-  .weak MemManage_Handler
-  .thumb_set MemManage_Handler,Default_Handler
-
-  .weak BusFault_Handler
-  .thumb_set BusFault_Handler,Default_Handler
-
-  .weak UsageFault_Handler
-  .thumb_set UsageFault_Handler,Default_Handler
-
-  .weak SVC_Handler
-  .thumb_set SVC_Handler,Default_Handler
-
-  .weak DebugMon_Handler
-  .thumb_set DebugMon_Handler,Default_Handler
-
-  .weak PendSV_Handler
-  .thumb_set PendSV_Handler,Default_Handler
-
-  .weak SysTick_Handler
-  .thumb_set SysTick_Handler,Default_Handler
-
-  .weak WWDG_IRQHandler
-  .thumb_set WWDG_IRQHandler,Default_Handler
-
-  .weak PVD_IRQHandler
-  .thumb_set PVD_IRQHandler,Default_Handler
-
-  .weak TAMPER_STAMP_IRQHandler
-  .thumb_set TAMPER_STAMP_IRQHandler,Default_Handler
-
-  .weak RTC_WKUP_IRQHandler
-  .thumb_set RTC_WKUP_IRQHandler,Default_Handler
-
-  .weak FLASH_IRQHandler
-  .thumb_set FLASH_IRQHandler,Default_Handler
-
-  .weak RCC_IRQHandler
-  .thumb_set RCC_IRQHandler,Default_Handler
-
-  .weak EXTI0_IRQHandler
-  .thumb_set EXTI0_IRQHandler,Default_Handler
-
-  .weak EXTI1_IRQHandler
-  .thumb_set EXTI1_IRQHandler,Default_Handler
-
-  .weak EXTI2_IRQHandler
-  .thumb_set EXTI2_IRQHandler,Default_Handler
-
-  .weak EXTI3_IRQHandler
-  .thumb_set EXTI3_IRQHandler,Default_Handler
-
-  .weak EXTI4_IRQHandler
-  .thumb_set EXTI4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel1_IRQHandler
-  .thumb_set DMA1_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel2_IRQHandler
-  .thumb_set DMA1_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel3_IRQHandler
-  .thumb_set DMA1_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel4_IRQHandler
-  .thumb_set DMA1_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel5_IRQHandler
-  .thumb_set DMA1_Channel5_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel6_IRQHandler
-  .thumb_set DMA1_Channel6_IRQHandler,Default_Handler
-
-  .weak DMA1_Channel7_IRQHandler
-  .thumb_set DMA1_Channel7_IRQHandler,Default_Handler
-
-  .weak ADC1_IRQHandler
-  .thumb_set ADC1_IRQHandler,Default_Handler
-
-  .weak USB_HP_IRQHandler
-  .thumb_set USB_HP_IRQHandler,Default_Handler
-
-  .weak USB_LP_IRQHandler
-  .thumb_set USB_LP_IRQHandler,Default_Handler
-
-  .weak DAC_IRQHandler
-  .thumb_set DAC_IRQHandler,Default_Handler
-
-  .weak COMP_IRQHandler
-  .thumb_set COMP_IRQHandler,Default_Handler
-
-  .weak EXTI9_5_IRQHandler
-  .thumb_set EXTI9_5_IRQHandler,Default_Handler
-
-  .weak TIM9_IRQHandler
-  .thumb_set TIM9_IRQHandler,Default_Handler
-
-  .weak TIM10_IRQHandler
-  .thumb_set TIM10_IRQHandler,Default_Handler
-
-  .weak TIM11_IRQHandler
-  .thumb_set TIM11_IRQHandler,Default_Handler
-
-  .weak TIM2_IRQHandler
-  .thumb_set TIM2_IRQHandler,Default_Handler
-
-  .weak TIM3_IRQHandler
-  .thumb_set TIM3_IRQHandler,Default_Handler
-
-  .weak TIM4_IRQHandler
-  .thumb_set TIM4_IRQHandler,Default_Handler
-
-  .weak I2C1_EV_IRQHandler
-  .thumb_set I2C1_EV_IRQHandler,Default_Handler
-
-  .weak I2C1_ER_IRQHandler
-  .thumb_set I2C1_ER_IRQHandler,Default_Handler
-
-  .weak I2C2_EV_IRQHandler
-  .thumb_set I2C2_EV_IRQHandler,Default_Handler
-
-  .weak I2C2_ER_IRQHandler
-  .thumb_set I2C2_ER_IRQHandler,Default_Handler
-
-  .weak SPI1_IRQHandler
-  .thumb_set SPI1_IRQHandler,Default_Handler
-
-  .weak SPI2_IRQHandler
-  .thumb_set SPI2_IRQHandler,Default_Handler
-
-  .weak USART1_IRQHandler
-  .thumb_set USART1_IRQHandler,Default_Handler
-
-  .weak USART2_IRQHandler
-  .thumb_set USART2_IRQHandler,Default_Handler
-
-  .weak USART3_IRQHandler
-  .thumb_set USART3_IRQHandler,Default_Handler
-
-  .weak EXTI15_10_IRQHandler
-  .thumb_set EXTI15_10_IRQHandler,Default_Handler
-
-  .weak RTC_Alarm_IRQHandler
-  .thumb_set RTC_Alarm_IRQHandler,Default_Handler
-
-  .weak USB_FS_WKUP_IRQHandler
-  .thumb_set USB_FS_WKUP_IRQHandler,Default_Handler
-
-  .weak TIM6_IRQHandler
-  .thumb_set TIM6_IRQHandler,Default_Handler
-
-  .weak TIM7_IRQHandler
-  .thumb_set TIM7_IRQHandler,Default_Handler
-
-  .weak TIM5_IRQHandler
-  .thumb_set TIM5_IRQHandler,Default_Handler
-  
-  .weak SPI3_IRQHandler
-  .thumb_set SPI3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel1_IRQHandler
-  .thumb_set DMA2_Channel1_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel2_IRQHandler
-  .thumb_set DMA2_Channel2_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel3_IRQHandler
-  .thumb_set DMA2_Channel3_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel4_IRQHandler
-  .thumb_set DMA2_Channel4_IRQHandler,Default_Handler
-
-  .weak DMA2_Channel5_IRQHandler
-  .thumb_set DMA2_Channel5_IRQHandler,Default_Handler
-
-  .weak COMP_ACQ_IRQHandler
-   .thumb_set COMP_ACQ_IRQHandler,Default_Handler
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,38 +0,0 @@
-/* mbed Microcontroller Library
- * A generic CMSIS include header
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_CMSIS_H
-#define MBED_CMSIS_H
-
-#include "stm32l1xx.h"
-#include "cmsis_nvic.h"
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis_nvic.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-#include "cmsis_nvic.h"
-
-#define NVIC_RAM_VECTOR_ADDRESS   (0x20000000)  // Vectors positioned at start of RAM
-#define NVIC_FLASH_VECTOR_ADDRESS (0x08000000)  // Initial vector position in flash
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) {
-    uint32_t *vectors = (uint32_t *)SCB->VTOR;
-    uint32_t i;
-
-    // Copy and switch to dynamic vectors if the first time called
-    if (SCB->VTOR == NVIC_FLASH_VECTOR_ADDRESS) {
-        uint32_t *old_vectors = vectors;
-        vectors = (uint32_t*)NVIC_RAM_VECTOR_ADDRESS;
-        for (i=0; i<NVIC_NUM_VECTORS; i++) {
-            vectors[i] = old_vectors[i];
-        }
-        SCB->VTOR = (uint32_t)NVIC_RAM_VECTOR_ADDRESS;
-    }
-    vectors[IRQn + NVIC_USER_IRQ_OFFSET] = vector;
-}
-
-uint32_t NVIC_GetVector(IRQn_Type IRQn) {
-    uint32_t *vectors = (uint32_t*)SCB->VTOR;
-    return vectors[IRQn + NVIC_USER_IRQ_OFFSET];
-}

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/cmsis_nvic.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,55 +0,0 @@
-/* mbed Microcontroller Library
- * CMSIS-style functionality to support dynamic vectors
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */ 
-
-#ifndef MBED_CMSIS_NVIC_H
-#define MBED_CMSIS_NVIC_H
-
-// STM32L151RC
-// CORE: 16 vectors = 64 bytes from 0x00 to 0x3F
-// MCU Peripherals: 57 vectors = 228 bytes from 0x40 to 0x123
-// Total: 73 vectors = 292 bytes (0x124) to be reserved in RAM
-#define NVIC_NUM_VECTORS      73
-#define NVIC_USER_IRQ_OFFSET  16
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector);
-uint32_t NVIC_GetVector(IRQn_Type IRQn);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/hal_tick.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.c
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-#include "hal_tick.h"
-
-TIM_HandleTypeDef TimMasterHandle;
-uint32_t PreviousVal = 0;
-
-void us_ticker_irq_handler(void);
-
-void timer_irq_handler(void) {
-    // Channel 1 for mbed timeout
-    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC1) == SET) {
-        us_ticker_irq_handler();
-    }
-
-    // Channel 2 for HAL tick
-    if (__HAL_TIM_GET_ITSTATUS(&TimMasterHandle, TIM_IT_CC2) == SET) {
-        __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC2);
-        uint32_t val = __HAL_TIM_GetCounter(&TimMasterHandle);
-        if ((val - PreviousVal) >= HAL_TICK_DELAY) {
-            // Increment HAL variable
-            HAL_IncTick();
-            // Prepare next interrupt
-            __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, val + HAL_TICK_DELAY);
-            PreviousVal = val;
-#if 0 // For DEBUG only
-            HAL_GPIO_TogglePin(GPIOB, GPIO_PIN_6);
-#endif
-        }
-    }
-}
-
-// Reconfigure the HAL tick using a standard timer instead of systick.
-HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority) {
-    // Enable timer clock
-    TIM_MST_RCC;
-
-    // Reset timer
-    TIM_MST_RESET_ON;
-    TIM_MST_RESET_OFF;
-
-    // Update the SystemCoreClock variable
-    SystemCoreClockUpdate();
-
-    // Configure time base
-    TimMasterHandle.Instance = TIM_MST;
-    TimMasterHandle.Init.Period            = 0xFFFFFFFF;
-    TimMasterHandle.Init.Prescaler         = (uint32_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
-    TimMasterHandle.Init.ClockDivision     = 0;
-    TimMasterHandle.Init.CounterMode       = TIM_COUNTERMODE_UP;
-    HAL_TIM_OC_Init(&TimMasterHandle);
-
-    NVIC_SetVector(TIM_MST_IRQ, (uint32_t)timer_irq_handler);
-    NVIC_EnableIRQ(TIM_MST_IRQ);
-
-    // Channel 1 for mbed timeout
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_1);
-
-    // Channel 2 for HAL tick
-    HAL_TIM_OC_Start(&TimMasterHandle, TIM_CHANNEL_2);
-    PreviousVal = __HAL_TIM_GetCounter(&TimMasterHandle);
-    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_2, PreviousVal + HAL_TICK_DELAY);
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
-
-#if 0 // For DEBUG only
-    __GPIOB_CLK_ENABLE();
-    GPIO_InitTypeDef GPIO_InitStruct;
-    GPIO_InitStruct.Pin = GPIO_PIN_6;
-    GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
-    GPIO_InitStruct.Pull = GPIO_PULLUP;
-    GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
-    HAL_GPIO_Init(GPIOB, &GPIO_InitStruct);
-#endif
-
-    return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */    
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/hal_tick.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,60 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    hal_tick.h
-  * @author  MCD Application Team
-  * @brief   Initialization of HAL tick
-  ******************************************************************************  
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-#ifndef __HAL_TICK_H
-#define __HAL_TICK_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#include "stm32l1xx.h"
-#include "cmsis_nvic.h"
-   
-#define TIM_MST      TIM5
-#define TIM_MST_IRQ  TIM5_IRQn
-#define TIM_MST_RCC  __TIM5_CLK_ENABLE()
-
-#define TIM_MST_RESET_ON   __TIM5_FORCE_RESET()
-#define TIM_MST_RESET_OFF  __TIM5_RELEASE_RESET()
-
-#define HAL_TICK_DELAY (1000) // 1 ms
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif // __HAL_TICK_H
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l151xc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,5701 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l151xc.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer Header File. 
-  *          This file contains all the peripheral register's definitions, bits 
-  *          definitions and memory mapping for STM32L1xx devices.            
-  *            
-  *          This file contains:
-  *           - Data structures and the address mapping for all peripherals
-  *           - Peripheral's registers declarations and bits definition
-  *           - Macros to access peripheral’s registers hardware
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l151xc
-  * @{
-  */
-    
-#ifndef __STM32L151xC_H
-#define __STM32L151xC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-  
-
-  /** @addtogroup Configuration_section_for_CMSIS
-  * @{
-  */
-/**
-  * @brief Configuration of the Cortex-M3 Processor and Core Peripherals 
- */
-#define __CM3_REV                 0x200 /*!< Cortex-M3 Revision r2p0                  */
-#define __MPU_PRESENT             1     /*!< STM32L1xx provides MPU                          */
-#define __NVIC_PRIO_BITS          4     /*!< STM32L1xx uses 4 Bits for the Priority Levels    */
-#define __Vendor_SysTickConfig    0     /*!< Set to 1 if different SysTick Config is used */
- 
-/**
-  * @}
-  */
-   
-/** @addtogroup Peripheral_interrupt_number_definition
-  * @{
-  */
-
-/**
- * @brief STM32L1xx Interrupt Number Definition, according to the selected device 
- *        in @ref Library_configuration_section 
- */
-
- /*!< Interrupt Number Definition */
-typedef enum
-{
-/******  Cortex-M3 Processor Exceptions Numbers ******************************************************/
-  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                */
-  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M3 Memory Management Interrupt                 */
-  BusFault_IRQn               = -11,    /*!< 5 Cortex-M3 Bus Fault Interrupt                         */
-  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M3 Usage Fault Interrupt                       */
-  SVC_IRQn                    = -5,     /*!< 11 Cortex-M3 SV Call Interrupt                          */
-  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M3 Debug Monitor Interrupt                    */
-  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M3 Pend SV Interrupt                          */
-  SysTick_IRQn                = -1,     /*!< 15 Cortex-M3 System Tick Interrupt                      */
-
-/******  STM32L specific Interrupt Numbers ***********************************************************/
-  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                               */
-  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt               */
-  TAMPER_STAMP_IRQn           = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line   */
-  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup Timer through EXTI Line Interrupt            */
-  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                  */
-  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                    */
-  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                    */
-  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                    */
-  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                    */
-  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                    */
-  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                    */
-  DMA1_Channel1_IRQn          = 11,     /*!< DMA1 Channel 1 global Interrupt                         */
-  DMA1_Channel2_IRQn          = 12,     /*!< DMA1 Channel 2 global Interrupt                         */
-  DMA1_Channel3_IRQn          = 13,     /*!< DMA1 Channel 3 global Interrupt                         */
-  DMA1_Channel4_IRQn          = 14,     /*!< DMA1 Channel 4 global Interrupt                         */
-  DMA1_Channel5_IRQn          = 15,     /*!< DMA1 Channel 5 global Interrupt                         */
-  DMA1_Channel6_IRQn          = 16,     /*!< DMA1 Channel 6 global Interrupt                         */
-  DMA1_Channel7_IRQn          = 17,     /*!< DMA1 Channel 7 global Interrupt                         */
-  ADC1_IRQn                   = 18,     /*!< ADC1 global Interrupt                                   */
-  USB_HP_IRQn                 = 19,     /*!< USB High Priority Interrupt                             */
-  USB_LP_IRQn                 = 20,     /*!< USB Low Priority Interrupt                              */
-  DAC_IRQn                    = 21,     /*!< DAC Interrupt                                           */
-  COMP_IRQn                   = 22,     /*!< Comparator through EXTI Line Interrupt                  */
-  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                           */
-  TIM9_IRQn                   = 25,     /*!< TIM9 global Interrupt                                   */
-  TIM10_IRQn                  = 26,     /*!< TIM10 global Interrupt                                  */
-  TIM11_IRQn                  = 27,     /*!< TIM11 global Interrupt                                  */
-  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                   */
-  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                   */
-  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                   */
-  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                    */
-  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                    */
-  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                    */
-  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                    */
-  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                   */
-  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                   */
-  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                 */
-  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                 */
-  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                 */
-  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                         */
-  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm through EXTI Line Interrupt                   */
-  USB_FS_WKUP_IRQn            = 42,     /*!< USB FS WakeUp from suspend through EXTI Line Interrupt  */
-  TIM6_IRQn                   = 43,     /*!< TIM6 global Interrupt                                   */
-  TIM7_IRQn                   = 44,     /*!< TIM7 global Interrupt                                   */
-  TIM5_IRQn                   = 46,     /*!< TIM5 global Interrupt                                   */
-  SPI3_IRQn                   = 47,     /*!< SPI3 global Interrupt                                   */
-  DMA2_Channel1_IRQn          = 50,     /*!< DMA2 Channel 1 global Interrupt                         */
-  DMA2_Channel2_IRQn          = 51,     /*!< DMA2 Channel 2 global Interrupt                         */
-  DMA2_Channel3_IRQn          = 52,     /*!< DMA2 Channel 3 global Interrupt                         */
-  DMA2_Channel4_IRQn          = 53,     /*!< DMA2 Channel 4 global Interrupt                         */
-  DMA2_Channel5_IRQn          = 54,     /*!< DMA2 Channel 5 global Interrupt                         */
-  COMP_ACQ_IRQn               = 56      /*!< Comparator Channel Acquisition global Interrupt         */
-} IRQn_Type;
-
-/**
-  * @}
-  */
-
-#include "core_cm3.h"
-#include "system_stm32l1xx.h"
-#include <stdint.h>
-
-/** @addtogroup Peripheral_registers_structures
-  * @{
-  */   
-
-/** 
-  * @brief Analog to Digital Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t SR;           /*!< ADC status register,                         Address offset: 0x00 */
-  __IO uint32_t CR1;          /*!< ADC control register 1,                      Address offset: 0x04 */
-  __IO uint32_t CR2;          /*!< ADC control register 2,                      Address offset: 0x08 */
-  __IO uint32_t SMPR1;        /*!< ADC sample time register 1,                  Address offset: 0x0C */
-  __IO uint32_t SMPR2;        /*!< ADC sample time register 2,                  Address offset: 0x10 */
-  __IO uint32_t SMPR3;        /*!< ADC sample time register 3,                  Address offset: 0x14 */
-  __IO uint32_t JOFR1;        /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
-  __IO uint32_t JOFR2;        /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
-  __IO uint32_t JOFR3;        /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
-  __IO uint32_t JOFR4;        /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
-  __IO uint32_t HTR;          /*!< ADC watchdog higher threshold register,      Address offset: 0x28 */
-  __IO uint32_t LTR;          /*!< ADC watchdog lower threshold register,       Address offset: 0x2C */
-  __IO uint32_t SQR1;         /*!< ADC regular sequence register 1,             Address offset: 0x30 */
-  __IO uint32_t SQR2;         /*!< ADC regular sequence register 2,             Address offset: 0x34 */
-  __IO uint32_t SQR3;         /*!< ADC regular sequence register 3,             Address offset: 0x38 */
-  __IO uint32_t SQR4;         /*!< ADC regular sequence register 4,             Address offset: 0x3C */
-  __IO uint32_t SQR5;         /*!< ADC regular sequence register 5,             Address offset: 0x40 */
-  __IO uint32_t JSQR;         /*!< ADC injected sequence register,              Address offset: 0x44 */
-  __IO uint32_t JDR1;         /*!< ADC injected data register 1,                Address offset: 0x48 */
-  __IO uint32_t JDR2;         /*!< ADC injected data register 2,                Address offset: 0x4C */
-  __IO uint32_t JDR3;         /*!< ADC injected data register 3,                Address offset: 0x50 */
-  __IO uint32_t JDR4;         /*!< ADC injected data register 4,                Address offset: 0x54 */
-  __IO uint32_t DR;           /*!< ADC regular data register,                   Address offset: 0x58 */
-  uint32_t RESERVED;          /*!< Reserved,                                    Address offset: 0x5C */
-} ADC_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< ADC common status register,                  Address offset: ADC1 base address + 0x300 */
-  __IO uint32_t CCR;          /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-} ADC_Common_TypeDef;
-
-/** 
-  * @brief Comparator 
-  */
-
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< COMP comparator control and status register, Address offset: 0x00 */
-} COMP_TypeDef;
-
-/** 
-  * @brief CRC calculation unit
-  */
-
-typedef struct
-{
-  __IO uint32_t DR;           /*!< CRC Data register,                           Address offset: 0x00 */
-  __IO uint32_t  IDR;          /*!< CRC Independent data register,               Address offset: 0x04 */
-  __IO uint32_t CR;           /*!< CRC Control register,                        Address offset: 0x08 */ 
-} CRC_TypeDef;
-
-/** 
-  * @brief Digital to Analog Converter
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;           /*!< DAC control register,                                     Address offset: 0x00 */
-  __IO uint32_t SWTRIGR;      /*!< DAC software trigger register,                            Address offset: 0x04 */
-  __IO uint32_t DHR12R1;      /*!< DAC channel1 12-bit right-aligned data holding register,  Address offset: 0x08 */
-  __IO uint32_t DHR12L1;      /*!< DAC channel1 12-bit left aligned data holding register,   Address offset: 0x0C */
-  __IO uint32_t DHR8R1;       /*!< DAC channel1 8-bit right aligned data holding register,   Address offset: 0x10 */
-  __IO uint32_t DHR12R2;      /*!< DAC channel2 12-bit right aligned data holding register,  Address offset: 0x14 */
-  __IO uint32_t DHR12L2;      /*!< DAC channel2 12-bit left aligned data holding register,   Address offset: 0x18 */
-  __IO uint32_t DHR8R2;       /*!< DAC channel2 8-bit right-aligned data holding register,   Address offset: 0x1C */
-  __IO uint32_t DHR12RD;      /*!< Dual DAC 12-bit right-aligned data holding register,      Address offset: 0x20 */
-  __IO uint32_t DHR12LD;      /*!< DUAL DAC 12-bit left aligned data holding register,       Address offset: 0x24 */
-  __IO uint32_t DHR8RD;       /*!< DUAL DAC 8-bit right aligned data holding register,       Address offset: 0x28 */
-  __IO uint32_t DOR1;         /*!< DAC channel1 data output register,                        Address offset: 0x2C */
-  __IO uint32_t DOR2;         /*!< DAC channel2 data output register,                        Address offset: 0x30 */
-  __IO uint32_t SR;           /*!< DAC status register,                                      Address offset: 0x34 */
-} DAC_TypeDef;
-
-/** 
-  * @brief Debug MCU
-  */
-
-typedef struct
-{
-  __IO uint32_t IDCODE;       /*!< MCU device ID code,                          Address offset: 0x00 */
-  __IO uint32_t CR;           /*!< Debug MCU configuration register,            Address offset: 0x04 */
-  __IO uint32_t APB1FZ;       /*!< Debug MCU APB1 freeze register,              Address offset: 0x08 */
-  __IO uint32_t APB2FZ;       /*!< Debug MCU APB2 freeze register,              Address offset: 0x0C */
-}DBGMCU_TypeDef;
-
-/** 
-  * @brief DMA Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t CCR;          /*!< DMA channel x configuration register        */
-  __IO uint32_t CNDTR;        /*!< DMA channel x number of data register       */
-  __IO uint32_t CPAR;         /*!< DMA channel x peripheral address register   */
-  __IO uint32_t CMAR;         /*!< DMA channel x memory address register       */
-} DMA_Channel_TypeDef;
-
-typedef struct
-{
-  __IO uint32_t ISR;          /*!< DMA interrupt status register,               Address offset: 0x00 */
-  __IO uint32_t IFCR;         /*!< DMA interrupt flag clear register,           Address offset: 0x04 */
-} DMA_TypeDef;
-
-/** 
-  * @brief External Interrupt/Event Controller
-  */
-
-typedef struct
-{
-  __IO uint32_t IMR;          /*!<EXTI Interrupt mask register,                 Address offset: 0x00 */
-  __IO uint32_t EMR;          /*!<EXTI Event mask register,                     Address offset: 0x04 */
-  __IO uint32_t RTSR;         /*!<EXTI Rising trigger selection register ,      Address offset: 0x08 */
-  __IO uint32_t FTSR;         /*!<EXTI Falling trigger selection register,      Address offset: 0x0C */
-  __IO uint32_t SWIER;        /*!<EXTI Software interrupt event register,       Address offset: 0x10 */
-  __IO uint32_t PR;           /*!<EXTI Pending register,                        Address offset: 0x14 */
-} EXTI_TypeDef;
-
-/** 
-  * @brief FLASH Registers
-  */
-typedef struct
-{
-  __IO uint32_t ACR;          /*!< Access control register,                     Address offset: 0x00 */
-  __IO uint32_t PECR;         /*!< Program/erase control register,              Address offset: 0x04 */
-  __IO uint32_t PDKEYR;       /*!< Power down key register,                     Address offset: 0x08 */
-  __IO uint32_t PEKEYR;       /*!< Program/erase key register,                  Address offset: 0x0c */
-  __IO uint32_t PRGKEYR;      /*!< Program memory key register,                 Address offset: 0x10 */
-  __IO uint32_t OPTKEYR;      /*!< Option byte key register,                    Address offset: 0x14 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x18 */
-  __IO uint32_t OBR;          /*!< Option byte register,                        Address offset: 0x1c */
-  __IO uint32_t WRPR1;        /*!< Write protection register 1,                 Address offset: 0x20 */
-  uint32_t   RESERVED[23];    /*!< Reserved,                                    Address offset: 0x24 */
-  __IO uint32_t WRPR2;        /*!< Write protection register 2,                 Address offset: 0x80 */
-} FLASH_TypeDef;
-
-/** 
-  * @brief Option Bytes Registers
-  */
-typedef struct
-{
-  __IO uint32_t RDP;              /*!< Read protection register,               Address offset: 0x00 */
-  __IO uint32_t USER;             /*!< user register,                          Address offset: 0x04 */
-  __IO uint32_t WRP01;            /*!< write protection register 0 1,          Address offset: 0x08 */
-  __IO uint32_t WRP23;            /*!< write protection register 2 3,          Address offset: 0x0C */
-  __IO uint32_t WRP45;            /*!< write protection register 4 5,          Address offset: 0x10 */
-  __IO uint32_t WRP67;            /*!< write protection register 6 7,          Address offset: 0x14 */
-} OB_TypeDef;
-
-/** 
-  * @brief Operational Amplifier (OPAMP)
-  */
-typedef struct
-{
-  __IO uint32_t CSR;          /*!< OPAMP control/status register,                     Address offset: 0x00 */
-  __IO uint32_t OTR;          /*!< OPAMP offset trimming register for normal mode,    Address offset: 0x04 */ 
-  __IO uint32_t LPOTR;        /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
-} OPAMP_TypeDef;
-
-/** 
-  * @brief General Purpose IO
-  */
-
-typedef struct
-{
-  __IO uint32_t MODER;        /*!< GPIO port mode register,                     Address offset: 0x00      */
-  __IO uint32_t OTYPER;       /*!< GPIO port output type register,              Address offset: 0x04      */
-  __IO uint32_t OSPEEDR;      /*!< GPIO port output speed register,             Address offset: 0x08      */
-  __IO uint32_t PUPDR;        /*!< GPIO port pull-up/pull-down register,        Address offset: 0x0C      */
-  __IO uint32_t IDR;          /*!< GPIO port input data register,               Address offset: 0x10      */
-  __IO uint32_t ODR;          /*!< GPIO port output data register,              Address offset: 0x14      */
-  __IO uint32_t BSRR;         /*!< GPIO port bit set/reset registerBSRR,        Address offset: 0x18      */
-  __IO uint32_t LCKR;         /*!< GPIO port configuration lock register,       Address offset: 0x1C      */
-  __IO uint32_t AFR[2];       /*!< GPIO alternate function register,            Address offset: 0x20-0x24 */
-  __IO uint32_t BRR;          /*!< GPIO bit reset register,                     Address offset: 0x28      */
-} GPIO_TypeDef;
-
-/** 
-  * @brief SysTem Configuration
-  */
-
-typedef struct
-{
-  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
-  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
-  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
-} SYSCFG_TypeDef;
-
-/** 
-  * @brief Inter-integrated Circuit Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< I2C Control register 1,                      Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< I2C Control register 2,                      Address offset: 0x04 */
-  __IO uint32_t OAR1;         /*!< I2C Own address register 1,                  Address offset: 0x08 */
-  __IO uint32_t OAR2;         /*!< I2C Own address register 2,                  Address offset: 0x0C */
-  __IO uint32_t DR;           /*!< I2C Data register,                           Address offset: 0x10 */
-  __IO uint32_t SR1;          /*!< I2C Status register 1,                       Address offset: 0x14 */
-  __IO uint32_t SR2;          /*!< I2C Status register 2,                       Address offset: 0x18 */
-  __IO uint32_t CCR;          /*!< I2C Clock control register,                  Address offset: 0x1C */
-  __IO uint32_t TRISE;        /*!< I2C TRISE register,                          Address offset: 0x20 */
-} I2C_TypeDef;
-
-/** 
-  * @brief Independent WATCHDOG
-  */
-
-typedef struct
-{
-  __IO uint32_t KR;           /*!< Key register,                                Address offset: 0x00 */
-  __IO uint32_t PR;           /*!< Prescaler register,                          Address offset: 0x04 */
-  __IO uint32_t RLR;          /*!< Reload register,                             Address offset: 0x08 */
-  __IO uint32_t SR;           /*!< Status register,                             Address offset: 0x0C */
-} IWDG_TypeDef;
-
-/** 
-  * @brief Power Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;   /*!< PWR power control register,                          Address offset: 0x00 */
-  __IO uint32_t CSR;  /*!< PWR power control/status register,                   Address offset: 0x04 */
-} PWR_TypeDef;
-
-/** 
-  * @brief Reset and Clock Control
-  */
-
-typedef struct
-{
-  __IO uint32_t CR;            /*!< RCC clock control register,                                   Address offset: 0x00 */
-  __IO uint32_t ICSCR;         /*!< RCC Internal clock sources calibration register,              Address offset: 0x04 */
-  __IO uint32_t CFGR;          /*!< RCC Clock configuration register,                             Address offset: 0x08 */
-  __IO uint32_t CIR;           /*!< RCC Clock interrupt register,                                 Address offset: 0x0C */
-  __IO uint32_t AHBRSTR;       /*!< RCC AHB peripheral reset register,                            Address offset: 0x10 */
-  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                           Address offset: 0x14 */
-  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                           Address offset: 0x18 */
-  __IO uint32_t AHBENR;        /*!< RCC AHB peripheral clock enable register,                     Address offset: 0x1C */
-  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                    Address offset: 0x20 */
-  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                    Address offset: 0x24 */
-  __IO uint32_t AHBLPENR;      /*!< RCC AHB peripheral clock enable in low power mode register,   Address offset: 0x28 */
-  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register,  Address offset: 0x2C */
-  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register,  Address offset: 0x30 */
-  __IO uint32_t CSR;           /*!< RCC Control/status register,                                  Address offset: 0x34 */
-} RCC_TypeDef;
-
-/** 
-  * @brief Routing Interface 
-  */
-
-typedef struct
-{
-  __IO uint32_t ICR;        /*!< RI input capture register,                     Address offset: 0x00 */
-  __IO uint32_t ASCR1;      /*!< RI analog switches control register,       Address offset: 0x04 */
-  __IO uint32_t ASCR2;      /*!< RI analog switch control register 2,        Address offset: 0x08 */
-  __IO uint32_t HYSCR1;     /*!< RI hysteresis control register,                Address offset: 0x0C */
-  __IO uint32_t HYSCR2;     /*!< RI Hysteresis control register,               Address offset: 0x10 */
-  __IO uint32_t HYSCR3;     /*!< RI Hysteresis control register,               Address offset: 0x14 */
-  uint32_t RESERVED1;       /*!< Reserved, 0x18                                                                  */
-  __IO uint32_t ASMR1;      /*!< RI Analog switch mode register 1,         Address offset: 0x1C */
-  __IO uint32_t CMR1;       /*!< RI Channel mask register 1,                   Address offset: 0x20 */
-  __IO uint32_t CICR1;      /*!< RI Channel Iden for capture register 1,  Address offset: 0x24 */
-  __IO uint32_t ASMR2;      /*!< RI Analog switch mode register 2,         Address offset: 0x28 */
-  __IO uint32_t CMR2;       /*!< RI Channel mask register 2,                   Address offset: 0x2C */
-  __IO uint32_t CICR2;      /*!< RI Channel Iden for capture register 2,  Address offset: 0x30 */
-  __IO uint32_t ASMR3;      /*!< RI Analog switch mode register 3,         Address offset: 0x34 */
-  __IO uint32_t CMR3;       /*!< RI Channel mask register 3,                   Address offset: 0x38 */
-  __IO uint32_t CICR3;      /*!< RI Channel Iden for capture register 3,  Address offset: 0x3C */
-} RI_TypeDef;
-
-/** 
-  * @brief Real-Time Clock
-  */
-typedef struct
-{
-  __IO uint32_t TR;         /*!< RTC time register,                                         Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< RTC date register,                                         Address offset: 0x04 */
-  __IO uint32_t CR;         /*!< RTC control register,                                      Address offset: 0x08 */                                                                                            
-  __IO uint32_t ISR;        /*!< RTC initialization and status register,                    Address offset: 0x0C */
-  __IO uint32_t PRER;       /*!< RTC prescaler register,                                    Address offset: 0x10 */
-  __IO uint32_t WUTR;       /*!< RTC wakeup timer register,                                 Address offset: 0x14 */
-  __IO uint32_t CALIBR;     /*!< RTC calibration register,                                  Address offset: 0x18 */
-  __IO uint32_t ALRMAR;     /*!< RTC alarm A register,                                      Address offset: 0x1C */
-  __IO uint32_t ALRMBR;     /*!< RTC alarm B register,                                      Address offset: 0x20 */
-  __IO uint32_t WPR;        /*!< RTC write protection register,                             Address offset: 0x24 */
-  __IO uint32_t SSR;        /*!< RTC sub second register,                                   Address offset: 0x28 */
-  __IO uint32_t SHIFTR;     /*!< RTC shift control register,                                Address offset: 0x2C */
-  __IO uint32_t TSTR;       /*!< RTC time stamp time register,                              Address offset: 0x30 */
-  __IO uint32_t TSDR;       /*!< RTC time stamp date register,                              Address offset: 0x34 */
-  __IO uint32_t TSSSR;      /*!< RTC time-stamp sub second register,                        Address offset: 0x38 */
-  __IO uint32_t CALR;       /*!< RRTC calibration register,                                 Address offset: 0x3C */
-  __IO uint32_t TAFCR;      /*!< RTC tamper and alternate function configuration register,  Address offset: 0x40 */
-  __IO uint32_t ALRMASSR;   /*!< RTC alarm A sub second register,                           Address offset: 0x44 */
-  __IO uint32_t ALRMBSSR;   /*!< RTC alarm B sub second register,                           Address offset: 0x48 */
-  uint32_t RESERVED7;       /*!< Reserved, 0x4C                                                                  */
-  __IO uint32_t BKP0R;      /*!< RTC backup register 0,                                     Address offset: 0x50 */
-  __IO uint32_t BKP1R;      /*!< RTC backup register 1,                                     Address offset: 0x54 */
-  __IO uint32_t BKP2R;      /*!< RTC backup register 2,                                     Address offset: 0x58 */
-  __IO uint32_t BKP3R;      /*!< RTC backup register 3,                                     Address offset: 0x5C */
-  __IO uint32_t BKP4R;      /*!< RTC backup register 4,                                     Address offset: 0x60 */
-  __IO uint32_t BKP5R;      /*!< RTC backup register 5,                                     Address offset: 0x64 */
-  __IO uint32_t BKP6R;      /*!< RTC backup register 6,                                     Address offset: 0x68 */
-  __IO uint32_t BKP7R;      /*!< RTC backup register 7,                                     Address offset: 0x6C */
-  __IO uint32_t BKP8R;      /*!< RTC backup register 8,                                     Address offset: 0x70 */
-  __IO uint32_t BKP9R;      /*!< RTC backup register 9,                                     Address offset: 0x74 */
-  __IO uint32_t BKP10R;     /*!< RTC backup register 10,                                    Address offset: 0x78 */
-  __IO uint32_t BKP11R;     /*!< RTC backup register 11,                                    Address offset: 0x7C */
-  __IO uint32_t BKP12R;     /*!< RTC backup register 12,                                    Address offset: 0x80 */
-  __IO uint32_t BKP13R;     /*!< RTC backup register 13,                                    Address offset: 0x84 */
-  __IO uint32_t BKP14R;     /*!< RTC backup register 14,                                    Address offset: 0x88 */
-  __IO uint32_t BKP15R;     /*!< RTC backup register 15,                                    Address offset: 0x8C */
-  __IO uint32_t BKP16R;     /*!< RTC backup register 16,                                    Address offset: 0x90 */
-  __IO uint32_t BKP17R;     /*!< RTC backup register 17,                                    Address offset: 0x94 */
-  __IO uint32_t BKP18R;     /*!< RTC backup register 18,                                    Address offset: 0x98 */
-  __IO uint32_t BKP19R;     /*!< RTC backup register 19,                                    Address offset: 0x9C */
-  __IO uint32_t BKP20R;     /*!< RTC backup register 20,                                    Address offset: 0xA0 */
-  __IO uint32_t BKP21R;     /*!< RTC backup register 21,                                    Address offset: 0xA4 */
-  __IO uint32_t BKP22R;     /*!< RTC backup register 22,                                    Address offset: 0xA8 */
-  __IO uint32_t BKP23R;     /*!< RTC backup register 23,                                    Address offset: 0xAC */
-  __IO uint32_t BKP24R;     /*!< RTC backup register 24,                                    Address offset: 0xB0 */
-  __IO uint32_t BKP25R;     /*!< RTC backup register 25,                                    Address offset: 0xB4 */
-  __IO uint32_t BKP26R;     /*!< RTC backup register 26,                                    Address offset: 0xB8 */
-  __IO uint32_t BKP27R;     /*!< RTC backup register 27,                                    Address offset: 0xBC */
-  __IO uint32_t BKP28R;     /*!< RTC backup register 28,                                    Address offset: 0xC0 */
-  __IO uint32_t BKP29R;     /*!< RTC backup register 29,                                    Address offset: 0xC4 */
-  __IO uint32_t BKP30R;     /*!< RTC backup register 30,                                    Address offset: 0xC8 */
-  __IO uint32_t BKP31R;     /*!< RTC backup register 31,                                    Address offset: 0xCC */
-} RTC_TypeDef;
-
-/** 
-  * @brief Serial Peripheral Interface
-  */
-
-typedef struct
-{
-  __IO uint32_t CR1;        /*!< SPI Control register 1 (not used in I2S mode),      Address offset: 0x00 */
-  __IO uint32_t CR2;        /*!< SPI Control register 2,                             Address offset: 0x04 */
-  __IO uint32_t SR;         /*!< SPI Status register,                                Address offset: 0x08 */
-  __IO uint32_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
-  __IO uint32_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
-  __IO uint32_t RXCRCR;     /*!< SPI Rx CRC register (not used in I2S mode),         Address offset: 0x14 */
-  __IO uint32_t TXCRCR;     /*!< SPI Tx CRC register (not used in I2S mode),         Address offset: 0x18 */
-  __IO uint32_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
-  __IO uint32_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
-} SPI_TypeDef;
-
-/** 
-  * @brief TIM
-  */
-typedef struct
-{
-  __IO uint32_t CR1;          /*!< TIM control register 1,              Address offset: 0x00 */
-  __IO uint32_t CR2;          /*!< TIM control register 2,              Address offset: 0x04 */
-  __IO uint32_t SMCR;         /*!< TIM slave Mode Control register,     Address offset: 0x08 */
-  __IO uint32_t DIER;         /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
-  __IO uint32_t SR;           /*!< TIM status register,                 Address offset: 0x10 */
-  __IO uint32_t EGR;          /*!< TIM event generation register,       Address offset: 0x14 */
-  __IO uint32_t CCMR1;        /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
-  __IO uint32_t CCMR2;        /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
-  __IO uint32_t CCER;         /*!< TIM capture/compare enable register, Address offset: 0x20 */
-  __IO uint32_t CNT;          /*!< TIM counter register,                Address offset: 0x24 */
-  __IO uint32_t PSC;          /*!< TIM prescaler register,              Address offset: 0x28 */
-  __IO uint32_t ARR;          /*!< TIM auto-reload register,            Address offset: 0x2C */
-  uint32_t      RESERVED12;   /*!< Reserved, 0x30                                            */    
-  __IO uint32_t CCR1;         /*!< TIM capture/compare register 1,      Address offset: 0x34 */    
-  __IO uint32_t CCR2;         /*!< TIM capture/compare register 2,      Address offset: 0x38 */    
-  __IO uint32_t CCR3;         /*!< TIM capture/compare register 3,      Address offset: 0x3C */
-  __IO uint32_t CCR4;         /*!< TIM capture/compare register 4,      Address offset: 0x40 */
-  uint32_t      RESERVED17;   /*!< Reserved, 0x44                                            */ 
-  __IO uint32_t DCR;          /*!< TIM DMA control register,            Address offset: 0x48 */
-  __IO uint32_t DMAR;         /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
-  __IO uint32_t OR;           /*!< TIM option register,                 Address offset: 0x50 */
-} TIM_TypeDef;
-/** 
-  * @brief Universal Synchronous Asynchronous Receiver Transmitter
-  */
- 
-typedef struct
-{
-  __IO uint32_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
-  __IO uint32_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
-  __IO uint32_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
-  __IO uint32_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
-  __IO uint32_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
-  __IO uint32_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
-  __IO uint32_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
-} USART_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-  
-typedef struct
-{
-  __IO uint16_t EP0R;            /*!< USB Endpoint 0 register,                Address offset: 0x00 */ 
-  __IO uint16_t RESERVED0;       /*!< Reserved */     
-  __IO uint16_t EP1R;            /*!< USB Endpoint 1 register,                Address offset: 0x04 */
-  __IO uint16_t RESERVED1;       /*!< Reserved */       
-  __IO uint16_t EP2R;            /*!< USB Endpoint 2 register,                Address offset: 0x08 */
-  __IO uint16_t RESERVED2;       /*!< Reserved */       
-  __IO uint16_t EP3R;            /*!< USB Endpoint 3 register,                Address offset: 0x0C */ 
-  __IO uint16_t RESERVED3;       /*!< Reserved */       
-  __IO uint16_t EP4R;            /*!< USB Endpoint 4 register,                Address offset: 0x10 */
-  __IO uint16_t RESERVED4;       /*!< Reserved */       
-  __IO uint16_t EP5R;            /*!< USB Endpoint 5 register,                Address offset: 0x14 */
-  __IO uint16_t RESERVED5;       /*!< Reserved */       
-  __IO uint16_t EP6R;            /*!< USB Endpoint 6 register,                Address offset: 0x18 */
-  __IO uint16_t RESERVED6;       /*!< Reserved */       
-  __IO uint16_t EP7R;            /*!< USB Endpoint 7 register,                Address offset: 0x1C */
-  __IO uint16_t RESERVED7[17];   /*!< Reserved */     
-  __IO uint16_t CNTR;            /*!< Control register,                       Address offset: 0x40 */
-  __IO uint16_t RESERVED8;       /*!< Reserved */       
-  __IO uint16_t ISTR;            /*!< Interrupt status register,              Address offset: 0x44 */
-  __IO uint16_t RESERVED9;       /*!< Reserved */       
-  __IO uint16_t FNR;             /*!< Frame number register,                  Address offset: 0x48 */
-  __IO uint16_t RESERVEDA;       /*!< Reserved */       
-  __IO uint16_t DADDR;           /*!< Device address register,                Address offset: 0x4C */
-  __IO uint16_t RESERVEDB;       /*!< Reserved */       
-  __IO uint16_t BTABLE;          /*!< Buffer Table address register,          Address offset: 0x50 */
-  __IO uint16_t RESERVEDC;       /*!< Reserved */       
-} USB_TypeDef;
-
-/** 
-  * @brief Window WATCHDOG
-  */
-typedef struct
-{
-  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
-  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
-  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
-} WWDG_TypeDef;
-
-/** 
-  * @brief Universal Serial Bus Full Speed Device
-  */
-/** 
-  * @}
-  */
-  
-/** @addtogroup Peripheral_memory_map
-  * @{
-  */
-
-#define FLASH_BASE            ((uint32_t)0x08000000)              /*!< FLASH base address in the alias region */
-#define FLASH_EEPROM_BASE     ((uint32_t)(FLASH_BASE + 0x80000))  /*!< FLASH EEPROM base address in the alias region */
-#define SRAM_BASE             ((uint32_t)0x20000000)              /*!< SRAM base address in the alias region */
-#define PERIPH_BASE           ((uint32_t)0x40000000)              /*!< Peripheral base address in the alias region */
-#define SRAM_BB_BASE          ((uint32_t)0x22000000)              /*!< SRAM base address in the bit-band region */
-#define PERIPH_BB_BASE        ((uint32_t)0x42000000)              /*!< Peripheral base address in the bit-band region */
-#define FLASH_END             ((uint32_t)0x0803FFFF)              /*!< Program end FLASH address for Cat3 */
-#define FLASH_EEPROM_END      ((uint32_t)0x08081FFF)              /*!< FLASH EEPROM end address (8KB) */
-
-/*!< Peripheral memory map */
-#define APB1PERIPH_BASE       PERIPH_BASE
-#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
-#define AHBPERIPH_BASE        (PERIPH_BASE + 0x00020000)
-
-/*!< APB1 peripherals */
-#define TIM2_BASE             (APB1PERIPH_BASE + 0x00000000)
-#define TIM3_BASE             (APB1PERIPH_BASE + 0x00000400)
-#define TIM4_BASE             (APB1PERIPH_BASE + 0x00000800)
-#define TIM5_BASE             (APB1PERIPH_BASE + 0x00000C00)
-#define TIM6_BASE             (APB1PERIPH_BASE + 0x00001000)
-#define TIM7_BASE             (APB1PERIPH_BASE + 0x00001400)
-#define RTC_BASE              (APB1PERIPH_BASE + 0x00002800)
-#define WWDG_BASE             (APB1PERIPH_BASE + 0x00002C00)
-#define IWDG_BASE             (APB1PERIPH_BASE + 0x00003000)
-#define SPI2_BASE             (APB1PERIPH_BASE + 0x00003800)
-#define SPI3_BASE             (APB1PERIPH_BASE + 0x00003C00)
-#define USART2_BASE           (APB1PERIPH_BASE + 0x00004400)
-#define USART3_BASE           (APB1PERIPH_BASE + 0x00004800)
-#define I2C1_BASE             (APB1PERIPH_BASE + 0x00005400)
-#define I2C2_BASE             (APB1PERIPH_BASE + 0x00005800)
-
-/* USB device FS */
-#define USB_BASE              (APB1PERIPH_BASE + 0x00005C00) /*!< USB_IP Peripheral Registers base address */
-#define USB_PMAADDR           (APB1PERIPH_BASE + 0x00006000) /*!< USB_IP Packet Memory Area base address */
-
-/* USB device FS SRAM */
-#define PWR_BASE              (APB1PERIPH_BASE + 0x00007000)
-#define DAC_BASE              (APB1PERIPH_BASE + 0x00007400)
-#define COMP_BASE             (APB1PERIPH_BASE + 0x00007C00)
-#define RI_BASE               (APB1PERIPH_BASE + 0x00007C04)
-#define OPAMP_BASE            (APB1PERIPH_BASE + 0x00007C5C)
-
-/*!< APB2 peripherals */
-#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x00000000)
-#define EXTI_BASE             (APB2PERIPH_BASE + 0x00000400)
-#define TIM9_BASE             (APB2PERIPH_BASE + 0x00000800)
-#define TIM10_BASE            (APB2PERIPH_BASE + 0x00000C00)
-#define TIM11_BASE            (APB2PERIPH_BASE + 0x00001000)
-#define ADC1_BASE             (APB2PERIPH_BASE + 0x00002400)
-#define ADC_BASE              (APB2PERIPH_BASE + 0x00002700)
-#define SPI1_BASE             (APB2PERIPH_BASE + 0x00003000)
-#define USART1_BASE           (APB2PERIPH_BASE + 0x00003800)
-
-/*!< AHB peripherals */
-#define GPIOA_BASE            (AHBPERIPH_BASE + 0x00000000)
-#define GPIOB_BASE            (AHBPERIPH_BASE + 0x00000400)
-#define GPIOC_BASE            (AHBPERIPH_BASE + 0x00000800)
-#define GPIOD_BASE            (AHBPERIPH_BASE + 0x00000C00)
-#define GPIOE_BASE            (AHBPERIPH_BASE + 0x00001000)
-#define GPIOH_BASE            (AHBPERIPH_BASE + 0x00001400)
-#define CRC_BASE              (AHBPERIPH_BASE + 0x00003000)
-#define RCC_BASE              (AHBPERIPH_BASE + 0x00003800)
-#define FLASH_R_BASE          (AHBPERIPH_BASE + 0x00003C00) /*!< FLASH registers base address */
-#define OB_BASE               ((uint32_t)0x1FF80000)    /*!< FLASH Option Bytes base address */
-#define DMA1_BASE             (AHBPERIPH_BASE + 0x00006000)
-#define DMA1_Channel1_BASE    (DMA1_BASE + 0x00000008)
-#define DMA1_Channel2_BASE    (DMA1_BASE + 0x0000001C)
-#define DMA1_Channel3_BASE    (DMA1_BASE + 0x00000030)
-#define DMA1_Channel4_BASE    (DMA1_BASE + 0x00000044)
-#define DMA1_Channel5_BASE    (DMA1_BASE + 0x00000058)
-#define DMA1_Channel6_BASE    (DMA1_BASE + 0x0000006C)
-#define DMA1_Channel7_BASE    (DMA1_BASE + 0x00000080)
-#define DMA2_BASE             (AHBPERIPH_BASE + 0x00006400)
-#define DMA2_Channel1_BASE    (DMA2_BASE + 0x00000008)
-#define DMA2_Channel2_BASE    (DMA2_BASE + 0x0000001C)
-#define DMA2_Channel3_BASE    (DMA2_BASE + 0x00000030)
-#define DMA2_Channel4_BASE    (DMA2_BASE + 0x00000044)
-#define DMA2_Channel5_BASE    (DMA2_BASE + 0x00000058)
-#define DBGMCU_BASE           ((uint32_t)0xE0042000)     /*!< Debug MCU registers base address */
-
-/**
-  * @}
-  */
-  
-/** @addtogroup Peripheral_declaration
-  * @{
-  */  
-
-#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
-#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
-#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
-#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
-#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
-#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
-#define RTC                 ((RTC_TypeDef *) RTC_BASE)
-#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
-#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
-#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
-#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
-#define USART2              ((USART_TypeDef *) USART2_BASE)
-#define USART3              ((USART_TypeDef *) USART3_BASE)
-#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
-#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
-/* USB device FS */
-#define USB                   ((USB_TypeDef *) USB_BASE)
-/* USB device FS SRAM */
-#define PWR                 ((PWR_TypeDef *) PWR_BASE)
-#define DAC                 ((DAC_TypeDef *) DAC_BASE)
-#define COMP                ((COMP_TypeDef *) COMP_BASE)
-#define COMP1               ((COMP_TypeDef *) COMP_BASE)
-#define COMP2               ((COMP_TypeDef *) (COMP_BASE + 0x00000001))
-#define RI                  ((RI_TypeDef *) RI_BASE)
-#define OPAMP               ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP1              ((OPAMP_TypeDef *) OPAMP_BASE)
-#define OPAMP2              ((OPAMP_TypeDef *) (OPAMP_BASE + 0x00000001))
-#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
-#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
-#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
-#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
-#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
-#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
-#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
-#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
-#define USART1              ((USART_TypeDef *) USART1_BASE)
-#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
-#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
-#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
-#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
-#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
-#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
-#define CRC                 ((CRC_TypeDef *) CRC_BASE)
-#define RCC                 ((RCC_TypeDef *) RCC_BASE)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define OB                  ((OB_TypeDef *) OB_BASE) 
-#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
-#define DMA1_Channel1       ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
-#define DMA1_Channel2       ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
-#define DMA1_Channel3       ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
-#define DMA1_Channel4       ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
-#define DMA1_Channel5       ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
-#define DMA1_Channel6       ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
-#define DMA1_Channel7       ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
-#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
-#define DMA2_Channel1       ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
-#define DMA2_Channel2       ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
-#define DMA2_Channel3       ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
-#define DMA2_Channel4       ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
-#define DMA2_Channel5       ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
-#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
-
- /**
-  * @}
-  */
-
-/** @addtogroup Exported_constants
-  * @{
-  */
-
-/** @addtogroup Peripheral_Registers_Bits_Definition
-  * @{
-  */
-    
-/******************************************************************************/
-/*                         Peripheral Registers Bits Definition               */
-/******************************************************************************/
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog to Digital Converter (ADC)                     */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for ADC_SR register  ********************/
-#define  ADC_SR_AWD                          ((uint32_t)0x00000001)        /*!< Analog watchdog flag */
-#define  ADC_SR_EOC                          ((uint32_t)0x00000002)        /*!< End of conversion */
-#define  ADC_SR_JEOC                         ((uint32_t)0x00000004)        /*!< Injected channel end of conversion */
-#define  ADC_SR_JSTRT                        ((uint32_t)0x00000008)        /*!< Injected channel Start flag */
-#define  ADC_SR_STRT                         ((uint32_t)0x00000010)        /*!< Regular channel Start flag */
-#define  ADC_SR_OVR                          ((uint32_t)0x00000020)        /*!< Overrun flag */
-#define  ADC_SR_ADONS                        ((uint32_t)0x00000040)        /*!< ADC ON status */
-#define  ADC_SR_RCNR                         ((uint32_t)0x00000100)        /*!< Regular channel not ready flag */
-#define  ADC_SR_JCNR                         ((uint32_t)0x00000200)        /*!< Injected channel not ready flag */
-
-/*******************  Bit definition for ADC_CR1 register  ********************/
-#define  ADC_CR1_AWDCH                       ((uint32_t)0x0000001F)        /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
-#define  ADC_CR1_AWDCH_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_CR1_AWDCH_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_CR1_AWDCH_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_CR1_AWDCH_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_CR1_AWDCH_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_CR1_EOCIE                       ((uint32_t)0x00000020)        /*!< Interrupt enable for EOC */
-#define  ADC_CR1_AWDIE                       ((uint32_t)0x00000040)        /*!< Analog Watchdog interrupt enable */
-#define  ADC_CR1_JEOCIE                      ((uint32_t)0x00000080)        /*!< Interrupt enable for injected channels */
-#define  ADC_CR1_SCAN                        ((uint32_t)0x00000100)        /*!< Scan mode */
-#define  ADC_CR1_AWDSGL                      ((uint32_t)0x00000200)        /*!< Enable the watchdog on a single channel in scan mode */
-#define  ADC_CR1_JAUTO                       ((uint32_t)0x00000400)        /*!< Automatic injected group conversion */
-#define  ADC_CR1_DISCEN                      ((uint32_t)0x00000800)        /*!< Discontinuous mode on regular channels */
-#define  ADC_CR1_JDISCEN                     ((uint32_t)0x00001000)        /*!< Discontinuous mode on injected channels */
-
-#define  ADC_CR1_DISCNUM                     ((uint32_t)0x0000E000)        /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
-#define  ADC_CR1_DISCNUM_0                   ((uint32_t)0x00002000)        /*!< Bit 0 */
-#define  ADC_CR1_DISCNUM_1                   ((uint32_t)0x00004000)        /*!< Bit 1 */
-#define  ADC_CR1_DISCNUM_2                   ((uint32_t)0x00008000)        /*!< Bit 2 */
-
-#define  ADC_CR1_PDD                         ((uint32_t)0x00010000)        /*!< Power Down during Delay phase */
-#define  ADC_CR1_PDI                         ((uint32_t)0x00020000)        /*!< Power Down during Idle phase */
-
-#define  ADC_CR1_JAWDEN                      ((uint32_t)0x00400000)        /*!< Analog watchdog enable on injected channels */
-#define  ADC_CR1_AWDEN                       ((uint32_t)0x00800000)        /*!< Analog watchdog enable on regular channels */
-
-#define  ADC_CR1_RES                         ((uint32_t)0x03000000)        /*!< RES[1:0] bits (Resolution) */
-#define  ADC_CR1_RES_0                       ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_CR1_RES_1                       ((uint32_t)0x02000000)        /*!< Bit 1 */
-
-#define  ADC_CR1_OVRIE                       ((uint32_t)0x04000000)        /*!< Overrun interrupt enable */
-  
-/*******************  Bit definition for ADC_CR2 register  ********************/
-#define  ADC_CR2_ADON                        ((uint32_t)0x00000001)        /*!< A/D Converter ON / OFF */
-#define  ADC_CR2_CONT                        ((uint32_t)0x00000002)        /*!< Continuous Conversion */
-#define  ADC_CR2_CFG                         ((uint32_t)0x00000004)        /*!< ADC Configuration */
-
-#define  ADC_CR2_DELS                        ((uint32_t)0x00000070)        /*!< DELS[2:0] bits (Delay selection) */
-#define  ADC_CR2_DELS_0                      ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  ADC_CR2_DELS_1                      ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  ADC_CR2_DELS_2                      ((uint32_t)0x00000040)        /*!< Bit 2 */
-
-#define  ADC_CR2_DMA                         ((uint32_t)0x00000100)        /*!< Direct Memory access mode */
-#define  ADC_CR2_DDS                         ((uint32_t)0x00000200)        /*!< DMA disable selection (Single ADC) */
-#define  ADC_CR2_EOCS                        ((uint32_t)0x00000400)        /*!< End of conversion selection */
-#define  ADC_CR2_ALIGN                       ((uint32_t)0x00000800)        /*!< Data Alignment */
-
-#define  ADC_CR2_JEXTSEL                     ((uint32_t)0x000F0000)        /*!< JEXTSEL[3:0] bits (External event select for injected group) */
-#define  ADC_CR2_JEXTSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  ADC_CR2_JEXTSEL_2                   ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  ADC_CR2_JEXTSEL_3                   ((uint32_t)0x00080000)        /*!< Bit 3 */
-
-#define  ADC_CR2_JEXTEN                      ((uint32_t)0x00300000)        /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
-#define  ADC_CR2_JEXTEN_0                    ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_CR2_JEXTEN_1                    ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-#define  ADC_CR2_JSWSTART                    ((uint32_t)0x00400000)        /*!< Start Conversion of injected channels */
-
-#define  ADC_CR2_EXTSEL                      ((uint32_t)0x0F000000)        /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
-#define  ADC_CR2_EXTSEL_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTSEL_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_CR2_EXTSEL_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-#define  ADC_CR2_EXTSEL_3                    ((uint32_t)0x08000000)        /*!< Bit 3 */
-
-#define  ADC_CR2_EXTEN                       ((uint32_t)0x30000000)        /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
-#define  ADC_CR2_EXTEN_0                     ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  ADC_CR2_EXTEN_1                     ((uint32_t)0x20000000)        /*!< Bit 1 */
-
-#define  ADC_CR2_SWSTART                     ((uint32_t)0x40000000)        /*!< Start Conversion of regular channels */
-
-/******************  Bit definition for ADC_SMPR1 register  *******************/
-#define  ADC_SMPR1_SMP20                     ((uint32_t)0x00000007)        /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
-#define  ADC_SMPR1_SMP20_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP20_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP20_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP21                     ((uint32_t)0x00000038)        /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
-#define  ADC_SMPR1_SMP21_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP21_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP21_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP22                     ((uint32_t)0x000001C0)        /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
-#define  ADC_SMPR1_SMP22_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP22_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP22_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP23                     ((uint32_t)0x00000E00)        /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
-#define  ADC_SMPR1_SMP23_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP23_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP23_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP24                     ((uint32_t)0x00007000)        /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
-#define  ADC_SMPR1_SMP24_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP24_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP24_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP25                     ((uint32_t)0x00038000)        /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
-#define  ADC_SMPR1_SMP25_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP25_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP25_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP26                     ((uint32_t)0x001C0000)        /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
-#define  ADC_SMPR1_SMP26_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP26_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP26_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP27                     ((uint32_t)0x00E00000)        /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
-#define  ADC_SMPR1_SMP27_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP27_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP27_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP28                     ((uint32_t)0x07000000)        /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
-#define  ADC_SMPR1_SMP28_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP28_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP28_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR1_SMP29                     ((uint32_t)0x38000000)        /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
-#define  ADC_SMPR1_SMP29_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR1_SMP29_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR1_SMP29_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR2 register  *******************/
-#define  ADC_SMPR2_SMP10                     ((uint32_t)0x00000007)        /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
-#define  ADC_SMPR2_SMP10_0                   ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP10_1                   ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP10_2                   ((uint32_t)0x00000004)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP11                     ((uint32_t)0x00000038)        /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
-#define  ADC_SMPR2_SMP11_0                   ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP11_1                   ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP11_2                   ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP12                     ((uint32_t)0x000001C0)        /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
-#define  ADC_SMPR2_SMP12_0                   ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP12_1                   ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP12_2                   ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP13                     ((uint32_t)0x00000E00)        /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
-#define  ADC_SMPR2_SMP13_0                   ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP13_1                   ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP13_2                   ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP14                     ((uint32_t)0x00007000)        /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
-#define  ADC_SMPR2_SMP14_0                   ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP14_1                   ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP14_2                   ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP15                     ((uint32_t)0x00038000)        /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR2_SMP15_0                   ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP15_1                   ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP15_2                   ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP16                     ((uint32_t)0x001C0000)        /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
-#define  ADC_SMPR2_SMP16_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP16_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP16_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP17                     ((uint32_t)0x00E00000)        /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
-#define  ADC_SMPR2_SMP17_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP17_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP17_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP18                     ((uint32_t)0x07000000)        /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
-#define  ADC_SMPR2_SMP18_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP18_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP18_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR2_SMP19                     ((uint32_t)0x38000000)        /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
-#define  ADC_SMPR2_SMP19_0                   ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR2_SMP19_1                   ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR2_SMP19_2                   ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_SMPR3 register  *******************/
-#define  ADC_SMPR3_SMP0                      ((uint32_t)0x00000007)        /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
-#define  ADC_SMPR3_SMP0_0                    ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP0_1                    ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP0_2                    ((uint32_t)0x00000004)        /*!< Bit 2 */
- 
-#define  ADC_SMPR3_SMP1                      ((uint32_t)0x00000038)        /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
-#define  ADC_SMPR3_SMP1_0                    ((uint32_t)0x00000008)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP1_1                    ((uint32_t)0x00000010)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP1_2                    ((uint32_t)0x00000020)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP2                      ((uint32_t)0x000001C0)        /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
-#define  ADC_SMPR3_SMP2_0                    ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP2_1                    ((uint32_t)0x00000080)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP2_2                    ((uint32_t)0x00000100)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP3                      ((uint32_t)0x00000E00)        /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
-#define  ADC_SMPR3_SMP3_0                    ((uint32_t)0x00000200)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP3_1                    ((uint32_t)0x00000400)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP3_2                    ((uint32_t)0x00000800)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP4                      ((uint32_t)0x00007000)        /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
-#define  ADC_SMPR3_SMP4_0                    ((uint32_t)0x00001000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP4_1                    ((uint32_t)0x00002000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP4_2                    ((uint32_t)0x00004000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP5                      ((uint32_t)0x00038000)        /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
-#define  ADC_SMPR3_SMP5_0                    ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP5_1                    ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP5_2                    ((uint32_t)0x00020000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP6                      ((uint32_t)0x001C0000)        /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
-#define  ADC_SMPR3_SMP6_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP6_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP6_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP7                      ((uint32_t)0x00E00000)        /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
-#define  ADC_SMPR3_SMP7_0                    ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP7_1                    ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP7_2                    ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP8                      ((uint32_t)0x07000000)        /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
-#define  ADC_SMPR3_SMP8_0                    ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP8_1                    ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP8_2                    ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-#define  ADC_SMPR3_SMP9                      ((uint32_t)0x38000000)        /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
-#define  ADC_SMPR3_SMP9_0                    ((uint32_t)0x08000000)        /*!< Bit 0 */
-#define  ADC_SMPR3_SMP9_1                    ((uint32_t)0x10000000)        /*!< Bit 1 */
-#define  ADC_SMPR3_SMP9_2                    ((uint32_t)0x20000000)        /*!< Bit 2 */
-
-/******************  Bit definition for ADC_JOFR1 register  *******************/
-#define  ADC_JOFR1_JOFFSET1                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 1 */
-
-/******************  Bit definition for ADC_JOFR2 register  *******************/
-#define  ADC_JOFR2_JOFFSET2                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 2 */
-
-/******************  Bit definition for ADC_JOFR3 register  *******************/
-#define  ADC_JOFR3_JOFFSET3                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 3 */
-
-/******************  Bit definition for ADC_JOFR4 register  *******************/
-#define  ADC_JOFR4_JOFFSET4                  ((uint32_t)0x00000FFF)        /*!< Data offset for injected channel 4 */
-
-/*******************  Bit definition for ADC_HTR register  ********************/
-#define  ADC_HTR_HT                          ((uint32_t)0x00000FFF)        /*!< Analog watchdog high threshold */
-
-/*******************  Bit definition for ADC_LTR register  ********************/
-#define  ADC_LTR_LT                          ((uint32_t)0x00000FFF)         /*!< Analog watchdog low threshold */
-
-/*******************  Bit definition for ADC_SQR1 register  *******************/
-#define  ADC_SQR1_L                          ((uint32_t)0x01F00000)        /*!< L[4:0] bits (Regular channel sequence length) */
-#define  ADC_SQR1_L_0                        ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR1_L_1                        ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR1_L_2                        ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR1_L_3                        ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR1_L_4                        ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ28                       ((uint32_t)0x000F8000)        /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
-#define  ADC_SQR1_SQ28_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ28_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ28_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ28_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ28_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ27                       ((uint32_t)0x00007C00)        /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
-#define  ADC_SQR1_SQ27_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ27_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ27_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ27_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ27_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ26                       ((uint32_t)0x000003E0)        /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
-#define  ADC_SQR1_SQ26_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ26_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ26_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ26_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ26_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR1_SQ25                       ((uint32_t)0x0000001F)        /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
-#define  ADC_SQR1_SQ25_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR1_SQ25_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR1_SQ25_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR1_SQ25_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR1_SQ25_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR2 register  *******************/
-#define  ADC_SQR2_SQ19                       ((uint32_t)0x0000001F)        /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
-#define  ADC_SQR2_SQ19_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ19_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ19_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ19_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ19_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ20                       ((uint32_t)0x000003E0)        /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
-#define  ADC_SQR2_SQ20_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ20_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ20_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ20_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ20_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ21                       ((uint32_t)0x00007C00)        /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
-#define  ADC_SQR2_SQ21_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ21_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ21_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ21_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ21_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ22                       ((uint32_t)0x000F8000)        /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
-#define  ADC_SQR2_SQ22_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ22_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ22_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ22_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ22_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ23                       ((uint32_t)0x01F00000)        /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
-#define  ADC_SQR2_SQ23_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ23_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ23_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ23_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ23_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR2_SQ24                       ((uint32_t)0x3E000000)        /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
-#define  ADC_SQR2_SQ24_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR2_SQ24_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR2_SQ24_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR2_SQ24_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR2_SQ24_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR3 register  *******************/
-#define  ADC_SQR3_SQ13                       ((uint32_t)0x0000001F)        /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
-#define  ADC_SQR3_SQ13_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ13_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ13_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ13_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ13_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ14                       ((uint32_t)0x000003E0)        /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
-#define  ADC_SQR3_SQ14_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ14_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ14_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ14_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ14_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ15                       ((uint32_t)0x00007C00)        /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
-#define  ADC_SQR3_SQ15_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ15_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ15_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ15_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ15_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ16                       ((uint32_t)0x000F8000)        /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
-#define  ADC_SQR3_SQ16_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ16_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ16_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ16_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ16_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ17                       ((uint32_t)0x01F00000)        /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
-#define  ADC_SQR3_SQ17_0                     ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ17_1                     ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ17_2                     ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ17_3                     ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ17_4                     ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR3_SQ18                       ((uint32_t)0x3E000000)        /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
-#define  ADC_SQR3_SQ18_0                     ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR3_SQ18_1                     ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR3_SQ18_2                     ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR3_SQ18_3                     ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR3_SQ18_4                     ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR4 register  *******************/
-#define  ADC_SQR4_SQ7                        ((uint32_t)0x0000001F)        /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
-#define  ADC_SQR4_SQ7_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ7_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ7_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ7_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ7_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ8                        ((uint32_t)0x000003E0)        /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
-#define  ADC_SQR4_SQ8_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ8_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ8_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ8_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ8_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ9                        ((uint32_t)0x00007C00)        /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
-#define  ADC_SQR4_SQ9_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ9_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ9_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ9_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ9_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ10                        ((uint32_t)0x000F8000)        /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
-#define  ADC_SQR4_SQ10_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ10_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ10_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ10_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ10_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ11                        ((uint32_t)0x01F00000)        /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
-#define  ADC_SQR4_SQ11_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ11_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ11_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ11_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ11_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR4_SQ12                        ((uint32_t)0x3E000000)        /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
-#define  ADC_SQR4_SQ12_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR4_SQ12_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR4_SQ12_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR4_SQ12_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR4_SQ12_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-/*******************  Bit definition for ADC_SQR5 register  *******************/
-#define  ADC_SQR5_SQ1                        ((uint32_t)0x0000001F)        /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
-#define  ADC_SQR5_SQ1_0                      ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ1_1                      ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ1_2                      ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ1_3                      ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ1_4                      ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ2                        ((uint32_t)0x000003E0)        /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
-#define  ADC_SQR5_SQ2_0                      ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ2_1                      ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ2_2                      ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ2_3                      ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ2_4                      ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ3                        ((uint32_t)0x00007C00)        /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
-#define  ADC_SQR5_SQ3_0                      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ3_1                      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ3_2                      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ3_3                      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ3_4                      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ4                        ((uint32_t)0x000F8000)        /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
-#define  ADC_SQR5_SQ4_0                      ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ4_1                      ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ4_2                      ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ4_3                      ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ4_4                      ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ5                        ((uint32_t)0x01F00000)        /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
-#define  ADC_SQR5_SQ5_0                      ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ5_1                      ((uint32_t)0x00200000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ5_2                      ((uint32_t)0x00400000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ5_3                      ((uint32_t)0x00800000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ5_4                      ((uint32_t)0x01000000)        /*!< Bit 4 */
-
-#define  ADC_SQR5_SQ6                        ((uint32_t)0x3E000000)        /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
-#define  ADC_SQR5_SQ6_0                      ((uint32_t)0x02000000)        /*!< Bit 0 */
-#define  ADC_SQR5_SQ6_1                      ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  ADC_SQR5_SQ6_2                      ((uint32_t)0x08000000)        /*!< Bit 2 */
-#define  ADC_SQR5_SQ6_3                      ((uint32_t)0x10000000)        /*!< Bit 3 */
-#define  ADC_SQR5_SQ6_4                      ((uint32_t)0x20000000)        /*!< Bit 4 */
-
-
-/*******************  Bit definition for ADC_JSQR register  *******************/
-#define  ADC_JSQR_JSQ1                       ((uint32_t)0x0000001F)        /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */  
-#define  ADC_JSQR_JSQ1_0                     ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ1_1                     ((uint32_t)0x00000002)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ1_2                     ((uint32_t)0x00000004)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ1_3                     ((uint32_t)0x00000008)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ1_4                     ((uint32_t)0x00000010)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ2                       ((uint32_t)0x000003E0)        /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ2_0                     ((uint32_t)0x00000020)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ2_1                     ((uint32_t)0x00000040)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ2_2                     ((uint32_t)0x00000080)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ2_3                     ((uint32_t)0x00000100)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ2_4                     ((uint32_t)0x00000200)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ3                       ((uint32_t)0x00007C00)        /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
-#define  ADC_JSQR_JSQ3_0                     ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ3_1                     ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ3_2                     ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ3_3                     ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ3_4                     ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JSQ4                       ((uint32_t)0x000F8000)        /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
-#define  ADC_JSQR_JSQ4_0                     ((uint32_t)0x00008000)        /*!< Bit 0 */
-#define  ADC_JSQR_JSQ4_1                     ((uint32_t)0x00010000)        /*!< Bit 1 */
-#define  ADC_JSQR_JSQ4_2                     ((uint32_t)0x00020000)        /*!< Bit 2 */
-#define  ADC_JSQR_JSQ4_3                     ((uint32_t)0x00040000)        /*!< Bit 3 */
-#define  ADC_JSQR_JSQ4_4                     ((uint32_t)0x00080000)        /*!< Bit 4 */
-
-#define  ADC_JSQR_JL                         ((uint32_t)0x00300000)        /*!< JL[1:0] bits (Injected Sequence length) */
-#define  ADC_JSQR_JL_0                       ((uint32_t)0x00100000)        /*!< Bit 0 */
-#define  ADC_JSQR_JL_1                       ((uint32_t)0x00200000)        /*!< Bit 1 */
-
-/*******************  Bit definition for ADC_JDR1 register  *******************/
-#define  ADC_JDR1_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR2 register  *******************/
-#define  ADC_JDR2_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR3 register  *******************/
-#define  ADC_JDR3_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/*******************  Bit definition for ADC_JDR4 register  *******************/
-#define  ADC_JDR4_JDATA                      ((uint32_t)0x0000FFFF)        /*!< Injected data */
-
-/********************  Bit definition for ADC_DR register  ********************/
-#define  ADC_DR_DATA                         ((uint32_t)0x0000FFFF)        /*!< Regular data */
-
-/*******************  Bit definition for ADC_CSR register  ********************/
-#define  ADC_CSR_AWD1                        ((uint32_t)0x00000001)        /*!< ADC1 Analog watchdog flag */
-#define  ADC_CSR_EOC1                        ((uint32_t)0x00000002)        /*!< ADC1 End of conversion */
-#define  ADC_CSR_JEOC1                       ((uint32_t)0x00000004)        /*!< ADC1 Injected channel end of conversion */
-#define  ADC_CSR_JSTRT1                      ((uint32_t)0x00000008)        /*!< ADC1 Injected channel Start flag */
-#define  ADC_CSR_STRT1                       ((uint32_t)0x00000010)        /*!< ADC1 Regular channel Start flag */
-#define  ADC_CSR_OVR1                        ((uint32_t)0x00000020)        /*!< ADC1 overrun  flag */
-#define  ADC_CSR_ADONS1                      ((uint32_t)0x00000040)        /*!< ADON status of ADC1 */
-
-/*******************  Bit definition for ADC_CCR register  ********************/
-#define  ADC_CCR_ADCPRE                      ((uint32_t)0x00030000)        /*!< ADC prescaler*/
-#define  ADC_CCR_ADCPRE_0                    ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  ADC_CCR_ADCPRE_1                    ((uint32_t)0x00020000)        /*!< Bit 1 */ 
-#define  ADC_CCR_TSVREFE                     ((uint32_t)0x00800000)        /*!< Temperature Sensor and VREFINT Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Analog Comparators (COMP)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for COMP_CSR register  ********************/
-#define  COMP_CSR_10KPU                      ((uint32_t)0x00000001)        /*!< 10K pull-up resistor */
-#define  COMP_CSR_400KPU                     ((uint32_t)0x00000002)        /*!< 400K pull-up resistor */
-#define  COMP_CSR_10KPD                      ((uint32_t)0x00000004)        /*!< 10K pull-down resistor */
-#define  COMP_CSR_400KPD                     ((uint32_t)0x00000008)        /*!< 400K pull-down resistor */
-#define  COMP_CSR_CMP1EN                     ((uint32_t)0x00000010)        /*!< Comparator 1 enable */
-#define  COMP_CSR_CMP1OUT                    ((uint32_t)0x00000080)        /*!< Comparator 1 output */
-
-#define  COMP_CSR_SPEED                      ((uint32_t)0x00001000)        /*!< Comparator 2 speed */
-#define  COMP_CSR_CMP2OUT                    ((uint32_t)0x00002000)        /*!< Comparator 2 ouput */
-#define  COMP_CSR_VREFOUTEN                  ((uint32_t)0x00010000)        /*!< Comparator Vref Enable */
-#define  COMP_CSR_WNDWE                      ((uint32_t)0x00020000)        /*!< Window mode enable */
-#define  COMP_CSR_INSEL                      ((uint32_t)0x001C0000)        /*!< INSEL[2:0] Inversion input Selection */
-#define  COMP_CSR_INSEL_0                    ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  COMP_CSR_INSEL_1                    ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  COMP_CSR_INSEL_2                    ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  COMP_CSR_OUTSEL                     ((uint32_t)0x00E00000)        /*!< OUTSEL[2:0] comparator 2 output redirection */
-#define  COMP_CSR_OUTSEL_0                   ((uint32_t)0x00200000)        /*!< Bit 0 */
-#define  COMP_CSR_OUTSEL_1                   ((uint32_t)0x00400000)        /*!< Bit 1 */
-#define  COMP_CSR_OUTSEL_2                   ((uint32_t)0x00800000)        /*!< Bit 2 */
-
-#define  COMP_CSR_FCH3                       ((uint32_t)0x04000000)        /*!< Bit 26 */
-#define  COMP_CSR_FCH8                       ((uint32_t)0x08000000)        /*!< Bit 27 */
-#define  COMP_CSR_RCH13                      ((uint32_t)0x10000000)        /*!< Bit 28 */
-
-#define  COMP_CSR_CAIE                       ((uint32_t)0x20000000)        /*!< Bit 29 */
-#define  COMP_CSR_CAIF                       ((uint32_t)0x40000000)        /*!< Bit 30 */
-#define  COMP_CSR_TSUSP                      ((uint32_t)0x80000000)        /*!< Bit 31 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Operational Amplifier (OPAMP)                      */
-/*                                                                            */
-/******************************************************************************/
-/*******************  Bit definition for OPAMP_CSR register  ******************/
-#define OPAMP_CSR_OPA1PD                     ((uint32_t)0x00000001)        /*!< OPAMP1 disable */
-#define OPAMP_CSR_S3SEL1                     ((uint32_t)0x00000002)        /*!< Switch 3 for OPAMP1 Enable */
-#define OPAMP_CSR_S4SEL1                     ((uint32_t)0x00000004)        /*!< Switch 4 for OPAMP1 Enable */
-#define OPAMP_CSR_S5SEL1                     ((uint32_t)0x00000008)        /*!< Switch 5 for OPAMP1 Enable */
-#define OPAMP_CSR_S6SEL1                     ((uint32_t)0x00000010)        /*!< Switch 6 for OPAMP1 Enable */
-#define OPAMP_CSR_OPA1CAL_L                  ((uint32_t)0x00000020)        /*!< OPAMP1 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA1CAL_H                  ((uint32_t)0x00000040)        /*!< OPAMP1 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA1LPM                    ((uint32_t)0x00000080)        /*!< OPAMP1 Low power enable */
-#define OPAMP_CSR_OPA2PD                     ((uint32_t)0x00000100)        /*!< OPAMP2 disable */
-#define OPAMP_CSR_S3SEL2                     ((uint32_t)0x00000200)        /*!< Switch 3 for OPAMP2 Enable */
-#define OPAMP_CSR_S4SEL2                     ((uint32_t)0x00000400)        /*!< Switch 4 for OPAMP2 Enable */
-#define OPAMP_CSR_S5SEL2                     ((uint32_t)0x00000800)        /*!< Switch 5 for OPAMP2 Enable */
-#define OPAMP_CSR_S6SEL2                     ((uint32_t)0x00001000)        /*!< Switch 6 for OPAMP2 Enable */
-#define OPAMP_CSR_OPA2CAL_L                  ((uint32_t)0x00002000)        /*!< OPAMP2 Offset calibration for P differential pair */
-#define OPAMP_CSR_OPA2CAL_H                  ((uint32_t)0x00004000)        /*!< OPAMP2 Offset calibration for N differential pair */
-#define OPAMP_CSR_OPA2LPM                    ((uint32_t)0x00008000)        /*!< OPAMP2 Low power enable */
-#define OPAMP_CSR_ANAWSEL1                   ((uint32_t)0x01000000)        /*!< Switch ANA Enable for OPAMP1 */ 
-#define OPAMP_CSR_ANAWSEL2                   ((uint32_t)0x02000000)        /*!< Switch ANA Enable for OPAMP2 */
-#define OPAMP_CSR_S7SEL2                     ((uint32_t)0x08000000)        /*!< Switch 7 for OPAMP2 Enable */
-#define OPAMP_CSR_AOP_RANGE                  ((uint32_t)0x10000000)        /*!< Power range selection */
-#define OPAMP_CSR_OPA1CALOUT                 ((uint32_t)0x20000000)        /*!< OPAMP1 calibration output */
-#define OPAMP_CSR_OPA2CALOUT                 ((uint32_t)0x40000000)        /*!< OPAMP2 calibration output */
-
-/*******************  Bit definition for OPAMP_OTR register  ******************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW    ((uint32_t)0x0000001F)        /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH   ((uint32_t)0x000003E0)        /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LOW    ((uint32_t)0x00007C00)        /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_HIGH   ((uint32_t)0x000F8000)        /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-#define OPAMP_OTR_OT_USER                    ((uint32_t)0x80000000)        /*!< Switch to OPAMP offset user trimmed values */
-
-/*******************  Bit definition for OPAMP_LPOTR register  ****************/
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_LOW  ((uint32_t)0x0000001F)        /*!< Offset trim for transistors differential pair PMOS of OPAMP1 */
-#define OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000003E0)        /*!< Offset trim for transistors differential pair NMOS of OPAMP1 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_LOW  ((uint32_t)0x00007C00)        /*!< Offset trim for transistors differential pair PMOS of OPAMP2 */
-#define OPAMP_OTR_AO2_OPT_OFFSET_TRIM_LP_HIGH ((uint32_t)0x000F8000)        /*!< Offset trim for transistors differential pair NMOS of OPAMP2 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       CRC calculation unit (CRC)                           */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for CRC_DR register  *********************/
-#define  CRC_DR_DR                           ((uint32_t)0xFFFFFFFF)        /*!< Data register bits */
-
-/*******************  Bit definition for CRC_IDR register  ********************/
-#define  CRC_IDR_IDR                         ((uint32_t)0x000000FF)               /*!< General-purpose 8-bit data register bits */
-
-/********************  Bit definition for CRC_CR register  ********************/
-#define  CRC_CR_RESET                        ((uint32_t)0x00000001)        /*!< RESET bit */
-
-/******************************************************************************/
-/*                                                                            */
-/*                    Digital to Analog Converter (DAC)                       */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for DAC_CR register  ********************/
-#define  DAC_CR_EN1                          ((uint32_t)0x00000001)        /*!<DAC channel1 enable */
-#define  DAC_CR_BOFF1                        ((uint32_t)0x00000002)        /*!<DAC channel1 output buffer disable */
-#define  DAC_CR_TEN1                         ((uint32_t)0x00000004)        /*!<DAC channel1 Trigger enable */
-
-#define  DAC_CR_TSEL1                        ((uint32_t)0x00000038)        /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
-#define  DAC_CR_TSEL1_0                      ((uint32_t)0x00000008)        /*!<Bit 0 */
-#define  DAC_CR_TSEL1_1                      ((uint32_t)0x00000010)        /*!<Bit 1 */
-#define  DAC_CR_TSEL1_2                      ((uint32_t)0x00000020)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE1                        ((uint32_t)0x000000C0)        /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE1_0                      ((uint32_t)0x00000040)        /*!<Bit 0 */
-#define  DAC_CR_WAVE1_1                      ((uint32_t)0x00000080)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP1                        ((uint32_t)0x00000F00)        /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP1_0                      ((uint32_t)0x00000100)        /*!<Bit 0 */
-#define  DAC_CR_MAMP1_1                      ((uint32_t)0x00000200)        /*!<Bit 1 */
-#define  DAC_CR_MAMP1_2                      ((uint32_t)0x00000400)        /*!<Bit 2 */
-#define  DAC_CR_MAMP1_3                      ((uint32_t)0x00000800)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN1                       ((uint32_t)0x00001000)        /*!<DAC channel1 DMA enable */
-#define  DAC_CR_DMAUDRIE1                    ((uint32_t)0x00002000)        /*!<DAC channel1 DMA Interrupt enable */
-#define  DAC_CR_EN2                          ((uint32_t)0x00010000)        /*!<DAC channel2 enable */
-#define  DAC_CR_BOFF2                        ((uint32_t)0x00020000)        /*!<DAC channel2 output buffer disable */
-#define  DAC_CR_TEN2                         ((uint32_t)0x00040000)        /*!<DAC channel2 Trigger enable */
-
-#define  DAC_CR_TSEL2                        ((uint32_t)0x00380000)        /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
-#define  DAC_CR_TSEL2_0                      ((uint32_t)0x00080000)        /*!<Bit 0 */
-#define  DAC_CR_TSEL2_1                      ((uint32_t)0x00100000)        /*!<Bit 1 */
-#define  DAC_CR_TSEL2_2                      ((uint32_t)0x00200000)        /*!<Bit 2 */
-
-#define  DAC_CR_WAVE2                        ((uint32_t)0x00C00000)        /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
-#define  DAC_CR_WAVE2_0                      ((uint32_t)0x00400000)        /*!<Bit 0 */
-#define  DAC_CR_WAVE2_1                      ((uint32_t)0x00800000)        /*!<Bit 1 */
-
-#define  DAC_CR_MAMP2                        ((uint32_t)0x0F000000)        /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
-#define  DAC_CR_MAMP2_0                      ((uint32_t)0x01000000)        /*!<Bit 0 */
-#define  DAC_CR_MAMP2_1                      ((uint32_t)0x02000000)        /*!<Bit 1 */
-#define  DAC_CR_MAMP2_2                      ((uint32_t)0x04000000)        /*!<Bit 2 */
-#define  DAC_CR_MAMP2_3                      ((uint32_t)0x08000000)        /*!<Bit 3 */
-
-#define  DAC_CR_DMAEN2                       ((uint32_t)0x10000000)        /*!<DAC channel2 DMA enabled */
-#define  DAC_CR_DMAUDRIE2                    ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun interrupt enable */
-/*****************  Bit definition for DAC_SWTRIGR register  ******************/
-#define  DAC_SWTRIGR_SWTRIG1                 ((uint32_t)0x00000001)        /*!<DAC channel1 software trigger */
-#define  DAC_SWTRIGR_SWTRIG2                 ((uint32_t)0x00000002)        /*!<DAC channel2 software trigger */
-
-/*****************  Bit definition for DAC_DHR12R1 register  ******************/
-#define  DAC_DHR12R1_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L1 register  ******************/
-#define  DAC_DHR12L1_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R1 register  ******************/
-#define  DAC_DHR8R1_DACC1DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel1 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12R2 register  ******************/
-#define  DAC_DHR12R2_DACC2DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12L2 register  ******************/
-#define  DAC_DHR12L2_DACC2DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8R2 register  ******************/
-#define  DAC_DHR8R2_DACC2DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel2 8-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12RD register  ******************/
-#define  DAC_DHR12RD_DACC1DHR                ((uint32_t)0x00000FFF)        /*!<DAC channel1 12-bit Right aligned data */
-#define  DAC_DHR12RD_DACC2DHR                ((uint32_t)0x0FFF0000)        /*!<DAC channel2 12-bit Right aligned data */
-
-/*****************  Bit definition for DAC_DHR12LD register  ******************/
-#define  DAC_DHR12LD_DACC1DHR                ((uint32_t)0x0000FFF0)        /*!<DAC channel1 12-bit Left aligned data */
-#define  DAC_DHR12LD_DACC2DHR                ((uint32_t)0xFFF00000)        /*!<DAC channel2 12-bit Left aligned data */
-
-/******************  Bit definition for DAC_DHR8RD register  ******************/
-#define  DAC_DHR8RD_DACC1DHR                 ((uint32_t)0x000000FF)        /*!<DAC channel1 8-bit Right aligned data */
-#define  DAC_DHR8RD_DACC2DHR                 ((uint32_t)0x0000FF00)        /*!<DAC channel2 8-bit Right aligned data */
-
-/*******************  Bit definition for DAC_DOR1 register  *******************/
-#define  DAC_DOR1_DACC1DOR                   ((uint32_t)0x00000FFF)        /*!<DAC channel1 data output */
-
-/*******************  Bit definition for DAC_DOR2 register  *******************/
-#define  DAC_DOR2_DACC2DOR                   ((uint_t)0x00000FFF)          /*!<DAC channel2 data output */
-
-/********************  Bit definition for DAC_SR register  ********************/
-#define  DAC_SR_DMAUDR1                      ((uint32_t)0x00002000)        /*!<DAC channel1 DMA underrun flag */
-#define  DAC_SR_DMAUDR2                      ((uint32_t)0x20000000)        /*!<DAC channel2 DMA underrun flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Debug MCU (DBGMCU)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/****************  Bit definition for DBGMCU_IDCODE register  *****************/
-#define  DBGMCU_IDCODE_DEV_ID                ((uint32_t)0x00000FFF)        /*!< Device Identifier */
-
-#define  DBGMCU_IDCODE_REV_ID                ((uint32_t)0xFFFF0000)        /*!< REV_ID[15:0] bits (Revision Identifier) */
-#define  DBGMCU_IDCODE_REV_ID_0              ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  DBGMCU_IDCODE_REV_ID_1              ((uint32_t)0x00020000)        /*!< Bit 1 */
-#define  DBGMCU_IDCODE_REV_ID_2              ((uint32_t)0x00040000)        /*!< Bit 2 */
-#define  DBGMCU_IDCODE_REV_ID_3              ((uint32_t)0x00080000)        /*!< Bit 3 */
-#define  DBGMCU_IDCODE_REV_ID_4              ((uint32_t)0x00100000)        /*!< Bit 4 */
-#define  DBGMCU_IDCODE_REV_ID_5              ((uint32_t)0x00200000)        /*!< Bit 5 */
-#define  DBGMCU_IDCODE_REV_ID_6              ((uint32_t)0x00400000)        /*!< Bit 6 */
-#define  DBGMCU_IDCODE_REV_ID_7              ((uint32_t)0x00800000)        /*!< Bit 7 */
-#define  DBGMCU_IDCODE_REV_ID_8              ((uint32_t)0x01000000)        /*!< Bit 8 */
-#define  DBGMCU_IDCODE_REV_ID_9              ((uint32_t)0x02000000)        /*!< Bit 9 */
-#define  DBGMCU_IDCODE_REV_ID_10             ((uint32_t)0x04000000)        /*!< Bit 10 */
-#define  DBGMCU_IDCODE_REV_ID_11             ((uint32_t)0x08000000)        /*!< Bit 11 */
-#define  DBGMCU_IDCODE_REV_ID_12             ((uint32_t)0x10000000)        /*!< Bit 12 */
-#define  DBGMCU_IDCODE_REV_ID_13             ((uint32_t)0x20000000)        /*!< Bit 13 */
-#define  DBGMCU_IDCODE_REV_ID_14             ((uint32_t)0x40000000)        /*!< Bit 14 */
-#define  DBGMCU_IDCODE_REV_ID_15             ((uint32_t)0x80000000)        /*!< Bit 15 */
-
-/******************  Bit definition for DBGMCU_CR register  *******************/
-#define  DBGMCU_CR_DBG_SLEEP                 ((uint32_t)0x00000001)        /*!< Debug Sleep Mode */
-#define  DBGMCU_CR_DBG_STOP                  ((uint32_t)0x00000002)        /*!< Debug Stop Mode */
-#define  DBGMCU_CR_DBG_STANDBY               ((uint32_t)0x00000004)        /*!< Debug Standby mode */
-#define  DBGMCU_CR_TRACE_IOEN                ((uint32_t)0x00000020)        /*!< Trace Pin Assignment Control */
-
-#define  DBGMCU_CR_TRACE_MODE                ((uint32_t)0x000000C0)        /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
-#define  DBGMCU_CR_TRACE_MODE_0              ((uint32_t)0x00000040)        /*!< Bit 0 */
-#define  DBGMCU_CR_TRACE_MODE_1              ((uint32_t)0x00000080)        /*!< Bit 1 */
-
-/******************  Bit definition for DBGMCU_APB1_FZ register  **************/
-
-#define  DBGMCU_APB1_FZ_DBG_TIM2_STOP             ((uint32_t)0x00000001)   /*!< TIM2 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM3_STOP             ((uint32_t)0x00000002)   /*!< TIM3 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM4_STOP             ((uint32_t)0x00000004)   /*!< TIM4 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM5_STOP             ((uint32_t)0x00000008)   /*!< TIM5 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM6_STOP             ((uint32_t)0x00000010)   /*!< TIM6 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_TIM7_STOP             ((uint32_t)0x00000020)   /*!< TIM7 counter stopped when core is halted */
-#define  DBGMCU_APB1_FZ_DBG_RTC_STOP              ((uint32_t)0x00000400)   /*!< RTC Counter stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_WWDG_STOP             ((uint32_t)0x00000800)   /*!< Debug Window Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_IWDG_STOP             ((uint32_t)0x00001000)   /*!< Debug Independent Watchdog stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)   /*!< SMBUS timeout mode stopped when Core is halted */
-#define  DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)   /*!< SMBUS timeout mode stopped when Core is halted */
-
-/******************  Bit definition for DBGMCU_APB2_FZ register  **************/
-
-#define  DBGMCU_APB2_FZ_DBG_TIM9_STOP             ((uint32_t)0x00000004)   /*!< TIM9 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM10_STOP            ((uint32_t)0x00000008)   /*!< TIM10 counter stopped when core is halted */
-#define  DBGMCU_APB2_FZ_DBG_TIM11_STOP            ((uint32_t)0x00000010)   /*!< TIM11 counter stopped when core is halted */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           DMA Controller (DMA)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for DMA_ISR register  ********************/
-#define  DMA_ISR_GIF1                        ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt flag */
-#define  DMA_ISR_TCIF1                       ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete flag */
-#define  DMA_ISR_HTIF1                       ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer flag */
-#define  DMA_ISR_TEIF1                       ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error flag */
-#define  DMA_ISR_GIF2                        ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt flag */
-#define  DMA_ISR_TCIF2                       ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete flag */
-#define  DMA_ISR_HTIF2                       ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer flag */
-#define  DMA_ISR_TEIF2                       ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error flag */
-#define  DMA_ISR_GIF3                        ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt flag */
-#define  DMA_ISR_TCIF3                       ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete flag */
-#define  DMA_ISR_HTIF3                       ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer flag */
-#define  DMA_ISR_TEIF3                       ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error flag */
-#define  DMA_ISR_GIF4                        ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt flag */
-#define  DMA_ISR_TCIF4                       ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete flag */
-#define  DMA_ISR_HTIF4                       ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer flag */
-#define  DMA_ISR_TEIF4                       ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error flag */
-#define  DMA_ISR_GIF5                        ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt flag */
-#define  DMA_ISR_TCIF5                       ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete flag */
-#define  DMA_ISR_HTIF5                       ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer flag */
-#define  DMA_ISR_TEIF5                       ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error flag */
-#define  DMA_ISR_GIF6                        ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt flag */
-#define  DMA_ISR_TCIF6                       ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete flag */
-#define  DMA_ISR_HTIF6                       ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer flag */
-#define  DMA_ISR_TEIF6                       ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error flag */
-#define  DMA_ISR_GIF7                        ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt flag */
-#define  DMA_ISR_TCIF7                       ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete flag */
-#define  DMA_ISR_HTIF7                       ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer flag */
-#define  DMA_ISR_TEIF7                       ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error flag */
-
-/*******************  Bit definition for DMA_IFCR register  *******************/
-#define  DMA_IFCR_CGIF1                      ((uint32_t)0x00000001)        /*!< Channel 1 Global interrupt clear */
-#define  DMA_IFCR_CTCIF1                     ((uint32_t)0x00000002)        /*!< Channel 1 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF1                     ((uint32_t)0x00000004)        /*!< Channel 1 Half Transfer clear */
-#define  DMA_IFCR_CTEIF1                     ((uint32_t)0x00000008)        /*!< Channel 1 Transfer Error clear */
-#define  DMA_IFCR_CGIF2                      ((uint32_t)0x00000010)        /*!< Channel 2 Global interrupt clear */
-#define  DMA_IFCR_CTCIF2                     ((uint32_t)0x00000020)        /*!< Channel 2 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF2                     ((uint32_t)0x00000040)        /*!< Channel 2 Half Transfer clear */
-#define  DMA_IFCR_CTEIF2                     ((uint32_t)0x00000080)        /*!< Channel 2 Transfer Error clear */
-#define  DMA_IFCR_CGIF3                      ((uint32_t)0x00000100)        /*!< Channel 3 Global interrupt clear */
-#define  DMA_IFCR_CTCIF3                     ((uint32_t)0x00000200)        /*!< Channel 3 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF3                     ((uint32_t)0x00000400)        /*!< Channel 3 Half Transfer clear */
-#define  DMA_IFCR_CTEIF3                     ((uint32_t)0x00000800)        /*!< Channel 3 Transfer Error clear */
-#define  DMA_IFCR_CGIF4                      ((uint32_t)0x00001000)        /*!< Channel 4 Global interrupt clear */
-#define  DMA_IFCR_CTCIF4                     ((uint32_t)0x00002000)        /*!< Channel 4 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF4                     ((uint32_t)0x00004000)        /*!< Channel 4 Half Transfer clear */
-#define  DMA_IFCR_CTEIF4                     ((uint32_t)0x00008000)        /*!< Channel 4 Transfer Error clear */
-#define  DMA_IFCR_CGIF5                      ((uint32_t)0x00010000)        /*!< Channel 5 Global interrupt clear */
-#define  DMA_IFCR_CTCIF5                     ((uint32_t)0x00020000)        /*!< Channel 5 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF5                     ((uint32_t)0x00040000)        /*!< Channel 5 Half Transfer clear */
-#define  DMA_IFCR_CTEIF5                     ((uint32_t)0x00080000)        /*!< Channel 5 Transfer Error clear */
-#define  DMA_IFCR_CGIF6                      ((uint32_t)0x00100000)        /*!< Channel 6 Global interrupt clear */
-#define  DMA_IFCR_CTCIF6                     ((uint32_t)0x00200000)        /*!< Channel 6 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF6                     ((uint32_t)0x00400000)        /*!< Channel 6 Half Transfer clear */
-#define  DMA_IFCR_CTEIF6                     ((uint32_t)0x00800000)        /*!< Channel 6 Transfer Error clear */
-#define  DMA_IFCR_CGIF7                      ((uint32_t)0x01000000)        /*!< Channel 7 Global interrupt clear */
-#define  DMA_IFCR_CTCIF7                     ((uint32_t)0x02000000)        /*!< Channel 7 Transfer Complete clear */
-#define  DMA_IFCR_CHTIF7                     ((uint32_t)0x04000000)        /*!< Channel 7 Half Transfer clear */
-#define  DMA_IFCR_CTEIF7                     ((uint32_t)0x08000000)        /*!< Channel 7 Transfer Error clear */
-
-/*******************  Bit definition for DMA_CCR register  *******************/
-#define  DMA_CCR_EN                         ((uint32_t)0x00000001)            /*!< Channel enable*/
-#define  DMA_CCR_TCIE                       ((uint32_t)0x00000002)            /*!< Transfer complete interrupt enable */
-#define  DMA_CCR_HTIE                       ((uint32_t)0x00000004)            /*!< Half Transfer interrupt enable */
-#define  DMA_CCR_TEIE                       ((uint32_t)0x00000008)            /*!< Transfer error interrupt enable */
-#define  DMA_CCR_DIR                        ((uint32_t)0x00000010)            /*!< Data transfer direction */
-#define  DMA_CCR_CIRC                       ((uint32_t)0x00000020)            /*!< Circular mode */
-#define  DMA_CCR_PINC                       ((uint32_t)0x00000040)            /*!< Peripheral increment mode */
-#define  DMA_CCR_MINC                       ((uint32_t)0x00000080)            /*!< Memory increment mode */
-
-#define  DMA_CCR_PSIZE                      ((uint32_t)0x00000300)            /*!< PSIZE[1:0] bits (Peripheral size) */
-#define  DMA_CCR_PSIZE_0                    ((uint32_t)0x00000100)            /*!< Bit 0 */
-#define  DMA_CCR_PSIZE_1                    ((uint32_t)0x00000200)            /*!< Bit 1 */
-
-#define  DMA_CCR_MSIZE                      ((uint32_t)0x00000C00)            /*!< MSIZE[1:0] bits (Memory size) */
-#define  DMA_CCR_MSIZE_0                    ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  DMA_CCR_MSIZE_1                    ((uint32_t)0x00000800)            /*!< Bit 1 */
-
-#define  DMA_CCR_PL                         ((uint32_t)0x00003000)            /*!< PL[1:0] bits(Channel Priority level) */
-#define  DMA_CCR_PL_0                       ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  DMA_CCR_PL_1                       ((uint32_t)0x00002000)            /*!< Bit 1 */
-
-#define  DMA_CCR_MEM2MEM                    ((uint32_t)0x00004000)            /*!< Memory to memory mode */
-
-/******************  Bit definition for DMA_CNDTR1 register  ******************/
-#define  DMA_CNDTR1_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR2 register  ******************/
-#define  DMA_CNDTR2_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR3 register  ******************/
-#define  DMA_CNDTR3_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR4 register  ******************/
-#define  DMA_CNDTR4_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR5 register  ******************/
-#define  DMA_CNDTR5_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR6 register  ******************/
-#define  DMA_CNDTR6_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CNDTR7 register  ******************/
-#define  DMA_CNDTR7_NDT                      ((uint32_t)0x0000FFFF)            /*!< Number of data to Transfer */
-
-/******************  Bit definition for DMA_CPAR1 register  *******************/
-#define  DMA_CPAR1_PA                        ((uint32_t)0xFFFFFFFF)            /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR2 register  *******************/
-#define  DMA_CPAR2_PA                        ((uint32_t)0xFFFFFFFF)            /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR3 register  *******************/
-#define  DMA_CPAR3_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR4 register  *******************/
-#define  DMA_CPAR4_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR5 register  *******************/
-#define  DMA_CPAR5_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CPAR6 register  *******************/
-#define  DMA_CPAR6_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-
-/******************  Bit definition for DMA_CPAR7 register  *******************/
-#define  DMA_CPAR7_PA                        ((uint32_t)0xFFFFFFFF)        /*!< Peripheral Address */
-
-/******************  Bit definition for DMA_CMAR1 register  *******************/
-#define  DMA_CMAR1_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR2 register  *******************/
-#define  DMA_CMAR2_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR3 register  *******************/
-#define  DMA_CMAR3_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-
-/******************  Bit definition for DMA_CMAR4 register  *******************/
-#define  DMA_CMAR4_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR5 register  *******************/
-#define  DMA_CMAR5_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR6 register  *******************/
-#define  DMA_CMAR6_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************  Bit definition for DMA_CMAR7 register  *******************/
-#define  DMA_CMAR7_MA                        ((uint32_t)0xFFFFFFFF)        /*!< Memory Address */
-
-/******************************************************************************/
-/*                                                                            */
-/*                  External Interrupt/Event Controller (EXTI)                */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for EXTI_IMR register  *******************/
-#define  EXTI_IMR_MR0                        ((uint32_t)0x00000001)        /*!< Interrupt Mask on line 0 */
-#define  EXTI_IMR_MR1                        ((uint32_t)0x00000002)        /*!< Interrupt Mask on line 1 */
-#define  EXTI_IMR_MR2                        ((uint32_t)0x00000004)        /*!< Interrupt Mask on line 2 */
-#define  EXTI_IMR_MR3                        ((uint32_t)0x00000008)        /*!< Interrupt Mask on line 3 */
-#define  EXTI_IMR_MR4                        ((uint32_t)0x00000010)        /*!< Interrupt Mask on line 4 */
-#define  EXTI_IMR_MR5                        ((uint32_t)0x00000020)        /*!< Interrupt Mask on line 5 */
-#define  EXTI_IMR_MR6                        ((uint32_t)0x00000040)        /*!< Interrupt Mask on line 6 */
-#define  EXTI_IMR_MR7                        ((uint32_t)0x00000080)        /*!< Interrupt Mask on line 7 */
-#define  EXTI_IMR_MR8                        ((uint32_t)0x00000100)        /*!< Interrupt Mask on line 8 */
-#define  EXTI_IMR_MR9                        ((uint32_t)0x00000200)        /*!< Interrupt Mask on line 9 */
-#define  EXTI_IMR_MR10                       ((uint32_t)0x00000400)        /*!< Interrupt Mask on line 10 */
-#define  EXTI_IMR_MR11                       ((uint32_t)0x00000800)        /*!< Interrupt Mask on line 11 */
-#define  EXTI_IMR_MR12                       ((uint32_t)0x00001000)        /*!< Interrupt Mask on line 12 */
-#define  EXTI_IMR_MR13                       ((uint32_t)0x00002000)        /*!< Interrupt Mask on line 13 */
-#define  EXTI_IMR_MR14                       ((uint32_t)0x00004000)        /*!< Interrupt Mask on line 14 */
-#define  EXTI_IMR_MR15                       ((uint32_t)0x00008000)        /*!< Interrupt Mask on line 15 */
-#define  EXTI_IMR_MR16                       ((uint32_t)0x00010000)        /*!< Interrupt Mask on line 16 */
-#define  EXTI_IMR_MR17                       ((uint32_t)0x00020000)        /*!< Interrupt Mask on line 17 */
-#define  EXTI_IMR_MR18                       ((uint32_t)0x00040000)        /*!< Interrupt Mask on line 18 */
-#define  EXTI_IMR_MR19                       ((uint32_t)0x00080000)        /*!< Interrupt Mask on line 19 */
-#define  EXTI_IMR_MR20                       ((uint32_t)0x00100000)        /*!< Interrupt Mask on line 20 */
-#define  EXTI_IMR_MR21                       ((uint32_t)0x00200000)        /*!< Interrupt Mask on line 21 */
-#define  EXTI_IMR_MR22                       ((uint32_t)0x00400000)        /*!< Interrupt Mask on line 22 */
-#define  EXTI_IMR_MR23                       ((uint32_t)0x00800000)        /*!< Interrupt Mask on line 23 */
-
-/*******************  Bit definition for EXTI_EMR register  *******************/
-#define  EXTI_EMR_MR0                        ((uint32_t)0x00000001)        /*!< Event Mask on line 0 */
-#define  EXTI_EMR_MR1                        ((uint32_t)0x00000002)        /*!< Event Mask on line 1 */
-#define  EXTI_EMR_MR2                        ((uint32_t)0x00000004)        /*!< Event Mask on line 2 */
-#define  EXTI_EMR_MR3                        ((uint32_t)0x00000008)        /*!< Event Mask on line 3 */
-#define  EXTI_EMR_MR4                        ((uint32_t)0x00000010)        /*!< Event Mask on line 4 */
-#define  EXTI_EMR_MR5                        ((uint32_t)0x00000020)        /*!< Event Mask on line 5 */
-#define  EXTI_EMR_MR6                        ((uint32_t)0x00000040)        /*!< Event Mask on line 6 */
-#define  EXTI_EMR_MR7                        ((uint32_t)0x00000080)        /*!< Event Mask on line 7 */
-#define  EXTI_EMR_MR8                        ((uint32_t)0x00000100)        /*!< Event Mask on line 8 */
-#define  EXTI_EMR_MR9                        ((uint32_t)0x00000200)        /*!< Event Mask on line 9 */
-#define  EXTI_EMR_MR10                       ((uint32_t)0x00000400)        /*!< Event Mask on line 10 */
-#define  EXTI_EMR_MR11                       ((uint32_t)0x00000800)        /*!< Event Mask on line 11 */
-#define  EXTI_EMR_MR12                       ((uint32_t)0x00001000)        /*!< Event Mask on line 12 */
-#define  EXTI_EMR_MR13                       ((uint32_t)0x00002000)        /*!< Event Mask on line 13 */
-#define  EXTI_EMR_MR14                       ((uint32_t)0x00004000)        /*!< Event Mask on line 14 */
-#define  EXTI_EMR_MR15                       ((uint32_t)0x00008000)        /*!< Event Mask on line 15 */
-#define  EXTI_EMR_MR16                       ((uint32_t)0x00010000)        /*!< Event Mask on line 16 */
-#define  EXTI_EMR_MR17                       ((uint32_t)0x00020000)        /*!< Event Mask on line 17 */
-#define  EXTI_EMR_MR18                       ((uint32_t)0x00040000)        /*!< Event Mask on line 18 */
-#define  EXTI_EMR_MR19                       ((uint32_t)0x00080000)        /*!< Event Mask on line 19 */
-#define  EXTI_EMR_MR20                       ((uint32_t)0x00100000)        /*!< Event Mask on line 20 */
-#define  EXTI_EMR_MR21                       ((uint32_t)0x00200000)        /*!< Event Mask on line 21 */
-#define  EXTI_EMR_MR22                       ((uint32_t)0x00400000)        /*!< Event Mask on line 22 */
-#define  EXTI_EMR_MR23                       ((uint32_t)0x00800000)        /*!< Event Mask on line 23 */
-
-/******************  Bit definition for EXTI_RTSR register  *******************/
-#define  EXTI_RTSR_TR0                       ((uint32_t)0x00000001)        /*!< Rising trigger event configuration bit of line 0 */
-#define  EXTI_RTSR_TR1                       ((uint32_t)0x00000002)        /*!< Rising trigger event configuration bit of line 1 */
-#define  EXTI_RTSR_TR2                       ((uint32_t)0x00000004)        /*!< Rising trigger event configuration bit of line 2 */
-#define  EXTI_RTSR_TR3                       ((uint32_t)0x00000008)        /*!< Rising trigger event configuration bit of line 3 */
-#define  EXTI_RTSR_TR4                       ((uint32_t)0x00000010)        /*!< Rising trigger event configuration bit of line 4 */
-#define  EXTI_RTSR_TR5                       ((uint32_t)0x00000020)        /*!< Rising trigger event configuration bit of line 5 */
-#define  EXTI_RTSR_TR6                       ((uint32_t)0x00000040)        /*!< Rising trigger event configuration bit of line 6 */
-#define  EXTI_RTSR_TR7                       ((uint32_t)0x00000080)        /*!< Rising trigger event configuration bit of line 7 */
-#define  EXTI_RTSR_TR8                       ((uint32_t)0x00000100)        /*!< Rising trigger event configuration bit of line 8 */
-#define  EXTI_RTSR_TR9                       ((uint32_t)0x00000200)        /*!< Rising trigger event configuration bit of line 9 */
-#define  EXTI_RTSR_TR10                      ((uint32_t)0x00000400)        /*!< Rising trigger event configuration bit of line 10 */
-#define  EXTI_RTSR_TR11                      ((uint32_t)0x00000800)        /*!< Rising trigger event configuration bit of line 11 */
-#define  EXTI_RTSR_TR12                      ((uint32_t)0x00001000)        /*!< Rising trigger event configuration bit of line 12 */
-#define  EXTI_RTSR_TR13                      ((uint32_t)0x00002000)        /*!< Rising trigger event configuration bit of line 13 */
-#define  EXTI_RTSR_TR14                      ((uint32_t)0x00004000)        /*!< Rising trigger event configuration bit of line 14 */
-#define  EXTI_RTSR_TR15                      ((uint32_t)0x00008000)        /*!< Rising trigger event configuration bit of line 15 */
-#define  EXTI_RTSR_TR16                      ((uint32_t)0x00010000)        /*!< Rising trigger event configuration bit of line 16 */
-#define  EXTI_RTSR_TR17                      ((uint32_t)0x00020000)        /*!< Rising trigger event configuration bit of line 17 */
-#define  EXTI_RTSR_TR18                      ((uint32_t)0x00040000)        /*!< Rising trigger event configuration bit of line 18 */
-#define  EXTI_RTSR_TR19                      ((uint32_t)0x00080000)        /*!< Rising trigger event configuration bit of line 19 */
-#define  EXTI_RTSR_TR20                      ((uint32_t)0x00100000)        /*!< Rising trigger event configuration bit of line 20 */
-#define  EXTI_RTSR_TR21                      ((uint32_t)0x00200000)        /*!< Rising trigger event configuration bit of line 21 */
-#define  EXTI_RTSR_TR22                      ((uint32_t)0x00400000)        /*!< Rising trigger event configuration bit of line 22 */
-#define  EXTI_RTSR_TR23                      ((uint32_t)0x00800000)        /*!< Rising trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_FTSR register  *******************/
-#define  EXTI_FTSR_TR0                       ((uint32_t)0x00000001)        /*!< Falling trigger event configuration bit of line 0 */
-#define  EXTI_FTSR_TR1                       ((uint32_t)0x00000002)        /*!< Falling trigger event configuration bit of line 1 */
-#define  EXTI_FTSR_TR2                       ((uint32_t)0x00000004)        /*!< Falling trigger event configuration bit of line 2 */
-#define  EXTI_FTSR_TR3                       ((uint32_t)0x00000008)        /*!< Falling trigger event configuration bit of line 3 */
-#define  EXTI_FTSR_TR4                       ((uint32_t)0x00000010)        /*!< Falling trigger event configuration bit of line 4 */
-#define  EXTI_FTSR_TR5                       ((uint32_t)0x00000020)        /*!< Falling trigger event configuration bit of line 5 */
-#define  EXTI_FTSR_TR6                       ((uint32_t)0x00000040)        /*!< Falling trigger event configuration bit of line 6 */
-#define  EXTI_FTSR_TR7                       ((uint32_t)0x00000080)        /*!< Falling trigger event configuration bit of line 7 */
-#define  EXTI_FTSR_TR8                       ((uint32_t)0x00000100)        /*!< Falling trigger event configuration bit of line 8 */
-#define  EXTI_FTSR_TR9                       ((uint32_t)0x00000200)        /*!< Falling trigger event configuration bit of line 9 */
-#define  EXTI_FTSR_TR10                      ((uint32_t)0x00000400)        /*!< Falling trigger event configuration bit of line 10 */
-#define  EXTI_FTSR_TR11                      ((uint32_t)0x00000800)        /*!< Falling trigger event configuration bit of line 11 */
-#define  EXTI_FTSR_TR12                      ((uint32_t)0x00001000)        /*!< Falling trigger event configuration bit of line 12 */
-#define  EXTI_FTSR_TR13                      ((uint32_t)0x00002000)        /*!< Falling trigger event configuration bit of line 13 */
-#define  EXTI_FTSR_TR14                      ((uint32_t)0x00004000)        /*!< Falling trigger event configuration bit of line 14 */
-#define  EXTI_FTSR_TR15                      ((uint32_t)0x00008000)        /*!< Falling trigger event configuration bit of line 15 */
-#define  EXTI_FTSR_TR16                      ((uint32_t)0x00010000)        /*!< Falling trigger event configuration bit of line 16 */
-#define  EXTI_FTSR_TR17                      ((uint32_t)0x00020000)        /*!< Falling trigger event configuration bit of line 17 */
-#define  EXTI_FTSR_TR18                      ((uint32_t)0x00040000)        /*!< Falling trigger event configuration bit of line 18 */
-#define  EXTI_FTSR_TR19                      ((uint32_t)0x00080000)        /*!< Falling trigger event configuration bit of line 19 */
-#define  EXTI_FTSR_TR20                      ((uint32_t)0x00100000)        /*!< Falling trigger event configuration bit of line 20 */
-#define  EXTI_FTSR_TR21                      ((uint32_t)0x00200000)        /*!< Falling trigger event configuration bit of line 21 */
-#define  EXTI_FTSR_TR22                      ((uint32_t)0x00400000)        /*!< Falling trigger event configuration bit of line 22 */
-#define  EXTI_FTSR_TR23                      ((uint32_t)0x00800000)        /*!< Falling trigger event configuration bit of line 23 */
-
-/******************  Bit definition for EXTI_SWIER register  ******************/
-#define  EXTI_SWIER_SWIER0                   ((uint32_t)0x00000001)        /*!< Software Interrupt on line 0 */
-#define  EXTI_SWIER_SWIER1                   ((uint32_t)0x00000002)        /*!< Software Interrupt on line 1 */
-#define  EXTI_SWIER_SWIER2                   ((uint32_t)0x00000004)        /*!< Software Interrupt on line 2 */
-#define  EXTI_SWIER_SWIER3                   ((uint32_t)0x00000008)        /*!< Software Interrupt on line 3 */
-#define  EXTI_SWIER_SWIER4                   ((uint32_t)0x00000010)        /*!< Software Interrupt on line 4 */
-#define  EXTI_SWIER_SWIER5                   ((uint32_t)0x00000020)        /*!< Software Interrupt on line 5 */
-#define  EXTI_SWIER_SWIER6                   ((uint32_t)0x00000040)        /*!< Software Interrupt on line 6 */
-#define  EXTI_SWIER_SWIER7                   ((uint32_t)0x00000080)        /*!< Software Interrupt on line 7 */
-#define  EXTI_SWIER_SWIER8                   ((uint32_t)0x00000100)        /*!< Software Interrupt on line 8 */
-#define  EXTI_SWIER_SWIER9                   ((uint32_t)0x00000200)        /*!< Software Interrupt on line 9 */
-#define  EXTI_SWIER_SWIER10                  ((uint32_t)0x00000400)        /*!< Software Interrupt on line 10 */
-#define  EXTI_SWIER_SWIER11                  ((uint32_t)0x00000800)        /*!< Software Interrupt on line 11 */
-#define  EXTI_SWIER_SWIER12                  ((uint32_t)0x00001000)        /*!< Software Interrupt on line 12 */
-#define  EXTI_SWIER_SWIER13                  ((uint32_t)0x00002000)        /*!< Software Interrupt on line 13 */
-#define  EXTI_SWIER_SWIER14                  ((uint32_t)0x00004000)        /*!< Software Interrupt on line 14 */
-#define  EXTI_SWIER_SWIER15                  ((uint32_t)0x00008000)        /*!< Software Interrupt on line 15 */
-#define  EXTI_SWIER_SWIER16                  ((uint32_t)0x00010000)        /*!< Software Interrupt on line 16 */
-#define  EXTI_SWIER_SWIER17                  ((uint32_t)0x00020000)        /*!< Software Interrupt on line 17 */
-#define  EXTI_SWIER_SWIER18                  ((uint32_t)0x00040000)        /*!< Software Interrupt on line 18 */
-#define  EXTI_SWIER_SWIER19                  ((uint32_t)0x00080000)        /*!< Software Interrupt on line 19 */
-#define  EXTI_SWIER_SWIER20                  ((uint32_t)0x00100000)        /*!< Software Interrupt on line 20 */
-#define  EXTI_SWIER_SWIER21                  ((uint32_t)0x00200000)        /*!< Software Interrupt on line 21 */
-#define  EXTI_SWIER_SWIER22                  ((uint32_t)0x00400000)        /*!< Software Interrupt on line 22 */
-#define  EXTI_SWIER_SWIER23                  ((uint32_t)0x00800000)        /*!< Software Interrupt on line 23 */
-
-/*******************  Bit definition for EXTI_PR register  ********************/
-#define  EXTI_PR_PR0                         ((uint32_t)0x00000001)        /*!< Pending bit 0 */
-#define  EXTI_PR_PR1                         ((uint32_t)0x00000002)        /*!< Pending bit 1 */
-#define  EXTI_PR_PR2                         ((uint32_t)0x00000004)        /*!< Pending bit 2 */
-#define  EXTI_PR_PR3                         ((uint32_t)0x00000008)        /*!< Pending bit 3 */
-#define  EXTI_PR_PR4                         ((uint32_t)0x00000010)        /*!< Pending bit 4 */
-#define  EXTI_PR_PR5                         ((uint32_t)0x00000020)        /*!< Pending bit 5 */
-#define  EXTI_PR_PR6                         ((uint32_t)0x00000040)        /*!< Pending bit 6 */
-#define  EXTI_PR_PR7                         ((uint32_t)0x00000080)        /*!< Pending bit 7 */
-#define  EXTI_PR_PR8                         ((uint32_t)0x00000100)        /*!< Pending bit 8 */
-#define  EXTI_PR_PR9                         ((uint32_t)0x00000200)        /*!< Pending bit 9 */
-#define  EXTI_PR_PR10                        ((uint32_t)0x00000400)        /*!< Pending bit 10 */
-#define  EXTI_PR_PR11                        ((uint32_t)0x00000800)        /*!< Pending bit 11 */
-#define  EXTI_PR_PR12                        ((uint32_t)0x00001000)        /*!< Pending bit 12 */
-#define  EXTI_PR_PR13                        ((uint32_t)0x00002000)        /*!< Pending bit 13 */
-#define  EXTI_PR_PR14                        ((uint32_t)0x00004000)        /*!< Pending bit 14 */
-#define  EXTI_PR_PR15                        ((uint32_t)0x00008000)        /*!< Pending bit 15 */
-#define  EXTI_PR_PR16                        ((uint32_t)0x00010000)        /*!< Pending bit 16 */
-#define  EXTI_PR_PR17                        ((uint32_t)0x00020000)        /*!< Pending bit 17 */
-#define  EXTI_PR_PR18                        ((uint32_t)0x00040000)        /*!< Pending bit 18 */
-#define  EXTI_PR_PR19                        ((uint32_t)0x00080000)        /*!< Pending bit 19 */
-#define  EXTI_PR_PR20                        ((uint32_t)0x00100000)        /*!< Pending bit 20 */
-#define  EXTI_PR_PR21                        ((uint32_t)0x00200000)        /*!< Pending bit 21 */
-#define  EXTI_PR_PR22                        ((uint32_t)0x00400000)        /*!< Pending bit 22 */
-#define  EXTI_PR_PR23                        ((uint32_t)0x00800000)        /*!< Pending bit 23 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                FLASH, DATA EEPROM and Option Bytes Registers               */
-/*                        (FLASH, DATA_EEPROM, OB)                            */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for FLASH_ACR register  ******************/
-#define  FLASH_ACR_LATENCY                   ((uint32_t)0x00000001)        /*!< Latency */
-#define  FLASH_ACR_PRFTEN                    ((uint32_t)0x00000002)        /*!< Prefetch Buffer Enable */
-#define  FLASH_ACR_ACC64                     ((uint32_t)0x00000004)        /*!< Access 64 bits */
-#define  FLASH_ACR_SLEEP_PD                  ((uint32_t)0x00000008)        /*!< Flash mode during sleep mode */
-#define  FLASH_ACR_RUN_PD                    ((uint32_t)0x00000010)        /*!< Flash mode during RUN mode */
-
-/*******************  Bit definition for FLASH_PECR register  ******************/
-#define FLASH_PECR_PELOCK                    ((uint32_t)0x00000001)        /*!< FLASH_PECR and Flash data Lock */
-#define FLASH_PECR_PRGLOCK                   ((uint32_t)0x00000002)        /*!< Program matrix Lock */
-#define FLASH_PECR_OPTLOCK                   ((uint32_t)0x00000004)        /*!< Option byte matrix Lock */
-#define FLASH_PECR_PROG                      ((uint32_t)0x00000008)        /*!< Program matrix selection */
-#define FLASH_PECR_DATA                      ((uint32_t)0x00000010)        /*!< Data matrix selection */
-#define FLASH_PECR_FTDW                      ((uint32_t)0x00000100)        /*!< Fixed Time Data write for Word/Half Word/Byte programming */
-#define FLASH_PECR_ERASE                     ((uint32_t)0x00000200)        /*!< Page erasing mode */
-#define FLASH_PECR_FPRG                      ((uint32_t)0x00000400)        /*!< Fast Page/Half Page programming mode */
-#define FLASH_PECR_EOPIE                     ((uint32_t)0x00010000)        /*!< End of programming interrupt */ 
-#define FLASH_PECR_ERRIE                     ((uint32_t)0x00020000)        /*!< Error interrupt */ 
-#define FLASH_PECR_OBL_LAUNCH                ((uint32_t)0x00040000)        /*!< Launch the option byte loading */ 
-
-/******************  Bit definition for FLASH_PDKEYR register  ******************/
-#define  FLASH_PDKEYR_PDKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PEKEYR register  ******************/
-#define  FLASH_PEKEYR_PEKEYR                 ((uint32_t)0xFFFFFFFF)       /*!< FLASH_PEC and data matrix Key */
-
-/******************  Bit definition for FLASH_PRGKEYR register  ******************/
-#define  FLASH_PRGKEYR_PRGKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Program matrix Key */
-
-/******************  Bit definition for FLASH_OPTKEYR register  ******************/
-#define  FLASH_OPTKEYR_OPTKEYR               ((uint32_t)0xFFFFFFFF)        /*!< Option bytes matrix Key */
-
-/******************  Bit definition for FLASH_SR register  *******************/
-#define  FLASH_SR_BSY                        ((uint32_t)0x00000001)        /*!< Busy */
-#define  FLASH_SR_EOP                        ((uint32_t)0x00000002)        /*!< End Of Programming*/
-#define  FLASH_SR_ENDHV                       ((uint32_t)0x00000004)        /*!< End of high voltage */
-#define  FLASH_SR_READY                      ((uint32_t)0x00000008)        /*!< Flash ready after low power mode */
-
-#define  FLASH_SR_WRPERR                     ((uint32_t)0x00000100)        /*!< Write protected error */
-#define  FLASH_SR_PGAERR                     ((uint32_t)0x00000200)        /*!< Programming Alignment Error */
-#define  FLASH_SR_SIZERR                     ((uint32_t)0x00000400)        /*!< Size error */
-#define  FLASH_SR_OPTVERR                    ((uint32_t)0x00000800)        /*!< Option validity error */
-#define  FLASH_SR_OPTVERRUSR                 ((uint32_t)0x00001000)        /*!< Option User validity error */
-#define  FLASH_SR_RDERR                      ((uint32_t)0x00002000)        /*!< Read protected error */
-
-/******************  Bit definition for FLASH_OBR register  *******************/
-#define  FLASH_OBR_RDPRT                     ((uint32_t)0x000000FF)        /*!< Read Protection */
-#define  FLASH_OBR_SPRMOD                    ((uint32_t)0x00000100)        /*!< Selection of protection mode of WPRi bits */
-#define  FLASH_OBR_BOR_LEV                   ((uint32_t)0x000F0000)        /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
-#define  FLASH_OBR_USER                      ((uint32_t)0x00700000)        /*!< User Option Bytes */
-#define  FLASH_OBR_IWDG_SW                   ((uint32_t)0x00100000)        /*!< IWDG_SW */
-#define  FLASH_OBR_nRST_STOP                 ((uint32_t)0x00200000)        /*!< nRST_STOP */
-#define  FLASH_OBR_nRST_STDBY                ((uint32_t)0x00400000)        /*!< nRST_STDBY */
-
-/******************  Bit definition for FLASH_WRPR register  ******************/
-#define  FLASH_WRPR1_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */
-#define  FLASH_WRPR2_WRP                      ((uint32_t)0xFFFFFFFF)        /*!< Write Protect */             
-
-/******************************************************************************/
-/*                                                                            */
-/*                            General Purpose I/O                             */
-/*                                                                            */
-/******************************************************************************/
-/******************  Bits definition for GPIO_MODER register  *****************/
-#define GPIO_MODER_MODER0          ((uint32_t)0x00000003)
-#define GPIO_MODER_MODER0_0        ((uint32_t)0x00000001)
-#define GPIO_MODER_MODER0_1        ((uint32_t)0x00000002)
-
-#define GPIO_MODER_MODER1          ((uint32_t)0x0000000C)
-#define GPIO_MODER_MODER1_0        ((uint32_t)0x00000004)
-#define GPIO_MODER_MODER1_1        ((uint32_t)0x00000008)
-
-#define GPIO_MODER_MODER2          ((uint32_t)0x00000030)
-#define GPIO_MODER_MODER2_0        ((uint32_t)0x00000010)
-#define GPIO_MODER_MODER2_1        ((uint32_t)0x00000020)
-
-#define GPIO_MODER_MODER3          ((uint32_t)0x000000C0)
-#define GPIO_MODER_MODER3_0        ((uint32_t)0x00000040)
-#define GPIO_MODER_MODER3_1        ((uint32_t)0x00000080)
-
-#define GPIO_MODER_MODER4          ((uint32_t)0x00000300)
-#define GPIO_MODER_MODER4_0        ((uint32_t)0x00000100)
-#define GPIO_MODER_MODER4_1        ((uint32_t)0x00000200)
-
-#define GPIO_MODER_MODER5          ((uint32_t)0x00000C00)
-#define GPIO_MODER_MODER5_0        ((uint32_t)0x00000400)
-#define GPIO_MODER_MODER5_1        ((uint32_t)0x00000800)
-
-#define GPIO_MODER_MODER6          ((uint32_t)0x00003000)
-#define GPIO_MODER_MODER6_0        ((uint32_t)0x00001000)
-#define GPIO_MODER_MODER6_1        ((uint32_t)0x00002000)
-
-#define GPIO_MODER_MODER7          ((uint32_t)0x0000C000)
-#define GPIO_MODER_MODER7_0        ((uint32_t)0x00004000)
-#define GPIO_MODER_MODER7_1        ((uint32_t)0x00008000)
-
-#define GPIO_MODER_MODER8          ((uint32_t)0x00030000)
-#define GPIO_MODER_MODER8_0        ((uint32_t)0x00010000)
-#define GPIO_MODER_MODER8_1        ((uint32_t)0x00020000)
-
-#define GPIO_MODER_MODER9          ((uint32_t)0x000C0000)
-#define GPIO_MODER_MODER9_0        ((uint32_t)0x00040000)
-#define GPIO_MODER_MODER9_1        ((uint32_t)0x00080000)
-
-#define GPIO_MODER_MODER10         ((uint32_t)0x00300000)
-#define GPIO_MODER_MODER10_0       ((uint32_t)0x00100000)
-#define GPIO_MODER_MODER10_1       ((uint32_t)0x00200000)
-
-#define GPIO_MODER_MODER11         ((uint32_t)0x00C00000)
-#define GPIO_MODER_MODER11_0       ((uint32_t)0x00400000)
-#define GPIO_MODER_MODER11_1       ((uint32_t)0x00800000)
-
-#define GPIO_MODER_MODER12         ((uint32_t)0x03000000)
-#define GPIO_MODER_MODER12_0       ((uint32_t)0x01000000)
-#define GPIO_MODER_MODER12_1       ((uint32_t)0x02000000)
-
-#define GPIO_MODER_MODER13         ((uint32_t)0x0C000000)
-#define GPIO_MODER_MODER13_0       ((uint32_t)0x04000000)
-#define GPIO_MODER_MODER13_1       ((uint32_t)0x08000000)
-
-#define GPIO_MODER_MODER14         ((uint32_t)0x30000000)
-#define GPIO_MODER_MODER14_0       ((uint32_t)0x10000000)
-#define GPIO_MODER_MODER14_1       ((uint32_t)0x20000000)
-
-#define GPIO_MODER_MODER15         ((uint32_t)0xC0000000)
-#define GPIO_MODER_MODER15_0       ((uint32_t)0x40000000)
-#define GPIO_MODER_MODER15_1       ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_OTYPER register  ****************/
-#define GPIO_OTYPER_OT_0           ((uint32_t)0x00000001)
-#define GPIO_OTYPER_OT_1           ((uint32_t)0x00000002)
-#define GPIO_OTYPER_OT_2           ((uint32_t)0x00000004)
-#define GPIO_OTYPER_OT_3           ((uint32_t)0x00000008)
-#define GPIO_OTYPER_OT_4           ((uint32_t)0x00000010)
-#define GPIO_OTYPER_OT_5           ((uint32_t)0x00000020)
-#define GPIO_OTYPER_OT_6           ((uint32_t)0x00000040)
-#define GPIO_OTYPER_OT_7           ((uint32_t)0x00000080)
-#define GPIO_OTYPER_OT_8           ((uint32_t)0x00000100)
-#define GPIO_OTYPER_OT_9           ((uint32_t)0x00000200)
-#define GPIO_OTYPER_OT_10          ((uint32_t)0x00000400)
-#define GPIO_OTYPER_OT_11          ((uint32_t)0x00000800)
-#define GPIO_OTYPER_OT_12          ((uint32_t)0x00001000)
-#define GPIO_OTYPER_OT_13          ((uint32_t)0x00002000)
-#define GPIO_OTYPER_OT_14          ((uint32_t)0x00004000)
-#define GPIO_OTYPER_OT_15          ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_OSPEEDR register  ***************/
-#define GPIO_OSPEEDER_OSPEEDR0     ((uint32_t)0x00000003)
-#define GPIO_OSPEEDER_OSPEEDR0_0   ((uint32_t)0x00000001)
-#define GPIO_OSPEEDER_OSPEEDR0_1   ((uint32_t)0x00000002)
-
-#define GPIO_OSPEEDER_OSPEEDR1     ((uint32_t)0x0000000C)
-#define GPIO_OSPEEDER_OSPEEDR1_0   ((uint32_t)0x00000004)
-#define GPIO_OSPEEDER_OSPEEDR1_1   ((uint32_t)0x00000008)
-
-#define GPIO_OSPEEDER_OSPEEDR2     ((uint32_t)0x00000030)
-#define GPIO_OSPEEDER_OSPEEDR2_0   ((uint32_t)0x00000010)
-#define GPIO_OSPEEDER_OSPEEDR2_1   ((uint32_t)0x00000020)
-
-#define GPIO_OSPEEDER_OSPEEDR3     ((uint32_t)0x000000C0)
-#define GPIO_OSPEEDER_OSPEEDR3_0   ((uint32_t)0x00000040)
-#define GPIO_OSPEEDER_OSPEEDR3_1   ((uint32_t)0x00000080)
-
-#define GPIO_OSPEEDER_OSPEEDR4     ((uint32_t)0x00000300)
-#define GPIO_OSPEEDER_OSPEEDR4_0   ((uint32_t)0x00000100)
-#define GPIO_OSPEEDER_OSPEEDR4_1   ((uint32_t)0x00000200)
-
-#define GPIO_OSPEEDER_OSPEEDR5     ((uint32_t)0x00000C00)
-#define GPIO_OSPEEDER_OSPEEDR5_0   ((uint32_t)0x00000400)
-#define GPIO_OSPEEDER_OSPEEDR5_1   ((uint32_t)0x00000800)
-
-#define GPIO_OSPEEDER_OSPEEDR6     ((uint32_t)0x00003000)
-#define GPIO_OSPEEDER_OSPEEDR6_0   ((uint32_t)0x00001000)
-#define GPIO_OSPEEDER_OSPEEDR6_1   ((uint32_t)0x00002000)
-
-#define GPIO_OSPEEDER_OSPEEDR7     ((uint32_t)0x0000C000)
-#define GPIO_OSPEEDER_OSPEEDR7_0   ((uint32_t)0x00004000)
-#define GPIO_OSPEEDER_OSPEEDR7_1   ((uint32_t)0x00008000)
-
-#define GPIO_OSPEEDER_OSPEEDR8     ((uint32_t)0x00030000)
-#define GPIO_OSPEEDER_OSPEEDR8_0   ((uint32_t)0x00010000)
-#define GPIO_OSPEEDER_OSPEEDR8_1   ((uint32_t)0x00020000)
-
-#define GPIO_OSPEEDER_OSPEEDR9     ((uint32_t)0x000C0000)
-#define GPIO_OSPEEDER_OSPEEDR9_0   ((uint32_t)0x00040000)
-#define GPIO_OSPEEDER_OSPEEDR9_1   ((uint32_t)0x00080000)
-
-#define GPIO_OSPEEDER_OSPEEDR10    ((uint32_t)0x00300000)
-#define GPIO_OSPEEDER_OSPEEDR10_0  ((uint32_t)0x00100000)
-#define GPIO_OSPEEDER_OSPEEDR10_1  ((uint32_t)0x00200000)
-
-#define GPIO_OSPEEDER_OSPEEDR11    ((uint32_t)0x00C00000)
-#define GPIO_OSPEEDER_OSPEEDR11_0  ((uint32_t)0x00400000)
-#define GPIO_OSPEEDER_OSPEEDR11_1  ((uint32_t)0x00800000)
-
-#define GPIO_OSPEEDER_OSPEEDR12    ((uint32_t)0x03000000)
-#define GPIO_OSPEEDER_OSPEEDR12_0  ((uint32_t)0x01000000)
-#define GPIO_OSPEEDER_OSPEEDR12_1  ((uint32_t)0x02000000)
-
-#define GPIO_OSPEEDER_OSPEEDR13    ((uint32_t)0x0C000000)
-#define GPIO_OSPEEDER_OSPEEDR13_0  ((uint32_t)0x04000000)
-#define GPIO_OSPEEDER_OSPEEDR13_1  ((uint32_t)0x08000000)
-
-#define GPIO_OSPEEDER_OSPEEDR14    ((uint32_t)0x30000000)
-#define GPIO_OSPEEDER_OSPEEDR14_0  ((uint32_t)0x10000000)
-#define GPIO_OSPEEDER_OSPEEDR14_1  ((uint32_t)0x20000000)
-
-#define GPIO_OSPEEDER_OSPEEDR15    ((uint32_t)0xC0000000)
-#define GPIO_OSPEEDER_OSPEEDR15_0  ((uint32_t)0x40000000)
-#define GPIO_OSPEEDER_OSPEEDR15_1  ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_PUPDR register  *****************/
-#define GPIO_PUPDR_PUPDR0          ((uint32_t)0x00000003)
-#define GPIO_PUPDR_PUPDR0_0        ((uint32_t)0x00000001)
-#define GPIO_PUPDR_PUPDR0_1        ((uint32_t)0x00000002)
-
-#define GPIO_PUPDR_PUPDR1          ((uint32_t)0x0000000C)
-#define GPIO_PUPDR_PUPDR1_0        ((uint32_t)0x00000004)
-#define GPIO_PUPDR_PUPDR1_1        ((uint32_t)0x00000008)
-
-#define GPIO_PUPDR_PUPDR2          ((uint32_t)0x00000030)
-#define GPIO_PUPDR_PUPDR2_0        ((uint32_t)0x00000010)
-#define GPIO_PUPDR_PUPDR2_1        ((uint32_t)0x00000020)
-
-#define GPIO_PUPDR_PUPDR3          ((uint32_t)0x000000C0)
-#define GPIO_PUPDR_PUPDR3_0        ((uint32_t)0x00000040)
-#define GPIO_PUPDR_PUPDR3_1        ((uint32_t)0x00000080)
-
-#define GPIO_PUPDR_PUPDR4          ((uint32_t)0x00000300)
-#define GPIO_PUPDR_PUPDR4_0        ((uint32_t)0x00000100)
-#define GPIO_PUPDR_PUPDR4_1        ((uint32_t)0x00000200)
-
-#define GPIO_PUPDR_PUPDR5          ((uint32_t)0x00000C00)
-#define GPIO_PUPDR_PUPDR5_0        ((uint32_t)0x00000400)
-#define GPIO_PUPDR_PUPDR5_1        ((uint32_t)0x00000800)
-
-#define GPIO_PUPDR_PUPDR6          ((uint32_t)0x00003000)
-#define GPIO_PUPDR_PUPDR6_0        ((uint32_t)0x00001000)
-#define GPIO_PUPDR_PUPDR6_1        ((uint32_t)0x00002000)
-
-#define GPIO_PUPDR_PUPDR7          ((uint32_t)0x0000C000)
-#define GPIO_PUPDR_PUPDR7_0        ((uint32_t)0x00004000)
-#define GPIO_PUPDR_PUPDR7_1        ((uint32_t)0x00008000)
-
-#define GPIO_PUPDR_PUPDR8          ((uint32_t)0x00030000)
-#define GPIO_PUPDR_PUPDR8_0        ((uint32_t)0x00010000)
-#define GPIO_PUPDR_PUPDR8_1        ((uint32_t)0x00020000)
-
-#define GPIO_PUPDR_PUPDR9          ((uint32_t)0x000C0000)
-#define GPIO_PUPDR_PUPDR9_0        ((uint32_t)0x00040000)
-#define GPIO_PUPDR_PUPDR9_1        ((uint32_t)0x00080000)
-
-#define GPIO_PUPDR_PUPDR10         ((uint32_t)0x00300000)
-#define GPIO_PUPDR_PUPDR10_0       ((uint32_t)0x00100000)
-#define GPIO_PUPDR_PUPDR10_1       ((uint32_t)0x00200000)
-
-#define GPIO_PUPDR_PUPDR11         ((uint32_t)0x00C00000)
-#define GPIO_PUPDR_PUPDR11_0       ((uint32_t)0x00400000)
-#define GPIO_PUPDR_PUPDR11_1       ((uint32_t)0x00800000)
-
-#define GPIO_PUPDR_PUPDR12         ((uint32_t)0x03000000)
-#define GPIO_PUPDR_PUPDR12_0       ((uint32_t)0x01000000)
-#define GPIO_PUPDR_PUPDR12_1       ((uint32_t)0x02000000)
-
-#define GPIO_PUPDR_PUPDR13         ((uint32_t)0x0C000000)
-#define GPIO_PUPDR_PUPDR13_0       ((uint32_t)0x04000000)
-#define GPIO_PUPDR_PUPDR13_1       ((uint32_t)0x08000000)
-
-#define GPIO_PUPDR_PUPDR14         ((uint32_t)0x30000000)
-#define GPIO_PUPDR_PUPDR14_0       ((uint32_t)0x10000000)
-#define GPIO_PUPDR_PUPDR14_1       ((uint32_t)0x20000000)
-#define GPIO_PUPDR_PUPDR15         ((uint32_t)0xC0000000)
-#define GPIO_PUPDR_PUPDR15_0       ((uint32_t)0x40000000)
-#define GPIO_PUPDR_PUPDR15_1       ((uint32_t)0x80000000)
-
-/******************  Bits definition for GPIO_IDR register  *******************/
-#define GPIO_IDR_IDR_0                       ((uint32_t)0x00000001)
-#define GPIO_IDR_IDR_1                       ((uint32_t)0x00000002)
-#define GPIO_IDR_IDR_2                       ((uint32_t)0x00000004)
-#define GPIO_IDR_IDR_3                       ((uint32_t)0x00000008)
-#define GPIO_IDR_IDR_4                       ((uint32_t)0x00000010)
-#define GPIO_IDR_IDR_5                       ((uint32_t)0x00000020)
-#define GPIO_IDR_IDR_6                       ((uint32_t)0x00000040)
-#define GPIO_IDR_IDR_7                       ((uint32_t)0x00000080)
-#define GPIO_IDR_IDR_8                       ((uint32_t)0x00000100)
-#define GPIO_IDR_IDR_9                       ((uint32_t)0x00000200)
-#define GPIO_IDR_IDR_10                      ((uint32_t)0x00000400)
-#define GPIO_IDR_IDR_11                      ((uint32_t)0x00000800)
-#define GPIO_IDR_IDR_12                      ((uint32_t)0x00001000)
-#define GPIO_IDR_IDR_13                      ((uint32_t)0x00002000)
-#define GPIO_IDR_IDR_14                      ((uint32_t)0x00004000)
-#define GPIO_IDR_IDR_15                      ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_ODR register  *******************/
-#define GPIO_ODR_ODR_0                       ((uint32_t)0x00000001)
-#define GPIO_ODR_ODR_1                       ((uint32_t)0x00000002)
-#define GPIO_ODR_ODR_2                       ((uint32_t)0x00000004)
-#define GPIO_ODR_ODR_3                       ((uint32_t)0x00000008)
-#define GPIO_ODR_ODR_4                       ((uint32_t)0x00000010)
-#define GPIO_ODR_ODR_5                       ((uint32_t)0x00000020)
-#define GPIO_ODR_ODR_6                       ((uint32_t)0x00000040)
-#define GPIO_ODR_ODR_7                       ((uint32_t)0x00000080)
-#define GPIO_ODR_ODR_8                       ((uint32_t)0x00000100)
-#define GPIO_ODR_ODR_9                       ((uint32_t)0x00000200)
-#define GPIO_ODR_ODR_10                      ((uint32_t)0x00000400)
-#define GPIO_ODR_ODR_11                      ((uint32_t)0x00000800)
-#define GPIO_ODR_ODR_12                      ((uint32_t)0x00001000)
-#define GPIO_ODR_ODR_13                      ((uint32_t)0x00002000)
-#define GPIO_ODR_ODR_14                      ((uint32_t)0x00004000)
-#define GPIO_ODR_ODR_15                      ((uint32_t)0x00008000)
-
-/******************  Bits definition for GPIO_BSRR register  ******************/
-#define GPIO_BSRR_BS_0             ((uint32_t)0x00000001)
-#define GPIO_BSRR_BS_1             ((uint32_t)0x00000002)
-#define GPIO_BSRR_BS_2             ((uint32_t)0x00000004)
-#define GPIO_BSRR_BS_3             ((uint32_t)0x00000008)
-#define GPIO_BSRR_BS_4             ((uint32_t)0x00000010)
-#define GPIO_BSRR_BS_5             ((uint32_t)0x00000020)
-#define GPIO_BSRR_BS_6             ((uint32_t)0x00000040)
-#define GPIO_BSRR_BS_7             ((uint32_t)0x00000080)
-#define GPIO_BSRR_BS_8             ((uint32_t)0x00000100)
-#define GPIO_BSRR_BS_9             ((uint32_t)0x00000200)
-#define GPIO_BSRR_BS_10            ((uint32_t)0x00000400)
-#define GPIO_BSRR_BS_11            ((uint32_t)0x00000800)
-#define GPIO_BSRR_BS_12            ((uint32_t)0x00001000)
-#define GPIO_BSRR_BS_13            ((uint32_t)0x00002000)
-#define GPIO_BSRR_BS_14            ((uint32_t)0x00004000)
-#define GPIO_BSRR_BS_15            ((uint32_t)0x00008000)
-#define GPIO_BSRR_BR_0             ((uint32_t)0x00010000)
-#define GPIO_BSRR_BR_1             ((uint32_t)0x00020000)
-#define GPIO_BSRR_BR_2             ((uint32_t)0x00040000)
-#define GPIO_BSRR_BR_3             ((uint32_t)0x00080000)
-#define GPIO_BSRR_BR_4             ((uint32_t)0x00100000)
-#define GPIO_BSRR_BR_5             ((uint32_t)0x00200000)
-#define GPIO_BSRR_BR_6             ((uint32_t)0x00400000)
-#define GPIO_BSRR_BR_7             ((uint32_t)0x00800000)
-#define GPIO_BSRR_BR_8             ((uint32_t)0x01000000)
-#define GPIO_BSRR_BR_9             ((uint32_t)0x02000000)
-#define GPIO_BSRR_BR_10            ((uint32_t)0x04000000)
-#define GPIO_BSRR_BR_11            ((uint32_t)0x08000000)
-#define GPIO_BSRR_BR_12            ((uint32_t)0x10000000)
-#define GPIO_BSRR_BR_13            ((uint32_t)0x20000000)
-#define GPIO_BSRR_BR_14            ((uint32_t)0x40000000)
-#define GPIO_BSRR_BR_15            ((uint32_t)0x80000000)
-
-/****************** Bit definition for GPIO_LCKR register  ********************/
-#define GPIO_LCKR_LCK0             ((uint32_t)0x00000001)
-#define GPIO_LCKR_LCK1             ((uint32_t)0x00000002)
-#define GPIO_LCKR_LCK2             ((uint32_t)0x00000004)
-#define GPIO_LCKR_LCK3             ((uint32_t)0x00000008)
-#define GPIO_LCKR_LCK4             ((uint32_t)0x00000010)
-#define GPIO_LCKR_LCK5             ((uint32_t)0x00000020)
-#define GPIO_LCKR_LCK6             ((uint32_t)0x00000040)
-#define GPIO_LCKR_LCK7             ((uint32_t)0x00000080)
-#define GPIO_LCKR_LCK8             ((uint32_t)0x00000100)
-#define GPIO_LCKR_LCK9             ((uint32_t)0x00000200)
-#define GPIO_LCKR_LCK10            ((uint32_t)0x00000400)
-#define GPIO_LCKR_LCK11            ((uint32_t)0x00000800)
-#define GPIO_LCKR_LCK12            ((uint32_t)0x00001000)
-#define GPIO_LCKR_LCK13            ((uint32_t)0x00002000)
-#define GPIO_LCKR_LCK14            ((uint32_t)0x00004000)
-#define GPIO_LCKR_LCK15            ((uint32_t)0x00008000)
-#define GPIO_LCKR_LCKK             ((uint32_t)0x00010000)
-
-/****************** Bit definition for GPIO_AFRL register  ********************/
-#define GPIO_AFRL_AFRL0            ((uint32_t)0x0000000F)
-#define GPIO_AFRL_AFRL1            ((uint32_t)0x000000F0)
-#define GPIO_AFRL_AFRL2            ((uint32_t)0x00000F00)
-#define GPIO_AFRL_AFRL3            ((uint32_t)0x0000F000)
-#define GPIO_AFRL_AFRL4            ((uint32_t)0x000F0000)
-#define GPIO_AFRL_AFRL5            ((uint32_t)0x00F00000)
-#define GPIO_AFRL_AFRL6            ((uint32_t)0x0F000000)
-#define GPIO_AFRL_AFRL7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_AFRH register  ********************/
-#define GPIO_AFRH_AFRH0            ((uint32_t)0x0000000F)
-#define GPIO_AFRH_AFRH1            ((uint32_t)0x000000F0)
-#define GPIO_AFRH_AFRH2            ((uint32_t)0x00000F00)
-#define GPIO_AFRH_AFRH3            ((uint32_t)0x0000F000)
-#define GPIO_AFRH_AFRH4            ((uint32_t)0x000F0000)
-#define GPIO_AFRH_AFRH5            ((uint32_t)0x00F00000)
-#define GPIO_AFRH_AFRH6            ((uint32_t)0x0F000000)
-#define GPIO_AFRH_AFRH7            ((uint32_t)0xF0000000)
-
-/****************** Bit definition for GPIO_BRR register  *********************/
-#define GPIO_BRR_BR_0              ((uint32_t)0x00000001)
-#define GPIO_BRR_BR_1              ((uint32_t)0x00000002)
-#define GPIO_BRR_BR_2              ((uint32_t)0x00000004)
-#define GPIO_BRR_BR_3              ((uint32_t)0x00000008)
-#define GPIO_BRR_BR_4              ((uint32_t)0x00000010)
-#define GPIO_BRR_BR_5              ((uint32_t)0x00000020)
-#define GPIO_BRR_BR_6              ((uint32_t)0x00000040)
-#define GPIO_BRR_BR_7              ((uint32_t)0x00000080)
-#define GPIO_BRR_BR_8              ((uint32_t)0x00000100)
-#define GPIO_BRR_BR_9              ((uint32_t)0x00000200)
-#define GPIO_BRR_BR_10             ((uint32_t)0x00000400)
-#define GPIO_BRR_BR_11             ((uint32_t)0x00000800)
-#define GPIO_BRR_BR_12             ((uint32_t)0x00001000)
-#define GPIO_BRR_BR_13             ((uint32_t)0x00002000)
-#define GPIO_BRR_BR_14             ((uint32_t)0x00004000)
-#define GPIO_BRR_BR_15             ((uint32_t)0x00008000)
-
-
-/******************************************************************************/
-/*                                                                            */
-/*                   Inter-integrated Circuit Interface (I2C)                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for I2C_CR1 register  ********************/
-#define  I2C_CR1_PE                          ((uint32_t)0x00000001)            /*!< Peripheral Enable */
-#define  I2C_CR1_SMBUS                       ((uint32_t)0x00000002)            /*!< SMBus Mode */
-#define  I2C_CR1_SMBTYPE                     ((uint32_t)0x00000008)            /*!< SMBus Type */
-#define  I2C_CR1_ENARP                       ((uint32_t)0x00000010)            /*!< ARP Enable */
-#define  I2C_CR1_ENPEC                       ((uint32_t)0x00000020)            /*!< PEC Enable */
-#define  I2C_CR1_ENGC                        ((uint32_t)0x00000040)            /*!< General Call Enable */
-#define  I2C_CR1_NOSTRETCH                   ((uint32_t)0x00000080)            /*!< Clock Stretching Disable (Slave mode) */
-#define  I2C_CR1_START                       ((uint32_t)0x00000100)            /*!< Start Generation */
-#define  I2C_CR1_STOP                        ((uint32_t)0x00000200)            /*!< Stop Generation */
-#define  I2C_CR1_ACK                         ((uint32_t)0x00000400)            /*!< Acknowledge Enable */
-#define  I2C_CR1_POS                         ((uint32_t)0x00000800)            /*!< Acknowledge/PEC Position (for data reception) */
-#define  I2C_CR1_PEC                         ((uint32_t)0x00001000)            /*!< Packet Error Checking */
-#define  I2C_CR1_ALERT                       ((uint32_t)0x00002000)            /*!< SMBus Alert */
-#define  I2C_CR1_SWRST                       ((uint32_t)0x00008000)            /*!< Software Reset */
-
-/*******************  Bit definition for I2C_CR2 register  ********************/
-#define  I2C_CR2_FREQ                        ((uint32_t)0x0000003F)            /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
-#define  I2C_CR2_FREQ_0                      ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  I2C_CR2_FREQ_1                      ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  I2C_CR2_FREQ_2                      ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  I2C_CR2_FREQ_3                      ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  I2C_CR2_FREQ_4                      ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  I2C_CR2_FREQ_5                      ((uint32_t)0x00000020)            /*!< Bit 5 */
-
-#define  I2C_CR2_ITERREN                     ((uint32_t)0x00000100)            /*!< Error Interrupt Enable */
-#define  I2C_CR2_ITEVTEN                     ((uint32_t)0x00000200)            /*!< Event Interrupt Enable */
-#define  I2C_CR2_ITBUFEN                     ((uint32_t)0x00000400)            /*!< Buffer Interrupt Enable */
-#define  I2C_CR2_DMAEN                       ((uint32_t)0x00000800)            /*!< DMA Requests Enable */
-#define  I2C_CR2_LAST                        ((uint32_t)0x00001000)            /*!< DMA Last Transfer */
-
-/*******************  Bit definition for I2C_OAR1 register  *******************/
-#define  I2C_OAR1_ADD1_7                     ((uint32_t)0x000000FE)            /*!< Interface Address */
-#define  I2C_OAR1_ADD8_9                     ((uint32_t)0x00000300)            /*!< Interface Address */
-
-#define  I2C_OAR1_ADD0                       ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  I2C_OAR1_ADD1                       ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  I2C_OAR1_ADD2                       ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  I2C_OAR1_ADD3                       ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  I2C_OAR1_ADD4                       ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  I2C_OAR1_ADD5                       ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  I2C_OAR1_ADD6                       ((uint32_t)0x00000040)            /*!< Bit 6 */
-#define  I2C_OAR1_ADD7                       ((uint32_t)0x00000080)            /*!< Bit 7 */
-#define  I2C_OAR1_ADD8                       ((uint32_t)0x00000100)            /*!< Bit 8 */
-#define  I2C_OAR1_ADD9                       ((uint32_t)0x00000200)            /*!< Bit 9 */
-
-#define  I2C_OAR1_ADDMODE                    ((uint32_t)0x00008000)            /*!< Addressing Mode (Slave mode) */
-
-/*******************  Bit definition for I2C_OAR2 register  *******************/
-#define  I2C_OAR2_ENDUAL                     ((uint32_t)0x00000001)               /*!< Dual addressing mode enable */
-#define  I2C_OAR2_ADD2                       ((uint32_t)0x000000FE)               /*!< Interface address */
-
-/********************  Bit definition for I2C_DR register  ********************/
-#define  I2C_DR_DR                           ((uint32_t)0x000000FF)               /*!< 8-bit Data Register */
-
-/*******************  Bit definition for I2C_SR1 register  ********************/
-#define  I2C_SR1_SB                          ((uint32_t)0x00000001)            /*!< Start Bit (Master mode) */
-#define  I2C_SR1_ADDR                        ((uint32_t)0x00000002)            /*!< Address sent (master mode)/matched (slave mode) */
-#define  I2C_SR1_BTF                         ((uint32_t)0x00000004)            /*!< Byte Transfer Finished */
-#define  I2C_SR1_ADD10                       ((uint32_t)0x00000008)            /*!< 10-bit header sent (Master mode) */
-#define  I2C_SR1_STOPF                       ((uint32_t)0x00000010)            /*!< Stop detection (Slave mode) */
-#define  I2C_SR1_RXNE                        ((uint32_t)0x00000040)            /*!< Data Register not Empty (receivers) */
-#define  I2C_SR1_TXE                         ((uint32_t)0x00000080)            /*!< Data Register Empty (transmitters) */
-#define  I2C_SR1_BERR                        ((uint32_t)0x00000100)            /*!< Bus Error */
-#define  I2C_SR1_ARLO                        ((uint32_t)0x00000200)            /*!< Arbitration Lost (master mode) */
-#define  I2C_SR1_AF                          ((uint32_t)0x00000400)            /*!< Acknowledge Failure */
-#define  I2C_SR1_OVR                         ((uint32_t)0x00000800)            /*!< Overrun/Underrun */
-#define  I2C_SR1_PECERR                      ((uint32_t)0x00001000)            /*!< PEC Error in reception */
-#define  I2C_SR1_TIMEOUT                     ((uint32_t)0x00004000)            /*!< Timeout or Tlow Error */
-#define  I2C_SR1_SMBALERT                    ((uint32_t)0x00008000)            /*!< SMBus Alert */
-
-/*******************  Bit definition for I2C_SR2 register  ********************/
-#define  I2C_SR2_MSL                         ((uint32_t)0x00000001)            /*!< Master/Slave */
-#define  I2C_SR2_BUSY                        ((uint32_t)0x00000002)            /*!< Bus Busy */
-#define  I2C_SR2_TRA                         ((uint32_t)0x00000004)            /*!< Transmitter/Receiver */
-#define  I2C_SR2_GENCALL                     ((uint32_t)0x00000010)            /*!< General Call Address (Slave mode) */
-#define  I2C_SR2_SMBDEFAULT                  ((uint32_t)0x00000020)            /*!< SMBus Device Default Address (Slave mode) */
-#define  I2C_SR2_SMBHOST                     ((uint32_t)0x00000040)            /*!< SMBus Host Header (Slave mode) */
-#define  I2C_SR2_DUALF                       ((uint32_t)0x00000080)            /*!< Dual Flag (Slave mode) */
-#define  I2C_SR2_PEC                         ((uint32_t)0x0000FF00)            /*!< Packet Error Checking Register */
-
-/*******************  Bit definition for I2C_CCR register  ********************/
-#define  I2C_CCR_CCR                         ((uint32_t)0x00000FFF)            /*!< Clock Control Register in Fast/Standard mode (Master mode) */
-#define  I2C_CCR_DUTY                        ((uint32_t)0x00004000)            /*!< Fast Mode Duty Cycle */
-#define  I2C_CCR_FS                          ((uint32_t)0x00008000)            /*!< I2C Master Mode Selection */
-
-/******************  Bit definition for I2C_TRISE register  *******************/
-#define  I2C_TRISE_TRISE                     ((uint32_t)0x0000003F)               /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        Independent WATCHDOG (IWDG)                         */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for IWDG_KR register  ********************/
-#define  IWDG_KR_KEY                         ((uint32_t)0x0000FFFF)            /*!< Key value (write only, read 0000h) */
-
-/*******************  Bit definition for IWDG_PR register  ********************/
-#define  IWDG_PR_PR                          ((uint32_t)0x00000007)               /*!< PR[2:0] (Prescaler divider) */
-#define  IWDG_PR_PR_0                        ((uint32_t)0x00000001)               /*!< Bit 0 */
-#define  IWDG_PR_PR_1                        ((uint32_t)0x00000002)               /*!< Bit 1 */
-#define  IWDG_PR_PR_2                        ((uint32_t)0x00000004)               /*!< Bit 2 */
-
-/*******************  Bit definition for IWDG_RLR register  *******************/
-#define  IWDG_RLR_RL                         ((uint32_t)0x00000FFF)            /*!< Watchdog counter reload value */
-
-/*******************  Bit definition for IWDG_SR register  ********************/
-#define  IWDG_SR_PVU                         ((uint32_t)0x00000001)               /*!< Watchdog prescaler value update */
-#define  IWDG_SR_RVU                         ((uint32_t)0x00000002)               /*!< Watchdog counter reload value update */
-
-/******************************************************************************/
-/*                                                                            */
-/*                          Power Control (PWR)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for PWR_CR register  ********************/
-#define  PWR_CR_LPSDSR                       ((uint32_t)0x00000001)     /*!< Low-power deepsleep/sleep/low power run */
-#define  PWR_CR_PDDS                         ((uint32_t)0x00000002)     /*!< Power Down Deepsleep */
-#define  PWR_CR_CWUF                         ((uint32_t)0x00000004)     /*!< Clear Wakeup Flag */
-#define  PWR_CR_CSBF                         ((uint32_t)0x00000008)     /*!< Clear Standby Flag */
-#define  PWR_CR_PVDE                         ((uint32_t)0x00000010)     /*!< Power Voltage Detector Enable */
-
-#define  PWR_CR_PLS                          ((uint32_t)0x000000E0)     /*!< PLS[2:0] bits (PVD Level Selection) */
-#define  PWR_CR_PLS_0                        ((uint32_t)0x00000020)     /*!< Bit 0 */
-#define  PWR_CR_PLS_1                        ((uint32_t)0x00000040)     /*!< Bit 1 */
-#define  PWR_CR_PLS_2                        ((uint32_t)0x00000080)     /*!< Bit 2 */
-
-/*!< PVD level configuration */
-#define  PWR_CR_PLS_LEV0                     ((uint32_t)0x00000000)     /*!< PVD level 0 */
-#define  PWR_CR_PLS_LEV1                     ((uint32_t)0x00000020)     /*!< PVD level 1 */
-#define  PWR_CR_PLS_LEV2                     ((uint32_t)0x00000040)     /*!< PVD level 2 */
-#define  PWR_CR_PLS_LEV3                     ((uint32_t)0x00000060)     /*!< PVD level 3 */
-#define  PWR_CR_PLS_LEV4                     ((uint32_t)0x00000080)     /*!< PVD level 4 */
-#define  PWR_CR_PLS_LEV5                     ((uint32_t)0x000000A0)     /*!< PVD level 5 */
-#define  PWR_CR_PLS_LEV6                     ((uint32_t)0x000000C0)     /*!< PVD level 6 */
-#define  PWR_CR_PLS_LEV7                     ((uint32_t)0x000000E0)     /*!< PVD level 7 */
-
-#define  PWR_CR_DBP                          ((uint32_t)0x00000100)     /*!< Disable Backup Domain write protection */
-#define  PWR_CR_ULP                          ((uint32_t)0x00000200)     /*!< Ultra Low Power mode */
-#define  PWR_CR_FWU                          ((uint32_t)0x00000400)     /*!< Fast wakeup */
-
-#define  PWR_CR_VOS                          ((uint32_t)0x00001800)     /*!< VOS[1:0] bits (Voltage scaling range selection) */
-#define  PWR_CR_VOS_0                        ((uint32_t)0x00000800)     /*!< Bit 0 */
-#define  PWR_CR_VOS_1                        ((uint32_t)0x00001000)     /*!< Bit 1 */
-#define  PWR_CR_LPRUN                        ((uint32_t)0x00004000)     /*!< Low power run mode */
-
-/*******************  Bit definition for PWR_CSR register  ********************/
-#define  PWR_CSR_WUF                         ((uint32_t)0x00000001)     /*!< Wakeup Flag */
-#define  PWR_CSR_SBF                         ((uint32_t)0x00000002)     /*!< Standby Flag */
-#define  PWR_CSR_PVDO                        ((uint32_t)0x00000004)     /*!< PVD Output */
-#define  PWR_CSR_VREFINTRDYF                 ((uint32_t)0x00000008)     /*!< Internal voltage reference (VREFINT) ready flag */
-#define  PWR_CSR_VOSF                        ((uint32_t)0x00000010)     /*!< Voltage Scaling select flag */
-#define  PWR_CSR_REGLPF                      ((uint32_t)0x00000020)     /*!< Regulator LP flag */
-
-#define  PWR_CSR_EWUP1                       ((uint32_t)0x00000100)     /*!< Enable WKUP pin 1 */
-#define  PWR_CSR_EWUP2                       ((uint32_t)0x00000200)     /*!< Enable WKUP pin 2 */
-#define  PWR_CSR_EWUP3                       ((uint32_t)0x00000400)     /*!< Enable WKUP pin 3 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                      Reset and Clock Control (RCC)                         */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bit definition for RCC_CR register  ********************/
-#define  RCC_CR_HSION                        ((uint32_t)0x00000001)        /*!< Internal High Speed clock enable */
-#define  RCC_CR_HSIRDY                       ((uint32_t)0x00000002)        /*!< Internal High Speed clock ready flag */
-
-#define  RCC_CR_MSION                        ((uint32_t)0x00000100)        /*!< Internal Multi Speed clock enable */
-#define  RCC_CR_MSIRDY                       ((uint32_t)0x00000200)        /*!< Internal Multi Speed clock ready flag */
-
-#define  RCC_CR_HSEON                        ((uint32_t)0x00010000)        /*!< External High Speed clock enable */
-#define  RCC_CR_HSERDY                       ((uint32_t)0x00020000)        /*!< External High Speed clock ready flag */
-#define  RCC_CR_HSEBYP                       ((uint32_t)0x00040000)        /*!< External High Speed clock Bypass */
-
-#define  RCC_CR_PLLON                        ((uint32_t)0x01000000)        /*!< PLL enable */
-#define  RCC_CR_PLLRDY                       ((uint32_t)0x02000000)        /*!< PLL clock ready flag */
-#define  RCC_CR_CSSON                        ((uint32_t)0x10000000)        /*!< Clock Security System enable */
-
-#define  RCC_CR_RTCPRE                       ((uint32_t)0x60000000)        /*!< RTC Prescaler */
-#define  RCC_CR_RTCPRE_0                     ((uint32_t)0x20000000)        /*!< Bit0 */
-#define  RCC_CR_RTCPRE_1                     ((uint32_t)0x40000000)        /*!< Bit1 */
-
-/********************  Bit definition for RCC_ICSCR register  *****************/
-#define  RCC_ICSCR_HSICAL                    ((uint32_t)0x000000FF)        /*!< Internal High Speed clock Calibration */
-#define  RCC_ICSCR_HSITRIM                   ((uint32_t)0x00001F00)        /*!< Internal High Speed clock trimming */
-
-#define  RCC_ICSCR_MSIRANGE                  ((uint32_t)0x0000E000)        /*!< Internal Multi Speed clock Range */
-#define  RCC_ICSCR_MSIRANGE_0                ((uint32_t)0x00000000)        /*!< Internal Multi Speed clock Range 65.536 KHz */
-#define  RCC_ICSCR_MSIRANGE_1                ((uint32_t)0x00002000)        /*!< Internal Multi Speed clock Range 131.072 KHz */
-#define  RCC_ICSCR_MSIRANGE_2                ((uint32_t)0x00004000)        /*!< Internal Multi Speed clock Range 262.144 KHz */
-#define  RCC_ICSCR_MSIRANGE_3                ((uint32_t)0x00006000)        /*!< Internal Multi Speed clock Range 524.288 KHz */
-#define  RCC_ICSCR_MSIRANGE_4                ((uint32_t)0x00008000)        /*!< Internal Multi Speed clock Range 1.048 MHz */
-#define  RCC_ICSCR_MSIRANGE_5                ((uint32_t)0x0000A000)        /*!< Internal Multi Speed clock Range 2.097 MHz */
-#define  RCC_ICSCR_MSIRANGE_6                ((uint32_t)0x0000C000)        /*!< Internal Multi Speed clock Range 4.194 MHz */
-#define  RCC_ICSCR_MSICAL                    ((uint32_t)0x00FF0000)        /*!< Internal Multi Speed clock Calibration */
-#define  RCC_ICSCR_MSITRIM                   ((uint32_t)0xFF000000)        /*!< Internal Multi Speed clock trimming */
-
-/********************  Bit definition for RCC_CFGR register  ******************/
-#define  RCC_CFGR_SW                         ((uint32_t)0x00000003)        /*!< SW[1:0] bits (System clock Switch) */
-#define  RCC_CFGR_SW_0                       ((uint32_t)0x00000001)        /*!< Bit 0 */
-#define  RCC_CFGR_SW_1                       ((uint32_t)0x00000002)        /*!< Bit 1 */
-
-/*!< SW configuration */
-#define  RCC_CFGR_SW_MSI                     ((uint32_t)0x00000000)        /*!< MSI selected as system clock */
-#define  RCC_CFGR_SW_HSI                     ((uint32_t)0x00000001)        /*!< HSI selected as system clock */
-#define  RCC_CFGR_SW_HSE                     ((uint32_t)0x00000002)        /*!< HSE selected as system clock */
-#define  RCC_CFGR_SW_PLL                     ((uint32_t)0x00000003)        /*!< PLL selected as system clock */
-
-#define  RCC_CFGR_SWS                        ((uint32_t)0x0000000C)        /*!< SWS[1:0] bits (System Clock Switch Status) */
-#define  RCC_CFGR_SWS_0                      ((uint32_t)0x00000004)        /*!< Bit 0 */
-#define  RCC_CFGR_SWS_1                      ((uint32_t)0x00000008)        /*!< Bit 1 */
-
-/*!< SWS configuration */
-#define  RCC_CFGR_SWS_MSI                    ((uint32_t)0x00000000)        /*!< MSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSI                    ((uint32_t)0x00000004)        /*!< HSI oscillator used as system clock */
-#define  RCC_CFGR_SWS_HSE                    ((uint32_t)0x00000008)        /*!< HSE oscillator used as system clock */
-#define  RCC_CFGR_SWS_PLL                    ((uint32_t)0x0000000C)        /*!< PLL used as system clock */
-
-#define  RCC_CFGR_HPRE                       ((uint32_t)0x000000F0)        /*!< HPRE[3:0] bits (AHB prescaler) */
-#define  RCC_CFGR_HPRE_0                     ((uint32_t)0x00000010)        /*!< Bit 0 */
-#define  RCC_CFGR_HPRE_1                     ((uint32_t)0x00000020)        /*!< Bit 1 */
-#define  RCC_CFGR_HPRE_2                     ((uint32_t)0x00000040)        /*!< Bit 2 */
-#define  RCC_CFGR_HPRE_3                     ((uint32_t)0x00000080)        /*!< Bit 3 */
-
-/*!< HPRE configuration */
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32_t)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_HPRE_DIV2                  ((uint32_t)0x00000080)        /*!< SYSCLK divided by 2 */
-#define  RCC_CFGR_HPRE_DIV4                  ((uint32_t)0x00000090)        /*!< SYSCLK divided by 4 */
-#define  RCC_CFGR_HPRE_DIV8                  ((uint32_t)0x000000A0)        /*!< SYSCLK divided by 8 */
-#define  RCC_CFGR_HPRE_DIV16                 ((uint32_t)0x000000B0)        /*!< SYSCLK divided by 16 */
-#define  RCC_CFGR_HPRE_DIV64                 ((uint32_t)0x000000C0)        /*!< SYSCLK divided by 64 */
-#define  RCC_CFGR_HPRE_DIV128                ((uint32_t)0x000000D0)        /*!< SYSCLK divided by 128 */
-#define  RCC_CFGR_HPRE_DIV256                ((uint32_t)0x000000E0)        /*!< SYSCLK divided by 256 */
-#define  RCC_CFGR_HPRE_DIV512                ((uint32_t)0x000000F0)        /*!< SYSCLK divided by 512 */
-
-#define  RCC_CFGR_PPRE1                      ((uint32_t)0x00000700)        /*!< PRE1[2:0] bits (APB1 prescaler) */
-#define  RCC_CFGR_PPRE1_0                    ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE1_1                    ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE1_2                    ((uint32_t)0x00000400)        /*!< Bit 2 */
-
-/*!< PPRE1 configuration */
-#define  RCC_CFGR_PPRE1_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32_t)0x00000400)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32_t)0x00000500)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE1_DIV8                 ((uint32_t)0x00000600)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE1_DIV16                ((uint32_t)0x00000700)        /*!< HCLK divided by 16 */
-
-#define  RCC_CFGR_PPRE2                      ((uint32_t)0x00003800)        /*!< PRE2[2:0] bits (APB2 prescaler) */
-#define  RCC_CFGR_PPRE2_0                    ((uint32_t)0x00000800)        /*!< Bit 0 */
-#define  RCC_CFGR_PPRE2_1                    ((uint32_t)0x00001000)        /*!< Bit 1 */
-#define  RCC_CFGR_PPRE2_2                    ((uint32_t)0x00002000)        /*!< Bit 2 */
-
-/*!< PPRE2 configuration */
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32_t)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32_t)0x00002000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE2_DIV4                 ((uint32_t)0x00002800)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV8                 ((uint32_t)0x00003000)        /*!< HCLK divided by 8 */
-#define  RCC_CFGR_PPRE2_DIV16                ((uint32_t)0x00003800)        /*!< HCLK divided by 16 */
-
-/*!< PLL entry clock source*/
-#define  RCC_CFGR_PLLSRC                     ((uint32_t)0x00010000)        /*!< PLL entry clock source */
-
-#define  RCC_CFGR_PLLSRC_HSI                 ((uint32_t)0x00000000)        /*!< HSI as PLL entry clock source */
-#define  RCC_CFGR_PLLSRC_HSE                 ((uint32_t)0x00010000)        /*!< HSE as PLL entry clock source */
-
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMUL                     ((uint32_t)0x003C0000)        /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
-#define  RCC_CFGR_PLLMUL_0                   ((uint32_t)0x00040000)        /*!< Bit 0 */
-#define  RCC_CFGR_PLLMUL_1                   ((uint32_t)0x00080000)        /*!< Bit 1 */
-#define  RCC_CFGR_PLLMUL_2                   ((uint32_t)0x00100000)        /*!< Bit 2 */
-#define  RCC_CFGR_PLLMUL_3                   ((uint32_t)0x00200000)        /*!< Bit 3 */
-
-/*!< PLLMUL configuration */
-#define  RCC_CFGR_PLLMUL3                    ((uint32_t)0x00000000)        /*!< PLL input clock * 3 */
-#define  RCC_CFGR_PLLMUL4                    ((uint32_t)0x00040000)        /*!< PLL input clock * 4 */
-#define  RCC_CFGR_PLLMUL6                    ((uint32_t)0x00080000)        /*!< PLL input clock * 6 */
-#define  RCC_CFGR_PLLMUL8                    ((uint32_t)0x000C0000)        /*!< PLL input clock * 8 */
-#define  RCC_CFGR_PLLMUL12                   ((uint32_t)0x00100000)        /*!< PLL input clock * 12 */
-#define  RCC_CFGR_PLLMUL16                   ((uint32_t)0x00140000)        /*!< PLL input clock * 16 */
-#define  RCC_CFGR_PLLMUL24                   ((uint32_t)0x00180000)        /*!< PLL input clock * 24 */
-#define  RCC_CFGR_PLLMUL32                   ((uint32_t)0x001C0000)        /*!< PLL input clock * 32 */
-#define  RCC_CFGR_PLLMUL48                   ((uint32_t)0x00200000)        /*!< PLL input clock * 48 */
-
-/*!< PLLDIV configuration */
-#define  RCC_CFGR_PLLDIV                     ((uint32_t)0x00C00000)        /*!< PLLDIV[1:0] bits (PLL Output Division) */
-#define  RCC_CFGR_PLLDIV_0                   ((uint32_t)0x00400000)        /*!< Bit0 */
-#define  RCC_CFGR_PLLDIV_1                   ((uint32_t)0x00800000)        /*!< Bit1 */
-
-
-/*!< PLLDIV configuration */
-#define  RCC_CFGR_PLLDIV1                    ((uint32_t)0x00000000)        /*!< PLL clock output = CKVCO / 1 */
-#define  RCC_CFGR_PLLDIV2                    ((uint32_t)0x00400000)        /*!< PLL clock output = CKVCO / 2 */
-#define  RCC_CFGR_PLLDIV3                    ((uint32_t)0x00800000)        /*!< PLL clock output = CKVCO / 3 */
-#define  RCC_CFGR_PLLDIV4                    ((uint32_t)0x00C00000)        /*!< PLL clock output = CKVCO / 4 */
-
-
-#define  RCC_CFGR_MCOSEL                     ((uint32_t)0x07000000)        /*!< MCO[2:0] bits (Microcontroller Clock Output) */
-#define  RCC_CFGR_MCOSEL_0                   ((uint32_t)0x01000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCOSEL_1                   ((uint32_t)0x02000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCOSEL_2                   ((uint32_t)0x04000000)        /*!< Bit 2 */
-
-/*!< MCO configuration */
-#define  RCC_CFGR_MCO_NOCLOCK                ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CFGR_MCO_SYSCLK                 ((uint32_t)0x01000000)        /*!< System clock selected */
-#define  RCC_CFGR_MCO_HSI                    ((uint32_t)0x02000000)        /*!< Internal 16 MHz RC oscillator clock selected */
-#define  RCC_CFGR_MCO_MSI                    ((uint32_t)0x03000000)        /*!< Internal Medium Speed RC oscillator clock selected */
-#define  RCC_CFGR_MCO_HSE                    ((uint32_t)0x04000000)        /*!< External 1-25 MHz oscillator clock selected */
-#define  RCC_CFGR_MCO_PLL                    ((uint32_t)0x05000000)        /*!< PLL clock divided */
-#define  RCC_CFGR_MCO_LSI                    ((uint32_t)0x06000000)        /*!< LSI selected */
-#define  RCC_CFGR_MCO_LSE                    ((uint32_t)0x07000000)        /*!< LSE selected */
-
-#define  RCC_CFGR_MCOPRE                     ((uint32_t)0x70000000)        /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
-#define  RCC_CFGR_MCOPRE_0                   ((uint32_t)0x10000000)        /*!< Bit 0 */
-#define  RCC_CFGR_MCOPRE_1                   ((uint32_t)0x20000000)        /*!< Bit 1 */
-#define  RCC_CFGR_MCOPRE_2                   ((uint32_t)0x40000000)        /*!< Bit 2 */
-
-/*!< MCO Prescaler configuration */
-#define  RCC_CFGR_MCO_DIV1                   ((uint32_t)0x00000000)        /*!< MCO Clock divided by 1 */
-#define  RCC_CFGR_MCO_DIV2                   ((uint32_t)0x10000000)        /*!< MCO Clock divided by 2 */
-#define  RCC_CFGR_MCO_DIV4                   ((uint32_t)0x20000000)        /*!< MCO Clock divided by 4 */
-#define  RCC_CFGR_MCO_DIV8                   ((uint32_t)0x30000000)        /*!< MCO Clock divided by 8 */
-#define  RCC_CFGR_MCO_DIV16                  ((uint32_t)0x40000000)        /*!< MCO Clock divided by 16 */
-
-/*!<******************  Bit definition for RCC_CIR register  ********************/
-#define  RCC_CIR_LSIRDYF                     ((uint32_t)0x00000001)        /*!< LSI Ready Interrupt flag */
-#define  RCC_CIR_LSERDYF                     ((uint32_t)0x00000002)        /*!< LSE Ready Interrupt flag */
-#define  RCC_CIR_HSIRDYF                     ((uint32_t)0x00000004)        /*!< HSI Ready Interrupt flag */
-#define  RCC_CIR_HSERDYF                     ((uint32_t)0x00000008)        /*!< HSE Ready Interrupt flag */
-#define  RCC_CIR_PLLRDYF                     ((uint32_t)0x00000010)        /*!< PLL Ready Interrupt flag */
-#define  RCC_CIR_MSIRDYF                     ((uint32_t)0x00000020)        /*!< MSI Ready Interrupt flag */
-#define  RCC_CIR_LSECSS                      ((uint32_t)0x00000040)        /*!< LSE CSS Interrupt flag */
-#define  RCC_CIR_CSSF                        ((uint32_t)0x00000080)        /*!< Clock Security System Interrupt flag */
-
-#define  RCC_CIR_LSIRDYIE                    ((uint32_t)0x00000100)        /*!< LSI Ready Interrupt Enable */
-#define  RCC_CIR_LSERDYIE                    ((uint32_t)0x00000200)        /*!< LSE Ready Interrupt Enable */
-#define  RCC_CIR_HSIRDYIE                    ((uint32_t)0x00000400)        /*!< HSI Ready Interrupt Enable */
-#define  RCC_CIR_HSERDYIE                    ((uint32_t)0x00000800)        /*!< HSE Ready Interrupt Enable */
-#define  RCC_CIR_PLLRDYIE                    ((uint32_t)0x00001000)        /*!< PLL Ready Interrupt Enable */
-#define  RCC_CIR_MSIRDYIE                    ((uint32_t)0x00002000)        /*!< MSI Ready Interrupt Enable */
-#define  RCC_CIR_LSECSSIE                    ((uint32_t)0x00004000)        /*!< LSE CSS Interrupt Enable */
-
-#define  RCC_CIR_LSIRDYC                     ((uint32_t)0x00010000)        /*!< LSI Ready Interrupt Clear */
-#define  RCC_CIR_LSERDYC                     ((uint32_t)0x00020000)        /*!< LSE Ready Interrupt Clear */
-#define  RCC_CIR_HSIRDYC                     ((uint32_t)0x00040000)        /*!< HSI Ready Interrupt Clear */
-#define  RCC_CIR_HSERDYC                     ((uint32_t)0x00080000)        /*!< HSE Ready Interrupt Clear */
-#define  RCC_CIR_PLLRDYC                     ((uint32_t)0x00100000)        /*!< PLL Ready Interrupt Clear */
-#define  RCC_CIR_MSIRDYC                     ((uint32_t)0x00200000)        /*!< MSI Ready Interrupt Clear */
-#define  RCC_CIR_LSECSSC                     ((uint32_t)0x00400000)        /*!< LSE CSS Interrupt Clear */
-#define  RCC_CIR_CSSC                        ((uint32_t)0x00800000)        /*!< Clock Security System Interrupt Clear */
-
-/*****************  Bit definition for RCC_AHBRSTR register  ******************/
-#define  RCC_AHBRSTR_GPIOARST                ((uint32_t)0x00000001)        /*!< GPIO port A reset */
-#define  RCC_AHBRSTR_GPIOBRST                ((uint32_t)0x00000002)        /*!< GPIO port B reset */
-#define  RCC_AHBRSTR_GPIOCRST                ((uint32_t)0x00000004)        /*!< GPIO port C reset */
-#define  RCC_AHBRSTR_GPIODRST                ((uint32_t)0x00000008)        /*!< GPIO port D reset */
-#define  RCC_AHBRSTR_GPIOERST                ((uint32_t)0x00000010)        /*!< GPIO port E reset */
-#define  RCC_AHBRSTR_GPIOHRST                ((uint32_t)0x00000020)        /*!< GPIO port H reset */
-#define  RCC_AHBRSTR_CRCRST                  ((uint32_t)0x00001000)        /*!< CRC reset */
-#define  RCC_AHBRSTR_FLITFRST                ((uint32_t)0x00008000)        /*!< FLITF reset */
-#define  RCC_AHBRSTR_DMA1RST                 ((uint32_t)0x01000000)        /*!< DMA1 reset */
-#define  RCC_AHBRSTR_DMA2RST                 ((uint32_t)0x02000000)        /*!< DMA2 reset */
- 
-/*****************  Bit definition for RCC_APB2RSTR register  *****************/
-#define  RCC_APB2RSTR_SYSCFGRST              ((uint32_t)0x00000001)        /*!< System Configuration SYSCFG reset */
-#define  RCC_APB2RSTR_TIM9RST                ((uint32_t)0x00000004)        /*!< TIM9 reset */
-#define  RCC_APB2RSTR_TIM10RST               ((uint32_t)0x00000008)        /*!< TIM10 reset */
-#define  RCC_APB2RSTR_TIM11RST               ((uint32_t)0x00000010)        /*!< TIM11 reset */
-#define  RCC_APB2RSTR_ADC1RST                ((uint32_t)0x00000200)        /*!< ADC1 reset */
-#define  RCC_APB2RSTR_SPI1RST                ((uint32_t)0x00001000)        /*!< SPI1 reset */
-#define  RCC_APB2RSTR_USART1RST              ((uint32_t)0x00004000)        /*!< USART1 reset */
-
-/*****************  Bit definition for RCC_APB1RSTR register  *****************/
-#define  RCC_APB1RSTR_TIM2RST                ((uint32_t)0x00000001)        /*!< Timer 2 reset */
-#define  RCC_APB1RSTR_TIM3RST                ((uint32_t)0x00000002)        /*!< Timer 3 reset */
-#define  RCC_APB1RSTR_TIM4RST                ((uint32_t)0x00000004)        /*!< Timer 4 reset */
-#define  RCC_APB1RSTR_TIM5RST                ((uint32_t)0x00000008)        /*!< Timer 5 reset */
-#define  RCC_APB1RSTR_TIM6RST                ((uint32_t)0x00000010)        /*!< Timer 6 reset */
-#define  RCC_APB1RSTR_TIM7RST                ((uint32_t)0x00000020)        /*!< Timer 7 reset */
-#define  RCC_APB1RSTR_WWDGRST                ((uint32_t)0x00000800)        /*!< Window Watchdog reset */
-#define  RCC_APB1RSTR_SPI2RST                ((uint32_t)0x00004000)        /*!< SPI 2 reset */
-#define  RCC_APB1RSTR_SPI3RST                ((uint32_t)0x00008000)        /*!< SPI 3 reset */
-#define  RCC_APB1RSTR_USART2RST              ((uint32_t)0x00020000)        /*!< USART 2 reset */
-#define  RCC_APB1RSTR_USART3RST              ((uint32_t)0x00040000)        /*!< USART 3 reset */
-#define  RCC_APB1RSTR_I2C1RST                ((uint32_t)0x00200000)        /*!< I2C 1 reset */
-#define  RCC_APB1RSTR_I2C2RST                ((uint32_t)0x00400000)        /*!< I2C 2 reset */
-#define  RCC_APB1RSTR_USBRST                 ((uint32_t)0x00800000)        /*!< USB reset */
-#define  RCC_APB1RSTR_PWRRST                 ((uint32_t)0x10000000)        /*!< Power interface reset */
-#define  RCC_APB1RSTR_DACRST                 ((uint32_t)0x20000000)        /*!< DAC interface reset */
-#define  RCC_APB1RSTR_COMPRST                ((uint32_t)0x80000000)        /*!< Comparator interface reset */
-
-/******************  Bit definition for RCC_AHBENR register  ******************/
-#define  RCC_AHBENR_GPIOAEN                  ((uint32_t)0x00000001)        /*!< GPIO port A clock enable */
-#define  RCC_AHBENR_GPIOBEN                  ((uint32_t)0x00000002)        /*!< GPIO port B clock enable */
-#define  RCC_AHBENR_GPIOCEN                  ((uint32_t)0x00000004)        /*!< GPIO port C clock enable */
-#define  RCC_AHBENR_GPIODEN                  ((uint32_t)0x00000008)        /*!< GPIO port D clock enable */
-#define  RCC_AHBENR_GPIOEEN                  ((uint32_t)0x00000010)        /*!< GPIO port E clock enable */
-#define  RCC_AHBENR_GPIOHEN                  ((uint32_t)0x00000020)        /*!< GPIO port H clock enable */
-#define  RCC_AHBENR_CRCEN                    ((uint32_t)0x00001000)        /*!< CRC clock enable */
-#define  RCC_AHBENR_FLITFEN                  ((uint32_t)0x00008000)        /*!< FLITF clock enable (has effect only when
-                                                                                the Flash memory is in power down mode) */
-#define  RCC_AHBENR_DMA1EN                   ((uint32_t)0x01000000)        /*!< DMA1 clock enable */
-#define  RCC_AHBENR_DMA2EN                   ((uint32_t)0x02000000)        /*!< DMA2 clock enable */
-
-/******************  Bit definition for RCC_APB2ENR register  *****************/
-#define  RCC_APB2ENR_SYSCFGEN                ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enable */
-#define  RCC_APB2ENR_TIM9EN                  ((uint32_t)0x00000004)         /*!< TIM9 interface clock enable */
-#define  RCC_APB2ENR_TIM10EN                 ((uint32_t)0x00000008)         /*!< TIM10 interface clock enable */
-#define  RCC_APB2ENR_TIM11EN                 ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enable */
-#define  RCC_APB2ENR_ADC1EN                  ((uint32_t)0x00000200)         /*!< ADC1 clock enable */
-#define  RCC_APB2ENR_SPI1EN                  ((uint32_t)0x00001000)         /*!< SPI1 clock enable */
-#define  RCC_APB2ENR_USART1EN                ((uint32_t)0x00004000)         /*!< USART1 clock enable */
-
-/*****************  Bit definition for RCC_APB1ENR register  ******************/
-#define  RCC_APB1ENR_TIM2EN                  ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled*/
-#define  RCC_APB1ENR_TIM3EN                  ((uint32_t)0x00000002)        /*!< Timer 3 clock enable */
-#define  RCC_APB1ENR_TIM4EN                  ((uint32_t)0x00000004)        /*!< Timer 4 clock enable */
-#define  RCC_APB1ENR_TIM5EN                  ((uint32_t)0x00000008)        /*!< Timer 5 clock enable */
-#define  RCC_APB1ENR_TIM6EN                  ((uint32_t)0x00000010)        /*!< Timer 6 clock enable */
-#define  RCC_APB1ENR_TIM7EN                  ((uint32_t)0x00000020)        /*!< Timer 7 clock enable */
-#define  RCC_APB1ENR_WWDGEN                  ((uint32_t)0x00000800)        /*!< Window Watchdog clock enable */
-#define  RCC_APB1ENR_SPI2EN                  ((uint32_t)0x00004000)        /*!< SPI 2 clock enable */
-#define  RCC_APB1ENR_SPI3EN                  ((uint32_t)0x00008000)        /*!< SPI 3 clock enable */
-#define  RCC_APB1ENR_USART2EN                ((uint32_t)0x00020000)        /*!< USART 2 clock enable */
-#define  RCC_APB1ENR_USART3EN                ((uint32_t)0x00040000)        /*!< USART 3 clock enable */
-#define  RCC_APB1ENR_I2C1EN                  ((uint32_t)0x00200000)        /*!< I2C 1 clock enable */
-#define  RCC_APB1ENR_I2C2EN                  ((uint32_t)0x00400000)        /*!< I2C 2 clock enable */
-#define  RCC_APB1ENR_USBEN                   ((uint32_t)0x00800000)        /*!< USB clock enable */
-#define  RCC_APB1ENR_PWREN                   ((uint32_t)0x10000000)        /*!< Power interface clock enable */
-#define  RCC_APB1ENR_DACEN                   ((uint32_t)0x20000000)        /*!< DAC interface clock enable */
-#define  RCC_APB1ENR_COMPEN                  ((uint32_t)0x80000000)        /*!< Comparator interface clock enable */
-
-/******************  Bit definition for RCC_AHBLPENR register  ****************/
-#define  RCC_AHBLPENR_GPIOALPEN              ((uint32_t)0x00000001)        /*!< GPIO port A clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOBLPEN              ((uint32_t)0x00000002)        /*!< GPIO port B clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOCLPEN              ((uint32_t)0x00000004)        /*!< GPIO port C clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIODLPEN              ((uint32_t)0x00000008)        /*!< GPIO port D clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOELPEN              ((uint32_t)0x00000010)        /*!< GPIO port E clock enabled in sleep mode */
-#define  RCC_AHBLPENR_GPIOHLPEN              ((uint32_t)0x00000020)        /*!< GPIO port H clock enabled in sleep mode */
-#define  RCC_AHBLPENR_CRCLPEN                ((uint32_t)0x00001000)        /*!< CRC clock enabled in sleep mode */
-#define  RCC_AHBLPENR_FLITFLPEN              ((uint32_t)0x00008000)        /*!< Flash Interface clock enabled in sleep mode
-                                                                                (has effect only when the Flash memory is
-                                                                                 in power down mode) */
-#define  RCC_AHBLPENR_SRAMLPEN               ((uint32_t)0x00010000)        /*!< SRAM clock enabled in sleep mode */
-#define  RCC_AHBLPENR_DMA1LPEN               ((uint32_t)0x01000000)        /*!< DMA1 clock enabled in sleep mode */
-#define  RCC_AHBLPENR_DMA2LPEN               ((uint32_t)0x02000000)        /*!< DMA2 clock enabled in sleep mode */
-
-/******************  Bit definition for RCC_APB2LPENR register  ***************/
-#define  RCC_APB2LPENR_SYSCFGLPEN            ((uint32_t)0x00000001)         /*!< System Configuration SYSCFG clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM9LPEN              ((uint32_t)0x00000004)         /*!< TIM9 interface clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM10LPEN             ((uint32_t)0x00000008)         /*!< TIM10 interface clock enabled in sleep mode */
-#define  RCC_APB2LPENR_TIM11LPEN             ((uint32_t)0x00000010)         /*!< TIM11 Timer clock enabled in sleep mode */
-#define  RCC_APB2LPENR_ADC1LPEN              ((uint32_t)0x00000200)         /*!< ADC1 clock enabled in sleep mode */
-#define  RCC_APB2LPENR_SPI1LPEN              ((uint32_t)0x00001000)         /*!< SPI1 clock enabled in sleep mode */
-#define  RCC_APB2LPENR_USART1LPEN            ((uint32_t)0x00004000)         /*!< USART1 clock enabled in sleep mode */
-
-/*****************  Bit definition for RCC_APB1LPENR register  ****************/
-#define  RCC_APB1LPENR_TIM2LPEN              ((uint32_t)0x00000001)        /*!< Timer 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM3LPEN              ((uint32_t)0x00000002)        /*!< Timer 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM4LPEN              ((uint32_t)0x00000004)        /*!< Timer 4 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM5LPEN              ((uint32_t)0x00000008)        /*!< Timer 5 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM6LPEN              ((uint32_t)0x00000010)        /*!< Timer 6 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_TIM7LPEN              ((uint32_t)0x00000020)        /*!< Timer 7 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_WWDGLPEN              ((uint32_t)0x00000800)        /*!< Window Watchdog clock enabled in sleep mode */
-#define  RCC_APB1LPENR_SPI2LPEN              ((uint32_t)0x00004000)        /*!< SPI 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_SPI3LPEN              ((uint32_t)0x00008000)        /*!< SPI 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USART2LPEN            ((uint32_t)0x00020000)        /*!< USART 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USART3LPEN            ((uint32_t)0x00040000)        /*!< USART 3 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_I2C1LPEN              ((uint32_t)0x00200000)        /*!< I2C 1 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_I2C2LPEN              ((uint32_t)0x00400000)        /*!< I2C 2 clock enabled in sleep mode */
-#define  RCC_APB1LPENR_USBLPEN               ((uint32_t)0x00800000)        /*!< USB clock enabled in sleep mode */
-#define  RCC_APB1LPENR_PWRLPEN               ((uint32_t)0x10000000)        /*!< Power interface clock enabled in sleep mode */
-#define  RCC_APB1LPENR_DACLPEN               ((uint32_t)0x20000000)        /*!< DAC interface clock enabled in sleep mode */
-#define  RCC_APB1LPENR_COMPLPEN              ((uint32_t)0x80000000)        /*!< Comparator interface clock enabled in sleep mode*/
-
-/*******************  Bit definition for RCC_CSR register  ********************/
-#define  RCC_CSR_LSION                      ((uint32_t)0x00000001)        /*!< Internal Low Speed oscillator enable */
-#define  RCC_CSR_LSIRDY                     ((uint32_t)0x00000002)        /*!< Internal Low Speed oscillator Ready */
-
-#define  RCC_CSR_LSEON                      ((uint32_t)0x00000100)        /*!< External Low Speed oscillator enable */
-#define  RCC_CSR_LSERDY                     ((uint32_t)0x00000200)        /*!< External Low Speed oscillator Ready */
-#define  RCC_CSR_LSEBYP                     ((uint32_t)0x00000400)        /*!< External Low Speed oscillator Bypass */
-
-#define  RCC_CSR_LSECSSON                   ((uint32_t)0x00000800)        /*!< External Low Speed oscillator CSS Enable */
-#define  RCC_CSR_LSECSSD                    ((uint32_t)0x00001000)        /*!< External Low Speed oscillator CSS Detected */
-
-#define  RCC_CSR_RTCSEL                     ((uint32_t)0x00030000)        /*!< RTCSEL[1:0] bits (RTC clock source selection) */
-#define  RCC_CSR_RTCSEL_0                   ((uint32_t)0x00010000)        /*!< Bit 0 */
-#define  RCC_CSR_RTCSEL_1                   ((uint32_t)0x00020000)        /*!< Bit 1 */
-
-/*!< RTC congiguration */
-#define  RCC_CSR_RTCSEL_NOCLOCK             ((uint32_t)0x00000000)        /*!< No clock */
-#define  RCC_CSR_RTCSEL_LSE                 ((uint32_t)0x00010000)        /*!< LSE oscillator clock used as RTC clock */
-#define  RCC_CSR_RTCSEL_LSI                 ((uint32_t)0x00020000)        /*!< LSI oscillator clock used as RTC clock */
-#define  RCC_CSR_RTCSEL_HSE                 ((uint32_t)0x00030000)        /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
-
-#define  RCC_CSR_RTCEN                      ((uint32_t)0x00400000)        /*!< RTC clock enable */
-#define  RCC_CSR_RTCRST                     ((uint32_t)0x00800000)        /*!< RTC reset  */
- 
-#define  RCC_CSR_RMVF                       ((uint32_t)0x01000000)        /*!< Remove reset flag */
-#define  RCC_CSR_OBLRSTF                    ((uint32_t)0x02000000)        /*!< Option Bytes Loader reset flag */
-#define  RCC_CSR_PINRSTF                    ((uint32_t)0x04000000)        /*!< PIN reset flag */
-#define  RCC_CSR_PORRSTF                    ((uint32_t)0x08000000)        /*!< POR/PDR reset flag */
-#define  RCC_CSR_SFTRSTF                    ((uint32_t)0x10000000)        /*!< Software Reset flag */
-#define  RCC_CSR_IWDGRSTF                   ((uint32_t)0x20000000)        /*!< Independent Watchdog reset flag */
-#define  RCC_CSR_WWDGRSTF                   ((uint32_t)0x40000000)        /*!< Window watchdog reset flag */
-#define  RCC_CSR_LPWRRSTF                   ((uint32_t)0x80000000)        /*!< Low-Power reset flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                           Real-Time Clock (RTC)                            */
-/*                                                                            */
-/******************************************************************************/
-/********************  Bits definition for RTC_TR register  *******************/
-#define RTC_TR_PM                            ((uint32_t)0x00400000)
-#define RTC_TR_HT                            ((uint32_t)0x00300000)
-#define RTC_TR_HT_0                          ((uint32_t)0x00100000)
-#define RTC_TR_HT_1                          ((uint32_t)0x00200000)
-#define RTC_TR_HU                            ((uint32_t)0x000F0000)
-#define RTC_TR_HU_0                          ((uint32_t)0x00010000)
-#define RTC_TR_HU_1                          ((uint32_t)0x00020000)
-#define RTC_TR_HU_2                          ((uint32_t)0x00040000)
-#define RTC_TR_HU_3                          ((uint32_t)0x00080000)
-#define RTC_TR_MNT                           ((uint32_t)0x00007000)
-#define RTC_TR_MNT_0                         ((uint32_t)0x00001000)
-#define RTC_TR_MNT_1                         ((uint32_t)0x00002000)
-#define RTC_TR_MNT_2                         ((uint32_t)0x00004000)
-#define RTC_TR_MNU                           ((uint32_t)0x00000F00)
-#define RTC_TR_MNU_0                         ((uint32_t)0x00000100)
-#define RTC_TR_MNU_1                         ((uint32_t)0x00000200)
-#define RTC_TR_MNU_2                         ((uint32_t)0x00000400)
-#define RTC_TR_MNU_3                         ((uint32_t)0x00000800)
-#define RTC_TR_ST                            ((uint32_t)0x00000070)
-#define RTC_TR_ST_0                          ((uint32_t)0x00000010)
-#define RTC_TR_ST_1                          ((uint32_t)0x00000020)
-#define RTC_TR_ST_2                          ((uint32_t)0x00000040)
-#define RTC_TR_SU                            ((uint32_t)0x0000000F)
-#define RTC_TR_SU_0                          ((uint32_t)0x00000001)
-#define RTC_TR_SU_1                          ((uint32_t)0x00000002)
-#define RTC_TR_SU_2                          ((uint32_t)0x00000004)
-#define RTC_TR_SU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_DR register  *******************/
-#define RTC_DR_YT                            ((uint32_t)0x00F00000)
-#define RTC_DR_YT_0                          ((uint32_t)0x00100000)
-#define RTC_DR_YT_1                          ((uint32_t)0x00200000)
-#define RTC_DR_YT_2                          ((uint32_t)0x00400000)
-#define RTC_DR_YT_3                          ((uint32_t)0x00800000)
-#define RTC_DR_YU                            ((uint32_t)0x000F0000)
-#define RTC_DR_YU_0                          ((uint32_t)0x00010000)
-#define RTC_DR_YU_1                          ((uint32_t)0x00020000)
-#define RTC_DR_YU_2                          ((uint32_t)0x00040000)
-#define RTC_DR_YU_3                          ((uint32_t)0x00080000)
-#define RTC_DR_WDU                           ((uint32_t)0x0000E000)
-#define RTC_DR_WDU_0                         ((uint32_t)0x00002000)
-#define RTC_DR_WDU_1                         ((uint32_t)0x00004000)
-#define RTC_DR_WDU_2                         ((uint32_t)0x00008000)
-#define RTC_DR_MT                            ((uint32_t)0x00001000)
-#define RTC_DR_MU                            ((uint32_t)0x00000F00)
-#define RTC_DR_MU_0                          ((uint32_t)0x00000100)
-#define RTC_DR_MU_1                          ((uint32_t)0x00000200)
-#define RTC_DR_MU_2                          ((uint32_t)0x00000400)
-#define RTC_DR_MU_3                          ((uint32_t)0x00000800)
-#define RTC_DR_DT                            ((uint32_t)0x00000030)
-#define RTC_DR_DT_0                          ((uint32_t)0x00000010)
-#define RTC_DR_DT_1                          ((uint32_t)0x00000020)
-#define RTC_DR_DU                            ((uint32_t)0x0000000F)
-#define RTC_DR_DU_0                          ((uint32_t)0x00000001)
-#define RTC_DR_DU_1                          ((uint32_t)0x00000002)
-#define RTC_DR_DU_2                          ((uint32_t)0x00000004)
-#define RTC_DR_DU_3                          ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_CR register  *******************/
-#define RTC_CR_COE                           ((uint32_t)0x00800000)
-#define RTC_CR_OSEL                          ((uint32_t)0x00600000)
-#define RTC_CR_OSEL_0                        ((uint32_t)0x00200000)
-#define RTC_CR_OSEL_1                        ((uint32_t)0x00400000)
-#define RTC_CR_POL                           ((uint32_t)0x00100000)
-#define RTC_CR_COSEL                         ((uint32_t)0x00080000)
-#define RTC_CR_BCK                           ((uint32_t)0x00040000)
-#define RTC_CR_SUB1H                         ((uint32_t)0x00020000)
-#define RTC_CR_ADD1H                         ((uint32_t)0x00010000)
-#define RTC_CR_TSIE                          ((uint32_t)0x00008000)
-#define RTC_CR_WUTIE                         ((uint32_t)0x00004000)
-#define RTC_CR_ALRBIE                        ((uint32_t)0x00002000)
-#define RTC_CR_ALRAIE                        ((uint32_t)0x00001000)
-#define RTC_CR_TSE                           ((uint32_t)0x00000800)
-#define RTC_CR_WUTE                          ((uint32_t)0x00000400)
-#define RTC_CR_ALRBE                         ((uint32_t)0x00000200)
-#define RTC_CR_ALRAE                         ((uint32_t)0x00000100)
-#define RTC_CR_DCE                           ((uint32_t)0x00000080)
-#define RTC_CR_FMT                           ((uint32_t)0x00000040)
-#define RTC_CR_BYPSHAD                       ((uint32_t)0x00000020)
-#define RTC_CR_REFCKON                       ((uint32_t)0x00000010)
-#define RTC_CR_TSEDGE                        ((uint32_t)0x00000008)
-#define RTC_CR_WUCKSEL                       ((uint32_t)0x00000007)
-#define RTC_CR_WUCKSEL_0                     ((uint32_t)0x00000001)
-#define RTC_CR_WUCKSEL_1                     ((uint32_t)0x00000002)
-#define RTC_CR_WUCKSEL_2                     ((uint32_t)0x00000004)
-
-/********************  Bits definition for RTC_ISR register  ******************/
-#define RTC_ISR_RECALPF                      ((uint32_t)0x00010000)
-#define RTC_ISR_TAMP3F                       ((uint32_t)0x00008000)
-#define RTC_ISR_TAMP2F                       ((uint32_t)0x00004000)
-#define RTC_ISR_TAMP1F                       ((uint32_t)0x00002000)
-#define RTC_ISR_TSOVF                        ((uint32_t)0x00001000)
-#define RTC_ISR_TSF                          ((uint32_t)0x00000800)
-#define RTC_ISR_WUTF                         ((uint32_t)0x00000400)
-#define RTC_ISR_ALRBF                        ((uint32_t)0x00000200)
-#define RTC_ISR_ALRAF                        ((uint32_t)0x00000100)
-#define RTC_ISR_INIT                         ((uint32_t)0x00000080)
-#define RTC_ISR_INITF                        ((uint32_t)0x00000040)
-#define RTC_ISR_RSF                          ((uint32_t)0x00000020)
-#define RTC_ISR_INITS                        ((uint32_t)0x00000010)
-#define RTC_ISR_SHPF                         ((uint32_t)0x00000008)
-#define RTC_ISR_WUTWF                        ((uint32_t)0x00000004)
-#define RTC_ISR_ALRBWF                       ((uint32_t)0x00000002)
-#define RTC_ISR_ALRAWF                       ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_PRER register  *****************/
-#define RTC_PRER_PREDIV_A                    ((uint32_t)0x007F0000)
-#define RTC_PRER_PREDIV_S                    ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_WUTR register  *****************/
-#define RTC_WUTR_WUT                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CALIBR register  ***************/
-#define RTC_CALIBR_DCS                       ((uint32_t)0x00000080)
-#define RTC_CALIBR_DC                        ((uint32_t)0x0000001F)
-
-/********************  Bits definition for RTC_ALRMAR register  ***************/
-#define RTC_ALRMAR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMAR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMAR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMAR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMAR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMAR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMAR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMAR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMAR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMAR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMAR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMAR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMAR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMAR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMAR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMAR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMAR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMAR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMAR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMAR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMAR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMAR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMAR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMAR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMAR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMAR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMAR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMAR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMAR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMAR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMAR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMAR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMAR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMAR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMAR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMAR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMAR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMAR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMAR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMAR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_ALRMBR register  ***************/
-#define RTC_ALRMBR_MSK4                      ((uint32_t)0x80000000)
-#define RTC_ALRMBR_WDSEL                     ((uint32_t)0x40000000)
-#define RTC_ALRMBR_DT                        ((uint32_t)0x30000000)
-#define RTC_ALRMBR_DT_0                      ((uint32_t)0x10000000)
-#define RTC_ALRMBR_DT_1                      ((uint32_t)0x20000000)
-#define RTC_ALRMBR_DU                        ((uint32_t)0x0F000000)
-#define RTC_ALRMBR_DU_0                      ((uint32_t)0x01000000)
-#define RTC_ALRMBR_DU_1                      ((uint32_t)0x02000000)
-#define RTC_ALRMBR_DU_2                      ((uint32_t)0x04000000)
-#define RTC_ALRMBR_DU_3                      ((uint32_t)0x08000000)
-#define RTC_ALRMBR_MSK3                      ((uint32_t)0x00800000)
-#define RTC_ALRMBR_PM                        ((uint32_t)0x00400000)
-#define RTC_ALRMBR_HT                        ((uint32_t)0x00300000)
-#define RTC_ALRMBR_HT_0                      ((uint32_t)0x00100000)
-#define RTC_ALRMBR_HT_1                      ((uint32_t)0x00200000)
-#define RTC_ALRMBR_HU                        ((uint32_t)0x000F0000)
-#define RTC_ALRMBR_HU_0                      ((uint32_t)0x00010000)
-#define RTC_ALRMBR_HU_1                      ((uint32_t)0x00020000)
-#define RTC_ALRMBR_HU_2                      ((uint32_t)0x00040000)
-#define RTC_ALRMBR_HU_3                      ((uint32_t)0x00080000)
-#define RTC_ALRMBR_MSK2                      ((uint32_t)0x00008000)
-#define RTC_ALRMBR_MNT                       ((uint32_t)0x00007000)
-#define RTC_ALRMBR_MNT_0                     ((uint32_t)0x00001000)
-#define RTC_ALRMBR_MNT_1                     ((uint32_t)0x00002000)
-#define RTC_ALRMBR_MNT_2                     ((uint32_t)0x00004000)
-#define RTC_ALRMBR_MNU                       ((uint32_t)0x00000F00)
-#define RTC_ALRMBR_MNU_0                     ((uint32_t)0x00000100)
-#define RTC_ALRMBR_MNU_1                     ((uint32_t)0x00000200)
-#define RTC_ALRMBR_MNU_2                     ((uint32_t)0x00000400)
-#define RTC_ALRMBR_MNU_3                     ((uint32_t)0x00000800)
-#define RTC_ALRMBR_MSK1                      ((uint32_t)0x00000080)
-#define RTC_ALRMBR_ST                        ((uint32_t)0x00000070)
-#define RTC_ALRMBR_ST_0                      ((uint32_t)0x00000010)
-#define RTC_ALRMBR_ST_1                      ((uint32_t)0x00000020)
-#define RTC_ALRMBR_ST_2                      ((uint32_t)0x00000040)
-#define RTC_ALRMBR_SU                        ((uint32_t)0x0000000F)
-#define RTC_ALRMBR_SU_0                      ((uint32_t)0x00000001)
-#define RTC_ALRMBR_SU_1                      ((uint32_t)0x00000002)
-#define RTC_ALRMBR_SU_2                      ((uint32_t)0x00000004)
-#define RTC_ALRMBR_SU_3                      ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_WPR register  ******************/
-#define RTC_WPR_KEY                          ((uint32_t)0x000000FF)
-
-/********************  Bits definition for RTC_SSR register  ******************/
-#define RTC_SSR_SS                           ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_SHIFTR register  ***************/
-#define RTC_SHIFTR_SUBFS                     ((uint32_t)0x00007FFF)
-#define RTC_SHIFTR_ADD1S                     ((uint32_t)0x80000000)
-
-/********************  Bits definition for RTC_TSTR register  *****************/
-#define RTC_TSTR_PM                          ((uint32_t)0x00400000)
-#define RTC_TSTR_HT                          ((uint32_t)0x00300000)
-#define RTC_TSTR_HT_0                        ((uint32_t)0x00100000)
-#define RTC_TSTR_HT_1                        ((uint32_t)0x00200000)
-#define RTC_TSTR_HU                          ((uint32_t)0x000F0000)
-#define RTC_TSTR_HU_0                        ((uint32_t)0x00010000)
-#define RTC_TSTR_HU_1                        ((uint32_t)0x00020000)
-#define RTC_TSTR_HU_2                        ((uint32_t)0x00040000)
-#define RTC_TSTR_HU_3                        ((uint32_t)0x00080000)
-#define RTC_TSTR_MNT                         ((uint32_t)0x00007000)
-#define RTC_TSTR_MNT_0                       ((uint32_t)0x00001000)
-#define RTC_TSTR_MNT_1                       ((uint32_t)0x00002000)
-#define RTC_TSTR_MNT_2                       ((uint32_t)0x00004000)
-#define RTC_TSTR_MNU                         ((uint32_t)0x00000F00)
-#define RTC_TSTR_MNU_0                       ((uint32_t)0x00000100)
-#define RTC_TSTR_MNU_1                       ((uint32_t)0x00000200)
-#define RTC_TSTR_MNU_2                       ((uint32_t)0x00000400)
-#define RTC_TSTR_MNU_3                       ((uint32_t)0x00000800)
-#define RTC_TSTR_ST                          ((uint32_t)0x00000070)
-#define RTC_TSTR_ST_0                        ((uint32_t)0x00000010)
-#define RTC_TSTR_ST_1                        ((uint32_t)0x00000020)
-#define RTC_TSTR_ST_2                        ((uint32_t)0x00000040)
-#define RTC_TSTR_SU                          ((uint32_t)0x0000000F)
-#define RTC_TSTR_SU_0                        ((uint32_t)0x00000001)
-#define RTC_TSTR_SU_1                        ((uint32_t)0x00000002)
-#define RTC_TSTR_SU_2                        ((uint32_t)0x00000004)
-#define RTC_TSTR_SU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSDR register  *****************/
-#define RTC_TSDR_WDU                         ((uint32_t)0x0000E000)
-#define RTC_TSDR_WDU_0                       ((uint32_t)0x00002000)
-#define RTC_TSDR_WDU_1                       ((uint32_t)0x00004000)
-#define RTC_TSDR_WDU_2                       ((uint32_t)0x00008000)
-#define RTC_TSDR_MT                          ((uint32_t)0x00001000)
-#define RTC_TSDR_MU                          ((uint32_t)0x00000F00)
-#define RTC_TSDR_MU_0                        ((uint32_t)0x00000100)
-#define RTC_TSDR_MU_1                        ((uint32_t)0x00000200)
-#define RTC_TSDR_MU_2                        ((uint32_t)0x00000400)
-#define RTC_TSDR_MU_3                        ((uint32_t)0x00000800)
-#define RTC_TSDR_DT                          ((uint32_t)0x00000030)
-#define RTC_TSDR_DT_0                        ((uint32_t)0x00000010)
-#define RTC_TSDR_DT_1                        ((uint32_t)0x00000020)
-#define RTC_TSDR_DU                          ((uint32_t)0x0000000F)
-#define RTC_TSDR_DU_0                        ((uint32_t)0x00000001)
-#define RTC_TSDR_DU_1                        ((uint32_t)0x00000002)
-#define RTC_TSDR_DU_2                        ((uint32_t)0x00000004)
-#define RTC_TSDR_DU_3                        ((uint32_t)0x00000008)
-
-/********************  Bits definition for RTC_TSSSR register  ****************/
-#define RTC_TSSSR_SS                         ((uint32_t)0x0000FFFF)
-
-/********************  Bits definition for RTC_CAL register  *****************/
-#define RTC_CALR_CALP                        ((uint32_t)0x00008000)
-#define RTC_CALR_CALW8                       ((uint32_t)0x00004000)
-#define RTC_CALR_CALW16                      ((uint32_t)0x00002000)
-#define RTC_CALR_CALM                        ((uint32_t)0x000001FF)
-#define RTC_CALR_CALM_0                      ((uint32_t)0x00000001)
-#define RTC_CALR_CALM_1                      ((uint32_t)0x00000002)
-#define RTC_CALR_CALM_2                      ((uint32_t)0x00000004)
-#define RTC_CALR_CALM_3                      ((uint32_t)0x00000008)
-#define RTC_CALR_CALM_4                      ((uint32_t)0x00000010)
-#define RTC_CALR_CALM_5                      ((uint32_t)0x00000020)
-#define RTC_CALR_CALM_6                      ((uint32_t)0x00000040)
-#define RTC_CALR_CALM_7                      ((uint32_t)0x00000080)
-#define RTC_CALR_CALM_8                      ((uint32_t)0x00000100)
-
-/********************  Bits definition for RTC_TAFCR register  ****************/
-#define RTC_TAFCR_ALARMOUTTYPE               ((uint32_t)0x00040000)
-#define RTC_TAFCR_TAMPPUDIS                  ((uint32_t)0x00008000)
-#define RTC_TAFCR_TAMPPRCH                   ((uint32_t)0x00006000)
-#define RTC_TAFCR_TAMPPRCH_0                 ((uint32_t)0x00002000)
-#define RTC_TAFCR_TAMPPRCH_1                 ((uint32_t)0x00004000)
-#define RTC_TAFCR_TAMPFLT                    ((uint32_t)0x00001800)
-#define RTC_TAFCR_TAMPFLT_0                  ((uint32_t)0x00000800)
-#define RTC_TAFCR_TAMPFLT_1                  ((uint32_t)0x00001000)
-#define RTC_TAFCR_TAMPFREQ                   ((uint32_t)0x00000700)
-#define RTC_TAFCR_TAMPFREQ_0                 ((uint32_t)0x00000100)
-#define RTC_TAFCR_TAMPFREQ_1                 ((uint32_t)0x00000200)
-#define RTC_TAFCR_TAMPFREQ_2                 ((uint32_t)0x00000400)
-#define RTC_TAFCR_TAMPTS                     ((uint32_t)0x00000080)
-#define RTC_TAFCR_TAMP3TRG                   ((uint32_t)0x00000040)
-#define RTC_TAFCR_TAMP3E                     ((uint32_t)0x00000020)
-#define RTC_TAFCR_TAMP2TRG                   ((uint32_t)0x00000010)
-#define RTC_TAFCR_TAMP2E                     ((uint32_t)0x00000008)
-#define RTC_TAFCR_TAMPIE                     ((uint32_t)0x00000004)
-#define RTC_TAFCR_TAMP1TRG                   ((uint32_t)0x00000002)
-#define RTC_TAFCR_TAMP1E                     ((uint32_t)0x00000001)
-
-/********************  Bits definition for RTC_ALRMASSR register  *************/
-#define RTC_ALRMASSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMASSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMASSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMASSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMASSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMASSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_ALRMBSSR register  *************/
-#define RTC_ALRMBSSR_MASKSS                  ((uint32_t)0x0F000000)
-#define RTC_ALRMBSSR_MASKSS_0                ((uint32_t)0x01000000)
-#define RTC_ALRMBSSR_MASKSS_1                ((uint32_t)0x02000000)
-#define RTC_ALRMBSSR_MASKSS_2                ((uint32_t)0x04000000)
-#define RTC_ALRMBSSR_MASKSS_3                ((uint32_t)0x08000000)
-#define RTC_ALRMBSSR_SS                      ((uint32_t)0x00007FFF)
-
-/********************  Bits definition for RTC_BKP0R register  ****************/
-#define RTC_BKP0R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP1R register  ****************/
-#define RTC_BKP1R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP2R register  ****************/
-#define RTC_BKP2R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP3R register  ****************/
-#define RTC_BKP3R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP4R register  ****************/
-#define RTC_BKP4R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP5R register  ****************/
-#define RTC_BKP5R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP6R register  ****************/
-#define RTC_BKP6R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP7R register  ****************/
-#define RTC_BKP7R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP8R register  ****************/
-#define RTC_BKP8R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP9R register  ****************/
-#define RTC_BKP9R                            ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP10R register  ***************/
-#define RTC_BKP10R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP11R register  ***************/
-#define RTC_BKP11R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP12R register  ***************/
-#define RTC_BKP12R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP13R register  ***************/
-#define RTC_BKP13R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP14R register  ***************/
-#define RTC_BKP14R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP15R register  ***************/
-#define RTC_BKP15R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP16R register  ***************/
-#define RTC_BKP16R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP17R register  ***************/
-#define RTC_BKP17R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP18R register  ***************/
-#define RTC_BKP18R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP19R register  ***************/
-#define RTC_BKP19R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP20R register  ***************/
-#define RTC_BKP20R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP21R register  ***************/
-#define RTC_BKP21R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP22R register  ***************/
-#define RTC_BKP22R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP23R register  ***************/
-#define RTC_BKP23R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP24R register  ***************/
-#define RTC_BKP24R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP25R register  ***************/
-#define RTC_BKP25R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP26R register  ***************/
-#define RTC_BKP26R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP27R register  ***************/
-#define RTC_BKP27R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP28R register  ***************/
-#define RTC_BKP28R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP29R register  ***************/
-#define RTC_BKP29R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP30R register  ***************/
-#define RTC_BKP30R                           ((uint32_t)0xFFFFFFFF)
-
-/********************  Bits definition for RTC_BKP31R register  ***************/
-#define RTC_BKP31R                           ((uint32_t)0xFFFFFFFF)
-
-/******************** Number of backup registers ******************************/
-#define RTC_BKP_NUMBER 32
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Serial Peripheral Interface (SPI)                      */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for SPI_CR1 register  ********************/
-#define  SPI_CR1_CPHA                        ((uint32_t)0x00000001)            /*!< Clock Phase */
-#define  SPI_CR1_CPOL                        ((uint32_t)0x00000002)            /*!< Clock Polarity */
-#define  SPI_CR1_MSTR                        ((uint32_t)0x00000004)            /*!< Master Selection */
-
-#define  SPI_CR1_BR                          ((uint32_t)0x00000038)            /*!< BR[2:0] bits (Baud Rate Control) */
-#define  SPI_CR1_BR_0                        ((uint32_t)0x00000008)            /*!< Bit 0 */
-#define  SPI_CR1_BR_1                        ((uint32_t)0x00000010)            /*!< Bit 1 */
-#define  SPI_CR1_BR_2                        ((uint32_t)0x00000020)            /*!< Bit 2 */
-
-#define  SPI_CR1_SPE                         ((uint32_t)0x00000040)            /*!< SPI Enable */
-#define  SPI_CR1_LSBFIRST                    ((uint32_t)0x00000080)            /*!< Frame Format */
-#define  SPI_CR1_SSI                         ((uint32_t)0x00000100)            /*!< Internal slave select */
-#define  SPI_CR1_SSM                         ((uint32_t)0x00000200)            /*!< Software slave management */
-#define  SPI_CR1_RXONLY                      ((uint32_t)0x00000400)            /*!< Receive only */
-#define  SPI_CR1_DFF                         ((uint32_t)0x00000800)            /*!< Data Frame Format */
-#define  SPI_CR1_CRCNEXT                     ((uint32_t)0x00001000)            /*!< Transmit CRC next */
-#define  SPI_CR1_CRCEN                       ((uint32_t)0x00002000)            /*!< Hardware CRC calculation enable */
-#define  SPI_CR1_BIDIOE                      ((uint32_t)0x00004000)            /*!< Output enable in bidirectional mode */
-#define  SPI_CR1_BIDIMODE                    ((uint32_t)0x00008000)            /*!< Bidirectional data mode enable */
-
-/*******************  Bit definition for SPI_CR2 register  ********************/
-#define  SPI_CR2_RXDMAEN                     ((uint32_t)0x00000001)               /*!< Rx Buffer DMA Enable */
-#define  SPI_CR2_TXDMAEN                     ((uint32_t)0x00000002)               /*!< Tx Buffer DMA Enable */
-#define  SPI_CR2_SSOE                        ((uint32_t)0x00000004)               /*!< SS Output Enable */
-#define  SPI_CR2_FRF                         ((uint32_t)0x00000010)               /*!< Frame format */
-#define  SPI_CR2_ERRIE                       ((uint32_t)0x00000020)               /*!< Error Interrupt Enable */
-#define  SPI_CR2_RXNEIE                      ((uint32_t)0x00000040)               /*!< RX buffer Not Empty Interrupt Enable */
-#define  SPI_CR2_TXEIE                       ((uint32_t)0x00000080)               /*!< Tx buffer Empty Interrupt Enable */
-
-/********************  Bit definition for SPI_SR register  ********************/
-#define  SPI_SR_RXNE                         ((uint32_t)0x00000001)               /*!< Receive buffer Not Empty */
-#define  SPI_SR_TXE                          ((uint32_t)0x00000002)               /*!< Transmit buffer Empty */
-#define  SPI_SR_CHSIDE                       ((uint32_t)0x00000004)               /*!< Channel side */
-#define  SPI_SR_UDR                          ((uint32_t)0x00000008)               /*!< Underrun flag */
-#define  SPI_SR_CRCERR                       ((uint32_t)0x00000010)               /*!< CRC Error flag */
-#define  SPI_SR_MODF                         ((uint32_t)0x00000020)               /*!< Mode fault */
-#define  SPI_SR_OVR                          ((uint32_t)0x00000040)               /*!< Overrun flag */
-#define  SPI_SR_BSY                          ((uint32_t)0x00000080)               /*!< Busy flag */
-#define  SPI_SR_FRE                          ((uint32_t)0x00000100)               /*!<Frame format error flag  */
-
-/********************  Bit definition for SPI_DR register  ********************/
-#define  SPI_DR_DR                           ((uint32_t)0x0000FFFF)            /*!< Data Register */
-
-/*******************  Bit definition for SPI_CRCPR register  ******************/
-#define  SPI_CRCPR_CRCPOLY                   ((uint32_t)0x0000FFFF)            /*!< CRC polynomial register */
-
-/******************  Bit definition for SPI_RXCRCR register  ******************/
-#define  SPI_RXCRCR_RXCRC                    ((uint32_t)0x0000FFFF)            /*!< Rx CRC Register */
-
-/******************  Bit definition for SPI_TXCRCR register  ******************/
-#define  SPI_TXCRCR_TXCRC                    ((uint32_t)0x0000FFFF)            /*!< Tx CRC Register */
-
-/******************  Bit definition for SPI_I2SCFGR register  *****************/
-#define  SPI_I2SCFGR_CHLEN                   ((uint32_t)0x00000001)            /*!<Channel length (number of bits per audio channel) */
-
-#define  SPI_I2SCFGR_DATLEN                  ((uint32_t)0x00000006)            /*!<DATLEN[1:0] bits (Data length to be transferred) */
-#define  SPI_I2SCFGR_DATLEN_0                ((uint32_t)0x00000002)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_DATLEN_1                ((uint32_t)0x00000004)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_CKPOL                   ((uint32_t)0x00000008)            /*!<steady state clock polarity */
-
-#define  SPI_I2SCFGR_I2SSTD                  ((uint32_t)0x00000030)            /*!<I2SSTD[1:0] bits (I2S standard selection) */
-#define  SPI_I2SCFGR_I2SSTD_0                ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SSTD_1                ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_PCMSYNC                 ((uint32_t)0x00000080)            /*!<PCM frame synchronization */
-
-#define  SPI_I2SCFGR_I2SCFG                  ((uint32_t)0x00000300)            /*!<I2SCFG[1:0] bits (I2S configuration mode) */
-#define  SPI_I2SCFGR_I2SCFG_0                ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  SPI_I2SCFGR_I2SCFG_1                ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  SPI_I2SCFGR_I2SE                    ((uint32_t)0x00000400)            /*!<I2S Enable */
-#define  SPI_I2SCFGR_I2SMOD                  ((uint32_t)0x00000800)            /*!<I2S mode selection */
-
-/******************  Bit definition for SPI_I2SPR register  *******************/
-#define  SPI_I2SPR_I2SDIV                    ((uint32_t)0x000000FF)            /*!<I2S Linear prescaler */
-#define  SPI_I2SPR_ODD                       ((uint32_t)0x00000100)            /*!<Odd factor for the prescaler */
-#define  SPI_I2SPR_MCKOE                     ((uint32_t)0x00000200)            /*!<Master Clock Output Enable */
-
-/******************************************************************************/
-/*                                                                            */
-/*                       System Configuration (SYSCFG)                        */
-/*                                                                            */
-/******************************************************************************/
-/*****************  Bit definition for SYSCFG_MEMRMP register  ****************/
-#define SYSCFG_MEMRMP_MEM_MODE          ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
-#define SYSCFG_MEMRMP_MEM_MODE_0        ((uint32_t)0x00000001) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_MEM_MODE_1        ((uint32_t)0x00000002) /*!< Bit 1 */
-#define SYSCFG_MEMRMP_BOOT_MODE         ((uint32_t)0x00000300) /*!< Boot mode Config */
-#define SYSCFG_MEMRMP_BOOT_MODE_0       ((uint32_t)0x00000100) /*!< Bit 0 */
-#define SYSCFG_MEMRMP_BOOT_MODE_1       ((uint32_t)0x00000200) /*!< Bit 1 */
-
-/*****************  Bit definition for SYSCFG_PMC register  *******************/
-#define SYSCFG_PMC_USB_PU               ((uint32_t)0x00000001) /*!< SYSCFG PMC */
-
-/*****************  Bit definition for SYSCFG_EXTICR1 register  ***************/
-#define SYSCFG_EXTICR1_EXTI0            ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
-#define SYSCFG_EXTICR1_EXTI1            ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
-#define SYSCFG_EXTICR1_EXTI2            ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
-#define SYSCFG_EXTICR1_EXTI3            ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
-
-/** 
-  * @brief  EXTI0 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI0_PA         ((uint32_t)0x00000000) /*!< PA[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PB         ((uint32_t)0x00000001) /*!< PB[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PC         ((uint32_t)0x00000002) /*!< PC[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PD         ((uint32_t)0x00000003) /*!< PD[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PE         ((uint32_t)0x00000004) /*!< PE[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PH         ((uint32_t)0x00000005) /*!< PH[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PF         ((uint32_t)0x00000006) /*!< PF[0] pin */
-#define SYSCFG_EXTICR1_EXTI0_PG         ((uint32_t)0x00000007) /*!< PG[0] pin */
-
-/** 
-  * @brief  EXTI1 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI1_PA         ((uint32_t)0x00000000) /*!< PA[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PB         ((uint32_t)0x00000010) /*!< PB[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PC         ((uint32_t)0x00000020) /*!< PC[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PD         ((uint32_t)0x00000030) /*!< PD[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PE         ((uint32_t)0x00000040) /*!< PE[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PH         ((uint32_t)0x00000050) /*!< PH[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PF         ((uint32_t)0x00000060) /*!< PF[1] pin */
-#define SYSCFG_EXTICR1_EXTI1_PG         ((uint32_t)0x00000070) /*!< PG[1] pin */
-
-/** 
-  * @brief  EXTI2 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI2_PA         ((uint32_t)0x00000000) /*!< PA[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PB         ((uint32_t)0x00000100) /*!< PB[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PC         ((uint32_t)0x00000200) /*!< PC[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PD         ((uint32_t)0x00000300) /*!< PD[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PE         ((uint32_t)0x00000400) /*!< PE[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PH         ((uint32_t)0x00000500) /*!< PH[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PF         ((uint32_t)0x00000600) /*!< PF[2] pin */
-#define SYSCFG_EXTICR1_EXTI2_PG         ((uint32_t)0x00000700) /*!< PG[2] pin */
-
-/** 
-  * @brief  EXTI3 configuration  
-  */ 
-#define SYSCFG_EXTICR1_EXTI3_PA         ((uint32_t)0x00000000) /*!< PA[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PB         ((uint32_t)0x00001000) /*!< PB[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PC         ((uint32_t)0x00002000) /*!< PC[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PD         ((uint32_t)0x00003000) /*!< PD[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PE         ((uint32_t)0x00004000) /*!< PE[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PF         ((uint32_t)0x00003000) /*!< PF[3] pin */
-#define SYSCFG_EXTICR1_EXTI3_PG         ((uint32_t)0x00004000) /*!< PG[3] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR2 register  *****************/
-#define SYSCFG_EXTICR2_EXTI4            ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
-#define SYSCFG_EXTICR2_EXTI5            ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
-#define SYSCFG_EXTICR2_EXTI6            ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
-#define SYSCFG_EXTICR2_EXTI7            ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
-
-/** 
-  * @brief  EXTI4 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI4_PA         ((uint32_t)0x00000000) /*!< PA[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PB         ((uint32_t)0x00000001) /*!< PB[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PC         ((uint32_t)0x00000002) /*!< PC[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PD         ((uint32_t)0x00000003) /*!< PD[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PE         ((uint32_t)0x00000004) /*!< PE[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PF         ((uint32_t)0x00000006) /*!< PF[4] pin */
-#define SYSCFG_EXTICR2_EXTI4_PG         ((uint32_t)0x00000007) /*!< PG[4] pin */
-
-/** 
-  * @brief  EXTI5 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI5_PA         ((uint32_t)0x00000000) /*!< PA[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PB         ((uint32_t)0x00000010) /*!< PB[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PC         ((uint32_t)0x00000020) /*!< PC[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PD         ((uint32_t)0x00000030) /*!< PD[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PE         ((uint32_t)0x00000040) /*!< PE[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PF         ((uint32_t)0x00000060) /*!< PF[5] pin */
-#define SYSCFG_EXTICR2_EXTI5_PG         ((uint32_t)0x00000070) /*!< PG[5] pin */
-
-/** 
-  * @brief  EXTI6 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI6_PA         ((uint32_t)0x00000000) /*!< PA[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PB         ((uint32_t)0x00000100) /*!< PB[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PC         ((uint32_t)0x00000200) /*!< PC[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PD         ((uint32_t)0x00000300) /*!< PD[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PE         ((uint32_t)0x00000400) /*!< PE[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PF         ((uint32_t)0x00000600) /*!< PF[6] pin */
-#define SYSCFG_EXTICR2_EXTI6_PG         ((uint32_t)0x00000700) /*!< PG[6] pin */
-
-/** 
-  * @brief  EXTI7 configuration  
-  */ 
-#define SYSCFG_EXTICR2_EXTI7_PA         ((uint32_t)0x00000000) /*!< PA[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PB         ((uint32_t)0x00001000) /*!< PB[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PC         ((uint32_t)0x00002000) /*!< PC[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PD         ((uint32_t)0x00003000) /*!< PD[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PE         ((uint32_t)0x00004000) /*!< PE[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PF         ((uint32_t)0x00006000) /*!< PF[7] pin */
-#define SYSCFG_EXTICR2_EXTI7_PG         ((uint32_t)0x00007000) /*!< PG[7] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR3 register  *****************/
-#define SYSCFG_EXTICR3_EXTI8            ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
-#define SYSCFG_EXTICR3_EXTI9            ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
-#define SYSCFG_EXTICR3_EXTI10           ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
-#define SYSCFG_EXTICR3_EXTI11           ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
-
-/** 
-  * @brief  EXTI8 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI8_PA         ((uint32_t)0x00000000) /*!< PA[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PB         ((uint32_t)0x00000001) /*!< PB[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PC         ((uint32_t)0x00000002) /*!< PC[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PD         ((uint32_t)0x00000003) /*!< PD[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PE         ((uint32_t)0x00000004) /*!< PE[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PF         ((uint32_t)0x00000006) /*!< PF[8] pin */
-#define SYSCFG_EXTICR3_EXTI8_PG         ((uint32_t)0x00000007) /*!< PG[8] pin */
-
-/** 
-  * @brief  EXTI9 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI9_PA         ((uint32_t)0x00000000) /*!< PA[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PB         ((uint32_t)0x00000010) /*!< PB[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PC         ((uint32_t)0x00000020) /*!< PC[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PD         ((uint32_t)0x00000030) /*!< PD[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PE         ((uint32_t)0x00000040) /*!< PE[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PF         ((uint32_t)0x00000060) /*!< PF[9] pin */
-#define SYSCFG_EXTICR3_EXTI9_PG         ((uint32_t)0x00000070) /*!< PG[9] pin */
-
-/** 
-  * @brief  EXTI10 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI10_PA        ((uint32_t)0x00000000) /*!< PA[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PB        ((uint32_t)0x00000100) /*!< PB[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PC        ((uint32_t)0x00000200) /*!< PC[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PD        ((uint32_t)0x00000300) /*!< PD[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PE        ((uint32_t)0x00000400) /*!< PE[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PF        ((uint32_t)0x00000600) /*!< PF[10] pin */
-#define SYSCFG_EXTICR3_EXTI10_PG        ((uint32_t)0x00000700) /*!< PG[10] pin */
-
-/** 
-  * @brief  EXTI11 configuration  
-  */ 
-#define SYSCFG_EXTICR3_EXTI11_PA        ((uint32_t)0x00000000) /*!< PA[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PB        ((uint32_t)0x00001000) /*!< PB[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PC        ((uint32_t)0x00002000) /*!< PC[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PD        ((uint32_t)0x00003000) /*!< PD[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PE        ((uint32_t)0x00004000) /*!< PE[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PF        ((uint32_t)0x00006000) /*!< PF[11] pin */
-#define SYSCFG_EXTICR3_EXTI11_PG        ((uint32_t)0x00007000) /*!< PG[11] pin */
-
-/*****************  Bit definition for SYSCFG_EXTICR4 register  *****************/
-#define SYSCFG_EXTICR4_EXTI12           ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
-#define SYSCFG_EXTICR4_EXTI13           ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
-#define SYSCFG_EXTICR4_EXTI14           ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
-#define SYSCFG_EXTICR4_EXTI15           ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
-
-/** 
-  * @brief  EXTI12 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI12_PA        ((uint32_t)0x00000000) /*!< PA[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PB        ((uint32_t)0x00000001) /*!< PB[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PC        ((uint32_t)0x00000002) /*!< PC[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PD        ((uint32_t)0x00000003) /*!< PD[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PE        ((uint32_t)0x00000004) /*!< PE[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PF        ((uint32_t)0x00000006) /*!< PF[12] pin */
-#define SYSCFG_EXTICR4_EXTI12_PG        ((uint32_t)0x00000007) /*!< PG[12] pin */
-
-/** 
-  * @brief  EXTI13 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI13_PA        ((uint32_t)0x00000000) /*!< PA[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PB        ((uint32_t)0x00000010) /*!< PB[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PC        ((uint32_t)0x00000020) /*!< PC[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PD        ((uint32_t)0x00000030) /*!< PD[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PE        ((uint32_t)0x00000040) /*!< PE[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PF        ((uint32_t)0x00000060) /*!< PF[13] pin */
-#define SYSCFG_EXTICR4_EXTI13_PG        ((uint32_t)0x00000070) /*!< PG[13] pin */
-
-/** 
-  * @brief  EXTI14 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI14_PA        ((uint32_t)0x00000000) /*!< PA[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PB        ((uint32_t)0x00000100) /*!< PB[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PC        ((uint32_t)0x00000200) /*!< PC[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PD        ((uint32_t)0x00000300) /*!< PD[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PE        ((uint32_t)0x00000400) /*!< PE[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PF        ((uint32_t)0x00000600) /*!< PF[14] pin */
-#define SYSCFG_EXTICR4_EXTI14_PG        ((uint32_t)0x00000700) /*!< PG[14] pin */
-
-/** 
-  * @brief  EXTI15 configuration  
-  */ 
-#define SYSCFG_EXTICR4_EXTI15_PA        ((uint32_t)0x00000000) /*!< PA[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PB        ((uint32_t)0x00001000) /*!< PB[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PC        ((uint32_t)0x00002000) /*!< PC[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PD        ((uint32_t)0x00003000) /*!< PD[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PE        ((uint32_t)0x00004000) /*!< PE[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PF        ((uint32_t)0x00006000) /*!< PF[15] pin */
-#define SYSCFG_EXTICR4_EXTI15_PG        ((uint32_t)0x00007000) /*!< PG[15] pin */
- 
-/******************************************************************************/
-/*                                                                            */
-/*                       Routing Interface (RI)                               */
-/*                                                                            */
-/******************************************************************************/
-
-/********************  Bit definition for RI_ICR register  ********************/
-#define  RI_ICR_IC1OS                    ((uint32_t)0x0000000F) /*!< IC1OS[3:0] bits (Input Capture 1 select bits) */
-#define  RI_ICR_IC1OS_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ICR_IC1OS_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ICR_IC1OS_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ICR_IC1OS_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-
-#define  RI_ICR_IC2OS                    ((uint32_t)0x000000F0) /*!< IC2OS[3:0] bits (Input Capture 2 select bits) */
-#define  RI_ICR_IC2OS_0                  ((uint32_t)0x00000010) /*!< Bit 0 */
-#define  RI_ICR_IC2OS_1                  ((uint32_t)0x00000020) /*!< Bit 1 */
-#define  RI_ICR_IC2OS_2                  ((uint32_t)0x00000040) /*!< Bit 2 */
-#define  RI_ICR_IC2OS_3                  ((uint32_t)0x00000080) /*!< Bit 3 */
-
-#define  RI_ICR_IC3OS                    ((uint32_t)0x00000F00) /*!< IC3OS[3:0] bits (Input Capture 3 select bits) */
-#define  RI_ICR_IC3OS_0                  ((uint32_t)0x00000100) /*!< Bit 0 */
-#define  RI_ICR_IC3OS_1                  ((uint32_t)0x00000200) /*!< Bit 1 */
-#define  RI_ICR_IC3OS_2                  ((uint32_t)0x00000400) /*!< Bit 2 */
-#define  RI_ICR_IC3OS_3                  ((uint32_t)0x00000800) /*!< Bit 3 */
-
-#define  RI_ICR_IC4OS                    ((uint32_t)0x0000F000) /*!< IC4OS[3:0] bits (Input Capture 4 select bits) */
-#define  RI_ICR_IC4OS_0                  ((uint32_t)0x00001000) /*!< Bit 0 */
-#define  RI_ICR_IC4OS_1                  ((uint32_t)0x00002000) /*!< Bit 1 */
-#define  RI_ICR_IC4OS_2                  ((uint32_t)0x00004000) /*!< Bit 2 */
-#define  RI_ICR_IC4OS_3                  ((uint32_t)0x00008000) /*!< Bit 3 */
-
-#define  RI_ICR_TIM                     ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
-#define  RI_ICR_TIM_0                   ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_ICR_TIM_1                   ((uint32_t)0x00020000) /*!< Bit 1 */
-
-#define  RI_ICR_IC1                     ((uint32_t)0x00040000) /*!< Input capture 1 */
-#define  RI_ICR_IC2                     ((uint32_t)0x00080000) /*!< Input capture 2 */
-#define  RI_ICR_IC3                     ((uint32_t)0x00100000) /*!< Input capture 3 */
-#define  RI_ICR_IC4                     ((uint32_t)0x00200000) /*!< Input capture 4 */
-
-/********************  Bit definition for RI_ASCR1 register  ********************/
-#define  RI_ASCR1_CH                    ((uint32_t)0x7BFDFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
-#define  RI_ASCR1_CH_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASCR1_CH_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASCR1_CH_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASCR1_CH_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASCR1_CH_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASCR1_CH_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASCR1_CH_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASCR1_CH_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASCR1_CH_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASCR1_CH_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASCR1_CH_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASCR1_CH_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASCR1_CH_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASCR1_CH_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASCR1_CH_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASCR1_CH_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-#define  RI_ASCR1_CH_31                 ((uint32_t)0x00010000) /*!< Bit 16 */
-#define  RI_ASCR1_CH_18                 ((uint32_t)0x00040000) /*!< Bit 18 */
-#define  RI_ASCR1_CH_19                 ((uint32_t)0x00080000) /*!< Bit 19 */
-#define  RI_ASCR1_CH_20                 ((uint32_t)0x00100000) /*!< Bit 20 */
-#define  RI_ASCR1_CH_21                 ((uint32_t)0x00200000) /*!< Bit 21 */
-#define  RI_ASCR1_CH_22                 ((uint32_t)0x00400000) /*!< Bit 22 */
-#define  RI_ASCR1_CH_23                 ((uint32_t)0x00800000) /*!< Bit 23 */
-#define  RI_ASCR1_CH_24                 ((uint32_t)0x01000000) /*!< Bit 24 */
-#define  RI_ASCR1_CH_25                 ((uint32_t)0x02000000) /*!< Bit 25 */
-#define  RI_ASCR1_VCOMP                 ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
-#define  RI_ASCR1_CH_27                 ((uint32_t)0x00400000) /*!< Bit 27 */
-#define  RI_ASCR1_CH_28                 ((uint32_t)0x00800000) /*!< Bit 28 */
-#define  RI_ASCR1_CH_29                 ((uint32_t)0x01000000) /*!< Bit 29 */
-#define  RI_ASCR1_CH_30                 ((uint32_t)0x02000000) /*!< Bit 30 */
-#define  RI_ASCR1_SCM                   ((uint32_t)0x80000000) /*!< I/O Switch control mode */
-
-/********************  Bit definition for RI_ASCR2 register  ********************/
-#define  RI_ASCR2_GR10_1                ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
-#define  RI_ASCR2_GR10_2                ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
-#define  RI_ASCR2_GR10_3                ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
-#define  RI_ASCR2_GR10_4                ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
-#define  RI_ASCR2_GR6_1                 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
-#define  RI_ASCR2_GR6_2                 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
-#define  RI_ASCR2_GR5_1                 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
-#define  RI_ASCR2_GR5_2                 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
-#define  RI_ASCR2_GR5_3                 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
-#define  RI_ASCR2_GR4_1                 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
-#define  RI_ASCR2_GR4_2                 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
-#define  RI_ASCR2_GR4_3                 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
-#define  RI_ASCR2_GR4_4                 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
-#define  RI_ASCR2_CH0b                  ((uint32_t)0x00010000) /*!< CH0b selection bit */
-#define  RI_ASCR2_GR6_3                 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
-#define  RI_ASCR2_GR6_4                 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
-
-/********************  Bit definition for RI_HYSCR1 register  ********************/
-#define  RI_HYSCR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
-#define  RI_HYSCR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR1_PB                   ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
-#define  RI_HYSCR1_PB_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR1_PB_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR1_PB_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR1_PB_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR1_PB_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR1_PB_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR1_PB_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR1_PB_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR1_PB_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR1_PB_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR1_PB_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR1_PB_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR1_PB_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR1_PB_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR1_PB_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR1_PB_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR2 register  ********************/
-#define  RI_HYSCR2_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
-#define  RI_HYSCR2_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR2_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR2_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR2_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR2_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR2_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR2_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR2_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR2_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR2_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR2_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR2_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR2_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR2_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR2_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR2_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-#define  RI_HYSCR2_PD                   ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
-#define  RI_HYSCR2_PD_0                 ((uint32_t)0x00010000) /*!< Bit 0 */
-#define  RI_HYSCR2_PD_1                 ((uint32_t)0x00020000) /*!< Bit 1 */
-#define  RI_HYSCR2_PD_2                 ((uint32_t)0x00040000) /*!< Bit 2 */
-#define  RI_HYSCR2_PD_3                 ((uint32_t)0x00080000) /*!< Bit 3 */
-#define  RI_HYSCR2_PD_4                 ((uint32_t)0x00100000) /*!< Bit 4 */
-#define  RI_HYSCR2_PD_5                 ((uint32_t)0x00200000) /*!< Bit 5 */
-#define  RI_HYSCR2_PD_6                 ((uint32_t)0x00400000) /*!< Bit 6 */
-#define  RI_HYSCR2_PD_7                 ((uint32_t)0x00800000) /*!< Bit 7 */
-#define  RI_HYSCR2_PD_8                 ((uint32_t)0x01000000) /*!< Bit 8 */
-#define  RI_HYSCR2_PD_9                 ((uint32_t)0x02000000) /*!< Bit 9 */
-#define  RI_HYSCR2_PD_10                ((uint32_t)0x04000000) /*!< Bit 10 */
-#define  RI_HYSCR2_PD_11                ((uint32_t)0x08000000) /*!< Bit 11 */
-#define  RI_HYSCR2_PD_12                ((uint32_t)0x10000000) /*!< Bit 12 */
-#define  RI_HYSCR2_PD_13                ((uint32_t)0x20000000) /*!< Bit 13 */
-#define  RI_HYSCR2_PD_14                ((uint32_t)0x40000000) /*!< Bit 14 */
-#define  RI_HYSCR2_PD_15                ((uint32_t)0x80000000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_HYSCR3 register  ********************/
-#define  RI_HYSCR3_PE                   ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
-#define  RI_HYSCR3_PE_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_HYSCR3_PE_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_HYSCR3_PE_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_HYSCR3_PE_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_HYSCR3_PE_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_HYSCR3_PE_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_HYSCR3_PE_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_HYSCR3_PE_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_HYSCR3_PE_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_HYSCR3_PE_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_HYSCR3_PE_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_HYSCR3_PE_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_HYSCR3_PE_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_HYSCR3_PE_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_HYSCR3_PE_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_HYSCR3_PE_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR1 register  ********************/
-#define  RI_ASMR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_ASMR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR1 register  ********************/
-#define  RI_CMR1_PA                    ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_CMR1_PA_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR1_PA_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR1_PA_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR1_PA_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR1_PA_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR1_PA_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR1_PA_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR1_PA_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR1_PA_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR1_PA_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR1_PA_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR1_PA_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR1_PA_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR1_PA_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR1_PA_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR1_PA_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR1 register  ********************/
-#define  RI_CICR1_PA                   ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A selection*/
-#define  RI_CICR1_PA_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR1_PA_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR1_PA_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR1_PA_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR1_PA_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR1_PA_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR1_PA_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR1_PA_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR1_PA_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR1_PA_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR1_PA_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR1_PA_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR1_PA_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR1_PA_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR1_PA_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR1_PA_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR2 register  ********************/
-#define  RI_ASMR2_PB                   ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_ASMR2_PB_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR2_PB_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR2_PB_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR2_PB_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR2_PB_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR2_PB_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR2_PB_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR2_PB_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR2_PB_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR2_PB_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR2_PB_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR2_PB_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR2_PB_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR2_PB_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR2_PB_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR2_PB_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR2 register  ********************/
-#define  RI_CMR2_PB                    ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_CMR2_PB_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR2_PB_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR2_PB_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR2_PB_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR2_PB_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR2_PB_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR2_PB_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR2_PB_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR2_PB_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR2_PB_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR2_PB_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR2_PB_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR2_PB_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR2_PB_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR2_PB_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR2_PB_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR2 register  ********************/
-#define  RI_CICR2_PB                   ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B selection */
-#define  RI_CICR2_PB_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR2_PB_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR2_PB_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR2_PB_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR2_PB_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR2_PB_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR2_PB_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR2_PB_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR2_PB_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR2_PB_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR2_PB_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR2_PB_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR2_PB_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR2_PB_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR2_PB_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR2_PB_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_ASMR3 register  ********************/
-#define  RI_ASMR3_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_ASMR3_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_ASMR3_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_ASMR3_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_ASMR3_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_ASMR3_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_ASMR3_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_ASMR3_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_ASMR3_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_ASMR3_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_ASMR3_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_ASMR3_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_ASMR3_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_ASMR3_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_ASMR3_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_ASMR3_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_ASMR3_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CMR3 register  ********************/
-#define  RI_CMR3_PC                    ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_CMR3_PC_0                  ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CMR3_PC_1                  ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CMR3_PC_2                  ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CMR3_PC_3                  ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CMR3_PC_4                  ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CMR3_PC_5                  ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CMR3_PC_6                  ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CMR3_PC_7                  ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CMR3_PC_8                  ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CMR3_PC_9                  ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CMR3_PC_10                 ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CMR3_PC_11                 ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CMR3_PC_12                 ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CMR3_PC_13                 ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CMR3_PC_14                 ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CMR3_PC_15                 ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/********************  Bit definition for RI_CICR3 register  ********************/
-#define  RI_CICR3_PC                   ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C selection */
-#define  RI_CICR3_PC_0                 ((uint32_t)0x00000001) /*!< Bit 0 */
-#define  RI_CICR3_PC_1                 ((uint32_t)0x00000002) /*!< Bit 1 */
-#define  RI_CICR3_PC_2                 ((uint32_t)0x00000004) /*!< Bit 2 */
-#define  RI_CICR3_PC_3                 ((uint32_t)0x00000008) /*!< Bit 3 */
-#define  RI_CICR3_PC_4                 ((uint32_t)0x00000010) /*!< Bit 4 */
-#define  RI_CICR3_PC_5                 ((uint32_t)0x00000020) /*!< Bit 5 */
-#define  RI_CICR3_PC_6                 ((uint32_t)0x00000040) /*!< Bit 6 */
-#define  RI_CICR3_PC_7                 ((uint32_t)0x00000080) /*!< Bit 7 */
-#define  RI_CICR3_PC_8                 ((uint32_t)0x00000100) /*!< Bit 8 */
-#define  RI_CICR3_PC_9                 ((uint32_t)0x00000200) /*!< Bit 9 */
-#define  RI_CICR3_PC_10                ((uint32_t)0x00000400) /*!< Bit 10 */
-#define  RI_CICR3_PC_11                ((uint32_t)0x00000800) /*!< Bit 11 */
-#define  RI_CICR3_PC_12                ((uint32_t)0x00001000) /*!< Bit 12 */
-#define  RI_CICR3_PC_13                ((uint32_t)0x00002000) /*!< Bit 13 */
-#define  RI_CICR3_PC_14                ((uint32_t)0x00004000) /*!< Bit 14 */
-#define  RI_CICR3_PC_15                ((uint32_t)0x00008000) /*!< Bit 15 */
-
-/******************************************************************************/
-/*                                                                            */
-/*                               Timers (TIM)                                 */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for TIM_CR1 register  ********************/
-#define  TIM_CR1_CEN                         ((uint32_t)0x00000001)            /*!<Counter enable */
-#define  TIM_CR1_UDIS                        ((uint32_t)0x00000002)            /*!<Update disable */
-#define  TIM_CR1_URS                         ((uint32_t)0x00000004)            /*!<Update request source */
-#define  TIM_CR1_OPM                         ((uint32_t)0x00000008)            /*!<One pulse mode */
-#define  TIM_CR1_DIR                         ((uint32_t)0x00000010)            /*!<Direction */
-
-#define  TIM_CR1_CMS                         ((uint32_t)0x00000060)            /*!<CMS[1:0] bits (Center-aligned mode selection) */
-#define  TIM_CR1_CMS_0                       ((uint32_t)0x00000020)            /*!<Bit 0 */
-#define  TIM_CR1_CMS_1                       ((uint32_t)0x00000040)            /*!<Bit 1 */
-
-#define  TIM_CR1_ARPE                        ((uint32_t)0x00000080)            /*!<Auto-reload preload enable */
-
-#define  TIM_CR1_CKD                         ((uint32_t)0x00000300)            /*!<CKD[1:0] bits (clock division) */
-#define  TIM_CR1_CKD_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CR1_CKD_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-/*******************  Bit definition for TIM_CR2 register  ********************/
-#define  TIM_CR2_CCDS                        ((uint32_t)0x00000008)            /*!<Capture/Compare DMA Selection */
-
-#define  TIM_CR2_MMS                         ((uint32_t)0x00000070)            /*!<MMS[2:0] bits (Master Mode Selection) */
-#define  TIM_CR2_MMS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CR2_MMS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CR2_MMS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CR2_TI1S                        ((uint32_t)0x00000080)            /*!<TI1 Selection */
-
-/*******************  Bit definition for TIM_SMCR register  *******************/
-#define  TIM_SMCR_SMS                        ((uint32_t)0x00000007)            /*!<SMS[2:0] bits (Slave mode selection) */
-#define  TIM_SMCR_SMS_0                      ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_SMCR_SMS_1                      ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define  TIM_SMCR_SMS_2                      ((uint32_t)0x00000004)            /*!<Bit 2 */
-
-#define  TIM_SMCR_OCCS                       ((uint32_t)0x00000008)            /*!< OCREF clear selection */
-
-#define  TIM_SMCR_TS                         ((uint32_t)0x00000070)            /*!<TS[2:0] bits (Trigger selection) */
-#define  TIM_SMCR_TS_0                       ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_SMCR_TS_1                       ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_SMCR_TS_2                       ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_SMCR_MSM                        ((uint32_t)0x00000080)            /*!<Master/slave mode */
-
-#define  TIM_SMCR_ETF                        ((uint32_t)0x00000F00)            /*!<ETF[3:0] bits (External trigger filter) */
-#define  TIM_SMCR_ETF_0                      ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_SMCR_ETF_1                      ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define  TIM_SMCR_ETF_2                      ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define  TIM_SMCR_ETF_3                      ((uint32_t)0x00000800)            /*!<Bit 3 */
-
-#define  TIM_SMCR_ETPS                       ((uint32_t)0x00003000)            /*!<ETPS[1:0] bits (External trigger prescaler) */
-#define  TIM_SMCR_ETPS_0                     ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_SMCR_ETPS_1                     ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  TIM_SMCR_ECE                        ((uint32_t)0x00004000)            /*!<External clock enable */
-#define  TIM_SMCR_ETP                        ((uint32_t)0x00008000)            /*!<External trigger polarity */
-
-/*******************  Bit definition for TIM_DIER register  *******************/
-#define  TIM_DIER_UIE                        ((uint32_t)0x00000001)            /*!<Update interrupt enable */
-#define  TIM_DIER_CC1IE                      ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt enable */
-#define  TIM_DIER_CC2IE                      ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt enable */
-#define  TIM_DIER_CC3IE                      ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt enable */
-#define  TIM_DIER_CC4IE                      ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt enable */
-#define  TIM_DIER_TIE                        ((uint32_t)0x00000040)            /*!<Trigger interrupt enable */
-#define  TIM_DIER_UDE                        ((uint32_t)0x00000100)            /*!<Update DMA request enable */
-#define  TIM_DIER_CC1DE                      ((uint32_t)0x00000200)            /*!<Capture/Compare 1 DMA request enable */
-#define  TIM_DIER_CC2DE                      ((uint32_t)0x00000400)            /*!<Capture/Compare 2 DMA request enable */
-#define  TIM_DIER_CC3DE                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 DMA request enable */
-#define  TIM_DIER_CC4DE                      ((uint32_t)0x00001000)            /*!<Capture/Compare 4 DMA request enable */
-#define  TIM_DIER_COMDE                      ((uint16_t)0x2000)            /*!<COM DMA request enable */
-#define  TIM_DIER_TDE                        ((uint32_t)0x00004000)            /*!<Trigger DMA request enable */
-
-/********************  Bit definition for TIM_SR register  ********************/
-#define  TIM_SR_UIF                          ((uint32_t)0x00000001)            /*!<Update interrupt Flag */
-#define  TIM_SR_CC1IF                        ((uint32_t)0x00000002)            /*!<Capture/Compare 1 interrupt Flag */
-#define  TIM_SR_CC2IF                        ((uint32_t)0x00000004)            /*!<Capture/Compare 2 interrupt Flag */
-#define  TIM_SR_CC3IF                        ((uint32_t)0x00000008)            /*!<Capture/Compare 3 interrupt Flag */
-#define  TIM_SR_CC4IF                        ((uint32_t)0x00000010)            /*!<Capture/Compare 4 interrupt Flag */
-#define  TIM_SR_TIF                          ((uint32_t)0x00000040)            /*!<Trigger interrupt Flag */
-#define  TIM_SR_CC1OF                        ((uint32_t)0x00000200)            /*!<Capture/Compare 1 Overcapture Flag */
-#define  TIM_SR_CC2OF                        ((uint32_t)0x00000400)            /*!<Capture/Compare 2 Overcapture Flag */
-#define  TIM_SR_CC3OF                        ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Overcapture Flag */
-#define  TIM_SR_CC4OF                        ((uint32_t)0x00001000)            /*!<Capture/Compare 4 Overcapture Flag */
-
-/*******************  Bit definition for TIM_EGR register  ********************/
-#define  TIM_EGR_UG                          ((uint32_t)0x00000001)               /*!<Update Generation */
-#define  TIM_EGR_CC1G                        ((uint32_t)0x00000002)               /*!<Capture/Compare 1 Generation */
-#define  TIM_EGR_CC2G                        ((uint32_t)0x00000004)               /*!<Capture/Compare 2 Generation */
-#define  TIM_EGR_CC3G                        ((uint32_t)0x00000008)               /*!<Capture/Compare 3 Generation */
-#define  TIM_EGR_CC4G                        ((uint32_t)0x00000010)               /*!<Capture/Compare 4 Generation */
-#define  TIM_EGR_TG                          ((uint32_t)0x00000040)               /*!<Trigger Generation */
-                   
-/******************  Bit definition for TIM_CCMR1 register  *******************/
-#define  TIM_CCMR1_CC1S                      ((uint32_t)0x00000003)            /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
-#define  TIM_CCMR1_CC1S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC1S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC1FE                     ((uint32_t)0x00000004)            /*!<Output Compare 1 Fast enable */
-#define  TIM_CCMR1_OC1PE                     ((uint32_t)0x00000008)            /*!<Output Compare 1 Preload enable */
-
-#define  TIM_CCMR1_OC1M                      ((uint32_t)0x00000070)            /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
-#define  TIM_CCMR1_OC1M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC1M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC1M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC1CE                     ((uint32_t)0x00000080)            /*!<Output Compare 1Clear Enable */
-
-#define  TIM_CCMR1_CC2S                      ((uint32_t)0x00000300)            /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
-#define  TIM_CCMR1_CC2S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CCMR1_CC2S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_OC2FE                     ((uint32_t)0x00000400)            /*!<Output Compare 2 Fast enable */
-#define  TIM_CCMR1_OC2PE                     ((uint32_t)0x00000800)            /*!<Output Compare 2 Preload enable */
-
-#define  TIM_CCMR1_OC2M                      ((uint32_t)0x00007000)            /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
-#define  TIM_CCMR1_OC2M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR1_OC2M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR1_OC2M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define  TIM_CCMR1_OC2CE                     ((uint32_t)0x00008000)            /*!<Output Compare 2 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR1_IC1PSC                    ((uint32_t)0x0000000C)            /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
-#define  TIM_CCMR1_IC1PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC1F                      ((uint32_t)0x000000F0)            /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
-#define  TIM_CCMR1_IC1F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC1F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC1F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC1F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define  TIM_CCMR1_IC2PSC                    ((uint32_t)0x00000C00)            /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
-#define  TIM_CCMR1_IC2PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define  TIM_CCMR1_IC2F                      ((uint32_t)0x0000F000)            /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
-#define  TIM_CCMR1_IC2F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR1_IC2F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR1_IC2F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR1_IC2F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/******************  Bit definition for TIM_CCMR2 register  *******************/
-#define  TIM_CCMR2_CC3S                      ((uint32_t)0x00000003)            /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
-#define  TIM_CCMR2_CC3S_0                    ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC3S_1                    ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC3FE                     ((uint32_t)0x00000004)            /*!<Output Compare 3 Fast enable */
-#define  TIM_CCMR2_OC3PE                     ((uint32_t)0x00000008)            /*!<Output Compare 3 Preload enable */
-
-#define  TIM_CCMR2_OC3M                      ((uint32_t)0x00000070)            /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
-#define  TIM_CCMR2_OC3M_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC3M_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC3M_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC3CE                     ((uint32_t)0x00000080)            /*!<Output Compare 3 Clear Enable */
-
-#define  TIM_CCMR2_CC4S                      ((uint32_t)0x00000300)            /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
-#define  TIM_CCMR2_CC4S_0                    ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_CCMR2_CC4S_1                    ((uint32_t)0x00000200)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_OC4FE                     ((uint32_t)0x00000400)            /*!<Output Compare 4 Fast enable */
-#define  TIM_CCMR2_OC4PE                     ((uint32_t)0x00000800)            /*!<Output Compare 4 Preload enable */
-
-#define  TIM_CCMR2_OC4M                      ((uint32_t)0x00007000)            /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
-#define  TIM_CCMR2_OC4M_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR2_OC4M_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR2_OC4M_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-
-#define  TIM_CCMR2_OC4CE                     ((uint32_t)0x00008000)            /*!<Output Compare 4 Clear Enable */
-
-/*----------------------------------------------------------------------------*/
-
-#define  TIM_CCMR2_IC3PSC                    ((uint32_t)0x0000000C)            /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
-#define  TIM_CCMR2_IC3PSC_0                  ((uint32_t)0x00000004)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3PSC_1                  ((uint32_t)0x00000008)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC3F                      ((uint32_t)0x000000F0)            /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
-#define  TIM_CCMR2_IC3F_0                    ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC3F_1                    ((uint32_t)0x00000020)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC3F_2                    ((uint32_t)0x00000040)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC3F_3                    ((uint32_t)0x00000080)            /*!<Bit 3 */
-
-#define  TIM_CCMR2_IC4PSC                    ((uint32_t)0x00000C00)            /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
-#define  TIM_CCMR2_IC4PSC_0                  ((uint32_t)0x00000400)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4PSC_1                  ((uint32_t)0x00000800)            /*!<Bit 1 */
-
-#define  TIM_CCMR2_IC4F                      ((uint32_t)0x0000F000)            /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
-#define  TIM_CCMR2_IC4F_0                    ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  TIM_CCMR2_IC4F_1                    ((uint32_t)0x00002000)            /*!<Bit 1 */
-#define  TIM_CCMR2_IC4F_2                    ((uint32_t)0x00004000)            /*!<Bit 2 */
-#define  TIM_CCMR2_IC4F_3                    ((uint32_t)0x00008000)            /*!<Bit 3 */
-
-/*******************  Bit definition for TIM_CCER register  *******************/
-#define  TIM_CCER_CC1E                       ((uint32_t)0x00000001)            /*!<Capture/Compare 1 output enable */
-#define  TIM_CCER_CC1P                       ((uint32_t)0x00000002)            /*!<Capture/Compare 1 output Polarity */
-#define  TIM_CCER_CC1NP                      ((uint32_t)0x00000008)            /*!<Capture/Compare 1 Complementary output Polarity */
-#define  TIM_CCER_CC2E                       ((uint32_t)0x00000010)            /*!<Capture/Compare 2 output enable */
-#define  TIM_CCER_CC2P                       ((uint32_t)0x00000020)            /*!<Capture/Compare 2 output Polarity */
-#define  TIM_CCER_CC2NP                      ((uint32_t)0x00000080)            /*!<Capture/Compare 2 Complementary output Polarity */
-#define  TIM_CCER_CC3E                       ((uint32_t)0x00000100)            /*!<Capture/Compare 3 output enable */
-#define  TIM_CCER_CC3P                       ((uint32_t)0x00000200)            /*!<Capture/Compare 3 output Polarity */
-#define  TIM_CCER_CC3NP                      ((uint32_t)0x00000800)            /*!<Capture/Compare 3 Complementary output Polarity */
-#define  TIM_CCER_CC4E                       ((uint32_t)0x00001000)            /*!<Capture/Compare 4 output enable */
-#define  TIM_CCER_CC4P                       ((uint32_t)0x00002000)            /*!<Capture/Compare 4 output Polarity */
-#define  TIM_CCER_CC4NP                      ((uint32_t)0x00008000)            /*!<Capture/Compare 4 Complementary output Polarity */
-
-/*******************  Bit definition for TIM_CNT register  ********************/
-#define  TIM_CNT_CNT                         ((uint32_t)0x0000FFFF)            /*!<Counter Value */
-
-/*******************  Bit definition for TIM_PSC register  ********************/
-#define  TIM_PSC_PSC                         ((uint32_t)0x0000FFFF)            /*!<Prescaler Value */
-
-/*******************  Bit definition for TIM_ARR register  ********************/
-#define  TIM_ARR_ARR                         ((uint32_t)0x0000FFFF)            /*!<actual auto-reload Value */
-           
-/*******************  Bit definition for TIM_CCR1 register  *******************/
-#define  TIM_CCR1_CCR1                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 1 Value */
-
-/*******************  Bit definition for TIM_CCR2 register  *******************/
-#define  TIM_CCR2_CCR2                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 2 Value */
-
-/*******************  Bit definition for TIM_CCR3 register  *******************/
-#define  TIM_CCR3_CCR3                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 3 Value */
-
-/*******************  Bit definition for TIM_CCR4 register  *******************/
-#define  TIM_CCR4_CCR4                       ((uint32_t)0x0000FFFF)            /*!<Capture/Compare 4 Value */
-
-/*******************  Bit definition for TIM_DCR register  ********************/
-#define  TIM_DCR_DBA                         ((uint32_t)0x0000001F)            /*!<DBA[4:0] bits (DMA Base Address) */
-#define  TIM_DCR_DBA_0                       ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_DCR_DBA_1                       ((uint32_t)0x00000002)            /*!<Bit 1 */
-#define  TIM_DCR_DBA_2                       ((uint32_t)0x00000004)            /*!<Bit 2 */
-#define  TIM_DCR_DBA_3                       ((uint32_t)0x00000008)            /*!<Bit 3 */
-#define  TIM_DCR_DBA_4                       ((uint32_t)0x00000010)            /*!<Bit 4 */
-
-#define  TIM_DCR_DBL                         ((uint32_t)0x00001F00)            /*!<DBL[4:0] bits (DMA Burst Length) */
-#define  TIM_DCR_DBL_0                       ((uint32_t)0x00000100)            /*!<Bit 0 */
-#define  TIM_DCR_DBL_1                       ((uint32_t)0x00000200)            /*!<Bit 1 */
-#define  TIM_DCR_DBL_2                       ((uint32_t)0x00000400)            /*!<Bit 2 */
-#define  TIM_DCR_DBL_3                       ((uint32_t)0x00000800)            /*!<Bit 3 */
-#define  TIM_DCR_DBL_4                       ((uint32_t)0x00001000)            /*!<Bit 4 */
-
-/*******************  Bit definition for TIM_DMAR register  *******************/
-#define  TIM_DMAR_DMAB                       ((uint32_t)0x0000FFFF)            /*!<DMA register for burst accesses */
-
-/*******************  Bit definition for TIM_OR register  *********************/
-#define  TIM_OR_TI1RMP                       ((uint32_t)0x00000003)            /*!<TI1_RMP[1:0] bits (TIM Input 1 remap) */
-#define  TIM_OR_TI1RMP_0                     ((uint32_t)0x00000001)            /*!<Bit 0 */
-#define  TIM_OR_TI1RMP_1                     ((uint32_t)0x00000002)            /*!<Bit 1 */
-
-#define  TIM_OR_ETR_RMP                      ((uint32_t)0x00000004)            /*!<ETR_RMP bit (TIM10/11 ETR remap)*/
-#define  TIM_OR_TI1_RMP_RI                   ((uint32_t)0x00000008)            /*!<TI1_RMP_RI bit (TIM10/11 Input 1 remap for Routing interface) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM9_OR_ITR1_RMP                    ((uint32_t)0x00000004)            /*!<ITR1_RMP bit (TIM9 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM2_OR_ITR1_RMP                    ((uint32_t)0x00000001)            /*!<ITR1_RMP bit (TIM2 Internal trigger 1 remap) */
-
-/*----------------------------------------------------------------------------*/
-#define  TIM3_OR_ITR2_RMP                    ((uint32_t)0x00000001)            /*!<ITR2_RMP bit (TIM3 Internal trigger 2 remap) */
-
-/*----------------------------------------------------------------------------*/
-
-
-/******************************************************************************/
-/*                                                                            */
-/*      Universal Synchronous Asynchronous Receiver Transmitter (USART)       */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for USART_SR register  *******************/
-#define  USART_SR_PE                         ((uint32_t)0x00000001)            /*!< Parity Error */
-#define  USART_SR_FE                         ((uint32_t)0x00000002)            /*!< Framing Error */
-#define  USART_SR_NE                         ((uint32_t)0x00000004)            /*!< Noise Error Flag */
-#define  USART_SR_ORE                        ((uint32_t)0x00000008)            /*!< OverRun Error */
-#define  USART_SR_IDLE                       ((uint32_t)0x00000010)            /*!< IDLE line detected */
-#define  USART_SR_RXNE                       ((uint32_t)0x00000020)            /*!< Read Data Register Not Empty */
-#define  USART_SR_TC                         ((uint32_t)0x00000040)            /*!< Transmission Complete */
-#define  USART_SR_TXE                        ((uint32_t)0x00000080)            /*!< Transmit Data Register Empty */
-#define  USART_SR_LBD                        ((uint32_t)0x00000100)            /*!< LIN Break Detection Flag */
-#define  USART_SR_CTS                        ((uint32_t)0x00000200)            /*!< CTS Flag */
-
-/*******************  Bit definition for USART_DR register  *******************/
-#define  USART_DR_DR                         ((uint32_t)0x000001FF)            /*!< Data value */
-
-/******************  Bit definition for USART_BRR register  *******************/
-#define  USART_BRR_DIV_FRACTION              ((uint32_t)0x0000000F)            /*!< Fraction of USARTDIV */
-#define  USART_BRR_DIV_MANTISSA              ((uint32_t)0x0000FFF0)            /*!< Mantissa of USARTDIV */
-
-/******************  Bit definition for USART_CR1 register  *******************/
-#define  USART_CR1_SBK                       ((uint32_t)0x00000001)            /*!< Send Break */
-#define  USART_CR1_RWU                       ((uint32_t)0x00000002)            /*!< Receiver wakeup */
-#define  USART_CR1_RE                        ((uint32_t)0x00000004)            /*!< Receiver Enable */
-#define  USART_CR1_TE                        ((uint32_t)0x00000008)            /*!< Transmitter Enable */
-#define  USART_CR1_IDLEIE                    ((uint32_t)0x00000010)            /*!< IDLE Interrupt Enable */
-#define  USART_CR1_RXNEIE                    ((uint32_t)0x00000020)            /*!< RXNE Interrupt Enable */
-#define  USART_CR1_TCIE                      ((uint32_t)0x00000040)            /*!< Transmission Complete Interrupt Enable */
-#define  USART_CR1_TXEIE                     ((uint32_t)0x00000080)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PEIE                      ((uint32_t)0x00000100)            /*!< PE Interrupt Enable */
-#define  USART_CR1_PS                        ((uint32_t)0x00000200)            /*!< Parity Selection */
-#define  USART_CR1_PCE                       ((uint32_t)0x00000400)            /*!< Parity Control Enable */
-#define  USART_CR1_WAKE                      ((uint32_t)0x00000800)            /*!< Wakeup method */
-#define  USART_CR1_M                         ((uint32_t)0x00001000)            /*!< Word length */
-#define  USART_CR1_UE                        ((uint32_t)0x00002000)            /*!< USART Enable */
-#define  USART_CR1_OVER8                     ((uint32_t)0x00008000)            /*!< Oversampling by 8-bit mode */
-
-/******************  Bit definition for USART_CR2 register  *******************/
-#define  USART_CR2_ADD                       ((uint32_t)0x0000000F)            /*!< Address of the USART node */
-#define  USART_CR2_LBDL                      ((uint32_t)0x00000020)            /*!< LIN Break Detection Length */
-#define  USART_CR2_LBDIE                     ((uint32_t)0x00000040)            /*!< LIN Break Detection Interrupt Enable */
-#define  USART_CR2_LBCL                      ((uint32_t)0x00000100)            /*!< Last Bit Clock pulse */
-#define  USART_CR2_CPHA                      ((uint32_t)0x00000200)            /*!< Clock Phase */
-#define  USART_CR2_CPOL                      ((uint32_t)0x00000400)            /*!< Clock Polarity */
-#define  USART_CR2_CLKEN                     ((uint32_t)0x00000800)            /*!< Clock Enable */
-
-#define  USART_CR2_STOP                      ((uint32_t)0x00003000)            /*!< STOP[1:0] bits (STOP bits) */
-#define  USART_CR2_STOP_0                    ((uint32_t)0x00001000)            /*!< Bit 0 */
-#define  USART_CR2_STOP_1                    ((uint32_t)0x00002000)            /*!< Bit 1 */
-
-#define  USART_CR2_LINEN                     ((uint32_t)0x00004000)            /*!< LIN mode enable */
-
-/******************  Bit definition for USART_CR3 register  *******************/
-#define  USART_CR3_EIE                       ((uint32_t)0x00000001)            /*!< Error Interrupt Enable */
-#define  USART_CR3_IREN                      ((uint32_t)0x00000002)            /*!< IrDA mode Enable */
-#define  USART_CR3_IRLP                      ((uint32_t)0x00000004)            /*!< IrDA Low-Power */
-#define  USART_CR3_HDSEL                     ((uint32_t)0x00000008)            /*!< Half-Duplex Selection */
-#define  USART_CR3_NACK                      ((uint32_t)0x00000010)            /*!< Smartcard NACK enable */
-#define  USART_CR3_SCEN                      ((uint32_t)0x00000020)            /*!< Smartcard mode enable */
-#define  USART_CR3_DMAR                      ((uint32_t)0x00000040)            /*!< DMA Enable Receiver */
-#define  USART_CR3_DMAT                      ((uint32_t)0x00000080)            /*!< DMA Enable Transmitter */
-#define  USART_CR3_RTSE                      ((uint32_t)0x00000100)            /*!< RTS Enable */
-#define  USART_CR3_CTSE                      ((uint32_t)0x00000200)            /*!< CTS Enable */
-#define  USART_CR3_CTSIE                     ((uint32_t)0x00000400)            /*!< CTS Interrupt Enable */
-#define  USART_CR3_ONEBIT                    ((uint32_t)0x00000800)            /*!< One sample bit method enable */
-
-/******************  Bit definition for USART_GTPR register  ******************/
-#define  USART_GTPR_PSC                      ((uint32_t)0x000000FF)            /*!< PSC[7:0] bits (Prescaler value) */
-#define  USART_GTPR_PSC_0                    ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  USART_GTPR_PSC_1                    ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  USART_GTPR_PSC_2                    ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  USART_GTPR_PSC_3                    ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  USART_GTPR_PSC_4                    ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  USART_GTPR_PSC_5                    ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  USART_GTPR_PSC_6                    ((uint32_t)0x00000040)            /*!< Bit 6 */
-#define  USART_GTPR_PSC_7                    ((uint32_t)0x00000080)            /*!< Bit 7 */
-
-#define  USART_GTPR_GT                       ((uint32_t)0x0000FF00)            /*!< Guard time value */
-
-/******************************************************************************/
-/*                                                                            */
-/*                     Universal Serial Bus (USB)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*!<Endpoint-specific registers */
-
-#define  USB_EP0R                              USB_BASE                        /*!< endpoint 0 register address */
-#define  USB_EP1R                             (USB_BASE + 0x00000004)         /*!< endpoint 1 register address */
-#define  USB_EP2R                             (USB_BASE + 0x00000008)         /*!< endpoint 2 register address */
-#define  USB_EP3R                             (USB_BASE + 0x0000000C)         /*!< endpoint 3 register address */
-#define  USB_EP4R                             (USB_BASE + 0x00000010)         /*!< endpoint 4 register address */
-#define  USB_EP5R                             (USB_BASE + 0x00000014)         /*!< endpoint 5 register address */
-#define  USB_EP6R                             (USB_BASE + 0x00000018)         /*!< endpoint 6 register address */
-#define  USB_EP7R                             (USB_BASE + 0x0000001C)         /*!< endpoint 7 register address */
-
-/* bit positions */ 
-#define  USB_EP_CTR_RX                        ((uint32_t)0x00008000)           /*!<  EndPoint Correct TRansfer RX */
-#define  USB_EP_DTOG_RX                       ((uint32_t)0x00004000)           /*!<  EndPoint Data TOGGLE RX */
-#define  USB_EPRX_STAT                        ((uint32_t)0x00003000)           /*!<  EndPoint RX STATus bit field */
-#define  USB_EP_SETUP                         ((uint32_t)0x00000800)           /*!<  EndPoint SETUP */
-#define  USB_EP_T_FIELD                       ((uint32_t)0x00000600)           /*!<  EndPoint TYPE */
-#define  USB_EP_KIND                          ((uint32_t)0x00000100)           /*!<  EndPoint KIND */
-#define  USB_EP_CTR_TX                        ((uint32_t)0x00000080)           /*!<  EndPoint Correct TRansfer TX */
-#define  USB_EP_DTOG_TX                       ((uint32_t)0x00000040)           /*!<  EndPoint Data TOGGLE TX */
-#define  USB_EPTX_STAT                        ((uint32_t)0x00000030)           /*!<  EndPoint TX STATus bit field */
-#define  USB_EPADDR_FIELD                     ((uint32_t)0x0000000F)           /*!<  EndPoint ADDRess FIELD */
-
-/* EndPoint REGister MASK (no toggle fields) */
-#define  USB_EPREG_MASK     (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
-                                                                               /*!< EP_TYPE[1:0] EndPoint TYPE */
-#define  USB_EP_TYPE_MASK                     ((uint32_t)0x00000600)           /*!< EndPoint TYPE Mask */
-#define  USB_EP_BULK                          ((uint32_t)0x00000000)           /*!< EndPoint BULK */
-#define  USB_EP_CONTROL                       ((uint32_t)0x00000200)           /*!< EndPoint CONTROL */
-#define  USB_EP_ISOCHRONOUS                   ((uint32_t)0x00000400)           /*!< EndPoint ISOCHRONOUS */
-#define  USB_EP_INTERRUPT                     ((uint32_t)0x00000600)           /*!< EndPoint INTERRUPT */
-#define  USB_EP_T_MASK      (~USB_EP_T_FIELD & USB_EPREG_MASK)
-                                                                 
-#define  USB_EPKIND_MASK    (~USB_EP_KIND & USB_EPREG_MASK)            /*!< EP_KIND EndPoint KIND */
-                                                                               /*!< STAT_TX[1:0] STATus for TX transfer */
-#define  USB_EP_TX_DIS                        ((uint32_t)0x00000000)           /*!< EndPoint TX DISabled */
-#define  USB_EP_TX_STALL                      ((uint32_t)0x00000010)           /*!< EndPoint TX STALLed */
-#define  USB_EP_TX_NAK                        ((uint32_t)0x00000020)           /*!< EndPoint TX NAKed */
-#define  USB_EP_TX_VALID                      ((uint32_t)0x00000030)           /*!< EndPoint TX VALID */
-#define  USB_EPTX_DTOG1                       ((uint32_t)0x00000010)           /*!< EndPoint TX Data TOGgle bit1 */
-#define  USB_EPTX_DTOG2                       ((uint32_t)0x00000020)           /*!< EndPoint TX Data TOGgle bit2 */
-#define  USB_EPTX_DTOGMASK  (USB_EPTX_STAT|USB_EPREG_MASK)
-                                                                               /*!< STAT_RX[1:0] STATus for RX transfer */
-#define  USB_EP_RX_DIS                        ((uint32_t)0x00000000)           /*!< EndPoint RX DISabled */
-#define  USB_EP_RX_STALL                      ((uint32_t)0x00001000)           /*!< EndPoint RX STALLed */
-#define  USB_EP_RX_NAK                        ((uint32_t)0x00002000)           /*!< EndPoint RX NAKed */
-#define  USB_EP_RX_VALID                      ((uint32_t)0x00003000)           /*!< EndPoint RX VALID */
-#define  USB_EPRX_DTOG1                       ((uint32_t)0x00001000)           /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOG2                       ((uint32_t)0x00002000)           /*!< EndPoint RX Data TOGgle bit1 */
-#define  USB_EPRX_DTOGMASK  (USB_EPRX_STAT|USB_EPREG_MASK)
-
-/*******************  Bit definition for USB_EP0R register  *******************/
-#define  USB_EP0R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP0R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP0R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP0R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP0R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP0R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP0R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP0R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP0R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP0R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP0R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP0R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP0R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP0R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP0R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP0R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP1R register  *******************/
-#define  USB_EP1R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP1R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP1R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP1R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP1R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP1R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP1R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP1R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP1R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP1R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP1R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP1R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP1R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP1R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP1R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP1R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP2R register  *******************/
-#define  USB_EP2R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP2R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP2R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP2R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP2R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP2R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP2R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP2R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP2R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP2R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP2R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP2R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP2R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP2R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP2R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP2R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP3R register  *******************/
-#define  USB_EP3R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP3R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP3R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP3R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP3R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP3R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP3R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP3R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP3R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP3R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP3R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP3R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP3R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP3R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP3R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP3R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP4R register  *******************/
-#define  USB_EP4R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP4R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP4R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP4R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP4R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP4R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP4R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP4R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP4R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP4R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP4R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP4R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP4R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP4R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP4R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP4R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP5R register  *******************/
-#define  USB_EP5R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP5R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP5R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP5R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP5R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP5R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP5R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP5R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP5R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP5R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP5R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP5R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP5R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP5R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP5R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP5R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP6R register  *******************/
-#define  USB_EP6R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP6R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP6R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP6R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP6R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP6R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP6R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP6R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP6R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP6R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP6R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP6R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP6R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP6R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP6R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP6R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*******************  Bit definition for USB_EP7R register  *******************/
-#define  USB_EP7R_EA                         ((uint32_t)0x0000000F)            /*!<Endpoint Address */
-
-#define  USB_EP7R_STAT_TX                    ((uint32_t)0x00000030)            /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
-#define  USB_EP7R_STAT_TX_0                  ((uint32_t)0x00000010)            /*!<Bit 0 */
-#define  USB_EP7R_STAT_TX_1                  ((uint32_t)0x00000020)            /*!<Bit 1 */
-
-#define  USB_EP7R_DTOG_TX                    ((uint32_t)0x00000040)            /*!<Data Toggle, for transmission transfers */
-#define  USB_EP7R_CTR_TX                     ((uint32_t)0x00000080)            /*!<Correct Transfer for transmission */
-#define  USB_EP7R_EP_KIND                    ((uint32_t)0x00000100)            /*!<Endpoint Kind */
-
-#define  USB_EP7R_EP_TYPE                    ((uint32_t)0x00000600)            /*!<EP_TYPE[1:0] bits (Endpoint type) */
-#define  USB_EP7R_EP_TYPE_0                  ((uint32_t)0x00000200)            /*!<Bit 0 */
-#define  USB_EP7R_EP_TYPE_1                  ((uint32_t)0x00000400)            /*!<Bit 1 */
-
-#define  USB_EP7R_SETUP                      ((uint32_t)0x00000800)            /*!<Setup transaction completed */
-
-#define  USB_EP7R_STAT_RX                    ((uint32_t)0x00003000)            /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
-#define  USB_EP7R_STAT_RX_0                  ((uint32_t)0x00001000)            /*!<Bit 0 */
-#define  USB_EP7R_STAT_RX_1                  ((uint32_t)0x00002000)            /*!<Bit 1 */
-
-#define  USB_EP7R_DTOG_RX                    ((uint32_t)0x00004000)            /*!<Data Toggle, for reception transfers */
-#define  USB_EP7R_CTR_RX                     ((uint32_t)0x00008000)            /*!<Correct Transfer for reception */
-
-/*!<Common registers */
-
-#define  USB_CNTR                             (USB_BASE + 0x00000040)          /*!< Control register */
-#define  USB_ISTR                             (USB_BASE + 0x00000044)          /*!< Interrupt status register */
-#define  USB_FNR                              (USB_BASE + 0x00000048)          /*!< Frame number register */
-#define  USB_DADDR                            (USB_BASE + 0x0000004C)          /*!< Device address register */
-#define  USB_BTABLE                           (USB_BASE + 0x00000050)          /*!< Buffer Table address register */
-
-
-
-/*******************  Bit definition for USB_CNTR register  *******************/
-#define  USB_CNTR_FRES                       ((uint32_t)0x00000001)            /*!<Force USB Reset */
-#define  USB_CNTR_PDWN                       ((uint32_t)0x00000002)            /*!<Power down */
-#define  USB_CNTR_LP_MODE                    ((uint32_t)0x00000004)            /*!<Low-power mode */
-#define  USB_CNTR_FSUSP                      ((uint32_t)0x00000008)            /*!<Force suspend */
-#define  USB_CNTR_RESUME                     ((uint32_t)0x00000010)            /*!<Resume request */
-#define  USB_CNTR_ESOFM                      ((uint32_t)0x00000100)            /*!<Expected Start Of Frame Interrupt Mask */
-#define  USB_CNTR_SOFM                       ((uint32_t)0x00000200)            /*!<Start Of Frame Interrupt Mask */
-#define  USB_CNTR_RESETM                     ((uint32_t)0x00000400)            /*!<RESET Interrupt Mask */
-#define  USB_CNTR_SUSPM                      ((uint32_t)0x00000800)            /*!<Suspend mode Interrupt Mask */
-#define  USB_CNTR_WKUPM                      ((uint32_t)0x00001000)            /*!<Wakeup Interrupt Mask */
-#define  USB_CNTR_ERRM                       ((uint32_t)0x00002000)            /*!<Error Interrupt Mask */
-#define  USB_CNTR_PMAOVRM                    ((uint32_t)0x00004000)            /*!<Packet Memory Area Over / Underrun Interrupt Mask */
-#define  USB_CNTR_CTRM                       ((uint32_t)0x00008000)            /*!<Correct Transfer Interrupt Mask */
-
-/*******************  Bit definition for USB_ISTR register  *******************/
-#define  USB_ISTR_EP_ID                      ((uint32_t)0x0000000F)            /*!<Endpoint Identifier */
-#define  USB_ISTR_DIR                        ((uint32_t)0x00000010)            /*!<Direction of transaction */
-#define  USB_ISTR_ESOF                       ((uint32_t)0x00000100)            /*!<Expected Start Of Frame */
-#define  USB_ISTR_SOF                        ((uint32_t)0x00000200)            /*!<Start Of Frame */
-#define  USB_ISTR_RESET                      ((uint32_t)0x00000400)            /*!<USB RESET request */
-#define  USB_ISTR_SUSP                       ((uint32_t)0x00000800)            /*!<Suspend mode request */
-#define  USB_ISTR_WKUP                       ((uint32_t)0x00001000)            /*!<Wake up */
-#define  USB_ISTR_ERR                        ((uint32_t)0x00002000)            /*!<Error */
-#define  USB_ISTR_PMAOVRM                    ((uint32_t)0x00004000)            /*!<Packet Memory Area Over / Underrun */
-#define  USB_ISTR_CTR                        ((uint32_t)0x00008000)            /*!<Correct Transfer */
-
-#define  USB_CLR_CTR                          (~USB_ISTR_CTR)                  /*!< clear Correct TRansfer bit */
-#define  USB_CLR_PMAOVRM                      (~USB_ISTR_PMAOVR)               /*!< clear DMA OVeR/underrun bit*/
-#define  USB_CLR_ERR                          (~USB_ISTR_ERR)                  /*!< clear ERRor bit */
-#define  USB_CLR_WKUP                         (~USB_ISTR_WKUP)                 /*!< clear WaKe UP bit */
-#define  USB_CLR_SUSP                         (~USB_ISTR_SUSP)                 /*!< clear SUSPend bit */
-#define  USB_CLR_RESET                        (~USB_ISTR_RESET)                /*!< clear RESET bit */
-#define  USB_CLR_SOF                          (~USB_ISTR_SOF)                  /*!< clear Start Of Frame bit */
-#define  USB_CLR_ESOF                         (~USB_ISTR_ESOF)                 /*!< clear Expected Start Of Frame bit */
-
-
-/*******************  Bit definition for USB_FNR register  ********************/
-#define  USB_FNR_FN                          ((uint32_t)0x000007FF)            /*!<Frame Number */
-#define  USB_FNR_LSOF                        ((uint32_t)0x00001800)            /*!<Lost SOF */
-#define  USB_FNR_LCK                         ((uint32_t)0x00002000)            /*!<Locked */
-#define  USB_FNR_RXDM                        ((uint32_t)0x00004000)            /*!<Receive Data - Line Status */
-#define  USB_FNR_RXDP                        ((uint32_t)0x00008000)            /*!<Receive Data + Line Status */
-
-/******************  Bit definition for USB_DADDR register  *******************/
-#define  USB_DADDR_ADD                       ((uint32_t)0x0000007F)               /*!<ADD[6:0] bits (Device Address) */
-#define  USB_DADDR_ADD0                      ((uint32_t)0x00000001)               /*!<Bit 0 */
-#define  USB_DADDR_ADD1                      ((uint32_t)0x00000002)               /*!<Bit 1 */
-#define  USB_DADDR_ADD2                      ((uint32_t)0x00000004)               /*!<Bit 2 */
-#define  USB_DADDR_ADD3                      ((uint32_t)0x00000008)               /*!<Bit 3 */
-#define  USB_DADDR_ADD4                      ((uint32_t)0x00000010)               /*!<Bit 4 */
-#define  USB_DADDR_ADD5                      ((uint32_t)0x00000020)               /*!<Bit 5 */
-#define  USB_DADDR_ADD6                      ((uint32_t)0x00000040)               /*!<Bit 6 */
-
-#define  USB_DADDR_EF                        ((uint32_t)0x00000080)               /*!<Enable Function */
-
-/******************  Bit definition for USB_BTABLE register  ******************/    
-#define  USB_BTABLE_BTABLE                   ((uint32_t)0x0000FFF8)            /*!<Buffer Table */
-
-/*!< Buffer descriptor table */
-/*****************  Bit definition for USB_ADDR0_TX register  *****************/
-#define  USB_ADDR0_TX_ADDR0_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_TX register  *****************/
-#define  USB_ADDR1_TX_ADDR1_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_TX register  *****************/
-#define  USB_ADDR2_TX_ADDR2_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_TX register  *****************/
-#define  USB_ADDR3_TX_ADDR3_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_TX register  *****************/
-#define  USB_ADDR4_TX_ADDR4_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_TX register  *****************/
-#define  USB_ADDR5_TX_ADDR5_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_TX register  *****************/
-#define  USB_ADDR6_TX_ADDR6_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_TX register  *****************/
-#define  USB_ADDR7_TX_ADDR7_TX               ((uint32_t)0x0000FFFE)            /*!< Transmission Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_TX register  ****************/
-#define  USB_COUNT0_TX_COUNT0_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 0 */
-
-/*****************  Bit definition for USB_COUNT1_TX register  ****************/
-#define  USB_COUNT1_TX_COUNT1_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 1 */
-
-/*****************  Bit definition for USB_COUNT2_TX register  ****************/
-#define  USB_COUNT2_TX_COUNT2_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 2 */
-
-/*****************  Bit definition for USB_COUNT3_TX register  ****************/
-#define  USB_COUNT3_TX_COUNT3_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 3 */
-
-/*****************  Bit definition for USB_COUNT4_TX register  ****************/
-#define  USB_COUNT4_TX_COUNT4_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 4 */
-
-/*****************  Bit definition for USB_COUNT5_TX register  ****************/
-#define  USB_COUNT5_TX_COUNT5_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 5 */
-
-/*****************  Bit definition for USB_COUNT6_TX register  ****************/
-#define  USB_COUNT6_TX_COUNT6_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 6 */
-
-/*****************  Bit definition for USB_COUNT7_TX register  ****************/
-#define  USB_COUNT7_TX_COUNT7_TX             ((uint32_t)0x000003FF)            /*!< Transmission Byte Count 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_TX_0 register  ***************/
-#define  USB_COUNT0_TX_0_COUNT0_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 0 (low) */
-
-/****************  Bit definition for USB_COUNT0_TX_1 register  ***************/
-#define  USB_COUNT0_TX_1_COUNT0_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 0 (high) */
-
-/****************  Bit definition for USB_COUNT1_TX_0 register  ***************/
-#define  USB_COUNT1_TX_0_COUNT1_TX_0          ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 1 (low) */
-
-/****************  Bit definition for USB_COUNT1_TX_1 register  ***************/
-#define  USB_COUNT1_TX_1_COUNT1_TX_1          ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 1 (high) */
-
-/****************  Bit definition for USB_COUNT2_TX_0 register  ***************/
-#define  USB_COUNT2_TX_0_COUNT2_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 2 (low) */
-
-/****************  Bit definition for USB_COUNT2_TX_1 register  ***************/
-#define  USB_COUNT2_TX_1_COUNT2_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 2 (high) */
-
-/****************  Bit definition for USB_COUNT3_TX_0 register  ***************/
-#define  USB_COUNT3_TX_0_COUNT3_TX_0         ((uint32_t)0x0000000003FF)        /*!< Transmission Byte Count 3 (low) */
-
-/****************  Bit definition for USB_COUNT3_TX_1 register  ***************/
-#define  USB_COUNT3_TX_1_COUNT3_TX_1         ((uint32_t)0x000003FF0000)        /*!< Transmission Byte Count 3 (high) */
-
-/****************  Bit definition for USB_COUNT4_TX_0 register  ***************/
-#define  USB_COUNT4_TX_0_COUNT4_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 4 (low) */
-
-/****************  Bit definition for USB_COUNT4_TX_1 register  ***************/
-#define  USB_COUNT4_TX_1_COUNT4_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 4 (high) */
-
-/****************  Bit definition for USB_COUNT5_TX_0 register  ***************/
-#define  USB_COUNT5_TX_0_COUNT5_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 5 (low) */
-
-/****************  Bit definition for USB_COUNT5_TX_1 register  ***************/
-#define  USB_COUNT5_TX_1_COUNT5_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 5 (high) */
-
-/****************  Bit definition for USB_COUNT6_TX_0 register  ***************/
-#define  USB_COUNT6_TX_0_COUNT6_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 6 (low) */
-
-/****************  Bit definition for USB_COUNT6_TX_1 register  ***************/
-#define  USB_COUNT6_TX_1_COUNT6_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 6 (high) */
-
-/****************  Bit definition for USB_COUNT7_TX_0 register  ***************/
-#define  USB_COUNT7_TX_0_COUNT7_TX_0         ((uint32_t)0x000003FF)        /*!< Transmission Byte Count 7 (low) */
-
-/****************  Bit definition for USB_COUNT7_TX_1 register  ***************/
-#define  USB_COUNT7_TX_1_COUNT7_TX_1         ((uint32_t)0x03FF0000)        /*!< Transmission Byte Count 7 (high) */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_ADDR0_RX register  *****************/
-#define  USB_ADDR0_RX_ADDR0_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 0 */
-
-/*****************  Bit definition for USB_ADDR1_RX register  *****************/
-#define  USB_ADDR1_RX_ADDR1_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 1 */
-
-/*****************  Bit definition for USB_ADDR2_RX register  *****************/
-#define  USB_ADDR2_RX_ADDR2_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 2 */
-
-/*****************  Bit definition for USB_ADDR3_RX register  *****************/
-#define  USB_ADDR3_RX_ADDR3_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 3 */
-
-/*****************  Bit definition for USB_ADDR4_RX register  *****************/
-#define  USB_ADDR4_RX_ADDR4_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 4 */
-
-/*****************  Bit definition for USB_ADDR5_RX register  *****************/
-#define  USB_ADDR5_RX_ADDR5_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 5 */
-
-/*****************  Bit definition for USB_ADDR6_RX register  *****************/
-#define  USB_ADDR6_RX_ADDR6_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 6 */
-
-/*****************  Bit definition for USB_ADDR7_RX register  *****************/
-#define  USB_ADDR7_RX_ADDR7_RX               ((uint32_t)0x0000FFFE)            /*!< Reception Buffer Address 7 */
-
-/*----------------------------------------------------------------------------*/
-
-/*****************  Bit definition for USB_COUNT0_RX register  ****************/
-#define  USB_COUNT0_RX_COUNT0_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT0_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT0_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT0_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT0_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT0_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT0_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT1_RX register  ****************/
-#define  USB_COUNT1_RX_COUNT1_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT1_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT1_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT1_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT1_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT1_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT1_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT2_RX register  ****************/
-#define  USB_COUNT2_RX_COUNT2_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT2_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT2_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT2_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT2_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT2_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT2_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT3_RX register  ****************/
-#define  USB_COUNT3_RX_COUNT3_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT3_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT3_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT3_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT3_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT3_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT3_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT4_RX register  ****************/
-#define  USB_COUNT4_RX_COUNT4_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT4_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT4_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT4_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT4_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT4_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT4_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT5_RX register  ****************/
-#define  USB_COUNT5_RX_COUNT5_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT5_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT5_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT5_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT5_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT5_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT5_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT6_RX register  ****************/
-#define  USB_COUNT6_RX_COUNT6_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT6_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT6_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT6_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT6_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT6_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT6_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*****************  Bit definition for USB_COUNT7_RX register  ****************/
-#define  USB_COUNT7_RX_COUNT7_RX             ((uint32_t)0x000003FF)            /*!< Reception Byte Count */
-
-#define  USB_COUNT7_RX_NUM_BLOCK             ((uint32_t)0x00007C00)            /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
-#define  USB_COUNT7_RX_NUM_BLOCK_0           ((uint32_t)0x00000400)            /*!< Bit 0 */
-#define  USB_COUNT7_RX_NUM_BLOCK_1           ((uint32_t)0x00000800)            /*!< Bit 1 */
-#define  USB_COUNT7_RX_NUM_BLOCK_2           ((uint32_t)0x00001000)            /*!< Bit 2 */
-#define  USB_COUNT7_RX_NUM_BLOCK_3           ((uint32_t)0x00002000)            /*!< Bit 3 */
-#define  USB_COUNT7_RX_NUM_BLOCK_4           ((uint32_t)0x00004000)            /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_BLSIZE                ((uint32_t)0x00008000)            /*!< BLock SIZE */
-
-/*----------------------------------------------------------------------------*/
-
-/****************  Bit definition for USB_COUNT0_RX_0 register  ***************/
-#define  USB_COUNT0_RX_0_COUNT0_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT0_RX_1 register  ***************/
-#define  USB_COUNT0_RX_1_COUNT0_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT0_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT0_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT1_RX_0 register  ***************/
-#define  USB_COUNT1_RX_0_COUNT1_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT1_RX_1 register  ***************/
-#define  USB_COUNT1_RX_1_COUNT1_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT1_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT1_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT2_RX_0 register  ***************/
-#define  USB_COUNT2_RX_0_COUNT2_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT2_RX_1 register  ***************/
-#define  USB_COUNT2_RX_1_COUNT2_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT2_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT2_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT3_RX_0 register  ***************/
-#define  USB_COUNT3_RX_0_COUNT3_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT3_RX_1 register  ***************/
-#define  USB_COUNT3_RX_1_COUNT3_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT3_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT3_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT4_RX_0 register  ***************/
-#define  USB_COUNT4_RX_0_COUNT4_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_0      ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_1      ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_2      ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_3      ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_0_NUM_BLOCK_0_4      ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT4_RX_1 register  ***************/
-#define  USB_COUNT4_RX_1_COUNT4_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT4_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT4_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/****************  Bit definition for USB_COUNT5_RX_0 register  ***************/
-#define  USB_COUNT5_RX_0_COUNT5_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT5_RX_1 register  ***************/
-#define  USB_COUNT5_RX_1_COUNT5_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT5_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT5_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT6_RX_0  register  ***************/
-#define  USB_COUNT6_RX_0_COUNT6_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/****************  Bit definition for USB_COUNT6_RX_1 register  ***************/
-#define  USB_COUNT6_RX_1_COUNT6_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT6_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT6_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/***************  Bit definition for USB_COUNT7_RX_0 register  ****************/
-#define  USB_COUNT7_RX_0_COUNT7_RX_0         ((uint32_t)0x000003FF)        /*!< Reception Byte Count (low) */
-
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0         ((uint32_t)0x00007C00)        /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_0       ((uint32_t)0x00000400)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_1       ((uint32_t)0x00000800)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_2       ((uint32_t)0x00001000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_3       ((uint32_t)0x00002000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_0_NUM_BLOCK_0_4       ((uint32_t)0x00004000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_0_BLSIZE_0            ((uint32_t)0x00008000)        /*!< BLock SIZE (low) */
-
-/***************  Bit definition for USB_COUNT7_RX_1 register  ****************/
-#define  USB_COUNT7_RX_1_COUNT7_RX_1         ((uint32_t)0x03FF0000)        /*!< Reception Byte Count (high) */
-
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1         ((uint32_t)0x7C000000)        /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_0       ((uint32_t)0x04000000)        /*!< Bit 0 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_1       ((uint32_t)0x08000000)        /*!< Bit 1 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_2       ((uint32_t)0x10000000)        /*!< Bit 2 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_3       ((uint32_t)0x20000000)        /*!< Bit 3 */
-#define  USB_COUNT7_RX_1_NUM_BLOCK_1_4       ((uint32_t)0x40000000)        /*!< Bit 4 */
-
-#define  USB_COUNT7_RX_1_BLSIZE_1            ((uint32_t)0x80000000)        /*!< BLock SIZE (high) */
-
-/******************************************************************************/
-/*                                                                            */
-/*                         Window WATCHDOG (WWDG)                             */
-/*                                                                            */
-/******************************************************************************/
-
-/*******************  Bit definition for WWDG_CR register  ********************/
-#define  WWDG_CR_T                           ((uint32_t)0x0000007F)               /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
-#define  WWDG_CR_T0                          ((uint32_t)0x00000001)               /*!< Bit 0 */
-#define  WWDG_CR_T1                          ((uint32_t)0x00000002)               /*!< Bit 1 */
-#define  WWDG_CR_T2                          ((uint32_t)0x00000004)               /*!< Bit 2 */
-#define  WWDG_CR_T3                          ((uint32_t)0x00000008)               /*!< Bit 3 */
-#define  WWDG_CR_T4                          ((uint32_t)0x00000010)               /*!< Bit 4 */
-#define  WWDG_CR_T5                          ((uint32_t)0x00000020)               /*!< Bit 5 */
-#define  WWDG_CR_T6                          ((uint32_t)0x00000040)               /*!< Bit 6 */
-
-#define  WWDG_CR_WDGA                        ((uint32_t)0x00000080)               /*!< Activation bit */
-
-/*******************  Bit definition for WWDG_CFR register  *******************/
-#define  WWDG_CFR_W                          ((uint32_t)0x0000007F)            /*!< W[6:0] bits (7-bit window value) */
-#define  WWDG_CFR_W0                         ((uint32_t)0x00000001)            /*!< Bit 0 */
-#define  WWDG_CFR_W1                         ((uint32_t)0x00000002)            /*!< Bit 1 */
-#define  WWDG_CFR_W2                         ((uint32_t)0x00000004)            /*!< Bit 2 */
-#define  WWDG_CFR_W3                         ((uint32_t)0x00000008)            /*!< Bit 3 */
-#define  WWDG_CFR_W4                         ((uint32_t)0x00000010)            /*!< Bit 4 */
-#define  WWDG_CFR_W5                         ((uint32_t)0x00000020)            /*!< Bit 5 */
-#define  WWDG_CFR_W6                         ((uint32_t)0x00000040)            /*!< Bit 6 */
-
-#define  WWDG_CFR_WDGTB                      ((uint32_t)0x00000180)            /*!< WDGTB[1:0] bits (Timer Base) */
-#define  WWDG_CFR_WDGTB0                     ((uint32_t)0x00000080)            /*!< Bit 0 */
-#define  WWDG_CFR_WDGTB1                     ((uint32_t)0x00000100)            /*!< Bit 1 */
-
-#define  WWDG_CFR_EWI                        ((uint32_t)0x00000200)            /*!< Early Wakeup Interrupt */
-
-/*******************  Bit definition for WWDG_SR register  ********************/
-#define  WWDG_SR_EWIF                        ((uint32_t)0x00000001)               /*!< Early Wakeup Interrupt Flag */
-
-/******************************************************************************/
-/*                                                                            */
-/*                        SystemTick (SysTick)                                */
-/*                                                                            */
-/******************************************************************************/
-
-/*****************  Bit definition for SysTick_CTRL register  *****************/
-#define  SysTick_CTRL_ENABLE                 ((uint32_t)0x00000001)        /*!< Counter enable */
-#define  SysTick_CTRL_TICKINT                ((uint32_t)0x00000002)        /*!< Counting down to 0 pends the SysTick handler */
-#define  SysTick_CTRL_CLKSOURCE              ((uint32_t)0x00000004)        /*!< Clock source */
-#define  SysTick_CTRL_COUNTFLAG              ((uint32_t)0x00010000)        /*!< Count Flag */
-
-/*****************  Bit definition for SysTick_LOAD register  *****************/
-#define  SysTick_LOAD_RELOAD                 ((uint32_t)0x00FFFFFF)        /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
-
-/*****************  Bit definition for SysTick_VAL register  ******************/
-#define  SysTick_VAL_CURRENT                 ((uint32_t)0x00FFFFFF)        /*!< Current value at the time the register is accessed */
-
-/*****************  Bit definition for SysTick_CALIB register  ****************/
-#define  SysTick_CALIB_TENMS                 ((uint32_t)0x00FFFFFF)        /*!< Reload value to use for 10ms timing */
-#define  SysTick_CALIB_SKEW                  ((uint32_t)0x40000000)        /*!< Calibration value is not exactly 10 ms */
-#define  SysTick_CALIB_NOREF                 ((uint32_t)0x80000000)        /*!< The reference clock is not provided */
-
-/******************************************************************************/
-/*                                                                            */
-/*               Nested Vectored Interrupt Controller (NVIC)                  */
-/*                                                                            */
-/******************************************************************************/
-
-/******************  Bit definition for NVIC_ISER register  *******************/
-#define  NVIC_ISER_SETENA                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set enable bits */
-#define  NVIC_ISER_SETENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISER_SETENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISER_SETENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISER_SETENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISER_SETENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISER_SETENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISER_SETENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISER_SETENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISER_SETENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISER_SETENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISER_SETENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISER_SETENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISER_SETENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISER_SETENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISER_SETENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISER_SETENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISER_SETENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISER_SETENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISER_SETENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISER_SETENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISER_SETENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISER_SETENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISER_SETENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISER_SETENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISER_SETENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISER_SETENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISER_SETENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISER_SETENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISER_SETENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISER_SETENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISER_SETENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISER_SETENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICER register  *******************/
-#define  NVIC_ICER_CLRENA                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-enable bits */
-#define  NVIC_ICER_CLRENA_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICER_CLRENA_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICER_CLRENA_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICER_CLRENA_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICER_CLRENA_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICER_CLRENA_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICER_CLRENA_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICER_CLRENA_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICER_CLRENA_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICER_CLRENA_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICER_CLRENA_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICER_CLRENA_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICER_CLRENA_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICER_CLRENA_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICER_CLRENA_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICER_CLRENA_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICER_CLRENA_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICER_CLRENA_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICER_CLRENA_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICER_CLRENA_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICER_CLRENA_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICER_CLRENA_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICER_CLRENA_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICER_CLRENA_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICER_CLRENA_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICER_CLRENA_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICER_CLRENA_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICER_CLRENA_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICER_CLRENA_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICER_CLRENA_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICER_CLRENA_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICER_CLRENA_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ISPR register  *******************/
-#define  NVIC_ISPR_SETPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt set-pending bits */
-#define  NVIC_ISPR_SETPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ISPR_SETPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ISPR_SETPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ISPR_SETPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ISPR_SETPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ISPR_SETPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ISPR_SETPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ISPR_SETPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ISPR_SETPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ISPR_SETPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ISPR_SETPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ISPR_SETPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ISPR_SETPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ISPR_SETPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ISPR_SETPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ISPR_SETPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ISPR_SETPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ISPR_SETPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ISPR_SETPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ISPR_SETPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ISPR_SETPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ISPR_SETPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ISPR_SETPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ISPR_SETPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ISPR_SETPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ISPR_SETPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ISPR_SETPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ISPR_SETPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ISPR_SETPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ISPR_SETPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ISPR_SETPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ISPR_SETPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_ICPR register  *******************/
-#define  NVIC_ICPR_CLRPEND                   ((uint32_t)0xFFFFFFFF)        /*!< Interrupt clear-pending bits */
-#define  NVIC_ICPR_CLRPEND_0                 ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_ICPR_CLRPEND_1                 ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_ICPR_CLRPEND_2                 ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_ICPR_CLRPEND_3                 ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_ICPR_CLRPEND_4                 ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_ICPR_CLRPEND_5                 ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_ICPR_CLRPEND_6                 ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_ICPR_CLRPEND_7                 ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_ICPR_CLRPEND_8                 ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_ICPR_CLRPEND_9                 ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_ICPR_CLRPEND_10                ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_ICPR_CLRPEND_11                ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_ICPR_CLRPEND_12                ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_ICPR_CLRPEND_13                ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_ICPR_CLRPEND_14                ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_ICPR_CLRPEND_15                ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_ICPR_CLRPEND_16                ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_ICPR_CLRPEND_17                ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_ICPR_CLRPEND_18                ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_ICPR_CLRPEND_19                ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_ICPR_CLRPEND_20                ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_ICPR_CLRPEND_21                ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_ICPR_CLRPEND_22                ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_ICPR_CLRPEND_23                ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_ICPR_CLRPEND_24                ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_ICPR_CLRPEND_25                ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_ICPR_CLRPEND_26                ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_ICPR_CLRPEND_27                ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_ICPR_CLRPEND_28                ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_ICPR_CLRPEND_29                ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_ICPR_CLRPEND_30                ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_ICPR_CLRPEND_31                ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_IABR register  *******************/
-#define  NVIC_IABR_ACTIVE                    ((uint32_t)0xFFFFFFFF)        /*!< Interrupt active flags */
-#define  NVIC_IABR_ACTIVE_0                  ((uint32_t)0x00000001)        /*!< bit 0 */
-#define  NVIC_IABR_ACTIVE_1                  ((uint32_t)0x00000002)        /*!< bit 1 */
-#define  NVIC_IABR_ACTIVE_2                  ((uint32_t)0x00000004)        /*!< bit 2 */
-#define  NVIC_IABR_ACTIVE_3                  ((uint32_t)0x00000008)        /*!< bit 3 */
-#define  NVIC_IABR_ACTIVE_4                  ((uint32_t)0x00000010)        /*!< bit 4 */
-#define  NVIC_IABR_ACTIVE_5                  ((uint32_t)0x00000020)        /*!< bit 5 */
-#define  NVIC_IABR_ACTIVE_6                  ((uint32_t)0x00000040)        /*!< bit 6 */
-#define  NVIC_IABR_ACTIVE_7                  ((uint32_t)0x00000080)        /*!< bit 7 */
-#define  NVIC_IABR_ACTIVE_8                  ((uint32_t)0x00000100)        /*!< bit 8 */
-#define  NVIC_IABR_ACTIVE_9                  ((uint32_t)0x00000200)        /*!< bit 9 */
-#define  NVIC_IABR_ACTIVE_10                 ((uint32_t)0x00000400)        /*!< bit 10 */
-#define  NVIC_IABR_ACTIVE_11                 ((uint32_t)0x00000800)        /*!< bit 11 */
-#define  NVIC_IABR_ACTIVE_12                 ((uint32_t)0x00001000)        /*!< bit 12 */
-#define  NVIC_IABR_ACTIVE_13                 ((uint32_t)0x00002000)        /*!< bit 13 */
-#define  NVIC_IABR_ACTIVE_14                 ((uint32_t)0x00004000)        /*!< bit 14 */
-#define  NVIC_IABR_ACTIVE_15                 ((uint32_t)0x00008000)        /*!< bit 15 */
-#define  NVIC_IABR_ACTIVE_16                 ((uint32_t)0x00010000)        /*!< bit 16 */
-#define  NVIC_IABR_ACTIVE_17                 ((uint32_t)0x00020000)        /*!< bit 17 */
-#define  NVIC_IABR_ACTIVE_18                 ((uint32_t)0x00040000)        /*!< bit 18 */
-#define  NVIC_IABR_ACTIVE_19                 ((uint32_t)0x00080000)        /*!< bit 19 */
-#define  NVIC_IABR_ACTIVE_20                 ((uint32_t)0x00100000)        /*!< bit 20 */
-#define  NVIC_IABR_ACTIVE_21                 ((uint32_t)0x00200000)        /*!< bit 21 */
-#define  NVIC_IABR_ACTIVE_22                 ((uint32_t)0x00400000)        /*!< bit 22 */
-#define  NVIC_IABR_ACTIVE_23                 ((uint32_t)0x00800000)        /*!< bit 23 */
-#define  NVIC_IABR_ACTIVE_24                 ((uint32_t)0x01000000)        /*!< bit 24 */
-#define  NVIC_IABR_ACTIVE_25                 ((uint32_t)0x02000000)        /*!< bit 25 */
-#define  NVIC_IABR_ACTIVE_26                 ((uint32_t)0x04000000)        /*!< bit 26 */
-#define  NVIC_IABR_ACTIVE_27                 ((uint32_t)0x08000000)        /*!< bit 27 */
-#define  NVIC_IABR_ACTIVE_28                 ((uint32_t)0x10000000)        /*!< bit 28 */
-#define  NVIC_IABR_ACTIVE_29                 ((uint32_t)0x20000000)        /*!< bit 29 */
-#define  NVIC_IABR_ACTIVE_30                 ((uint32_t)0x40000000)        /*!< bit 30 */
-#define  NVIC_IABR_ACTIVE_31                 ((uint32_t)0x80000000)        /*!< bit 31 */
-
-/******************  Bit definition for NVIC_PRI0 register  *******************/
-#define  NVIC_IPR0_PRI_0                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 0 */
-#define  NVIC_IPR0_PRI_1                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 1 */
-#define  NVIC_IPR0_PRI_2                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 2 */
-#define  NVIC_IPR0_PRI_3                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 3 */
-
-/******************  Bit definition for NVIC_PRI1 register  *******************/
-#define  NVIC_IPR1_PRI_4                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 4 */
-#define  NVIC_IPR1_PRI_5                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 5 */
-#define  NVIC_IPR1_PRI_6                     ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 6 */
-#define  NVIC_IPR1_PRI_7                     ((uint32_t)0xFF000000)        /*!< Priority of interrupt 7 */
-
-/******************  Bit definition for NVIC_PRI2 register  *******************/
-#define  NVIC_IPR2_PRI_8                     ((uint32_t)0x000000FF)        /*!< Priority of interrupt 8 */
-#define  NVIC_IPR2_PRI_9                     ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 9 */
-#define  NVIC_IPR2_PRI_10                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 10 */
-#define  NVIC_IPR2_PRI_11                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 11 */
-
-/******************  Bit definition for NVIC_PRI3 register  *******************/
-#define  NVIC_IPR3_PRI_12                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 12 */
-#define  NVIC_IPR3_PRI_13                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 13 */
-#define  NVIC_IPR3_PRI_14                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 14 */
-#define  NVIC_IPR3_PRI_15                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 15 */
-
-/******************  Bit definition for NVIC_PRI4 register  *******************/
-#define  NVIC_IPR4_PRI_16                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 16 */
-#define  NVIC_IPR4_PRI_17                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 17 */
-#define  NVIC_IPR4_PRI_18                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 18 */
-#define  NVIC_IPR4_PRI_19                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 19 */
-
-/******************  Bit definition for NVIC_PRI5 register  *******************/
-#define  NVIC_IPR5_PRI_20                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 20 */
-#define  NVIC_IPR5_PRI_21                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 21 */
-#define  NVIC_IPR5_PRI_22                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 22 */
-#define  NVIC_IPR5_PRI_23                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 23 */
-
-/******************  Bit definition for NVIC_PRI6 register  *******************/
-#define  NVIC_IPR6_PRI_24                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 24 */
-#define  NVIC_IPR6_PRI_25                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 25 */
-#define  NVIC_IPR6_PRI_26                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 26 */
-#define  NVIC_IPR6_PRI_27                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 27 */
-
-/******************  Bit definition for NVIC_PRI7 register  *******************/
-#define  NVIC_IPR7_PRI_28                    ((uint32_t)0x000000FF)        /*!< Priority of interrupt 28 */
-#define  NVIC_IPR7_PRI_29                    ((uint32_t)0x0000FF00)        /*!< Priority of interrupt 29 */
-#define  NVIC_IPR7_PRI_30                    ((uint32_t)0x00FF0000)        /*!< Priority of interrupt 30 */
-#define  NVIC_IPR7_PRI_31                    ((uint32_t)0xFF000000)        /*!< Priority of interrupt 31 */
-
-/******************  Bit definition for SCB_CPUID register  *******************/
-#define  SCB_CPUID_REVISION                  ((uint32_t)0x0000000F)        /*!< Implementation defined revision number */
-#define  SCB_CPUID_PARTNO                    ((uint32_t)0x0000FFF0)        /*!< Number of processor within family */
-#define  SCB_CPUID_Constant                  ((uint32_t)0x000F0000)        /*!< Reads as 0x0F */
-#define  SCB_CPUID_VARIANT                   ((uint32_t)0x00F00000)        /*!< Implementation defined variant number */
-#define  SCB_CPUID_IMPLEMENTER               ((uint32_t)0xFF000000)        /*!< Implementer code. ARM is 0x41 */
-
-/*******************  Bit definition for SCB_ICSR register  *******************/
-#define  SCB_ICSR_VECTACTIVE                 ((uint32_t)0x000001FF)        /*!< Active ISR number field */
-#define  SCB_ICSR_RETTOBASE                  ((uint32_t)0x00000800)        /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
-#define  SCB_ICSR_VECTPENDING                ((uint32_t)0x003FF000)        /*!< Pending ISR number field */
-#define  SCB_ICSR_ISRPENDING                 ((uint32_t)0x00400000)        /*!< Interrupt pending flag */
-#define  SCB_ICSR_ISRPREEMPT                 ((uint32_t)0x00800000)        /*!< It indicates that a pending interrupt becomes active in the next running cycle */
-#define  SCB_ICSR_PENDSTCLR                  ((uint32_t)0x02000000)        /*!< Clear pending SysTick bit */
-#define  SCB_ICSR_PENDSTSET                  ((uint32_t)0x04000000)        /*!< Set pending SysTick bit */
-#define  SCB_ICSR_PENDSVCLR                  ((uint32_t)0x08000000)        /*!< Clear pending pendSV bit */
-#define  SCB_ICSR_PENDSVSET                  ((uint32_t)0x10000000)        /*!< Set pending pendSV bit */
-#define  SCB_ICSR_NMIPENDSET                 ((uint32_t)0x80000000)        /*!< Set pending NMI bit */
-
-/*******************  Bit definition for SCB_VTOR register  *******************/
-#define  SCB_VTOR_TBLOFF                     ((uint32_t)0x1FFFFF80)        /*!< Vector table base offset field */
-#define  SCB_VTOR_TBLBASE                    ((uint32_t)0x20000000)        /*!< Table base in code(0) or RAM(1) */
-
-/*!<*****************  Bit definition for SCB_AIRCR register  *******************/
-#define  SCB_AIRCR_VECTRESET                 ((uint32_t)0x00000001)        /*!< System Reset bit */
-#define  SCB_AIRCR_VECTCLRACTIVE             ((uint32_t)0x00000002)        /*!< Clear active vector bit */
-#define  SCB_AIRCR_SYSRESETREQ               ((uint32_t)0x00000004)        /*!< Requests chip control logic to generate a reset */
-
-#define  SCB_AIRCR_PRIGROUP                  ((uint32_t)0x00000700)        /*!< PRIGROUP[2:0] bits (Priority group) */
-#define  SCB_AIRCR_PRIGROUP_0                ((uint32_t)0x00000100)        /*!< Bit 0 */
-#define  SCB_AIRCR_PRIGROUP_1                ((uint32_t)0x00000200)        /*!< Bit 1 */
-#define  SCB_AIRCR_PRIGROUP_2                ((uint32_t)0x00000400)        /*!< Bit 2  */
-
-/* prority group configuration */
-#define  SCB_AIRCR_PRIGROUP0                 ((uint32_t)0x00000000)        /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
-#define  SCB_AIRCR_PRIGROUP1                 ((uint32_t)0x00000100)        /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP2                 ((uint32_t)0x00000200)        /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP3                 ((uint32_t)0x00000300)        /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP4                 ((uint32_t)0x00000400)        /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP5                 ((uint32_t)0x00000500)        /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP6                 ((uint32_t)0x00000600)        /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
-#define  SCB_AIRCR_PRIGROUP7                 ((uint32_t)0x00000700)        /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
-
-#define  SCB_AIRCR_ENDIANESS                 ((uint32_t)0x00008000)        /*!< Data endianness bit */
-#define  SCB_AIRCR_VECTKEY                   ((uint32_t)0xFFFF0000)        /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
-
-/*******************  Bit definition for SCB_SCR register  ********************/
-#define  SCB_SCR_SLEEPONEXIT                 ((uint32_t)0x00000002)               /*!< Sleep on exit bit */
-#define  SCB_SCR_SLEEPDEEP                   ((uint32_t)0x00000004)               /*!< Sleep deep bit */
-#define  SCB_SCR_SEVONPEND                   ((uint32_t)0x00000010)               /*!< Wake up from WFE */
-
-/********************  Bit definition for SCB_CCR register  *******************/
-#define  SCB_CCR_NONBASETHRDENA              ((uint32_t)0x00000001)            /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
-#define  SCB_CCR_USERSETMPEND                ((uint32_t)0x00000002)            /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
-#define  SCB_CCR_UNALIGN_TRP                 ((uint32_t)0x00000008)            /*!< Trap for unaligned access */
-#define  SCB_CCR_DIV_0_TRP                   ((uint32_t)0x00000010)            /*!< Trap on Divide by 0 */
-#define  SCB_CCR_BFHFNMIGN                   ((uint32_t)0x00000100)            /*!< Handlers running at priority -1 and -2 */
-#define  SCB_CCR_STKALIGN                    ((uint32_t)0x00000200)            /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
-
-/*******************  Bit definition for SCB_SHPR register ********************/
-#define  SCB_SHPR_PRI_N                      ((uint32_t)0x000000FF)        /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
-#define  SCB_SHPR_PRI_N1                     ((uint32_t)0x0000FF00)        /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
-#define  SCB_SHPR_PRI_N2                     ((uint32_t)0x00FF0000)        /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
-#define  SCB_SHPR_PRI_N3                     ((uint32_t)0xFF000000)        /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
-
-/******************  Bit definition for SCB_SHCSR register  *******************/
-#define  SCB_SHCSR_MEMFAULTACT               ((uint32_t)0x00000001)        /*!< MemManage is active */
-#define  SCB_SHCSR_BUSFAULTACT               ((uint32_t)0x00000002)        /*!< BusFault is active */
-#define  SCB_SHCSR_USGFAULTACT               ((uint32_t)0x00000008)        /*!< UsageFault is active */
-#define  SCB_SHCSR_SVCALLACT                 ((uint32_t)0x00000080)        /*!< SVCall is active */
-#define  SCB_SHCSR_MONITORACT                ((uint32_t)0x00000100)        /*!< Monitor is active */
-#define  SCB_SHCSR_PENDSVACT                 ((uint32_t)0x00000400)        /*!< PendSV is active */
-#define  SCB_SHCSR_SYSTICKACT                ((uint32_t)0x00000800)        /*!< SysTick is active */
-#define  SCB_SHCSR_USGFAULTPENDED            ((uint32_t)0x00001000)        /*!< Usage Fault is pended */
-#define  SCB_SHCSR_MEMFAULTPENDED            ((uint32_t)0x00002000)        /*!< MemManage is pended */
-#define  SCB_SHCSR_BUSFAULTPENDED            ((uint32_t)0x00004000)        /*!< Bus Fault is pended */
-#define  SCB_SHCSR_SVCALLPENDED              ((uint32_t)0x00008000)        /*!< SVCall is pended */
-#define  SCB_SHCSR_MEMFAULTENA               ((uint32_t)0x00010000)        /*!< MemManage enable */
-#define  SCB_SHCSR_BUSFAULTENA               ((uint32_t)0x00020000)        /*!< Bus Fault enable */
-#define  SCB_SHCSR_USGFAULTENA               ((uint32_t)0x00040000)        /*!< UsageFault enable */
-
-/*******************  Bit definition for SCB_CFSR register  *******************/
-/*!< MFSR */
-#define  SCB_CFSR_IACCVIOL                   ((uint32_t)0x00000001)        /*!< Instruction access violation */
-#define  SCB_CFSR_DACCVIOL                   ((uint32_t)0x00000002)        /*!< Data access violation */
-#define  SCB_CFSR_MUNSTKERR                  ((uint32_t)0x00000008)        /*!< Unstacking error */
-#define  SCB_CFSR_MSTKERR                    ((uint32_t)0x00000010)        /*!< Stacking error */
-#define  SCB_CFSR_MMARVALID                  ((uint32_t)0x00000080)        /*!< Memory Manage Address Register address valid flag */
-/*!< BFSR */
-#define  SCB_CFSR_IBUSERR                    ((uint32_t)0x00000100)        /*!< Instruction bus error flag */
-#define  SCB_CFSR_PRECISERR                  ((uint32_t)0x00000200)        /*!< Precise data bus error */
-#define  SCB_CFSR_IMPRECISERR                ((uint32_t)0x00000400)        /*!< Imprecise data bus error */
-#define  SCB_CFSR_UNSTKERR                   ((uint32_t)0x00000800)        /*!< Unstacking error */
-#define  SCB_CFSR_STKERR                     ((uint32_t)0x00001000)        /*!< Stacking error */
-#define  SCB_CFSR_BFARVALID                  ((uint32_t)0x00008000)        /*!< Bus Fault Address Register address valid flag */
-/*!< UFSR */
-#define  SCB_CFSR_UNDEFINSTR                 ((uint32_t)0x00010000)        /*!< The processor attempt to excecute an undefined instruction */
-#define  SCB_CFSR_INVSTATE                   ((uint32_t)0x00020000)        /*!< Invalid combination of EPSR and instruction */
-#define  SCB_CFSR_INVPC                      ((uint32_t)0x00040000)        /*!< Attempt to load EXC_RETURN into pc illegally */
-#define  SCB_CFSR_NOCP                       ((uint32_t)0x00080000)        /*!< Attempt to use a coprocessor instruction */
-#define  SCB_CFSR_UNALIGNED                  ((uint32_t)0x01000000)        /*!< Fault occurs when there is an attempt to make an unaligned memory access */
-#define  SCB_CFSR_DIVBYZERO                  ((uint32_t)0x02000000)        /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
-
-/*******************  Bit definition for SCB_HFSR register  *******************/
-#define  SCB_HFSR_VECTTBL                    ((uint32_t)0x00000002)        /*!< Fault occures because of vector table read on exception processing */
-#define  SCB_HFSR_FORCED                     ((uint32_t)0x40000000)        /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
-#define  SCB_HFSR_DEBUGEVT                   ((uint32_t)0x80000000)        /*!< Fault related to debug */
-
-/*******************  Bit definition for SCB_DFSR register  *******************/
-#define  SCB_DFSR_HALTED                     ((uint32_t)0x00000001)               /*!< Halt request flag */
-#define  SCB_DFSR_BKPT                       ((uint32_t)0x00000002)               /*!< BKPT flag */
-#define  SCB_DFSR_DWTTRAP                    ((uint32_t)0x00000004)               /*!< Data Watchpoint and Trace (DWT) flag */
-#define  SCB_DFSR_VCATCH                     ((uint32_t)0x00000008)               /*!< Vector catch flag */
-#define  SCB_DFSR_EXTERNAL                   ((uint32_t)0x00000010)               /*!< External debug request flag */
-
-/*******************  Bit definition for SCB_MMFAR register  ******************/
-#define  SCB_MMFAR_ADDRESS                   ((uint32_t)0xFFFFFFFF)        /*!< Mem Manage fault address field */
-
-/*******************  Bit definition for SCB_BFAR register  *******************/
-#define  SCB_BFAR_ADDRESS                    ((uint32_t)0xFFFFFFFF)        /*!< Bus fault address field */
-
-/*******************  Bit definition for SCB_afsr register  *******************/
-#define  SCB_AFSR_IMPDEF                     ((uint32_t)0xFFFFFFFF)        /*!< Implementation defined */
-/**
-  * @}
-  */
-
- /**
-  * @}
-  */ 
-/** @addtogroup Exported_macro
-  * @{
-  */
-      
-/****************************** ADC Instances *********************************/
-#define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
-
-/******************************** COMP Instances ******************************/
-#define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
-                                        ((INSTANCE) == COMP2))
-
-/****************************** CRC Instances *********************************/
-#define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
-
-/****************************** DAC Instances *********************************/
-#define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
-
-/****************************** DMA Instances *********************************/
-#define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
-                                       ((INSTANCE) == DMA1_Channel2) || \
-                                       ((INSTANCE) == DMA1_Channel3) || \
-                                       ((INSTANCE) == DMA1_Channel4) || \
-                                       ((INSTANCE) == DMA1_Channel5) || \
-                                       ((INSTANCE) == DMA1_Channel6) || \
-                                       ((INSTANCE) == DMA1_Channel7) || \
-                                       ((INSTANCE) == DMA2_Channel1) || \
-                                       ((INSTANCE) == DMA2_Channel2) || \
-                                       ((INSTANCE) == DMA2_Channel3) || \
-                                       ((INSTANCE) == DMA2_Channel4) || \
-                                       ((INSTANCE) == DMA2_Channel5))
-
-/******************************* GPIO Instances *******************************/
-#define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
-                                        ((INSTANCE) == GPIOB) || \
-                                        ((INSTANCE) == GPIOC) || \
-                                        ((INSTANCE) == GPIOD) || \
-                                        ((INSTANCE) == GPIOE) || \
-                                        ((INSTANCE) == GPIOH))
-
-/**************************** GPIO Lock Instances *****************************/
-/* On L1, all GPIO Bank support the Lock mechanism */
-#define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
-
-/******************************** I2C Instances *******************************/
-#define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
-                                       ((INSTANCE) == I2C2))
-
-#define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-/****************************** IWDG Instances ********************************/
-#define IS_IWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == IWDG)
-
-/****************************** OPAMP Instances *******************************/
-#define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
-                                         ((INSTANCE) == OPAMP2))
-                                         
-/****************************** RTC Instances *********************************/
-#define IS_RTC_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == RTC)
-
-/******************************** SPI Instances *******************************/
-#define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
-                                       ((INSTANCE) == SPI2) || \
-                                       ((INSTANCE) == SPI3))
-
-/****************************** TIM Instances *********************************/ 
-#define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                   ((INSTANCE) == TIM3)    || \
-                                   ((INSTANCE) == TIM4)    || \
-                                   ((INSTANCE) == TIM5)    || \
-                                   ((INSTANCE) == TIM6)    || \
-                                   ((INSTANCE) == TIM7)    || \
-                                   ((INSTANCE) == TIM9)    || \
-                                   ((INSTANCE) == TIM10)   || \
-                                   ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9)  || \
-                                       ((INSTANCE) == TIM10) || \
-                                       ((INSTANCE) == TIM11))
-
-#define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5)  || \
-                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                        ((INSTANCE) == TIM3)  || \
-                                                        ((INSTANCE) == TIM4)  || \
-                                                        ((INSTANCE) == TIM5)  || \
-                                                        ((INSTANCE) == TIM9)  || \
-                                                        ((INSTANCE) == TIM10) || \
-                                                        ((INSTANCE) == TIM11))
-
-#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                   ((INSTANCE) == TIM3)  || \
-                                                   ((INSTANCE) == TIM4)  || \
-                                                   ((INSTANCE) == TIM5)  || \
-                                                   ((INSTANCE) == TIM9))
-
-#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                    ((INSTANCE) == TIM3)  || \
-                                                    ((INSTANCE) == TIM4)  || \
-                                                    ((INSTANCE) == TIM5)  || \
-                                                    ((INSTANCE) == TIM9))
-
-#define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                ((INSTANCE) == TIM3)  || \
-                                                ((INSTANCE) == TIM4))
-
-#define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                       ((INSTANCE) == TIM3)  || \
-                                       ((INSTANCE) == TIM4)  || \
-                                       ((INSTANCE) == TIM5))
-
-#define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5)  || \
-                                          ((INSTANCE) == TIM6)  || \
-                                          ((INSTANCE) == TIM7)  || \
-                                          ((INSTANCE) == TIM9))
-
-#define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                         ((INSTANCE) == TIM3)  || \
-                                         ((INSTANCE) == TIM4)  || \
-                                         ((INSTANCE) == TIM5)  || \
-                                         ((INSTANCE) == TIM9))
-
-#define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) ((INSTANCE) == TIM5)
-
-#define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                            ((INSTANCE) == TIM3)  || \
-                                            ((INSTANCE) == TIM4)  || \
-                                            ((INSTANCE) == TIM5))
-
-#define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
-    ((((INSTANCE) == TIM2) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM3) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM4) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM5) &&                   \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2) ||          \
-      ((CHANNEL) == TIM_CHANNEL_3) ||          \
-      ((CHANNEL) == TIM_CHANNEL_4)))           \
-    ||                                         \
-    (((INSTANCE) == TIM9) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1) ||          \
-      ((CHANNEL) == TIM_CHANNEL_2)))           \
-    ||                                         \
-    (((INSTANCE) == TIM10) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1)))           \
-    ||                                         \
-    (((INSTANCE) == TIM11) &&                  \
-     (((CHANNEL) == TIM_CHANNEL_1))))
-
-#define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                  ((INSTANCE) == TIM3)  || \
-                                                  ((INSTANCE) == TIM4)  || \
-                                                  ((INSTANCE) == TIM5)  || \
-                                                  ((INSTANCE) == TIM9)  || \
-                                                  ((INSTANCE) == TIM10) || \
-                                                  ((INSTANCE) == TIM11))
-
-#define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                       ((INSTANCE) == TIM3)    || \
-                                       ((INSTANCE) == TIM4)    || \
-                                       ((INSTANCE) == TIM5)    || \
-                                       ((INSTANCE) == TIM6)    || \
-                                       ((INSTANCE) == TIM7))
-    
-#define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                          ((INSTANCE) == TIM3)  || \
-                                          ((INSTANCE) == TIM4)  || \
-                                          ((INSTANCE) == TIM5))
-
-#define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                                       ((INSTANCE) == TIM3)    || \
-                                                       ((INSTANCE) == TIM4)    || \
-                                                       ((INSTANCE) == TIM5)    || \
-                                                       ((INSTANCE) == TIM9))
-
-#define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)  || \
-                                                     ((INSTANCE) == TIM3)  || \
-                                                     ((INSTANCE) == TIM4)  || \
-                                                     ((INSTANCE) == TIM5)  || \
-                                                     ((INSTANCE) == TIM9))
-
-#define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2)    || \
-                                         ((INSTANCE) == TIM3)    || \
-                                         ((INSTANCE) == TIM9)    || \
-                                         ((INSTANCE) == TIM10)   || \
-                                         ((INSTANCE) == TIM11))
-
-/******************** USART Instances : Synchronous mode **********************/                                           
-#define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                     ((INSTANCE) == USART2) || \
-                                     ((INSTANCE) == USART3))
-
-/******************** UART Instances : Asynchronous mode **********************/
-#define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/******************** UART Instances : Half-Duplex mode **********************/
-#define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                 ((INSTANCE) == USART2) || \
-                                                 ((INSTANCE) == USART3))                                       
-
-/******************** UART Instances : LIN mode **********************/
-#define IS_UART_LIN_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                          ((INSTANCE) == USART2) || \
-                                          ((INSTANCE) == USART3)) 
-
-/****************** UART Instances : Hardware Flow control ********************/                                    
-#define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                           ((INSTANCE) == USART2) || \
-                                           ((INSTANCE) == USART3))
-
-/********************* UART Instances : Smard card mode ***********************/
-#define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                         ((INSTANCE) == USART2) || \
-                                         ((INSTANCE) == USART3))
-
-/*********************** UART Instances : IRDA mode ***************************/
-#define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
-                                    ((INSTANCE) == USART2) || \
-                                    ((INSTANCE) == USART3))
-
-/***************** UART Instances : Multi-Processor mode **********************/
-#define IS_UART_MULTIPROCESSOR_INSTANCE(INSTANCE)   (((INSTANCE) == USART1) || \
-                                                     ((INSTANCE) == USART2) || \
-                                                     ((INSTANCE) == USART3)) 
-
-/****************************** WWDG Instances ********************************/
-#define IS_WWDG_ALL_INSTANCE(INSTANCE)  ((INSTANCE) == WWDG)
-
-/****************************** USB Instances ********************************/
-#define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
-
-/**
-  * @}
-  */
-
-/******************************************************************************/
-/*  For a painless codes migration between the STM32L1xx device product       */
-/*  lines, the aliases defined below are put in place to overcome the         */
-/*  differences in the interrupt handlers and IRQn definitions.               */
-/*  No need to update developed interrupt code when moving across             */ 
-/*  product lines within the same STM32L1 Family                              */
-/******************************************************************************/
-
-/* Aliases for __IRQn */
-
-/* Aliases for __IRQHandler */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L151xC_H */
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l1xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,261 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS STM32L1xx Device Peripheral Access Layer Header File. 
-  *
-  *          The file is the unique include file that the application programmer
-  *          is using in the C source code, usually in main.c. This file contains:
-  *            - Configuration section that allows to select:
-  *              - The STM32L1xx device used in the target application
-  *              - To use or not the peripheral’s drivers in application code(i.e. 
-  *                code will be based on direct access to peripheral’s registers 
-  *                rather than drivers API), this option is controlled by 
-  *                "#define USE_HAL_DRIVER"
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx
-  * @{
-  */
-    
-#ifndef __STM32L1XX_H
-#define __STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif /* __cplusplus */
-  
-/** @addtogroup Library_configuration_section
-  * @{
-  */
-
-
-//MODTRONIX BEGIN - HAL Defines ///////////////////////////////////////////////
-//Provide place for adding HAL defines. Alternative to adding them in IDE project properties.
-//Add project defines here, or add them to your toolchain compiler preprocessor
-
-//Defines what ports to use for default serial port.
-//0 = B10/B11
-//1 = A2/A3
-#if !defined  (MX_DEFAULT_SERIAL_PINS)
-#define MX_DEFAULT_SERIAL_PINS   0          /*!< Use B10/B11 for default serial port, in stead of A2/A3 */
-#endif
-
-//MODTRONIX END ///////////////////////////////////////////////////////////////
-
-/* Uncomment the line below according to the target STM32L device used in your 
-   application 
-  */
-
-#if !defined (STM32L100xB) && !defined (STM32L100xBA) && !defined (STM32L100xC) && \
-    !defined (STM32L151xB) && !defined (STM32L151xBA) && !defined (STM32L151xC) && !defined (STM32L151xCA) && !defined (STM32L151xD) && !defined (STM32L151xE) && \
-    !defined (STM32L152xB) && !defined (STM32L152xBA) && !defined (STM32L152xC) && !defined (STM32L152xCA) && !defined (STM32L152xD) && !defined (STM32L152xE) && \
-    !defined (STM32L162xC) && !defined (STM32L162xCA) && !defined (STM32L162xD) && !defined (STM32L162xE)
-  /* #define STM32L100xB  */   /*!< STM32L100C6, STM32L100R and STM32L100RB Devices */
-  /* #define STM32L100xBA */   /*!< STM32L100C6-A, STM32L100R8-A and STM32L100RB-A Devices */
-  /* #define STM32L100xC  */   /*!< STM32L100RC Devices */
-  /* #define STM32L151xB  */   /*!< STM32L151C6, STM32L151R6, STM32L151C8, STM32L151R8, STM32L151V8, STM32L151CB, STM32L151RB and STM32L151VB */
-  /* #define STM32L151xBA */   /*!< STM32L151C6-A, STM32L151R6-A, STM32L151C8-A, STM32L151R8-A, STM32L151V8-A, STM32L151CB-A, STM32L151RB-A and STM32L151VB-A */ 
-  #define STM32L151xC          /*!< STM32L151CC, STM32L151UC, STM32L151RC and STM32L151VC */
-  /* #define STM32L151xCA */   /*!< STM32L151RC-A, STM32L151VC-A, STM32L151QC and STM32L151ZC */
-  /* #define STM32L151xD  */   /*!< STM32L151QD, STM32L151RD, STM32L151VD & STM32L151ZD */
-  /* #define STM32L151xE  */   /*!< STM32L151QE, STM32L151RE, STM32L151VE and STM32L151ZE */
-  /* #define STM32L152xB  */   /*!< STM32L152C6, STM32L152R6, STM32L152C8, STM32L152R8, STM32L152V8, STM32L152CB, STM32L152RB and STM32L152VB */
-  /* #define STM32L152xBA */   /*!< STM32L152C6-A, STM32L152R6-A, STM32L152C8-A, STM32L152R8-A, STM32L152V8-A, STM32L152CB-A, STM32L152RB-A and STM32L152VB-A */
-  /* #define STM32L152xC  */   /*!< STM32L152CC, STM32L152UC, STM32L152RC and STM32L152VC */
-  /* #define STM32L152xCA */   /*!< STM32L152RC-A, STM32L152VC-A, STM32L152QC and STM32L152ZC */
-  /* #define STM32L152xD  */   /*!< STM32L152QD, STM32L152RD, STM32L152VD and STM32L152ZD */  
-  /* #define STM32L152xE  */   /*!< STM32L152QE, STM32L152RE, STM32L152VE and STM32L152ZE */
-  /* #define STM32L162xC  */   /*!< STM32L162RC and STM32L162VC */
-  /* #define STM32L162xCA */   /*!< STM32L162RC-A, STM32L162VC-A, STM32L162QC and STM32L162ZC */
-  /* #define STM32L162xD  */   /*!< STM32L162QD, STM32L162RD, STM32L162VD and STM32L162ZD */
-  /* #define STM32L162xE  */   /*!< STM32L162RE, STM32L162VE and STM32L162ZE */
-#endif
-
-/*  Tip: To avoid modifying this file each time you need to switch between these
-        devices, you can define the device in your toolchain compiler preprocessor.
-  */
-  
-#if !defined  (USE_HAL_DRIVER)
-/**
- * @brief Comment the line below if you will not use the peripherals drivers.
-   In this case, these drivers will not be included and the application code will 
-   be based on direct access to peripherals registers 
-   */
-#define USE_HAL_DRIVER
-#endif /* USE_HAL_DRIVER */
-
-/**
-  * @brief CMSIS Device version number V2.0.0
-  */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_MAIN   (0x02) /*!< [31:24] main version */                                  
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L1xx_CMSIS_DEVICE_VERSION_RC     (0x00) /*!< [7:0]  release candidate */ 
-#define __STM32L1xx_CMSIS_DEVICE_VERSION        ((__CMSIS_DEVICE_VERSION_MAIN     << 24)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB1 << 16)\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_SUB2 << 8 )\
-                                      |(__CMSIS_DEVICE_HAL_VERSION_RC))
-
-/**
-  * @}
-  */
-
-/** @addtogroup Device_Included
-  * @{
-  */
-
-#if defined(STM32L100xB)
-  #include "stm32l100xb.h"
-#elif defined(STM32L100xBA)
-  #include "stm32l100xba.h"
-#elif defined(STM32L100xC)
-  #include "stm32l100xc.h"
-#elif defined(STM32L151xB)
-  #include "stm32l151xb.h"
-#elif defined(STM32L151xBA)
-  #include "stm32l151xba.h"
-#elif defined(STM32L151xC)
-  #include "stm32l151xc.h"
-#elif defined(STM32L151xCA)
-  #include "stm32l151xca.h"
-#elif defined(STM32L151xD)
-  #include "stm32l151xd.h"
-#elif defined(STM32L151xE)
-  #include "stm32l151xe.h"
-#elif defined(STM32L152xB)
-  #include "stm32l152xb.h"
-#elif defined(STM32L152xBA)
-  #include "stm32l152xba.h"
-#elif defined(STM32L152xC)
-  #include "stm32l152xc.h"
-#elif defined(STM32L152xCA)
-  #include "stm32l152xca.h"
-#elif defined(STM32L152xD)
-  #include "stm32l152xd.h"
-#elif defined(STM32L152xE)
-  #include "stm32l152xe.h"
-#elif defined(STM32L162xC)
-  #include "stm32l162xc.h"
-#elif defined(STM32L162xCA)
-  #include "stm32l162xca.h"
-#elif defined(STM32L162xD)
-  #include "stm32l162xd.h"
-#elif defined(STM32L162xE)
-  #include "stm32l162xe.h"
-#else
- #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
-#endif
-
-/**
-  * @}
-  */
-
-/** @addtogroup Exported_types
-  * @{
-  */  
-typedef enum 
-{
-  RESET = 0, 
-  SET = !RESET
-} FlagStatus, ITStatus;
-
-typedef enum 
-{
-  DISABLE = 0, 
-  ENABLE = !DISABLE
-} FunctionalState;
-#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-
-typedef enum 
-{
-  ERROR = 0, 
-  SUCCESS = !ERROR
-} ErrorStatus;
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup Exported_macros
-  * @{
-  */
-#define SET_BIT(REG, BIT)     ((REG) |= (BIT))
-
-#define CLEAR_BIT(REG, BIT)   ((REG) &= ~(BIT))
-
-#define READ_BIT(REG, BIT)    ((REG) & (BIT))
-
-#define CLEAR_REG(REG)        ((REG) = (0x0))
-
-#define WRITE_REG(REG, VAL)   ((REG) = (VAL))
-
-#define READ_REG(REG)         ((REG))
-
-#define MODIFY_REG(REG, CLEARMASK, SETMASK)  WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-
-#define POSITION_VAL(VAL)     (__CLZ(__RBIT(VAL))) 
-
-
-/**
-  * @}
-  */
-
-#if defined (USE_HAL_DRIVER)
- #include "stm32l1xx_hal.h"
-#endif /* USE_HAL_DRIVER */
-
-
-#ifdef __cplusplus
-}
-#endif /* __cplusplus */
-
-#endif /* __STM32L1xx_H */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/stm32l1xx_hal_conf.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,291 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_conf_template.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   HAL configuration template file. 
-  *          This file should be copied to the application folder and renamed
-  *          to stm32l1xx_hal_conf.h.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CONF_H
-#define __STM32L1xx_HAL_CONF_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/* ########################## Module Selection ############################## */
-/**
-  * @brief This is the list of modules to be used in the HAL driver 
-  */
-#define HAL_MODULE_ENABLED  
-#define HAL_ADC_MODULE_ENABLED
-#define HAL_COMP_MODULE_ENABLED
-#define HAL_CORTEX_MODULE_ENABLED
-#define HAL_CRC_MODULE_ENABLED
-#define HAL_CRYP_MODULE_ENABLED
-#define HAL_DAC_MODULE_ENABLED
-#define HAL_DMA_MODULE_ENABLED
-#define HAL_FLASH_MODULE_ENABLED
-#define HAL_GPIO_MODULE_ENABLED
-#define HAL_I2C_MODULE_ENABLED
-#define HAL_I2S_MODULE_ENABLED
-#define HAL_IRDA_MODULE_ENABLED
-#define HAL_IWDG_MODULE_ENABLED
-#define HAL_LCD_MODULE_ENABLED
-#define HAL_NOR_MODULE_ENABLED
-#define HAL_OPAMP_MODULE_ENABLED
-#define HAL_PCD_MODULE_ENABLED
-#define HAL_PWR_MODULE_ENABLED
-#define HAL_RCC_MODULE_ENABLED
-#define HAL_RTC_MODULE_ENABLED
-#define HAL_SD_MODULE_ENABLED
-#define HAL_SMARTCARD_MODULE_ENABLED
-#define HAL_SPI_MODULE_ENABLED
-#define HAL_SRAM_MODULE_ENABLED
-#define HAL_TIM_MODULE_ENABLED
-#define HAL_UART_MODULE_ENABLED
-#define HAL_USART_MODULE_ENABLED
-#define HAL_WWDG_MODULE_ENABLED
-
-/* ########################## Oscillator Values adaptation ####################*/
-/**
-  * @brief Adjust the value of External High Speed oscillator (HSE) used in your application.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSE is used as system clock source, directly or through the PLL).  
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)16000000) /*!< NZ32-SC151 has a 16MHz External crystal */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSE_STARTUP_TIMEOUT)
-  #define HSE_STARTUP_TIMEOUT    ((uint32_t)500)   /*!< Time out for HSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-/**
-  * @brief Internal Multiple Speed oscillator (MSI) default value.
-  *        This value is the default MSI range value after Reset.
-  */
-#if !defined  (MSI_VALUE)
-  #define MSI_VALUE    ((uint32_t)2097000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* MSI_VALUE */
-/**
-  * @brief Internal High Speed oscillator (HSI) value.
-  *        This value is used by the RCC HAL module to compute the system frequency
-  *        (when HSI is used as system clock source, directly or through the PLL). 
-  */
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
-#endif /* HSI_VALUE */
-
-/**
-  * @brief External Low Speed oscillator (LSE) value.
-  *        This value is used by the UART, RTC HAL module to compute the system frequency
-  */
-#if !defined  (LSE_VALUE)
-  #define LSE_VALUE    ((uint32_t)32768) /*!< Value of the External oscillator in Hz*/
-#endif /* LSE_VALUE */
-
-   
-#if !defined  (LSE_STARTUP_TIMEOUT)
-  #define LSE_STARTUP_TIMEOUT    ((uint32_t)5000)   /*!< Time out for LSE start up, in ms */
-#endif /* HSE_STARTUP_TIMEOUT */
-
-   
-/* Tip: To avoid modifying this file each time you need to use different HSE,
-   ===  you can define the HSE value in your toolchain compiler preprocessor. */
-
-/* ########################### System Configuration ######################### */
-/**
-  * @brief This is the HAL system configuration section
-  */     
-#define  VDD_VALUE                    ((uint32_t)3300) /*!< Value of VDD in mv */          
-#define  TICK_INT_PRIORITY            ((uint32_t)0x000F)    /*!< tick interrupt priority */            
-#define  USE_RTOS                     0     
-#define  PREFETCH_ENABLE              1
-#define  INSTRUCTION_CACHE_ENABLE     0
-#define  DATA_CACHE_ENABLE            0
-
-/* ########################## Assert Selection ############################## */
-/**
-  * @brief Uncomment the line below to expanse the "assert_param" macro in the 
-  *        HAL drivers code
-  */
-/*#define USE_FULL_ASSERT    1*/ 
-
-/* Includes ------------------------------------------------------------------*/
-/**
-  * @brief Include module's header file 
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
- #include "stm32l1xx_hal_rcc.h"
-#endif /* HAL_RCC_MODULE_ENABLED */
-  
-#ifdef HAL_GPIO_MODULE_ENABLED
- #include "stm32l1xx_hal_gpio.h"
-#endif /* HAL_GPIO_MODULE_ENABLED */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-  #include "stm32l1xx_hal_dma.h"
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
- #include "stm32l1xx_hal_cortex.h"
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-
-#ifdef HAL_ADC_MODULE_ENABLED
- #include "stm32l1xx_hal_adc.h"
-#endif /* HAL_ADC_MODULE_ENABLED */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-  #include "stm32l1xx_hal_comp.h"
-#endif /* HAL_COMP_MODULE_ENABLED */
-
-#ifdef HAL_CRC_MODULE_ENABLED
- #include "stm32l1xx_hal_crc.h"
-#endif /* HAL_CRC_MODULE_ENABLED */
-
-#ifdef HAL_CRYP_MODULE_ENABLED
- #include "stm32l1xx_hal_cryp.h"
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-#ifdef HAL_DAC_MODULE_ENABLED
- #include "stm32l1xx_hal_dac.h"
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
- #include "stm32l1xx_hal_flash.h"
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-#ifdef HAL_SRAM_MODULE_ENABLED
- #include "stm32l1xx_hal_sram.h"
-#endif /* HAL_SRAM_MODULE_ENABLED */
-
-#ifdef HAL_NOR_MODULE_ENABLED
- #include "stm32l1xx_hal_nor.h"
-#endif /* HAL_NOR_MODULE_ENABLED */ 
-
-#ifdef HAL_I2C_MODULE_ENABLED
- #include "stm32l1xx_hal_i2c.h"
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-#ifdef HAL_I2S_MODULE_ENABLED
- #include "stm32l1xx_hal_i2s.h"
-#endif /* HAL_I2S_MODULE_ENABLED */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
- #include "stm32l1xx_hal_iwdg.h"
-#endif /* HAL_IWDG_MODULE_ENABLED */
-
-#ifdef HAL_LCD_MODULE_ENABLED
- #include "stm32l1xx_hal_lcd.h"
-#endif /* HAL_LCD_MODULE_ENABLED */
-   
-#ifdef HAL_OPAMP_MODULE_ENABLED
- #include "stm32l1xx_hal_opamp.h"
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-
-#ifdef HAL_PWR_MODULE_ENABLED
- #include "stm32l1xx_hal_pwr.h"
-#endif /* HAL_PWR_MODULE_ENABLED */
-
-#ifdef HAL_RTC_MODULE_ENABLED
- #include "stm32l1xx_hal_rtc.h"
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-#ifdef HAL_SD_MODULE_ENABLED
- #include "stm32l1xx_hal_sd.h"
-#endif /* HAL_SD_MODULE_ENABLED */     
-
-#ifdef HAL_SPI_MODULE_ENABLED
- #include "stm32l1xx_hal_spi.h"
-#endif /* HAL_SPI_MODULE_ENABLED */
-
-#ifdef HAL_TIM_MODULE_ENABLED
- #include "stm32l1xx_hal_tim.h"
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-#ifdef HAL_UART_MODULE_ENABLED
- #include "stm32l1xx_hal_uart.h"
-#endif /* HAL_UART_MODULE_ENABLED */
-
-#ifdef HAL_USART_MODULE_ENABLED
- #include "stm32l1xx_hal_usart.h"
-#endif /* HAL_USART_MODULE_ENABLED */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
- #include "stm32l1xx_hal_irda.h"
-#endif /* HAL_IRDA_MODULE_ENABLED */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
- #include "stm32l1xx_hal_smartcard.h"
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
- #include "stm32l1xx_hal_wwdg.h"
-#endif /* HAL_WWDG_MODULE_ENABLED */
-
-#ifdef HAL_PCD_MODULE_ENABLED
- #include "stm32l1xx_hal_pcd.h"
-#endif /* HAL_PCD_MODULE_ENABLED */
-   
-/* Exported macro ------------------------------------------------------------*/
-#ifdef  USE_FULL_ASSERT
-/**
-  * @brief  The assert_param macro is used for function's parameters check.
-  * @param  expr: If expr is false, it calls assert_failed function
-  *         which reports the name of the source file and the source
-  *         line number of the call that failed. 
-  *         If expr is true, it returns no value.
-  * @retval None
-  */
-  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
-/* Exported functions ------------------------------------------------------- */
-  void assert_failed(uint8_t* file, uint32_t line);
-#else
-  #define assert_param(expr) ((void)0)
-#endif /* USE_FULL_ASSERT */   
-   
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CONF_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,605 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.c
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
-  *
-  *   This file provides two functions and one global variable to be called from 
-  *   user application:
-  *      - SystemInit(): This function is called at startup just after reset and 
-  *                      before branch to main program. This call is made inside
-  *                      the "startup_stm32l1xx.s" file.
-  *
-  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
-  *                                  by the user application to setup the SysTick 
-  *                                  timer or configure other parameters.
-  *                                     
-  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
-  *                                 be called whenever the core clock is changed
-  *                                 during program execution.
-  *
-  * This file configures the system clock as follows:
-  *-----------------------------------------------------------------------------
-  * System clock source                | 1- PLL_HSE_EXTC         | 3- PLL_HSI
-  *                                    | (external 16 MHz clock) | (internal 16 MHz)
-  *                                    | 2- PLL_HSE_XTAL         |
-  *                                    | (external 16 MHz xtal)  |
-  *-----------------------------------------------------------------------------
-  * SYSCLK(MHz)                        | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * AHBCLK (MHz)                       | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB1CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * APB2CLK (MHz)                      | 32                     | 32
-  *-----------------------------------------------------------------------------
-  * USB capable (48 MHz precise clock) | YES                    | NO
-  *-----------------------------------------------------------------------------
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/** @addtogroup STM32L1xx_System_Private_Includes
-  * @{
-  */
-
-#include "stm32l1xx.h"
-#include "hal_tick.h"
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_TypesDefinitions
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Defines
-  * @{
-  */
-#if !defined  (HSE_VALUE) 
-  #define HSE_VALUE    ((uint32_t)16000000) /*!< Default value of the External oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSE_VALUE */
-
-#if !defined  (HSI_VALUE)
-  #define HSI_VALUE    ((uint32_t)16000000) /*!< Default value of the Internal oscillator in Hz.
-                                                This value can be provided and adapted by the user application. */
-#endif /* HSI_VALUE */
-
-/*!< Uncomment the following line if you need to use external SRAM mounted
-     on STM32L152D_EVAL board as data memory  */
-/* #define DATA_IN_ExtSRAM */
-  
-/*!< Uncomment the following line if you need to relocate your vector Table in
-     Internal SRAM. */ 
-/* #define VECT_TAB_SRAM */
-#define VECT_TAB_OFFSET  0x0 /*!< Vector Table base offset field. 
-                                  This value must be a multiple of 0x200. */
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Macros
-  * @{
-  */
-
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (0) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Variables
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetHCLKFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
-const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-  static void SystemInit_ExtMemCtl(void); 
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
-
-uint8_t SetSysClock_PLL_HSI(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  Setup the microcontroller system.
-  *         Initialize the Embedded Flash Interface, the PLL and update the 
-  *         SystemCoreClock variable.
-  * @param  None
-  * @retval None
-  */
-void SystemInit (void)
-{
-  /*!< Set MSION bit */
-  RCC->CR |= (uint32_t)0x00000100;
-
-  /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
-  RCC->CFGR &= (uint32_t)0x88FFC00C;
-  
-  /*!< Reset HSION, HSEON, CSSON and PLLON bits */
-  RCC->CR &= (uint32_t)0xEEFEFFFE;
-
-  /*!< Reset HSEBYP bit */
-  RCC->CR &= (uint32_t)0xFFFBFFFF;
-
-  /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
-  RCC->CFGR &= (uint32_t)0xFF02FFFF;
-
-  /*!< Disable all interrupts */
-  RCC->CIR = 0x00000000;
-
-#ifdef DATA_IN_ExtSRAM
-  SystemInit_ExtMemCtl(); 
-#endif /* DATA_IN_ExtSRAM */
-    
-#ifdef VECT_TAB_SRAM
-  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
-#else
-  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
-#endif
-
-  /* Configure the Cube driver */
-  SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
-  HAL_Init();
-
-  /* Configure the System clock source, PLL Multiplier and Divider factors,
-     AHB/APBx prescalers and Flash settings */
-  SetSysClock();
-  
-  /* Reset the timer to avoid issues after the RAM initialization */
-  TIM_MST_RESET_ON;
-  TIM_MST_RESET_OFF;
-}
-
-/**
-  * @brief  Update SystemCoreClock according to Clock Register Values
-  *         The SystemCoreClock variable contains the core clock (HCLK), it can
-  *         be used by the user application to setup the SysTick timer or configure
-  *         other parameters.
-  *           
-  * @note   Each time the core clock (HCLK) changes, this function must be called
-  *         to update SystemCoreClock variable value. Otherwise, any configuration
-  *         based on this variable will be incorrect.         
-  *     
-  * @note   - The system frequency computed by this function is not the real 
-  *           frequency in the chip. It is calculated based on the predefined 
-  *           constant and the selected clock source:
-  *             
-  *           - If SYSCLK source is MSI, SystemCoreClock will contain the MSI 
-  *             value as defined by the MSI range.
-  *                                   
-  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
-  *                                              
-  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
-  *                          
-  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
-  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
-  *         
-  *         (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
-  *             16 MHz) but the real value may vary depending on the variations
-  *             in voltage and temperature.   
-  *    
-  *         (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
-  *              8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *              frequency of the crystal used. Otherwise, this function may
-  *              have wrong result.
-  *                
-  *         - The result of this function could be not correct when using fractional
-  *           value for HSE crystal.
-  * @param  None
-  * @retval None
-  */
-void SystemCoreClockUpdate (void)
-{
-  uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
-
-  /* Get SYSCLK source -------------------------------------------------------*/
-  tmp = RCC->CFGR & RCC_CFGR_SWS;
-  
-  switch (tmp)
-  {
-    case 0x00:  /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-    case 0x04:  /* HSI used as system clock */
-      SystemCoreClock = HSI_VALUE;
-      break;
-    case 0x08:  /* HSE used as system clock */
-      SystemCoreClock = HSE_VALUE;
-      break;
-    case 0x0C:  /* PLL used as system clock */
-      /* Get PLL clock source and multiplication factor ----------------------*/
-      pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
-      plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
-      pllmul = PLLMulTable[(pllmul >> 18)];
-      plldiv = (plldiv >> 22) + 1;
-      
-      pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
-
-      if (pllsource == 0x00)
-      {
-        /* HSI oscillator clock selected as PLL clock entry */
-        SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
-      }
-      else
-      {
-        /* HSE selected as PLL clock entry */
-        SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
-      }
-      break;
-    default: /* MSI used as system clock */
-      msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
-      SystemCoreClock = (32768 * (1 << (msirange + 1)));
-      break;
-  }
-  /* Compute HCLK clock frequency --------------------------------------------*/
-  /* Get HCLK prescaler */
-  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
-  /* HCLK clock frequency */
-  SystemCoreClock >>= tmp;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#ifdef DATA_IN_ExtSRAM
-/**
-  * @brief  Setup the external memory controller.
-  *         Called in SystemInit() function before jump to main.
-  *         This function configures the external SRAM mounted on STM32L152D_EVAL board
-  *         This SRAM will be used as program data memory (including heap and stack).
-  * @param  None
-  * @retval None
-  */
-void SystemInit_ExtMemCtl(void)
-{
-/*-- GPIOs Configuration -----------------------------------------------------*/
-/*
- +-------------------+--------------------+------------------+------------------+
- +                       SRAM pins assignment                                   +
- +-------------------+--------------------+------------------+------------------+
- | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 |
- | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 |
- | PD4  <-> FSMC_NOE | PE7  <-> FSMC_D4   | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 |
- | PD5  <-> FSMC_NWE | PE8  <-> FSMC_D5   | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 |
- | PD8  <-> FSMC_D13 | PE9  <-> FSMC_D6   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 |
- | PD9  <-> FSMC_D14 | PE10 <-> FSMC_D7   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 |
- | PD10 <-> FSMC_D15 | PE11 <-> FSMC_D8   | PF12 <-> FSMC_A6 | PG10<-> FSMC_NE2 |
- | PD11 <-> FSMC_A16 | PE12 <-> FSMC_D9   | PF13 <-> FSMC_A7 |------------------+
- | PD12 <-> FSMC_A17 | PE13 <-> FSMC_D10  | PF14 <-> FSMC_A8 | 
- | PD13 <-> FSMC_A18 | PE14 <-> FSMC_D11  | PF15 <-> FSMC_A9 | 
- | PD14 <-> FSMC_D0  | PE15 <-> FSMC_D12  |------------------+
- | PD15 <-> FSMC_D1  |--------------------+ 
- +-------------------+
-*/
-
-  /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
-  RCC->AHBENR   = 0x000080D8;
-  
-  /* Connect PDx pins to FSMC Alternate function */
-  GPIOD->AFR[0]  = 0x00CC00CC;
-  GPIOD->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PDx pins in Alternate function mode */  
-  GPIOD->MODER   = 0xAAAA0A0A;
-  /* Configure PDx pins speed to 40 MHz */  
-  GPIOD->OSPEEDR = 0xFFFF0F0F;
-  /* Configure PDx pins Output type to push-pull */  
-  GPIOD->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PDx pins */ 
-  GPIOD->PUPDR   = 0x00000000;
-
-  /* Connect PEx pins to FSMC Alternate function */
-  GPIOE->AFR[0]  = 0xC00000CC;
-  GPIOE->AFR[1]  = 0xCCCCCCCC;
-  /* Configure PEx pins in Alternate function mode */ 
-  GPIOE->MODER   = 0xAAAA800A;
-  /* Configure PEx pins speed to 40 MHz */ 
-  GPIOE->OSPEEDR = 0xFFFFC00F;
-  /* Configure PEx pins Output type to push-pull */  
-  GPIOE->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PEx pins */ 
-  GPIOE->PUPDR   = 0x00000000;
-
-  /* Connect PFx pins to FSMC Alternate function */
-  GPIOF->AFR[0]  = 0x00CCCCCC;
-  GPIOF->AFR[1]  = 0xCCCC0000;
-  /* Configure PFx pins in Alternate function mode */   
-  GPIOF->MODER   = 0xAA000AAA;
-  /* Configure PFx pins speed to 40 MHz */ 
-  GPIOF->OSPEEDR = 0xFF000FFF;
-  /* Configure PFx pins Output type to push-pull */  
-  GPIOF->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PFx pins */ 
-  GPIOF->PUPDR   = 0x00000000;
-
-  /* Connect PGx pins to FSMC Alternate function */
-  GPIOG->AFR[0]  = 0x00CCCCCC;
-  GPIOG->AFR[1]  = 0x00000C00;
-  /* Configure PGx pins in Alternate function mode */ 
-  GPIOG->MODER   = 0x00200AAA;
-  /* Configure PGx pins speed to 40 MHz */ 
-  GPIOG->OSPEEDR = 0x00300FFF;
-  /* Configure PGx pins Output type to push-pull */  
-  GPIOG->OTYPER  = 0x00000000;
-  /* No pull-up, pull-down for PGx pins */ 
-  GPIOG->PUPDR   = 0x00000000;
-  
-/*-- FSMC Configuration ------------------------------------------------------*/
-  /* Enable the FSMC interface clock */
-  RCC->AHBENR    = 0x400080D8;
-
-  /* Configure and enable Bank1_SRAM3 */
-  FSMC_Bank1->BTCR[4]  = 0x00001011;
-  FSMC_Bank1->BTCR[5]  = 0x00000300;
-  FSMC_Bank1E->BWTR[4] = 0x0FFFFFFF;
-/*
-  Bank1_SRAM3 is configured as follow:
-
-  p.FSMC_AddressSetupTime = 0;
-  p.FSMC_AddressHoldTime = 0;
-  p.FSMC_DataSetupTime = 3;
-  p.FSMC_BusTurnAroundDuration = 0;
-  p.FSMC_CLKDivision = 0;
-  p.FSMC_DataLatency = 0;
-  p.FSMC_AccessMode = FSMC_AccessMode_A;
-
-  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM3;
-  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
-  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
-  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
-  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
-  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
-  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
-  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
-  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
-
-  FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
-
-  FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM3, ENABLE);
-*/
-  
-}
-#endif /* DATA_IN_ExtSRAM */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
-  *               AHB/APBx prescalers and Flash settings
-  * @note   This function should be called only once the RCC clock configuration  
-  *         is reset to the default reset state (done in SystemInit() function).             
-  * @param  None
-  * @retval None
-  */
-void SetSysClock(void)
-{
-  /* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
-  if (SetSysClock_PLL_HSE(1) == 0)
-#endif
-  {
-    /* 2- If fail try to start with HSE and external xtal */
-    #if USE_PLL_HSE_XTAL != 0
-    if (SetSysClock_PLL_HSE(0) == 0)
-    #endif
-    {
-      /* 3- If fail start with HSI clock */
-      if (SetSysClock_PLL_HSI() == 0)
-      {
-        while(1)
-        {
-          // [TODO] Put something here to tell the user that a problem occured...
-        }
-      }
-    }
-  }
-  
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1);
-}
-
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* Used to gain time after DeepSleep in case HSI is used */
-  if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-  {
-    return 0;
-  }
-  
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
-  if (bypass == 0)
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_ON; /* External 16 MHz xtal on OSC_IN/OSC_OUT */
-  }
-  else
-  {
-    RCC_OscInitStruct.HSEState          = RCC_HSE_BYPASS; /* External 16 MHz clock on OSC_IN */
-  }
-  RCC_OscInitStruct.HSIState            = RCC_HSI_OFF;
-  // SYSCLK = 32 MHz ((16 MHz * 6) / 3)
-  // USBCLK = 48 MHz ((16 MHz * 6) / 2) --> USB OK
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSE;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL6;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV3;
-
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
- 
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //if (bypass == 0)
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
-  //else
-    //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
-  
-  return 1; // OK
-}
-#endif
-
-/******************************************************************************/
-/*            PLL (clocked by HSI) used as System clock source                */
-/******************************************************************************/
-uint8_t SetSysClock_PLL_HSI(void)
-{
-  RCC_ClkInitTypeDef RCC_ClkInitStruct;
-  RCC_OscInitTypeDef RCC_OscInitStruct;
-
-  /* The voltage scaling allows optimizing the power consumption when the device is 
-     clocked below the maximum system frequency, to update the voltage scaling value 
-     regarding system frequency refer to product datasheet. */
-  __PWR_CLK_ENABLE();
-  __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1);
-  
-  /* Enable HSI oscillator and activate PLL with HSI as source */
-  RCC_OscInitStruct.OscillatorType      = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
-  RCC_OscInitStruct.HSEState            = RCC_HSE_OFF;
-  RCC_OscInitStruct.HSIState            = RCC_HSI_ON;
-  // SYSCLK = 32 MHz ((16 MHz * 4) / 2)
-  // USBCLK = 64 MHz (16 MHz * 4) --> USB not possible
-  RCC_OscInitStruct.PLL.PLLState        = RCC_PLL_ON;
-  RCC_OscInitStruct.PLL.PLLSource       = RCC_PLLSOURCE_HSI;
-  RCC_OscInitStruct.PLL.PLLMUL          = RCC_PLL_MUL4;
-  RCC_OscInitStruct.PLL.PLLDIV          = RCC_PLL_DIV2;
-  if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-  
-  /* Poll VOSF bit of in PWR_CSR. Wait until it is reset to 0 */
-  while (__HAL_PWR_GET_FLAG(PWR_FLAG_VOS) != RESET) {};
-
-  /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
-  RCC_ClkInitStruct.ClockType      = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
-  RCC_ClkInitStruct.SYSCLKSource   = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz
-  RCC_ClkInitStruct.AHBCLKDivider  = RCC_SYSCLK_DIV1;         // 32 MHz
-  RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1;           // 32 MHz
-  if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK)
-  {
-    return 0; // FAIL
-  }
-
-  /* Output clock on MCO1 pin(PA8) for debugging purpose */
-  //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
-  
-  return 1; // OK
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/system_stm32l1xx.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    system_stm32l1xx.h
-  * @author  MCD Application Team
-  * @version V2.0.0
-  * @date    5-September-2014
-  * @brief   CMSIS Cortex-M3 Device System Source File for STM32L1xx devices.  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/** @addtogroup CMSIS
-  * @{
-  */
-
-/** @addtogroup stm32l1xx_system
-  * @{
-  */  
-  
-/**
-  * @brief Define to prevent recursive inclusion
-  */
-#ifndef __SYSTEM_STM32L1XX_H
-#define __SYSTEM_STM32L1XX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif 
-
-/** @addtogroup STM32L1xx_System_Includes
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup STM32L1xx_System_Exported_types
-  * @{
-  */
-  /* This variable is updated in three ways:
-      1) by calling CMSIS function SystemCoreClockUpdate()
-      2) by calling HAL API function HAL_RCC_GetSysClockFreq()
-      3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency 
-         Note: If you use this function to configure the system clock; then there
-               is no need to call the 2 first functions listed above, since SystemCoreClock
-               variable is updated automatically.
-  */
-extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Constants
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Macros
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup STM32L1xx_System_Exported_Functions
-  * @{
-  */
-  
-extern void SystemInit(void);
-extern void SystemCoreClockUpdate(void);
-extern void SetSysClock(void);
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__SYSTEM_STM32L1XX_H */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */  
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,454 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   HAL module driver.
-  *          This is the common part of the HAL initialization
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-    The common HAL driver contains a set of generic and common APIs that can be
-    used by the PPP peripheral drivers and the user to start using the HAL. 
-    [..]
-    The HAL contains two APIs' categories: 
-         (+) Common HAL APIs
-         (+) Services HAL APIs
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup HAL HAL
-  * @brief HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup HAL_Private_Defines HAL Private Defines
-  * @{
-  */
-
-/**
- * @brief STM32L1xx HAL Driver version number V1.0.0
-   */
-#define __STM32L1xx_HAL_VERSION_MAIN   (0x01) /*!< [31:24] main version */
-#define __STM32L1xx_HAL_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
-#define __STM32L1xx_HAL_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
-#define __STM32L1xx_HAL_VERSION_RC     (0x00) /*!< [7:0]  release candidate */
-#define __STM32L1xx_HAL_VERSION         ((__STM32L1xx_HAL_VERSION_MAIN << 24)\
-                                        |(__STM32L1xx_HAL_VERSION_SUB1 << 16)\
-                                        |(__STM32L1xx_HAL_VERSION_SUB2 << 8 )\
-                                        |(__STM32L1xx_HAL_VERSION_RC))
-
-#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/** @defgroup HAL_Private_Variables HAL Private Variables
-  * @{
-  */
-
-static __IO uint32_t uwTick;
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Functions HAL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions 
- *  @brief    Initialization and de-initialization functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..]  This section provides functions allowing to:
-      (+) Initializes the Flash interface, the NVIC allocation and initial clock 
-          configuration. It initializes the source of time base also when timeout 
-          is needed and the backup domain when enabled.
-      (+) de-Initializes common part of the HAL.
-      (+) Configure The time base source to have 1ms time base with a dedicated 
-          Tick interrupt priority. 
-        (++) Systick timer is used by default as source of time base, but user 
-             can eventually implement his proper time base source (a general purpose 
-             timer for example or other time source), keeping in mind that Time base 
-             duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and 
-             handled in milliseconds basis.
-        (++) Time base configuration function (HAL_InitTick ()) is called automatically 
-             at the beginning of the program after reset by HAL_Init() or at any time 
-             when clock is configured, by HAL_RCC_ClockConfig(). 
-        (++) Source of time base is configured  to generate interrupts at regular 
-             time intervals. Care must be taken if HAL_Delay() is called from a 
-             peripheral ISR process, the Tick interrupt line must have higher priority 
-            (numerically lower) than the peripheral interrupt. Otherwise the caller 
-            ISR process will be blocked. 
-       (++) functions affecting time base configurations are declared as __Weak  
-             to make  override possible  in case of other  implementations in user file.
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function configures the Flash prefetch, 
-  *        Configures time base source, NVIC and Low level hardware
-  * @note This function is called at the beginning of program after reset and before 
-  *       the clock configuration
-  * @note The time base configuration is based on MSI clock when exiting from Reset.
-  *       Once done, time base tick start incrementing.
-  *        In the default implementation,Systick is used as source of time base.
-  *        the tick variable is incremented each 1ms in its ISR.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_Init(void)
-{
-  /* Configure Flash prefetch */
-#if (PREFETCH_ENABLE != 0)
-  __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
-#endif /* PREFETCH_ENABLE */
-
-  /* Set Interrupt Group Priority */
-  HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
-  /* Use systick as time base source and configure 1ms tick (default clock after Reset is MSI) */
-  HAL_InitTick(TICK_INT_PRIORITY);
-
-  /* Init the low level hardware */
-  HAL_MspInit();
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief This function de-Initializes common part of the HAL and stops the source
-  *        of time base.
-  * @note This function is optional.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DeInit(void)
-{
-  /* Reset of all peripherals */
-  __APB1_FORCE_RESET();
-  __APB1_RELEASE_RESET();
-
-  __APB2_FORCE_RESET();
-  __APB2_RELEASE_RESET();
-
-  __AHB_FORCE_RESET();
-  __AHB_RELEASE_RESET();
-
-  /* De-Init the low level hardware */
-  HAL_MspDeInit();
-    
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspInit(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the MSP.
-  * @retval None
-  */
-__weak void HAL_MspDeInit(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief This function configures the source of the time base. 
-  *        The time source is configured  to have 1ms time base with a dedicated 
-  *        Tick interrupt priority.
-  * @note This function is called  automatically at the beginning of program after
-  *       reset by HAL_Init() or at any time when clock is reconfigured  by HAL_RCC_ClockConfig(). 
-  * @note In the default implementation, SysTick timer is the source of time base. 
-  *       It is used to generate interrupts at regular time intervals. 
-  *       Care must be taken if HAL_Delay() is called from a peripheral ISR process, 
-  *       The the SysTick interrupt must have higher priority (numerically lower) 
-  *       than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
-  *       The function is declared as __Weak  to be overwritten  in case of other
-  *       implementation  in user file.
-  * @param TickPriority: Tick interrupt priority.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
-{
-  /*Configure the SysTick to have interrupt in 1ms time basis*/
-  HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
-
-  /*Configure the SysTick IRQ priority */
-  HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
-
-   /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_Exported_Functions_Group2 HAL Control functions 
- *  @brief    HAL Control functions
- *
-@verbatim
- ===============================================================================
-                      ##### HAL Control functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Provide a tick value in millisecond
-      (+) Provide a blocking delay in millisecond
-      (+) Suspend the time base source interrupt
-      (+) Resume the time base source interrupt
-      (+) Get the HAL API driver version
-      (+) Get the device identifier
-      (+) Get the device revision identifier
-      (+) Enable/Disable Debug module during Sleep mode
-      (+) Enable/Disable Debug module during STOP mode
-      (+) Enable/Disable Debug module during STANDBY mode
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function is called to increment  a global variable "uwTick"
-  *        used as application time base.
-  * @note In the default implementation, this variable is incremented each 1ms
-  *       in Systick ISR.
- * @note This function is declared as __weak to be overwritten in case of other 
-  *      implementations in user file.
-  * @retval None
-  */
-__weak void HAL_IncTick(void)
-{
-  uwTick++;
-}
-
-/**
-  * @brief Provides a tick value in millisecond.
-  * @note This function is declared as __weak to be overwritten in case of other 
-  *       implementations in user file.
-  * @retval tick value
-  */
-__weak uint32_t HAL_GetTick(void)
-{
-  return uwTick;
-}
-
-/**
-  * @brief This function provides accurate delay (in milliseconds) based 
-  *        on variable incremented.
-  * @note In the default implementation , SysTick timer is the source of time base.
-  *       It is used to generate interrupts at regular time intervals where uwTick
-  *       is incremented.
-  * @note ThiS function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @param Delay: specifies the delay time length, in milliseconds.
-  * @retval None
-  */
-__weak void HAL_Delay(__IO uint32_t Delay)
-{
-  uint32_t tickstart = 0;
-  tickstart = HAL_GetTick();
-  while((HAL_GetTick() - tickstart) < Delay)
-  {
-  }
-}
-
-/**
-  * @brief Suspend Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_SuspendTick()
-  *       is called, the the SysTick interrupt will be disabled and so Tick increment 
-  *       is suspended.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_SuspendTick(void)
-{
-  /* Disable SysTick Interrupt */
-  CLEAR_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief Resume Tick increment.
-  * @note In the default implementation , SysTick timer is the source of time base. It is
-  *       used to generate interrupts at regular time intervals. Once HAL_ResumeTick()
-  *       is called, the the SysTick interrupt will be enabled and so Tick increment 
-  *       is resumed.
-  * @note This function is declared as __weak to be overwritten in case of other
-  *       implementations in user file.
-  * @retval None
-  */
-__weak void HAL_ResumeTick(void)
-{
-  /* Enable SysTick Interrupt */
-  SET_BIT(SysTick->CTRL,SysTick_CTRL_TICKINT_Msk);
-}
-
-/**
-  * @brief Returns the HAL revision
-  * @retval version: 0xXYZR (8bits for each decimal, R for RC)
-  */
-uint32_t HAL_GetHalVersion(void)
-{
- return __STM32L1xx_HAL_VERSION;
-}
-
-/**
-  * @brief Returns the device revision identifier.
-  * @retval Device revision identifier
-  */
-uint32_t HAL_GetREVID(void)
-{
-  return((DBGMCU->IDCODE) >> 16);
-}
-
-/**
-  * @brief  Returns the device identifier.
-  * @retval Device identifier
-  */
-uint32_t HAL_GetDEVID(void)
-{
-   return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
-}
-
-/**
-  * @brief  Enable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_EnableDBGSleepMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Disable the Debug Module during SLEEP mode
-  * @retval None
-  */
-void HAL_DisableDBGSleepMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_SLEEP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_EnableDBGStopMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Disable the Debug Module during STOP mode
-  * @retval None
-  */
-void HAL_DisableDBGStopMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STOP);
-}
-
-/**
-  * @brief  Enable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_EnableDBGStandbyMode(void)
-{
-  SET_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @brief  Disable the Debug Module during STANDBY mode
-  * @retval None
-  */
-void HAL_DisableDBGStandbyMode(void)
-{
-  CLEAR_BIT(DBGMCU->CR, DBGMCU_CR_DBG_STANDBY);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,955 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   This file contains all the functions prototypes for the HAL 
-  *          module driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_H
-#define __STM32L1xx_HAL_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_conf.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup HAL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup HAL_Exported_Constants HAL Exported Constants
-  * @{
-  */ 
-
-/** @defgroup SYSCFG_Constants SYSCFG: SYStem ConFiG
-  * @{
-  */ 
-
-/** @defgroup SYSCFG_BootMode Boot Mode
-  * @{
-  */
-
-#define SYSCFG_BOOT_MAINFLASH          ((uint32_t)0x00000000)
-#define SYSCFG_BOOT_SYSTEMFLASH        ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_0)
-#if defined(FSMC_R_BASE)
-#define SYSCFG_BOOT_FSMC               ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE_1)
-#endif /* FSMC_R_BASE  */
-#define SYSCFG_BOOT_SRAM               ((uint32_t)SYSCFG_MEMRMP_BOOT_MODE)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RI_Constants RI: Routing Interface
-  * @{
-  */ 
-
-/** @defgroup RI_InputCapture Input Capture
-  * @{
-  */ 
-
-#define RI_INPUTCAPTURE_IC1  RI_ICR_IC1    /*!< Input Capture 1 */
-#define RI_INPUTCAPTURE_IC2  RI_ICR_IC2    /*!< Input Capture 2 */
-#define RI_INPUTCAPTURE_IC3  RI_ICR_IC3    /*!< Input Capture 3 */
-#define RI_INPUTCAPTURE_IC4  RI_ICR_IC4    /*!< Input Capture 4 */
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup TIM_Select TIM Select
-  * @{
-  */ 
-  
-#define TIM_SELECT_NONE  ((uint32_t)0x00000000)    /*!< None selected */
-#define TIM_SELECT_TIM2  ((uint32_t)RI_ICR_TIM_0)  /*!< Timer 2 selected */
-#define TIM_SELECT_TIM3  ((uint32_t)RI_ICR_TIM_1)  /*!< Timer 3 selected */
-#define TIM_SELECT_TIM4  ((uint32_t)RI_ICR_TIM)    /*!< Timer 4 selected */
-
-#define IS_RI_TIM(__TIM__) (((__TIM__) == TIM_SELECT_NONE) || \
-                        ((__TIM__) == TIM_SELECT_TIM2) || \
-                        ((__TIM__) == TIM_SELECT_TIM3) || \
-                        ((__TIM__) == TIM_SELECT_TIM4))
-
-/**
-  * @}
-  */ 
-  
-/** @defgroup RI_InputCaptureRouting Input Capture Routing
-  * @{
-  */ 
-                                                          /* TIMx_IC1 TIMx_IC2  TIMx_IC3  TIMx_IC4 */  
-#define RI_INPUTCAPTUREROUTING_0   ((uint32_t)0x00000000) /* PA0       PA1      PA2       PA3      */
-#define RI_INPUTCAPTUREROUTING_1   ((uint32_t)0x00000001) /* PA4       PA5      PA6       PA7      */
-#define RI_INPUTCAPTUREROUTING_2   ((uint32_t)0x00000002) /* PA8       PA9      PA10      PA11     */
-#define RI_INPUTCAPTUREROUTING_3   ((uint32_t)0x00000003) /* PA12      PA13     PA14      PA15     */
-#define RI_INPUTCAPTUREROUTING_4   ((uint32_t)0x00000004) /* PC0       PC1      PC2       PC3      */
-#define RI_INPUTCAPTUREROUTING_5   ((uint32_t)0x00000005) /* PC4       PC5      PC6       PC7      */
-#define RI_INPUTCAPTUREROUTING_6   ((uint32_t)0x00000006) /* PC8       PC9      PC10      PC11     */
-#define RI_INPUTCAPTUREROUTING_7   ((uint32_t)0x00000007) /* PC12      PC13     PC14      PC15     */
-#define RI_INPUTCAPTUREROUTING_8   ((uint32_t)0x00000008) /* PD0       PD1      PD2       PD3      */
-#define RI_INPUTCAPTUREROUTING_9   ((uint32_t)0x00000009) /* PD4       PD5      PD6       PD7      */
-#define RI_INPUTCAPTUREROUTING_10  ((uint32_t)0x0000000A) /* PD8       PD9      PD10      PD11     */
-#define RI_INPUTCAPTUREROUTING_11  ((uint32_t)0x0000000B) /* PD12      PD13     PD14      PD15     */
-#define RI_INPUTCAPTUREROUTING_12  ((uint32_t)0x0000000C) /* PE0       PE1      PE2       PE3      */
-#define RI_INPUTCAPTUREROUTING_13  ((uint32_t)0x0000000D) /* PE4       PE5      PE6       PE7      */
-#define RI_INPUTCAPTUREROUTING_14  ((uint32_t)0x0000000E) /* PE8       PE9      PE10      PE11     */
-#define RI_INPUTCAPTUREROUTING_15  ((uint32_t)0x0000000F) /* PE12      PE13     PE14      PE15     */
-
-#define IS_RI_INPUTCAPTURE_ROUTING(__ROUTING__) (((__ROUTING__) == RI_INPUTCAPTUREROUTING_0) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_1) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_2) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_3) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_4) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_5) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_6) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_7) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_8) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_9) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_10) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_11) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_12) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_13) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_14) || \
-                                             ((__ROUTING__) == RI_INPUTCAPTUREROUTING_15))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RI_IOSwitch IO Switch
-  * @{
-  */ 
-#define RI_ASCR1_REGISTER       ((uint32_t)0x80000000)
-/* ASCR1 I/O switch: bit 31 is set to '1' to indicate that the mask is in ASCR1 register */
-#define RI_IOSWITCH_CH0         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_0)
-#define RI_IOSWITCH_CH1         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_1)
-#define RI_IOSWITCH_CH2         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_2)
-#define RI_IOSWITCH_CH3         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_3)
-#define RI_IOSWITCH_CH4         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_4)
-#define RI_IOSWITCH_CH5         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_5)
-#define RI_IOSWITCH_CH6         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_6)
-#define RI_IOSWITCH_CH7         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_7)
-#define RI_IOSWITCH_CH8         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_8)
-#define RI_IOSWITCH_CH9         ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_9)
-#define RI_IOSWITCH_CH10        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_10)
-#define RI_IOSWITCH_CH11        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_11)
-#define RI_IOSWITCH_CH12        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_12)
-#define RI_IOSWITCH_CH13        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_13)
-#define RI_IOSWITCH_CH14        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_14)
-#define RI_IOSWITCH_CH15        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_15)
-#define RI_IOSWITCH_CH18        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_18)
-#define RI_IOSWITCH_CH19        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_19)
-#define RI_IOSWITCH_CH20        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_20)
-#define RI_IOSWITCH_CH21        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_21)
-#define RI_IOSWITCH_CH22        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_22)
-#define RI_IOSWITCH_CH23        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_23)
-#define RI_IOSWITCH_CH24        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_24)
-#define RI_IOSWITCH_CH25        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_25)
-#define RI_IOSWITCH_VCOMP       ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_VCOMP) /* VCOMP (ADC channel 26) is an internal switch used to connect selected channel to COMP1 non inverting input */
-#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
-#define RI_IOSWITCH_CH27        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_27)
-#define RI_IOSWITCH_CH28        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_28)
-#define RI_IOSWITCH_CH29        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_29)
-#define RI_IOSWITCH_CH30        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_30)
-#define RI_IOSWITCH_CH31        ((uint32_t)RI_ASCR1_REGISTER | RI_ASCR1_CH_31)
-#endif /* RI_ASCR2_CH1b */
-
-/* ASCR2 IO switch: bit 31 is set to '0' to indicate that the mask is in ASCR2 register */  
-#define RI_IOSWITCH_GR10_1      ((uint32_t)RI_ASCR2_GR10_1)
-#define RI_IOSWITCH_GR10_2      ((uint32_t)RI_ASCR2_GR10_2)
-#define RI_IOSWITCH_GR10_3      ((uint32_t)RI_ASCR2_GR10_3)
-#define RI_IOSWITCH_GR10_4      ((uint32_t)RI_ASCR2_GR10_4)
-#define RI_IOSWITCH_GR6_1       ((uint32_t)RI_ASCR2_GR6_1)
-#define RI_IOSWITCH_GR6_2       ((uint32_t)RI_ASCR2_GR6_2)
-#define RI_IOSWITCH_GR5_1       ((uint32_t)RI_ASCR2_GR5_1)
-#define RI_IOSWITCH_GR5_2       ((uint32_t)RI_ASCR2_GR5_2)
-#define RI_IOSWITCH_GR5_3       ((uint32_t)RI_ASCR2_GR5_3)
-#define RI_IOSWITCH_GR4_1       ((uint32_t)RI_ASCR2_GR4_1)
-#define RI_IOSWITCH_GR4_2       ((uint32_t)RI_ASCR2_GR4_2)
-#define RI_IOSWITCH_GR4_3       ((uint32_t)RI_ASCR2_GR4_3)
-#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3, Cat.4 and Cat.5 */
-#define RI_IOSWITCH_CH0b        ((uint32_t)RI_ASCR2_CH0b)
-#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
-#define RI_IOSWITCH_CH1b        ((uint32_t)RI_ASCR2_CH1b)
-#define RI_IOSWITCH_CH2b        ((uint32_t)RI_ASCR2_CH2b)
-#define RI_IOSWITCH_CH3b        ((uint32_t)RI_ASCR2_CH3b)
-#define RI_IOSWITCH_CH6b        ((uint32_t)RI_ASCR2_CH6b)
-#define RI_IOSWITCH_CH7b        ((uint32_t)RI_ASCR2_CH7b)
-#define RI_IOSWITCH_CH8b        ((uint32_t)RI_ASCR2_CH8b)
-#define RI_IOSWITCH_CH9b        ((uint32_t)RI_ASCR2_CH9b)
-#define RI_IOSWITCH_CH10b       ((uint32_t)RI_ASCR2_CH10b)
-#define RI_IOSWITCH_CH11b       ((uint32_t)RI_ASCR2_CH11b)
-#define RI_IOSWITCH_CH12b       ((uint32_t)RI_ASCR2_CH12b)
-#endif /* RI_ASCR2_CH1b */
-#define RI_IOSWITCH_GR6_3       ((uint32_t)RI_ASCR2_GR6_3)
-#define RI_IOSWITCH_GR6_4       ((uint32_t)RI_ASCR2_GR6_4)
-#endif /* RI_ASCR2_CH0b */
-
-
-#if defined (RI_ASCR2_CH1b) /* STM32L1 devices category Cat.4 and Cat.5 */
-
-#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_CH27)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH28)    || ((__IOSWITCH__) == RI_IOSWITCH_CH29)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH30)    || ((__IOSWITCH__) == RI_IOSWITCH_CH31)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_1)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_2) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_3)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_4) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR6_3)   || ((__IOSWITCH__) == RI_IOSWITCH_GR6_4)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH0b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH1b)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH2b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH3b)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH6b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH7b)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH8b)    || ((__IOSWITCH__) == RI_IOSWITCH_CH9b)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH10b)   || ((__IOSWITCH__) == RI_IOSWITCH_CH11b)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH12b))
-
-#else /* !RI_ASCR2_CH1b */
-
-#if defined (RI_ASCR2_CH0b) /* STM32L1 devices category Cat.3 */
-
-#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_2)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_4)  || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_3)   || ((__IOSWITCH__) == RI_IOSWITCH_CH0b))
-
-#else /* !RI_ASCR2_CH0b */  /* STM32L1 devices category Cat.1 and Cat.2 */
-
-#define IS_RI_IOSWITCH(__IOSWITCH__) (((__IOSWITCH__) == RI_IOSWITCH_CH0) || ((__IOSWITCH__) == RI_IOSWITCH_CH1)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH2)     || ((__IOSWITCH__) == RI_IOSWITCH_CH3)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH4)     || ((__IOSWITCH__) == RI_IOSWITCH_CH5)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH6)     || ((__IOSWITCH__) == RI_IOSWITCH_CH7)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH8)     || ((__IOSWITCH__) == RI_IOSWITCH_CH9)    || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH10)    || ((__IOSWITCH__) == RI_IOSWITCH_CH11)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH12)    || ((__IOSWITCH__) == RI_IOSWITCH_CH13)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH14)    || ((__IOSWITCH__) == RI_IOSWITCH_CH15)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH18)    || ((__IOSWITCH__) == RI_IOSWITCH_CH19)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH20)    || ((__IOSWITCH__) == RI_IOSWITCH_CH21)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH22)    || ((__IOSWITCH__) == RI_IOSWITCH_CH23)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_CH24)    || ((__IOSWITCH__) == RI_IOSWITCH_CH25)   || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_VCOMP)   || ((__IOSWITCH__) == RI_IOSWITCH_GR10_1) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_2)  || ((__IOSWITCH__) == RI_IOSWITCH_GR10_3) || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR10_4)  || ((__IOSWITCH__) == RI_IOSWITCH_GR6_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR6_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_1)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR5_2)   || ((__IOSWITCH__) == RI_IOSWITCH_GR5_3)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_1)   || ((__IOSWITCH__) == RI_IOSWITCH_GR4_2)  || \
-                                  ((__IOSWITCH__) == RI_IOSWITCH_GR4_3))
-
-#endif /* RI_ASCR2_CH0b */
-#endif /* RI_ASCR2_CH1b */
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_Pin PIN define
-  * @{
-  */
-#define RI_PIN_0                 ((uint16_t)0x0001)  /*!< Pin 0 selected */
-#define RI_PIN_1                 ((uint16_t)0x0002)  /*!< Pin 1 selected */
-#define RI_PIN_2                 ((uint16_t)0x0004)  /*!< Pin 2 selected */
-#define RI_PIN_3                 ((uint16_t)0x0008)  /*!< Pin 3 selected */
-#define RI_PIN_4                 ((uint16_t)0x0010)  /*!< Pin 4 selected */
-#define RI_PIN_5                 ((uint16_t)0x0020)  /*!< Pin 5 selected */
-#define RI_PIN_6                 ((uint16_t)0x0040)  /*!< Pin 6 selected */
-#define RI_PIN_7                 ((uint16_t)0x0080)  /*!< Pin 7 selected */
-#define RI_PIN_8                 ((uint16_t)0x0100)  /*!< Pin 8 selected */
-#define RI_PIN_9                 ((uint16_t)0x0200)  /*!< Pin 9 selected */
-#define RI_PIN_10                ((uint16_t)0x0400)  /*!< Pin 10 selected */
-#define RI_PIN_11                ((uint16_t)0x0800)  /*!< Pin 11 selected */
-#define RI_PIN_12                ((uint16_t)0x1000)  /*!< Pin 12 selected */
-#define RI_PIN_13                ((uint16_t)0x2000)  /*!< Pin 13 selected */
-#define RI_PIN_14                ((uint16_t)0x4000)  /*!< Pin 14 selected */
-#define RI_PIN_15                ((uint16_t)0x8000)  /*!< Pin 15 selected */
-#define RI_PIN_ALL               ((uint16_t)0xFFFF)  /*!< All pins selected */
-
-#define IS_RI_PIN(__PIN__) ((__PIN__) != (uint16_t)0x00)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup HAL_Exported_Macros HAL Exported Macros
-  * @{
-  */
-
-/** @defgroup DBGMCU_Macros DBGMCU: Debug MCU
-  * @{
-  */
-
-/** @defgroup DBGMCU_Freeze_Unfreeze Freeze Unfreeze Peripherals in Debug mode 
-  * @brief   Freeze/Unfreeze Peripherals in Debug mode 
-  * @{
-  */
-  
-/**
-  * @brief  TIM2 Peripherals Debug mode 
-  */  
-#if defined (DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#define __HAL_FREEZE_TIM2_DBGMCU()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#define __HAL_UNFREEZE_TIM2_DBGMCU()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM2_STOP)
-#endif
-
-/**
-  * @brief  TIM3 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#define __HAL_FREEZE_TIM3_DBGMCU()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#define __HAL_UNFREEZE_TIM3_DBGMCU()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM3_STOP)
-#endif
-
-/**
-  * @brief  TIM4 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM4_STOP)
-#define __HAL_FREEZE_TIM4_DBGMCU()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
-#define __HAL_UNFREEZE_TIM4_DBGMCU()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM4_STOP)
-#endif
-
-/**
-  * @brief  TIM5 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM5_STOP)
-#define __HAL_FREEZE_TIM5_DBGMCU()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
-#define __HAL_UNFREEZE_TIM5_DBGMCU()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM5_STOP)
-#endif
-
-/**
-  * @brief  TIM6 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#define __HAL_FREEZE_TIM6_DBGMCU()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#define __HAL_UNFREEZE_TIM6_DBGMCU()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM6_STOP)
-#endif
-
-/**
-  * @brief  TIM7 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#define __HAL_FREEZE_TIM7_DBGMCU()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#define __HAL_UNFREEZE_TIM7_DBGMCU()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_TIM7_STOP)
-#endif
-
-/**
-  * @brief  RTC Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#define __HAL_FREEZE_RTC_DBGMCU()             SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#define __HAL_UNFREEZE_RTC_DBGMCU()           CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_RTC_STOP)
-#endif
-
-/**
-  * @brief  WWDG Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#define __HAL_FREEZE_WWDG_DBGMCU()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#define __HAL_UNFREEZE_WWDG_DBGMCU()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_WWDG_STOP)
-#endif
-
-/**
-  * @brief  IWDG Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#define __HAL_FREEZE_IWDG_DBGMCU()            SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#define __HAL_UNFREEZE_IWDG_DBGMCU()          CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_IWDG_STOP)
-#endif
-
-/**
-  * @brief  I2C1 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU()    SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
-#define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU()  CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
-#endif
-
-/**
-  * @brief  I2C2 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
-#define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU()    SET_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
-#define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU()  CLEAR_BIT(DBGMCU->APB1FZ, DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT)
-#endif
-
-/**
-  * @brief  TIM9 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB2_FZ_DBG_TIM9_STOP)
-#define __HAL_FREEZE_TIM9_DBGMCU()            SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
-#define __HAL_UNFREEZE_TIM9_DBGMCU()          CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM9_STOP)
-#endif
-
-/**
-  * @brief  TIM10 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB2_FZ_DBG_TIM10_STOP)
-#define __HAL_FREEZE_TIM10_DBGMCU()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
-#define __HAL_UNFREEZE_TIM10_DBGMCU()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM10_STOP)
-#endif
-
-/**
-  * @brief  TIM11 Peripherals Debug mode 
-  */
-#if defined (DBGMCU_APB2_FZ_DBG_TIM11_STOP)
-#define __HAL_FREEZE_TIM11_DBGMCU()           SET_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
-#define __HAL_UNFREEZE_TIM11_DBGMCU()         CLEAR_BIT(DBGMCU->APB2FZ, DBGMCU_APB2_FZ_DBG_TIM11_STOP)
-#endif
-
-/**
-  * @brief  Enables or disables the output of internal reference voltage 
-  *         (VREFINT) on I/O pin.
-  *         The VREFINT output can be routed to any I/O in group 3:
-  *          - For Cat.1 and Cat.2 devices: CH8 (PB0) or CH9 (PB1).
-  *          - For Cat.3 devices: CH8 (PB0), CH9 (PB1) or CH0b (PB2).
-  *          - For Cat.4 and Cat.5 devices: CH8 (PB0), CH9 (PB1), CH0b (PB2), 
-  *            CH1b (PF11) or CH2b (PF12).
-  *         Note: Comparator peripheral clock must be preliminarility enabled,
-  *               either in COMP user function "HAL_COMP_MspInit()" (should be 
-  *               done if comparators are used) or by direct clock enable:
-  *               Refer to macro "__COMP_CLK_ENABLE()".
-  *         Note: In addition with this macro, Vrefint output buffer must be 
-  *               connected to the selected I/O pin. Refer to macro
-  *               "__HAL_RI_IOSWITCH_CLOSE()".
-  * @note  ENABLE: Internal reference voltage connected to I/O group 3
-  * @note  DISABLE: Internal reference voltage disconnected from I/O group 3
-  * @retval None
-  */
-#define __HAL_VREFINT_OUT_ENABLE()       SET_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
-#define __HAL_VREFINT_OUT_DISABLE()      CLEAR_BIT(COMP->CSR, COMP_CSR_VREFOUTEN)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_Macros SYSCFG: SYStem ConFiG
-  * @{
-  */
-
-/** @defgroup SYSCFG_BootModeConfig Boot Mode Configuration
-  * @{
-  */
-
-/**
-  * @brief  Main Flash memory mapped at 0x00000000
-  */
-#define __HAL_REMAPMEMORY_FLASH()             CLEAR_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE)
-
-/** @brief  System Flash memory mapped at 0x00000000
-  */
-#define __HAL_REMAPMEMORY_SYSTEMFLASH()       MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0)
-
-/** @brief  Embedded SRAM mapped at 0x00000000
-  */
-#define __HAL_REMAPMEMORY_SRAM()              MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1)
-
-#if defined(FSMC_R_BASE)
-/** @brief  FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
-  */
-#define __HAL_REMAPMEMORY_FSMC()              MODIFY_REG(SYSCFG->MEMRMP, SYSCFG_MEMRMP_MEM_MODE, SYSCFG_MEMRMP_MEM_MODE_1)
-
-#endif /* FSMC_R_BASE */
-
-/**
-  * @brief  Returns the boot mode as configured by user.
-  * @retval The boot mode as configured by user. The returned value can be one 
-  *         of the following values:
-  *           @arg SYSCFG_BOOT_MAINFLASH
-  *           @arg SYSCFG_BOOT_SYSTEMFLASH
-  *           @arg SYSCFG_BOOT_FSMC (available only for STM32L151xD, STM32L152xD & STM32L162xD)
-  *           @arg SYSCFG_BOOT_SRAM
-  */
-#define __HAL_SYSCFG_GET_BOOT_MODE()          READ_BIT(SYSCFG->MEMRMP, SYSCFG_MEMRMP_BOOT_MODE)
-
-/**
-  * @}
-  */
-
-/** @defgroup SYSCFG_USBConfig USB DP line Configuration
-  * @{
-  */
-
-/**
-  * @brief  Control the internal pull-up on USB DP line.
-  */
-#define __HAL_SYSCFG_USBPULLUP_ENABLE()       SET_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
-
-#define __HAL_SYSCFG_USBPULLUP_DISABLE()      CLEAR_BIT(SYSCFG->PMC, SYSCFG_PMC_USB_PU)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_Macris RI: Routing Interface
-  * @{
-  */ 
-
-/** @defgroup RI_InputCaputureConfig Input Capture configuration
-  * @{
-  */ 
-
-/**
-  * @brief  Configures the routing interface to map Input Capture 1 of TIMx to a selected I/O pin.
-  * @param  __TIMSELECT__: Timer select.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
-  *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
-  * @param  __INPUT__: selects which pin to be routed to Input Capture.
-  *   This parameter must be a value of @ref RI_InputCaptureRouting
-  *     e.g.
-  *       __HAL_RI_REMAP_INPUTCAPTURE1(TIM_SELECT_TIM2, RI_INPUTCAPTUREROUTING_1)
-  *       allows routing of Input capture IC1 of TIM2 to PA4.
-  *       For details about correspondence between RI_INPUTCAPTUREROUTING_x 
-  *       and I/O pins refer to the parameters' description in the header file
-  *       or refer to the product reference manual.
-  * @note Input capture selection bits are not reset by this function.
-  *       To reset input capture selection bits, use SYSCFG_RIDeInit() function.
-  * @note The I/O should be configured in alternate function mode (AF14) using
-  *       GPIO_PinAFConfig() function.
-  * @retval None.
-  */
-#define __HAL_RI_REMAP_INPUTCAPTURE1(__TIMSELECT__, __INPUT__)  \
-          do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
-              assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
-              MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
-              SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC1); \
-              MODIFY_REG(RI->ICR, RI_ICR_IC1OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC1OS)); \
-          }while(0)
-
-/**
-  * @brief  Configures the routing interface to map Input Capture 2 of TIMx to a selected I/O pin.
-  * @param  __TIMSELECT__: Timer select.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
-  *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
-  * @param  __INPUT__: selects which pin to be routed to Input Capture.
-  *   This parameter must be a value of @ref RI_InputCaptureRouting
-  * @retval None.
-  */
-#define __HAL_RI_REMAP_INPUTCAPTURE2(__TIMSELECT__, __INPUT__)  \
-          do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
-              assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
-              MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
-              SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC2); \
-              MODIFY_REG(RI->ICR, RI_ICR_IC2OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC2OS)); \
-          }while(0)
-
-/**
-  * @brief  Configures the routing interface to map Input Capture 3 of TIMx to a selected I/O pin.
-  * @param  __TIMSELECT__: Timer select.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
-  *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
-  * @param  __INPUT__: selects which pin to be routed to Input Capture.
-  *   This parameter must be a value of @ref RI_InputCaptureRouting
-  * @retval None.
-  */
-#define __HAL_RI_REMAP_INPUTCAPTURE3(__TIMSELECT__, __INPUT__)  \
-          do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
-              assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
-              MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
-              SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC3); \
-              MODIFY_REG(RI->ICR, RI_ICR_IC3OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC3OS)); \
-          }while(0)
-
-/**
-  * @brief  Configures the routing interface to map Input Capture 4 of TIMx to a selected I/O pin.
-  * @param  __TIMSELECT__: Timer select.
-  *   This parameter can be one of the following values:
-  *     @arg TIM_SELECT_NONE: No timer selected and default Timer mapping is enabled.
-  *     @arg TIM_SELECT_TIM2: Timer 2 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM3: Timer 3 Input Captures to be routed.
-  *     @arg TIM_SELECT_TIM4: Timer 4 Input Captures to be routed.
-  * @param  __INPUT__: selects which pin to be routed to Input Capture.
-  *   This parameter must be a value of @ref RI_InputCaptureRouting
-  * @retval None.
-  */
-#define __HAL_RI_REMAP_INPUTCAPTURE4(__TIMSELECT__, __INPUT__)  \
-          do {assert_param(IS_RI_TIM(__TIMSELECT__)); \
-              assert_param(IS_RI_INPUTCAPTURE_ROUTING(__INPUT__)); \
-              MODIFY_REG(RI->ICR, RI_ICR_TIM, (__TIMSELECT__)); \
-              SET_BIT(RI->ICR, RI_INPUTCAPTURE_IC4); \
-              MODIFY_REG(RI->ICR, RI_ICR_IC4OS, (__INPUT__) << POSITION_VAL(RI_ICR_IC4OS)); \
-          }while(0)
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_SwitchControlConfig Switch Control configuration
-  * @{
-  */ 
-
-/**
-  * @brief  Enable or disable the switch control mode.
-  * @note  ENABLE: ADC analog switches closed if the corresponding 
-  *                    I/O switch is also closed.
-  *                    When using COMP1, switch control mode must be enabled.
-  * @note  DISABLE: ADC analog switches open or controlled by the ADC interface.
-  *                    When using the ADC for acquisition, switch control mode 
-  *                    must be disabled.
-  * @note COMP1 comparator and ADC cannot be used at the same time since 
-  *       they share the ADC switch matrix.
-  * @retval None
-  */
-#define __HAL_RI_SWITCHCONTROLMODE_ENABLE()       SET_BIT(RI->ASCR1, RI_ASCR1_SCM)
-
-#define __HAL_RI_SWITCHCONTROLMODE_DISABLE()      CLEAR_BIT(RI->ASCR1, RI_ASCR1_SCM)
-
-/*
-  * @brief  Close or Open the routing interface Input Output switches.
-  * @param  __IOSWITCH__: selects the I/O analog switch number.
-  *   This parameter must be a value of @ref RI_IOSwitch
-  * @retval None
-  */
-#define __HAL_RI_IOSWITCH_CLOSE(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
-            if ((__IOSWITCH__) >> 31 != 0 ) \
-            { \
-              SET_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
-            } \
-            else \
-            { \
-              SET_BIT(RI->ASCR2, (__IOSWITCH__)); \
-            } \
-          }while(0)
-
-#define __HAL_RI_IOSWITCH_OPEN(__IOSWITCH__) do { assert_param(IS_RI_IOSWITCH(__IOSWITCH__)); \
-            if ((__IOSWITCH__) >> 31 != 0 ) \
-            { \
-              CLEAR_BIT(RI->ASCR1, (__IOSWITCH__) & 0x7FFFFFFF); \
-            } \
-            else \
-            { \
-              CLEAR_BIT(RI->ASCR2, (__IOSWITCH__)); \
-            } \
-          }while(0)
-
-#if defined (COMP_CSR_SW1)
-/**
-  * @brief  Close or open the internal switch COMP1_SW1.
-  *         This switch connects I/O pin PC3 (can be used as ADC channel 13) 
-  *         and OPAMP3 ouput to ADC switch matrix (ADC channel VCOMP, channel
-  *         26) and COMP1 non-inverting input.
-  *         Pin PC3 connection depends on another switch setting, refer to
-  *         macro "__HAL_ADC_CHANNEL_SPEED_FAST()".
-  * @retval None.
-  */
-#define __HAL_RI_SWITCH_COMP1_SW1_CLOSE()  SET_BIT(COMP->CSR, COMP_CSR_SW1)
-
-#define __HAL_RI_SWITCH_COMP1_SW1_OPEN()   CLEAR_BIT(COMP->CSR, COMP_CSR_SW1)
-#endif /* COMP_CSR_SW1 */
-
-/**
-  * @}
-  */
-
-/** @defgroup RI_HystConfig Hysteresis Activation and Deactivation
-  * @{
-  */ 
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports A
-  *         When the I/Os are programmed in input mode by standard I/O port 
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the 
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTA_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR1, (__IOPIN__)); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTA_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR1, (__IOPIN__)); \
-          } while(0)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports B
-  *         When the I/Os are programmed in input mode by standard I/O port 
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the 
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTB_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTB_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR1, (__IOPIN__) << 16 ); \
-          } while(0)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports C
-  *         When the I/Os are programmed in input mode by standard I/O port 
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the 
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTC_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR2, (__IOPIN__)); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTC_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR2, (__IOPIN__)); \
-          } while(0)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports D
-  *         When the I/Os are programmed in input mode by standard I/O port 
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the 
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTD_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTD_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR2, (__IOPIN__) << 16 ); \
-          } while(0)
-
-#if defined (GPIOE_BASE)
-    
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports E
-  *         When the I/Os are programmed in input mode by standard I/O port 
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the 
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTE_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR3, (__IOPIN__)); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTE_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR3, (__IOPIN__)); \
-          } while(0)
-
-#endif /* GPIOE_BASE */
-
-#if defined(GPIOF_BASE) || defined(GPIOG_BASE)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports F
-  *         When the I/Os are programmed in input mode by standard I/O port 
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the 
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTF_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTF_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR3, (__IOPIN__) << 16 ); \
-          } while(0)
-
-/**
-  * @brief  Enable or disable Hysteresis of the input schmitt triger of Ports G
-  *         When the I/Os are programmed in input mode by standard I/O port 
-  *         registers, the Schmitt trigger and the hysteresis are enabled by default.
-  *         When hysteresis is disabled, it is possible to read the 
-  *         corresponding port with a trigger level of VDDIO/2.
-  *  @param __IOPIN__ : Selects the pin(s) on which to enable or disable hysteresis.
-  *   This parameter must be a value of @ref RI_Pin
-  * @retval None
-  */
-#define __HAL_RI_HYSTERIS_PORTG_ON(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            CLEAR_BIT(RI->HYSCR4, (__IOPIN__)); \
-          } while(0)
-
-#define __HAL_RI_HYSTERIS_PORTG_OFF(__IOPIN__) do {assert_param(IS_RI_PIN(__IOPIN__)); \
-            SET_BIT(RI->HYSCR4, (__IOPIN__)); \
-          } while(0)
-
-#endif /* GPIOF_BASE || GPIOG_BASE */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup HAL_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_Init(void);
-HAL_StatusTypeDef HAL_DeInit(void);
-void              HAL_MspInit(void);
-void              HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
-
-/**
-  * @}
-  */
-
-/** @addtogroup HAL_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void              HAL_IncTick(void);
-void              HAL_Delay(__IO uint32_t Delay);
-uint32_t          HAL_GetTick(void);
-void              HAL_SuspendTick(void);
-void              HAL_ResumeTick(void);
-uint32_t          HAL_GetHalVersion(void);
-uint32_t          HAL_GetREVID(void);
-uint32_t          HAL_GetDEVID(void);
-void              HAL_EnableDBGSleepMode(void);
-void              HAL_DisableDBGSleepMode(void);
-void              HAL_EnableDBGStopMode(void);
-void              HAL_DisableDBGStopMode(void);
-void              HAL_EnableDBGStandbyMode(void);
-void              HAL_DisableDBGStandbyMode(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1759 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_adc.c
-  * @author  MCD Application conversion
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Initialization and de-initialization functions
-  *             ++ Initialization and Configuration of ADC
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of regular
-  *             group, using 3 possible modes: polling, interruption or DMA.
-  *           + Control functions
-  *             ++ Analog Watchdog configuration
-  *             ++ Channels configuration on regular group
-  *           + State functions
-  *             ++ ADC state machine management
-  *             ++ Interrupts and flags management
-  *          Other functions (extended functions) are available in file 
-  *          "stm32l1xx_hal_adc_ex.c".
-  *
-  @verbatim
-  ==============================================================================
-                    ##### ADC specific features #####
-  ==============================================================================
-  [..] 
-  (#) 12-bit, 10-bit, 8-bit or 6-bit configurable resolution
-
-  (#) Interrupt generation at the end of regular conversion, end of injected
-      conversion, and in case of analog watchdog or overrun events.
-  
-  (#) Single and continuous conversion modes.
-  
-  (#) Scan mode for automatic conversion of channel 0 to channel 'n'.
-  
-  (#) Data alignment with in-built data coherency.
-  
-  (#) Channel-wise programmable sampling time.
-  
-  (#) ADC conversion Regular or Injected groups.
-
-  (#) External trigger (timer or EXTI) with configurable polarity for both  
-      regular and injected groups.
-
-  (#) DMA request generation for transfer of conversions data of regular group.
-  
-  (#) ADC calibration
-
-  (#) ADC offset on injected channels
-    
-  (#) ADC supply requirements: 2.4 V to 3.6 V at full speed and down to 1.8 V at 
-      slower speed.
-  
-  (#) ADC input range: from Vref– (connected to Vssa) to Vref+ (connected to 
-      Vdda or to an external voltage reference).
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-
-    (#) Enable the ADC interface 
-        As prerequisite, ADC clock must be configured at RCC top level.
-        Two clocks settings are mandatory:
-         - ADC clock (core clock):
-            Example:
-            Into HAL_ADC_MspInit() (recommended code location):
-              __ADC1_CLK_ENABLE();
-
-         - ADC clock (conversions clock): 
-            Only one possible clock source: derived from HSI RC 16MHz oscillator
-            (HSI).
-            Example:
-            Into HAL_ADC_MspInit() or with main setting of RCC:
-              RCC_OscInitTypeDef   RCC_OscInitStructure;
-              HAL_RCC_GetOscConfig(&RCC_OscInitStructure);
-              RCC_OscInitStructure.OscillatorType = (... | RCC_OSCILLATORTYPE_HSI);
-              RCC_OscInitStructure.HSIState = RCC_HSI_ON;
-              RCC_OscInitStructure.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
-              RCC_OscInitStructure.PLL.PLLState = RCC_PLL_NONE;
-              RCC_OscInitStructure.PLL.PLLSource = ...
-              RCC_OscInitStructure.PLL...
-              HAL_RCC_OscConfig(&RCC_OscInitStructure);
-
-            Note: ADC is connected directly to HSI RC 16MHz oscillator.
-                  Therefore, RCC PLL setting has no impact on ADC.
-                  PLL can be disabled (".PLL.PLLState = RCC_PLL_NONE") or 
-                  enabled with HSI16 as clock source
-                  (".PLL.PLLSource = RCC_PLLSOURCE_HSI") to be used as device 
-                  main clock source SYSCLK.
-                  The only mandatory setting is ".HSIState = RCC_HSI_ON"
-
-            Note: ADC clock prescaler is configured at ADC level with
-                  parameter "ClockPrescaler" using function HAL_ADC_Init().
-
-    (#) ADC pins configuration
-         (++) Enable the clock for the ADC GPIOs using the following function:
-             __GPIOx_CLK_ENABLE();   
-         (++) Configure these ADC pins in analog mode using HAL_GPIO_Init();  
-  
-     (#) Configure the ADC parameters (conversion resolution, data alignment,  
-         continuous mode, ...) using the HAL_ADC_Init() function.
-
-     (#) Activate the ADC peripheral using one of the start functions: 
-         HAL_ADC_Start(), HAL_ADC_Start_IT(), HAL_ADC_Start_DMA().
-  
-     *** Channels configuration to regular group  ***
-     ================================================
-     [..]    
-       (+) To configure the ADC regular group features, use 
-           HAL_ADC_Init() and HAL_ADC_ConfigChannel() functions.
-       (+) To read the ADC converted values, use the HAL_ADC_GetValue() function.
-              
-     *** DMA for regular group configuration ***
-     =========================================== 
-     [..]
-       (+) To enable the DMA mode for regular group, use the  
-           HAL_ADC_Start_DMA() function.
-       (+) To enable the generation of DMA requests continuously at the end of 
-           the last DMA transfer, use the HAL_ADC_Init() function.
-  
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADC ADC
-  * @brief ADC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ADC_Private_Constants ADC Private Constants
-  * @{
-  */
-
-  /* Fixed timeout values for ADC calibration, enable settling time.          */
-  /* Values defined to be higher than worst cases: low clocks freq,           */
-  /* maximum prescaler.                                                       */
-  /* Ex of profile low frequency : Clock source at 0.1 MHz, ADC clock         */
-  /* prescaler 4, sampling time 7.5 ADC clock cycles, resolution 12 bits.     */
-  /* Unit: ms                                                                 */
-  #define ADC_ENABLE_TIMEOUT              ((uint32_t) 2)
-  #define ADC_DISABLE_TIMEOUT             ((uint32_t) 2)
-
-  /* Delay for ADC stabilization time.                                        */
-  /* Maximum delay is 3.5us (refer to device datasheet, parameter tSTAB).     */
-  /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */
-  /* have the minimum number of CPU cycles to fulfill this delay.             */
-  #define ADC_STAB_DELAY_CPU_CYCLES       ((uint32_t)112)
-/**
-    * @}
-    */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma);
-static void ADC_DMAError(DMA_HandleTypeDef *hdma);
-/**
-    * @}
-    */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Functions ADC Exported Functions
-  * @{
-  */
-
-/** @defgroup ADC_Exported_Functions_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the ADC. 
-      (+) De-initialize the ADC
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the ADC peripheral and regular group according to  
-  *         parameters specified in structure "ADC_InitTypeDef".
-  * @note   As prerequisite, ADC clock must be configured at RCC top level
-  *         (clock source APB2).
-  *         See commented example code below that can be copied and uncommented 
-  *         into HAL_ADC_MspInit().
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes the ADC MSP (HAL_ADC_MspInit()) only when
-  *         coming from ADC state reset. Following calls to this function can
-  *         be used to reconfigure some parameters of ADC_InitTypeDef  
-  *         structure on the fly, without modifying MSP configuration. If ADC  
-  *         MSP has to be modified again, HAL_ADC_DeInit() must be called
-  *         before HAL_ADC_Init().
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_InitTypeDef".
-  * @note   This function configures the ADC within 2 scopes: scope of entire 
-  *         ADC and scope of regular group. For parameters details, see comments 
-  *         of structure "ADC_InitTypeDef".
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  uint32_t tmp_cr1 = 0;
-  uint32_t tmp_cr2 = 0;
-  
-  /* Check ADC handle */
-  if(hadc == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CLOCKPRESCALER(hadc->Init.ClockPrescaler));
-  assert_param(IS_ADC_RESOLUTION(hadc->Init.Resolution));
-  assert_param(IS_ADC_DATA_ALIGN(hadc->Init.DataAlign)); 
-  assert_param(IS_ADC_SCAN_MODE(hadc->Init.ScanConvMode));
-  assert_param(IS_ADC_EOC_SELECTION(hadc->Init.EOCSelection));
-  assert_param(IS_ADC_AUTOWAIT(hadc->Init.LowPowerAutoWait));
-  assert_param(IS_ADC_AUTOPOWEROFF(hadc->Init.LowPowerAutoPowerOff));
-  assert_param(IS_ADC_CHANNELSBANK(hadc->Init.ChannelsBank));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_EXTTRIG(hadc->Init.ExternalTrigConv));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DMAContinuousRequests));
-  
-  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
-  {
-    assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
-    assert_param(IS_FUNCTIONAL_STATE(hadc->Init.DiscontinuousConvMode));
-    assert_param(IS_ADC_REGULAR_DISCONT_NUMBER(hadc->Init.NbrOfDiscConversion));
-  }
-      
-  if(hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-  {
-    assert_param(IS_ADC_EXTTRIG_EDGE(hadc->Init.ExternalTrigConvEdge));
-  }
-  
-  
-  /* As prerequisite, into HAL_ADC_MspInit(), ADC clock must be configured    */
-  /* at RCC top level.                                                        */
-  /* Refer to header of this file for more details on clock enabling          */
-  /* procedure.                                                               */
-
-  /* Actions performed only if ADC is coming from state reset:                */
-  /* - Initialization of ADC MSP                                              */
-  if (hadc->State == HAL_ADC_STATE_RESET)
-  {
-    /* Enable SYSCFG clock to control the routing Interface (RI) */
-    __SYSCFG_CLK_ENABLE();
-  
-    /* Init the low level hardware */
-    HAL_ADC_MspInit(hadc);
-  } 
-  
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed.                                                     */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* Initialize the ADC state */
-    hadc->State = HAL_ADC_STATE_BUSY;
-
-    /* Set ADC parameters */
-    
-    /* Configuration of common ADC clock: clock source HSI with selectable    */
-    /* prescaler                                                              */
-    MODIFY_REG(ADC->CCR                 ,
-               ADC_CCR_ADCPRE           ,
-               hadc->Init.ClockPrescaler );
-
-    /* Configuration of ADC:                                                  */
-    /*  - external trigger polarity                                           */
-    /*  - End of conversion selection                                         */
-    /*  - DMA continuous request                                              */
-    /*  - Channels bank (Banks availability depends on devices categories)    */
-    /*  - continuous conversion mode                                          */
-    tmp_cr2 |= (hadc->Init.DataAlign                                   |
-                hadc->Init.EOCSelection                                |
-                __ADC_CR2_DMACONTREQ(hadc->Init.DMAContinuousRequests) |
-                hadc->Init.ChannelsBank                                |
-                __ADC_CR2_CONTINUOUS(hadc->Init.ContinuousConvMode)     );
-
-    /* Enable external trigger if trigger selection is different of software  */
-    /* start.                                                                 */
-    /* Note: This configuration keeps the hardware feature of parameter       */
-    /*       ExternalTrigConvEdge "trigger edge none" equivalent to           */
-    /*       software start.                                                  */
-    if (hadc->Init.ExternalTrigConv != ADC_SOFTWARE_START)
-    {
-      tmp_cr2 |= ( hadc->Init.ExternalTrigConv    |
-                  hadc->Init.ExternalTrigConvEdge );
-    }
-    
-    /* Parameters update conditioned to ADC state:                            */
-    /* Parameters that can be updated only when ADC is disabled:              */
-    /*  - delay selection (LowPowerAutoWait mode)                             */
-    /*  - resolution                                                          */
-    /*  - auto power off (LowPowerAutoPowerOff mode)                          */
-    /*  - scan mode                                                           */
-    /*  - discontinuous mode disable/enable                                   */
-    /*  - discontinuous mode number of conversions                            */
-    if ((__HAL_ADC_IS_ENABLED(hadc) == RESET))
-    {
-      tmp_cr2 |= hadc->Init.LowPowerAutoWait;
-      
-      tmp_cr1 |= (hadc->Init.Resolution                  |
-                  hadc->Init.LowPowerAutoPowerOff        |
-                  __ADC_CR1_SCAN(hadc->Init.ScanConvMode) );
-
-      /* Enable discontinuous mode only if continuous mode is disabled */
-      if ((hadc->Init.DiscontinuousConvMode == ENABLE) &&
-          (hadc->Init.ContinuousConvMode == DISABLE)     )
-      {    
-        /* Enable discontinuous mode of regular group */ 
-        /* Set the number of channels to be converted in discontinuous mode */
-        tmp_cr1 |= ((ADC_CR1_DISCEN) |
-                    __ADC_CR1_DISCONTINUOUS_NUM(hadc->Init.NbrOfDiscConversion));
-      }
-      
-      /* Update ADC configuration register CR1 with previous settings */
-        MODIFY_REG(hadc->Instance->CR1,
-                   ADC_CR1_RES     |
-                   ADC_CR1_PDI     |
-                   ADC_CR1_PDD     |
-                   ADC_CR1_DISCNUM |
-                   ADC_CR1_DISCEN  |
-                   ADC_CR1_SCAN       ,
-                   tmp_cr1             );
-    }
-    
-    /* Update ADC configuration register CR2 with previous settings */
-    MODIFY_REG(hadc->Instance->CR2      ,
-               __ADC_CR2_MASK_ADCINIT() ,
-               tmp_cr2                   );
-    
-    /* Configuration of regular group sequencer:                              */
-    /* - if scan mode is disabled, regular channels sequence length is set to */
-    /*   0x00: 1 channel converted (channel on regular rank 1)                */
-    /*   Parameter "NbrOfConversion" is discarded.                            */
-    /*   Note: Scan mode is present by hardware on this device and, if        */
-    /*   disabled, discards automatically nb of conversions. Anyway, nb of    */
-    /*   conversions is forced to 0x00 for alignment over all STM32 devices.  */
-    /* - if scan mode is enabled, regular channels sequence length is set to  */
-    /*   parameter "NbrOfConversion"                                          */
-    if (hadc->Init.ScanConvMode == ADC_SCAN_ENABLE)
-    {
-      MODIFY_REG(hadc->Instance->SQR1                    ,
-                 ADC_SQR1_L                              ,
-                 __ADC_SQR1_L(hadc->Init.NbrOfConversion) );
-    }
-    else
-    {
-      MODIFY_REG(hadc->Instance->SQR1,
-                 ADC_SQR1_L          ,
-                 0x00000000           );
-    }
-    
-    /* Check back that ADC registers have effectively been configured to      */
-    /* ensure of no potential problem of ADC core IP clocking.                */
-    /* Check through register CR2 (excluding execution control bits ADON,     */
-    /* JSWSTART, SWSTART and injected trigger bits JEXTEN and JEXTSEL).       */
-    if ((READ_REG(hadc->Instance->CR2) & ~(ADC_CR2_ADON |
-                                           ADC_CR2_SWSTART | ADC_CR2_JSWSTART |
-                                           ADC_CR2_JEXTEN  | ADC_CR2_JEXTSEL   ))
-         == tmp_cr2)
-    {
-      /* Set ADC error code to none */
-      __HAL_ADC_CLEAR_ERRORCODE(hadc);
-      
-      /* Initialize the ADC state */
-      hadc->State = HAL_ADC_STATE_READY;
-    }
-    else
-    {
-      /* Update ADC state machine to error */
-      hadc->State = HAL_ADC_STATE_ERROR;
-      
-      /* Set ADC error code to ADC IP internal error */
-      hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
-      
-      tmpHALStatus = HAL_ERROR;
-    }
-    
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    hadc->State = HAL_ADC_STATE_ERROR;
-        
-    tmpHALStatus = HAL_ERROR;
-  }
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Deinitialize the ADC peripheral registers to its default reset values.
-  * @note   To not impact other ADCs, reset of common ADC registers have been
-  *         left commented below.
-  *         If needed, the example code can be copied and uncommented into
-  *         function HAL_ADC_MspDeInit().
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef* hadc)
-{ 
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check ADC handle */
-  if(hadc == HAL_NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_BUSY;
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  tmpHALStatus = ADC_ConversionStop_Disable(hadc);
-  
-  
-  /* Configuration of ADC parameters if previous preliminary actions are      */ 
-  /* correctly completed.                                                     */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* ========== Reset ADC registers ========== */
-    /* Reset register SR */
-    __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_AWD | ADC_FLAG_JEOC | ADC_FLAG_EOC |
-                                ADC_FLAG_JSTRT | ADC_FLAG_STRT));
-                         
-    /* Reset register CR1 */
-    CLEAR_BIT(hadc->Instance->CR1, (ADC_CR1_OVRIE   | ADC_CR1_RES     | ADC_CR1_AWDEN  |
-                                    ADC_CR1_JAWDEN  | ADC_CR1_PDI     | ADC_CR1_PDD    |
-                                    ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN |
-                                    ADC_CR1_JAUTO   | ADC_CR1_AWDSGL  | ADC_CR1_SCAN   |
-                                    ADC_CR1_JEOCIE  | ADC_CR1_AWDIE   | ADC_CR1_EOCIE  |
-                                    ADC_CR1_AWDCH                                       ));
-    
-    /* Reset register CR2 */
-    __ADC_CR2_CLEAR(hadc);
-    
-    /* Reset register SMPR0 */
-    __ADC_SMPR0_CLEAR(hadc);
-    
-    /* Reset register SMPR1 */
-    CLEAR_BIT(hadc->Instance->SMPR1, (ADC_SMPR1_SMP29 | ADC_SMPR1_SMP28 | ADC_SMPR1_SMP27 | 
-                                      ADC_SMPR1_SMP26 | ADC_SMPR1_SMP25 | ADC_SMPR1_SMP24 | 
-                                      ADC_SMPR1_SMP23 | ADC_SMPR1_SMP22 | ADC_SMPR1_SMP21 |
-                                      ADC_SMPR1_SMP20                                      ));
-
-    /* Reset register SMPR2 */
-    CLEAR_BIT(hadc->Instance->SMPR2, (ADC_SMPR2_SMP19 | ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | 
-                                      ADC_SMPR2_SMP16 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | 
-                                      ADC_SMPR2_SMP13 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 |
-                                      ADC_SMPR2_SMP10                                      ));
-    
-    /* Reset register SMPR3 */
-    CLEAR_BIT(hadc->Instance->SMPR3, (ADC_SMPR3_SMP9 | ADC_SMPR3_SMP8 | ADC_SMPR3_SMP7 | 
-                                      ADC_SMPR3_SMP6 | ADC_SMPR3_SMP5 | ADC_SMPR3_SMP4 | 
-                                      ADC_SMPR3_SMP3 | ADC_SMPR3_SMP2 | ADC_SMPR3_SMP1 |
-                                      ADC_SMPR3_SMP0                                    ));
-    
-    /* Reset register JOFR1 */
-    CLEAR_BIT(hadc->Instance->JOFR1, ADC_JOFR1_JOFFSET1);
-    /* Reset register JOFR2 */
-    CLEAR_BIT(hadc->Instance->JOFR2, ADC_JOFR2_JOFFSET2);
-    /* Reset register JOFR3 */
-    CLEAR_BIT(hadc->Instance->JOFR3, ADC_JOFR3_JOFFSET3);
-    /* Reset register JOFR4 */
-    CLEAR_BIT(hadc->Instance->JOFR4, ADC_JOFR4_JOFFSET4);
-    
-    /* Reset register HTR */
-    CLEAR_BIT(hadc->Instance->HTR, ADC_HTR_HT);
-    /* Reset register LTR */
-    CLEAR_BIT(hadc->Instance->LTR, ADC_LTR_LT);
-    
-    /* Reset register SQR1 */
-    CLEAR_BIT(hadc->Instance->SQR1, (ADC_SQR1_L | __ADC_SQR1_SQXX));
-    
-    /* Reset register SQR2 */
-    CLEAR_BIT(hadc->Instance->SQR2, (ADC_SQR2_SQ24 | ADC_SQR2_SQ23 | ADC_SQR2_SQ22 | 
-                                     ADC_SQR2_SQ21 | ADC_SQR2_SQ20 | ADC_SQR2_SQ19  ));
-    
-    /* Reset register SQR3 */
-    CLEAR_BIT(hadc->Instance->SQR3, (ADC_SQR3_SQ18 | ADC_SQR3_SQ17 | ADC_SQR3_SQ16 | 
-                                     ADC_SQR3_SQ15 | ADC_SQR3_SQ14 | ADC_SQR3_SQ13  ));
-    
-    /* Reset register SQR4 */
-    CLEAR_BIT(hadc->Instance->SQR4, (ADC_SQR4_SQ12 | ADC_SQR4_SQ11 | ADC_SQR4_SQ10 | 
-                                     ADC_SQR4_SQ9  | ADC_SQR4_SQ8  | ADC_SQR4_SQ7   ));
-    
-    /* Reset register SQR5 */
-    CLEAR_BIT(hadc->Instance->SQR5, (ADC_SQR5_SQ6 | ADC_SQR5_SQ5 | ADC_SQR5_SQ4 | 
-                                     ADC_SQR5_SQ3 | ADC_SQR5_SQ2 | ADC_SQR5_SQ1  ));
-    
-    
-    /* Reset register JSQR */
-    CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL |
-                                     ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | 
-                                     ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  ));
-    
-    /* Reset register JSQR */
-    CLEAR_BIT(hadc->Instance->JSQR, (ADC_JSQR_JL |
-                                     ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3 | 
-                                     ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1  ));
-    
-    /* Reset register DR */
-    /* bits in access mode read only, no direct reset applicable*/
-    
-    /* Reset registers JDR1, JDR2, JDR3, JDR4 */
-    /* bits in access mode read only, no direct reset applicable*/
-    
-    /* Reset register CCR */
-    CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE);   
-    
-    /* ========== Hard reset ADC peripheral ========== */
-    /* Performs a global reset of the entire ADC peripheral: ADC state is     */
-    /* forced to a similar state after device power-on.                       */
-    /* If needed, copy-paste and uncomment the following reset code into      */
-    /* function "void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)":              */
-    /*                                                                        */
-    /*  __ADC1_FORCE_RESET()                                                  */
-    /*  __ADC1_RELEASE_RESET()                                                */
-    
-    /* DeInit the low level hardware */
-    HAL_ADC_MspDeInit(hadc);
-    
-    /* Set ADC error code to none */
-    __HAL_ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_RESET; 
-  
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-    
-/**
-  * @brief  Initializes the ADC MSP.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc)
-{
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_MspInit must be implemented in the user file.
-   */ 
-}
-
-/**
-  * @brief  DeInitializes the ADC MSP.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc)
-{
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_MspDeInit must be implemented in the user file.
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of regular group.
-      (+) Stop conversion of regular group.
-      (+) Poll for conversion complete on regular group.
-      (+) Poll for conversion event.
-      (+) Get result of regular channel conversion.
-      (+) Start conversion of regular group and enable interruptions.
-      (+) Stop conversion of regular group and disable interruptions.
-      (+) Handle ADC interrupt request
-      (+) Start conversion of regular group and enable DMA transfer.
-      (+) Stop conversion of regular group and disable ADC DMA transfer.
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables ADC, starts conversion of regular group.
-  *         Interruptions enabled in this function: None.
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-   
-  /* Enable the ADC peripheral */
-  tmpHALStatus = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* State machine update: Check if an injected conversion is ongoing */
-    if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
-    }
-    else
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_REG;
-    }
-
-    /* Set ADC error code to none */
-    __HAL_ADC_CLEAR_ERRORCODE(hadc);
-  
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-        
-    /* Start conversion of regular group if software start has been selected. */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
-    {
-      /* Start ADC conversion on regular group */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected channels in 
-  *         case of auto_injection mode), disable ADC peripheral.
-  * @note:  ADC peripheral disable is forcing interruption of potential 
-  *         conversion on injected group. If injected group is under use, it
-  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-     
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  tmpHALStatus = ADC_ConversionStop_Disable(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_READY;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Wait for regular group conversion to be completed.
-  * @param  hadc: ADC handle
-  * @param  Timeout: Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
- 
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-     
-  /* Wait until End of Conversion flag is raised */
-  while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_EOC))
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update ADC state machine to timeout */
-        hadc->State = HAL_ADC_STATE_TIMEOUT;
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_ERROR;
-      }
-    }
-  }
-  
-  /* Clear end of conversion flag of regular group if low power feature "Auto */
-  /* Wait" is disabled, to not interfere with this feature until data         */
-  /* register is read using function HAL_ADC_GetValue().                      */
-  if (hadc->Init.LowPowerAutoWait == DISABLE)
-  {
-    /* Clear regular group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-  }
-  
-  /* Update state machine on conversion status if not in error state */
-  if(hadc->State != HAL_ADC_STATE_ERROR)
-  {
-    /* Update ADC state machine */
-    if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
-    {
-      /* Check if a conversion is ready on injected group */
-      if(hadc->State == HAL_ADC_STATE_EOC_INJ)
-      {
-        /* Change ADC state */
-        hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
-      }
-      else
-      {
-        /* Change ADC state */
-        hadc->State = HAL_ADC_STATE_EOC_REG;
-      }
-    }
-  }
-  
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Poll for conversion event.
-  * @param  hadc: ADC handle
-  * @param  EventType: the ADC event type.
-  *          This parameter can be one of the following values:
-  *            @arg AWD_EVENT: ADC Analog watchdog event.
-  *            @arg OVR_EVENT: ADC Overrun event
-  * @param  Timeout: Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout)
-{
-  uint32_t tickstart = 0; 
-
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_EVENT_TYPE(EventType));
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-      
-  /* Check selected event flag */
-  while(__HAL_ADC_GET_FLAG(hadc, EventType) == RESET)
-  {
-    /* Check if timeout is disabled (set to infinite wait) */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update ADC state machine to timeout */
-        hadc->State = HAL_ADC_STATE_TIMEOUT;
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-        
-        return HAL_ERROR;
-      }
-    }
-  }
-  
-  switch(EventType)
-  {
-  /* Analog watchdog (level out of window) event */
-  case AWD_EVENT:
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_AWD;
-      
-    /* Clear ADC analog watchdog flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_AWD);
-    break;
-  
-  /* Overrun event */
-  default: /* Case OVR_EVENT */
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_ERROR;
-      
-    /* Set ADC error code to overrun */
-    hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
-
-    /* Clear ADC Overrun flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-    break;
-  }
-    
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of regular group with interruption.
-  *         Interruptions enabled in this function: EOC (end of conversion),
-  *         overrun.
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Enable the ADC peripheral */
-  tmpHALStatus = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* State machine update: Check if an injected conversion is ongoing */
-    if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
-    }
-    else
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_REG;
-    }
-
-    /* Set ADC error code to none */
-    __HAL_ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-    
-    /* Enable end of conversion interrupt for regular group */
-    __HAL_ADC_ENABLE_IT(hadc, (ADC_IT_EOC | ADC_IT_OVR));
-    
-    /* Start conversion of regular group if software start has been selected. */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
-    {
-      /* Start ADC conversion on regular group */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
-    }   
-    
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
-  *         case of auto_injection mode), disable interrution of 
-  *         end-of-conversion, disable ADC peripheral.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-     
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  tmpHALStatus = ADC_ConversionStop_Disable(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* Disable ADC end of conversion interrupt for regular group */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-    
-    /* Change ADC state */
-    hadc->State = HAL_ADC_STATE_READY;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of regular group and transfers result
-  *         through DMA.
-  *         Interruptions enabled in this function:
-  *         overrun, DMA half transfer, DMA transfer complete. 
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc: ADC handle
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from ADC peripheral to memory.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Enable the ADC peripheral */
-  tmpHALStatus = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* State machine update: Check if an injected conversion is ongoing */
-    if(hadc->State == HAL_ADC_STATE_BUSY_INJ)
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
-    }
-    else
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_REG;
-    }
-    
-    /* Set ADC error code to none */
-    __HAL_ADC_CLEAR_ERRORCODE(hadc);
-    
-
-    /* Set the DMA transfer complete callback */
-    hadc->DMA_Handle->XferCpltCallback = ADC_DMAConvCplt;
-
-    /* Set the DMA half transfer complete callback */
-    hadc->DMA_Handle->XferHalfCpltCallback = ADC_DMAHalfConvCplt;
-    
-    /* Set the DMA error callback */
-    hadc->DMA_Handle->XferErrorCallback = ADC_DMAError;
-
-    
-    /* Manage ADC and DMA start: ADC overrun interruption, DMA start, ADC     */
-    /* start (in case of SW start):                                           */
-    
-    /* Clear regular group conversion flag and overrun flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_EOC);
-
-    /* Enable ADC overrun interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_OVR);
-    
-    /* Enable ADC DMA mode */
-    hadc->Instance->CR2 |= ADC_CR2_DMA;
-    
-    /* Start the DMA channel */
-    HAL_DMA_Start_IT(hadc->DMA_Handle, (uint32_t)&hadc->Instance->DR, (uint32_t)pData, Length);
-    
-    /* Start conversion of regular group if software start has been selected. */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    /* Note: Alternate trigger for single conversion could be to force an     */
-    /*       additional set of bit ADON "hadc->Instance->CR2 |= ADC_CR2_ADON;"*/
-    if (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc))
-    {
-      /* Start ADC conversion on regular group */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_SWSTART);
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Stop ADC conversion of regular group (and injected group in 
-  *         case of auto_injection mode), disable ADC DMA transfer, disable 
-  *         ADC peripheral.
-  * @note:  ADC peripheral disable is forcing interruption of potential 
-  *         conversion on injected group. If injected group is under use, it
-  *         should be preliminarily stopped using HAL_ADCEx_InjectedStop function.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-     
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Stop potential conversion on going, on regular and injected groups */
-  /* Disable ADC peripheral */
-  tmpHALStatus = ADC_ConversionStop_Disable(hadc);
-  
-  /* Check if ADC is effectively disabled */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* Disable ADC DMA mode */
-    hadc->Instance->CR2 &= ~ADC_CR2_DMA;
-    
-    /* Disable the DMA channel (in case of DMA in circular mode or stop while */
-    /* DMA transfer is on going)                                              */
-    tmpHALStatus = HAL_DMA_Abort(hadc->DMA_Handle);
-    
-    /* Check if DMA channel effectively disabled */
-    if (tmpHALStatus != HAL_ERROR)
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_READY;
-    }
-    else
-    {
-      /* Update ADC state machine to error */
-      hadc->State = HAL_ADC_STATE_ERROR;      
-    }
-  }
-    
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-    
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Get ADC regular group conversion result.
-  * @param  hadc: ADC handle
-  * @retval Converted value
-  */
-uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Note: EOC flag is not cleared here by software because automatically     */
-  /*       cleared by hardware when reading register DR.                      */
-  
-  /* Return ADC converted value */ 
-  return hadc->Instance->DR;
-}
-
-/**
-  * @brief  DMA transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAConvCplt(DMA_HandleTypeDef *hdma)
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
- 
-  /* Update state machine on conversion status if not in error state */
-  if(hadc->State != HAL_ADC_STATE_ERROR)
-  {
-    /* Update ADC state machine */
-    if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
-    {
-      /* Check if a conversion is ready on injected group */
-      if(hadc->State == HAL_ADC_STATE_EOC_INJ)
-      {
-        /* Change ADC state */
-        hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
-      }
-      else
-      {
-        /* Change ADC state */
-        hadc->State = HAL_ADC_STATE_EOC_REG;
-      }
-    }
-  }
-  
-  /* Conversion complete callback */
-  HAL_ADC_ConvCpltCallback(hadc); 
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAHalfConvCplt(DMA_HandleTypeDef *hdma)   
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Half conversion callback */
-  HAL_ADC_ConvHalfCpltCallback(hadc); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to DMA handle.
-  * @retval None
-  */
-static void ADC_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  /* Retrieve ADC handle corresponding to current DMA handle */
-  ADC_HandleTypeDef* hadc = ( ADC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Change ADC state */
-  hadc->State = HAL_ADC_STATE_ERROR;
-  
-  /* Set ADC error code to DMA error */
-  hadc->ErrorCode |= HAL_ADC_ERROR_DMA;
-  
-  /* Error callback */
-  HAL_ADC_ErrorCallback(hadc); 
-}
-
-/**
-  * @brief  Handles ADC interrupt request  
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_FUNCTIONAL_STATE(hadc->Init.ContinuousConvMode));
-  assert_param(IS_ADC_REGULAR_NB_CONV(hadc->Init.NbrOfConversion));
-
-  
-  /* ========== Check End of Conversion flag for regular group ========== */
-  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_EOC))
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_EOC) )
-    {
-      /* Update state machine on conversion status if not in error state */
-      if(hadc->State != HAL_ADC_STATE_ERROR)
-      {
-        /* Update ADC state machine */
-        if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
-        {
-          /* Check if a conversion is ready on injected group */
-          if(hadc->State == HAL_ADC_STATE_EOC_INJ)
-          {
-            /* Change ADC state */
-            hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
-          }
-          else
-          {
-            /* Change ADC state */
-            hadc->State = HAL_ADC_STATE_EOC_REG;
-          }
-        }
-      }
-
-      /* Disable interruption if no further conversion upcoming regular         */
-      /* external trigger or by continuous mode                                 */
-      if(__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) && 
-         (hadc->Init.ContinuousConvMode == DISABLE)  )
-      {
-        /* Disable ADC end of single conversion interrupt  */
-        /* Note: Overrun interrupt was enabled with EOC interrupt in            */
-        /* HAL_ADC_Start_IT(), but is not disabled here because can be used by  */
-        /* overrun IRQ process below.                                           */
-        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_EOC);
-      }
-
-      /* Conversion complete callback */
-      HAL_ADC_ConvCpltCallback(hadc);
-      
-      /* Clear regular group conversion flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_STRT | ADC_FLAG_EOC);
-    }
-  }
-
-  /* ========== Check End of Conversion flag for injected group ========== */
-  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_JEOC))
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_JEOC))
-    {
-      /* Update state machine on conversion status if not in error state */
-      if(hadc->State != HAL_ADC_STATE_ERROR)
-      {
-        /* Update ADC state machine */
-        if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
-        {
-
-          if(hadc->State == HAL_ADC_STATE_EOC_REG)
-          {
-            /* Change ADC state */
-            hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
-          }
-          else
-          {
-            /* Change ADC state */
-            hadc->State = HAL_ADC_STATE_EOC_INJ;
-          }
-        }
-      }
-
-      /* Disable interruption if no further conversion upcoming injected        */
-      /* external trigger or by automatic injected conversion with regular      */
-      /* group having no further conversion upcoming (same conditions as        */
-      /* regular group interruption disabling above).                           */
-      if(__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc)              || 
-         (HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO) &&     
-         (__HAL_ADC_IS_SOFTWARE_START_REGULAR(hadc) &&              
-          (hadc->Init.ContinuousConvMode == DISABLE)  )         )  )
-      {
-        /* Disable ADC end of single conversion interrupt  */
-        __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-      }
-
-      /* Conversion complete callback */ 
-      HAL_ADCEx_InjectedConvCpltCallback(hadc);
-      
-      /* Clear injected group conversion flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, (ADC_FLAG_JSTRT | ADC_FLAG_JEOC));
-    }
-  }
-   
-  /* ========== Check Analog watchdog flags ========== */
-  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_AWD))
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_AWD))
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_AWD;
-        
-      /* Clear the ADCx's Analog watchdog flag */
-      __HAL_ADC_CLEAR_FLAG(hadc,ADC_FLAG_AWD);
-      
-      /* Level out of window callback */ 
-      HAL_ADC_LevelOutOfWindowCallback(hadc);
-    }
-  }
-  
-  /* ========== Check Overrun flag ========== */
-  if(__HAL_ADC_GET_IT_SOURCE(hadc, ADC_IT_OVR))
-  {
-    if(__HAL_ADC_GET_FLAG(hadc, ADC_FLAG_OVR))
-    {
-      /* Change ADC state to error state */
-      hadc->State = HAL_ADC_STATE_ERROR;
-      
-      /* Set ADC error code to overrun */
-      hadc->ErrorCode |= HAL_ADC_ERROR_OVR;
-      
-      /* Error callback */ 
-      HAL_ADC_ErrorCallback(hadc);
-      
-      /* Clear the Overrun flag */
-      __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_OVR);
-    }
-  }
-  
-}
-
-/**
-  * @brief  Conversion complete callback in non blocking mode 
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ConvCpltCallback must be implemented in the user file.
-   */
-}
-
-/**
-  * @brief  Conversion DMA half-transfer callback in non blocking mode 
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ConvHalfCpltCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  Analog watchdog callback in non blocking mode. 
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc)
-{
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_LevelOutOfWindowCallback must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  ADC error callback in non blocking mode
-  *        (ADC conversion with interruption or transfer by DMA)
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc)
-{
-  /* NOTE : This function should not be modified. When the callback is needed,
-            function HAL_ADC_ErrorCallback must be implemented in the user file.
-  */
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels on regular group
-      (+) Configure the analog watchdog
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the the selected channel to be linked to the regular
-  *         group.
-  * @note   In case of usage of internal measurement channels:
-  *         Vbat/VrefInt/TempSensor.
-  *         These internal paths can be be disabled using function 
-  *         HAL_ADC_DeInit().
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes channel into regular group, following  
-  *         calls to this function can be used to reconfigure some parameters 
-  *         of structure "ADC_ChannelConfTypeDef" on the fly, without reseting 
-  *         the ADC.
-  *         The setting of these parameters is conditioned to ADC state.
-  *         For parameters constraints, see comments of structure 
-  *         "ADC_ChannelConfTypeDef".
-  * @param  hadc: ADC handle
-  * @param  sConfig: Structure of ADC channel for regular group.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig)
-{ 
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CHANNEL(sConfig->Channel));
-  assert_param(IS_ADC_REGULAR_RANK(sConfig->Rank));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfig->SamplingTime));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-   
-  /* Regular sequence configuration */
-  /* For Rank 1 to 6 */
-  if (sConfig->Rank < 7)
-  {    
-    MODIFY_REG(hadc->Instance->SQR5,
-               __ADC_SQR5_RK(ADC_SQR5_SQ1, sConfig->Rank),
-               __ADC_SQR5_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 7 to 12 */
-  else if (sConfig->Rank < 13)
-  {   
-    MODIFY_REG(hadc->Instance->SQR4,
-               __ADC_SQR4_RK(ADC_SQR4_SQ7, sConfig->Rank),
-               __ADC_SQR4_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 13 to 18 */
-  else if (sConfig->Rank < 19)
-  {
-    MODIFY_REG(hadc->Instance->SQR3,
-               __ADC_SQR3_RK(ADC_SQR3_SQ13, sConfig->Rank),
-               __ADC_SQR3_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 19 to 24 */
-  else if (sConfig->Rank < 25)
-  {
-    MODIFY_REG(hadc->Instance->SQR2,
-               __ADC_SQR2_RK(ADC_SQR2_SQ19, sConfig->Rank),
-               __ADC_SQR2_RK(sConfig->Channel, sConfig->Rank) );
-  }
-  /* For Rank 25 to 28 */
-  else
-  {
-    MODIFY_REG(hadc->Instance->SQR1,
-               __ADC_SQR1_RK(ADC_SQR1_SQ25, sConfig->Rank),
-               __ADC_SQR1_RK(sConfig->Channel, sConfig->Rank) );
-  }
-      
-  
-  /* Channel sampling time configuration */
-  /* For channels 0 to 9 */
-  if (sConfig->Channel < ADC_CHANNEL_10)
-  {
-    MODIFY_REG(hadc->Instance->SMPR3,
-               __ADC_SMPR3(ADC_SMPR3_SMP0, sConfig->Channel),
-               __ADC_SMPR3(sConfig->SamplingTime, sConfig->Channel) );
-  }
-  /* For channels 10 to 19 */
-  else if (sConfig->Channel < ADC_CHANNEL_20)
-  {
-    MODIFY_REG(hadc->Instance->SMPR2,
-               __ADC_SMPR2(ADC_SMPR2_SMP10, sConfig->Channel),
-               __ADC_SMPR2(sConfig->SamplingTime, sConfig->Channel) );
-  }
-  /* For channels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
-  /* For channels 20 to 29 for devices Cat4, Cat.5 */
-  else if (sConfig->Channel <= ADC_SMPR1_CHANNEL_MAX)
-  {
-    MODIFY_REG(hadc->Instance->SMPR1,
-               __ADC_SMPR1(ADC_SMPR1_SMP20, sConfig->Channel),
-               __ADC_SMPR1(sConfig->SamplingTime, sConfig->Channel) );
-  }
-  /* For channels 30 to 31 for devices Cat4, Cat.5 */
-  else
-  {
-    __ADC_SMPR0_CHANNEL_SET(hadc, sConfig->SamplingTime, sConfig->Channel);
-  }
-
-  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
-  /* and VREFINT measurement path.                                            */
-  if ((sConfig->Channel == ADC_CHANNEL_TEMPSENSOR) ||
-      (sConfig->Channel == ADC_CHANNEL_VREFINT)      )
-  {
-    SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
-  }
-   
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Configures the analog watchdog.
-  * @param  hadc: ADC handle
-  * @param  AnalogWDGConfig: Structure of ADC analog watchdog configuration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_ANALOG_WATCHDOG_MODE(AnalogWDGConfig->WatchdogMode));
-  assert_param(IS_FUNCTIONAL_STATE(AnalogWDGConfig->ITMode));
-  assert_param(IS_ADC_RANGE(AnalogWDGConfig->HighThreshold));
-  assert_param(IS_ADC_RANGE(AnalogWDGConfig->LowThreshold));
-  
-  if((AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REG)     ||
-     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_INJEC)   ||
-     (AnalogWDGConfig->WatchdogMode == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  )
-  {
-    assert_param(IS_ADC_CHANNEL(AnalogWDGConfig->Channel));
-  }
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Analog watchdog configuration */
-
-  /* Configure ADC Analog watchdog interrupt */
-  if(AnalogWDGConfig->ITMode == ENABLE)
-  {
-    /* Enable the ADC Analog watchdog interrupt */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_AWD);
-  }
-  else
-  {
-    /* Disable the ADC Analog watchdog interrupt */
-    __HAL_ADC_DISABLE_IT(hadc, ADC_IT_AWD);
-  }
-  
-  /* Configuration of analog watchdog:                                        */
-  /*  - Set the analog watchdog enable mode: regular and/or injected groups,  */
-  /*    one or all channels.                                                  */
-  /*  - Set the Analog watchdog channel (is not used if watchdog              */
-  /*    mode "all channels": ADC_CFGR_AWD1SGL=0).                             */
-  hadc->Instance->CR1 &= ~( ADC_CR1_AWDSGL |
-                            ADC_CR1_JAWDEN |
-                            ADC_CR1_AWDEN  |
-                            ADC_CR1_AWDCH   );
-  
-  hadc->Instance->CR1 |= ( AnalogWDGConfig->WatchdogMode |
-                           AnalogWDGConfig->Channel       );
-      
-  /* Set the high threshold */
-  hadc->Instance->HTR = AnalogWDGConfig->HighThreshold;
-  
-  /* Set the low threshold */
-  hadc->Instance->LTR = AnalogWDGConfig->LowThreshold;
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_Exported_Functions_Group4 Peripheral State functions
- *  @brief    Peripheral State functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions to get in run-time the status of the  
-    peripheral.
-      (+) Check the ADC state
-      (+) Check the ADC error code
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the ADC state
-  * @param  hadc: ADC handle
-  * @retval HAL state
-  */
-HAL_ADC_StateTypeDef HAL_ADC_GetState(ADC_HandleTypeDef* hadc)
-{
-  /* Return ADC state */
-  return hadc->State;
-}
-
-/**
-  * @brief  Return the ADC error code
-  * @param  hadc: ADC handle
-  * @retval ADC Error Code
-  */
-uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc)
-{
-  return hadc->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Private_Functions ADC Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Enable the selected ADC.
-  * @note   Prerequisite condition to use this function: ADC must be disabled
-  *         and voltage regulator must be enabled (done into HAL_ADC_Init()).
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc)
-{
-  uint32_t wait_loop_index = 0;
-  uint32_t tickstart = 0;
-  
-  /* ADC enable and wait for ADC ready (in case of ADC is disabled or         */
-  /* enabling phase not yet completed: flag ADC ready not yet set).           */
-  /* Timeout implemented to not be stuck if ADC cannot be enabled (possible   */
-  /* causes: ADC clock not running, ...).                                     */
-  if (__HAL_ADC_IS_ENABLED(hadc) == RESET)
-  {
-    /* Enable the Peripheral */
-    __ADC_ENABLE(hadc);
-    
-    /* Delay for ADC stabilization time.                                      */
-    /* Delay fixed to worst case: maximum CPU frequency                       */
-    while(wait_loop_index < ADC_STAB_DELAY_CPU_CYCLES)
-    {
-      wait_loop_index++;
-    }
-    
-    /* Get timeout */
-    tickstart = HAL_GetTick();    
-
-    /* Wait for ADC effectively enabled */
-    while(__HAL_ADC_IS_ENABLED(hadc) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > ADC_ENABLE_TIMEOUT)
-      {
-        /* Update ADC state machine to error */
-        hadc->State = HAL_ADC_STATE_ERROR;
-      
-        /* Set ADC error code to ADC IP internal error */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
-        
-        /* Process unlocked */
-        __HAL_UNLOCK(hadc);
-      
-        return HAL_ERROR;
-      }
-    }
-  }
-   
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop ADC conversion and disable the selected ADC
-  * @note   Prerequisite condition to use this function: ADC conversions must be
-  *         stopped to disable the ADC.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc)
-{
-  uint32_t tickstart = 0;
-  
-  /* Verification if ADC is not already disabled:                             */
-  if (__HAL_ADC_IS_ENABLED(hadc) != RESET)
-  {
-    /* Disable the ADC peripheral */
-    __ADC_DISABLE(hadc);
-     
-    /* Get timeout */
-    tickstart = HAL_GetTick();
-    
-    /* Wait for ADC effectively disabled */    
-    while(__HAL_ADC_IS_ENABLED(hadc) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > ADC_DISABLE_TIMEOUT)
-      {
-        /* Update ADC state machine to error */
-        hadc->State = HAL_ADC_STATE_ERROR;
-        
-        /* Set ADC error code to ADC IP internal error */
-        hadc->ErrorCode |= HAL_ADC_ERROR_INTERNAL;
-        
-        return HAL_ERROR;
-      }
-    }
-  }
-  
-  /* Return HAL status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1107 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_adc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file containing functions prototypes of ADC HAL library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_ADC_H
-#define __STM32L1xx_HAL_ADC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"  
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup ADC_Exported_Types ADC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  Structure definition of ADC and regular group initialization 
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
-  *          - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
-  * @note   The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all parameters except 'Resolution', 'ScanConvMode', 'LowPowerAutoWait', 'LowPowerAutoPowerOff', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
-  *          - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
-  *         If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
-  *         without error reporting without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
-  */
-typedef struct
-{
-  uint32_t ClockPrescaler;        /*!< Select ADC clock source (asynchronous clock derived from HSI RC oscillator) and clock prescaler.
-                                       This parameter can be a value of @ref ADC_ClockPrescaler
-                                       Note: In case of usage of channels on injected group, ADC frequency should be low than AHB clock frequency /4 for resolution 12 or 10 bits, 
-                                             AHB clock frequency /3 for resolution 8 bits, AHB clock frequency /2 for resolution 6 bits.
-                                       Note: HSI RC oscillator must be preliminarily enabled at RCC top level. */
-  uint32_t Resolution;            /*!< Configures the ADC resolution. 
-                                       This parameter can be a value of @ref ADC_Resolution */
-  uint32_t DataAlign;             /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
-                                       or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
-                                       This parameter can be a value of @ref ADC_Data_align */
-  uint32_t ScanConvMode;          /*!< Configures the sequencer of regular and injected groups.
-                                       This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
-                                       If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
-                                                    Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
-                                       If enabled:  Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
-                                                    Scan direction is upward: from rank1 to rank 'n'.
-                                       This parameter can be a value of @ref ADC_Scan_mode */
-  uint32_t EOCSelection;          /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
-                                       This parameter can be a value of @ref ADC_EOCSelection.
-                                       Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
-                                             Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
-                                             or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
-                                       Note: If overrun feature is intending to be used in ADC mode 'interruption' (function HAL_ADC_Start_IT() ), parameter EOCSelection must be set to each conversion (this is not needed for ADC mode 'transfer by DMA', with function HAL_ADC_Start_DMA()) */
-  uint32_t LowPowerAutoWait;      /*!< Selects the dynamic low power Auto Delay: new conversion start only when the previous
-                                       conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
-                                       This feature automatically adapts the speed of ADC to the speed of the system that reads the data. Moreover, this avoids risk of overrun for low frequency applications. 
-                                       This parameter can be a value of @ref ADC_LowPowerAutoWait.
-                                       Note: Do not use with interruption or DMA (HAL_ADC_Start_IT(), HAL_ADC_Start_DMA()) since they have to clear immediately the EOC flag to free the IRQ vector sequencer.
-                                             Do use with polling: 1. Start conversion with HAL_ADC_Start(), 2. Later on, when conversion data is needed: use HAL_ADC_PollForConversion() to ensure that conversion is completed
-                                             and use HAL_ADC_GetValue() to retrieve conversion result and trig another conversion.
-                                       Note: ADC clock latency and some timing constraints depending on clock prescaler have to be taken into account: refer to reference manual (register ADC_CR2 bit DELS description). */
-  uint32_t LowPowerAutoPowerOff;  /*!< Selects the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
-                                       This feature can be combined with automatic wait mode (parameter 'LowPowerAutoWait').
-                                       This parameter can be a value of @ref ADC_LowPowerAutoPowerOff. */
-  uint32_t ChannelsBank;          /*!< Selects the ADC channels bank.
-                                       This parameter can be a value of @ref ADC_ChannelsBank.
-                                       Note: Banks availability depends on devices categories.
-                                       Note: To change bank selection on the fly, without going through execution of 'HAL_ADC_Init()', macro '__HAL_ADC_CHANNELS_BANK()' can be used directly. */
-  uint32_t ContinuousConvMode;    /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
-                                       after the selected trigger occurred (software start or external trigger).
-                                       This parameter can be set to ENABLE or DISABLE. */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
-                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 28. */
-#else
-  uint32_t NbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
-                                       To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 27. */
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                       Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                       Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                       This parameter can be set to ENABLE or DISABLE. */
-  uint32_t NbrOfDiscConversion;   /*!< Specifies the number of discontinuous conversions in which the  main sequence of regular group (parameter NbrOfConversion) will be subdivided.
-                                       If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
-                                       This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
-  uint32_t ExternalTrigConv;      /*!< Selects the external event used to trigger the conversion start of regular group.
-                                       If set to ADC_SOFTWARE_START, external triggers are disabled.
-                                       If set to external trigger source, triggering is on event rising edge.
-                                       This parameter can be a value of @ref ADC_External_trigger_source_Regular */
-  uint32_t ExternalTrigConvEdge;  /*!< Selects the external trigger edge of regular group.
-                                       If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
-                                       This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
-  uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
-                                       or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
-                                       Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
-                                       This parameter can be set to ENABLE or DISABLE.
-                                       Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could lauch a conversion). */
-}ADC_InitTypeDef;
-
-/** 
-  * @brief  Structure definition of ADC channel for regular group   
-  * @note   The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
-  *         ADC can be either disabled or enabled without conversion on going on regular group.
-  */ 
-typedef struct 
-{
-  uint32_t Channel;                /*!< Specifies the channel to configure into ADC regular group.
-                                        This parameter can be a value of @ref ADC_channels
-                                        Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability.
-                                              Maximum number of channels by device category (without taking in account each device package constraints): 
-                                              STM32L1 category 1, 2: 24 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26.
-                                              STM32L1 category 3:    25 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 26, 1 additional channel in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
-                                              STM32L1 category 4, 5: 40 channels on external pins + 3 channels on internal measurement paths (VrefInt, Temp sensor, Vcomp): Channel 0 to channel 31, 11 additional channels in bank B. Note: OPAMP1 and OPAMP2 are connected internally but not increasing internal channels number: they are sharing ADC input with external channels ADC_IN3 and ADC_IN8.
-                                        Note: In case of peripherals OPAMPx not used: 3 channels (3, 8, 13) can be configured as direct channels (fast channels). Refer to macro ' __HAL_ADC_CHANNEL_SPEED_FAST() '.
-                                        Note: In case of peripheral OPAMP3 and ADC channel OPAMP3 used (OPAMP3 available on STM32L1 devices Cat.4 only): the analog switch COMP1_SW1 must be closed. Refer to macro: ' __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1() '. */
-  uint32_t Rank;                   /*!< Specifies the rank in the regular group sequencer 
-                                        This parameter can be a value of @ref ADC_regular_rank
-                                        Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
-  uint32_t SamplingTime;           /*!< Sampling time value to be set for the selected channel.
-                                        Unit: ADC clock cycles
-                                        Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
-                                        This parameter can be a value of @ref ADC_sampling_times
-                                        Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                        Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                              sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                              Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
-}ADC_ChannelConfTypeDef;
-
-/**
-  * @brief  ADC Configuration analog watchdog definition
-  * @note   The setting of these parameters with function is conditioned to ADC state.
-  *         ADC state can be either disabled or enabled without conversion on going on regular and injected groups.
-  */
-typedef struct
-{
-  uint32_t WatchdogMode;      /*!< Configures the ADC analog watchdog mode: single/all channels, regular/injected group.
-                                   This parameter can be a value of @ref ADC_analog_watchdog_mode. */
-  uint32_t Channel;           /*!< Selects which ADC channel to monitor by analog watchdog.
-                                   This parameter has an effect only if watchdog mode is configured on single channel (parameter WatchdogMode)
-                                   This parameter can be a value of @ref ADC_channels. */
-  uint32_t ITMode;            /*!< Specifies whether the analog watchdog is configured in interrupt or polling mode.
-                                   This parameter can be set to ENABLE or DISABLE */
-  uint32_t HighThreshold;     /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-  uint32_t LowThreshold;      /*!< Configures the ADC analog watchdog High threshold value.
-                                   This parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF. */
-  uint32_t WatchdogNumber;    /*!< Reserved for future use, can be set to 0 */
-}ADC_AnalogWDGConfTypeDef;
-
-/** 
-  * @brief  HAL ADC state machine: ADC States structure definition  
-  */ 
-typedef enum
-{
-  HAL_ADC_STATE_RESET                   = 0x00,    /*!< ADC not yet initialized or disabled */
-  HAL_ADC_STATE_READY                   = 0x01,    /*!< ADC peripheral ready for use */
-  HAL_ADC_STATE_BUSY                    = 0x02,    /*!< An internal process is ongoing */ 
-  HAL_ADC_STATE_BUSY_REG                = 0x12,    /*!< Regular conversion is ongoing */
-  HAL_ADC_STATE_BUSY_INJ                = 0x22,    /*!< Injected conversion is ongoing */
-  HAL_ADC_STATE_BUSY_INJ_REG            = 0x32,    /*!< Injected and regular conversion are ongoing */
-  HAL_ADC_STATE_TIMEOUT                 = 0x03,    /*!< Timeout state */
-  HAL_ADC_STATE_ERROR                   = 0x04,    /*!< ADC state error */
-  HAL_ADC_STATE_EOC                     = 0x05,    /*!< Conversion is completed */
-  HAL_ADC_STATE_EOC_REG                 = 0x15,    /*!< Regular conversion is completed */
-  HAL_ADC_STATE_EOC_INJ                 = 0x25,    /*!< Injected conversion is completed */
-  HAL_ADC_STATE_EOC_INJ_REG             = 0x35,    /*!< Injected and regular conversion are completed */
-  HAL_ADC_STATE_AWD                     = 0x06,    /*!< ADC state analog watchdog */
-  HAL_ADC_STATE_AWD2                    = 0x07,    /*!< Not used on STM32L1xx devices (kept for compatibility with other devices featuring several AWD) */
-  HAL_ADC_STATE_AWD3                    = 0x08,    /*!< Not used on STM32l1xx devices (kept for compatibility with other devices featuring several AWD) */ 
-}HAL_ADC_StateTypeDef;
-
-/** 
-  * @brief  ADC handle Structure definition  
-  */ 
-typedef struct
-{
-  ADC_TypeDef                   *Instance;              /*!< Register base address */
-
-  ADC_InitTypeDef               Init;                   /*!< ADC required parameters */
-
-  __IO uint32_t                 NbrOfConversionRank ;   /*!< ADC conversion rank counter */
-
-  DMA_HandleTypeDef             *DMA_Handle;            /*!< Pointer DMA Handler */
-
-  HAL_LockTypeDef               Lock;                   /*!< ADC locking object */
-
-  __IO HAL_ADC_StateTypeDef     State;                  /*!< ADC communication state */
-
-  __IO uint32_t                 ErrorCode;              /*!< ADC Error code */
-}ADC_HandleTypeDef;
-/**
-  * @}
-  */
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Constants ADC Exported Constants
-  * @{
-  */
-
-/** @defgroup ADC_Error_Code ADC Error Code
-  * @{
-  */ 
-#define HAL_ADC_ERROR_NONE        ((uint32_t)0x00)   /*!< No error                                              */
-#define HAL_ADC_ERROR_INTERNAL    ((uint32_t)0x01)   /*!< ADC IP internal error: if problem of clocking, 
-                                                          enable/disable, erroneous state                       */
-#define HAL_ADC_ERROR_OVR         ((uint32_t)0x02)   /*!< Overrun error                                         */
-#define HAL_ADC_ERROR_DMA         ((uint32_t)0x04)   /*!< DMA transfer error                                    */
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_ClockPrescaler ADC ClockPrescaler
-  * @{
-  */
-#define ADC_CLOCK_ASYNC_DIV1          ((uint32_t)0x00000000)          /*!< ADC asynchronous clock derived from ADC dedicated HSI without prescaler */
-#define ADC_CLOCK_ASYNC_DIV2          ((uint32_t)ADC_CCR_ADCPRE_0)    /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 2 */
-#define ADC_CLOCK_ASYNC_DIV4          ((uint32_t)ADC_CCR_ADCPRE_1)    /*!< ADC asynchronous clock derived from ADC dedicated HSI divided by a prescaler of 4 */
-
-#define IS_ADC_CLOCKPRESCALER(ADC_CLOCK) (((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV1) || \
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV2) || \
-                                          ((ADC_CLOCK) == ADC_CLOCK_ASYNC_DIV4)   )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Resolution ADC Resolution
-  * @{
-  */
-#define ADC_RESOLUTION12b      ((uint32_t)0x00000000)          /*!<  ADC 12-bit resolution */
-#define ADC_RESOLUTION10b      ((uint32_t)ADC_CR1_RES_0)       /*!<  ADC 10-bit resolution */
-#define ADC_RESOLUTION8b       ((uint32_t)ADC_CR1_RES_1)       /*!<  ADC 8-bit resolution */
-#define ADC_RESOLUTION6b       ((uint32_t)ADC_CR1_RES)         /*!<  ADC 6-bit resolution */
-
-#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION12b) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION10b) || \
-                                       ((RESOLUTION) == ADC_RESOLUTION8b)  || \
-                                       ((RESOLUTION) == ADC_RESOLUTION6b)    )
-
-#define IS_ADC_RESOLUTION_8_6_BITS(RESOLUTION) (((RESOLUTION) == ADC_RESOLUTION8b) || \
-                                                ((RESOLUTION) == ADC_RESOLUTION6b)   )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Data_align ADC Data_align
-  * @{
-  */
-#define ADC_DATAALIGN_RIGHT      ((uint32_t)0x00000000)
-#define ADC_DATAALIGN_LEFT       ((uint32_t)ADC_CR2_ALIGN)
-
-#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DATAALIGN_RIGHT) || \
-                                  ((ALIGN) == ADC_DATAALIGN_LEFT)    )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Scan_mode ADC Scan mode
-  * @{
-  */
-#define ADC_SCAN_DISABLE         ((uint32_t)0x00000000)
-#define ADC_SCAN_ENABLE          ((uint32_t)0x00000001)
-
-#define IS_ADC_SCAN_MODE(SCAN_MODE) (((SCAN_MODE) == ADC_SCAN_DISABLE) || \
-                                     ((SCAN_MODE) == ADC_SCAN_ENABLE)    )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_External_trigger_edge_Regular ADC External trigger edge Regular
-  * @{
-  */
-#define ADC_EXTERNALTRIGCONVEDGE_NONE           ((uint32_t)0x00000000)
-#define ADC_EXTERNALTRIGCONVEDGE_RISING         ((uint32_t)ADC_CR2_EXTEN_0)         
-#define ADC_EXTERNALTRIGCONVEDGE_FALLING        ((uint32_t)ADC_CR2_EXTEN_1)
-#define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING  ((uint32_t)ADC_CR2_EXTEN)
-
-#define IS_ADC_EXTTRIG_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGCONVEDGE_NONE)         || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISING)       || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_FALLING)      || \
-                                   ((EDGE) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING)  )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_External_trigger_source_Regular ADC External trigger source Regular
-  * @{
-  */
-/* List of external triggers with generic trigger name, sorted by trigger     */
-/* name:                                                                      */
-
-/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIGCONV_T2_CC3      ADC_EXTERNALTRIG_T2_CC3
-#define ADC_EXTERNALTRIGCONV_T2_CC2      ADC_EXTERNALTRIG_T2_CC2
-#define ADC_EXTERNALTRIGCONV_T2_TRGO     ADC_EXTERNALTRIG_T2_TRGO
-#define ADC_EXTERNALTRIGCONV_T3_CC1      ADC_EXTERNALTRIG_T3_CC1
-#define ADC_EXTERNALTRIGCONV_T3_CC3      ADC_EXTERNALTRIG_T3_CC3
-#define ADC_EXTERNALTRIGCONV_T3_TRGO     ADC_EXTERNALTRIG_T3_TRGO
-#define ADC_EXTERNALTRIGCONV_T4_CC4      ADC_EXTERNALTRIG_T4_CC4
-#define ADC_EXTERNALTRIGCONV_T4_TRGO     ADC_EXTERNALTRIG_T4_TRGO
-#define ADC_EXTERNALTRIGCONV_T6_TRGO     ADC_EXTERNALTRIG_T6_TRGO
-#define ADC_EXTERNALTRIGCONV_T9_CC2      ADC_EXTERNALTRIG_T9_CC2
-#define ADC_EXTERNALTRIGCONV_T9_TRGO     ADC_EXTERNALTRIG_T9_TRGO
-#define ADC_EXTERNALTRIGCONV_EXT_IT11    ADC_EXTERNALTRIG_EXT_IT11
-
-#define ADC_SOFTWARE_START               ((uint32_t)0x00000010)
-
-#define IS_ADC_EXTTRIG(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC3)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_CC2)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T2_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC1)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_CC3)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T3_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_CC4)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T4_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T6_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_CC2)   || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_T9_TRGO)  || \
-                                 ((REGTRIG) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
-                                 ((REGTRIG) == ADC_SOFTWARE_START)              )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Internal_HAL_driver_Ext_trig_src_Regular ADC Internal HAL driver Ext trig src Regular
-  * @{
-  */
-
-/* List of external triggers of regular group for ADC1:                       */
-/* (used internally by HAL driver. To not use into HAL structure parameters)  */
-
-/* External triggers of regular group for ADC1 */
-#define ADC_EXTERNALTRIG_T9_CC2         ((uint32_t) 0x00000000)
-#define ADC_EXTERNALTRIG_T9_TRGO        ((uint32_t)(                                                         ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T2_CC3         ((uint32_t)(                                      ADC_CR2_EXTSEL_1                   ))
-#define ADC_EXTERNALTRIG_T2_CC2         ((uint32_t)(                                      ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T3_TRGO        ((uint32_t)(                   ADC_CR2_EXTSEL_2                                      ))
-#define ADC_EXTERNALTRIG_T4_CC4         ((uint32_t)(                   ADC_CR2_EXTSEL_2 |                    ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T2_TRGO        ((uint32_t)(                   ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1                   ))
-#define ADC_EXTERNALTRIG_T3_CC1         ((uint32_t)(                   ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T3_CC3         ((uint32_t)(ADC_CR2_EXTSEL_3                                                         ))
-#define ADC_EXTERNALTRIG_T4_TRGO        ((uint32_t)(ADC_CR2_EXTSEL_3                                       | ADC_CR2_EXTSEL_0))
-#define ADC_EXTERNALTRIG_T6_TRGO        ((uint32_t)(ADC_CR2_EXTSEL_3                    | ADC_CR2_EXTSEL_1                   ))
-#define ADC_EXTERNALTRIG_EXT_IT11       ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
-
-/**
-  * @}
-  */
-
-/** @defgroup ADC_EOCSelection ADC EOCSelection
-  * @{
-  */
-#define EOC_SEQ_CONV            ((uint32_t)0x00000000)
-#define EOC_SINGLE_CONV         ((uint32_t)ADC_CR2_EOCS)
-
-#define IS_ADC_EOC_SELECTION(EOC_SELECTION) (((EOC_SELECTION) == EOC_SINGLE_CONV)    || \
-                                             ((EOC_SELECTION) == EOC_SEQ_CONV)         )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LowPowerAutoWait ADC LowPowerAutoWait
-  * @{
-  */
-/*!< Note : For compatibility with other STM32 devices with ADC autowait      */
-/* feature limited to enable or disable settings:                             */
-/* Setting "ADC_AUTOWAIT_UNTIL_DATA_READ" is equivalent to "ENABLE".          */
-
-#define ADC_AUTOWAIT_DISABLE                ((uint32_t)0x00000000)
-#define ADC_AUTOWAIT_UNTIL_DATA_READ        ((uint32_t)(                                  ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: infinite delay, until the result of previous conversion is read */
-#define ADC_AUTOWAIT_7_APBCLOCKCYCLES       ((uint32_t)(                 ADC_CR2_DELS_1                 )) /*!< Insert a delay between ADC conversions: 7 APB clock cycles */
-#define ADC_AUTOWAIT_15_APBCLOCKCYCLES      ((uint32_t)(                 ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 15 APB clock cycles */
-#define ADC_AUTOWAIT_31_APBCLOCKCYCLES      ((uint32_t)(ADC_CR2_DELS_2                                  )) /*!< Insert a delay between ADC conversions: 31 APB clock cycles */
-#define ADC_AUTOWAIT_63_APBCLOCKCYCLES      ((uint32_t)(ADC_CR2_DELS_2                  | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 63 APB clock cycles */
-#define ADC_AUTOWAIT_127_APBCLOCKCYCLES     ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1                 )) /*!< Insert a delay between ADC conversions: 127 APB clock cycles */
-#define ADC_AUTOWAIT_255_APBCLOCKCYCLES     ((uint32_t)(ADC_CR2_DELS_2 | ADC_CR2_DELS_1 | ADC_CR2_DELS_0)) /*!< Insert a delay between ADC conversions: 255 APB clock cycles */
-
-#define IS_ADC_AUTOWAIT(AUTOWAIT) (((AUTOWAIT) == ADC_AUTOWAIT_DISABLE)            || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_UNTIL_DATA_READ)    || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_7_APBCLOCKCYCLES)   || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_15_APBCLOCKCYCLES)  || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_31_APBCLOCKCYCLES)  || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_63_APBCLOCKCYCLES)  || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_127_APBCLOCKCYCLES) || \
-                                   ((AUTOWAIT) == ADC_AUTOWAIT_255_APBCLOCKCYCLES)   )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_LowPowerAutoPowerOff ADC LowPowerAutoPowerOff
-  * @{
-  */
-#define ADC_AUTOPOWEROFF_DISABLE            ((uint32_t)0x00000000)
-#define ADC_AUTOPOWEROFF_IDLE_PHASE         ((uint32_t)ADC_CR1_PDI)                     /*!< ADC power off when ADC is not converting (idle phase) */
-#define ADC_AUTOPOWEROFF_DELAY_PHASE        ((uint32_t)ADC_CR1_PDD)                     /*!< ADC power off when a delay is inserted between conversions (see parameter ADC_LowPowerAutoWait) */
-#define ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES  ((uint32_t)(ADC_CR1_PDI | ADC_CR1_PDD))     /*!< ADC power off when ADC is not converting (idle phase) and when a delay is inserted between conversions */
-
-#define IS_ADC_AUTOPOWEROFF(AUTOPOWEROFF) (((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DISABLE)          || \
-                                           ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_PHASE)       || \
-                                           ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_DELAY_PHASE)      || \
-                                           ((AUTOPOWEROFF) == ADC_AUTOPOWEROFF_IDLE_DELAY_PHASES)  )
-/**
-  * @}
-  */
-
-
-/** @defgroup ADC_ChannelsBank ADC ChannelsBank
-  * @{
-  */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define ADC_CHANNELS_BANK_A                 ((uint32_t)0x00000000)
-#define ADC_CHANNELS_BANK_B                 ((uint32_t)ADC_CR2_CFG)
-
-#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A) || \
-                                   ((BANK) == ADC_CHANNELS_BANK_B)   )
-#else
-#define ADC_CHANNELS_BANK_A                 ((uint32_t)0x00000000)
-
-#define IS_ADC_CHANNELSBANK(BANK) (((BANK) == ADC_CHANNELS_BANK_A))
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_channels ADC channels
-  * @{
-  */
-/* Note: Depending on devices, some channels may not be available on package  */
-/*       pins. Refer to device datasheet for channels availability.           */
-#define ADC_CHANNEL_0           ((uint32_t)0x00000000)                                                                            /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_1           ((uint32_t)(                                                                    ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_2           ((uint32_t)(                                                   ADC_SQR5_SQ1_1                 ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_3           ((uint32_t)(                                                   ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_4           ((uint32_t)(                                  ADC_SQR5_SQ1_2                                  ))  /* Direct (fast) channel */
-#define ADC_CHANNEL_5           ((uint32_t)(                                  ADC_SQR5_SQ1_2                  | ADC_SQR5_SQ1_0))  /* Direct (fast) channel */
-#define ADC_CHANNEL_6           ((uint32_t)(                                  ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1                 ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_7           ((uint32_t)(                                  ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_8           ((uint32_t)(                 ADC_SQR5_SQ1_3                                                   ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_9           ((uint32_t)(                 ADC_SQR5_SQ1_3                                   | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_10          ((uint32_t)(                 ADC_SQR5_SQ1_3                  | ADC_SQR5_SQ1_1                 ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_11          ((uint32_t)(                 ADC_SQR5_SQ1_3                  | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_12          ((uint32_t)(                 ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2                                  ))  /* Channel different in bank A and bank B */
-#define ADC_CHANNEL_13          ((uint32_t)(                 ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2                  | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_14          ((uint32_t)(                 ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1                 ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_15          ((uint32_t)(                 ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_16          ((uint32_t)(ADC_SQR5_SQ1_4                                                                    ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_17          ((uint32_t)(ADC_SQR5_SQ1_4                                                    | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_18          ((uint32_t)(ADC_SQR5_SQ1_4                                   | ADC_SQR5_SQ1_1                 ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_19          ((uint32_t)(ADC_SQR5_SQ1_4                                   | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_20          ((uint32_t)(ADC_SQR5_SQ1_4                  | ADC_SQR5_SQ1_2                                  ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_21          ((uint32_t)(ADC_SQR5_SQ1_4                  | ADC_SQR5_SQ1_2                  | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_22          ((uint32_t)(ADC_SQR5_SQ1_4                  | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1                 ))  /* Direct (fast) channel */
-#define ADC_CHANNEL_23          ((uint32_t)(ADC_SQR5_SQ1_4                  | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Direct (fast) channel */
-#define ADC_CHANNEL_24          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3                                                   ))  /* Direct (fast) channel */
-#define ADC_CHANNEL_25          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3                                   | ADC_SQR5_SQ1_0))  /* Direct (fast) channel */
-#define ADC_CHANNEL_26          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3                  | ADC_SQR5_SQ1_1                 ))  /* Channel common to both bank A and bank B */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define ADC_CHANNEL_27          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3                  | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_28          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2                                  ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_29          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2                  | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_30          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1                 ))  /* Channel common to both bank A and bank B */
-#define ADC_CHANNEL_31          ((uint32_t)(ADC_SQR5_SQ1_4 | ADC_SQR5_SQ1_3 | ADC_SQR5_SQ1_2 | ADC_SQR5_SQ1_1 | ADC_SQR5_SQ1_0))  /* Channel common to both bank A and bank B */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#define ADC_CHANNEL_TEMPSENSOR  ADC_CHANNEL_16  /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
-#define ADC_CHANNEL_VREFINT     ADC_CHANNEL_17  /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
-#define ADC_CHANNEL_VCOMP       ADC_CHANNEL_26  /* ADC internal channel (no connection on device pin). Channel common to both bank A and bank B. */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define ADC_CHANNEL_VOPAMP1     ADC_CHANNEL_3   /* Internal connection from OPAMP1 output to ADC switch matrix */
-#define ADC_CHANNEL_VOPAMP2     ADC_CHANNEL_8   /* Internal connection from OPAMP2 output to ADC switch matrix */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD)
-#define ADC_CHANNEL_VOPAMP3     ADC_CHANNEL_13  /* Internal connection from OPAMP3 output to ADC switch matrix */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_17)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_18)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_19)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_20)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_21)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_22)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_23)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_24)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_25)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_26)            )
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_CHANNEL_0)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_1)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_2)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_3)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_4)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_5)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_6)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_7)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_8)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_9)           || \
-                                 ((CHANNEL) == ADC_CHANNEL_10)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_11)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_12)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_13)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_14)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_15)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_16)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_17)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_18)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_19)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_20)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_21)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_22)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_23)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_24)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_25)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_26)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_27)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_28)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_29)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_30)          || \
-                                 ((CHANNEL) == ADC_CHANNEL_31)            )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times ADC sampling times
-  * @{
-  */
-#define ADC_SAMPLETIME_4CYCLES      ((uint32_t)0x00000000)                            /*!< Sampling time 4 ADC clock cycles */
-#define ADC_SAMPLETIME_9CYCLES      ((uint32_t) ADC_SMPR3_SMP0_0)                     /*!< Sampling time 9 ADC clock cycles */
-#define ADC_SAMPLETIME_16CYCLES     ((uint32_t) ADC_SMPR3_SMP0_1)                     /*!< Sampling time 16 ADC clock cycles */
-#define ADC_SAMPLETIME_24CYCLES     ((uint32_t)(ADC_SMPR3_SMP0_1 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 24 ADC clock cycles */
-#define ADC_SAMPLETIME_48CYCLES     ((uint32_t) ADC_SMPR3_SMP0_2)                     /*!< Sampling time 48 ADC clock cycles */
-#define ADC_SAMPLETIME_96CYCLES     ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_0)) /*!< Sampling time 96 ADC clock cycles */
-#define ADC_SAMPLETIME_192CYCLES    ((uint32_t)(ADC_SMPR3_SMP0_2 | ADC_SMPR3_SMP0_1)) /*!< Sampling time 192 ADC clock cycles */
-#define ADC_SAMPLETIME_384CYCLES    ((uint32_t) ADC_SMPR3_SMP0)                       /*!< Sampling time 384 ADC clock cycles */
-
-#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SAMPLETIME_4CYCLES)   || \
-                                  ((TIME) == ADC_SAMPLETIME_9CYCLES)   || \
-                                  ((TIME) == ADC_SAMPLETIME_16CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_24CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_48CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_96CYCLES)  || \
-                                  ((TIME) == ADC_SAMPLETIME_192CYCLES) || \
-                                  ((TIME) == ADC_SAMPLETIME_384CYCLES)   )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_sampling_times_all_channels ADC sampling times all channels
-  * @{
-  */
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2                                          \
-     (ADC_SMPR3_SMP9_2 | ADC_SMPR3_SMP8_2 | ADC_SMPR3_SMP7_2 | ADC_SMPR3_SMP6_2 |     \
-      ADC_SMPR3_SMP5_2 | ADC_SMPR3_SMP4_2 | ADC_SMPR3_SMP3_2 | ADC_SMPR3_SMP2_2 |     \
-      ADC_SMPR3_SMP1_2 | ADC_SMPR3_SMP0_2)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2                                          \
-     (ADC_SMPR2_SMP19_2 | ADC_SMPR2_SMP18_2 | ADC_SMPR2_SMP17_2 | ADC_SMPR2_SMP16_2 | \
-      ADC_SMPR2_SMP15_2 | ADC_SMPR2_SMP14_2 | ADC_SMPR2_SMP13_2 | ADC_SMPR2_SMP12_2 | \
-      ADC_SMPR2_SMP11_2 | ADC_SMPR2_SMP10_2)
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2                                          \
-     (ADC_SMPR1_SMP26_2 | ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | \
-      ADC_SMPR1_SMP22_2 | ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2                                          \
-     (ADC_SMPR1_SMP29_2 | ADC_SMPR1_SMP28_2 | ADC_SMPR1_SMP27_2 | ADC_SMPR1_SMP26_2 | \
-      ADC_SMPR1_SMP25_2 | ADC_SMPR1_SMP24_2 | ADC_SMPR1_SMP23_2 | ADC_SMPR1_SMP22_2 | \
-      ADC_SMPR1_SMP21_2 | ADC_SMPR1_SMP20_2)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2                                          \
-     (ADC_SMPR0_SMP31_2 | ADC_SMPR0_SMP30_2 )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-       
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT1                                          \
-     (ADC_SMPR3_SMP9_1 | ADC_SMPR3_SMP8_1 | ADC_SMPR3_SMP7_1 | ADC_SMPR3_SMP6_1 |     \
-      ADC_SMPR3_SMP5_1 | ADC_SMPR3_SMP4_1 | ADC_SMPR3_SMP3_1 | ADC_SMPR3_SMP2_1 |     \
-      ADC_SMPR3_SMP1_1 | ADC_SMPR3_SMP0_1)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT1                                          \
-     (ADC_SMPR2_SMP19_1 | ADC_SMPR2_SMP18_1 | ADC_SMPR2_SMP17_1 | ADC_SMPR2_SMP16_1 | \
-      ADC_SMPR2_SMP15_1 | ADC_SMPR2_SMP14_1 | ADC_SMPR2_SMP13_1 | ADC_SMPR2_SMP12_1 | \
-      ADC_SMPR2_SMP11_1 | ADC_SMPR2_SMP10_1)
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1                                          \
-     (ADC_SMPR1_SMP26_1 | ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | \
-      ADC_SMPR1_SMP22_1 | ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT1                                          \
-     (ADC_SMPR1_SMP29_1 | ADC_SMPR1_SMP28_1 | ADC_SMPR1_SMP27_1 | ADC_SMPR1_SMP26_1 | \
-      ADC_SMPR1_SMP25_1 | ADC_SMPR1_SMP24_1 | ADC_SMPR1_SMP23_1 | ADC_SMPR1_SMP22_1 | \
-      ADC_SMPR1_SMP21_1 | ADC_SMPR1_SMP20_1)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT1                                          \
-     (ADC_SMPR0_SMP31_1 | ADC_SMPR0_SMP30_1 )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-       
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT0                                          \
-     (ADC_SMPR3_SMP9_0 | ADC_SMPR3_SMP8_0 | ADC_SMPR3_SMP7_0 | ADC_SMPR3_SMP6_0 |     \
-      ADC_SMPR3_SMP5_0 | ADC_SMPR3_SMP4_0 | ADC_SMPR3_SMP3_0 | ADC_SMPR3_SMP2_0 |     \
-      ADC_SMPR3_SMP1_0 | ADC_SMPR3_SMP0_0)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT0                                          \
-     (ADC_SMPR2_SMP19_0 | ADC_SMPR2_SMP18_0 | ADC_SMPR2_SMP17_0 | ADC_SMPR2_SMP16_0 | \
-      ADC_SMPR2_SMP15_0 | ADC_SMPR2_SMP14_0 | ADC_SMPR2_SMP13_0 | ADC_SMPR2_SMP12_0 | \
-      ADC_SMPR2_SMP11_0 | ADC_SMPR2_SMP10_0)
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0                                          \
-     (ADC_SMPR1_SMP26_0 | ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | \
-      ADC_SMPR1_SMP22_0 | ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT0                                          \
-     (ADC_SMPR1_SMP29_0 | ADC_SMPR1_SMP28_0 | ADC_SMPR1_SMP27_0 | ADC_SMPR1_SMP26_0 | \
-      ADC_SMPR1_SMP25_0 | ADC_SMPR1_SMP24_0 | ADC_SMPR1_SMP23_0 | ADC_SMPR1_SMP22_0 | \
-      ADC_SMPR1_SMP21_0 | ADC_SMPR1_SMP20_0)
-#define ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT0                                          \
-     (ADC_SMPR0_SMP31_0 | ADC_SMPR0_SMP30_0 )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_rank ADC regular rank
-  * @{
-  */
-#define ADC_REGULAR_RANK_1    ((uint32_t)0x00000001)
-#define ADC_REGULAR_RANK_2    ((uint32_t)0x00000002)
-#define ADC_REGULAR_RANK_3    ((uint32_t)0x00000003)
-#define ADC_REGULAR_RANK_4    ((uint32_t)0x00000004)
-#define ADC_REGULAR_RANK_5    ((uint32_t)0x00000005)
-#define ADC_REGULAR_RANK_6    ((uint32_t)0x00000006)
-#define ADC_REGULAR_RANK_7    ((uint32_t)0x00000007)
-#define ADC_REGULAR_RANK_8    ((uint32_t)0x00000008)
-#define ADC_REGULAR_RANK_9    ((uint32_t)0x00000009)
-#define ADC_REGULAR_RANK_10   ((uint32_t)0x0000000A)
-#define ADC_REGULAR_RANK_11   ((uint32_t)0x0000000B)
-#define ADC_REGULAR_RANK_12   ((uint32_t)0x0000000C)
-#define ADC_REGULAR_RANK_13   ((uint32_t)0x0000000D)
-#define ADC_REGULAR_RANK_14   ((uint32_t)0x0000000E)
-#define ADC_REGULAR_RANK_15   ((uint32_t)0x0000000F)
-#define ADC_REGULAR_RANK_16   ((uint32_t)0x00000010)
-#define ADC_REGULAR_RANK_17   ((uint32_t)0x00000011)
-#define ADC_REGULAR_RANK_18   ((uint32_t)0x00000012)
-#define ADC_REGULAR_RANK_19   ((uint32_t)0x00000013)
-#define ADC_REGULAR_RANK_20   ((uint32_t)0x00000014)
-#define ADC_REGULAR_RANK_21   ((uint32_t)0x00000015)
-#define ADC_REGULAR_RANK_22   ((uint32_t)0x00000016)
-#define ADC_REGULAR_RANK_23   ((uint32_t)0x00000017)
-#define ADC_REGULAR_RANK_24   ((uint32_t)0x00000018)
-#define ADC_REGULAR_RANK_25   ((uint32_t)0x00000019)
-#define ADC_REGULAR_RANK_26   ((uint32_t)0x0000001A)
-#define ADC_REGULAR_RANK_27   ((uint32_t)0x0000001B)
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define ADC_REGULAR_RANK_28   ((uint32_t)0x0000001C)
-       
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_10) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_11) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_12) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_13) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_14) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_15) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_16) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_17) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_18) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_19) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_20) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_21) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_22) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_23) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_24) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_25) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_26) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_27) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_28)   )
-#else
-
-#define IS_ADC_REGULAR_RANK(CHANNEL) (((CHANNEL) == ADC_REGULAR_RANK_1 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_2 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_3 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_4 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_5 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_6 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_7 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_8 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_9 ) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_10) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_11) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_12) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_13) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_14) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_15) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_16) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_17) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_18) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_19) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_20) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_21) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_22) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_23) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_24) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_25) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_26) || \
-                                      ((CHANNEL) == ADC_REGULAR_RANK_27)   )
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_analog_watchdog_mode ADC analog watchdog mode
-  * @{
-  */
-#define ADC_ANALOGWATCHDOG_NONE                 ((uint32_t)0x00000000)
-#define ADC_ANALOGWATCHDOG_SINGLE_REG           ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_INJEC         ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC      ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-#define ADC_ANALOGWATCHDOG_ALL_REG              ((uint32_t) ADC_CR1_AWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_INJEC            ((uint32_t) ADC_CR1_JAWDEN)
-#define ADC_ANALOGWATCHDOG_ALL_REGINJEC         ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
-
-#define IS_ADC_ANALOG_WATCHDOG_MODE(WATCHDOG) (((WATCHDOG) == ADC_ANALOGWATCHDOG_NONE)             || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REG)       || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_INJEC)     || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC)  || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REG)          || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_INJEC)        || \
-                                               ((WATCHDOG) == ADC_ANALOGWATCHDOG_ALL_REGINJEC)       )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_conversion_group ADC conversion group
-  * @{
-  */
-#define REGULAR_GROUP             ((uint32_t)(ADC_FLAG_EOC))
-#define INJECTED_GROUP            ((uint32_t)(ADC_FLAG_JEOC))
-#define REGULAR_INJECTED_GROUP    ((uint32_t)(ADC_FLAG_EOC | ADC_FLAG_JEOC))
-
-#define IS_ADC_CONVERSION_GROUP(CONVERSION) (((CONVERSION) == REGULAR_GROUP)         || \
-                                             ((CONVERSION) == INJECTED_GROUP)        || \
-                                             ((CONVERSION) == REGULAR_INJECTED_GROUP)  )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_Event_type ADC Event type
-  * @{
-  */
-#define AWD_EVENT               ((uint32_t)ADC_FLAG_AWD)   /*!< ADC Analog watchdog event */
-#define OVR_EVENT               ((uint32_t)ADC_FLAG_OVR)   /*!< ADC overrun event */
-
-#define IS_ADC_EVENT_TYPE(EVENT) (((EVENT) == AWD_EVENT)  || \
-                                  ((EVENT) == ADC_FLAG_OVR) )
-/**
-  * @}
-  */
-
-/** @defgroup ADC_interrupts_definition ADC interrupts definition
-  * @{
-  */
-#define ADC_IT_EOC           ADC_CR1_EOCIE        /*!< ADC End of Regular Conversion interrupt source */
-#define ADC_IT_JEOC          ADC_CR1_JEOCIE       /*!< ADC End of Injected Conversion interrupt source */
-#define ADC_IT_AWD           ADC_CR1_AWDIE        /*!< ADC Analog watchdog interrupt source */
-#define ADC_IT_OVR           ADC_CR1_OVRIE        /*!< ADC overrun interrupt source */
-/**
-  * @}
-  */
-
-/** @defgroup ADC_flags_definition ADC flags definition
-  * @{
-  */
-#define ADC_FLAG_AWD           ADC_SR_AWD      /*!< ADC Analog watchdog flag */
-#define ADC_FLAG_EOC           ADC_SR_EOC      /*!< ADC End of Regular conversion flag */
-#define ADC_FLAG_JEOC          ADC_SR_JEOC     /*!< ADC End of Injected conversion flag */
-#define ADC_FLAG_JSTRT         ADC_SR_JSTRT    /*!< ADC Injected group start flag */
-#define ADC_FLAG_STRT          ADC_SR_STRT     /*!< ADC Regular group start flag */
-#define ADC_FLAG_OVR           ADC_SR_OVR      /*!< ADC overrun flag */
-#define ADC_FLAG_ADONS         ADC_SR_ADONS    /*!< ADC ready status flag */
-#define ADC_FLAG_RCNR          ADC_SR_RCNR     /*!< ADC Regular group ready status flag */
-#define ADC_FLAG_JCNR          ADC_SR_JCNR     /*!< ADC Regular group ready status flag */
-
-/* Combination of all post-conversion flags bits: EOC/EOS, JEOC/JEOS, OVR, AWDx */
-#define ADC_FLAG_POSTCONV_ALL   (ADC_FLAG_EOC | ADC_FLAG_JEOC | ADC_FLAG_AWD | \
-                                 ADC_FLAG_OVR)
-/**
-  * @}
-  */
-
-/** @defgroup ADC_range_verification ADC range verification
-  * For a unique ADC resolution: 12 bits
-  * @{
-  */
-#define IS_ADC_RANGE(ADC_VALUE) ((ADC_VALUE) <= ((uint32_t)0x0FFF))
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_nb_conv_verification ADC regular nb conv verification
-  * @{
-  */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)28)))
-#else
-#define IS_ADC_REGULAR_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)27)))
-#endif
-/**
-  * @}
-  */
-
-/** @defgroup ADC_regular_discontinuous_mode_number_verification ADC regular discontinuous mode number verification
-  * @{
-  */
-#define IS_ADC_REGULAR_DISCONT_NUMBER(NUMBER) (((NUMBER) >= ((uint32_t)1)) && ((NUMBER) <= ((uint32_t)8)))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADC_Exported_Macros ADC Exported Macros
-  * @{
-  */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user.                                                                */
-
-/**
-  * @brief Verification of ADC state: enabled or disabled
-  * @param __HANDLE__: ADC handle
-  * @retval SET (ADC enabled) or RESET (ADC disabled)
-  */
-#define __HAL_ADC_IS_ENABLED(__HANDLE__)                                       \
-       ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS )       \
-        ) ? SET : RESET)
-
-/**
-  * @brief Test if conversion trigger of regular group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define __HAL_ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__)                        \
-       (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
-
-/**
-  * @brief Test if conversion trigger of injected group is software start
-  *        or external trigger.
-  * @param __HANDLE__: ADC handle
-  * @retval SET (software start) or RESET (external trigger)
-  */
-#define __HAL_ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__)                       \
-       (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
-
-/** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC interrupt source to check
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                     \
-    (( ((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)      \
-     )? SET : RESET                                                            \
-    )
-         
-/**
-  * @brief Enable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
-  * @retval None
-  */
-#define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                         \
-  (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/**
-  * @brief Disable the ADC end of conversion interrupt.
-  * @param __HANDLE__: ADC handle
-  * @param __INTERRUPT__: ADC Interrupt
-  * @retval None
-  */
-#define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                        \
-  (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
-
-/**
-  * @brief Get the selected ADC's flag status.
-  * @param __HANDLE__: ADC handle
-  * @param __FLAG__: ADC flag
-  * @retval None
-  */
-#define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__)                               \
-  ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief Clear the ADC's pending flags
-  * @param __HANDLE__: ADC handle
-  * @param __FLAG__: ADC flag
-  * @retval None
-  */
-#define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-
-/**
-  * @brief Clear ADC error code (set it to error code: "no error")
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_CLEAR_ERRORCODE(__HANDLE__)                                  \
-  ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
-
-/** @brief  Reset ADC handle state
-  * @param  __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
-      
-/**
-  * @}
-  */
-
-/* Include ADC HAL Extension module */
-#include "stm32l1xx_hal_adc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup ADC_Exported_Functions_Group1
-  * @{
-  */
-
-
-/* Initialization and de-initialization functions  **********************************/
-HAL_StatusTypeDef       HAL_ADC_Init(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
-void                    HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */
-
-/* IO operation functions  *****************************************************/
-
-/** @addtogroup ADC_Exported_Functions_Group2
-  * @{
-  */
-
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADC_Start(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-HAL_StatusTypeDef       HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
-
-/* Non-blocking mode: DMA */
-HAL_StatusTypeDef       HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
-HAL_StatusTypeDef       HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption and DMA) */
-void                    HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
-void                    HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup ADC_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef       HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
-HAL_StatusTypeDef       HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
-/**
-  * @}
-  */
-
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup ADC_Exported_Functions_Group4
-  * @{
-  */
-HAL_ADC_StateTypeDef    HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
-uint32_t                HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/* Internal HAL driver functions **********************************************/
-/** @addtogroup ADC_Private_Functions
-  * @{
-  */
-
-HAL_StatusTypeDef ADC_Enable(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef ADC_ConversionStop_Disable(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_ADC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,849 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_adc_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   This file provides firmware functions to manage the following 
-  *          functionalities of the Analog to Digital Convertor (ADC)
-  *          peripheral:
-  *           + Initialization and de-initialization functions
-  *             ++ Initialization and Configuration of ADC
-  *           + Operation functions
-  *             ++ Start, stop, get result of conversions of regular
-  *             group, using 3 possible modes: polling, interruption or DMA.
-  *           + Control functions
-  *             ++ Analog Watchdog configuration
-  *             ++ Channels configuration on regular group
-  *           + State functions
-  *             ++ ADC state machine management
-  *             ++ Interrupts and flags management
-  *          Other functions (generic functions) are available in file 
-  *          "stm32l1xx_hal_adc.c".
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-
-     (#) Activate the ADC peripheral using one of the start functions: 
-         HAL_ADCEx_InjectedStart(), HAL_ADCEx_InjectedStart_IT().
-    
-     *** Channels configuration to injected group ***
-     ================================================    
-     [..]
-       (+) To configure the ADC Injected channels group features, use 
-           HAL_ADCEx_InjectedConfigChannel() functions.
-       (+) To activate the continuous mode, use the HAL_ADC_Init() function.
-       (+) To read the ADC converted values, use the HAL_ADCEx_InjectedGetValue() 
-           function.
-  
-    @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup ADCEx ADCEx
-  * @brief ADC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_ADC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup ADCEx_Private_Constants ADCEx Private Constants
-  * @{
-  */
-
-  /* ADC conversion cycles (unit: ADC clock cycles)                           */
-  /* (selected sampling time + conversion time of 12 ADC clock cycles, with   */
-  /* resolution 12 bits)                                                      */
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_4CYCLE5   ((uint32_t) 16)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_9CYCLES   ((uint32_t) 21)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_16CYCLES  ((uint32_t) 28)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES  ((uint32_t) 36)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_48CYCLES  ((uint32_t) 60)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_96CYCLES  ((uint32_t)108)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_192CYCLES ((uint32_t)204)
-  #define ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES ((uint32_t)396)
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Functions ADCEx Exported Functions
-  * @{
-  */
-
-/** @defgroup ADCEx_Exported_Functions_Group1 Extended Initialization/de-initialization functions 
- *  @brief    Extended Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Start conversion of injected group.
-      (+) Stop conversion of injected group.
-      (+) Poll for conversion complete on injected group.
-      (+) Get result of injected channel conversion.
-      (+) Start conversion of injected group and enable interruptions.
-      (+) Stop conversion of injected group and disable interruptions.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables ADC, starts conversion of injected group.
-  *         Interruptions enabled in this function: None.
-  * @param  hadc: ADC handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Enable the ADC peripheral */
-  tmpHALStatus = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* Check if a regular conversion is ongoing */
-    if(hadc->State == HAL_ADC_STATE_BUSY_REG)
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;
-    }
-    else
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_INJ;
-    }
-    
-    /* Set ADC error code to none */
-    __HAL_ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Clear injected group conversion flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-    
-    /* Start conversion of injected group if software start has been selected */
-    /* and if automatic injected conversion is disabled.                      */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    /* If automatic injected conversion is enabled, conversion will start     */
-    /* after next regular group conversion.                                   */
-    if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc)        && 
-        HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)  )
-    {
-      /* Enable ADC software conversion for injected channels */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART);
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Stop conversion of injected channels. Disable ADC peripheral if
-  *         no regular conversion is on going.
-  * @note   If ADC must be disabled with this function and if regular conversion
-  *         is on going, function HAL_ADC_Stop must be used preliminarily.
-  * @note   In case of auto-injection mode, HAL_ADC_Stop must be used.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Stop potential conversion and disable ADC peripheral                     */
-  /* Conditioned to:                                                          */
-  /* - No conversion on the other group (regular group) is intended to        */
-  /*   continue (injected and regular groups stop conversion and ADC disable  */
-  /*   are common)                                                            */
-  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */
-    if((hadc->State != HAL_ADC_STATE_BUSY_REG)            &&
-       (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG)        &&
-       HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
-    /* Stop potential conversion on going, on regular and injected groups */
-    /* Disable ADC peripheral */
-    tmpHALStatus = ADC_ConversionStop_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmpHALStatus != HAL_ERROR)
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_READY;
-    }
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    hadc->State = HAL_ADC_STATE_ERROR;
-      
-    tmpHALStatus = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Wait for injected group conversion to be completed.
-  * @param  hadc: ADC handle
-  * @param  Timeout: Timeout value in millisecond.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout)
-{
-  uint32_t tickstart;
-
-  /* Variables for polling in case of scan mode enabled and polling for each  */
-  /* conversion.                                                              */
-  /* Note: Variable "conversion_timeout_cpu_cycles" set to offset 28 CPU      */
-  /* cycles to compensate number of CPU cycles for processing of variable     */
-  /* "conversion_timeout_cpu_cycles_max"                                      */
-  uint32_t conversion_timeout_cpu_cycles = 28;
-  uint32_t conversion_timeout_cpu_cycles_max = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Get timeout */
-  tickstart = HAL_GetTick();  
-     
-  /* Polling for end of conversion: differentiation if single/sequence        */
-  /* conversion.                                                              */
-  /* For injected group, flag JEOC is set only at the end of the sequence,    */
-  /* not for each conversion within the sequence.                             */
-  /* If setting "EOCSelection" is set to poll for each single conversion,     */
-  /* management of polling depends on setting of injected group sequencer:    */ 
-  /*  - If single conversion for injected group (scan mode disabled or        */
-  /*    InjectedNbrOfConversion ==1), flag JEOC is used to determine the      */
-  /*    conversion completion.                                                */
-  /*  - If sequence conversion for injected group (scan mode enabled and      */
-  /*    InjectedNbrOfConversion >=2), flag JEOC is set only at the end of the */
-  /*    sequence.                                                             */
-  /*    To poll for each conversion, the maximum conversion time is computed  */
-  /*    from ADC conversion time (selected sampling time + conversion time of */
-  /*    12 ADC clock cycles) and APB2/ADC clock prescalers (depending on      */
-  /*    settings, conversion time range can vary from 8 to several thousands  */
-  /*    of CPU cycles).                                                       */
-
-  /* Note: On STM32L1, setting "EOCSelection" is related to regular group     */
-  /*       only, by hardware. For compatibility with other STM32 devices,     */
-  /*       this setting is related also to injected group by software.        */
-  if (((hadc->Instance->JSQR & ADC_JSQR_JL) == RESET) ||
-      (hadc->Init.EOCSelection != EOC_SINGLE_CONV)      )
-  {
-    /* Wait until End of Conversion flag is raised */
-    while(HAL_IS_BIT_CLR(hadc->Instance->SR, ADC_FLAG_JEOC))
-    {
-      /* Check if timeout is disabled (set to infinite wait) */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Update ADC state machine to timeout */
-          hadc->State = HAL_ADC_STATE_TIMEOUT;
-          
-          /* Process unlocked */
-          __HAL_UNLOCK(hadc);
-          
-          return HAL_ERROR;
-        }
-      }
-    }
-  }
-  else
-  {
-    /* Computation of CPU cycles corresponding to ADC conversion cycles.      */
-    /* Retrieve ADC clock prescaler and ADC maximum conversion cycles on all  */
-    /* channels.                                                              */
-    conversion_timeout_cpu_cycles_max = __ADC_GET_CLOCK_PRESCALER_DECIMAL(hadc);
-    conversion_timeout_cpu_cycles_max *= __ADC_CONVCYCLES_MAX_RANGE(hadc);
-
-    /* Poll with maximum conversion time */
-    while(conversion_timeout_cpu_cycles < conversion_timeout_cpu_cycles_max)
-    {
-      /* Check if timeout is disabled (set to infinite wait) */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Update ADC state machine to timeout */
-          hadc->State = HAL_ADC_STATE_TIMEOUT;
-
-          /* Process unlocked */
-          __HAL_UNLOCK(hadc);
-          
-          return HAL_ERROR;
-        }
-      }
-      conversion_timeout_cpu_cycles ++;
-    }
-  }
-  
-  /* Clear end of conversion flag of injected group if low power feature      */
-  /* "Auto Wait" is disabled, to not interfere with this feature until data   */
-  /* register is read using function HAL_ADCEx_InjectedGetValue().            */
-  if (hadc->Init.LowPowerAutoWait == DISABLE)
-  {
-    /* Clear injected group conversion flag */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JSTRT | ADC_FLAG_JEOC);
-  }
-  
-  /* Update state machine on conversion status if not in error state */
-  if(hadc->State != HAL_ADC_STATE_ERROR)
-  {
-    /* Update ADC state machine */
-    if(hadc->State != HAL_ADC_STATE_EOC_INJ_REG)
-    {
-
-      if(hadc->State == HAL_ADC_STATE_EOC_REG)
-      {
-        /* Change ADC state */
-        hadc->State = HAL_ADC_STATE_EOC_INJ_REG;  
-      }
-      else
-      {
-        /* Change ADC state */
-        hadc->State = HAL_ADC_STATE_EOC_INJ;
-      }
-    }
-  }
-      
-  /* Return ADC state */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables ADC, starts conversion of injected group with interruption.
-  *         Interruptions enabled in this function: JEOC (end of conversion).
-  *         Each of these interruptions has its dedicated callback function.
-  * @param  hadc: ADC handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Enable the ADC peripheral */
-  tmpHALStatus = ADC_Enable(hadc);
-  
-  /* Start conversion if ADC is effectively enabled */
-  if (tmpHALStatus != HAL_ERROR)
-  {
-    /* Check if a regular conversion is ongoing */
-    if(hadc->State == HAL_ADC_STATE_BUSY_REG)
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_INJ_REG;  
-    }
-    else
-    {
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_BUSY_INJ;
-    }
-    
-    /* Set ADC error code to none */
-    __HAL_ADC_CLEAR_ERRORCODE(hadc);
-    
-    /* Clear injected group conversion flag */
-    /* (To ensure of no unknown state from potential previous ADC operations) */
-    __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-    
-    /* Enable end of conversion interrupt for injected channels */
-    __HAL_ADC_ENABLE_IT(hadc, ADC_IT_JEOC);
-    
-    /* Start conversion of injected group if software start has been selected */
-    /* and if automatic injected conversion is disabled.                      */
-    /* If external trigger has been selected, conversion will start at next   */
-    /* trigger event.                                                         */
-    /* If automatic injected conversion is enabled, conversion will start     */
-    /* after next regular group conversion.                                   */
-    if (__HAL_ADC_IS_SOFTWARE_START_INJECTED(hadc)        && 
-        HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)  )
-    {
-      /* Enable ADC software conversion for injected channels */
-      SET_BIT(hadc->Instance->CR2, ADC_CR2_JSWSTART);
-    }
-  }
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Stop conversion of injected channels, disable interruption of 
-  *         end-of-conversion. Disable ADC peripheral if no regular conversion
-  *         is on going.
-  * @note   If ADC must be disabled with this function and if regular conversion
-  *         is on going, function HAL_ADC_Stop must be used preliminarily.
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc)
-{
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-
-  /* Process locked */
-  __HAL_LOCK(hadc);
-    
-  /* Stop potential conversion and disable ADC peripheral                     */
-  /* Conditioned to:                                                          */
-  /* - No conversion on the other group (regular group) is intended to        */
-  /*   continue (injected and regular groups stop conversion and ADC disable  */
-  /*   are common)                                                            */
-  /* - In case of auto-injection mode, HAL_ADC_Stop must be used.             */ 
-    if((hadc->State != HAL_ADC_STATE_BUSY_REG)            &&
-       (hadc->State != HAL_ADC_STATE_BUSY_INJ_REG)        &&
-       HAL_IS_BIT_CLR(hadc->Instance->CR1, ADC_CR1_JAUTO)   )
-  {
-    /* Stop potential conversion on going, on regular and injected groups */
-    /* Disable ADC peripheral */
-    tmpHALStatus = ADC_ConversionStop_Disable(hadc);
-    
-    /* Check if ADC is effectively disabled */
-    if (tmpHALStatus != HAL_ERROR)
-    {
-      /* Disable ADC end of conversion interrupt for injected channels */
-      __HAL_ADC_DISABLE_IT(hadc, ADC_IT_JEOC);
-      
-      /* Change ADC state */
-      hadc->State = HAL_ADC_STATE_READY;
-    }
-  }
-  else
-  {
-    /* Update ADC state machine to error */
-    hadc->State = HAL_ADC_STATE_ERROR;
-      
-    tmpHALStatus = HAL_ERROR;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @brief  Get ADC injected group conversion result.
-  * @param  hadc: ADC handle
-  * @param  InjectedRank: the converted ADC injected rank.
-  *          This parameter can be one of the following values:
-  *            @arg ADC_INJECTED_RANK_1: Injected Channel1 selected
-  *            @arg ADC_INJECTED_RANK_2: Injected Channel2 selected
-  *            @arg ADC_INJECTED_RANK_3: Injected Channel3 selected
-  *            @arg ADC_INJECTED_RANK_4: Injected Channel4 selected
-  * @retval None
-  */
-uint32_t HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank)
-{
-  uint32_t tmp_jdr = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_INJECTED_RANK(InjectedRank));
-   
-  /* Clear injected group conversion flag to have similar behaviour as         */
-  /* regular group: reading data register also clears end of conversion flag. */
-  __HAL_ADC_CLEAR_FLAG(hadc, ADC_FLAG_JEOC);
-  
-  /* Get ADC converted value */ 
-  switch(InjectedRank)
-  {  
-    case ADC_INJECTED_RANK_4: 
-      tmp_jdr = hadc->Instance->JDR4;
-      break;
-    case ADC_INJECTED_RANK_3: 
-      tmp_jdr = hadc->Instance->JDR3;
-      break;
-    case ADC_INJECTED_RANK_2: 
-      tmp_jdr = hadc->Instance->JDR2;
-      break;
-    case ADC_INJECTED_RANK_1:
-    default:
-      tmp_jdr = hadc->Instance->JDR1;
-      break;
-  }
-  
-  /* Return ADC converted value */ 
-  return tmp_jdr;
-}
-
-/**
-  * @brief  Injected conversion complete callback in non blocking mode 
-  * @param  hadc: ADC handle
-  * @retval None
-  */
-__weak void HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_ADCEx_InjectedConvCpltCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Exported_Functions_Group2 Extended Peripheral Control functions
-  * @brief    Extended Peripheral Control functions
-  *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels on injected group
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the ADC injected group and the selected channel to be
-  *         linked to the injected group.
-  * @note   Possibility to update parameters on the fly:
-  *         This function initializes injected group, following calls to this 
-  *         function can be used to reconfigure some parameters of structure
-  *         "ADC_InjectionConfTypeDef" on the fly, without reseting the ADC.
-  *         The setting of these parameters is conditioned to ADC state: 
-  *         this function must be called when ADC is not under conversion.
-  * @param  hadc: ADC handle
-  * @param  sConfigInjected: Structure of ADC injected group and ADC channel for
-  *         injected group.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected)
-{   
-  HAL_StatusTypeDef tmpHALStatus = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_ADC_ALL_INSTANCE(hadc->Instance));
-  assert_param(IS_ADC_CHANNEL(sConfigInjected->InjectedChannel));
-  assert_param(IS_ADC_SAMPLE_TIME(sConfigInjected->InjectedSamplingTime));
-  assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->AutoInjectedConv));
-  assert_param(IS_ADC_EXTTRIGINJEC(sConfigInjected->ExternalTrigInjecConv));
-  assert_param(IS_ADC_RANGE(sConfigInjected->InjectedOffset));
-  
-  if(hadc->Init.ScanConvMode != ADC_SCAN_DISABLE)
-  {
-    assert_param(IS_ADC_INJECTED_RANK(sConfigInjected->InjectedRank));
-    assert_param(IS_ADC_INJECTED_NB_CONV(sConfigInjected->InjectedNbrOfConversion));
-    assert_param(IS_FUNCTIONAL_STATE(sConfigInjected->InjectedDiscontinuousConvMode));
-  }
-  
-  if(sConfigInjected->ExternalTrigInjecConvEdge != ADC_INJECTED_SOFTWARE_START)
-  {
-    assert_param(IS_ADC_EXTTRIGINJEC_EDGE(sConfigInjected->ExternalTrigInjecConvEdge));
-  }
-  
-  /* Process locked */
-  __HAL_LOCK(hadc);
-  
-  /* Configuration of injected group sequencer:                               */
-  /* - if scan mode is disabled, injected channels sequence length is set to  */
-  /*   0x00: 1 channel converted (channel on regular rank 1)                  */
-  /*   Parameter "InjectedNbrOfConversion" is discarded.                      */
-  /*   Note: Scan mode is present by hardware on this device and, if          */
-  /*   disabled, discards automatically nb of conversions. Anyway, nb of      */
-  /*   conversions is forced to 0x00 for alignment over all STM32 devices.    */
-  /* - if scan mode is enabled, injected channels sequence length is set to   */
-  /*   parameter ""InjectedNbrOfConversion".                                  */
-  if (hadc->Init.ScanConvMode == ADC_SCAN_DISABLE)
-  {
-    if (sConfigInjected->InjectedRank == ADC_INJECTED_RANK_1)
-    {
-      /* Clear the old SQx bits for all injected ranks */
-        MODIFY_REG(hadc->Instance->JSQR                           ,
-                   ADC_JSQR_JL   |
-                   ADC_JSQR_JSQ4 |
-                   ADC_JSQR_JSQ3 |
-                   ADC_JSQR_JSQ2 |
-                   ADC_JSQR_JSQ1                                  ,
-                   __ADC_JSQR_RK(sConfigInjected->InjectedChannel,
-                                 ADC_INJECTED_RANK_1,
-                                 0x01)                             );
-    }
-    /* If another injected rank than rank1 was intended to be set, and could  */
-    /* not due to ScanConvMode disabled, error is reported.                   */
-    else
-    {
-        /* Update ADC state machine to error */
-        hadc->State = HAL_ADC_STATE_ERROR;
-        
-        tmpHALStatus = HAL_ERROR;
-    }
-  }
-  else
-  {   
-    /* Since injected channels rank conv. order depends on total number of   */
-    /* injected conversions, selected rank must be below or equal to total   */
-    /* number of injected conversions to be updated.                         */
-    if (sConfigInjected->InjectedRank <= sConfigInjected->InjectedNbrOfConversion)
-    {
-      /* Clear the old SQx bits for the selected rank */
-      /* Set the SQx bits for the selected rank */
-      MODIFY_REG(hadc->Instance->JSQR                                                 ,
-                 
-                 ADC_JSQR_JL                                            |
-                 __ADC_JSQR_RK(ADC_JSQR_JSQ1,                         
-                               sConfigInjected->InjectedRank,         
-                               sConfigInjected->InjectedNbrOfConversion)              ,
-                 
-                 __ADC_JSQR_JL(sConfigInjected->InjectedNbrOfConversion) |
-                 __ADC_JSQR_RK(sConfigInjected->InjectedChannel,      
-                                             sConfigInjected->InjectedRank,         
-                                             sConfigInjected->InjectedNbrOfConversion) );
-    }
-    else
-    {
-      /* Clear the old SQx bits for the selected rank */
-      MODIFY_REG(hadc->Instance->JSQR                                    ,
-                 
-                 ADC_JSQR_JL                                            |
-                 __ADC_JSQR_RK(ADC_JSQR_JSQ1,                         
-                               sConfigInjected->InjectedRank,         
-                               sConfigInjected->InjectedNbrOfConversion) ,
-                 
-                 0x00000000                                               );
-    }
-  } 
-    
-  /* Enable external trigger if trigger selection is different of software    */
-  /* start.                                                                   */
-  /* Note: This configuration keeps the hardware feature of parameter         */
-  /*       ExternalTrigConvEdge "trigger edge none" equivalent to             */
-  /*       software start.                                                    */
-  
-  if (sConfigInjected->ExternalTrigInjecConv != ADC_INJECTED_SOFTWARE_START)
-  {    
-    MODIFY_REG(hadc->Instance->CR2                        ,
-               ADC_CR2_JEXTEN  |
-               ADC_CR2_JEXTSEL                            ,
-               sConfigInjected->ExternalTrigInjecConv    |
-               sConfigInjected->ExternalTrigInjecConvEdge  );
-  }
-  else
-  {
-    MODIFY_REG(hadc->Instance->CR2,
-               ADC_CR2_JEXTEN  |
-               ADC_CR2_JEXTSEL    ,
-               0x00000000          );
-  }
-
-  /* Configuration of injected group                                          */
-  /* Parameters update conditioned to ADC state:                              */
-  /* Parameters that can be updated only when ADC is disabled:                */
-  /*  - Automatic injected conversion                                         */
-  /*  - Injected discontinuous mode                                           */
-  if ((__HAL_ADC_IS_ENABLED(hadc) == RESET))
-  {
-    hadc->Instance->CR1 &= ~(ADC_CR1_JAUTO   |
-                             ADC_CR1_JDISCEN  );
-    
-    /* Automatic injected conversion can be enabled if injected group         */
-    /* external triggers are disabled.                                        */
-    if (sConfigInjected->AutoInjectedConv == ENABLE)
-    {
-      if (sConfigInjected->ExternalTrigInjecConv == ADC_INJECTED_SOFTWARE_START)
-      {
-        SET_BIT(hadc->Instance->CR1, ADC_CR1_JAUTO);
-      }
-      else
-      {
-        /* Update ADC state machine to error */
-        hadc->State = HAL_ADC_STATE_ERROR;
-        
-        tmpHALStatus = HAL_ERROR;
-      }
-    }
-    
-    /* Injected discontinuous can be enabled only if auto-injected mode is    */
-    /* disabled.                                                              */  
-    if (sConfigInjected->InjectedDiscontinuousConvMode == ENABLE)
-    {
-      if (sConfigInjected->AutoInjectedConv == DISABLE)
-      {
-        SET_BIT(hadc->Instance->CR1, ADC_CR1_JDISCEN);
-      } 
-      else
-      {
-        /* Update ADC state machine to error */
-        hadc->State = HAL_ADC_STATE_ERROR;
-        
-        tmpHALStatus = HAL_ERROR;
-      }
-    }
-  }
-
-  /* InjectedChannel sampling time configuration */
-  /* For InjectedChannels 0 to 9 */
-  if (sConfigInjected->InjectedChannel < ADC_CHANNEL_10)
-  {
-    MODIFY_REG(hadc->Instance->SMPR3,
-               __ADC_SMPR3(ADC_SMPR3_SMP0, sConfigInjected->InjectedChannel),
-               __ADC_SMPR3(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
-  }
-  /* For InjectedChannels 10 to 19 */
-  else if (sConfigInjected->InjectedChannel < ADC_CHANNEL_20)
-  {
-    MODIFY_REG(hadc->Instance->SMPR2,
-               __ADC_SMPR2(ADC_SMPR2_SMP10, sConfigInjected->InjectedChannel),
-               __ADC_SMPR2(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
-  }
-  /* For InjectedChannels 20 to 26 for devices Cat.1, Cat.2, Cat.3 */
-  /* For InjectedChannels 20 to 29 for devices Cat4, Cat.5 */
-  else if (sConfigInjected->InjectedChannel <= ADC_SMPR1_CHANNEL_MAX)
-  {   
-    MODIFY_REG(hadc->Instance->SMPR1,
-               __ADC_SMPR1(ADC_SMPR1_SMP20, sConfigInjected->InjectedChannel),
-               __ADC_SMPR1(sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel) );
-  }
-  /* For InjectedChannels 30 to 31 for devices Cat4, Cat.5 */
-  else
-  {
-    __ADC_SMPR0_CHANNEL_SET(hadc, sConfigInjected->InjectedSamplingTime, sConfigInjected->InjectedChannel);
-  }
-  
-  
-  /* Configure the offset: offset enable/disable, InjectedChannel, offset value */
-  switch(sConfigInjected->InjectedRank)
-  {
-    case 1:
-      /* Set injected channel 1 offset */     
-      MODIFY_REG(hadc->Instance->JOFR1,
-                 ADC_JOFR1_JOFFSET1,
-                 sConfigInjected->InjectedOffset);
-      break;
-    case 2:
-      /* Set injected channel 2 offset */
-      MODIFY_REG(hadc->Instance->JOFR2,
-                 ADC_JOFR2_JOFFSET2,
-                 sConfigInjected->InjectedOffset);
-      break;
-    case 3:
-      /* Set injected channel 3 offset */
-      MODIFY_REG(hadc->Instance->JOFR3,
-                 ADC_JOFR3_JOFFSET3,
-                 sConfigInjected->InjectedOffset);
-      break;
-    case 4:
-    default:
-      MODIFY_REG(hadc->Instance->JOFR4,
-                 ADC_JOFR4_JOFFSET4,
-                 sConfigInjected->InjectedOffset);
-      break;
-  }
-  
-  /* If ADC1 Channel_16 or Channel_17 is selected, enable Temperature sensor  */
-  /* and VREFINT measurement path.                                            */
-  if ((sConfigInjected->InjectedChannel == ADC_CHANNEL_TEMPSENSOR) ||
-      (sConfigInjected->InjectedChannel == ADC_CHANNEL_VREFINT)      )
-  {
-    SET_BIT(ADC->CCR, ADC_CCR_TSVREFE);
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hadc);
-  
-  /* Return function status */
-  return tmpHALStatus;
-}
-
-/**
-  * @}
-  */  
-
-/**
-  * @}
-  */
-
-#endif /* HAL_ADC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_adc_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,693 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_adc_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of ADC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_ADC_EX_H
-#define __STM32L1xx_HAL_ADC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"  
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup ADCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup ADCEx_Exported_Types ADCEx Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  ADC Configuration injected Channel structure definition
-  * @note   Parameters of this structure are shared within 2 scopes:
-  *          - Scope channel: InjectedChannel, InjectedRank, InjectedSamplingTime, InjectedOffset
-  *          - Scope injected group (affects all channels of injected group): InjectedNbrOfConversion, InjectedDiscontinuousConvMode,
-  *            AutoInjectedConv, ExternalTrigInjecConvEdge, ExternalTrigInjecConv.
-  * @note   The setting of these parameters with function HAL_ADCEx_InjectedConfigChannel() is conditioned to ADC state.
-  *         ADC state can be either:
-  *          - For all parameters: ADC disabled
-  *          - For all except parameters 'InjectedDiscontinuousConvMode' and 'AutoInjectedConv': ADC enabled without conversion on going on injected group.
-  *          - For parameters 'ExternalTrigInjecConv' and 'ExternalTrigInjecConvEdge': ADC enabled, even with conversion on going on injected group.
-  */
-typedef struct 
-{
-  uint32_t InjectedChannel;               /*!< Selection of ADC channel to configure
-                                               This parameter can be a value of @ref ADC_channels
-                                               Note: Depending on devices, some channels may not be available on package pins. Refer to device datasheet for channels availability. */
-  uint32_t InjectedRank;                  /*!< Rank in the injected group sequencer
-                                               This parameter must be a value of @ref ADCEx_injected_rank
-                                               Note: In case of need to disable a channel or change order of conversion sequencer, rank containing a previous channel setting can be overwritten by the new channel setting (or parameter number of conversions can be adjusted) */
-  uint32_t InjectedSamplingTime;          /*!< Sampling time value to be set for the selected channel.
-                                               Unit: ADC clock cycles
-                                               Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
-                                               This parameter can be a value of @ref ADC_sampling_times
-                                               Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
-                                                        If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
-                                               Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
-                                                     sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
-                                                     Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */                          
-  uint32_t InjectedOffset;                /*!< Defines the offset to be subtracted from the raw converted data (for channels set on injected group only).
-                                               Offset value must be a positive number.
-                                               Depending of ADC resolution selected (12, 10, 8 or 6 bits),
-                                               this parameter must be a number between Min_Data = 0x000 and Max_Data = 0xFFF, 0x3FF, 0xFF or 0x3F respectively. */
-  uint32_t InjectedNbrOfConversion;       /*!< Specifies the number of ranks that will be converted within the injected group sequencer.
-                                               To use the injected group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
-                                               This parameter must be a number between Min_Data = 1 and Max_Data = 4.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t InjectedDiscontinuousConvMode; /*!< Specifies whether the conversions sequence of injected group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
-                                               Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
-                                               Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
-                                               This parameter can be set to ENABLE or DISABLE.
-                                               Note: For injected group, number of discontinuous ranks increment is fixed to one-by-one.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t AutoInjectedConv;              /*!< Enables or disables the selected ADC automatic injected group conversion after regular one
-                                               This parameter can be set to ENABLE or DISABLE.      
-                                               Note: To use Automatic injected conversion, discontinuous mode must be disabled ('DiscontinuousConvMode' and 'InjectedDiscontinuousConvMode' set to DISABLE)
-                                               Note: To use Automatic injected conversion, injected group external triggers must be disabled ('ExternalTrigInjecConv' set to ADC_SOFTWARE_START)
-                                               Note: In case of DMA used with regular group: if DMA configured in normal mode (single shot) JAUTO will be stopped upon DMA transfer complete.
-                                                     To maintain JAUTO always enabled, DMA must be configured in circular mode.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConv;         /*!< Selects the external event used to trigger the conversion start of injected group.
-                                               If set to ADC_INJECTED_SOFTWARE_START, external triggers are disabled.
-                                               If set to external trigger source, triggering is on event rising edge.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_source_Injected
-                                               Note: This parameter must be modified when ADC is disabled (before ADC start conversion or after ADC stop conversion).
-                                                     If ADC is enabled, this parameter setting is bypassed without error reporting (as it can be the expected behaviour in case of another parameter update on the fly)
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-  uint32_t ExternalTrigInjecConvEdge;     /*!< Selects the external trigger edge of injected group.
-                                               This parameter can be a value of @ref ADCEx_External_trigger_edge_Injected.
-                                               If trigger is set to ADC_INJECTED_SOFTWARE_START, this parameter is discarded.
-                                               Caution: this setting impacts the entire injected group. Therefore, call of HAL_ADCEx_InjectedConfigChannel() to 
-                                                        configure a channel on injected group can impact the configuration of other channels previously set. */
-}ADC_InjectionConfTypeDef; 
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-   
-/** @defgroup ADCEx_Exported_Constants ADCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup ADCEx_injected_rank ADCEx injected rank
-  * @{
-  */
-#define ADC_INJECTED_RANK_1    ((uint32_t)0x00000001)
-#define ADC_INJECTED_RANK_2    ((uint32_t)0x00000002)
-#define ADC_INJECTED_RANK_3    ((uint32_t)0x00000003)
-#define ADC_INJECTED_RANK_4    ((uint32_t)0x00000004)
-
-#define IS_ADC_INJECTED_RANK(CHANNEL) (((CHANNEL) == ADC_INJECTED_RANK_1) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_2) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_3) || \
-                                       ((CHANNEL) == ADC_INJECTED_RANK_4)   )
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_External_trigger_edge_Injected ADCEx External trigger edge Injected
-  * @{
-  */
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_NONE           ((uint32_t)0x00000000)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISING         ((uint32_t)ADC_CR2_JEXTEN_0)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING        ((uint32_t)ADC_CR2_JEXTEN_1)
-#define ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING  ((uint32_t)ADC_CR2_JEXTEN)
-
-#define IS_ADC_EXTTRIGINJEC_EDGE(EDGE) (((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_NONE)         || \
-                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISING)       || \
-                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_FALLING)      || \
-                                        ((EDGE) == ADC_EXTERNALTRIGINJECCONV_EDGE_RISINGFALLING)  )
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_External_trigger_source_Injected ADCEx External trigger source Injected
-  * @{
-  */
-/* External triggers for injected groups of ADC1 */
-#define ADC_EXTERNALTRIGINJECCONV_T2_CC1      ADC_EXTERNALTRIGINJEC_T2_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T2_TRGO     ADC_EXTERNALTRIGINJEC_T2_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T3_CC4      ADC_EXTERNALTRIGINJEC_T3_CC4
-#define ADC_EXTERNALTRIGINJECCONV_T4_TRGO     ADC_EXTERNALTRIGINJEC_T4_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC1      ADC_EXTERNALTRIGINJEC_T4_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC2      ADC_EXTERNALTRIGINJEC_T4_CC2
-#define ADC_EXTERNALTRIGINJECCONV_T4_CC3      ADC_EXTERNALTRIGINJEC_T4_CC3
-#define ADC_EXTERNALTRIGINJECCONV_T7_TRGO     ADC_EXTERNALTRIGINJEC_T7_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T9_CC1      ADC_EXTERNALTRIGINJEC_T9_CC1
-#define ADC_EXTERNALTRIGINJECCONV_T9_TRGO     ADC_EXTERNALTRIGINJEC_T9_TRGO
-#define ADC_EXTERNALTRIGINJECCONV_T10_CC1     ADC_EXTERNALTRIGINJEC_T10_CC1
-#define ADC_EXTERNALTRIGINJECCONV_EXT_IT15    ADC_EXTERNALTRIGINJEC_EXT_IT15
-
-#define ADC_INJECTED_SOFTWARE_START      ((uint32_t)0x00000010)
-
-#define IS_ADC_EXTTRIGINJEC(REGTRIG) (((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T2_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T3_CC4)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC2)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T4_CC3)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T7_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_CC1)   || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T9_TRGO)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_T10_CC1)  || \
-                                      ((REGTRIG) == ADC_EXTERNALTRIGINJECCONV_EXT_IT15) || \
-                                      ((REGTRIG) == ADC_SOFTWARE_START)              )
-/**
-  * @}
-  */
-
-/** @defgroup ADCEx_Internal_HAL_driver_Ext_trig_src_Injected ADCEx Internal HAL driver Ext trig src Injected
-  * @{
-  */
-
-/* List of external triggers of injected group for ADC1:                      */
-/* (used internally by HAL driver. To not use into HAL structure parameters)  */
-#define ADC_EXTERNALTRIGINJEC_T9_CC1         ((uint32_t) 0x00000000)
-#define ADC_EXTERNALTRIGINJEC_T9_TRGO        ((uint32_t)(                                                         ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T2_TRGO        ((uint32_t)(                                      ADC_CR2_JEXTSEL_1                   ))
-#define ADC_EXTERNALTRIGINJEC_T2_CC1         ((uint32_t)(                                      ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T3_CC4         ((uint32_t)(                   ADC_CR2_JEXTSEL_2                                      ))
-#define ADC_EXTERNALTRIGINJEC_T4_TRGO        ((uint32_t)(                   ADC_CR2_JEXTSEL_2 |                    ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T4_CC1         ((uint32_t)(                   ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1                   ))
-#define ADC_EXTERNALTRIGINJEC_T4_CC2         ((uint32_t)(                   ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T4_CC3         ((uint32_t)(ADC_CR2_JEXTSEL_3                                                         ))
-#define ADC_EXTERNALTRIGINJEC_T10_CC1        ((uint32_t)(ADC_CR2_JEXTSEL_3                                       | ADC_CR2_JEXTSEL_0))
-#define ADC_EXTERNALTRIGINJEC_T7_TRGO        ((uint32_t)(ADC_CR2_JEXTSEL_3                    | ADC_CR2_JEXTSEL_1                   ))
-#define ADC_EXTERNALTRIGINJEC_EXT_IT15       ((uint32_t)(ADC_CR2_JEXTSEL_3 | ADC_CR2_JEXTSEL_2 | ADC_CR2_JEXTSEL_1 | ADC_CR2_JEXTSEL_0))
-
-/**
-  * @}
-  */
-
-
-/** @defgroup ADCEx_injected_nb_conv_verification ADCEx injected nb conv verification
-  * @{
-  */
-#define IS_ADC_INJECTED_NB_CONV(LENGTH) (((LENGTH) >= ((uint32_t)1)) && ((LENGTH) <= ((uint32_t)4)))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Exported_Macros ADCEx Exported Macros
-  * @{
-  */
-/* Macro for internal HAL driver usage, and possibly can be used into code of */
-/* final user.                                                                */
-
-/**
-  * @brief Selection of channels bank. 
-  * Note: Banks availability depends on devices categories.
-  * This macro is intended to change bank selection quickly on the fly,   
-  * without going through ADC init structure update and execution of function
-  * 'HAL_ADC_Init()'.
-  * @param __HANDLE__: ADC handle
-  * @param __BANK__: Bank selection. This parameter can be a value of @ref ADC_ChannelsBank.
-  * @retval None
-  */
-#define __HAL_ADC_CHANNELS_BANK(__HANDLE__, __BANK__)                          \
-  MODIFY_REG((__HANDLE__)->Instance->CR2, ADC_CR2_CFG, (__BANK__))
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
- * @brief Configures the ADC channels speed.
- * Limited to channels 3, 8, 13 and to devices category Cat.3, Cat.4, Cat.5.
- *  - For ADC_CHANNEL_3: Used as ADC direct channel (fast channel) if OPAMP1 is
- *    in power down mode.
- *  - For ADC_CHANNEL_8: Used as ADC direct channel (fast channel) if OPAMP2 is
- *    in power down mode.
- *  - For ADC_CHANNEL_13: Used as ADC re-routed channel if OPAMP3 is in 
- *    power down mode. Otherwise, channel 13 is connected to OPAMP3 output and 
- *    routed through switches COMP1_SW1 and VCOMP to ADC switch matrix.
- *    (Note: OPAMP3 is available on STM32L1 Cat.4 only).
- * @param __CHANNEL__: ADC channel
- * This parameter can be one of the following values:
- * @arg ADC_CHANNEL_3: Channel 3 is selected.
- * @arg ADC_CHANNEL_8: Channel 8 is selected.
- * @arg ADC_CHANNEL_13: Channel 13 is selected.
- * @retval None
- */
-#define __HAL_ADC_CHANNEL_SPEED_FAST(__CHANNEL__)                              \
-  ( ( ((__CHANNEL__) == ADC_CHANNEL_3)                                         \
-    )?                                                                         \
-     (SET_BIT(COMP->CSR, COMP_CSR_FCH3))                                       \
-     :                                                                         \
-     ( ( ((__CHANNEL__) == ADC_CHANNEL_8)                                      \
-       )?                                                                      \
-        (SET_BIT(COMP->CSR, COMP_CSR_FCH8))                                    \
-        :                                                                      \
-        ( ( ((__CHANNEL__) == ADC_CHANNEL_13)                                  \
-          )?                                                                   \
-           (SET_BIT(COMP->CSR, COMP_CSR_RCH13))                                \
-           :                                                                   \
-           (SET_BIT(COMP->CSR, 0x00000000))                                    \
-        )                                                                      \
-     )                                                                         \
-  )
-
-#define __HAL_ADC_CHANNEL_SPEED_SLOW(__CHANNEL__)                              \
-  ( ( ((__CHANNEL__) == ADC_CHANNEL_3)                                         \
-    )?                                                                         \
-     (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH3))                                     \
-     :                                                                         \
-     ( ( ((__CHANNEL__) == ADC_CHANNEL_8)                                      \
-       )?                                                                      \
-        (CLEAR_BIT(COMP->CSR, COMP_CSR_FCH8))                                  \
-        :                                                                      \
-        ( ( ((__CHANNEL__) == ADC_CHANNEL_13)                                  \
-          )?                                                                   \
-           (CLEAR_BIT(COMP->CSR, COMP_CSR_RCH13))                              \
-           :                                                                   \
-           (SET_BIT(COMP->CSR, 0x00000000))                                    \
-        )                                                                      \
-     )                                                                         \
-  )
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-    
-/**
-  * @}
-  */
-
-/* Private macro ------------------------------------------------------------*/
-
-/** @defgroup ADCEx_Private_Macro ADCEx Private Macro
-  * @{
-  */
-/* Macro reserved for internal HAL driver usage, not intended to be used in   */
-/* code of final user.                                                        */
-
-/**
-  * @brief Set ADC number of ranks into regular channel sequence length.
-  * @param _NbrOfConversion_: Regular channel sequence length 
-  * @retval None
-  */
-#define __ADC_SQR1_L(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << POSITION_VAL(ADC_SQR1_L))
-
-/**
-  * @brief Set ADC ranks available in register SQR1.
-  * Register SQR1 bits availability depends on device category.
-  * @param _NbrOfConversion_: Regular channel sequence length 
-  * @retval None
-  */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define __ADC_SQR1_SQXX   ADC_SQR1_SQ28 | ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25
-#else
-#define __ADC_SQR1_SQXX   ADC_SQR1_SQ27 | ADC_SQR1_SQ26 | ADC_SQR1_SQ25
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @brief Set the ADC's sample time for channel numbers between 30 and 31.
-  * Register SMPR0 availability depends on device category. If register is not
-  * available on the current device, this macro does nothing.
-  * @retval None
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 30)))
-#else
-#define __ADC_SMPR0(_SAMPLETIME_, _CHANNELNB_) ((uint32_t)0x00000000)
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-    
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
-  * @brief Set the ADC's sample time for channel numbers between 20 and 29.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.
-  * @retval None
-  */
-#define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
-#else
-/**
-  * @brief Set the ADC's sample time for channel numbers between 20 and 26.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.
-  * @retval None
-  */
-#define __ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 20)))
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @brief Defines the highest channel available in register SMPR1. Channels
-  * availability depends on device category:
-  * Highest channel in register SMPR1 is channel 26 for devices Cat.1, Cat.2, Cat.3
-  * Highest channel in register SMPR1 is channel 29 for devices Cat.4, Cat.5
-  * @param None
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define ADC_SMPR1_CHANNEL_MAX   ADC_CHANNEL_29
-#else
-#define ADC_SMPR1_CHANNEL_MAX   ADC_CHANNEL_26
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-   
-/**
-  * @brief Set the ADC's sample time for channel numbers between 10 and 18.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#define __ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((_CHANNELNB_) - 10)))
-
-/**
-  * @brief Set the ADC's sample time for channel numbers between 0 and 9.
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param _CHANNELNB_: Channel number.  
-  * @retval None
-  */
-#define __ADC_SMPR3(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (_CHANNELNB_)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 1 and 6.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define __ADC_SQR5_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 1)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 7 and 12.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define __ADC_SQR4_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 7)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 13 and 18.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define __ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 13)))
-
-/**
-  * @brief Set the selected regular channel rank for rank between 19 and 24.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define __ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 19)))
-      
-/**
-  * @brief Set the selected regular channel rank for rank between 25 and 28.
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.    
-  * @retval None
-  */
-#define __ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) ((_CHANNELNB_) << (5 * ((_RANKNB_) - 25)))
-      
-/**
-  * @brief Set the injected sequence length.
-  * @param _JSQR_JL_: Sequence length.
-  * @retval None
-  */
-#define __ADC_JSQR_JL(_JSQR_JL_)   (((_JSQR_JL_) -1) << 20)
-
-/**
-  * @brief Set the selected injected Channel rank (channels sequence starting from 4-JL)
-  * @param _CHANNELNB_: Channel number.
-  * @param _RANKNB_: Rank number.
-  * @param _JSQR_JL_: Sequence length.
-  * @retval None
-  */
-#define __ADC_JSQR_RK(_CHANNELNB_, _RANKNB_, _JSQR_JL_)                        \
-    ((_CHANNELNB_) << (5 * ((4 - ((_JSQR_JL_) - (_RANKNB_))) - 1)))
-
-      
-/**
-  * @brief Enable the ADC DMA continuous request.
-  * @param _DMACONTREQ_MODE_: DMA continuous request mode.
-  * @retval None
-  */
-#define __ADC_CR2_DMACONTREQ(_DMACONTREQ_MODE_) ((_DMACONTREQ_MODE_) << POSITION_VAL(ADC_CR2_DDS))
-
-/**
-  * @brief Enable ADC continuous conversion mode.
-  * @param _CONTINUOUS_MODE_: Continuous mode.
-  * @retval None
-  */
-#define __ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << POSITION_VAL(ADC_CR2_CONT))
-
-/**
-  * @brief Define mask of configuration bits of ADC and regular group in
-  * register CR2 (bits of ADC enable, conversion start and injected group are 
-  * excluded of this mask).
-  * @retval None
-  */
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define __ADC_CR2_MASK_ADCINIT()                                               \
-  (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CFG | ADC_CR2_CONT)
-#else
-#define __ADC_CR2_MASK_ADCINIT()                                               \
-  (ADC_CR2_EXTEN | ADC_CR2_EXTSEL | ADC_CR2_ALIGN | ADC_CR2_EOCS | ADC_CR2_DDS | ADC_CR2_DELS | ADC_CR2_CONT)
-#endif
-
-/**
-  * @brief Configures the number of discontinuous conversions for the regular group channels.
-  * @param _NBR_DISCONTINUOUS_CONV_: Number of discontinuous conversions.
-  * @retval None
-  */
-#define __ADC_CR1_DISCONTINUOUS_NUM(_NBR_DISCONTINUOUS_CONV_) (((_NBR_DISCONTINUOUS_CONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
-   
-/**
-  * @brief Enable ADC scan mode to convert multiple ranks with sequencer.
-  * @param _SCAN_MODE_: Scan conversion mode.
-  * @retval None
-  */
-#define __ADC_CR1_SCAN(_SCAN_MODE_)                                            \
-  ( ( (_SCAN_MODE_) == (ADC_SCAN_ENABLE)                                       \
-    )? (ADC_CR1_SCAN) : (0x00000000)                                           \
-  )
-
-/**
-  * @brief Get the maximum ADC conversion cycles on all channels.
-  * Returns the selected sampling time + conversion time (12.5 ADC clock cycles)
-  * Approximation of sampling time within 2 ranges, returns the higher value:
-  *   below 24 cycles {4 cycles; 9 cycles; 16 cycles; 24 cycles}
-  *   between 48 cycles and 384 cycles {48 cycles; 96 cycles; 192 cycles; 384 cycles}
-  * Unit: ADC clock cycles
-  * @param __HANDLE__: ADC handle
-  * @retval ADC conversion cycles on all channels
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                          \
-    (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR0 & ADC_SAMPLETIME_ALLCHANNELS_SMPR0BIT2) == RESET) ) ?            \
-                                                                                                        \
-        ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES  \
-     )
-#else
-#define __ADC_CONVCYCLES_MAX_RANGE(__HANDLE__)                                                          \
-    (( (((__HANDLE__)->Instance->SMPR3 & ADC_SAMPLETIME_ALLCHANNELS_SMPR3BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR2 & ADC_SAMPLETIME_ALLCHANNELS_SMPR2BIT2) == RESET)  &&            \
-       (((__HANDLE__)->Instance->SMPR1 & ADC_SAMPLETIME_ALLCHANNELS_SMPR1BIT2) == RESET) ) ?            \
-                                                                                                        \
-        ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_24CYCLES : ADC_CONVERSIONCLOCKCYCLES_SAMPLETIME_384CYCLES  \
-     )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @brief Get the ADC clock prescaler from ADC common control register
-  * and convert it to its decimal number setting (refer to reference manual)
-  * @retval None
-  */
-#define __ADC_GET_CLOCK_PRESCALER_DECIMAL(__HANDLE__)                          \
-    ((0x01) << ((ADC->CCR & ADC_CCR_ADCPRE) >> POSITION_VAL(ADC_CCR_ADCPRE)))
-
-/**
-  * @brief Clear register SMPR0.
-  * Register SMPR0 availability depends on device category. If register is not
-  * available on the current device, this macro performs no action.
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define __ADC_SMPR0_CLEAR(__HANDLE__)                                          \
-  (CLEAR_BIT((__HANDLE__)->Instance->SMPR0, (ADC_SMPR0_SMP31 | ADC_SMPR0_SMP30)))
-#else
-#define __ADC_SMPR0_CLEAR(__HANDLE__) __NOP()
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @brief Clear register CR2.
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define __ADC_CR2_CLEAR(__HANDLE__)                                                                \
-  (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL  |   \
-                                           ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |   \
-                                           ADC_CR2_ALIGN    | ADC_CR2_EOCS   | ADC_CR2_DDS     |   \
-                                           ADC_CR2_DMA      | ADC_CR2_DELS   | ADC_CR2_CFG     |   \
-                                           ADC_CR2_CONT     | ADC_CR2_ADON                      )) \
-  )
-#else
-#define __ADC_CR2_CLEAR(__HANDLE__)                                                                \
-  (CLEAR_BIT((__HANDLE__)->Instance->CR2, (ADC_CR2_SWSTART  | ADC_CR2_EXTEN  | ADC_CR2_EXTSEL  |   \
-                                           ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL |   \
-                                           ADC_CR2_ALIGN    | ADC_CR2_EOCS   | ADC_CR2_DDS     |   \
-                                           ADC_CR2_DMA      | ADC_CR2_DELS   |                     \
-                                           ADC_CR2_CONT     | ADC_CR2_ADON                      )) \
-  )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-      
-/**
-  * @brief Set the sampling time of selected channel on register SMPR0
-  * Register SMPR0 availability depends on device category. If register is not
-  * available on the current device, this macro performs no action.
-  * @param __HANDLE__: ADC handle
-  * @param _SAMPLETIME_: Sample time parameter.
-  * @param __CHANNEL__: Channel number.
-  * @retval None
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__)         \
-    MODIFY_REG((__HANDLE__)->Instance->SMPR0,                                  \
-               __ADC_SMPR0(ADC_SMPR0_SMP30, (__CHANNEL__)),                    \
-               __ADC_SMPR0((_SAMPLETIME_), (__CHANNEL__))  )
-#else
-#define __ADC_SMPR0_CHANNEL_SET(__HANDLE__, _SAMPLETIME_, __CHANNEL__) __NOP()
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */     
-
-      
-/**
-  * @brief Enable the ADC peripheral
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __ADC_ENABLE(__HANDLE__)                                               \
-            (__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON
-  
-/**
-  * @brief Disable the ADC peripheral
-  * @param __HANDLE__: ADC handle
-  * @retval None
-  */
-#define __ADC_DISABLE(__HANDLE__)                                              \
-            (__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON
-
-/**
-  * @}
-  */      
-   
-   
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup ADCEx_Exported_Functions
-  * @{
-  */
-
-/* IO operation functions  *****************************************************/
-/** @addtogroup ADCEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* Blocking mode: Polling */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
-
-/* Non-blocking mode: Interruption */
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStart_IT(ADC_HandleTypeDef* hadc);
-HAL_StatusTypeDef       HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc);
-
-/* ADC retrieve conversion value intended to be used with polling or interruption */
-uint32_t                HAL_ADCEx_InjectedGetValue(ADC_HandleTypeDef* hadc, uint32_t InjectedRank);
-
-/* ADC IRQHandler and Callbacks used in non-blocking modes (Interruption) */
-void                    HAL_ADCEx_InjectedConvCpltCallback(ADC_HandleTypeDef* hadc);
-/**
-  * @}
-  */
-
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup ADCEx_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef       HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc,ADC_InjectionConfTypeDef* sConfigInjected);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_ADC_EX_H */
-
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,810 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_comp.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   COMP HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the COMP peripheral:
-  *           + Initialization and de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-================================================================================
-          ##### COMP Peripheral features #####
-================================================================================
-           
-  [..]       
-      The STM32L1xx device family integrates 2 analog comparators COMP1 and 
-      COMP2:
-      (#) The non inverting input and inverting input can be set to GPIO pins.
-          Refer to "table1. COMP Inputs" below.
-          HAL COMP driver configures the Routing Interface (RI) to connect the
-          selected I/O pins to comparator input.
-          Caution: Comparator COMP1 and ADC cannot be used at the same time as 
-          ADC since they share the ADC switch matrix: COMP1 non-inverting 
-          input is routed through ADC switch matrix. Except if ADC is intented 
-          to measure voltage on COMP1 non-inverting input: it can be performed 
-          on ADC channel VCOMP.
-
-      (#) The COMP output is available using HAL_COMP_GetOutputLevel().
-
-      (#) The COMP output can be redirected to embedded timers (TIM2, TIM3, 
-          TIM4, TIM10).
-          COMP output cannot be redirected to any I/O pin.
-          Refer to "table 2. COMP Outputs redirection to embedded timers" below.
-
-      (#) The comparators COMP1 and COMP2 can be combined in window mode. 
-          In this mode, COMP2 non inverting input is used as common 
-          non-inverting input.
-  
-      (#) The 2 comparators have interrupt capability with wake-up
-          from Sleep and Stop modes (through the EXTI controller):
-          (++) COMP1 is internally connected to EXTI Line 21
-          (++) COMP2 is internally connected to EXTI Line 22
-
-          From the corresponding IRQ handler, the right interrupt source can be
-          retrieved with macro __HAL_COMP_EXTI_GET_FLAG(). Possible values are: 
-          (++) COMP_EXTI_LINE_COMP1_EVENT
-          (++) COMP_EXTI_LINE_COMP2_EVENT
-  
-      (#) The comparators also offer the possibility to ouput the voltage 
-          reference (VrefInt), used on inverting inputs, on I/O pin through 
-          a buffer. To use it, refer to macro "__HAL_VREFINT_OUT_ENABLE()".
-
-            
-[..] Table 1. COMP Inputs for the STM32L1xx devices
- +----------------------------------------------------------------------+
- |                 |                                |  COMP1  |  COMP2  |
- |-----------------|--------------------------------|---------|---------|
- |                 | 1/4 VREFINT                    |   --    |   OK    |
- |                 | 1/2 VREFINT                    |   --    |   OK    |
- |                 | 3/4 VREFINT                    |   --    |   OK    |
- | Inverting       | VREFINT                        |   OK    |   OK    |
- | input           | DAC Ch1 OUT (PA4)              |   --    |   OK    |
- |                 | DAC Ch2 OUT (PA5)              |   --    |   OK    |
- |                 | IO: PB3                        |   --    |   OK    |
- |-----------------|--------------------------------|---------|---------|
- |                 | IO:                            |         |         |
- |                 |   PB4, 5, 6*, 7*               |   ---   |   OK    |
- | Non-inverting   |   PA0*, 1*, 2*, 3*, 4, 5, 6, 7 |   OK    |   ---   |
- | input           |   PB0, 1, 12, 13, 14, 15       |   OK    |   ---   |
- |                 |   PC0, 1, 2, 3, 4, 5           |   OK    |   ---   |
- |                 |   PE7, 8, 9, 10                |   OK    |   ---   |
- |                 |   PF6, 7, 8, 9, 10             |   OK    |   ---   |
- |                 | OPAMP1 output                  |   OK    |   ---   |
- |                 | OPAMP2 output                  |   OK    |   ---   |
- |                 | OPAMP3 output**                |   OK    |   ---   |
- +----------------------------------------------------------------------+
- *: Available on devices category Cat.3, Cat.4, Cat.5 only. 
- **: Available on devices category Cat.4 only. 
-
- [..] Table 2. COMP Outputs redirection to embedded timers
- +-----------------------------------+     
- |      COMP1      |      COMP2      |
- |-----------------|-----------------|
- |                 |  TIM2 IC4       |
- |                 |  TIM2 OCREF CLR |
- | (no redirection |  TIM3 IC4       |
- |   to timers)    |  TIM3 OCREF CLR |
- |                 |  TIM4 IC4       |
- |                 |  TIM4 OCREF CLR |
- |                 |  TIM10 IC1      |
- +-----------------------------------+
-
-
-            ##### How to use this driver #####
-================================================================================
-  [..]
-      This driver provides functions to configure and program the Comparators of all STM32L1xx devices.
-
-      To use the comparator, perform the following steps:
-  
-      (#)  Initialize the COMP low level resources by implementing the HAL_COMP_MspInit().
-      (++) Configure the comparator input I/O pin using HAL_GPIO_Init():
-           - For all inputs: I/O pin in analog mode (Schmitt trigger disabled)
-           - Possible alternate configuration, for non-inverting inputs of comparator 2: I/O pin in floating mode (Schmitt trigger enabled).
-           It is recommended to use analog configuration to avoid any overconsumption around VDD/2.
-      (++) Enable COMP Peripheral clock using macro __COMP_CLK_ENABLE()
-      (++) If required enable the COMP interrupt (EXTI line Interrupt): enable
-           the comparator interrupt vector using HAL_NVIC_EnableIRQ(COMP_IRQn)
-           and HAL_NVIC_SetPriority(COMP_IRQn, xxx, xxx) functions.
-  
-      (#) Configure the comparator using HAL_COMP_Init() function:
-      (++) Select the inverting input (COMP2 only)
-      (++) Select the non-inverting input
-      (++) Select the output redirection to timers (COMP2 only)
-      (++) Select the speed mode (COMP2 only)
-      (++) Select the window mode (related to COMP1 and COMP2, but selected 
-           by COMP2 only)
-      (++) Select the pull-up/down resistors on non-inverting input (COMP1 only)
-
-      (#) Enable the comparator using HAL_COMP_Start() or HAL_COMP_Start_IT() 
-          function
-    
-      (#) If needed, use HAL_COMP_GetOutputLevel() or HAL_COMP_TriggerCallback()
-          functions to manage comparator actions (output level or events)
-
-      (#) Disable the comparator using HAL_COMP_Stop() or HAL_COMP_Stop_IT() 
-          function
-
-      (#) De-initialize the comparator using HAL_COMP_DeInit() function
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup COMP COMP
-  * @brief COMP HAL module driver
-  * @{
-  */
-
-#ifdef HAL_COMP_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup COMP_Private_Constants COMP Private Constants
-  * @{
-  */
-  /* Delay for COMP startup time.                                             */
-  /* Maximum delay is 10us for comparator 1 and 25us for comparator 2 in slow */
-  /* mode (refer to device datasheet, parameter tSTART).                      */
-  /* Delay in CPU cycles, fixed to worst case: maximum CPU frequency 32MHz to */
-  /* have the minimum number of CPU cycles to fulfill this delay.             */
-  /*  - Comparator 1: delay minimum of 320 CPU cyles. Wait loop takes 3 CPU   */
-  /*                 cycles per iteration, therefore total wait iterations    */
-  /*                 number must be initialized at 106 iterations.            */
-  /*  - Comparator 2: delay minimum of 800 CPU cyles. Wait loop takes 3 CPU   */
-  /*                 cycles per iteration, therefore total wait iterations    */
-  /*                 number must be initialized at 266 iterations.            */
-#define COMP1_START_DELAY_CPU_CYCLES       ((uint32_t)106)
-#define COMP2_START_DELAY_CPU_CYCLES       ((uint32_t)266)
-
-  /* Comparator status "locked": to update COMP handle state (software lock   */
-  /* only on COMP of STM32L1xx devices) by bitfield:                          */
-  /* states HAL_COMP_STATE_READY_LOCKED, HAL_COMP_STATE_BUSY_LOCKED.          */
-#define COMP_STATE_BIT_LOCK     ((uint32_t) 0x00000010)  
-
-/**
-  * @}
-  */
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Functions COMP Exported Functions
-  * @{
-  */
-
-/** @defgroup COMP_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions to initialize and de-initialize comparators 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the COMP according to the specified
-  *         parameters in the COMP_InitTypeDef and create the associated handle.
-  * @note   If the selected comparator is locked, initialization can't be performed.
-  *         To unlock the configuration, perform a system reset.
-  * @param  hcomp: COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    if (hcomp->Instance == COMP1)
-    {
-      assert_param(IS_COMP_NONINVERTINGINPUTPULL(hcomp->Init.NonInvertingInputPull));
-    }
-    else /* if (hcomp->Instance == COMP2) */
-    {
-      assert_param(IS_COMP_INVERTINGINPUT(hcomp->Init.InvertingInput));
-      assert_param(IS_COMP_OUTPUT(hcomp->Init.Output));
-      assert_param(IS_COMP_MODE(hcomp->Init.Mode));
-      assert_param(IS_COMP_WINDOWMODE(hcomp->Init.WindowMode));
-    }
-  
-    /* In window mode, non-inverting inputs of the 2 comparators are          */
-    /* connected together and are using inputs of COMP2 only. If COMP1 is     */
-    /* selected, this parameter is discarded.                                 */
-    if ((hcomp->Init.WindowMode == COMP_WINDOWMODE_DISABLED) ||
-        (hcomp->Instance == COMP2)                             )
-    {
-      assert_param(IS_COMP_NONINVERTINGINPUT(hcomp->Init.NonInvertingInput));
-    }
-    
-      
-    /* Enable SYSCFG clock and the low level hardware to access comparators */
-    if(hcomp->State == HAL_COMP_STATE_RESET)
-    {
-      /* Enable SYSCFG clock to control the routing Interface (RI) */
-      __SYSCFG_CLK_ENABLE();
-      
-      /* Init the low level hardware */
-      HAL_COMP_MspInit(hcomp);
-    }
-  
-    /* Configuration of comparator:                                           */
-    /*  - Output selection                                                    */
-    /*  - Inverting input selection                                           */
-    /*  - Window mode                                                         */
-    /*  - Mode fast/slow speed                                                */
-    /*  - Inverting input pull-up/down resistors                              */
-    
-    /* Configuration depending on comparator instance */
-    if (hcomp->Instance == COMP1)
-    {
-      MODIFY_REG(COMP->CSR, COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU,
-                            hcomp->Init.NonInvertingInputPull                                   );
-    }
-    else /* if (hcomp->Instance == COMP2) */
-    {
-      /* Note: If comparator 2 is not enabled, inverting input (parameter     */
-      /*       "hcomp->Init.InvertingInput") is configured into function      */
-      /*       "HAL_COMP_Start()" since inverting  input selection also       */
-      /*       enables the comparator 2.                                      */
-      /*       If comparator 2 is already enabled, inverting input is         */
-      /*       reconfigured on the fly.                                       */
-      if (__COMP_IS_ENABLED(hcomp) == RESET)
-      {
-        MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL  |
-                              COMP_CSR_WNDWE   |
-                              COMP_CSR_SPEED          ,
-                              hcomp->Init.Output     |
-                              hcomp->Init.WindowMode |
-                              hcomp->Init.Mode        );
-      }
-      else
-      {
-        MODIFY_REG(COMP->CSR, COMP_CSR_OUTSEL  |
-                              COMP_CSR_INSEL   |
-                              COMP_CSR_WNDWE   |
-                              COMP_CSR_SPEED              ,
-                              hcomp->Init.Output         |
-                              hcomp->Init.InvertingInput |
-                              hcomp->Init.WindowMode     |
-                              hcomp->Init.Mode            );
-      }
-    }
-    
-    /* Configure Routing Interface (RI) switches for comparator non-inverting */
-    /* input.                                                                 */
-    /* Except in 2 cases:                                                     */
-    /* - if non-inverting input has no selection: it can be the case for      */
-    /*   COMP1 in window mode.                                                */
-    /* - particular case for PC3: if switch COMP1_SW1 is closed               */
-    /*   (by macro "__HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1()" or             */
-    /*   "__HAL_RI_SWITCH_COMP1_SW1_CLOSE()"), connection between pin PC3     */
-    /*    (or OPAMP3, if available) and COMP1 is done directly, without going */
-    /*    through ADC switch matrix.                                          */
-    if (__COMP_ROUTING_INTERFACE_TOBECONFIGURED(hcomp))
-    {
-      if (hcomp->Instance == COMP1)
-      {
-        /* Enable the switch control mode */
-        __HAL_RI_SWITCHCONTROLMODE_ENABLE();
-
-        /* Close the analog switch of ADC switch matrix to COMP1 (ADC         */
-        /* channel 26: Vcomp)                                                 */
-        __HAL_RI_IOSWITCH_CLOSE(RI_IOSWITCH_VCOMP);
-      }
-
-      /* Close the I/O analog switch corresponding to comparator              */
-      /* non-inverting input selected.                                        */
-      __HAL_RI_IOSWITCH_CLOSE(hcomp->Init.NonInvertingInput);
-    }
-
-    
-    /* Initialize the COMP state*/
-    if(hcomp->State == HAL_COMP_STATE_RESET)
-    {
-      hcomp->State = HAL_COMP_STATE_READY;
-    }
-  }
-  
-  return status;
-}
-
-
-/**
-  * @brief  DeInitializes the COMP peripheral 
-  * @note   Deinitialization can't be performed if the COMP configuration is locked.
-  *         To unlock the configuration, perform a system reset.
-  * @param  hcomp: COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_DeInit(COMP_HandleTypeDef *hcomp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-    
-    /* Reset configuration depending on comparator instance */
-    if (hcomp->Instance == COMP1)
-    {
-      CLEAR_BIT(COMP->CSR , COMP_CSR_400KPD | COMP_CSR_10KPD | COMP_CSR_400KPU | COMP_CSR_10KPU);
-    }
-    else /* if (hcomp->Instance == COMP2) */
-    {
-      CLEAR_BIT(COMP->CSR , COMP_CSR_OUTSEL |
-                            COMP_CSR_WNDWE  |
-                            COMP_CSR_INSEL  |
-                            COMP_CSR_SPEED   );
-    }
-    
-    
-    /* Restore default state of Routing Interface (RI) switches for           */
-    /* comparator non-inverting input.                                        */
-    if (hcomp->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE)
-    {
-      /* Open the I/O analog switch corresponding to comparator               */
-      /* non-inverting input selected.                                        */
-      __HAL_RI_IOSWITCH_OPEN(hcomp->Init.NonInvertingInput);
-    }
-    if (hcomp->Instance == COMP1)
-    {
-      /* Open the analog switch of ADC switch matrix to COMP1 (ADC            */
-      /* channel 26: Vcomp)                                                   */
-      __HAL_RI_IOSWITCH_OPEN(RI_IOSWITCH_VCOMP);
-      
-      /* Disable the switch control mode */
-      __HAL_RI_SWITCHCONTROLMODE_DISABLE();
-    }
-  
-    
-    /* DeInit the low level hardware: SYSCFG, GPIO, CLOCK and NVIC */
-    HAL_COMP_MspDeInit(hcomp);
-
-    hcomp->State = HAL_COMP_STATE_RESET;
-    
-    /* Process unlocked */
-    __HAL_UNLOCK(hcomp);
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Initializes the COMP MSP.
-  * @param  hcomp: COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_COMP_MspInit could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes COMP MSP.
-  * @param  hcomp: COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_COMP_MspDeInit could be implenetd in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group2 I/O operation functions 
- *  @brief   I/O operation functions
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the COMP 
-    start and stop actions with or without interruption on ExtI line.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the comparator 
-  * @param  hcomp: COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t wait_loop_cycles = 0;
-  __IO uint32_t wait_loop_index = 0;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    if(hcomp->State == HAL_COMP_STATE_READY)
-    {
-      
-      /* Note: For comparator 2, inverting input (parameter                   */
-      /*       "hcomp->Init.InvertingInput") is configured into this          */
-      /*       function instead of function "HAL_COMP_Init()" since           */
-      /*       inverting input selection also enables the comparator 2.       */
-      __HAL_COMP_ENABLE(hcomp);
-
-      /* Set delay for COMP startup time */
-      if (hcomp->Instance == COMP1)
-      {
-        wait_loop_cycles = COMP1_START_DELAY_CPU_CYCLES;
-      }
-      else /* if (hcomp->Instance == COMP2) */
-      {
-        wait_loop_cycles = COMP2_START_DELAY_CPU_CYCLES;
-      }
-
-      /* Delay for COMP startup time.                                         */
-      /* Delay fixed to worst case: maximum CPU frequency                     */
-      while(wait_loop_index < wait_loop_cycles)
-      {
-        wait_loop_index++;
-      }
-
-      /* Update COMP state */
-      hcomp->State = HAL_COMP_STATE_BUSY;
-      
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Stop the comparator 
-  * @param  hcomp: COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    if(hcomp->State == HAL_COMP_STATE_BUSY)
-    {
-      /* Disable the selected comparator */
-      __HAL_COMP_DISABLE(hcomp);
-      
-      /* Update COMP state */
-      hcomp->State = HAL_COMP_STATE_READY;
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  
-  return status;
-}
-
-/**
-  * @brief  Enables the interrupt and starts the comparator
-  * @param  hcomp: COMP handle
-  * @retval HAL status.
-  */
-HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t extiline = 0;
-  
-  status = HAL_COMP_Start(hcomp);
-  if(status == HAL_OK)
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_TRIGGERMODE(hcomp->Init.TriggerMode));
-    
-    /* Get the Exti Line output configuration */
-    extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
-    
-    /* Configure the rising edge */
-    /* COMP TriggerMode set to COMP_TRIGGERMODE_IT_RISING or                  */
-    /* COMP_TRIGGERMODE_IT_RISING_FALLING.                                    */
-    if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_RISING) != RESET)
-    {
-      __HAL_COMP_EXTI_RISING_IT_ENABLE(extiline);
-    }
-    else
-    {
-      __HAL_COMP_EXTI_RISING_IT_DISABLE(extiline);
-    }
-    
-    /* Configure the falling edge */
-    /* COMP TriggerMode set to COMP_TRIGGERMODE_IT_FALLING or                 */
-    /* COMP_TRIGGERMODE_IT_RISING_FALLING.                                    */
-    if((hcomp->Init.TriggerMode & COMP_TRIGGERMODE_IT_FALLING) != RESET)
-    {
-      __HAL_COMP_EXTI_FALLING_IT_ENABLE(extiline);
-    }
-    else
-    {
-      __HAL_COMP_EXTI_FALLING_IT_DISABLE(extiline);
-    }
-    
-    /* Enable Exti interrupt mode */
-    __HAL_COMP_EXTI_ENABLE_IT(extiline);
-    /* Clear COMP Exti pending bit */
-    __HAL_COMP_EXTI_CLEAR_FLAG(extiline);
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Disable the interrupt and Stop the comparator 
-  * @param  hcomp: COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Disable the Exti Line interrupt mode */
-  __HAL_COMP_EXTI_DISABLE_IT(__HAL_COMP_GET_EXTI_LINE(hcomp->Instance));
-  
-  status = HAL_COMP_Stop(hcomp);
-  
-  return status;
-}
-
-/**
-  * @brief  Comparator IRQ Handler 
-  * @param  hcomp: COMP handle
-  * @retval HAL status
-  */
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp)
-{
-  uint32_t extiline = __HAL_COMP_GET_EXTI_LINE(hcomp->Instance);
-  
-  /* Check COMP Exti flag */
-  if(__HAL_COMP_EXTI_GET_FLAG(extiline) != RESET)
-  {
-    /* Clear COMP Exti pending bit */
-    __HAL_COMP_EXTI_CLEAR_FLAG(extiline);
-
-    /* COMP trigger user callback */
-    HAL_COMP_TriggerCallback(hcomp);    
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group3 Peripheral Control functions
- *  @brief   Peripheral Control functions
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the COMP 
-    management functions: Lock status, comparator output level check, IRQ
-    callback (in case of usage of comparator with interruption on ExtI line).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Lock the selected comparator configuration.
-  *         Caution: On STM32L1, HAL COMP lock is software lock only (not  
-  *         hardware lock as on some other STM32 devices)
-  * @param  hcomp: COMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the COMP handle allocation and lock status */
-  if((hcomp == HAL_NULL) || ((hcomp->State & COMP_STATE_BIT_LOCK) != RESET))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-    /* Set lock flag */
-    hcomp->State |= COMP_STATE_BIT_LOCK;
-  }
-  
-  return status; 
-}
-
-/**
-  * @brief  Return the output level (high or low) of the selected comparator. 
-  *         The output level depends on the selected polarity.
-  *           - Comparator output is low when the non-inverting input is at a lower
-  *             voltage than the inverting input
-  *           - Comparator output is high when the non-inverting input is at a higher
-  *             voltage than the inverting input
-  * @param  hcomp: COMP handle
-  * @retval Returns the selected comparator output level: COMP_OUTPUTLEVEL_LOW or COMP_OUTPUTLEVEL_HIGH.
-  *       
-  */
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp)
-{
-  uint32_t level = 0;
-  
-  /* Check the parameter */
-  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-  /* Read output level of the selected comparator */
-  if(READ_BIT(COMP->CSR, __COMP_CSR_CMPXOUT(hcomp)) == RESET)
-  {
-    level = COMP_OUTPUTLEVEL_LOW;
-  }
-  else
-  {
-    level = COMP_OUTPUTLEVEL_HIGH;
-  }
-  
-  return(level);
-}
-
-/**
-  * @brief  Comparator callback.
-  * @param  hcomp: COMP handle
-  * @retval None
-  */
-__weak void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_COMP_TriggerCallback should be implemented in the user file
-   */
-}
-
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the COMP state
-  * @param  hcomp : COMP handle
-  * @retval HAL state
-  */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp)
-{
-  /* Check the COMP handle allocation */
-  if(hcomp == HAL_NULL)
-  {
-    return HAL_COMP_STATE_RESET;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_COMP_ALL_INSTANCE(hcomp->Instance));
-
-  return hcomp->State;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_COMP_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,520 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_comp.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of COMP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_COMP_H
-#define __STM32L1xx_HAL_COMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup COMP
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup COMP_Exported_Types COMP Exported Types
-  * @{
-  */
-    
-/** 
-  * @brief  COMP Init structure definition  
-  */
-typedef struct
-{
-
-  uint32_t InvertingInput;        /*!< Selects the inverting input of the comparator.
-                                       This parameter can be a value of @ref COMP_InvertingInput
-                                       Note: Inverting input can be changed on the fly, while comparator is running.
-                                       Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded (On COMP1, inverting input is fixed to Vrefint). */
-
-  uint32_t NonInvertingInput;     /*!< Selects the non inverting input of the comparator.
-                                       This parameter can be a value of @ref COMPEx_NonInvertingInput */
-
-  uint32_t Output;                /*!< Selects the output redirection of the comparator.
-                                       This parameter can be a value of @ref COMP_Output
-                                       Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded. */
-
-  uint32_t Mode;                  /*!< Selects the operating consumption mode of the comparator
-                                       to adjust the speed/consumption.
-                                       This parameter can be a value of @ref COMP_Mode
-                                       Note: This feature is available on COMP2 only. If COMP1 is selected, this parameter is discarded. */
-                                         
-  uint32_t WindowMode;            /*!< Selects the window mode of the 2 comparators.
-                                       If enabled, non-inverting inputs of the 2 comparators are connected together and are using inputs of COMP2 only (COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP).
-                                       This parameter can be a value of @ref COMP_WindowMode
-                                       Note: This feature must be enabled from COMP2 instance. If COMP1 is selected, this parameter is discarded. */
-
-  uint32_t TriggerMode;           /*!< Selects the trigger mode of the comparator when using interruption on EXTI line (interrupt mode).
-                                       This parameter can be a value of @ref COMP_TriggerMode
-                                       Note: This feature is used with function "HAL_COMP_Start_IT()". In all other functions, this parameter is discarded. */
-
-  uint32_t NonInvertingInputPull; /*!< Selects the internal pulling resistor connected on non inverting input.
-                                       This parameter can be a value of @ref COMP_NonInvertingInputPull
-                                       Note: To avoid extra power consumption, only one resistor should be enabled at a time.
-                                       Note: This feature is available on COMP1 only. If COMP2 is selected, this parameter is discarded. */
-  
-}COMP_InitTypeDef;
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_COMP_STATE_RESET             = 0x00,    /*!< COMP not yet initialized or disabled             */
-  HAL_COMP_STATE_READY             = 0x01,    /*!< COMP initialized and ready for use               */
-  HAL_COMP_STATE_READY_LOCKED      = 0x11,    /*!< COMP initialized but the configuration is locked */
-  HAL_COMP_STATE_BUSY              = 0x02,    /*!< COMP is running                                  */
-  HAL_COMP_STATE_BUSY_LOCKED       = 0x12     /*!< COMP is running and the configuration is locked  */
-}HAL_COMP_StateTypeDef;
-
-/** 
-  * @brief  COMP Handle Structure definition  
-  */ 
-typedef struct
-{
-  COMP_TypeDef       *Instance;       /*!< Register base address    */
-  COMP_InitTypeDef   Init;            /*!< COMP required parameters */
-  HAL_LockTypeDef    Lock;            /*!< Locking object           */
-  __IO HAL_COMP_StateTypeDef  State;  /*!< COMP communication state */
-} COMP_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMP_Exported_Constants COMP Exported Constants
-  * @{
-  */
-
-/** @defgroup COMP_Output COMP Output
-  * @{
-  */
-#define COMP_OUTPUT_TIM2IC4                     ((uint32_t)0x00000000)                                      /*!< COMP2 output connected to TIM2 Input Capture 4 */
-#define COMP_OUTPUT_TIM2OCREFCLR                (                                        COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM2 OCREF Clear */
-#define COMP_OUTPUT_TIM3IC4                     (                    COMP_CSR_OUTSEL_1                    ) /*!< COMP2 output connected to TIM3 Input Capture 4 */
-#define COMP_OUTPUT_TIM3OCREFCLR                (                    COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM3 OCREF Clear */
-#define COMP_OUTPUT_TIM4IC4                     (COMP_CSR_OUTSEL_2                                        ) /*!< COMP2 output connected to TIM4 Input Capture 4 */
-#define COMP_OUTPUT_TIM4OCREFCLR                (COMP_CSR_OUTSEL_2                     | COMP_CSR_OUTSEL_0) /*!< COMP2 output connected to TIM4 OCREF Clear */
-#define COMP_OUTPUT_TIM10IC1                    (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1                    ) /*!< COMP2 output connected to TIM10 Input Capture 1 */
-#define COMP_OUTPUT_NONE                        (COMP_CSR_OUTSEL_2 | COMP_CSR_OUTSEL_1 | COMP_CSR_OUTSEL_0) /*!< COMP2 output is not connected to other peripherals */
-
-#define IS_COMP_OUTPUT(OUTPUT) (((OUTPUT) == COMP_OUTPUT_TIM2IC4)      || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM2OCREFCLR) || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM3IC4)      || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM3OCREFCLR) || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM4IC4)      || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM4OCREFCLR) || \
-                                ((OUTPUT) == COMP_OUTPUT_TIM10IC1)     || \
-                                ((OUTPUT) == COMP_OUTPUT_NONE)           )
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_InvertingInput COMP InvertingInput
-  * @{
-  */
-/* Inverting Input specific to COMP2 */
-#define COMP_INVERTINGINPUT_IO                  (                                      COMP_CSR_INSEL_0) /*!< External I/O (COMP2_INM connected to pin PB3) connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_VREFINT             (                   COMP_CSR_INSEL_1                   ) /*!< VREFINT connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_3_4VREFINT          (                   COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< 3/4 VREFINT connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_1_2VREFINT          (COMP_CSR_INSEL_2                                      ) /*!< 1/2 VREFINT connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_1_4VREFINT          (COMP_CSR_INSEL_2                    | COMP_CSR_INSEL_0) /*!< 1/4 VREFINT connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_DAC1                (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1                   ) /*!< DAC_OUT1 (PA4) connected to comparator 2 inverting input */
-#define COMP_INVERTINGINPUT_DAC2                (COMP_CSR_INSEL_2 | COMP_CSR_INSEL_1 | COMP_CSR_INSEL_0) /*!< DAC2_OUT (PA5) connected to comparator 2 inverting input */
-
-#define IS_COMP_INVERTINGINPUT(INPUT) (((INPUT) == COMP_INVERTINGINPUT_IO)         || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_VREFINT)    || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_3_4VREFINT) || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_1_2VREFINT) || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_1_4VREFINT) || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_DAC1)       || \
-                                       ((INPUT) == COMP_INVERTINGINPUT_DAC2)         )
-/**
-  * @}
-  */
-
-/** @defgroup COMP_Mode COMP Mode
-  * @{
-  */
-/* Please refer to the electrical characteristics in the device datasheet for
-   the power consumption values */
-#define COMP_MODE_LOWSPEED          ((uint32_t)0x00000000)  /*!< Low Speed */
-#define COMP_MODE_HIGHSPEED         COMP_CSR_SPEED          /*!< High Speed */
-
-#define IS_COMP_MODE(SPEED)    (((SPEED) == COMP_MODE_LOWSPEED) || \
-                                ((SPEED) == COMP_MODE_HIGHSPEED))
-/**
-  * @}
-  */
-
-/** @defgroup COMP_WindowMode COMP WindowMode
-  * @{
-  */
-#define COMP_WINDOWMODE_DISABLED               ((uint32_t)0x00000000)  /*!< Window mode disabled: COMP1 non-inverting input is independant */
-#define COMP_WINDOWMODE_ENABLED                COMP_CSR_WNDWE          /*!< Window mode enabled: COMP1 non-inverting input is no more accessible, even from ADC channel VCOMP) (connected to COMP2 non-inverting input) */
-
-#define IS_COMP_WINDOWMODE(WINDOWMODE) (((WINDOWMODE) == COMP_WINDOWMODE_DISABLED) || \
-                                        ((WINDOWMODE) == COMP_WINDOWMODE_ENABLED))
-/**
-  * @}
-  */
-
-/** @defgroup COMP_OutputLevel COMP OutputLevel
-  * @{
-  */ 
-/* Comparator output is low when the non-inverting input is at a lower        */
-/* voltage than the inverting input.                                          */
-#define COMP_OUTPUTLEVEL_LOW                   ((uint32_t)0x00000000)
-
-/* Comparator output is high when the non-inverting input is at a higher      */
-/* voltage than the inverting input.                                          */
-#define COMP_OUTPUTLEVEL_HIGH                  ((uint32_t)0x00000001)
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_TriggerMode COMP TriggerMode 
-  * @{
-  */
-#define COMP_TRIGGERMODE_NONE                  ((uint32_t)0x00000000)   /*!< No External Interrupt trigger detection */
-#define COMP_TRIGGERMODE_IT_RISING             ((uint32_t)0x00000001)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define COMP_TRIGGERMODE_IT_FALLING            ((uint32_t)0x00000002)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define COMP_TRIGGERMODE_IT_RISING_FALLING     ((uint32_t)0x00000003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-
-#define IS_COMP_TRIGGERMODE(MODE)  (((MODE) == COMP_TRIGGERMODE_NONE)             || \
-                                    ((MODE) == COMP_TRIGGERMODE_IT_RISING)        || \
-                                    ((MODE) == COMP_TRIGGERMODE_IT_FALLING)       || \
-                                    ((MODE) == COMP_TRIGGERMODE_IT_RISING_FALLING)  )
-/**
-  * @}
-  */ 
-
-/** @defgroup COMP_ExtiLineEvent COMP ExtiLineEvent
-  * @{
-  */
-#define COMP_EXTI_LINE_COMP1_EVENT             EXTI_RTSR_TR21  /*!< External interrupt line 21 Connected to COMP1 */
-#define COMP_EXTI_LINE_COMP2_EVENT             EXTI_RTSR_TR22  /*!< External interrupt line 22 Connected to COMP2 */
-
-/**
-  * @}
-  */
-
-/** @defgroup COMP_NonInvertingInputPull COMP NonInvertingInputPull
-  * @{
-  */
-#define COMP_NONINVERTINGINPUT_NOPULL           ((uint32_t)0x00000000)  /*!< No internal pull-up or pull-down resistor connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_10KPU            COMP_CSR_10KPU          /*!< Internal 10kOhm pull-up resistor connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_10KPD            COMP_CSR_10KPD          /*!< Internal 10kOhm pull-down resistor connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_400KPU           COMP_CSR_400KPU         /*!< Internal 400kOhm pull-up resistor connected to comparator non inverting input */
-#define COMP_NONINVERTINGINPUT_400KPD           COMP_CSR_400KPD         /*!< Internal 400kOhm pull-down resistor connected to comparator non inverting input */
-
-#define IS_COMP_NONINVERTINGINPUTPULL(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_NOPULL) || \
-                                              ((INPUT) == COMP_NONINVERTINGINPUT_10KPU)  || \
-                                              ((INPUT) == COMP_NONINVERTINGINPUT_10KPD)  || \
-                                              ((INPUT) == COMP_NONINVERTINGINPUT_400KPU) || \
-                                              ((INPUT) == COMP_NONINVERTINGINPUT_400KPD)   )
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup COMP_Exported_Macro COMP Exported Macro
-  * @{
-  */
-
-/** @brief Reset COMP handle state
-  * @param  __HANDLE__: COMP handle.
-  * @retval None
-  */
-#define __HAL_COMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_COMP_STATE_RESET)
-
-/**
-  * @brief Enables the specified comparator
-  * @param  __HANDLE__: COMP handle.
-  * @retval None.
-  */
-#define __HAL_COMP_ENABLE(__HANDLE__)                                          \
-  ( ( ((__HANDLE__)->Instance == COMP1)                                        \
-    )?                                                                         \
-     SET_BIT(COMP->CSR, COMP_CSR_CMP1EN)                                       \
-     :                                                                         \
-     MODIFY_REG(COMP->CSR, COMP_CSR_INSEL, (__HANDLE__)->Init.InvertingInput ) \
-  )
-
-/**
-  * @brief Disables the specified comparator
-  * @param  __HANDLE__: COMP handle.
-  * @retval None.
-  */
-#define __HAL_COMP_DISABLE(__HANDLE__)                                         \
-  ( ( ((__HANDLE__)->Instance == COMP1)                                        \
-    )?                                                                         \
-     CLEAR_BIT(COMP->CSR, COMP_CSR_CMP1EN)                                     \
-     :                                                                         \
-     CLEAR_BIT(COMP->CSR, COMP_CSR_INSEL)                                      \
-  )
-    
-    
-/** @brief  Checks whether the specified COMP flag is set or not.
-  * @param  __HANDLE__: specifies the COMP Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg COMP_FLAG_LOCK:  lock flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_COMP_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->CSR, (__FLAG__)) == (__FLAG__))   
-
-
-/**
-  * @brief Enable the Exti Line rising edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
-  *          This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval None.
-  */                                         
-#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (SET_BIT(EXTI->RTSR, (__EXTILINE__)))
-
-/**
-  * @brief  Disable the Exti Line rising edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
-  *         This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval None.
-  */                                         
-#define __HAL_COMP_EXTI_RISING_IT_DISABLE(__EXTILINE__) (CLEAR_BIT(EXTI->RTSR, (__EXTILINE__)))
-
-/**
-  * @brief Enable the Exti Line falling edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
-  *          This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval None.
-  */                                         
-#define __HAL_COMP_EXTI_FALLING_IT_ENABLE(__EXTILINE__) (SET_BIT(EXTI->FTSR, (__EXTILINE__)))
-
-/**
-  * @brief  Disable the Exti Line falling edge trigger.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
-  *         This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval None.
-  */                                         
-#define __HAL_COMP_EXTI_FALLING_IT_DISABLE(__EXTILINE__) (CLEAR_BIT(EXTI->FTSR, (__EXTILINE__)))
-
-/**
-  * @brief  Get the specified EXTI line for a comparator instance
-  * @param  __INSTANCE__: specifies the COMP instance.
-  * @retval value of @ref COMP_ExtiLineEvent
-  */
-#define __HAL_COMP_GET_EXTI_LINE(__INSTANCE__)                                 \
-  ( ( ((__INSTANCE__) == COMP1)                                                \
-    )?                                                                         \
-     (COMP_EXTI_LINE_COMP1_EVENT)                                              \
-     :                                                                         \
-     (COMP_EXTI_LINE_COMP2_EVENT)                                              \
-  )
-    
-/**
-  * @brief Enable the COMP Exti Line.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be enabled.
-  *          This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval None.
-  */                                         
-#define __HAL_COMP_EXTI_ENABLE_IT(__EXTILINE__) (SET_BIT(EXTI->IMR, (__EXTILINE__)))
-
-/**
-  * @brief Disable the COMP Exti Line.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to be disabled.
-  *          This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval None.
-  */
-#define __HAL_COMP_EXTI_DISABLE_IT(__EXTILINE__) (CLEAR_BIT(EXTI->IMR, (__EXTILINE__)))
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __FLAG__: specifies the COMP Exti sources to be checked.
-  *          This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval The state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_COMP_EXTI_GET_FLAG(__FLAG__) (READ_BIT(EXTI->PR, (__FLAG__)))
-     
-/**
-  * @brief Clear the COMP Exti flags.
-  * @param  __FLAG__: specifies the COMP Exti sources to be cleared.
-  *          This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval None.
-  */
-#define __HAL_COMP_EXTI_CLEAR_FLAG(__FLAG__)   (EXTI->PR = (__FLAG__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTILINE__: specifies the COMP Exti sources to trig.
-  *          This parameter can be a value of @ref COMP_ExtiLineEvent 
-  * @retval None
-  */
-#define __HAL_COMP_EXTI_GENERATE_SWIT(__EXTILINE__) (SET_BIT(EXTI->SWIER, (__EXTILINE__)))
-
-/**
-  * @}
-  */ 
-    
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup COMP_Private_Macro COMP Private Macro
-  * @{
-  */
-
-/**
-  * @brief Select the COMP register CSR bit CMPxOUT corresponding to the 
-  * selected COMP instance.
-  * @param __HANDLE__: COMP handle
-  * @retval Comparator register CSR bit COMP_CSR_CMP1OUT or COMP_CSR_CMP2OUT
-  */
-#define __COMP_CSR_CMPXOUT(__HANDLE__)                                         \
-  ( ( ((__HANDLE__)->Instance == COMP1)                                        \
-    )?                                                                         \
-     (COMP_CSR_CMP1OUT)                                                        \
-     :                                                                         \
-     (COMP_CSR_CMP2OUT)                                                        \
-  )
-
-/**
-  * @brief Verification of COMP state: enabled or disabled
-  * @param __HANDLE__: COMP handle
-  * @retval SET (COMP enabled) or RESET (COMP disabled)
-  */
-#define __COMP_IS_ENABLED(__HANDLE__)                                          \
-  ( ( ((__HANDLE__)->Instance == COMP1)                                        \
-    )?                                                                         \
-     (((READ_BIT(COMP->CSR , COMP_CSR_CMP1EN) == COMP_CSR_CMP1EN)              \
-      ) ? SET : RESET)                                                         \
-     :                                                                         \
-     (((READ_BIT(COMP->CSR , COMP_CSR_INSEL) != RESET)                         \
-      ) ? SET : RESET)                                                         \
-  )
-    
-/**
-  * @}
-  */ 
-
-    
-/* Include COMP HAL Extension module */
-#include "stm32l1xx_hal_comp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup COMP_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-/** @addtogroup COMP_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Init(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_DeInit (COMP_HandleTypeDef *hcomp);
-void HAL_COMP_MspInit(COMP_HandleTypeDef *hcomp);
-void HAL_COMP_MspDeInit(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup COMP_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Start(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Start_IT(COMP_HandleTypeDef *hcomp);
-HAL_StatusTypeDef HAL_COMP_Stop_IT(COMP_HandleTypeDef *hcomp);
-void HAL_COMP_IRQHandler(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup COMP_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef HAL_COMP_Lock(COMP_HandleTypeDef *hcomp);
-uint32_t HAL_COMP_GetOutputLevel(COMP_HandleTypeDef *hcomp);
-
-/* Callback in Interrupt mode */
-void HAL_COMP_TriggerCallback(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/* Peripheral State functions  **************************************************/
-/** @addtogroup COMP_Exported_Functions_Group4
-  * @{
-  */
-HAL_COMP_StateTypeDef HAL_COMP_GetState(COMP_HandleTypeDef *hcomp);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_COMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_comp_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,336 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_comp_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of COMP HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_COMP_EX_H
-#define __STM32L1xx_HAL_COMP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup COMPEx COMPEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup COMPEx_Exported_Constants COMPEx Exported Constants
-  * @{
-  */
-
-/** @defgroup COMPEx_NonInvertingInput COMPEx NonInvertingInput
-  * @{
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/* Non-inverting inputs specific to COMP2 */
-#define COMP_NONINVERTINGINPUT_PB4      RI_IOSWITCH_GR6_1       /*!< I/O pin PB4 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB5      RI_IOSWITCH_GR6_2       /*!< I/O pin PB5 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB6      RI_IOSWITCH_GR6_3       /*!< I/O pin PB6 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB7      RI_IOSWITCH_GR6_4       /*!< I/O pin PB7 connection to COMP2 non-inverting input */
-
-/* Non-inverting inputs specific to COMP1 */
-#define COMP_NONINVERTINGINPUT_NONE     ((uint32_t)0x00000000)  /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
-#define COMP_NONINVERTINGINPUT_PA0      RI_IOSWITCH_CH0         /*!< I/O pin PA0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA1      RI_IOSWITCH_CH1         /*!< I/O pin PA1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA2      RI_IOSWITCH_CH2         /*!< I/O pin PA2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA3      RI_IOSWITCH_CH3         /*!< I/O pin PA3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA4      RI_IOSWITCH_CH4         /*!< I/O pin PA4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA5      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA6      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA7      RI_IOSWITCH_CH7         /*!< I/O pin PA7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB0      RI_IOSWITCH_CH8         /*!< I/O pin PB0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB1      RI_IOSWITCH_CH9         /*!< I/O pin PB1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC0      RI_IOSWITCH_CH10        /*!< I/O pin PC0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC1      RI_IOSWITCH_CH11        /*!< I/O pin PC1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC2      RI_IOSWITCH_CH12        /*!< I/O pin PC2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC3      RI_IOSWITCH_CH13        /*!< I/O pin PC3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC4      RI_IOSWITCH_CH14        /*!< I/O pin PC4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC5      RI_IOSWITCH_CH15        /*!< I/O pin PC5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB12     RI_IOSWITCH_CH18        /*!< I/O pin PB12 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB13     RI_IOSWITCH_CH19        /*!< I/O pin PB13 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB14     RI_IOSWITCH_CH20        /*!< I/O pin PB14 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB15     RI_IOSWITCH_CH21        /*!< I/O pin PB15 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE7      RI_IOSWITCH_CH22        /*!< I/O pin PE7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE8      RI_IOSWITCH_CH23        /*!< I/O pin PE8 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE9      RI_IOSWITCH_CH24        /*!< I/O pin PE9 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE10     RI_IOSWITCH_CH25        /*!< I/O pin PE10 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF6      RI_IOSWITCH_CH27        /*!< I/O pin PF6 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF7      RI_IOSWITCH_CH28        /*!< I/O pin PF7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF8      RI_IOSWITCH_CH29        /*!< I/O pin PF8 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF9      RI_IOSWITCH_CH30        /*!< I/O pin PF9 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PF10     RI_IOSWITCH_CH31        /*!< I/O pin PF10 connection to COMP1 non-inverting input */
-
-#define COMP_NONINVERTINGINPUT_OPAMP1   COMP_NONINVERTINGINPUT_PA3  /*!< OPAMP1 output connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_OPAMP2   COMP_NONINVERTINGINPUT_PB0  /*!< OPAMP2 output connection to COMP1 non-inverting input */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD)
-#define COMP_NONINVERTINGINPUT_OPAMP3   COMP_NONINVERTINGINPUT_PC3  /*!< OPAMP3 output connection to COMP1 non-inverting input */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-   
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-/* Non-inverting inputs specific to COMP2 */
-#define COMP_NONINVERTINGINPUT_PB4      RI_IOSWITCH_GR6_1       /*!< I/O pin PB4 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB5      RI_IOSWITCH_GR6_2       /*!< I/O pin PB5 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB6      RI_IOSWITCH_GR6_3       /*!< I/O pin PB6 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB7      RI_IOSWITCH_GR6_4       /*!< I/O pin PB7 connection to COMP2 non-inverting input */
-
-/* Non-inverting inputs specific to COMP1 */
-#define COMP_NONINVERTINGINPUT_NONE     ((uint32_t)0x00000000)  /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
-#define COMP_NONINVERTINGINPUT_PA0      RI_IOSWITCH_CH0         /*!< I/O pin PA0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA1      RI_IOSWITCH_CH1         /*!< I/O pin PA1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA2      RI_IOSWITCH_CH2         /*!< I/O pin PA2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA3      RI_IOSWITCH_CH3         /*!< I/O pin PA3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA4      RI_IOSWITCH_CH4         /*!< I/O pin PA4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA5      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA6      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA7      RI_IOSWITCH_CH7         /*!< I/O pin PA7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB0      RI_IOSWITCH_CH8         /*!< I/O pin PB0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB1      RI_IOSWITCH_CH9         /*!< I/O pin PB1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC0      RI_IOSWITCH_CH10        /*!< I/O pin PC0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC1      RI_IOSWITCH_CH11        /*!< I/O pin PC1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC2      RI_IOSWITCH_CH12        /*!< I/O pin PC2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC3      RI_IOSWITCH_CH13        /*!< I/O pin PC3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC4      RI_IOSWITCH_CH14        /*!< I/O pin PC4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC5      RI_IOSWITCH_CH15        /*!< I/O pin PC5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB12     RI_IOSWITCH_CH18        /*!< I/O pin PB12 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB13     RI_IOSWITCH_CH19        /*!< I/O pin PB13 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB14     RI_IOSWITCH_CH20        /*!< I/O pin PB14 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB15     RI_IOSWITCH_CH21        /*!< I/O pin PB15 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE7      RI_IOSWITCH_CH22        /*!< I/O pin PE7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE8      RI_IOSWITCH_CH23        /*!< I/O pin PE8 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE9      RI_IOSWITCH_CH24        /*!< I/O pin PE9 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE10     RI_IOSWITCH_CH25        /*!< I/O pin PE10 connection to COMP1 non-inverting input */
-
-#define COMP_NONINVERTINGINPUT_OPAMP1   COMP_NONINVERTINGINPUT_PA3  /*!< OPAMP1 output connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_OPAMP2   COMP_NONINVERTINGINPUT_PB0  /*!< OPAMP2 output connection to COMP1 non-inverting input */
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */   
-   
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA)
-/* Non-inverting inputs specific to COMP2 */
-#define COMP_NONINVERTINGINPUT_PB4      RI_IOSWITCH_GR6_1       /*!< I/O pin PB4 connection to COMP2 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB5      RI_IOSWITCH_GR6_2       /*!< I/O pin PB5 connection to COMP2 non-inverting input */
-
-/* Non-inverting inputs specific to COMP1 */
-#define COMP_NONINVERTINGINPUT_NONE     ((uint32_t)0x00000000)  /*!< In case of window mode: No I/O pin connection to COMP1 non-inverting input. Instead, connection to COMP2 non-inverting input. */
-#define COMP_NONINVERTINGINPUT_PA0      RI_IOSWITCH_CH0         /*!< I/O pin PA0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA1      RI_IOSWITCH_CH1         /*!< I/O pin PA1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA2      RI_IOSWITCH_CH2         /*!< I/O pin PA2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA3      RI_IOSWITCH_CH3         /*!< I/O pin PA3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA4      RI_IOSWITCH_CH4         /*!< I/O pin PA4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA5      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA6      RI_IOSWITCH_CH5         /*!< I/O pin PA5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PA7      RI_IOSWITCH_CH7         /*!< I/O pin PA7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB0      RI_IOSWITCH_CH8         /*!< I/O pin PB0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB1      RI_IOSWITCH_CH9         /*!< I/O pin PB1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC0      RI_IOSWITCH_CH10        /*!< I/O pin PC0 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC1      RI_IOSWITCH_CH11        /*!< I/O pin PC1 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC2      RI_IOSWITCH_CH12        /*!< I/O pin PC2 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC3      RI_IOSWITCH_CH13        /*!< I/O pin PC3 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC4      RI_IOSWITCH_CH14        /*!< I/O pin PC4 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PC5      RI_IOSWITCH_CH15        /*!< I/O pin PC5 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB12     RI_IOSWITCH_CH18        /*!< I/O pin PB12 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB13     RI_IOSWITCH_CH19        /*!< I/O pin PB13 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB14     RI_IOSWITCH_CH20        /*!< I/O pin PB14 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PB15     RI_IOSWITCH_CH21        /*!< I/O pin PB15 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE7      RI_IOSWITCH_CH22        /*!< I/O pin PE7 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE8      RI_IOSWITCH_CH23        /*!< I/O pin PE8 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE9      RI_IOSWITCH_CH24        /*!< I/O pin PE9 connection to COMP1 non-inverting input */
-#define COMP_NONINVERTINGINPUT_PE10     RI_IOSWITCH_CH25        /*!< I/O pin PE10 connection to COMP1 non-inverting input */
-
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
-
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_NONE)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB12)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB13)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB14)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB15)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE8)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE9)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE10)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF8)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF9)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PF10)    )
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_NONE)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB12)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB13)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB14)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB15)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE8)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE9)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE10)    )
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA)
-#define IS_COMP_NONINVERTINGINPUT(INPUT) (((INPUT) == COMP_NONINVERTINGINPUT_PB4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_NONE)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA6)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PA7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC0)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC1)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC2)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC3)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC4)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PC5)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB12)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB13)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB14)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PB15)  || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE7)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE8)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE9)   || \
-                                          ((INPUT) == COMP_NONINVERTINGINPUT_PE10)    )
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup COMPEx_Private_Macro COMP Private Macro
-  * @{
-  */
-
-/**
-  * @brief Specifies whether Routing Interface (RI) needs to be configured for 
-  * switches of comparator non-inverting input.
-  * @param  __HANDLE__: COMP handle.
-  * @retval None.
-  */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__)                    \
-  (((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE) &&    \
-   (READ_BIT(COMP->CSR, COMP_CSR_SW1) == RESET)                            )
-#else
-#define __COMP_ROUTING_INTERFACE_TOBECONFIGURED(__HANDLE__)                    \
-  ((__HANDLE__)->Init.NonInvertingInput != COMP_NONINVERTINGINPUT_NONE)
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @}
-  */ 
-
-
-
-/* Exported functions --------------------------------------------------------*/
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_COMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,441 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cortex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   CORTEX HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the CORTEX:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *          
-  *  @verbatim    
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-
-    [..]  
-    *** How to configure Interrupts using Cortex HAL driver ***
-    ===========================================================
-    [..]     
-    This section provide functions allowing to configure the NVIC interrupts (IRQ).
-    The Cortex-M3 exceptions are managed by CMSIS functions.
-   
-    (#) Configure the NVIC Priority Grouping using HAL_NVIC_SetPriorityGrouping()
-        function according to the following table.
-
-     The table below gives the allowed values of the pre-emption priority and subpriority according
-     to the Priority Grouping configuration performed by HAL_NVIC_SetPriorityGrouping() function.
-       ==========================================================================================================================
-         NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
-       ==========================================================================================================================
-        NVIC_PRIORITYGROUP_0  |                0                  |            0-15             | 0 bits for pre-emption priority
-                              |                                   |                             | 4 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------
-        NVIC_PRIORITYGROUP_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
-                              |                                   |                             | 3 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
-                              |                                   |                             | 2 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
-                              |                                   |                             | 1 bits for subpriority
-       --------------------------------------------------------------------------------------------------------------------------    
-        NVIC_PRIORITYGROUP_4  |                0-15               |            0                | 4 bits for pre-emption priority
-                              |                                   |                             | 0 bits for subpriority                       
-       ==========================================================================================================================
-     (#)  Configure the priority of the selected IRQ Channels using HAL_NVIC_SetPriority() 
-
-     (#)  Enable the selected IRQ Channels using HAL_NVIC_EnableIRQ() 
-      
-
-     -@- When the NVIC_PRIORITYGROUP_0 is selected, IRQ pre-emption is no more possible. 
-         The pending IRQ priority will be managed only by the sub priority.
-   
-     -@- IRQ priority order (sorted by highest to lowest priority):
-        (+@) Lowest pre-emption priority
-        (+@) Lowest sub priority
-        (+@) Lowest hardware priority (IRQ number)
- 
-    [..]  
-    *** How to configure Systick using Cortex HAL driver ***
-    ========================================================
-    [..]
-    Setup SysTick Timer for 1 msec interrupts.
-           
-   (+) The HAL_SYSTICK_Config()function calls the SysTick_Config() function which
-       is a CMSIS function that:
-        (++) Configures the SysTick Reload register with value passed as function parameter.
-        (++) Configures the SysTick IRQ priority to the lowest value (0x0F).
-        (++) Resets the SysTick Counter register.
-        (++) Configures the SysTick Counter clock source to be Core Clock Source (HCLK).
-        (++) Enables the SysTick Interrupt.
-        (++) Starts the SysTick Counter.
-    
-   (+) You can change the SysTick Clock source to be HCLK_Div8 by calling the macro
-       __HAL_CORTEX_SYSTICKCLK_CONFIG(SYSTICK_CLKSOURCE_HCLK_DIV8) just after the
-       HAL_SYSTICK_Config() function call. The __HAL_CORTEX_SYSTICKCLK_CONFIG() macro is defined
-       inside the stm32l1xx_hal_cortex.h file.
-
-   (+) You can change the SysTick IRQ priority by calling the
-       HAL_NVIC_SetPriority(SysTick_IRQn,...) function just after the HAL_SYSTICK_Config() function 
-       call. The HAL_NVIC_SetPriority() call the NVIC_SetPriority() function which is a CMSIS function.
-
-   (+) To adjust the SysTick time base, use the following formula:
-                            
-       Reload Value = SysTick Counter Clock (Hz) x  Desired Time base (s)
-       (++) Reload Value is the parameter to be passed for HAL_SYSTICK_Config() function
-       (++) Reload Value should not exceed 0xFFFFFF
-   
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CORTEX CORTEX
-  * @brief CORTEX HAL module driver
-  * @{
-  */
-
-#ifdef HAL_CORTEX_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Functions CORTEX Exported Functions
-  * @{
-  */
-
-
-/** @defgroup CORTEX_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]
-      This section provide the Cortex HAL driver functions allowing to configure Interrupts
-      Systick functionalities 
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Sets the priority grouping field (pre-emption priority and subpriority)
-  *         using the required unlock sequence.
-  * @param  PriorityGroup: The priority grouping bits length. 
-  *         This parameter can be one of the following values:
-  *         @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
-  *                                    4 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
-  *                                    3 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
-  *                                    2 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
-  *                                    1 bits for subpriority
-  *         @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
-  *                                    0 bits for subpriority
-  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
-  *         The pending IRQ priority will be managed only by the subpriority. 
-  * @retval None
-  */
-void HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
-  
-  /* Set the PRIGROUP[10:8] bits according to the PriorityGroup parameter value */
-  NVIC_SetPriorityGrouping(PriorityGroup);
-}
-
-/**
-  * @brief  Sets the priority of an interrupt.
-  * @param  IRQn: External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
-  * @param  PreemptPriority: The pre-emption priority for the IRQn channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority 
-  * @param  SubPriority: the subpriority level for the IRQ channel.
-  *         This parameter can be a value between 0 and 15
-  *         A lower priority value indicates a higher priority.          
-  * @retval None
-  */
-void HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-  uint32_t prioritygroup = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_NVIC_SUB_PRIORITY(SubPriority));
-  assert_param(IS_NVIC_PREEMPTION_PRIORITY(PreemptPriority));
-  
-  prioritygroup = NVIC_GetPriorityGrouping();
-  
-  NVIC_SetPriority(IRQn, NVIC_EncodePriority(prioritygroup, PreemptPriority, SubPriority));
-}
-
-/**
-  * @brief  Enables a device specific interrupt in the NVIC interrupt controller.
-  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
-  *         function should be called before. 
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xx.h))
-  * @retval None
-  */
-void HAL_NVIC_EnableIRQ(IRQn_Type IRQn)
-{
-  /* Enable interrupt */
-  NVIC_EnableIRQ(IRQn);
-}
-
-/**
-  * @brief  Disables a device specific interrupt in the NVIC interrupt controller.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval None
-  */
-void HAL_NVIC_DisableIRQ(IRQn_Type IRQn)
-{
-  /* Disable interrupt */
-  NVIC_DisableIRQ(IRQn);
-}
-
-/**
-  * @brief  Initiates a system reset request to reset the MCU.
-  * @retval None
-  */
-void HAL_NVIC_SystemReset(void)
-{
-  /* System Reset */
-  NVIC_SystemReset();
-}
-
-/**
-  * @brief  Initializes the System Timer and its interrupt, and starts the System Tick Timer.
-  *         Counter is in free running mode to generate periodic interrupts.
-  * @param  TicksNumb: Specifies the ticks Number of ticks between two interrupts.
-  * @retval status:  - 0  Function succeeded.
-  *                  - 1  Function failed.
-  */
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb)
-{
-   return SysTick_Config(TicksNumb);
-}
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_Exported_Functions_Group2 Peripheral Control functions
- *  @brief    Cortex control functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================
-    [..]
-      This subsection provides a set of functions allowing to control the CORTEX
-      (NVIC, SYSTICK) functionalities. 
- 
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Gets the priority grouping field from the NVIC Interrupt Controller.
-  * @retval Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field)
-  */
-uint32_t HAL_NVIC_GetPriorityGrouping(void)
-{
-  /* Get the PRIGROUP[10:8] field value */
-  return NVIC_GetPriorityGrouping();
-}
-
-/**
-  * @brief  Gets the priority of an interrupt.
-  * @param  IRQn: External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))
-  * @param   PriorityGroup: the priority grouping bits length.
-  *         This parameter can be one of the following values:
-  *           @arg NVIC_PRIORITYGROUP_0: 0 bits for pre-emption priority
-  *                                      4 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_1: 1 bits for pre-emption priority
-  *                                      3 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_2: 2 bits for pre-emption priority
-  *                                      2 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_3: 3 bits for pre-emption priority
-  *                                      1 bits for subpriority
-  *           @arg NVIC_PRIORITYGROUP_4: 4 bits for pre-emption priority
-  *                                      0 bits for subpriority
-  * @param  pPreemptPriority: Pointer on the Preemptive priority value (starting from 0).
-  * @param  pSubPriority: Pointer on the Subpriority value (starting from 0).
-  * @retval None
-  */
-void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
-{
-  /* Check the parameters */
-  assert_param(IS_NVIC_PRIORITY_GROUP(PriorityGroup));
- /* Get priority for Cortex-M system or device specific interrupts */
-  NVIC_DecodePriority(NVIC_GetPriority(IRQn), PriorityGroup, pPreemptPriority, pSubPriority);
-}
-
-/**
-  * @brief  Sets Pending bit of an external interrupt.
-  * @param  IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval None
-  */
-void HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Set interrupt pending */
-  NVIC_SetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Gets Pending Interrupt (reads the pending register in the NVIC 
-  *         and returns the pending bit for the specified interrupt).
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Return 1 if pending else 0 */
-  return NVIC_GetPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Clears the pending bit of an external interrupt.
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval None
-  */
-void HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn)
-{ 
-  /* Clear pending interrupt */
-  NVIC_ClearPendingIRQ(IRQn);
-}
-
-/**
-  * @brief Gets active interrupt ( reads the active register in NVIC and returns the active bit).
-  * @param IRQn External interrupt number
-  *         This parameter can be an enumerator of IRQn_Type enumeration
-  *         (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32l1xxxx.h))  
-  * @retval status: - 0  Interrupt status is not pending.
-  *                 - 1  Interrupt status is pending.
-  */
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn)
-{ 
-  /* Return 1 if active else 0 */
-  return NVIC_GetActive(IRQn);
-}
-
-/**
-  * @brief  Configures the SysTick clock source.
-  * @param  CLKSource: specifies the SysTick clock source.
-  *         This parameter can be one of the following values:
-  *             @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *             @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-void HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource)
-{
-  /* Check the parameters */
-  assert_param(IS_SYSTICK_CLK_SOURCE(CLKSource));
-  if (CLKSource == SYSTICK_CLKSOURCE_HCLK)
-  {
-    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;
-  }
-  else
-  {
-    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;
-  }
-}
-
-/**
-  * @brief  This function handles SYSTICK interrupt request.
-  * @retval None
-  */
-void HAL_SYSTICK_IRQHandler(void)
-{
-  HAL_SYSTICK_Callback();
-}
-
-/**
-  * @brief  SYSTICK callback.
-  * @retval None
-  */
-__weak void HAL_SYSTICK_Callback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SYSTICK_Callback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CORTEX_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cortex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,220 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cortex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of CORTEX HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CORTEX_H
-#define __STM32L1xx_HAL_CORTEX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CORTEX
-  * @{
-  */ 
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CORTEX_Exported_Constants CORTEX Exported Constants
-  * @{
-  */
-
-
-/** @defgroup CORTEX_Preemption_Priority_Group  CORTEX Preemption Priority Group 
-  * @{
-  */
-
-#define NVIC_PRIORITYGROUP_0         ((uint32_t)0x00000007) /*!< 0 bits for pre-emption priority
-                                                                 4 bits for subpriority */
-#define NVIC_PRIORITYGROUP_1         ((uint32_t)0x00000006) /*!< 1 bits for pre-emption priority
-                                                                 3 bits for subpriority */
-#define NVIC_PRIORITYGROUP_2         ((uint32_t)0x00000005) /*!< 2 bits for pre-emption priority
-                                                                 2 bits for subpriority */
-#define NVIC_PRIORITYGROUP_3         ((uint32_t)0x00000004) /*!< 3 bits for pre-emption priority
-                                                                 1 bits for subpriority */
-#define NVIC_PRIORITYGROUP_4         ((uint32_t)0x00000003) /*!< 4 bits for pre-emption priority
-                                                                 0 bits for subpriority */
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source CORTEX SysTick clock source
-  * @{
-  */
-#define SYSTICK_CLKSOURCE_HCLK_DIV8    ((uint32_t)0x00000000)
-#define SYSTICK_CLKSOURCE_HCLK         ((uint32_t)0x00000004)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported Macros -----------------------------------------------------------*/
-/** @defgroup CORTEX_Exported_Macros CORTEX Exported Macros
-  * @{
-  */
-
-/** @defgroup CORTEX_Preemption_Priority_Group_Macro  CORTEX Preemption Priority Group 
-  * @{
-  */
-#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PRIORITYGROUP_0) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_1) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_2) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_3) || \
-                                       ((GROUP) == NVIC_PRIORITYGROUP_4))
-
-#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
-
-/**
-  * @}
-  */
-
-/** @defgroup CORTEX_SysTick_clock_source_Macro_Exported CORTEX SysTick clock source
-  * @{
-  */
-
-/** @brief Configures the SysTick clock source.
-  * @param __CLKSRC__: specifies the SysTick clock source.
-  *   This parameter can be one of the following values:
-  *     @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source.
-  *     @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
-  * @retval None
-  */
-#define __HAL_CORTEX_SYSTICKCLK_CONFIG(__CLKSRC__)                             \
-                            do {                                               \
-                                 if ((__CLKSRC__) == SYSTICK_CLKSOURCE_HCLK)   \
-                                  {                                            \
-                                    SysTick->CTRL |= SYSTICK_CLKSOURCE_HCLK;   \
-                                  }                                            \
-                                 else                                          \
-                                    SysTick->CTRL &= ~SYSTICK_CLKSOURCE_HCLK;  \
-                                } while(0)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup CORTEX_Private_Macros CORTEX Private Macros
-  * @{
-  */  
-                                  
-/** @defgroup CORTEX_SysTick_clock_source_Macro_Private CORTEX SysTick clock source
-  * @{
-  */                       
-#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SYSTICK_CLKSOURCE_HCLK) || \
-                                       ((SOURCE) == SYSTICK_CLKSOURCE_HCLK_DIV8))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CORTEX_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group1
-  * @{
-  */  
-/* Initialization and de-initialization functions *****************************/
-void     HAL_NVIC_SetPriorityGrouping(uint32_t PriorityGroup);
-void     HAL_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority);
-void     HAL_NVIC_EnableIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_DisableIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_SystemReset(void);
-uint32_t HAL_SYSTICK_Config(uint32_t TicksNumb);
-/**
-  * @}
-  */
-
-/** @addtogroup CORTEX_Exported_Functions_Group2
-  * @{
-  */ 
-/* Peripheral Control functions ***********************************************/
-uint32_t HAL_NVIC_GetPriorityGrouping(void);
-void     HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority);
-uint32_t HAL_NVIC_GetPendingIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_SetPendingIRQ(IRQn_Type IRQn);
-void     HAL_NVIC_ClearPendingIRQ(IRQn_Type IRQn);
-uint32_t HAL_NVIC_GetActive(IRQn_Type IRQn);
-void     HAL_SYSTICK_CLKSourceConfig(uint32_t CLKSource);
-void     HAL_SYSTICK_IRQHandler(void);
-void     HAL_SYSTICK_Callback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CORTEX_H */
- 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,339 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_crc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   CRC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Cyclic Redundancy Check (CRC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The CRC HAL driver can be used as follows:
-
-      (#) Enable CRC AHB clock using __CRC_CLK_ENABLE();
-
-      (#) Use HAL_CRC_Accumulate() function to compute the CRC value of 
-          a 32-bit data buffer using combination of the previous CRC value
-          and the new one.
-
-      (#) Use HAL_CRC_Calculate() function to compute the CRC Value of 
-          a new 32-bit data buffer. This function resets the CRC computation  
-          unit before starting the computation to avoid getting wrong CRC values.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRC CRC
-  * @brief CRC HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_CRC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Functions CRC Exported Functions
-  * @{
-  */
-
-/** @defgroup CRC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
-  ==============================================================================
-            ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the CRC according to the specified parameters 
-          in the CRC_InitTypeDef and create the associated handle
-      (+) DeInitialize the CRC peripheral
-      (+) Initialize the CRC MSP
-      (+) DeInitialize CRC MSP 
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRC according to the specified
-  *         parameters in the CRC_InitTypeDef and creates the associated handle.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc)
-{
-  /* Check the CRC handle allocation */
-  if(hcrc == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
-  if(hcrc->State == HAL_CRC_STATE_RESET)
-  {
-    /* Init the low level hardware */
-    HAL_CRC_MspInit(hcrc);
-  }
-  
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-   
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the CRC peripheral.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc)
-{
-  /* Check the CRC handle allocation */
-  if(hcrc == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_CRC_ALL_INSTANCE(hcrc->Instance));
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* DeInit the low level hardware */
-  HAL_CRC_MspDeInit(hcrc);
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hcrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRC MSP.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @retval None
-  */
-__weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the CRC MSP.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @retval None
-  */
-__weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief    management functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Compute the 32-bit CRC value of 32-bit data buffer,
-          using combination of the previous CRC value and the new one.
-      (+) Compute the 32-bit CRC value of 32-bit data buffer,
-          independently of the previous CRC value.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Computes the 32-bit CRC of 32-bit data buffer using combination
-  *         of the previous CRC value and the new one.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @param  pBuffer: pointer to the buffer containing the data to be computed
-  * @param  BufferLength: length of the buffer to be computed (defined in word, 4 bytes)
-  * @retval 32-bit CRC
-  */
-uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t index = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hcrc);
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* Enter Data to the CRC calculator */
-  for(index = 0; index < BufferLength; index++)
-  {
-    hcrc->Instance->DR = pBuffer[index];
-  }
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcrc);
-
-  /* Return the CRC computed value */
-  return hcrc->Instance->DR;
-}
-
-/**
-  * @brief  Computes the 32-bit CRC of 32-bit data buffer independently
-  *         of the previous CRC value.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @param  pBuffer: Pointer to the buffer containing the data to be computed
-  * @param  BufferLength: Length of the buffer to be computed (defined in word, 4 bytes)
-  * @retval 32-bit CRC
-  */
-uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength)
-{
-  uint32_t index = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hcrc); 
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_BUSY;
-
-  /* Reset CRC Calculation Unit */
-  __HAL_CRC_DR_RESET(hcrc);
-
-  /* Enter Data to the CRC calculator */
-  for(index = 0; index < BufferLength; index++)
-  {
-    hcrc->Instance->DR = pBuffer[index];
-  }
-
-  /* Change CRC peripheral state */
-  hcrc->State = HAL_CRC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcrc);
-
-  /* Return the CRC computed value */
-  return hcrc->Instance->DR;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRC_Exported_Functions_Group3 Peripheral State functions 
- *  @brief    Peripheral State functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the CRC state.
-  * @param  hcrc: pointer to a CRC_HandleTypeDef structure that contains
-  *         the configuration information for CRC
-  * @retval HAL state
-  */
-HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
-{
-  return hcrc->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CRC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_crc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,192 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_crc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of CRC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CRC_H
-#define __STM32L1xx_HAL_CRC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Types CRC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  CRC HAL State Structure definition  
-  */ 
-typedef enum
-{
-  HAL_CRC_STATE_RESET     = 0x00,  /*!< CRC not yet initialized or disabled */
-  HAL_CRC_STATE_READY     = 0x01,  /*!< CRC initialized and ready for use   */
-  HAL_CRC_STATE_BUSY      = 0x02,  /*!< CRC internal process is ongoing     */
-  HAL_CRC_STATE_TIMEOUT   = 0x03,  /*!< CRC timeout state                   */
-  HAL_CRC_STATE_ERROR     = 0x04   /*!< CRC error state                     */
-
-}HAL_CRC_StateTypeDef;
-
-/** 
-  * @brief  CRC handle Structure definition
-  */ 
-typedef struct
-{
-  CRC_TypeDef                 *Instance;  /*!< Register base address   */
-
-  HAL_LockTypeDef             Lock;       /*!< CRC locking object      */
-
-  __IO HAL_CRC_StateTypeDef   State;      /*!< CRC communication state */
-
-}CRC_HandleTypeDef;
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRC_Exported_Macros CRC Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRC handle state
-  * @param  __HANDLE__: CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_CRC_STATE_RESET)
-
-/**
-  * @brief  Resets CRC Data Register.
-  * @param  __HANDLE__: CRC handle
-  * @retval None
-  */
-#define __HAL_CRC_DR_RESET(__HANDLE__)            (SET_BIT((__HANDLE__)->Instance->CR,CRC_CR_RESET))
-
-/**
-  * @brief Stores a 8-bit data in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
-  * @param __VALUE__: 8-bit value to be stored in the ID register
-  * @retval None
-  */
-#define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (MODIFY_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))
-
-/**
-  * @brief Returns the 8-bit data stored in the Independent Data(ID) register.
-  * @param __HANDLE__: CRC handle
-  * @retval 8-bit value of the ID register 
-  */
-#define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRC_Exported_Functions
-  * @{
-  */ 
-
-/** @addtogroup CRC_Exported_Functions_Group1
-  * @{
-  */ 
-
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef     HAL_CRC_Init(CRC_HandleTypeDef *hcrc);
-HAL_StatusTypeDef     HAL_CRC_DeInit (CRC_HandleTypeDef *hcrc);
-void                  HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc);
-void                  HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRC_Exported_Functions_Group2
-  * @{
-  */ 
-
-/** @addtogroup CRC_Exported_Functions_Group3
-  ** @{
-  */ 
-/* Peripheral Control functions  ************************************************/
-uint32_t              HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-uint32_t              HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength);
-
-/* Peripheral State functions  **************************************************/
-HAL_CRC_StateTypeDef  HAL_CRC_GetState(CRC_HandleTypeDef *hcrc);
-
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CRC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2111 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cryp.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   CRYP HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Cryptography (CRYP) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Processing functions by algorithm using polling mode
-  *           + Processing functions by algorithm using interrupt mode
-  *           + Processing functions by algorithm using DMA mode
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The CRYP HAL driver can be used as follows:
-
-      (#)Initialize the CRYP low level resources by implementing the HAL_CRYP_MspInit():
-         (##) Enable the CRYP interface clock using __CRYP_CLK_ENABLE()
-         (##) In case of using interrupts (e.g. HAL_CRYP_AESECB_Encrypt_IT())
-             (+) Configure the CRYP interrupt priority using HAL_NVIC_SetPriority()
-             (+) Enable the CRYP IRQ handler using HAL_NVIC_EnableIRQ()
-             (+) In CRYP IRQ handler, call HAL_CRYP_IRQHandler()
-         (##) In case of using DMA to control data transfer (e.g. HAL_CRYP_AESECB_Encrypt_DMA())
-             (+) Enable the DMA2 interface clock using 
-                 (++) __DMA2_CLK_ENABLE()
-             (+) Configure and enable two DMA Channels one for managing data transfer from
-                 memory to peripheral (input channel) and another channel for managing data
-                 transfer from peripheral to memory (output channel)
-             (+) Associate the initialized DMA handle to the CRYP DMA handle
-                 using  __HAL_LINKDMA()
-             (+) Configure the priority and enable the NVIC for the transfer complete
-                 interrupt on the two DMA Streams. The output stream should have higher
-                 priority than the input stream.
-                 (++) HAL_NVIC_SetPriority()
-                 (++) HAL_NVIC_EnableIRQ()
-    
-      (#)Initialize the CRYP HAL using HAL_CRYP_Init(). This function configures mainly:
-         (##) The data type: 1-bit, 8-bit, 16-bit and 32-bit
-         (##) The encryption/decryption key.
-         (##) The initialization vector (counter). It is not used ECB mode.
-    
-      (#)Three processing (encryption/decryption) functions are available:
-         (##) Polling mode: encryption and decryption APIs are blocking functions
-              i.e. they process the data and wait till the processing is finished
-              e.g. HAL_CRYP_AESCBC_Encrypt()
-         (##) Interrupt mode: encryption and decryption APIs are not blocking functions
-              i.e. they process the data under interrupt
-              e.g. HAL_CRYP_AESCBC_Encrypt_IT()
-         (##) DMA mode: encryption and decryption APIs are not blocking functions
-              i.e. the data transfer is ensured by DMA
-              e.g. HAL_CRYP_AESCBC_Encrypt_DMA()
-    
-      (#)When the processing function is called for the first time after HAL_CRYP_Init()
-         the CRYP peripheral is initialized and processes the buffer in input.
-         At second call, the processing function performs an append of the already
-         processed buffer.
-         When a new data block is to be processed, call HAL_CRYP_Init() then the
-         processing function.
-         
-      (#)Call HAL_CRYP_DeInit() to deinitialize the CRYP peripheral.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRYP CRYP
-  * @brief CRYP HAL module driver.
-  * @{
-  */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup CRYP_Private_Defines CRYP Private Defines
-  * @{
-  */
-
-#define  CRYP_ALGO_CHAIN_MASK         (AES_CR_MODE | AES_CR_CHMOD)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/** @defgroup CRYP_Private_Functions CRYP Private Functions
-  * @{
-  */
-
-static HAL_StatusTypeDef  CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp);
-static void               CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector);
-static void               CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key);
-static HAL_StatusTypeDef  CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout);
-static void               CRYP_DMAInCplt(DMA_HandleTypeDef *hdma);
-static void               CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma);
-static void               CRYP_DMAError(DMA_HandleTypeDef *hdma);
-static void               CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr);
-
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Functions CRYP Exported Functions
-  * @{
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the CRYP according to the specified parameters 
-          in the CRYP_InitTypeDef and creates the associated handle
-      (+) DeInitialize the CRYP peripheral
-      (+) Initialize the CRYP MSP
-      (+) DeInitialize CRYP MSP 
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYP according to the specified
-  *         parameters in the CRYP_InitTypeDef and creates the associated handle.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp)
-{ 
-  /* Check the CRYP handle allocation */
-  if(hcryp == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_CRYP_DATATYPE(hcryp->Init.DataType));
-  
-  if(hcryp->State == HAL_CRYP_STATE_RESET)
-  {
-    /* Init the low level hardware */
-    HAL_CRYP_MspInit(hcryp);
-  }
-  
-  /* Check if AES already enabled */
-  if (HAL_IS_BIT_CLR(AES->CR, AES_CR_EN))
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;  
-
-    /* Set the data type*/
-    MODIFY_REG(AES->CR, AES_CR_DATATYPE, hcryp->Init.DataType);
-    
-    /* Reset CrypInCount and CrypOutCount */
-    hcryp->CrypInCount = 0;
-    hcryp->CrypOutCount = 0;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Set the default CRYP phase */
-    hcryp->Phase = HAL_CRYP_PHASE_READY;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* The Datatype selection must be changed if the AES is disabled. Writing these bits while the AES is */
-    /* enabled is forbidden to avoid unpredictable AES behavior.*/
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-
-}
-
-/**
-  * @brief  DeInitializes the CRYP peripheral. 
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* Check the CRYP handle allocation */
-  if(hcryp == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_BUSY;
-  
-  /* Set the default CRYP phase */
-  hcryp->Phase = HAL_CRYP_PHASE_READY;
-  
-  /* Reset CrypInCount and CrypOutCount */
-  hcryp->CrypInCount = 0;
-  hcryp->CrypOutCount = 0;
-  
-  /* Disable the CRYP Peripheral Clock */
-  __HAL_CRYP_DISABLE();
-  
-  /* DeInit the low level hardware: CLOCK, NVIC.*/
-  HAL_CRYP_MspDeInit(hcryp);
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_RESET;
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP MSP.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_MspInit can be implemented in the user file */
-}
-
-/**
-  * @brief  DeInitializes CRYP MSP.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp)
-{
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_MspDeInit can be implemented in the user file */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group2 AES processing functions 
- *  @brief   processing functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### AES processing functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Encrypt plaintext using AES algorithm in different chaining modes
-      (+) Decrypt cyphertext using AES algorithm in different chaining modes
-    [..]  Three processing functions are available:
-      (+) Polling mode
-      (+) Interrupt mode
-      (+) DMA mode
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout: Specify Timeout value 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-
-  /* Check that data aligned on u32 and Size multiple of 16*/
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE();
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE();
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode
-  *         then encrypt pPlainData. The cypher data are available in pCypherData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE();
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Plain Data and Get Cypher Data */
-    if(CRYP_ProcessData(hcryp, pPlainData, Size, pCypherData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE();
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Cypher Data and Get Plain Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout: Specify Timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if(hcryp->State != HAL_CRYP_STATE_RESET)
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Enable CRYP */
-      __HAL_CRYP_ENABLE();
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Write Cypher Data and Get Plain Data */
-    if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode
-  *         then decrypted pCypherData. The cypher data are available in pPlainData
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Timeout: Specify Timeout value   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout)
-{  
-  /* Process Locked */
-  __HAL_LOCK(hcryp);
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if initialization phase has already been performed */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->Phase == HAL_CRYP_PHASE_READY))
-  {
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Set the key */
-    CRYP_SetKey(hcryp, hcryp->Init.pKey);
-    
-    /* Reset the CHMOD & MODE bits */
-    CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-    
-    /* Set the CRYP peripheral in AES CTR decryption mode */
-    __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
-    
-    /* Set the Initialization Vector */
-    CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
-    
-    /* Set the phase */
-    hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-  }
-  
-  /* Write Cypher Data and Get Plain Data */
-  if(CRYP_ProcessData(hcryp, pCypherData, Size, pPlainData, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-  
-  /* Change the CRYP state */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hcryp);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(AES_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(AES_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pPlainData;
-    hcryp->pCrypOutBuffPtr = pCypherData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(AES_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);   
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(AES_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC decryption mode using IT.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);   
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(AES_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    /* Get the buffer addresses and sizes */
-    hcryp->CrypInCount = Size;
-    hcryp->pCrypInBuffPtr = pCypherData;
-    hcryp->pCrypOutBuffPtr = pPlainData;
-    hcryp->CrypOutCount = Size;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CTR decryption mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);   
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Enable Interrupts */
-    __HAL_CRYP_ENABLE_IT(AES_IT_CC);
-    
-    /* Enable CRYP */
-    __HAL_CRYP_ENABLE();
-    
-    /* Get the last input data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;    
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    /* Return function status */
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES ECB mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CBC mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16.
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pPlainData;
-    outputaddr = (uint32_t)pCypherData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES ECB decryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{  
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES ECB decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CBC encryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16 bytes
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Reset the CHMOD & MODE bits */
-      CLEAR_BIT(AES->CR, CRYP_ALGO_CHAIN_MASK);
-      
-      /* Set the CRYP peripheral in AES CBC decryption mode (with key derivation) */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @brief  Initializes the CRYP peripheral in AES CTR decryption mode using DMA.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  pCypherData: Pointer to the cyphertext buffer (aligned on u32)
-  * @param  Size: Length of the plaintext buffer, must be a multiple of 16
-  * @param  pPlainData: Pointer to the plaintext buffer (aligned on u32)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData)
-{  
-  uint32_t inputaddr = 0, outputaddr = 0;
-  
-  /* Check that data aligned on u32 */
-  if((((uint32_t)pPlainData & (uint32_t)0x00000003) != 0) || (((uint32_t)pCypherData & (uint32_t)0x00000003) != 0) || ((Size & (uint16_t)0x000F) != 0))
-  {
-    /* Process Locked */
-    __HAL_UNLOCK(hcryp);
-
-    /* Return function status */
-    return HAL_ERROR;
-  }
-  
-  /* Check if HAL_CRYP_Init has been called */
-  if ((hcryp->State != HAL_CRYP_STATE_RESET) && (hcryp->State == HAL_CRYP_STATE_READY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hcryp);
-    
-    inputaddr  = (uint32_t)pCypherData;
-    outputaddr = (uint32_t)pPlainData;
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_BUSY;
-    
-    /* Check if initialization phase has already been performed */
-    if(hcryp->Phase == HAL_CRYP_PHASE_READY)
-    {
-      /* Set the key */
-      CRYP_SetKey(hcryp, hcryp->Init.pKey);
-      
-      /* Set the CRYP peripheral in AES CTR mode */
-      __HAL_CRYP_SET_MODE(CRYP_CR_ALGOMODE_AES_CTR_DECRYPT);
-      
-      /* Set the Initialization Vector */
-      CRYP_SetInitVector(hcryp, hcryp->Init.pInitVect);
-      
-      /* Set the phase */
-      hcryp->Phase = HAL_CRYP_PHASE_PROCESS;
-    }
-    
-    /* Set the input and output addresses and start DMA transfer */ 
-    CRYP_SetDMAConfig(hcryp, inputaddr, Size, outputaddr);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Return function status */
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;   
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group3 DMA callback functions 
- *  @brief   DMA callback functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### DMA callback functions  #####
-  ==============================================================================  
-    [..]  This section provides DMA callback functions:
-      (+) DMA Input data transfer complete
-      (+) DMA Output data transfer complete
-      (+) DMA error
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  CRYP error callback.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
- __weak void HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_ErrorCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Input transfer completed callback.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_InCpltCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Output transfer completed callback.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* NOTE : This function should not be modified; when the callback is needed, 
-            the HAL_CRYP_OutCpltCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group4 CRYP IRQ handler 
- *  @brief   CRYP IRQ handler.
- *
-@verbatim   
-  ==============================================================================
-                ##### CRYP IRQ handler management #####
-  ==============================================================================  
-[..]  This section provides CRYP IRQ handler function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  This function handles CRYP interrupt request.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-void HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp)
-{
-  /* Check if error occurred*/
-  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_ERR) != RESET)
-  {
-    if (__HAL_CRYP_GET_FLAG(AES_FLAG_RDERR) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_RDERR);
-    }
-    
-    if (__HAL_CRYP_GET_FLAG(AES_FLAG_WRERR) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_WRERR);
-    }
-    
-    if (__HAL_CRYP_GET_FLAG(AES_FLAG_CCF) != RESET)
-    {
-      __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF);
-    }
-    
-    hcryp->State= HAL_CRYP_STATE_ERROR;
-    /* Disable Computation Complete Interrupt */
-    __HAL_CRYP_DISABLE_IT(AES_IT_CC);
-    __HAL_CRYP_DISABLE_IT(AES_IT_ERR);
-    
-    HAL_CRYP_ErrorCallback(hcryp);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    return;
-  }
-  
-  /* Check if computation complete interrupt was enabled*/
-  if (__HAL_CRYP_GET_IT_SOURCE(hcryp, AES_IT_CC) != RESET)
-  {
-    /* Clear CCF Flag */
-    __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF);
-  
-    CRYP_EncryptDecrypt_IT(hcryp);
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_Exported_Functions_Group5 Peripheral State functions 
- *  @brief   Peripheral State functions. 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the CRYP state.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL state
-  */
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp)
-{
-  return hcryp->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup CRYP_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  IT function called under interruption context to continue encryption or decryption
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef CRYP_EncryptDecrypt_IT(CRYP_HandleTypeDef *hcryp)
-{
-  uint32_t inputaddr = 0, outputaddr = 0;
-
-  /* Get the last Output data adress */
-  outputaddr = (uint32_t)hcryp->pCrypOutBuffPtr;
-  
-  /* Read the Output block from the Output Register */
-  *(uint32_t*)(outputaddr) = AES->DOUTR;
-  outputaddr+=4;
-  *(uint32_t*)(outputaddr) = AES->DOUTR;
-  outputaddr+=4;
-  *(uint32_t*)(outputaddr) = AES->DOUTR;
-  outputaddr+=4;
-  *(uint32_t*)(outputaddr) = AES->DOUTR;
-  
-  hcryp->pCrypOutBuffPtr += 16;
-  hcryp->CrypOutCount -= 16;
-  
-  /* Check if all input text is encrypted or decrypted */
-  if(hcryp->CrypOutCount == 0)
-  {
-    /* Disable Computation Complete Interrupt */
-    __HAL_CRYP_DISABLE_IT(AES_IT_CC);
-    __HAL_CRYP_DISABLE_IT(AES_IT_ERR);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hcryp);
-    
-    /* Change the CRYP state */
-    hcryp->State = HAL_CRYP_STATE_READY;
-    
-    /* Call computation complete callback */
-    HAL_CRYPEx_ComputationCpltCallback(hcryp);
-  }
-  else /* Process the rest of input text */
-  {
-    /* Get the last Intput data adress */
-    inputaddr = (uint32_t)hcryp->pCrypInBuffPtr;
-    
-    /* Write the Input block in the Data Input register */
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    hcryp->pCrypInBuffPtr += 16;
-    hcryp->CrypInCount -= 16;      
-  }
-  return HAL_OK;
-}
-/**
-  * @brief  DMA CRYP Input Data process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma)  
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Disable the DMA transfer for input request  */
-  CLEAR_BIT(AES->CR, AES_CR_DMAINEN);
-  
-  /* Call input data transfer complete callback */
-  HAL_CRYP_InCpltCallback(hcryp);
-}
-
-/**
-  * @brief  DMA CRYP Output Data process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma)
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Disable the DMA transfer for output request by resetting the DMAOUTEN bit
-     in the DMACR register */
-  CLEAR_BIT(AES->CR, AES_CR_DMAOUTEN);
-
-  /* Clear CCF Flag */
-  __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF);
-
-  /* Disable CRYP */
-  __HAL_CRYP_DISABLE();
-  
-  /* Change the CRYP state to ready */
-  hcryp->State = HAL_CRYP_STATE_READY;
-  
-  /* Call output data transfer complete callback */
-  HAL_CRYP_OutCpltCallback(hcryp);
-}
-
-/**
-  * @brief  DMA CRYP communication error callback. 
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void CRYP_DMAError(DMA_HandleTypeDef *hdma)
-{
-  CRYP_HandleTypeDef* hcryp = (CRYP_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  hcryp->State= HAL_CRYP_STATE_ERROR;
-  HAL_CRYP_ErrorCallback(hcryp);
-}
-
-/**
-  * @brief  Writes the Key in Key registers. 
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Key: Pointer to Key buffer
-  * @note Key must be written as little endian.
-  *         If Key pointer points at address n, 
-  *         n[15:0] contains key[96:127], 
-  *         (n+4)[15:0] contains key[64:95], 
-  *         (n+8)[15:0] contains key[32:63] and 
-  *         (n+12)[15:0] contains key[0:31]
-  * @retval None
-  */
-static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key)
-{  
-  uint32_t keyaddr = (uint32_t)Key;
-  
-  AES->KEYR3 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4;
-  AES->KEYR2 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4;
-  AES->KEYR1 = __REV(*(uint32_t*)(keyaddr));
-  keyaddr+=4;
-  AES->KEYR0 = __REV(*(uint32_t*)(keyaddr));  
-}
-
-/**
-  * @brief  Writes the InitVector/InitCounter in IV registers. 
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  InitVector: Pointer to InitVector/InitCounter buffer
-  * @note Init Vector must be written as little endian.
-  *         If Init Vector pointer points at address n, 
-  *         n[15:0] contains Vector[96:127], 
-  *         (n+4)[15:0] contains Vector[64:95], 
-  *         (n+8)[15:0] contains Vector[32:63] and 
-  *         (n+12)[15:0] contains Vector[0:31]
-  * @retval None
-  */
-static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector)
-{
-  uint32_t ivaddr = (uint32_t)InitVector;
-  
-  AES->IVR3 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4;
-  AES->IVR2 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4;
-  AES->IVR1 = __REV(*(uint32_t*)(ivaddr));
-  ivaddr+=4;
-  AES->IVR0 = __REV(*(uint32_t*)(ivaddr));
-}
-
-/**
-  * @brief  Process Data: Writes Input data in polling mode and reads the output data
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  Input: Pointer to the Input buffer
-  * @param  Ilength: Length of the Input buffer, must be a multiple of 16.
-  * @param  Output: Pointer to the returned buffer
-  * @param  Timeout: Specify Timeout value  
-  * @retval None
-  */
-static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  
-  uint32_t index = 0;
-  uint32_t inputaddr  = (uint32_t)Input;
-  uint32_t outputaddr = (uint32_t)Output;
-  
-  for(index=0; (index < Ilength); index += 16)
-  {
-    /* Write the Input block in the Data Input register */
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR  = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    AES->DINR = *(uint32_t*)(inputaddr);
-    inputaddr+=4;
-    
-    /* Get timeout */
-    tickstart = HAL_GetTick();
-    
-    while(HAL_IS_BIT_CLR(AES->SR, AES_SR_CCF))
-    {    
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Change state */
-          hcryp->State = HAL_CRYP_STATE_TIMEOUT;
-          
-          /* Process Unlocked */          
-          __HAL_UNLOCK(hcryp);
-          
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    /* Clear CCF Flag */
-    __HAL_CRYP_CLEAR_FLAG(hcryp, AES_CLEARFLAG_CCF);
-    
-    /* Read the Output block from the Data Output Register */
-    *(uint32_t*)(outputaddr) = AES->DOUTR;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = AES->DOUTR;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = AES->DOUTR;
-    outputaddr+=4;
-    *(uint32_t*)(outputaddr) = AES->DOUTR;
-    outputaddr+=4;
-  }
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the DMA configuration and start the DMA transfer
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @param  inputaddr: address of the Input buffer
-  * @param  Size: Size of the Input buffer, must be a multiple of 16.
-  * @param  outputaddr: address of the Output buffer
-  * @retval None
-  */
-static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr)
-{
-  /* Set the CRYP DMA transfer complete callback */
-  hcryp->hdmain->XferCpltCallback = CRYP_DMAInCplt;
-  /* Set the DMA error callback */
-  hcryp->hdmain->XferErrorCallback = CRYP_DMAError;
-  
-  /* Set the CRYP DMA transfer complete callback */
-  hcryp->hdmaout->XferCpltCallback = CRYP_DMAOutCplt;
-  /* Set the DMA error callback */
-  hcryp->hdmaout->XferErrorCallback = CRYP_DMAError;
-
-  /* Enable the DMA In DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmain, inputaddr, (uint32_t)&AES->DINR, Size/4);
-
-  /* Enable the DMA Out DMA Stream */
-  HAL_DMA_Start_IT(hcryp->hdmaout, (uint32_t)&AES->DOUTR, outputaddr, Size/4);
-
-  /* Enable In and Out DMA requests */
-  SET_BIT(AES->CR, (AES_CR_DMAINEN | AES_CR_DMAOUTEN));
-
-  /* Enable CRYP */
-  __HAL_CRYP_ENABLE();
-}
-
-/**
-  * @}
-  */
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,411 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cryp.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of CRYP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CRYP_H
-#define __STM32L1xx_HAL_CRYP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-   
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRYP
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup CRYP_Exported_Types CRYP Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  CRYP Configuration Structure definition  
-  */
-typedef struct
-{  
-  uint32_t DataType;    /*!< 32-bit data, 16-bit data, 8-bit data or 1-bit string.
-                             This parameter can be a value of @ref CRYP_Data_Type */
-  
-  uint8_t* pKey;        /*!< The key used for encryption/decryption */
-  
-  uint8_t* pInitVect;   /*!< The initialization vector used also as initialization
-                             counter in CTR mode */
-  
-}CRYP_InitTypeDef;
-
-/** 
-  * @brief HAL CRYP State structures definition  
-  */ 
-typedef enum
-{
-  HAL_CRYP_STATE_RESET             = 0x00,  /*!< CRYP not yet initialized or disabled  */
-  HAL_CRYP_STATE_READY             = 0x01,  /*!< CRYP initialized and ready for use    */
-  HAL_CRYP_STATE_BUSY              = 0x02,  /*!< CRYP internal processing is ongoing   */
-  HAL_CRYP_STATE_TIMEOUT           = 0x03,  /*!< CRYP timeout state                    */
-  HAL_CRYP_STATE_ERROR             = 0x04   /*!< CRYP error state                      */ 
-    
-}HAL_CRYP_STATETypeDef;
-
-/** 
-  * @brief HAL CRYP phase structures definition  
-  */ 
-typedef enum
-{
-  HAL_CRYP_PHASE_READY             = 0x01,    /*!< CRYP peripheral is ready for initialization. */
-  HAL_CRYP_PHASE_PROCESS           = 0x02,    /*!< CRYP peripheral is in processing phase */
-}HAL_PhaseTypeDef;
-
-/** 
-  * @brief  CRYP handle Structure definition  
-  */ 
-typedef struct
-{
-  CRYP_InitTypeDef            Init;             /*!< CRYP required parameters */
-
-  uint8_t                     *pCrypInBuffPtr;  /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-  uint8_t                     *pCrypOutBuffPtr; /*!< Pointer to CRYP processing (encryption, decryption,...) buffer */
-
-  __IO uint16_t               CrypInCount;      /*!< Counter of inputed data */
-
-  __IO uint16_t               CrypOutCount;     /*!< Counter of outputed data */
-
-  HAL_StatusTypeDef           Status;           /*!< CRYP peripheral status */
-
-  HAL_PhaseTypeDef            Phase;            /*!< CRYP peripheral phase */
-
-  DMA_HandleTypeDef           *hdmain;          /*!< CRYP In DMA handle parameters */
-
-  DMA_HandleTypeDef           *hdmaout;         /*!< CRYP Out DMA handle parameters */
-
-  HAL_LockTypeDef             Lock;             /*!< CRYP locking object */
-
-  __IO  HAL_CRYP_STATETypeDef State;            /*!< CRYP peripheral state */
-
-}CRYP_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Constants CRYP Exported Constants
-  * @{
-  */
-
-/** @defgroup CRYP_Data_Type CRYP Data Type
-  * @{
-  */
-#define CRYP_DATATYPE_32B         ((uint32_t)0x00000000)
-#define CRYP_DATATYPE_16B         AES_CR_DATATYPE_0
-#define CRYP_DATATYPE_8B          AES_CR_DATATYPE_1
-#define CRYP_DATATYPE_1B          AES_CR_DATATYPE
-
-#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DATATYPE_32B) || \
-                                    ((DATATYPE) == CRYP_DATATYPE_16B) || \
-                                    ((DATATYPE) == CRYP_DATATYPE_8B)  || \
-                                    ((DATATYPE) == CRYP_DATATYPE_1B))  
-/**
-  * @}
-  */
-
-/** @defgroup CRYP_AlgoModeDirection CRYP Algo Mode Direction
-  * @{
-  */ 
-#define CRYP_CR_ALGOMODE_DIRECTION              (uint32_t)(AES_CR_MODE|AES_CR_CHMOD)
-
-#define CRYP_CR_ALGOMODE_AES_ECB_ENCRYPT        ((uint32_t)0x00000000)
-#define CRYP_CR_ALGOMODE_AES_ECB_KEYDERDECRYPT  (AES_CR_MODE)
-#define CRYP_CR_ALGOMODE_AES_CBC_ENCRYPT        (AES_CR_CHMOD_0)
-#define CRYP_CR_ALGOMODE_AES_CBC_KEYDERDECRYPT  ((uint32_t)(AES_CR_CHMOD_0|AES_CR_MODE))
-#define CRYP_CR_ALGOMODE_AES_CTR_ENCRYPT        (AES_CR_CHMOD_1)
-#define CRYP_CR_ALGOMODE_AES_CTR_DECRYPT        ((uint32_t)(AES_CR_CHMOD_1 | AES_CR_MODE_1))
-/**
-  * @}
-  */
-  
-/** @defgroup CRYP_AES_Interrupts AES Interrupts
-  * @{
-  */ 
-#define AES_IT_CC                          AES_CR_CCIE  /*!< Computation Complete interrupt */
-#define AES_IT_ERR                         AES_CR_ERRIE /*!< Error interrupt                */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup CRYP_AES_Flags AES Flags
-  * @{
-  */ 
-#define AES_FLAG_CCF                       AES_SR_CCF    /*!< Computation Complete Flag */
-#define AES_FLAG_RDERR                     AES_SR_RDERR  /*!< Read Error Flag           */
-#define AES_FLAG_WRERR                     AES_SR_WRERR  /*!< Write Error Flag          */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup CRYP_AES_Clear_Flags AES Clear Flags
-  * @{
-  */ 
-#define AES_CLEARFLAG_CCF                       AES_CR_CCFC   /*!< Computation Complete Flag Clear */
-#define AES_CLEARFLAG_RDERR                     AES_CR_ERRC   /*!< Read Error Clear           */
-#define AES_CLEARFLAG_WRERR                     AES_CR_ERRC   /*!< Write Error Clear          */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup CRYP_Exported_Macros CRYP Exported Macros
-  * @{
-  */
-
-/** @brief Reset CRYP handle state
-  * @param  __HANDLE__: specifies the CRYP Handle.
-  * @retval None
-  */
-#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
-
-/**
-  * @brief  Enable/Disable the CRYP peripheral.
-  * @retval None
-  */
-#define __HAL_CRYP_ENABLE()                   SET_BIT(AES->CR, AES_CR_EN)
-#define __HAL_CRYP_DISABLE()                  CLEAR_BIT(AES->CR, AES_CR_EN)
-
-/**
-  * @brief  Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC,...
-  * @param  __MODE__: The algorithm mode.
-  * @retval None
-  */
-#define __HAL_CRYP_SET_MODE(__MODE__)             SET_BIT(AES->CR, (__MODE__))
-
-
-/** @brief  Check whether the specified CRYP flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg AES_FLAG_CCF   : Computation Complete Flag
-  *            @arg AES_FLAG_RDERR : Read Error Flag
-  *            @arg AES_FLAG_WRERR : Write Error Flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_CRYP_GET_FLAG(__FLAG__)         ((AES->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the CRYP pending flag.
-  * @param  __HANDLE__: specifies the CRYP handle.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *            @arg AES_CLEARFLAG_CCF   : Computation Complete Clear Flag
-  *            @arg AES_CLEARFLAG_RDERR : Read Error Clear
-  *            @arg AES_CLEARFLAG_WRERR : Write Error Clear
-  * @retval None
-  */
-#define __HAL_CRYP_CLEAR_FLAG(__HANDLE__, __FLAG__) SET_BIT(AES->CR, (__FLAG__))
-
-/**
-  * @brief  Enable the CRYP interrupt.
-  * @param  __INTERRUPT__: CRYP Interrupt.
-  * @retval None
-  */
-#define __HAL_CRYP_ENABLE_IT(__INTERRUPT__)   SET_BIT(AES->CR, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the CRYP interrupt.
-  * @param  __INTERRUPT__: CRYP interrupt.
-  * @retval None
-  */
-#define __HAL_CRYP_DISABLE_IT(__INTERRUPT__)  CLEAR_BIT(AES->CR, (__INTERRUPT__))
-
-/** @brief  Checks if the specified CRYP interrupt source is enabled or disabled.
-  * @param __HANDLE__: CRYP handle
-  * @param __INTERRUPT__: CRYP interrupt source to check
-  *         This parameter can be one of the following values:
-  *            @arg AES_IT_CC   : Computation Complete interrupt
-  *            @arg AES_IT_ERR : Error interrupt (used for RDERR and WRERR)
-  * @retval State of interruption (SET or RESET)
-  */
-#define __HAL_CRYP_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) \
-    (( (AES->CR & (__INTERRUPT__)) == (__INTERRUPT__)       \
-     )? SET : RESET                                         \
-    )
-         
-/** @brief  Clear the CRYP pending IT.
-  * @param  __HANDLE__: specifies the CRYP handle.
-  * @param  __IT__: specifies the IT to clear.
-  *         This parameter can be one of the following values:
-  *            @arg AES_CLEARFLAG_CCF   : Computation Complete Clear Flag
-  *            @arg AES_CLEARFLAG_RDERR : Read Error Clear
-  *            @arg AES_CLEARFLAG_WRERR : Write Error Clear
-  * @retval None
-  */
-#define __HAL_CRYP_CLEAR_IT(__HANDLE__, __IT__) SET_BIT(AES->CR, (__IT__))
-
-/**
-  * @}
-  */
-
-/* Include CRYP HAL Extension module */
-#include "stm32l1xx_hal_cryp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRYP_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRYP_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization/de-initialization functions *********************************/
-HAL_StatusTypeDef     HAL_CRYP_Init(CRYP_HandleTypeDef *hcryp);
-HAL_StatusTypeDef     HAL_CRYP_DeInit(CRYP_HandleTypeDef *hcryp);
-
-/* MSP functions  *************************************************************/
-void                  HAL_CRYP_MspInit(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_MspDeInit(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group2
-  * @{
-  */
-
-/* AES encryption/decryption using polling  ***********************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout);
-
-/* AES encryption/decryption using interrupt  *********************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/* AES encryption/decryption using DMA  ***************************************/
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData);
-HAL_StatusTypeDef     HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group3
-  * @{
-  */
-
-/* CallBack functions  ********************************************************/
-void                  HAL_CRYP_InCpltCallback(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_OutCpltCallback(CRYP_HandleTypeDef *hcryp);
-void                  HAL_CRYP_ErrorCallback(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group4
-  * @{
-  */
-
-/* Processing functions  ********************************************************/
-void                  HAL_CRYP_IRQHandler(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup CRYP_Exported_Functions_Group5
-  * @{
-  */
-
-/* Peripheral State functions  **************************************************/
-HAL_CRYP_STATETypeDef HAL_CRYP_GetState(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CRYP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,118 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cryp_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   CRYPEx HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Cryptography (CRYP) extension peripheral:
-  *           + Computation completed callback.
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-#ifdef HAL_CRYP_MODULE_ENABLED
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup CRYPEx CRYPEx
-  * @brief CRYP HAL Extended module driver.
-  * @{
-  */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup CRYPEx_Exported_Functions CRYPEx Exported Functions
-  * @{
-  */
-
-
-/** @defgroup CRYPEx_Exported_Functions_Group1 Extended features functions 
- *  @brief    Extended features functions. 
- *
-@verbatim   
- ===============================================================================
-                 ##### Extended features functions #####
- =============================================================================== 
-    [..]  This section provides callback functions:
-      (+) Computation completed.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Computation completed callbacks.
-  * @param  hcryp: pointer to a CRYP_HandleTypeDef structure that contains
-  *         the configuration information for CRYP module
-  * @retval None
-  */
-__weak void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_CRYP_ComputationCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_CRYP_MODULE_ENABLED */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_cryp_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_cryp_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of CRYPEx HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_CRYP_EX_H
-#define __STM32L1xx_HAL_CRYP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-   
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup CRYPEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup CRYPEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup CRYPEx_Exported_Functions_Group1
-  * @{
-  */
-
-/* CallBack functions  ********************************************************/
-void HAL_CRYPEx_ComputationCpltCallback(CRYP_HandleTypeDef *hcryp);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE*/
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_CRYP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,963 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dac.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following 
-  *         functionalities of the Digital to Analog Converter (DAC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State and Errors functions      
-  *     
-  *
-  @verbatim      
-  ==============================================================================
-                      ##### DAC Peripheral features #####
-  ==============================================================================
-    [..]        
-      *** DAC Channels ***
-      ====================  
-    [..]  
-    The device integrates two 12-bit Digital Analog Converters that can 
-    be used independently or simultaneously (dual mode):
-      (#) DAC channel1 with DAC_OUT1 (PA4) as output
-      (#) DAC channel2 with DAC_OUT2 (PA5) as output
-      
-      *** DAC Triggers ***
-      ====================
-    [..]
-    Digital to Analog conversion can be non-triggered using DAC_Trigger_None
-    and DAC_OUT1/DAC_OUT2 is available once writing to DHRx register. 
-    [..] 
-    Digital to Analog conversion can be triggered by:
-      (#) External event: EXTI Line 9 (any GPIOx_Pin9) using DAC_Trigger_Ext_IT9.
-          The used pin (GPIOx_Pin9) must be configured in input mode.
-  
-      (#) Timers TRGO: TIM2, TIM4, TIM6, TIM7, TIM9
-          (DAC_Trigger_T2_TRGO, DAC_Trigger_T4_TRGO...)
-  
-      (#) Software using DAC_Trigger_Software
-  
-      *** DAC Buffer mode feature ***
-      =============================== 
-      [..] 
-      Each DAC channel integrates an output buffer that can be used to 
-      reduce the output impedance, and to drive external loads directly
-      without having to add an external operational amplifier.
-      To enable, the output buffer use  
-      sConfig.DAC_OutputBuffer = DAC_OutputBuffer_Enable;
-      [..]           
-      (@) Refer to the device datasheet for more details about output 
-          impedance value with and without output buffer.
-            
-       *** DAC wave generation feature ***
-       =================================== 
-       [..]     
-       Both DAC channels can be used to generate
-         (#) Noise wave 
-         (#) Triangle wave
-            
-       *** DAC data format ***
-       =======================
-       [..]   
-       The DAC data format can be:
-         (#) 8-bit right alignment using DAC_ALIGN_8B_R
-         (#) 12-bit left alignment using DAC_ALIGN_12B_L
-         (#) 12-bit right alignment using DAC_ALIGN_12B_R
-  
-       *** DAC data value to voltage correspondence ***  
-       ================================================ 
-       [..] 
-       The analog output voltage on each DAC channel pin is determined
-       by the following equation: 
-       DAC_OUTx = VREF+ * DOR / 4095
-       with  DOR is the Data Output Register
-          VEF+ is the input voltage reference (refer to the device datasheet)
-        e.g. To set DAC_OUT1 to 0.7V, use
-          Assuming that VREF+ = 3.3V, DAC_OUT1 = (3.3 * 868) / 4095 = 0.7V
-  
-       *** DMA requests  ***
-       =====================
-       [..]    
-       A DMA1 request can be generated when an external trigger (but not
-       a software trigger) occurs if DMA1 requests are enabled using
-       HAL_DAC_Start_DMA()
-       [..]
-       DMA1 requests are mapped as following:
-         (#) DAC channel1 : mapped on DMA1 channel2 which must be 
-             already configured
-         (#) DAC channel2 : mapped on DMA1 channel3 which must be 
-             already configured
-       
-    -@- For Dual mode and specific signal (Triangle and noise) generation please 
-        refer to Extension Features Driver description        
-  
-      
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]          
-      (+) DAC APB clock must be enabled to get write access to DAC
-          registers using HAL_DAC_Init()
-      (+) Configure DAC_OUTx (DAC_OUT1: PA4, DAC_OUT2: PA5) in analog mode.
-      (+) Configure the DAC channel using HAL_DAC_ConfigChannel() function.
-      (+) Enable the DAC channel using HAL_DAC_Start() or HAL_DAC_Start_DMA functions
-
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start() 
-       (+) To read the DAC last data output value value, use the HAL_DAC_GetValue() function.
-       (+) Stop the DAC peripheral using HAL_DAC_Stop()
-       
-     *** DMA mode IO operation ***    
-     ==============================
-     [..]    
-       (+) Start the DAC peripheral using HAL_DAC_Start_DMA(), at this stage the user specify the length 
-           of data to be transferred at each end of conversion
-       (+) At the middle of data transfer HAL_DAC_ConvHalfCpltCallbackCh1()or HAL_DAC_ConvHalfCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_ConvHalfCpltCallbackCh1 or HAL_DAC_ConvHalfCpltCallbackCh2
-       (+) At The end of data transfer HAL_DAC_ConvCpltCallbackCh1()or HAL_DAC_ConvCpltCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_ConvCpltCallbackCh1 or HAL_DAC_ConvCpltCallbackCh2
-       (+) In case of transfer Error, HAL_DAC_ErrorCallbackCh1() function is executed and user can 
-           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
-       (+) In case of DMA underrun, DAC interruption triggers and execute internal function HAL_DAC_IRQHandler.
-           HAL_DAC_DMAUnderrunCallbackCh1()or HAL_DAC_DMAUnderrunCallbackCh2()  
-           function is executed and user can add his own code by customization of function pointer 
-           HAL_DAC_DMAUnderrunCallbackCh1 or HAL_DAC_DMAUnderrunCallbackCh2
-           add his own code by customization of function pointer HAL_DAC_ErrorCallbackCh1
-       (+) Stop the DAC peripheral using HAL_DAC_Stop_DMA()
-
-     *** DAC HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in DAC HAL driver.
-       
-      (+) __HAL_DAC_ENABLE : Enable the DAC peripheral
-      (+) __HAL_DAC_DISABLE : Disable the DAC peripheral
-      (+) __HAL_DAC_CLEAR_FLAG: Clear the DAC's pending flags
-      (+) __HAL_DAC_GET_FLAG: Get the selected DAC's flag status
-      
-     [..]
-      (@) You can refer to the DAC HAL driver header file for more useful macros  
-   
- @endverbatim    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DAC DAC
-  * @brief DAC driver modules
-  * @{
-  */ 
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DAC_Private_Functions DAC Private Functions
-  * @{
-  */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma);
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma); 
-
-/**
-  * @}
-  */
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Functions DAC Exported Functions
-  * @{
-  */
-
-/** @defgroup DAC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
-  ==============================================================================
-              ##### Initialization and de-initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize and configure the DAC. 
-      (+) De-initialize the DAC. 
-         
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the DAC peripheral according to the specified parameters
-  *         in the DAC_InitStruct.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac)
-{ 
-  /* Check DAC handle */
-  if(hdac == HAL_NULL)
-  {
-     return HAL_ERROR;
-  }
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-  
-  if(hdac->State == HAL_DAC_STATE_RESET)
-  {  
-    /* Init the low level hardware */
-    HAL_DAC_MspInit(hdac);
-  }
-  
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-  
-  /* Initialize the DAC state*/
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac)
-{
-  /* Check DAC handle */
-  if(hdac == HAL_NULL)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_DAC_ALL_INSTANCE(hdac->Instance));
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  /* DeInit the low level hardware */
-  HAL_DAC_MspDeInit(hdac);
-
-  /* Set DAC error code to none */
-  hdac->ErrorCode = HAL_DAC_ERROR_NONE;
-
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdac);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DeInitializes the DAC MSP.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.  
-  * @retval None
-  */
-__weak void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group2 IO operation functions
- *  @brief    IO operation functions 
- *
-@verbatim   
-  ==============================================================================
-             ##### IO operation functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-                     
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  uint32_t tmp1 = 0, tmp2 = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the Peripharal */
-  __HAL_DAC_ENABLE(hdac, Channel);
-  
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN1;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL1;
-    /* Check if software trigger enabled */
-    if((tmp1 ==  DAC_CR_TEN1) && (tmp2 ==  DAC_CR_TSEL1))
-    {
-      /* Enable the selected DAC software conversion */
-      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG1);
-    }
-  }
-  else
-  {
-    tmp1 = hdac->Instance->CR & DAC_CR_TEN2;
-    tmp2 = hdac->Instance->CR & DAC_CR_TSEL2;    
-    /* Check if software trigger enabled */
-    if((tmp1 == DAC_CR_TEN2) && (tmp2 == DAC_CR_TSEL2))
-    {
-      /* Enable the selected DAC software conversion*/
-      SET_BIT(hdac->Instance->SWTRIGR, DAC_SWTRIGR_SWTRIG2);
-    }
-  }
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-    
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Disable the Peripheral */
-  __HAL_DAC_DISABLE(hdac, Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables DAC and starts conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @param  pData: The destination peripheral Buffer address.
-  * @param  Length: The length of data to be transferred from memory to DAC peripheral
-  * @param  Alignment: Specifies the data alignment for DAC channel.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment)
-{
-  uint32_t tmpreg = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Set the DMA transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferCpltCallback = DAC_DMAConvCpltCh1;
-
-    /* Set the DMA half transfer complete callback for channel1 */
-    hdac->DMA_Handle1->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh1;
-
-    /* Set the DMA error callback for channel1 */
-    hdac->DMA_Handle1->XferErrorCallback = DAC_DMAErrorCh1;
-
-    /* Enable the selected DAC channel1 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN1);
-       
-    /* Case of use of channel 1 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R1;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L1;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R1 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R1;
-        break;
-      default:
-        break;
-    }
-  }
-  else
-  {
-    /* Set the DMA transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferCpltCallback = DAC_DMAConvCpltCh2;
-
-    /* Set the DMA half transfer complete callback for channel2 */
-    hdac->DMA_Handle2->XferHalfCpltCallback = DAC_DMAHalfConvCpltCh2;
-    
-    /* Set the DMA error callback for channel2 */
-    hdac->DMA_Handle2->XferErrorCallback = DAC_DMAErrorCh2;
-
-    /* Enable the selected DAC channel2 DMA request */
-    SET_BIT(hdac->Instance->CR, DAC_CR_DMAEN2);
-
-    /* Case of use of channel 2 */
-    switch(Alignment)
-    {
-      case DAC_ALIGN_12B_R:
-        /* Get DHR12R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12R2;
-        break;
-      case DAC_ALIGN_12B_L:
-        /* Get DHR12L2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR12L2;
-        break;
-      case DAC_ALIGN_8B_R:
-        /* Get DHR8R2 address */
-        tmpreg = (uint32_t)&hdac->Instance->DHR8R2;
-        break;
-      default:
-        break;
-    }
-  }
-  
-  /* Enable the DMA Stream */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR1);
-    
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle1, (uint32_t)pData, tmpreg, Length);
-  } 
-  else
-  {
-    /* Enable the DAC DMA underrun interrupt */
-    __HAL_DAC_ENABLE_IT(hdac, DAC_IT_DMAUDR2);
-    
-    /* Enable the DMA Stream */
-    HAL_DMA_Start_IT(hdac->DMA_Handle2, (uint32_t)pData, tmpreg, Length);
-  }
-  
-  /* Enable the Peripharal */
-  __HAL_DAC_ENABLE(hdac, Channel);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables DAC and stop conversion of channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Disable the selected DAC channel DMA request */
-  hdac->Instance->CR &= ~(DAC_CR_DMAEN1 << Channel);
-    
-  /* Disable the Peripharal */
-  __HAL_DAC_DISABLE(hdac, Channel);
-  
-  /* Disable the DMA Channel */
-  /* Channel1 is used */
-  if(Channel == DAC_CHANNEL_1)
-  { 
-    status = HAL_DMA_Abort(hdac->DMA_Handle1);
-  }
-  else /* Channel2 is used for */
-  { 
-    status = HAL_DMA_Abort(hdac->DMA_Handle2); 
-  }
-
-  /* Check if DMA Channel effectively disabled */
-  if(status != HAL_OK)
-  {
-    /* Update ADC state machine to error */
-    hdac->State = HAL_DAC_STATE_ERROR;      
-  }
-  else
-  {
-    /* Change DAC state */
-    hdac->State = HAL_DAC_STATE_READY;
-  }
-
-  /* Return function status */
-  return status;
-}
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Returns the DAC channel data output register value */
-  if(Channel == DAC_CHANNEL_1)
-  {
-    return hdac->Instance->DOR1;
-  }
-  else
-  {
-    return hdac->Instance->DOR2;
-  }
-}
-
-/**
-  * @brief  Handles DAC interrupt request  
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac)
-{
-  /* Check underrun flag of DAC channel 1 */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR1))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-    
-    /* Set DAC error code to chanel1 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH1;
-    
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR1);
-    
-    /* Disable the selected DAC channel1 DMA request */
-    hdac->Instance->CR &= ~DAC_CR_DMAEN1;
-    
-    /* Error callback */ 
-    HAL_DAC_DMAUnderrunCallbackCh1(hdac);
-  }
-  
-  /* Check underrun flag of DAC channel 2 */
-  if(__HAL_DAC_GET_FLAG(hdac, DAC_FLAG_DMAUDR2))
-  {
-    /* Change DAC state to error state */
-    hdac->State = HAL_DAC_STATE_ERROR;
-    
-    /* Set DAC error code to channel2 DMA underrun error */
-    hdac->ErrorCode |= HAL_DAC_ERROR_DMAUNDERRUNCH2;
-    
-    /* Clear the underrun flag */
-    __HAL_DAC_CLEAR_FLAG(hdac,DAC_FLAG_DMAUDR2);
-    
-    /* Disable the selected DAC channel1 DMA request */
-    hdac->Instance->CR &= ~DAC_CR_DMAEN2;
-    
-    /* Error callback */ 
-    HAL_DACEx_DMAUnderrunCallbackCh2(hdac);
-  }  
-}
-
-/**
-  * @brief  Conversion complete callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel1 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ConvHalfCpltCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_ErrorCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel1.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh1 could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_Exported_Functions_Group3 Peripheral Control functions
- *  @brief    Peripheral Control functions 
- *
-@verbatim   
-  ==============================================================================
-             ##### Peripheral Control functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure channels. 
-      (+) Set the specified data holding register value for DAC channel.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  sConfig: DAC configuration structure.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel)
-{
-  uint32_t tmpreg1 = 0, tmpreg2 = 0;
-
-  /* Check the DAC parameters */
-  assert_param(IS_DAC_TRIGGER(sConfig->DAC_Trigger));
-  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(sConfig->DAC_OutputBuffer));
-  assert_param(IS_DAC_CHANNEL(Channel));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Get the DAC CR value */
-  tmpreg1 = DAC->CR;
-  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
-  tmpreg1 &= ~(((uint32_t)(DAC_CR_MAMP1 | DAC_CR_WAVE1 | DAC_CR_TSEL1 | DAC_CR_TEN1 | DAC_CR_BOFF1)) << Channel);
-  /* Configure for the selected DAC channel: buffer output, trigger */
-  /* Set TSELx and TENx bits according to DAC_Trigger value */
-  /* Set BOFFx bit according to DAC_OutputBuffer value */   
-  tmpreg2 = (sConfig->DAC_Trigger | sConfig->DAC_OutputBuffer);
-  /* Calculate CR register value depending on DAC_Channel */
-  tmpreg1 |= tmpreg2 << Channel;
-  /* Write to DAC CR */
-  DAC->CR = tmpreg1;
-  /* Disable wave generation */
-  DAC->CR &= ~(DAC_CR_WAVE1 << Channel);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified data holding register value for DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_CHANNEL_1: DAC Channel1 selected
-  *            @arg DAC_CHANNEL_2: DAC Channel2 selected  
-  * @param  Alignment: Specifies the data alignment.
-  *          This parameter can be one of the following values:
-  *            @arg DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            @arg DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            @arg DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data: Data to be loaded in the selected data holding register.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data)
-{  
-  __IO uint32_t tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data));
-  
-  tmp = (uint32_t)hdac->Instance; 
-  if(Channel == DAC_CHANNEL_1)
-  {
-    tmp += __HAL_DHR12R1_ALIGNEMENT(Alignment);
-  }
-  else
-  {
-    tmp += __HAL_DHR12R2_ALIGNEMENT(Alignment);
-  }
-
-  /* Set the DAC channel selected data holding register */
-  *(__IO uint32_t *) tmp = Data;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Exported_Functions_Group4 Peripheral State and Errors functions
- *  @brief   Peripheral State and Errors functions 
- *
-@verbatim   
-  ==============================================================================
-            ##### Peripheral State and Errors functions #####
-  ==============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DAC state.
-      (+) Check the DAC Errors.
-        
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  return the DAC state
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval HAL state
-  */
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac)
-{
-  /* Return DAC state */
-  return hdac->State;
-}
-
-
-/**
-  * @brief  Return the DAC error code
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval DAC Error Code
-  */
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac)
-{
-  return hdac->ErrorCode;
-}
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAConvCpltCh1(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DAC_ConvCpltCallbackCh1(hdac); 
-  
-  hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAHalfConvCpltCh1(DMA_HandleTypeDef *hdma)   
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DAC_ConvHalfCpltCallbackCh1(hdac); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void DAC_DMAErrorCh1(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DAC_ErrorCallbackCh1(hdac); 
-    
-  hdac->State = HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,385 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dac.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of DAC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_DAC_H
-#define __STM32L1xx_HAL_DAC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-   
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DAC
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Types DAC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_DAC_STATE_RESET             = 0x00,  /*!< DAC not yet initialized or disabled  */
-  HAL_DAC_STATE_READY             = 0x01,  /*!< DAC initialized and ready for use    */
-  HAL_DAC_STATE_BUSY              = 0x02,  /*!< DAC internal processing is ongoing   */
-  HAL_DAC_STATE_TIMEOUT           = 0x03,  /*!< DAC timeout state                    */
-  HAL_DAC_STATE_ERROR             = 0x04   /*!< DAC error state                      */
- 
-}HAL_DAC_StateTypeDef;
- 
-/** 
-  * @brief  DAC handle Structure definition  
-  */ 
-typedef struct
-{
-  DAC_TypeDef                 *Instance;     /*!< Register base address             */
-  
-  __IO HAL_DAC_StateTypeDef   State;         /*!< DAC communication state           */
-
-  HAL_LockTypeDef             Lock;          /*!< DAC locking object                */
-  
-  DMA_HandleTypeDef           *DMA_Handle1;  /*!< Pointer DMA handler for channel 1 */
-  
-  DMA_HandleTypeDef           *DMA_Handle2;  /*!< Pointer DMA handler for channel 2 */ 
-  
-  __IO uint32_t               ErrorCode;     /*!< DAC Error code                    */
-  
-}DAC_HandleTypeDef;
-
-/** 
-  * @brief   DAC Configuration regular Channel structure definition  
-  */ 
-typedef struct
-{
-  uint32_t DAC_Trigger;       /*!< Specifies the external trigger for the selected DAC channel.
-                                   This parameter can be a value of @ref DAC_trigger_selection */
-  
-  uint32_t DAC_OutputBuffer;  /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
-                                   This parameter can be a value of @ref DAC_output_buffer */
-  
-}DAC_ChannelConfTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Constants DAC Exported Constants
-  * @{
-  */  
-
-/** @defgroup DAC_Error_Code DAC Error Code
-  * @{
-  */
-#define  HAL_DAC_ERROR_NONE              0x00    /*!< No error                          */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH1    0x01    /*!< DAC channel1 DAM underrun error   */
-#define  HAL_DAC_ERROR_DMAUNDERRUNCH2    0x02    /*!< DAC channel2 DAM underrun error   */
-#define  HAL_DAC_ERROR_DMA               0x04    /*!< DMA error                         */   
-/**
-  * @}
-  */
-  
-/** @defgroup DAC_trigger_selection DAC trigger selection
-  * @{
-  */
-#define DAC_TRIGGER_NONE                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
-                                                                       has been loaded, and not by external trigger */
-#define DAC_TRIGGER_T6_TRGO                ((uint32_t)                                                    DAC_CR_TEN1)  /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T7_TRGO                ((uint32_t)(                 DAC_CR_TSEL1_1                  | DAC_CR_TEN1)) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T9_TRGO                ((uint32_t)(                 DAC_CR_TSEL1_1 | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM9 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T2_TRGO                ((uint32_t)(DAC_CR_TSEL1_2                                   | DAC_CR_TEN1)) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_T4_TRGO                ((uint32_t)(DAC_CR_TSEL1_2                  | DAC_CR_TSEL1_0 | DAC_CR_TEN1)) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_EXT_IT9                ((uint32_t)(DAC_CR_TSEL1_2 | DAC_CR_TSEL1_1                  | DAC_CR_TEN1)) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
-#define DAC_TRIGGER_SOFTWARE               ((uint32_t)(DAC_CR_TSEL1                                     | DAC_CR_TEN1)) /*!< Conversion started by software trigger for DAC channel */
-
-#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_TRIGGER_NONE)    || \
-                                 ((TRIGGER) == DAC_TRIGGER_T6_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T7_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T9_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T2_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_T4_TRGO) || \
-                                 ((TRIGGER) == DAC_TRIGGER_EXT_IT9) || \
-                                 ((TRIGGER) == DAC_TRIGGER_SOFTWARE))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_output_buffer DAC output buffer
-  * @{
-  */
-#define DAC_OUTPUTBUFFER_ENABLE            ((uint32_t)0x00000000)
-#define DAC_OUTPUTBUFFER_DISABLE           ((uint32_t)DAC_CR_BOFF1)
-
-#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OUTPUTBUFFER_ENABLE) || \
-                                           ((STATE) == DAC_OUTPUTBUFFER_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_Channel_selection DAC Channel selection
-  * @{
-  */
-#define DAC_CHANNEL_1                      ((uint32_t)0x00000000)
-#define DAC_CHANNEL_2                      ((uint32_t)0x00000010)
-
-#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_CHANNEL_1) || \
-                                 ((CHANNEL) == DAC_CHANNEL_2))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data_alignement DAC data alignement
-  * @{
-  */
-#define DAC_ALIGN_12B_R                    ((uint32_t)0x00000000)
-#define DAC_ALIGN_12B_L                    ((uint32_t)0x00000004)
-#define DAC_ALIGN_8B_R                     ((uint32_t)0x00000008)
-
-#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_ALIGN_12B_R) || \
-                             ((ALIGN) == DAC_ALIGN_12B_L) || \
-                             ((ALIGN) == DAC_ALIGN_8B_R))
-/**
-  * @}
-  */
-
-/** @defgroup DAC_data DAC data
-  * @{
-  */
-#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
-/**
-  * @}
-  */
-
-/** @defgroup DAC_flags_definition DAC flags definition
-  * @{
-  */ 
-#define DAC_FLAG_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_FLAG_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
-
-/**
-  * @}
-  */
-
-/** @defgroup DAC_IT_definition DAC IT definition
-  * @{
-  */ 
-#define DAC_IT_DMAUDR1                   ((uint32_t)DAC_SR_DMAUDR1)
-#define DAC_IT_DMAUDR2                   ((uint32_t)DAC_SR_DMAUDR2)   
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup DAC_Exported_Macros DAC Exported Macros
-  * @{
-  */
-
-/** @brief Reset DAC handle state
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @retval None
-  */
-#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
-
-/** @brief Enable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __DAC_Channel__: specifies the DAC channel
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR |=  (DAC_CR_EN1 << (__DAC_Channel__)))
-
-/** @brief Disable the DAC channel
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __DAC_Channel__: specifies the DAC channel.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) \
-((__HANDLE__)->Instance->CR &=  ~(DAC_CR_EN1 << (__DAC_Channel__)))
- 
-/** @brief Set DHR12R1 alignment
-  * @param  __ALIGNEMENT__: specifies the DAC alignement
-  * @retval None
-  */
-#define __HAL_DHR12R1_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000008) + (__ALIGNEMENT__))
-
-/** @brief  Set DHR12R2 alignment
-  * @param  __ALIGNEMENT__: specifies the DAC alignement
-  * @retval None
-  */
-#define __HAL_DHR12R2_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000014) + (__ALIGNEMENT__))
-
-/** @brief  Set DHR12RD alignment
-  * @param  __ALIGNEMENT__: specifies the DAC alignement
-  * @retval None
-  */
-#define __HAL_DHR12RD_ALIGNEMENT(__ALIGNEMENT__) (((uint32_t)0x00000020) + (__ALIGNEMENT__))
-
-/** @brief Enable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  * @retval None
-  */
-#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
-
-/** @brief Disable the DAC interrupt
-  * @param  __HANDLE__: specifies the DAC handle
-  * @param  __INTERRUPT__: specifies the DAC interrupt.
-  * @retval None
-  */
-#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
-
-/** @brief  Get the selected DAC's flag status.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the FLAG.
-  * @retval None
-  */
-#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the DAC's flag.
-  * @param  __HANDLE__: specifies the DAC handle.
-  * @param  __FLAG__: specifies the FLAG.
-  * @retval None
-  */
-#define __HAL_DAC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = (__FLAG__))
-
-/**
-  * @}
-  */ 
-
-
-/* Include DAC HAL Extension module */
-#include "stm32l1xx_hal_dac_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup DAC_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group1
-  * @{
-  */ 
-/* Initialization and de-initialization functions *****************************/ 
-HAL_StatusTypeDef HAL_DAC_Init(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DAC_DeInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspInit(DAC_HandleTypeDef* hdac);
-void HAL_DAC_MspDeInit(DAC_HandleTypeDef* hdac);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
-  * @{
-  */
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DAC_Start(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Stop(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_Start_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t* pData, uint32_t Length, uint32_t Alignment);
-HAL_StatusTypeDef HAL_DAC_Stop_DMA(DAC_HandleTypeDef* hdac, uint32_t Channel);
-HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data);
-uint32_t HAL_DAC_GetValue(DAC_HandleTypeDef* hdac, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral Control functions ***********************************************/
-HAL_StatusTypeDef HAL_DAC_ConfigChannel(DAC_HandleTypeDef* hdac, DAC_ChannelConfTypeDef* sConfig, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup DAC_Exported_Functions_Group2
-  * @{
-  */
-/* Peripheral State functions ***************************************************/
-HAL_DAC_StateTypeDef HAL_DAC_GetState(DAC_HandleTypeDef* hdac);
-void HAL_DAC_IRQHandler(DAC_HandleTypeDef* hdac);
-uint32_t HAL_DAC_GetError(DAC_HandleTypeDef *hdac);
-
-void HAL_DAC_ConvCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ConvHalfCpltCallbackCh1(DAC_HandleTypeDef* hdac);
-void HAL_DAC_ErrorCallbackCh1(DAC_HandleTypeDef *hdac);
-void HAL_DAC_DMAUnderrunCallbackCh1(DAC_HandleTypeDef *hdac);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L1xx_HAL_DAC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,382 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dac_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   DAC HAL module driver.
-  *         This file provides firmware functions to manage the following 
-  *         functionalities of DAC extension peripheral:
-  *           + Extended features functions
-  *     
-  *
-  @verbatim      
-  ==============================================================================
-                      ##### How to use this driver #####
-  ==============================================================================
-    [..]          
-      (+) When Dual mode is enabled (i.e DAC Channel1 and Channel2 are used simultaneously) :
-          Use HAL_DACEx_DualGetValue() to get digital data to be converted and use
-          HAL_DACEx_DualSetValue() to set digital value to converted simultaneously in Channel 1 and Channel 2.  
-      (+) Use HAL_DACEx_TriangleWaveGenerate() to generate Triangle signal.
-      (+) Use HAL_DACEx_NoiseWaveGenerate() to generate Noise signal.
-   
- @endverbatim    
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DACEx DACEx
-  * @brief DAC driver modules
-  * @{
-  */ 
-
-#ifdef HAL_DAC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DACEx_Exported_Functions DACEx Exported Functions
-  * @{
-  */
-
-/** @defgroup DACEx_Exported_Functions_Group1 Extended features functions
- *  @brief    Extended features functions 
- *
-@verbatim   
-  ==============================================================================
-                 ##### Extended features functions #####
-  ==============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start conversion.
-      (+) Stop conversion.
-      (+) Start conversion and enable DMA transfer.
-      (+) Stop conversion and disable DMA transfer.
-      (+) Get result of conversion.
-      (+) Get result of dual mode conversion.
-                     
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the last data output value of the selected DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval The selected DAC channel data output value.
-  */
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac)
-{
-  uint32_t tmp = 0;
-  
-  tmp |= hdac->Instance->DOR1;
-  
-  tmp |= hdac->Instance->DOR2 << 16;
-  
-  /* Returns the DAC channel data output register value */
-  return tmp;
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Select max triangle amplitude. 
-  *          This parameter can be one of the following values:
-  *            @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1
-  *            @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3
-  *            @arg DAC_TRIANGLEAMPLITUDE_7: Select max triangle amplitude of 7
-  *            @arg DAC_TRIANGLEAMPLITUDE_15: Select max triangle amplitude of 15
-  *            @arg DAC_TRIANGLEAMPLITUDE_31: Select max triangle amplitude of 31
-  *            @arg DAC_TRIANGLEAMPLITUDE_63: Select max triangle amplitude of 63
-  *            @arg DAC_TRIANGLEAMPLITUDE_127: Select max triangle amplitude of 127
-  *            @arg DAC_TRIANGLEAMPLITUDE_255: Select max triangle amplitude of 255
-  *            @arg DAC_TRIANGLEAMPLITUDE_511: Select max triangle amplitude of 511
-  *            @arg DAC_TRIANGLEAMPLITUDE_1023: Select max triangle amplitude of 1023
-  *            @arg DAC_TRIANGLEAMPLITUDE_2047: Select max triangle amplitude of 2047
-  *            @arg DAC_TRIANGLEAMPLITUDE_4095: Select max triangle amplitude of 4095                               
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the selected wave generation for the selected DAC channel */
-  hdac->Instance->CR |= (DAC_WAVE_TRIANGLE | Amplitude) << Channel;
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables or disables the selected DAC channel wave generation.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC. 
-  * @param  Channel: The selected DAC channel. 
-  *          This parameter can be one of the following values:
-  *            DAC_CHANNEL_1 / DAC_CHANNEL_2
-  * @param  Amplitude: Unmask DAC channel LFSR for noise wave generation. 
-  *          This parameter can be one of the following values: 
-  *            @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation  
-  *            @arg DAC_LFSRUNMASK_BITS2_0: Unmask DAC channel LFSR bit[2:0] for noise wave generation
-  *            @arg DAC_LFSRUNMASK_BITS3_0: Unmask DAC channel LFSR bit[3:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS4_0: Unmask DAC channel LFSR bit[4:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS5_0: Unmask DAC channel LFSR bit[5:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS6_0: Unmask DAC channel LFSR bit[6:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS7_0: Unmask DAC channel LFSR bit[7:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS8_0: Unmask DAC channel LFSR bit[8:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS9_0: Unmask DAC channel LFSR bit[9:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS10_0: Unmask DAC channel LFSR bit[10:0] for noise wave generation 
-  *            @arg DAC_LFSRUNMASK_BITS11_0: Unmask DAC channel LFSR bit[11:0] for noise wave generation 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude)
-{  
-  /* Check the parameters */
-  assert_param(IS_DAC_CHANNEL(Channel));
-  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(Amplitude));
-  
-  /* Process locked */
-  __HAL_LOCK(hdac);
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_BUSY;
-  
-  /* Enable the selected wave generation for the selected DAC channel */
-  hdac->Instance->CR |= (DAC_WAVE_NOISE | Amplitude) << Channel;
-  
-  /* Change DAC state */
-  hdac->State = HAL_DAC_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hdac);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the specified data holding register value for dual DAC channel.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *               the configuration information for the specified DAC.
-  * @param  Alignment: Specifies the data alignment for dual channel DAC.
-  *          This parameter can be one of the following values:
-  *            DAC_ALIGN_8B_R: 8bit right data alignment selected
-  *            DAC_ALIGN_12B_L: 12bit left data alignment selected
-  *            DAC_ALIGN_12B_R: 12bit right data alignment selected
-  * @param  Data1: Data for DAC Channel2 to be loaded in the selected data holding register.
-  * @param  Data2: Data for DAC Channel1 to be loaded in the selected data  holding register.
-  * @note   In dual mode, a unique register access is required to write in both
-  *          DAC channels at the same time.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2)
-{  
-  uint32_t data = 0, tmp = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_DAC_ALIGN(Alignment));
-  assert_param(IS_DAC_DATA(Data1));
-  assert_param(IS_DAC_DATA(Data2));
-  
-  /* Calculate and set dual DAC data holding register value */
-  if (Alignment == DAC_ALIGN_8B_R)
-  {
-    data = ((uint32_t)Data2 << 8) | Data1; 
-  }
-  else
-  {
-    data = ((uint32_t)Data2 << 16) | Data1;
-  }
-  
-  tmp = (uint32_t)hdac->Instance;
-  tmp += __HAL_DHR12RD_ALIGNEMENT(Alignment);
-
-  /* Set the dual DAC selected data holding register */
-  *(__IO uint32_t *)tmp = data;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Conversion complete callback in non blocking mode for Channel2 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Conversion half DMA transfer callback in non blocking mode for Channel2 
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DACEx_ConvHalfCpltCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Error DAC callback for Channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DACEx_ErrorCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DMA underrun DAC callback for channel2.
-  * @param  hdac: pointer to a DAC_HandleTypeDef structure that contains
-  *         the configuration information for the specified DAC.
-  * @retval None
-  */
-__weak void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef *hdac)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_DAC_DMAUnderrunCallbackCh2 could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup DACEx_Private_Functions DACEx Private Functions
-  * @{
-  */
-/**
-  * @brief  DMA conversion complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  HAL_DACEx_ConvCpltCallbackCh2(hdac); 
-  
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @brief  DMA half transfer complete callback. 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma)   
-{
-    DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    /* Conversion complete callback */
-    HAL_DACEx_ConvHalfCpltCallbackCh2(hdac); 
-}
-
-/**
-  * @brief  DMA error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma)   
-{
-  DAC_HandleTypeDef* hdac = ( DAC_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-    
-  /* Set DAC error code to DMA error */
-  hdac->ErrorCode |= HAL_DAC_ERROR_DMA;
-    
-  HAL_DACEx_ErrorCallbackCh2(hdac); 
-    
-  hdac->State= HAL_DAC_STATE_READY;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_DAC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dac_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,205 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dac_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of DAC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_DAC_EX_H
-#define __STM32L1xx_HAL_DAC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DACEx
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-  
-/** @defgroup DACEx_Exported_Constants DACEx Exported Constants
-  * @{
-  */ 
-   
-/** @defgroup DACEx_wave_generation DACEx wave generation
-  * @{
-  */
-#define DAC_WAVEGENERATION_NONE            ((uint32_t)0x00000000)
-#define DAC_WAVEGENERATION_NOISE           ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVEGENERATION_TRIANGLE        ((uint32_t)DAC_CR_WAVE1_1)
-
-#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WAVEGENERATION_NONE)  || \
-                                    ((WAVE) == DAC_WAVEGENERATION_NOISE) || \
-                                    ((WAVE) == DAC_WAVEGENERATION_TRIANGLE))
-/**
-  * @}
-  */
-
-/** @defgroup DACEx_lfsrunmask_triangleamplitude DACEx lfsrunmask triangleamplitude
-  * @{
-  */
-#define DAC_LFSRUNMASK_BIT0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
-#define DAC_LFSRUNMASK_BITS1_0             ((uint32_t)DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS2_0             ((uint32_t)DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS3_0             ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0)/*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS4_0             ((uint32_t)DAC_CR_MAMP1_2) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS5_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS6_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS7_0             ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS8_0             ((uint32_t)DAC_CR_MAMP1_3) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS9_0             ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS10_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
-#define DAC_LFSRUNMASK_BITS11_0            ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
-#define DAC_TRIANGLEAMPLITUDE_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
-#define DAC_TRIANGLEAMPLITUDE_3            ((uint32_t)DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 3 */
-#define DAC_TRIANGLEAMPLITUDE_7            ((uint32_t)DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 7 */
-#define DAC_TRIANGLEAMPLITUDE_15           ((uint32_t)DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 15 */
-#define DAC_TRIANGLEAMPLITUDE_31           ((uint32_t)DAC_CR_MAMP1_2) /*!< Select max triangle amplitude of 31 */
-#define DAC_TRIANGLEAMPLITUDE_63           ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 63 */
-#define DAC_TRIANGLEAMPLITUDE_127          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 127 */
-#define DAC_TRIANGLEAMPLITUDE_255          ((uint32_t)DAC_CR_MAMP1_2 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 255 */
-#define DAC_TRIANGLEAMPLITUDE_511          ((uint32_t)DAC_CR_MAMP1_3) /*!< Select max triangle amplitude of 511 */
-#define DAC_TRIANGLEAMPLITUDE_1023         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 1023 */
-#define DAC_TRIANGLEAMPLITUDE_2047         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1) /*!< Select max triangle amplitude of 2047 */
-#define DAC_TRIANGLEAMPLITUDE_4095         ((uint32_t)DAC_CR_MAMP1_3 | DAC_CR_MAMP1_1 | DAC_CR_MAMP1_0) /*!< Select max triangle amplitude of 4095 */
-
-#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUNMASK_BIT0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS1_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS2_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS3_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS4_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS5_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS6_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS7_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS8_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS9_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS10_0) || \
-                                                      ((VALUE) == DAC_LFSRUNMASK_BITS11_0) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_3) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_7) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_15) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_31) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_63) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_127) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_255) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_511) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_1023) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_2047) || \
-                                                      ((VALUE) == DAC_TRIANGLEAMPLITUDE_4095))
-/**
-  * @}
-  */
-
-/** @defgroup DACEx_wave_generation DACEx wave generation
-  * @{
-  */
-#define DAC_WAVE_NOISE                     ((uint32_t)DAC_CR_WAVE1_0)
-#define DAC_WAVE_TRIANGLE                  ((uint32_t)DAC_CR_WAVE1_1)
-
-#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NOISE) || \
-                           ((WAVE) == DAC_WAVE_TRIANGLE))
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/  
-
-/** @addtogroup DACEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup DACEx_Exported_Functions_Group1
-  * @{
-  */
-/* Extension features functions ***********************************************/
-uint32_t HAL_DACEx_DualGetValue(DAC_HandleTypeDef* hdac);
-HAL_StatusTypeDef HAL_DACEx_TriangleWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_NoiseWaveGenerate(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Amplitude);
-HAL_StatusTypeDef HAL_DACEx_DualSetValue(DAC_HandleTypeDef* hdac, uint32_t Alignment, uint32_t Data1, uint32_t Data2);
-
-void HAL_DACEx_ConvCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ConvHalfCpltCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_ErrorCallbackCh2(DAC_HandleTypeDef* hdac);
-void HAL_DACEx_DMAUnderrunCallbackCh2(DAC_HandleTypeDef* hdac);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/** @addtogroup DACEx_Private_Functions
-  * @{
-  */ 
-void DAC_DMAConvCpltCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAErrorCh2(DMA_HandleTypeDef *hdma);
-void DAC_DMAHalfConvCpltCh2(DMA_HandleTypeDef *hdma); 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /*__STM32L1xx_HAL_DAC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_def.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,195 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_def.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   This file contains HAL common defines, enumeration, macros and 
-  *          structures definitions. 
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_DEF
-#define __STM32L1xx_HAL_DEF
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx.h"
-
-/* Exported types ------------------------------------------------------------*/
-
-/** 
-  * @brief  HAL Status structures definition  
-  */  
-typedef enum 
-{
-  HAL_OK       = 0x00,
-  HAL_ERROR    = 0x01,
-  HAL_BUSY     = 0x02,
-  HAL_TIMEOUT  = 0x03
-} HAL_StatusTypeDef;
-
-/** 
-  * @brief  HAL Lock structures definition  
-  */
-typedef enum 
-{
-  HAL_UNLOCKED = 0x00,
-  HAL_LOCKED   = 0x01  
-} HAL_LockTypeDef;
-
-/* Exported macro ------------------------------------------------------------*/
-#ifndef HAL_NULL
-  #define HAL_NULL      (void *) 0
-#endif
-
-#define HAL_MAX_DELAY      0xFFFFFFFF
-
-#define HAL_IS_BIT_SET(REG, BIT)         (((REG) & (BIT)) != RESET)
-#define HAL_IS_BIT_CLR(REG, BIT)         (((REG) & (BIT)) == RESET)
-
-#define __HAL_LINKDMA(__HANDLE__, __PPP_DMA_FIELD_, __DMA_HANDLE_)           \
-                        do{                                                  \
-                              (__HANDLE__)->__PPP_DMA_FIELD_ = &(__DMA_HANDLE_); \
-                              (__DMA_HANDLE_).Parent = (__HANDLE__);             \
-                          } while(0)
-
-/** @brief Reset the Handle's State field.
-  * @param __HANDLE__: specifies the Peripheral Handle.
-  * @note  This macro can be used for the following purpose: 
-  *          - When the Handle is declared as local variable; before passing it as parameter
-  *            to HAL_PPP_Init() for the first time, it is mandatory to use this macro 
-  *            to set to 0 the Handle's "State" field.
-  *            Otherwise, "State" field may have any random value and the first time the function 
-  *            HAL_PPP_Init() is called, the low level hardware initialization will be missed
-  *            (i.e. HAL_PPP_MspInit() will not be executed).
-  *          - When there is a need to reconfigure the low level hardware: instead of calling
-  *            HAL_PPP_DeInit() then HAL_PPP_Init(), user can make a call to this macro then HAL_PPP_Init().
-  *            In this later function, when the Handle's "State" field is set to 0, it will execute the function
-  *            HAL_PPP_MspInit() which will reconfigure the low level hardware.
-  * @retval None
-  */
-#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0)
-
-#if (USE_RTOS == 1)
-  #error " USE_RTOS should be 0 in the current HAL release "
-#else
-  #define __HAL_LOCK(__HANDLE__)                                           \
-                                do{                                        \
-                                    if((__HANDLE__)->Lock == HAL_LOCKED)  \
-                                    {                                      \
-                                       return HAL_BUSY;                    \
-                                    }                                      \
-                                    else                                   \
-                                    {                                      \
-                                       (__HANDLE__)->Lock = HAL_LOCKED;    \
-                                    }                                      \
-                                  }while (0)
-
-  #define __HAL_UNLOCK(__HANDLE__)                                          \
-                                  do{                                       \
-                                      (__HANDLE__)->Lock = HAL_UNLOCKED;   \
-                                    }while (0)
-#endif /* USE_RTOS */
-
-#if  defined ( __GNUC__ )
-  #ifndef __weak
-    #define __weak   __attribute__((weak))
-  #endif /* __weak */
-  #ifndef __packed
-    #define __packed __attribute__((__packed__))
-  #endif /* __packed */
-#endif /* __GNUC__ */
-
-
-/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined   (__GNUC__)        /* GNU Compiler */
-  #ifndef __ALIGN_END
-    #define __ALIGN_END    __attribute__ ((aligned (4)))
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN  
-    #define __ALIGN_BEGIN
-  #endif /* __ALIGN_BEGIN */
-#else
-  #ifndef __ALIGN_END
-    #define __ALIGN_END
-  #endif /* __ALIGN_END */
-  #ifndef __ALIGN_BEGIN      
-    #if defined   (__CC_ARM)      /* ARM Compiler */
-      #define __ALIGN_BEGIN    __align(4)  
-    #elif defined (__ICCARM__)    /* IAR Compiler */
-      #define __ALIGN_BEGIN 
-    #endif /* __CC_ARM */
-  #endif /* __ALIGN_BEGIN */
-#endif /* __GNUC__ */
-
-/** 
-  * @brief  __RAM_FUNC definition
-  */ 
-#if defined ( __CC_ARM   )
-/* ARM Compiler
-   ------------
-   RAM functions are defined using the toolchain options. 
-   Functions that are executed in RAM should reside in a separate source module.
-   Using the 'Options for File' dialog you can simply change the 'Code / Const' 
-   area of a module to a memory space in physical RAM.
-   Available memory areas are declared in the 'Target' tab of the 'Options for Target'
-   dialog. 
-*/
-#define __RAM_FUNC HAL_StatusTypeDef 
-
-#elif defined ( __ICCARM__ )
-/* ICCARM Compiler
-   ---------------
-   RAM functions are defined using a specific toolchain keyword "__ramfunc". 
-*/
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
-
-#elif defined   (  __GNUC__  )
-/* GNU Compiler
-   ------------
-  RAM functions are defined using a specific toolchain attribute 
-   "__attribute__((section(".RamFunc")))".
-*/
-#define __RAM_FUNC HAL_StatusTypeDef  __attribute__((section(".RamFunc")))
-
-#endif
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* ___STM32L1xx_HAL_DEF */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,707 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dma.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   DMA HAL module driver.
-  *    
-  *         This file provides firmware functions to manage the following 
-  *         functionalities of the Direct Memory Access (DMA) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and errors functions
-  @verbatim     
-  ==============================================================================      
-                        ##### How to use this driver #####
-  ============================================================================== 
-  [..]
-   (#) Enable and configure the peripheral to be connected to the DMA Channel
-       (except for internal SRAM / FLASH memories: no initialization is 
-       necessary) please refer to Reference manual for connection between peripherals
-       and DMA requests .
-          
-   (#) For a given Channel, program the required configuration through the following parameters:   
-       Transfer Direction, Source and Destination data formats, 
-       Circular, Normal or peripheral flow control mode, Channel Priority level, 
-       Source and Destination Increment mode, FIFO mode and its Threshold (if needed), 
-       Burst mode for Source and/or Destination (if needed) using HAL_DMA_Init() function.
-   
-     *** Polling mode IO operation ***
-     =================================   
-    [..] 
-          (+) Use HAL_DMA_Start() to start DMA transfer after the configuration of Source 
-              address and destination address and the Length of data to be transferred
-          (+) Use HAL_DMA_PollForTransfer() to poll for the end of current transfer, in this  
-              case a fixed Timeout can be configured by User depending from his application.
-  
-     *** Interrupt mode IO operation ***    
-     =================================== 
-    [..]     
-          (+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
-          (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ() 
-          (+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of  
-              Source address and destination address and the Length of data to be transferred. In this 
-              case the DMA interrupt is configured 
-          (+) Use HAL_DMA_IRQHandler() called under DMA_IRQHandler() Interrupt subroutine
-          (+) At the end of data transfer HAL_DMA_IRQHandler() function is executed and user can 
-              add his own function by customization of function pointer XferCpltCallback and 
-              XferErrorCallback (i.e a member of DMA handle structure). 
-                
-     (#) Use HAL_DMA_GetState() function to return the DMA state and HAL_DMA_GetError() in case of error 
-         detection.
-                      
-     (#) Use HAL_DMA_Abort() function to abort the current transfer
-                     
-     -@-   In Memory-to-Memory transfer mode, Circular mode is not allowed.
-                   
-     *** DMA HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in DMA HAL driver.
-    
-      (+) __HAL_DMA_ENABLE: Enable the specified DMA Channel.
-      (+) __HAL_DMA_DISABLE: Disable the specified DMA Channel.
-      (+) __HAL_DMA_GET_FLAG: Get the DMA Channel pending flags.
-      (+) __HAL_DMA_CLEAR_FLAG: Clear the DMA Channel pending flags.
-      (+) __HAL_DMA_ENABLE_IT: Enable the specified DMA Channel interrupts.
-      (+) __HAL_DMA_DISABLE_IT: Disable the specified DMA Channel interrupts.
-      (+) __HAL_DMA_GET_IT_SOURCE: Check whether the specified DMA Channel interrupt has occurred or not. 
-      
-     [..] 
-      (@) You can refer to the DMA HAL driver header file for more useful macros  
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup DMA DMA
-  * @brief DMA HAL module driver
-  * @{
-  */
-
-#ifdef HAL_DMA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup DMA_Private_Constants DMA Private Constants
-* @{
-*/
-#define HAL_TIMEOUT_DMA_ABORT    ((uint32_t)1000)  /* 1s  */
-/**
-  * @}
-  */
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup DMA_Private_Functions DMA Private Functions
-* @{
-*/
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-/**
-  * @}
-  */
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Functions DMA Exported Functions
-  * @{
-  */
-
-/** @defgroup DMA_Group1 Initialization and de-initialization functions
- *  @brief   Initialization and de-initialization functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Initialization and de-initialization functions  #####
- ===============================================================================  
-    [..]
-    This section provides functions allowing to initialize the DMA Channel source
-    and destination addresses, incrementation and data sizes, transfer direction, 
-    circular/normal mode selection, memory-to-memory mode selection and Channel priority value.
-    [..]
-    The HAL_DMA_Init() function follows the DMA configuration procedures as described in
-    reference manual.  
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initializes the DMA according to the specified
-  *         parameters in the DMA_InitTypeDef and create the associated handle.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma)
-{ 
-  uint32_t tmp = 0;
-  
-  /* Check the DMA peripheral state */
-  if(hdma == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_DMA_ALL_INSTANCE(hdma->Instance));
-  assert_param(IS_DMA_DIRECTION(hdma->Init.Direction));
-  assert_param(IS_DMA_PERIPHERAL_INC_STATE(hdma->Init.PeriphInc));
-  assert_param(IS_DMA_MEMORY_INC_STATE(hdma->Init.MemInc));
-  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(hdma->Init.PeriphDataAlignment));
-  assert_param(IS_DMA_MEMORY_DATA_SIZE(hdma->Init.MemDataAlignment));
-  assert_param(IS_DMA_MODE(hdma->Init.Mode));
-  assert_param(IS_DMA_PRIORITY(hdma->Init.Priority));
-  
-  /* Change DMA peripheral state */
-  hdma->State = HAL_DMA_STATE_BUSY;
-
-  /* Get the CR register value */
-  tmp = hdma->Instance->CCR;
-  
-  /* Clear PL, MSIZE, PSIZE, MINC, PINC, CIRC, DIR bits */
-  tmp &= ((uint32_t)~(DMA_CCR_PL    | DMA_CCR_MSIZE  | DMA_CCR_PSIZE  | \
-                      DMA_CCR_MINC  | DMA_CCR_PINC   | DMA_CCR_CIRC   | \
-                      DMA_CCR_DIR));
-  
-  /* Prepare the DMA Channel configuration */
-  tmp |=  hdma->Init.Direction        |
-          hdma->Init.PeriphInc           | hdma->Init.MemInc           |
-          hdma->Init.PeriphDataAlignment | hdma->Init.MemDataAlignment |
-          hdma->Init.Mode                | hdma->Init.Priority;
-
-  /* Write to DMA Channel CR register */
-  hdma->Instance->CCR = tmp;  
-  
-  /* Initialise the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state*/
-  hdma->State  = HAL_DMA_STATE_READY;
-  
-  return HAL_OK;
-}  
-  
-/**
-  * @brief  DeInitializes the DMA peripheral 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_DeInit(DMA_HandleTypeDef *hdma)
-{
-  /* Check the DMA peripheral state */
-  if(hdma == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the DMA peripheral handle */
-  if(hdma->State == HAL_DMA_STATE_BUSY)
-  {
-     return HAL_ERROR;
-  }
-
-  /* Disable the selected DMA Channelx */
-  __HAL_DMA_DISABLE(hdma);
-  
-  /* Reset DMA Channel control register */
-  hdma->Instance->CCR  = 0;
-  
-  /* Reset DMA Channel Number of Data to Transfer register */
-  hdma->Instance->CNDTR = 0;
-  
-  /* Reset DMA Channel peripheral address register */
-  hdma->Instance->CPAR  = 0;
-  
-  /* Reset DMA Channel memory address register */
-  hdma->Instance->CMAR = 0;
-
-  /* Clear all flags */
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-  __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-  
-  /* Initialise the error code */
-  hdma->ErrorCode = HAL_DMA_ERROR_NONE;
-
-  /* Initialize the DMA state */
-  hdma->State = HAL_DMA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hdma);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Group2 I/O operation functions 
- *  @brief   I/O operation functions  
- *
-@verbatim   
- ===============================================================================
-                      #####  IO operation functions  #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Configure the source, destination address and data length and Start DMA transfer
-      (+) Configure the source, destination address and data length and 
-          Start DMA transfer with interrupt
-      (+) Abort DMA transfer
-      (+) Poll for transfer complete
-      (+) Handle DMA interrupt request  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the DMA Transfer.
-  * @param  hdma      : pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{ 
-  /* Process locked */
-  __HAL_LOCK(hdma);  
-
-  /* Change DMA peripheral state */  
-  hdma->State = HAL_DMA_STATE_BUSY;  
-
-   /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-  
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);  
-  
-  /* Configure the source, destination address and the data length */
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-
-  /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);  
-
-  return HAL_OK; 
-} 
-
-/**
-  * @brief  Start the DMA Transfer with interrupt enabled.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{
-  /* Process locked */
-  __HAL_LOCK(hdma);
-
-  /* Change DMA peripheral state */  
-  hdma->State = HAL_DMA_STATE_BUSY;  
-
-   /* Check the parameters */
-  assert_param(IS_DMA_BUFFER_SIZE(DataLength));
-  
-  /* Disable the peripheral */
-  __HAL_DMA_DISABLE(hdma);
-  
-  /* Configure the source, destination address and the data length */  
-  DMA_SetConfig(hdma, SrcAddress, DstAddress, DataLength);
-  
-  /* Enable the transfer complete interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TC);
-
-  /* Enable the Half transfer complete interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_HT);  
-
-  /* Enable the transfer Error interrupt */
-  __HAL_DMA_ENABLE_IT(hdma, DMA_IT_TE);
-  
-   /* Enable the Peripheral */
-  __HAL_DMA_ENABLE(hdma);   
-  
-  return HAL_OK;    
-} 
-
-/**
-  * @brief  Aborts the DMA Transfer.
-  * @param  hdma  : pointer to a DMA_HandleTypeDef structure that contains
-  *                 the configuration information for the specified DMA Channel.
-  *                   
-  * @note  After disabling a DMA Channel, a check for wait until the DMA Channel is 
-  *        effectively disabled is added. If a Channel is disabled 
-  *        while a data transfer is ongoing, the current data will be transferred
-  *        and the Channel will be effectively disabled only after the transfer of
-  *        this single data is finished.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma)
-{
-  uint32_t tickstart = 0x00;
-  
-  /* Disable the channel */
-  __HAL_DMA_DISABLE(hdma);
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-  
-  /* Check if the DMA Channel is effectively disabled */
-  while((hdma->Instance->CCR & DMA_CCR_EN) != 0) 
-  {
-    /* Check for the Timeout */
-    if((HAL_GetTick() - tickstart ) > HAL_TIMEOUT_DMA_ABORT)
-    {
-      /* Update error code */
-      SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-      
-      /* Change the DMA state */
-      hdma->State = HAL_DMA_STATE_TIMEOUT;
-
-      return HAL_TIMEOUT;
-    }
-  }
-  /* Process Unlocked */
-  __HAL_UNLOCK(hdma);
-  
-  /* Change the DMA state*/
-  hdma->State = HAL_DMA_STATE_READY; 
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Polling for transfer complete.
-  * @param  hdma:    pointer to a DMA_HandleTypeDef structure that contains
-  *                  the configuration information for the specified DMA Channel.
-  * @param  CompleteLevel: Specifies the DMA level complete.  
-  * @param  Timeout:       Timeout duration.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout)
-{
-  uint32_t temp;
-  uint32_t tickstart = 0x00;
-  
-  /* Get the level transfer complete flag */
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Transfer Complete flag */
-    temp = __HAL_DMA_GET_TC_FLAG_INDEX(hdma);
-  }
-  else
-  {
-    /* Half Transfer Complete flag */
-    temp = __HAL_DMA_GET_HT_FLAG_INDEX(hdma);
-  } 
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_DMA_GET_FLAG(hdma, temp) == RESET)
-  {
-    if((__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET))
-    {      
-      /* Clear the transfer error flags */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-      
-      /* Update error code */
-      SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
-
-      /* Change the DMA state */
-      hdma->State= HAL_DMA_STATE_ERROR;       
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hdma);
-      
-      return HAL_ERROR;      
-    }      
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        /* Update error code */
-        SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TIMEOUT);
-        
-        /* Change the DMA state */
-        hdma->State= HAL_DMA_STATE_TIMEOUT;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hdma);
-      
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  if(CompleteLevel == HAL_DMA_FULL_TRANSFER)
-  {
-    /* Clear the transfer complete flag */
-    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-
-    /* The selected Channelx EN bit is cleared (DMA is disabled and 
-    all transfers are complete) */
-    hdma->State = HAL_DMA_STATE_READY;
-  
-    /* Process unlocked */
-    __HAL_UNLOCK(hdma);  
-  }
-  else
-  { 
-    /* Clear the half transfer complete flag */
-    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-  
-    /* The selected Channelx EN bit is cleared (DMA is disabled and 
-  all transfers are complete) */
-    hdma->State = HAL_DMA_STATE_READY_HALF;
-      /* Process unlocked */
-    __HAL_UNLOCK(hdma);  
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles DMA interrupt request.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.  
-  * @retval None
-  */
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma)
-{        
-  /* Transfer Error Interrupt management ***************************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TE) != RESET)
-  {
-      /* Disable the transfer error interrupt */
-    __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TE);
-    
-    /* Clear the transfer error flag */
-    __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TE_FLAG_INDEX(hdma));
-    
-      /* Update error code */
-      SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_TE);
-
-      /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_ERROR;    
-    
-      /* Process Unlocked */
-    __HAL_UNLOCK(hdma); 
-    
-    if (hdma->XferErrorCallback != HAL_NULL)
-    {
-        /* Transfer error callback */
-      hdma->XferErrorCallback(hdma);
-    }
-  }
-  }
-
-  /* Half Transfer Complete Interrupt management ******************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_HT) != RESET)
-    { 
-      /* Disable the half transfer interrupt if the DMA mode is not CIRCULAR */
-      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-      {
-        /* Disable the half transfer interrupt */
-        __HAL_DMA_DISABLE_IT(hdma, DMA_IT_HT);
-      }
-      /* Clear the half transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_HT_FLAG_INDEX(hdma));
-
-      /* Change DMA peripheral state */
-      hdma->State = HAL_DMA_STATE_READY_HALF;
-
-      if(hdma->XferHalfCpltCallback != HAL_NULL)
-      {
-        /* Half transfer callback */
-        hdma->XferHalfCpltCallback(hdma);
-      }
-    }
-  }
-  
-  /* Transfer Complete Interrupt management ***********************************/
-  if(__HAL_DMA_GET_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma)) != RESET)
-  {
-    if(__HAL_DMA_GET_IT_SOURCE(hdma, DMA_IT_TC) != RESET)
-    {
-      if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  { 
-    /* Disable the transfer complete interrupt */
-    __HAL_DMA_DISABLE_IT(hdma, DMA_IT_TC);
-      }
-      /* Clear the transfer complete flag */
-      __HAL_DMA_CLEAR_FLAG(hdma, __HAL_DMA_GET_TC_FLAG_INDEX(hdma));
-    
-      /* Update error code */
-      SET_BIT(hdma->ErrorCode, HAL_DMA_ERROR_NONE);
-
-      /* Change the DMA state */
-    hdma->State = HAL_DMA_STATE_READY;    
-    
-      /* Process Unlocked */
-    __HAL_UNLOCK(hdma);
-    
-    if(hdma->XferCpltCallback != HAL_NULL)
-    {       
-        /* Transfer complete callback */
-      hdma->XferCpltCallback(hdma);
-    }
-  }
-}  
-}  
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Group3 Peripheral State functions
- *  @brief    Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                    ##### State and Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Check the DMA state
-      (+) Get error code
-
-@endverbatim
-  * @{
-  */  
-
-/**
-  * @brief  Returns the DMA state.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA Channel.  
-  * @retval HAL state
-  */
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma)
-{
-  return hdma->State;
-}
-
-/**
-  * @brief  Return the DMA error code
-  * @param  hdma : pointer to a DMA_HandleTypeDef structure that contains
-  *              the configuration information for the specified DMA Channel.
-  * @retval DMA Error Code
-  */
-uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma)
-{
-  return hdma->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup DMA_Private_Functions
-* @{
-*/
-
-/**
-  * @brief  Sets the DMA Transfer parameter.
-  * @param  hdma:       pointer to a DMA_HandleTypeDef structure that contains
-  *                     the configuration information for the specified DMA Channel.  
-  * @param  SrcAddress: The source memory Buffer address
-  * @param  DstAddress: The destination memory Buffer address
-  * @param  DataLength: The length of data to be transferred from source to destination
-  * @retval HAL status
-  */
-static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
-{  
-  /* Configure DMA Channel data length */
-  hdma->Instance->CNDTR = DataLength;
-  
-  /* Peripheral to Memory */
-  if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
-  {   
-    /* Configure DMA Channel destination address */
-    hdma->Instance->CPAR = DstAddress;
-    
-    /* Configure DMA Channel source address */
-    hdma->Instance->CMAR = SrcAddress;
-  }
-  /* Memory to Peripheral */
-  else
-  {
-    /* Configure DMA Channel source address */
-    hdma->Instance->CPAR = SrcAddress;
-    
-    /* Configure DMA Channel destination address */
-    hdma->Instance->CMAR = DstAddress;
-  }
-}
-
-/**
-  * @}
-  */
-
-
-#endif /* HAL_DMA_MODULE_ENABLED */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,444 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dma.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of DMA HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_DMA_H
-#define __STM32L1xx_HAL_DMA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMA
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup DMA_Exported_Types DMA Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  DMA Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t Direction;                 /*!< Specifies if the data will be transferred from memory to peripheral, 
-                                           from memory to memory or from peripheral to memory.
-                                           This parameter can be a value of @ref DMA_Data_transfer_direction */
-
-  uint32_t PeriphInc;                 /*!< Specifies whether the Peripheral address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
-                               
-  uint32_t MemInc;                    /*!< Specifies whether the memory address register should be incremented or not.
-                                           This parameter can be a value of @ref DMA_Memory_incremented_mode */
-  
-  uint32_t PeriphDataAlignment;       /*!< Specifies the Peripheral data width.
-                                           This parameter can be a value of @ref DMA_Peripheral_data_size */
-
-  uint32_t MemDataAlignment;          /*!< Specifies the Memory data width.
-                                           This parameter can be a value of @ref DMA_Memory_data_size */
-                               
-  uint32_t Mode;                      /*!< Specifies the operation mode of the DMAy Channelx.
-                                           This parameter can be a value of @ref DMA_mode
-                                           @note The circular buffer mode cannot be used if the memory-to-memory
-                                                 data transfer is configured on the selected Channel */ 
-
-  uint32_t Priority;                   /*!< Specifies the software priority for the DMAy Channelx.
-                                            This parameter can be a value of @ref DMA_Priority_level */
-
-} DMA_InitTypeDef;
-
-/** 
-  * @brief DMA Configuration enumeration values definition 
-  */  
-typedef enum 
-{
-  DMA_MODE            = 0,      /*!< Control related DMA mode Parameter in DMA_InitTypeDef        */
-  DMA_PRIORITY        = 1,      /*!< Control related priority level Parameter in DMA_InitTypeDef  */
-  
-} DMA_ControlTypeDef;
-
-/**
-  * @brief  HAL DMA State structures definition  
-  */
-typedef enum
-{
-  HAL_DMA_STATE_RESET             = 0x00,  /*!< DMA not yet initialized or disabled */  
-  HAL_DMA_STATE_READY             = 0x01,  /*!< DMA process success and ready for use   */
-  HAL_DMA_STATE_READY_HALF        = 0x11,  /*!< DMA Half process success            */
-  HAL_DMA_STATE_BUSY              = 0x02,  /*!< DMA process is ongoing              */     
-  HAL_DMA_STATE_TIMEOUT           = 0x03,  /*!< DMA timeout state                   */  
-  HAL_DMA_STATE_ERROR             = 0x04,  /*!< DMA error state                     */
-                                                                        
-}HAL_DMA_StateTypeDef;
-
-/** 
-  * @brief  HAL DMA Error Code structure definition  
-  */ 
-typedef enum
-{
-  HAL_DMA_FULL_TRANSFER      = 0x00,    /*!< Full transfer     */
-  HAL_DMA_HALF_TRANSFER      = 0x01,    /*!< Half Transfer     */
-
-}HAL_DMA_LevelCompleteTypeDef;
-                                                                        
-
-/** 
-  * @brief  DMA handle Structure definition  
-  */ 
-typedef struct __DMA_HandleTypeDef
-{  
-  DMA_Channel_TypeDef    *Instance;                       /*!< Register base address                  */
-  
-  DMA_InitTypeDef       Init;                            /*!< DMA communication parameters           */ 
-  
-  HAL_LockTypeDef       Lock;                            /*!< DMA locking object                     */  
-  
-  HAL_DMA_StateTypeDef  State;                           /*!< DMA transfer state                     */
-  
-  void                  *Parent;                                                      /*!< Parent object state                    */  
-  
-  void                  (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma);     /*!< DMA transfer complete callback         */
-  
-  void                  (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback    */
-  
-  void                  (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma);    /*!< DMA transfer error callback            */
-  
-  __IO uint32_t              ErrorCode;                                               /*!< DMA Error code                         */
-  
-} DMA_HandleTypeDef;    
-/**
-  * @}
-  */
-
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup DMA_Exported_Constants DMA Exported Constants
-  * @{
-  */
-
-/** @defgroup DMA_Error_Code DMA_Error_Code
-  * @{
-  */ 
-#define HAL_DMA_ERROR_NONE      ((uint32_t)0x00000000)    /*!< No error             */
-#define HAL_DMA_ERROR_TE        ((uint32_t)0x00000001)    /*!< Transfer error       */
-#define HAL_DMA_ERROR_TIMEOUT   ((uint32_t)0x00000020)    /*!< Timeout error        */
-/**
-  * @}
-  */
-
-
-/** @defgroup DMA_Data_transfer_direction DMA_Data_transfer_direction
-  * @{
-  */ 
-#define DMA_PERIPH_TO_MEMORY         ((uint32_t)0x00000000)        /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH         ((uint32_t)DMA_CCR_DIR)       /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY         ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction     */
-
-#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_PERIPH)  || \
-                                     ((DIRECTION) == DMA_MEMORY_TO_MEMORY)) 
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Data_buffer_size DMA_Data_buffer_size
-  * @{
-  */ 
-#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
-/**
-  * @}
-  */     
-    
-/** @defgroup DMA_Peripheral_incremented_mode DMA_Peripheral_incremented_mode
-  * @{
-  */ 
-#define DMA_PINC_ENABLE        ((uint32_t)DMA_CCR_PINC)   /*!< Peripheral increment mode Enable */
-#define DMA_PINC_DISABLE       ((uint32_t)0x00000000)     /*!< Peripheral increment mode Disable */
-
-#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
-                                            ((STATE) == DMA_PINC_DISABLE))
-/**
-  * @}
-  */ 
-
-/** @defgroup DMA_Memory_incremented_mode DMA_Memory_incremented_mode
-  * @{
-  */ 
-#define DMA_MINC_ENABLE         ((uint32_t)DMA_CCR_MINC)  /*!< Memory increment mode Enable  */
-#define DMA_MINC_DISABLE        ((uint32_t)0x00000000)    /*!< Memory increment mode Disable */
-
-#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE)  || \
-                                        ((STATE) == DMA_MINC_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Peripheral_data_size DMA_Peripheral_data_size
-  * @{
-  */ 
-#define DMA_PDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Peripheral data alignment : Byte     */
-#define DMA_PDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_PSIZE_0)  /*!< Peripheral data alignment : HalfWord */
-#define DMA_PDATAALIGN_WORD          ((uint32_t)DMA_CCR_PSIZE_1)  /*!< Peripheral data alignment : Word     */
-
-#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE)     || \
-                                           ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
-                                           ((SIZE) == DMA_PDATAALIGN_WORD))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_Memory_data_size DMA_Memory_data_size
-  * @{ 
-  */
-#define DMA_MDATAALIGN_BYTE          ((uint32_t)0x00000000)       /*!< Memory data alignment : Byte     */
-#define DMA_MDATAALIGN_HALFWORD      ((uint32_t)DMA_CCR_MSIZE_0)  /*!< Memory data alignment : HalfWord */
-#define DMA_MDATAALIGN_WORD          ((uint32_t)DMA_CCR_MSIZE_1)  /*!< Memory data alignment : Word     */
-
-#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE)     || \
-                                       ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
-                                       ((SIZE) == DMA_MDATAALIGN_WORD ))
-/**
-  * @}
-  */
-
-/** @defgroup DMA_mode DMA_mode
-  * @{
-  */ 
-#define DMA_NORMAL         ((uint32_t)0x00000000)      /*!< Normal Mode                  */
-#define DMA_CIRCULAR       ((uint32_t)DMA_CCR_CIRC)    /*!< Circular Mode                */
-
-#define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL )  || \
-                           ((MODE) == DMA_CIRCULAR)) 
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Priority_level DMA_Priority_level
-  * @{
-  */
-#define DMA_PRIORITY_LOW             ((uint32_t)0x00000000)    /*!< Priority level : Low       */
-#define DMA_PRIORITY_MEDIUM          ((uint32_t)DMA_CCR_PL_0)  /*!< Priority level : Medium    */
-#define DMA_PRIORITY_HIGH            ((uint32_t)DMA_CCR_PL_1)  /*!< Priority level : High      */
-#define DMA_PRIORITY_VERY_HIGH       ((uint32_t)DMA_CCR_PL)    /*!< Priority level : Very_High */
-
-#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW )   || \
-                                   ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
-                                   ((PRIORITY) == DMA_PRIORITY_HIGH)   || \
-                                   ((PRIORITY) == DMA_PRIORITY_VERY_HIGH)) 
-/**
-  * @}
-  */ 
-
-
-/** @defgroup DMA_interrupt_enable_definitions DMA_interrupt_enable_definitions
-  * @{
-  */
-
-#define DMA_IT_TC                         ((uint32_t)DMA_CCR_TCIE)
-#define DMA_IT_HT                         ((uint32_t)DMA_CCR_HTIE)
-#define DMA_IT_TE                         ((uint32_t)DMA_CCR_TEIE)
-
-/**
-  * @}
-  */
-
-/** @defgroup DMA_flag_definitions DMA_flag_definitions
-  * @{
-  */ 
-
-#define DMA_FLAG_GL1                      ((uint32_t)0x00000001)
-#define DMA_FLAG_TC1                      ((uint32_t)0x00000002)
-#define DMA_FLAG_HT1                      ((uint32_t)0x00000004)
-#define DMA_FLAG_TE1                      ((uint32_t)0x00000008)
-#define DMA_FLAG_GL2                      ((uint32_t)0x00000010)
-#define DMA_FLAG_TC2                      ((uint32_t)0x00000020)
-#define DMA_FLAG_HT2                      ((uint32_t)0x00000040)
-#define DMA_FLAG_TE2                      ((uint32_t)0x00000080)
-#define DMA_FLAG_GL3                      ((uint32_t)0x00000100)
-#define DMA_FLAG_TC3                      ((uint32_t)0x00000200)
-#define DMA_FLAG_HT3                      ((uint32_t)0x00000400)
-#define DMA_FLAG_TE3                      ((uint32_t)0x00000800)
-#define DMA_FLAG_GL4                      ((uint32_t)0x00001000)
-#define DMA_FLAG_TC4                      ((uint32_t)0x00002000)
-#define DMA_FLAG_HT4                      ((uint32_t)0x00004000)
-#define DMA_FLAG_TE4                      ((uint32_t)0x00008000)
-#define DMA_FLAG_GL5                      ((uint32_t)0x00010000)
-#define DMA_FLAG_TC5                      ((uint32_t)0x00020000)
-#define DMA_FLAG_HT5                      ((uint32_t)0x00040000)
-#define DMA_FLAG_TE5                      ((uint32_t)0x00080000)
-#define DMA_FLAG_GL6                      ((uint32_t)0x00100000)
-#define DMA_FLAG_TC6                      ((uint32_t)0x00200000)
-#define DMA_FLAG_HT6                      ((uint32_t)0x00400000)
-#define DMA_FLAG_TE6                      ((uint32_t)0x00800000)
-#define DMA_FLAG_GL7                      ((uint32_t)0x01000000)
-#define DMA_FLAG_TC7                      ((uint32_t)0x02000000)
-#define DMA_FLAG_HT7                      ((uint32_t)0x04000000)
-#define DMA_FLAG_TE7                      ((uint32_t)0x08000000)
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup DMA_Exported_macros DMA Exported Macros
-  * @{
-  */
-
-/** @brief  Reset DMA handle state
-  * @param  __HANDLE__: DMA handle.
-  * @retval None
-  */
-#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
-  
-/**
-  * @brief  Enable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
-  * @retval None.
-  */
-#define __HAL_DMA_ENABLE(__HANDLE__)        (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
-
-/**
-  * @brief  Disable the specified DMA Channel.
-  * @param  __HANDLE__: DMA handle
-  * @retval None.
-  */
-#define __HAL_DMA_DISABLE(__HANDLE__)       (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
-
-
-/* Interrupt & Flag management */
-
-/**
-  * @brief  Enables the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
-
-/**
-  * @brief  Disables the specified DMA Channel interrupts.
-  * @param  __HANDLE__: DMA handle
-  * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled. 
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval None
-  */
-#define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
-
-/**
-  * @brief  Checks whether the specified DMA Channel interrupt has occurred or not.
-  * @param  __HANDLE__: DMA handle
-  * @param  __INTERRUPT__: specifies the DMA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
-  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
-  *            @arg DMA_IT_TE:  Transfer error interrupt mask
-  * @retval The state of DMA_IT (SET or RESET).
-  */
-#define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)  ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/**
-  * @}
-  */
-
-
-/* Include DMA HAL Extension module */
-#include "stm32l1xx_hal_dma_ex.h"   
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup DMA_Exported_Functions
-  * @{
-  */
-
-
-/* Initialization and de-initialization functions *****************************/
-HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma); 
-HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
-HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
-void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-
-/* Peripheral State and Error functions ***************************************/
-HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
-uint32_t             HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_DMA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_dma_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,248 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_dma_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of DMA HAL extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_DMA_EX_H
-#define __STM32L1xx_HAL_DMA_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup DMAEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/* Exported constants --------------------------------------------------------*/
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup DMAEx_Exported_Macros DMAEx Exported Macros
-  * @{
-  */
-
-/* Interrupt & Flag management */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
-  * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TC7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TC4 :\
-   DMA_FLAG_TC5)
-
-/**
-  * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified half transfer complete flag index.
-  */      
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_HT7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_HT4 :\
-   DMA_FLAG_HT5)
-
-/**
-  * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel7))? DMA_FLAG_TE7 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA2_Channel4))? DMA_FLAG_TE4 :\
-   DMA_FLAG_TE5)
-
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 or 1_5 to select the DMA Channel flag.   
-  * @retval The state of FLAG (SET or RESET).
-  */
-
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)\
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->ISR & (__FLAG__)) :\
-  (DMA1->ISR & (__FLAG__)))
-
-/**
-  * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 or 1_5 to select the DMA Channel flag.   
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-(((uint32_t)((__HANDLE__)->Instance) > (uint32_t)DMA1_Channel7)? (DMA2->IFCR = (__FLAG__)) :\
-  (DMA1->IFCR = (__FLAG__)))
-
-#else
-/**
-  * @brief  Returns the current DMA Channel transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer complete flag index.
-  */
-#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TC1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TC2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TC3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TC4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TC5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TC6 :\
-   DMA_FLAG_TC7)
-
-/**
-  * @brief  Returns the current DMA Channel half transfer complete flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified half transfer complete flag index.
-  */      
-#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_HT1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_HT2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_HT3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_HT4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_HT5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_HT6 :\
-   DMA_FLAG_HT7)
-
-/**
-  * @brief  Returns the current DMA Channel transfer error flag.
-  * @param  __HANDLE__: DMA handle
-  * @retval The specified transfer error flag index.
-  */
-#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
-(((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel1))? DMA_FLAG_TE1 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel2))? DMA_FLAG_TE2 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel3))? DMA_FLAG_TE3 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel4))? DMA_FLAG_TE4 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel5))? DMA_FLAG_TE5 :\
- ((uint32_t)((__HANDLE__)->Instance) == ((uint32_t)DMA1_Channel6))? DMA_FLAG_TE6 :\
-   DMA_FLAG_TE7)
-
-/**
-  * @brief  Get the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: Get the specified flag.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 to select the DMA Channel flag.   
-  * @retval The state of FLAG (SET or RESET).
-  */
-
-#define __HAL_DMA_GET_FLAG(__HANDLE__, __FLAG__)   (DMA1->ISR & (__FLAG__))
-
-/**
-  * @brief  Clears the DMA Channel pending flags.
-  * @param  __HANDLE__: DMA handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg DMA_FLAG_TCx:  Transfer complete flag
-  *            @arg DMA_FLAG_HTx:  Half transfer complete flag
-  *            @arg DMA_FLAG_TEx:  Transfer error flag
-  *         Where x can be 1_7 to select the DMA Channel flag.   
-  * @retval None
-  */
-#define __HAL_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) (DMA1->IFCR = (__FLAG__))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif 
-
-#endif /* __STM32L1xx_HAL_DMA_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,490 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the internal FLASH memory:
-  *            + FLASH Interface configuration
-  *            + FLASH Memory Programming
-  *            + Interrupts and flags management
-  *
-  *  @verbatim
-
-  ==============================================================================
-                      ##### FLASH peripheral features #####
-  ==============================================================================
-           
-  [..] The Flash memory interface manages CPU AHB I-Code and D-Code accesses 
-       to the Flash memory. It implements the erase and program Flash memory operations 
-       and the read and write protection mechanisms.
-      
-  [..] The Flash memory interface accelerates code execution with a system of instruction prefetch. 
-
-  [..] The FLASH main features are:
-      (+) Flash memory read operations
-      (+) Flash memory program/erase operations
-      (+) Read / write protections
-      (+) Prefetch on I-Code
-      (+) Option Bytes programming
-      
-            ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure and program the Flash 
-     memory of all STM32L1xx devices.
-
-     (#) FLASH Memory Programming functions: this group includes all 
-       needed functions to erase and program the main memory:
-       (++) Lock and Unlock the Flash interface.
-       (++) Erase function: Erase Page.
-       (++) Program functions: Fast Word and Half Page(should be 
-        executed from internal SRAM).
-  
-     (#) DATA EEPROM Programming functions: this group includes all 
-       needed functions to erase and program the DATA EEPROM memory:
-       (++) Lock and Unlock the DATA EEPROM interface.
-       (++) Erase function: Erase Byte, erase HalfWord, erase Word, erase 
-       Double Word (should be executed from internal SRAM).
-       (++) Program functions: Fast Program Byte, Fast Program Half-Word, 
-        FastProgramWord, Program Byte, Program Half-Word, 
-        Program Word and Program Double-Word (should be executed 
-        from internal SRAM).
-  
-     (#) FLASH Option Bytes Programming functions: this group includes 
-       all needed functions to:
-       (++) Lock and Unlock the Flash Option bytes.
-       (++) Set/Reset the write protection.
-       (++) Set the Read protection Level.
-       (++) Set the BOR level.
-       (++) Program the user option Bytes.
-       (++) Launch the Option Bytes loader.
-       (++) Get the Write protection.
-       (++) Get the read protection status.
-       (++) Get the BOR level.
-       (++) Get the user option bytes.
-       
-     (#) Interrupts and flags management functions : 
-       (++) Handle FLASH interrupts by calling HAL_FLASH_IRQHandler()
-       (++) Wait for last FLASH operation according to its status
-       (++) Get error flag status by calling HAL_GetErrorCode()          
-
-    (#) FLASH Interface configuration functions: this group includes 
-      the management of following features:
-      (++) Enable/Disable the RUN PowerDown mode.
-      (++) Enable/Disable the SLEEP PowerDown mode.  
-  
-    (#) FLASH Peripheral State methods: this group includes 
-      the management of following features:
-      (++) Wait for the FLASH operation
-      (++)  Get the specific FLASH error flag
-    
-  [..] In addition to these function, this driver includes a set of macros allowing
-       to handle the following operations:
-      
-    (+) Set/Get the latency
-    (+) Enable/Disable the prefetch buffer
-    (+) Enable/Disable the 64 bit Read Access. 
-       (+) Enable/Disable the Flash power-down
-       (+) Enable/Disable the FLASH interrupts
-       (+) Monitor the FLASH flags status
-
-  ===============================================================================
-                 ##### Programming operation functions #####
-  ===============================================================================  
-     [..]
-     This subsection provides a set of functions allowing to manage the FLASH 
-     program operations.
-  
-    [..] The FLASH Memory Programming functions, includes the following functions:
-     (+) HAL_FLASH_Unlock(void);
-     (+) HAL_FLASH_Lock(void);
-     (+) HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-     (+) HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-    
-     [..] Any operation of erase or program should follow these steps:
-     (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and 
-         program memory access.
-     (#) Call the desired function to erase page or program data.
-     (#) Call the HAL_FLASH_Lock() to disable the flash program memory access 
-        (recommended to protect the FLASH memory against possible unwanted operation).
-  
-   ==============================================================================
-               ##### Option Bytes Programming functions ##### 
-   ==============================================================================  
-  
-     [..] The FLASH_Option Bytes Programming_functions, includes the following functions:
-     (+) HAL_FLASH_OB_Unlock(void);
-     (+) HAL_FLASH_OB_Lock(void);
-     (+) HAL_FLASH_OB_Launch(void);
-     (+) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-     (+) HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-    
-     [..] Any operation of erase or program should follow these steps:
-     (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control 
-         register access.
-     (#) Call the following functions to program the desired option bytes.
-         (++) HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);      
-     (#) Once all needed option bytes to be programmed are correctly written, call the
-         HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-     (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
-         to protect the option Bytes against possible unwanted operations).
-  
-  *  @endverbatim
-  *                      
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/** @defgroup FLASH FLASH
-  * @brief FLASH driver modules
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup FLASH_Internal_Variables FLASH Internal Variables
-  * @{
-  */  
-
-/**
-  * @brief  Variable used for Program/Erase sectors under interruption 
-  */
-FLASH_ProcessTypeDef      ProcFlash;
-
-
-/**
-  * @}
-  */ 
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Functions FLASH Exported functions
-  * @{
-  */
-  
-/** @defgroup FLASH_Exported_Functions_Group1 Programming operation functions 
- *  @brief   Programming operation functions 
- *
-@verbatim
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Program word at a specified address
-  * @note   To correctly run this function, the HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_Lock() to disable the flash memory access
-  *         (recommended to protect the FLASH memory against possible unwanted operation).
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&ProcFlash);
-
-  /* Check the parameters */
-  assert_param(IS_TYPEPROGRAMFLASH(TypeProgram));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /*Program word (32-bit) at a specified address.*/
-    *(__IO uint32_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&ProcFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Program word at a specified address  with interrupt enabled.
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *                           This parameter can be a value of @ref FLASH_Type_Program
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Process Locked */
-  __HAL_LOCK(&ProcFlash);
-
-  /* Check the parameters */
-  assert_param(IS_TYPEPROGRAMFLASH(TypeProgram));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(Address));
-
-  /* Enable End of FLASH Operation interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-  
-  /* Enable Error source interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-  
-  /* Clear pending flags (if any) */  
-  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK);  
-
-  ProcFlash.ProcedureOnGoing = FLASH_PROC_PROGRAM;
-  ProcFlash.Address = Address;
-
-  if(TypeProgram == TYPEPROGRAM_WORD)
-  {
-    /*Program word (32-bit) at a specified address.*/
-    *(__IO uint32_t *)Address = Data;
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(&ProcFlash);
-  
-  return status;
-}
-
-/**
-  * @brief  FLASH end of operation interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
-  *                 - Pages Erase: Sector which has been erased 
-  *                    (if 0xFFFFFFFF, it means that all the selected sectors have been erased)
-  *                 - Program: Address which was selected for data program
-  * @retval none
-  */
-__weak void HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_EndOfOperationCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  FLASH operation error interrupt callback
-  * @param  ReturnValue: The value saved in this parameter depends on the ongoing procedure
-  *                 - Pagess Erase: Sector number which returned an error
-  *                 - Program: Address which was selected for data program
-  * @retval none
-  */
-__weak void HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_FLASH_OperationErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */  
-
-/** @defgroup FLASH_Exported_Functions_Group2 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the FLASH 
-    memory operations.
-
-@endverbatim
-  * @{
-  */  
-
-/**
-  * @brief  Unlock the FLASH control register access
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Unlock(void)  
-{
-  if((FLASH->PECR & FLASH_PECR_PRGLOCK) != RESET)
-  {
-    /* Unlocking FLASH_PECR register access*/
-    if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
-    {  
-      FLASH->PEKEYR = FLASH_PEKEY1;
-      FLASH->PEKEYR = FLASH_PEKEY2;
-    }
-    
-    /* Unlocking the program memory access */
-    FLASH->PRGKEYR = FLASH_PRGKEY1;
-    FLASH->PRGKEYR = FLASH_PRGKEY2;  
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Locks the FLASH control register access
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_Lock(void)
-{
-  /* Set the PRGLOCK Bit to lock the program memory access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PRGLOCK);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Unlock the FLASH Option Control Registers access.
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Unlock(void)
-{
-  if((FLASH->PECR & FLASH_PECR_OPTLOCK) != RESET)
-  {
-    /* Unlocking FLASH_PECR register access*/
-    if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
-    {  
-      /* Unlocking FLASH_PECR register access*/
-      FLASH->PEKEYR = FLASH_PEKEY1;
-      FLASH->PEKEYR = FLASH_PEKEY2;
-    }
-
-    /* Unlocking the option bytes block access */
-    FLASH->OPTKEYR = FLASH_OPTKEY1;
-    FLASH->OPTKEYR = FLASH_OPTKEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }  
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Lock the FLASH Option Control Registers access.
-  * @retval HAL_StatusTypeDef HAL Status 
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Lock(void)
-{
-  /* Set the OPTLOCK Bit to lock the option bytes block access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_OPTLOCK);
-
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Launch the option byte loading.
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASH_OB_Launch(void)
-{
-  /* Set the OBL_Launch bit to lauch the option byte loading */
-  SET_BIT(FLASH->PECR, FLASH_PECR_OBL_LAUNCH);
-  
-  /* Wait for last operation to be completed */
-  return(FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE));  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Exported_Functions_Group3 Peripheral State and Errors functions 
- *  @brief   Peripheral Errors functions 
- *
-@verbatim   
- ===============================================================================
-                ##### Peripheral Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time Errors of the FLASH peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Get the specific FLASH error flag.
-  * @retval FLASH_ErrorCode: The returned value can be:
-  *            @arg FLASH_ERROR_WRP: FLASH Write protected error flag
-  *            @arg FLASH_ERROR_PGA: FLASH Programming Alignment error flag
-  *            @arg FLASH_ERROR_SIZE: FLASH Size error flag
-  *            @arg FLASH_ERROR_OPTV: Option validity error flag
-  *            @arg FLASH_ERROR_OPTVUSR: Option UserValidity Error flag (available only Cat.3, Cat.4 and Cat.5 devices)
-  *            @arg FLASH_ERROR_RD:   FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices)
-  */
-FLASH_ErrorTypeDef HAL_FLASH_GetError(void)
-{ 
-   return ProcFlash.ErrorCode;
-}  
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-     
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,385 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of Flash HAL module.
-  ******************************************************************************
-  * @attention
-  *   
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_FLASH_H
-#define __STM32L1xx_HAL_FLASH_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup FLASH_Exported_Types FLASH Exported Types
-  * @{
-  */  
-
-/**
-  * @brief  FLASH Error structure definition
-  */
-typedef enum
-{ 
-  FLASH_ERROR_SIZE      = 0x01,
-  FLASH_ERROR_OPTV      = 0x02,
-  FLASH_ERROR_OPTVUSR   = 0x04,
-  FLASH_ERROR_PGA       = 0x08,
-  FLASH_ERROR_WRP       = 0x10,
-  FLASH_ERROR_RD        = 0x20,
-  FLASH_ERROR_OPERATION = 0x40
-}FLASH_ErrorTypeDef;
-
-
-/**
-  * @brief  FLASH Procedure structure definition
-  */
-typedef enum 
-{
-  FLASH_PROC_NONE = 0, 
-  FLASH_PROC_PAGEERASE,
-  FLASH_PROC_PROGRAM
-} FLASH_ProcedureTypeDef;
-
-/** 
-  * @brief  FLASH handle Structure definition  
-  */
-typedef struct
-{
-  __IO FLASH_ProcedureTypeDef ProcedureOnGoing;   /*Internal variable to indicate which procedure is ongoing or not in IT context*/
-  
-  __IO uint32_t               NbPagesToErase;    /*Internal variable to save the remaining sectors to erase in IT context*/
-  
-  __IO uint32_t               Page;              /*Internal variable to define the current sector which is erasing*/
-  
-  __IO uint32_t               Address;           /*Internal variable to save address selected for program*/
-  
-  HAL_LockTypeDef             Lock;               /* FLASH locking object                */
-
-  __IO FLASH_ErrorTypeDef     ErrorCode;          /* FLASH error code                    */
-
-}FLASH_ProcessTypeDef;
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_Internal_Variables
-  * @{
-  */  
-
-/**
-  * @brief  Variable used for Program/Erase sectors under interruption.
-  *     Put as extern as used also in flash_ex.c. 
-  */
-extern FLASH_ProcessTypeDef      ProcFlash;
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Constants FLASH Exported Constants
-  * @{
-  */  
-
-#define HAL_FLASH_TIMEOUT_VALUE   ((uint32_t)50000) /* 50 s */
-
-#define FLASH_PAGE_SIZE           ((uint32_t)256)
-  
-/** @defgroup FLASH_Type_Program FLASH Type Program
-  * @{
-  */ 
-#define TYPEPROGRAM_WORD        ((uint32_t)0x02)  /*!< Program a word (32-bit) at a specified address        */
-
-#define IS_TYPEPROGRAMFLASH(_VALUE_)   (((_VALUE_) == TYPEPROGRAM_WORD))  
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASH_Latency FLASH Latency 
-  * @{
-  */ 
-#define FLASH_LATENCY_0                ((uint8_t)0x00)  /*!< FLASH Zero Latency cycle */
-#define FLASH_LATENCY_1                ((uint8_t)0x01)  /*!< FLASH One Latency cycle */
-
-#define IS_FLASH_LATENCY(__LATENCY__) (((__LATENCY__) == FLASH_LATENCY_0) || \
-                                   ((__LATENCY__) == FLASH_LATENCY_1))
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Interrupts FLASH Interrupts 
-  * @{
-  */
-   
-#define FLASH_IT_EOP               FLASH_PECR_EOPIE  /*!< End of programming interrupt source */
-#define FLASH_IT_ERR               FLASH_PECR_ERRIE  /*!< Error interrupt source */
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Flags FLASH Flags 
-  * @{
-  */ 
-
-#define FLASH_FLAG_BSY             FLASH_SR_BSY        /*!< FLASH Busy flag */
-#define FLASH_FLAG_EOP             FLASH_SR_EOP        /*!< FLASH End of Programming flag */
-#define FLASH_FLAG_ENDHV           FLASH_SR_ENDHV      /*!< FLASH End of High Voltage flag */
-#define FLASH_FLAG_READY           FLASH_SR_READY      /*!< FLASH Ready flag after low power mode */
-#define FLASH_FLAG_WRPERR          FLASH_SR_WRPERR     /*!< FLASH Write protected error flag */
-#define FLASH_FLAG_PGAERR          FLASH_SR_PGAERR     /*!< FLASH Programming Alignment error flag */
-#define FLASH_FLAG_SIZERR          FLASH_SR_SIZERR     /*!< FLASH Size error flag  */
-#define FLASH_FLAG_OPTVERR         FLASH_SR_OPTVERR    /*!< FLASH Option Validity error flag  */
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASH_Keys FLASH Keys 
-  * @{
-  */ 
-
-#define FLASH_PDKEY1               ((uint32_t)0x04152637) /*!< Flash power down key1 */
-#define FLASH_PDKEY2               ((uint32_t)0xFAFBFCFD) /*!< Flash power down key2: used with FLASH_PDKEY1 
-                                                              to unlock the RUN_PD bit in FLASH_ACR */
-
-#define FLASH_PEKEY1               ((uint32_t)0x89ABCDEF) /*!< Flash program erase key1 */
-#define FLASH_PEKEY2               ((uint32_t)0x02030405) /*!< Flash program erase key: used with FLASH_PEKEY2
-                                                               to unlock the write access to the FLASH_PECR register and
-                                                               data EEPROM */
-
-#define FLASH_PRGKEY1              ((uint32_t)0x8C9DAEBF) /*!< Flash program memory key1 */
-#define FLASH_PRGKEY2              ((uint32_t)0x13141516) /*!< Flash program memory key2: used with FLASH_PRGKEY2
-                                                               to unlock the program memory */
-
-#define FLASH_OPTKEY1              ((uint32_t)0xFBEAD9C8) /*!< Flash option key1 */
-#define FLASH_OPTKEY2              ((uint32_t)0x24252627) /*!< Flash option key2: used with FLASH_OPTKEY1 to
-                                                              unlock the write access to the option byte block */
-/**
-  * @}
-  */
-  
-
-
-#if defined ( __ICCARM__ )   
-#define InterruptType_ACTLR_DISMCYCINT_Msk         IntType_ACTLR_DISMCYCINT_Msk
-#endif
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FLASH_Exported_Macros FLASH Exported Macros
-  * @{
-  */  
-
-/** @defgroup FLASH_Interrupt FLASH Interrupts
- *  @brief macros to handle FLASH interrupts
- * @{
- */ 
-
-/**
-  * @brief  Enable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ : FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_ERR: Error Interrupt    
-  * @retval none
-  */  
-#define __HAL_FLASH_ENABLE_IT(__INTERRUPT__)  ((FLASH->PECR) |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified FLASH interrupt.
-  * @param  __INTERRUPT__ : FLASH interrupt 
-  *         This parameter can be any combination of the following values:
-  *     @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
-  *     @arg FLASH_IT_ERR: Error Interrupt    
-  * @retval none
-  */  
-#define __HAL_FLASH_DISABLE_IT(__INTERRUPT__)  ((FLASH->PECR) &= ~(uint32_t)(__INTERRUPT__))
-
-/**
-  * @brief  Get the specified FLASH flag status. 
-  * @param  __FLAG__: specifies the FLASH flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_FLAG_BSY   :              FLASH Busy flag
-  *            @arg FLASH_FLAG_EOP   :              FLASH End of Operation flag 
-  *            @arg FLASH_FLAG_ENDHV :            FLASH End of High Voltage flag
-  *            @arg FLASH_FLAG_READY:             FLASH Ready flag after low power mode
-  *            @arg FLASH_FLAG_WRPERR:           FLASH Write protected error flag 
-  *            @arg FLASH_FLAG_PGAERR:           FLASH Programming Alignment error flag
-  *            @arg FLASH_FLAG_SIZERR:            FLASH Size error flag
-  *            @arg FLASH_FLAG_OPTVERR:          FLASH Option validity error error flag
-  *            @arg FLASH_FLAG_OPTVERRUSR :   FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices)
-  *            @arg FLASH_FLAG_RDERR :            FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices)
-  * @retval The new state of __FLAG__ (SET or RESET).
-  */
-#define __HAL_FLASH_GET_FLAG(__FLAG__)   (((FLASH->SR) & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear the specified FLASH flag.
-  * @param  __FLAG__: specifies the FLASH flags to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg FLASH_FLAG_BSY   :              FLASH Busy flag
-  *            @arg FLASH_FLAG_EOP   :              FLASH End of Operation flag 
-  *            @arg FLASH_FLAG_ENDHV :            FLASH End of High Voltage flag
-  *            @arg FLASH_FLAG_READY:             FLASH Ready flag after low power mode
-  *            @arg FLASH_FLAG_WRPERR:           FLASH Write protected error flag 
-  *            @arg FLASH_FLAG_PGAERR:           FLASH Programming Alignment error flag
-  *            @arg FLASH_FLAG_SIZERR:            FLASH Size error flag
-  *            @arg FLASH_FLAG_OPTVERR:          FLASH Option validity error error flag
-  *            @arg FLASH_FLAG_OPTVERRUSR :   FLASH Option UserValidity (available only Cat.3, Cat.4 and Cat.5 devices)
-  *            @arg FLASH_FLAG_RDERR :            FLASH Read Protection error flag (PCROP) (available only Cat.2 and Cat.3 devices)
-  * @retval none
-  */
-#define __HAL_FLASH_CLEAR_FLAG(__FLAG__)   ((FLASH->SR) = (__FLAG__))
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Include FLASH HAL Extension module */
-#include "stm32l1xx_hal_flash_ex.h"
-#include "stm32l1xx_hal_flash_ramfunc.h"
-
-/* Exported functions ------------------------------------------------------- */
-
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group1
-  * @{
-  */
-
-/** 
-  * @brief  FLASH memory functions that can be executed from FLASH.  
-  */  
-/* Program operation functions  ***********************************************/
-HAL_StatusTypeDef   HAL_FLASH_Program(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-HAL_StatusTypeDef   HAL_FLASH_Program_IT(uint32_t TypeProgram, uint32_t Address, uint64_t Data);
-
-/* FLASH IRQ handler function */
-void                HAL_FLASH_IRQHandler(void);
-
-/* Callbacks in non blocking modes */
-void                HAL_FLASH_EndOfOperationCallback(uint32_t ReturnValue);
-void                HAL_FLASH_OperationErrorCallback(uint32_t ReturnValue); 
-  
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_Exported_Functions_Group2
-  * @{
-  */
-
-/* FLASH Memory Programming functions *****************************************/   
-HAL_StatusTypeDef   HAL_FLASH_Unlock(void);
-HAL_StatusTypeDef   HAL_FLASH_Lock(void);
-
-/* Option Bytes Programming functions *****************************************/
-HAL_StatusTypeDef   HAL_FLASH_OB_Unlock(void);
-HAL_StatusTypeDef   HAL_FLASH_OB_Lock(void);
-HAL_StatusTypeDef   HAL_FLASH_OB_Launch(void);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_Exported_Functions_Group3
-  * @{
-  */
-
-/* Peripheral State methods  **************************************************/
-FLASH_ErrorTypeDef  HAL_FLASH_GetError(void);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASH_Internal_Functions
-  * @{
-  */
-
-/** 
-  * @brief  Function used internally by HAL FLASH driver. 
-  */  
-HAL_StatusTypeDef   FLASH_WaitForLastOperation(uint32_t Timeout);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_FLASH_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ 

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1952 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   FLASH HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the internal FLASH memory:
-  *            + FLASH Interface configuration
-  *            + FLASH Memory Erasing
-  *            + DATA EEPROM Programming/Erasing
-  *            + Option Bytes Programming
-  *            + Interrupts management
-  *    
-  *  @verbatim
-  ==============================================================================
-               ##### Flash peripheral Extended features  #####
-  ==============================================================================
-           
-  [..] Comparing to other products, the FLASH interface for STM32L1xx
-       devices contains the following additional features        
-       (+) Erase functions
-       (+) DATA_EEPROM memory management
-       (+) BOOT option bit configuration       
-       (+) PCROP protection for all sectors
-   
-                      ##### How to use this driver #####
-  ==============================================================================
-  [..] This driver provides functions to configure and program the FLASH memory 
-       of all STM32L1xx. It includes:       
-       (+) Full DATA_EEPROM erase and program management
-       (+) Boot activation
-       (+) PCROP protection configuration and control for all pages
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASHEx FLASHEx
-  * @brief FLASH HAL Extension module driver
-  * @{
-  */
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void               FLASH_SetErrorCode(void);
-static void               FLASH_ErasePage(uint32_t PageAddress);
-
-static HAL_StatusTypeDef  FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState);
-static void               FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState);
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-      defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-      defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-static void               FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState);
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-static void               FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState);
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-static void               FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState);
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
-static HAL_StatusTypeDef  FLASH_OB_RDPConfig(uint8_t OB_RDP);
-static HAL_StatusTypeDef  FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
-static HAL_StatusTypeDef  FLASH_OB_BORConfig(uint8_t OB_BOR);
-static uint8_t            FLASH_OB_GetRDP(void);
-static uint8_t            FLASH_OB_GetUser(void);
-static uint8_t            FLASH_OB_GetBOR(void);
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-static HAL_StatusTypeDef  FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState);
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-static HAL_StatusTypeDef  FLASH_OB_BootConfig(uint8_t OB_BOOT);
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data);
-static HAL_StatusTypeDef  FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data);
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Functions FLASHEx Exported functions
-  * @{
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group1 FLASH Memory Erasing functions
- *  @brief   FLASH Memory Erasing functions
- *
-@verbatim   
-  ==============================================================================
-                ##### FLASH Erasing Programming functions ##### 
-  ==============================================================================
-
-    [..] The FLASH Memory Erasing functions, includes the following functions:
-    (+) HAL_FLASHEx_Erase: return only when erase has been done
-    (+) HAL_FLASHEx_Erase_IT: end of erase is done when HAL_FLASH_EndOfOperationCallback is called with parameter
-        0xFFFFFFFF
-
-    [..] Any operation of erase should follow these steps:
-    (#) Call the HAL_FLASH_Unlock() function to enable the flash control register and 
-        program memory access.
-    (#) Call the desired function to erase page.
-    (#) Call the HAL_FLASH_Lock() to disable the flash program memory access 
-       (recommended to protect the FLASH memory against possible unwanted operation).
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Erase the specified FLASH memory Pages 
-  * @note   To correctly run this function, the HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_Lock() to disable the flash memory access 
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param[in]  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  * 
-  * @param[out]  PageError: pointer to variable  that
-  *         contains the configuration information on faulty sector in case of error 
-  *         (0xFFFFFFFF means that all the sectors have been correctly erased)
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  uint32_t index = 0;
-  
-  /* Process Locked */
-  __HAL_LOCK(&ProcFlash);
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-
-  if (status == HAL_OK)
-  {
-    /*Initialization of PageError variable*/
-    *PageError = 0xFFFFFFFF;
-
-    /* Check the parameters */
-    assert_param(IS_NBPAGES(pEraseInit->NbPages));
-    assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
-    assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
-    assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
-
-    /* Erase by sector by sector to be done*/
-    for(index = pEraseInit->PageAddress; index < ((pEraseInit->NbPages * FLASH_PAGE_SIZE)+ pEraseInit->PageAddress); index += FLASH_PAGE_SIZE)
-    {
-      FLASH_ErasePage(index);
-
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-
-      /* If the erase operation is completed, disable the ERASE Bit */
-      CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-      CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-      if (status != HAL_OK) 
-      {
-        /* In case of error, stop erase procedure and return the faulty sector*/
-        *PageError = index;
-        break;
-      }
-    }
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(&ProcFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Perform a page erase of the specified FLASH memory pages  with interrupt enabled
-  * @note   To correctly run this function, the HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_Lock() to disable the flash memory access 
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  * @param  pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
-  *         contains the configuration information for the erasing.
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Process Locked */
-  __HAL_LOCK(&ProcFlash);
-
-  /* Enable End of FLASH Operation interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_EOP);
-  
-  /* Enable Error source interrupt */
-  __HAL_FLASH_ENABLE_IT(FLASH_IT_ERR);
-  
-  /* Clear pending flags (if any) */  
-  __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK);
-
-  /* Check the parameters */
-  assert_param(IS_NBPAGES(pEraseInit->NbPages));
-  assert_param(IS_TYPEERASE(pEraseInit->TypeErase));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress));
-  assert_param(IS_FLASH_PROGRAM_ADDRESS(pEraseInit->PageAddress + pEraseInit->NbPages * FLASH_PAGE_SIZE - 1));
-
-  ProcFlash.ProcedureOnGoing = FLASH_PROC_PAGEERASE;
-  ProcFlash.NbPagesToErase = pEraseInit->NbPages;
-  ProcFlash.Page = pEraseInit->PageAddress;
-
-  /*Erase 1st page and wait for IT*/
-  FLASH_ErasePage(pEraseInit->PageAddress);
-
-  return status;
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup FLASHEx_Exported_Functions_Group2 Option Bytes Programming functions
- *  @brief   Option Bytes Programming functions 
- *
-@verbatim   
-  ==============================================================================
-                ##### Option Bytes Programming functions ##### 
-  ==============================================================================  
-
-    [..] Any operation of erase or program should follow these steps:
-    (#) Call the HAL_FLASH_OB_Unlock() function to enable the Flash option control 
-        register access.
-    (#) Call following function to program the desired option bytes.
-        (++) HAL_FLASHEx_OBProgram:
-         - To Enable/Disable the desired sector write protection.
-         - To set the desired read Protection Level.
-         - To configure the user option Bytes: IWDG, STOP and the Standby.
-         - To Set the BOR level.
-    (#) Once all needed option bytes to be programmed are correctly written, call the
-        HAL_FLASH_OB_Launch(void) function to launch the Option Bytes programming process.
-    (#) Call the HAL_FLASH_OB_Lock() to disable the Flash option control register access (recommended
-        to protect the option Bytes against possible unwanted operations).
-
-    [..] Proprietary code Read Out Protection (PcROP):    
-    (#) The PcROP sector is selected by using the same option bytes as the Write
-        protection (nWRPi bits). As a result, these 2 options are exclusive each other.
-    (#) In order to activate the PcROP (change the function of the nWRPi option bits), 
-        the SPRMOD option bit must be activated.
-    (#) The active value of nWRPi bits is inverted when PCROP mode is active, this
-        means: if SPRMOD = 1 and nWRPi = 1 (default value), then the user sector "i"
-        is read/write protected.
-    (#) To activate PCROP mode for Flash sector(s), you need to call the following function:
-        (++) HAL_FLASHEx_AdvOBProgram in selecting sectors to be read/write protected
-        (++) HAL_FLASHEx_OB_SelectPCROP to enable the read/write protection
-    (#) PcROP is available only in STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Program option bytes
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&ProcFlash);
-
-  /* Check the parameters */
-  assert_param(IS_OPTIONBYTE(pOBInit->OptionType));
-
-  /*Write protection configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_WRP) == OPTIONBYTE_WRP)
-  {
-    assert_param(IS_WRPSTATE(pOBInit->WRPState));
-    if (pOBInit->WRPState == WRPSTATE_ENABLE)
-    {
-      /* Enable of Write protection on the selected Sector*/
-      status = FLASH_OB_WRPConfig(pOBInit, ENABLE);
-    }
-    else
-    {
-      /* Disable of Write protection on the selected Sector*/
-      status = FLASH_OB_WRPConfig(pOBInit, DISABLE);
-    }
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&ProcFlash);
-      return status;
-    }
-  }
-  
-  /* Read protection configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_RDP) == OPTIONBYTE_RDP)
-  {
-    status = FLASH_OB_RDPConfig(pOBInit->RDPLevel);
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&ProcFlash);
-      return status;
-    }
-  }
-  
-  /* USER  configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_USER) == OPTIONBYTE_USER)
-  {
-    status = FLASH_OB_UserConfig(pOBInit->USERConfig & OB_IWDG_SW, 
-                                 pOBInit->USERConfig & OB_STOP_NORST,
-                                 pOBInit->USERConfig & OB_STDBY_NORST);
-    if (status != HAL_OK)
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(&ProcFlash);
-      return status;
-    }
-  }
-
-  /* BOR Level  configuration*/
-  if((pOBInit->OptionType & OPTIONBYTE_BOR) == OPTIONBYTE_BOR)
-  {
-    status = FLASH_OB_BORConfig(pOBInit->BORLevel);
-  } 
-  /* Process Unlocked */
-  __HAL_UNLOCK(&ProcFlash);
-
-  return status;
-}
-
-/**
-  * @brief   Get the Option byte configuration
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval None
-  */
-void HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit)
-{
-  pOBInit->OptionType = OPTIONBYTE_WRP | OPTIONBYTE_RDP | OPTIONBYTE_USER | OPTIONBYTE_BOR;
-
-  /*Get WRP1*/
-  pOBInit->WRPSector0To31 = (uint32_t)(FLASH->WRPR1);
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-  /*Get WRP2*/
-  pOBInit->WRPSector32To63 = (uint32_t)(FLASH->WRPR2);
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-  /*Get WRP3*/
-  pOBInit->WRPSector64To95 = (uint32_t)(FLASH->WRPR3);
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-  /*Get WRP4*/
-  pOBInit->WRPSector96To127 = (uint32_t)(FLASH->WRPR4);
-
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
-
-  /*Get RDP Level*/
-  pOBInit->RDPLevel   = FLASH_OB_GetRDP();
-
-  /*Get USER*/
-  pOBInit->USERConfig = FLASH_OB_GetUser();
-
-  /*Get BOR Level*/
-  pOBInit->BORLevel   = FLASH_OB_GetBOR();
-  
-}
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-/**
-  * @brief  Program option bytes
-  * @note   This function can be used only for Cat2 & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2.
-  * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Check the parameters */
-  assert_param(IS_OBEX(pAdvOBInit->OptionType));
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-    
-  /* Cat2 & Cat3 devices only */
-  /*Program PCROP option byte*/
-  if ((pAdvOBInit->OptionType & OBEX_PCROP) == OBEX_PCROP)
-  {
-    /* Check the parameters */
-    assert_param(IS_PCROPSTATE(pAdvOBInit->PCROPState));
-    if (pAdvOBInit->PCROPState == PCROPSTATE_ENABLE)
-    {
-      /*Enable of Write protection on the selected Sector*/
-      status = FLASH_OB_PCROPConfig(pAdvOBInit, ENABLE);
-      if (status != HAL_OK)
-      {
-        return status;
-      }
-    }
-    else
-    {
-      /*Disable of Write protection on the selected Sector*/ 
-      status = FLASH_OB_PCROPConfig(pAdvOBInit, DISABLE);
-      if (status != HAL_OK)
-      {
-        return status;
-      }
-    }
-  }
-  
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-  /* Cat4 & Cat5 devices only */
-  /*Program BOOT config option byte*/
-  if ((pAdvOBInit->OptionType & OBEX_BOOTCONFIG) == OBEX_BOOTCONFIG)
-  {
-    status = FLASH_OB_BootConfig(pAdvOBInit->BootConfig);
-  }
-  
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-  return status;
-}
-
-/**
-  * @brief   Get the OBEX byte configuration
-  * @note   This function can be used only for Cat2  & Cat3 devices for PCROP and Cat4 & Cat5 for BFB2.
-  * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains the configuration information for the programming.
-  * 
-  * @retval None
-  */
-void HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit)
-{
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-      
-  pAdvOBInit->OptionType = OBEX_PCROP;
-
-  /*Get PCROP state */
-  pAdvOBInit->PCROPState = (FLASH->OBR & FLASH_OBR_SPRMOD) >> POSITION_VAL(FLASH_OBR_SPRMOD);
-  
-  /*Get PCROP protected sector from 0 to 31 */
-  pAdvOBInit->PCROPSector0To31 = FLASH->WRPR1;
-  
-  #if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-
-  /*Get PCROP protected sector from 32 to 63 */
-  pAdvOBInit->PCROPSector32To63 = FLASH->WRPR2;
-
-  #endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC */
-  
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-      
-  pAdvOBInit->OptionType = OBEX_BOOTCONFIG;
-
-  /*Get Boot config OB*/
-  pAdvOBInit->BootConfig = (FLASH->OBR & 0x80000000) >> 24;
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-}
-
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-
-/**
-  * @brief  Select the Protection Mode (SPRMOD).
-  * @note   This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices
-  * @note   Once SPRMOD bit is active, unprotection of a protected sector is not possible 
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint16_t tmp1 = 0;
-  uint32_t tmp2 = 0;
-  uint8_t optiontmp = 0;
-  uint16_t optiontmp2 = 0;
-  
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  /* Mask RDP Byte */
-  optiontmp =  (uint8_t)(*(__IO uint8_t *)(OB_BASE)); 
-  
-  /* Update Option Byte */
-  optiontmp2 = (uint16_t)(OB_PCROP_SELECTED | optiontmp); 
-  
-  /* calculate the option byte to write */
-  tmp1 = (uint16_t)(~(optiontmp2 ));
-  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2));
-  
-  if(status == HAL_OK)
-  {         
-    /* program PCRop */
-    OB->RDP = tmp2;
-  }
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  /* Return the Read protection operation Status */
-  return status;            
-}
-
-/**
-  * @brief  Deselect the Protection Mode (SPRMOD).
-  * @note   This function can be used only for STM32L151xBA, STM32L152xBA, STM32L151xC, STM32L152xC & STM32L162xC devices
-  * @note   Once SPRMOD bit is active, unprotection of a protected sector is not possible 
-  * @note   Read a protected sector will set RDERR Flag and write a protected sector will set WRPERR Flag
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint16_t tmp1 = 0;
-  uint32_t tmp2 = 0;
-  uint8_t optiontmp = 0;
-  uint16_t optiontmp2 = 0;
-  
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  /* Mask RDP Byte */
-  optiontmp =  (uint8_t)(*(__IO uint8_t *)(OB_BASE)); 
-  
-  /* Update Option Byte */
-  optiontmp2 = (uint16_t)(OB_PCROP_DESELECTED | optiontmp); 
-  
-  /* calculate the option byte to write */
-  tmp1 = (uint16_t)(~(optiontmp2 ));
-  tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)optiontmp2));
-  
-  if(status == HAL_OK)
-  {         
-    /* program PCRop */
-    OB->RDP = tmp2;
-  }
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  /* Return the Read protection operation Status */
-  return status;            
-}
-
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Exported_Functions_Group3 DATA EEPROM Programming functions
- *  @brief   DATA EEPROM Programming functions
- *
-@verbatim   
- ===============================================================================
-                     ##### DATA EEPROM Programming functions ##### 
- ===============================================================================  
- 
-    [..] Any operation of erase or program should follow these steps:
-    (#) Call the HAL_FLASHEx_DATAEEPROM_Unlock() function to enable the data EEPROM access
-        and Flash program erase control register access.
-    (#) Call the desired function to erase or program data.
-    (#) Call the HAL_FLASHEx_DATAEEPROM_Lock() to disable the data EEPROM access
-        and Flash program erase control register access(recommended
-        to protect the DATA_EEPROM against possible unwanted operation).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlocks the data memory and FLASH_PECR register access.
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void)
-{
-  if((FLASH->PECR & FLASH_PECR_PELOCK) != RESET)
-  {  
-    /* Unlocking the Data memory and FLASH_PECR register access*/
-    FLASH->PEKEYR = FLASH_PEKEY1;
-    FLASH->PEKEYR = FLASH_PEKEY2;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Locks the Data memory and FLASH_PECR register access.
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void)
-{
-  /* Set the PELOCK Bit to lock the data memory and FLASH_PECR register access */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PELOCK);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Erase a word in data memory.
-  * @param  Address: specifies the address to be erased.
-  * @param  TypeErase:  Indicate the way to erase at a specified address.
-  *         This parameter can be a value of @ref FLASH_Type_Program
-  * @note   To correctly run this function, the DATA_EEPROM_Unlock() function
-  *         must be called before.
-  *         Call the DATA_EEPROM_Lock() to the data EEPROM access
-  *         and Flash program erase control register access(recommended to protect 
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @retval FLASH Status: The returned value can be: 
-  *   FLASH_ERROR_PROGRAM, FLASH_ERROR_WRP, FLASH_COMPLETE or FLASH_TIMEOUT.
-  */
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_TYPEPROGRAMDATA(TypeErase));
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    if(TypeErase == TYPEERASEDATA_WORD)
-    {
-      /* Write 00000000h to valid address in the data memory */
-      *(__IO uint32_t *) Address = 0x00000000;
-    }
-
-    if(TypeErase == TYPEERASEDATA_HALFWORD)
-    {
-      /* Write 0000h to valid address in the data memory */
-      *(__IO uint16_t *) Address = (uint16_t)0x0000;
-    }
-
-    if(TypeErase == TYPEERASEDATA_BYTE)
-    {
-      /* Write 00h to valid address in the data memory */
-      *(__IO uint8_t *) Address = (uint8_t)0x00;
-    }
-  }
-   
-  /* Return the erase status */
-  return status;
-}  
-
-/**
-  * @brief  Program word at a specified address
-  * @note   To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASHEx_DATAEEPROM_Unlock() to he data EEPROM access
-  *         and Flash program erase control register access(recommended to protect 
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @note   The function  HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram() can be called before 
-  *         this function to configure the Fixed Time Programming.
-  * @param  TypeProgram:  Indicate the way to program at a specified address.
-  *         This parameter can be a value of @ref FLASHEx_Type_Program_Data
-  * @param  Address:  specifies the address to be programmed.
-  * @param  Data: specifies the data to be programmed
-  * 
-  * @retval HAL_StatusTypeDef HAL Status
-  */
-
-HAL_StatusTypeDef   HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_ERROR;
-  
-  /* Process Locked */
-  __HAL_LOCK(&ProcFlash);
-
-  /* Check the parameters */
-  assert_param(IS_TYPEPROGRAMDATA(TypeProgram));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    if(TypeProgram == TYPEPROGRAMDATA_FASTBYTE)
-    {
-      /*Program word (8-bit) at a specified address.*/
-      FLASH_DATAEEPROM_FastProgramByte(Address, (uint8_t) Data);
-    }
-    
-    if(TypeProgram == TYPEPROGRAMDATA_FASTHALFWORD)
-    {
-      /*Program word (16-bit) at a specified address.*/
-      FLASH_DATAEEPROM_FastProgramHalfWord(Address, (uint16_t) Data);
-    }    
-    
-    if(TypeProgram == TYPEPROGRAMDATA_FASTWORD)
-    {
-      /*Program word (32-bit) at a specified address.*/
-      FLASH_DATAEEPROM_FastProgramWord(Address, (uint32_t) Data);
-    }
-    
-    if(TypeProgram == TYPEPROGRAMDATA_WORD)
-    {
-      /*Program word (32-bit) at a specified address.*/
-      FLASH_DATAEEPROM_ProgramWord(Address, (uint32_t) Data);
-    }
-       
-    if(TypeProgram == TYPEPROGRAMDATA_HALFWORD)
-    {
-      /*Program word (16-bit) at a specified address.*/
-      FLASH_DATAEEPROM_ProgramHalfWord(Address, (uint16_t) Data);
-    }
-        
-    if(TypeProgram == TYPEPROGRAMDATA_BYTE)
-    {
-      /*Program word (8-bit) at a specified address.*/
-      FLASH_DATAEEPROM_ProgramByte(Address, (uint8_t) Data);
-    }
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation((uint32_t)HAL_FLASH_TIMEOUT_VALUE);
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(&ProcFlash);
-
-  return status;
-}
-
-/**
-  * @brief  Enable DATA EEPROM fixed Time programming (2*Tprog).
-  * @retval None
-  */
-void HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void)
-{
-  SET_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-}
-
-/**
-  * @brief  Disables DATA EEPROM fixed Time programming (2*Tprog).
-  * @retval None
-  */
-void HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void)
-{
-  CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Private_Functions FLASHEx Private functions
-  * @{
-  */
-
-/*
-==============================================================================
-              ##### FLASH STATIC functions ##### 
-==============================================================================
-*/
-
-/*
-==============================================================================
-              FLASH
-==============================================================================
-*/
-
-/**
-  * @brief  Set the specific FLASH error flag.
-  * @retval None
-  */
-static void FLASH_SetErrorCode(void)
-{ 
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR) != RESET)
-  {
-   ProcFlash.ErrorCode = FLASH_ERROR_WRP;
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR) != RESET)
-  {
-   ProcFlash.ErrorCode |= FLASH_ERROR_PGA;
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR) != RESET)
-  {
-    ProcFlash.ErrorCode |= FLASH_ERROR_SIZE;
-  }
-  
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR) != RESET)
-  {
-    ProcFlash.ErrorCode |= FLASH_ERROR_OPTV;
-  }
-  
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR) != RESET)
-  {
-    ProcFlash.ErrorCode |= FLASH_ERROR_RD;
-  }
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET)
-  {
-    ProcFlash.ErrorCode |= FLASH_ERROR_OPTVUSR;
-  }
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-}
-
-/**
-  * @brief  Erases a specified page in program memory.
-  * @param  PageAddress: The page address in program memory to be erased.
-  * @note   A Page is erased in the Program memory only if the address to load 
-  *         is the start address of a page (multiple of 256 bytes).
-  * @retval None
-  */
-static void FLASH_ErasePage(uint32_t PageAddress)
-{
-  /* Set the ERASE bit */
-  SET_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-  /* Set PROG bit */
-  SET_BIT(FLASH->PECR, FLASH_PECR_PROG);
-
-  /* Write 00000000h to the first word of the program page to erase */
-  *(__IO uint32_t *)PageAddress = 0x00000000;
-}
-  
-
-/*
-==============================================================================
-              OPTIONS BYTES
-==============================================================================
-*/
-/**
-  * @brief  Enables or disables the read out protection.
-  * @note   To correctly run this function, the HAL_FLASH_OB_Unlock() function
-  *         must be called before.
-  * @param  OB_RDP: specifies the read protection level. 
-  *   This parameter can be:
-  *     @arg OB_RDP_LEVEL0: No protection
-  *     @arg OB_RDP_LEVEL1: Read protection of the memory
-  *     @arg OB_RDP_LEVEL2: Chip protection
-  * 
-  *  !!!Warning!!! When enabling OB_RDP_LEVEL2 it's no more possible to go back to level 1 or 0
-  *   
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_RDPConfig(uint8_t OB_RDP)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp1 = 0, tmp2 = 0, sprmod = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_OB_RDP(OB_RDP));
-  
-  /* According to errata sheet, DocID022054 Rev 5, par2.1.5
-  Before setting Level0 in the RDP register, check that the current level is not equal to Level0.
-  If the current level is not equal to Level0, Level0 can be activated.
-  If the current level is Level0 then the RDP register must not be written again with Level0. */
-  tmp1 = (uint32_t)(OB->RDP & 0x000000FF);
-  
-  if ((tmp1 == OB_RDP_LEVEL0) && (OB_RDP == OB_RDP_LEVEL0))
-  {
-    /*current level is Level0 then the RDP register must not be written again with Level0. */
-    status = HAL_ERROR;
-  }
-  else 
-  {
-    /* Mask SPRMOD bit */
-    sprmod = (uint32_t)(OB->RDP & 0x00000100);
-
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-    
-    /* calculate the option byte to write */
-    tmp1 = (~((uint32_t)(OB_RDP | sprmod)));
-    tmp2 = (uint32_t)(((uint32_t)((uint32_t)(tmp1) << 16)) | ((uint32_t)(OB_RDP | sprmod)));
-    
-    if(status == HAL_OK)
-    {         
-     /* program read protection level */
-      OB->RDP = tmp2;
-    }
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  }
-     
-  /* Return the Read protection operation Status */
-  return status;            
-}
-
-/**
-  * @brief  Programs the FLASH brownout reset threshold level Option Byte.
-  * @param  OB_BOR: Selects the brownout reset threshold level.
-  *   This parameter can be one of the following values:
-  *     @arg OB_BOR_OFF: BOR is disabled at power down, the reset is asserted when the VDD 
-  *                      power supply reaches the PDR(Power Down Reset) threshold (1.5V)
-  *     @arg OB_BOR_LEVEL1: BOR Reset threshold levels for 1.7V - 1.8V VDD power supply
-  *     @arg OB_BOR_LEVEL2: BOR Reset threshold levels for 1.9V - 2.0V VDD power supply
-  *     @arg OB_BOR_LEVEL3: BOR Reset threshold levels for 2.3V - 2.4V VDD power supply
-  *     @arg OB_BOR_LEVEL4: BOR Reset threshold levels for 2.55V - 2.65V VDD power supply
-  *     @arg OB_BOR_LEVEL5: BOR Reset threshold levels for 2.8V - 2.9V VDD power supply
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_BORConfig(uint8_t OB_BOR)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp = 0, tmp1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOR_LEVEL(OB_BOR));
-
-  /* Get the User Option byte register */
-  tmp1 = (FLASH->OBR & (FLASH_OBR_USER)) >> 16;
-     
-  /* Calculate the option byte to write - [0xFF | nUSER | 0x00 | USER]*/
-  tmp = (uint32_t)~((OB_BOR | tmp1)) << 16;
-  tmp |= (OB_BOR | tmp1);
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {  
-    /* Write the BOR Option Byte */            
-    OB->USER = tmp; 
-  }
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-        
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-/**
-  * @brief  Returns the FLASH User Option Bytes values.
-  * @retval The FLASH User Option Bytes.
-  */
-static uint8_t FLASH_OB_GetUser(void)
-{
-  /* Return the User Option Byte */
-  return (uint8_t)((FLASH->OBR & FLASH_OBR_USER) >> POSITION_VAL(FLASH_OBR_USER));
-}
-
-/**
-  * @brief  Checks whether the FLASH Read out Protection Status is set or not.
-  * @retval FLASH ReadOut Protection
-  */
-static uint8_t FLASH_OB_GetRDP(void)
-{
-  return (uint8_t)(FLASH->OBR & FLASH_OBR_RDPRT);
-}
-
-/**
-  * @brief  Returns the FLASH BOR level.
-  * @retval The FLASH User Option Bytes.
-  */
-static uint8_t FLASH_OB_GetBOR(void)
-{
-  /* Return the BOR level */
-  return (uint8_t)((FLASH->OBR & (uint32_t)FLASH_OBR_BOR_LEV) >> POSITION_VAL(FLASH_OBR_BOR_LEV));
-}
-
-/**
-  * @brief  Write protects the desired pages of the first 64KB of the Flash.
-  * @param  pOBInit: pointer to an FLASH_OBInitStruct structure that
-  *         contains WRP parameters.
-  * @param  NewState: new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval HAL_StatusTypeDef
-  */
-static HAL_StatusTypeDef FLASH_OB_WRPConfig(FLASH_OBProgramInitTypeDef *pOBInit, FunctionalState NewState)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
- 
-  if(status == HAL_OK)
-  {
-    /* WRP for sector between 0 to 31 */
-    if (pOBInit->WRPSector0To31 != 0)
-    {
-      FLASH_OB_WRPConfigWRP1OrPCROP1(pOBInit->WRPSector0To31, NewState);
-    }
-    
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-      defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-      defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-      
-    /* Pages for Cat3, Cat4 & Cat5 devices*/
-    /* WRP for sector between 32 to 63 */
-    if (pOBInit->WRPSector32To63 != 0)
-    {
-      FLASH_OB_WRPConfigWRP2OrPCROP2(pOBInit->WRPSector32To63, NewState);
-    }
-    
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-      
-    /* Pages for devices with FLASH >= 256KB*/
-    /* WRP for sector between 64 to 95 */
-    if (pOBInit->WRPSector64To95 != 0)
-    {
-      FLASH_OB_WRPConfigWRP3(pOBInit->WRPSector64To95, NewState);
-    }
-    
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-    /* Pages for Cat5 devices*/
-    /* WRP for sector between 96 to 127 */
-    if (pOBInit->WRPSector96To127 != 0)
-    {
-      FLASH_OB_WRPConfigWRP4(pOBInit->WRPSector96To127, NewState);
-    }
-    
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the write protection operation Status */
-  return status;      
-}
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-/**
-  * @brief  Enables the read/write protection (PCROP) of the desired 
-  *         sectors.
-  * @note   This function can be used only for Cat2 & Cat3 devices
-  * @param  pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
-  *         contains PCROP parameters.
-  * @param  NewState: new state of the specified FLASH Pages read/Write protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_PCROPConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit, FunctionalState NewState)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  FunctionalState pcropstate = DISABLE;
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  /* Invert state to use same function of WRP */
-  if (NewState == DISABLE)
-  {
-    pcropstate = ENABLE;
-  }
-        
-  if(status == HAL_OK)
-  {
-    /* Pages for Cat2 devices*/
-    /* PCROP for sector between 0 to 31 */
-    if (pAdvOBInit->PCROPSector0To31 != 0)
-    {
-      FLASH_OB_WRPConfigWRP1OrPCROP1(pAdvOBInit->PCROPSector0To31, pcropstate);
-    }
-    
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-
-    /* Pages for Cat3 devices*/
-    /* WRP for sector between 32 to 63 */
-    if (pAdvOBInit->PCROPSector32To63 != 0)
-    {
-      FLASH_OB_WRPConfigWRP2OrPCROP2(pAdvOBInit->PCROPSector32To63, pcropstate);
-    }
-    
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC  */
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  }
-
-  /* Return the write protection operation Status */
-  return status;      
-}
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-/**
-  * @brief  Write protects the desired pages of the first 128KB of the Flash.
-  * @param  WRP1OrPCROP1: specifies the address of the pages to be write protected.
-  *   This parameter can be:
-  *     @arg  value between OB_WRP1/PCROP1_PAGES0TO15 and OB_WRP1/PCROP1_PAGES496TO511
-  *     @arg  OB_WRP1/PCROP1_ALLPAGES
-  * @param  NewState: new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-static void FLASH_OB_WRPConfigWRP1OrPCROP1(uint32_t WRP1OrPCROP1, FunctionalState NewState)
-{
-  uint32_t wrp01data = 0, wrp23data = 0;
-  
-  uint32_t tmp1 = 0, tmp2 = 0;
-  
-  if (NewState != DISABLE)
-  {
-    wrp01data = (uint16_t)(((WRP1OrPCROP1 & WRP_MASK_LOW) | OB->WRP01));
-    wrp23data = (uint16_t)((((WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 | OB->WRP23))); 
-    tmp1 = (uint32_t)(~(wrp01data) << 16)|(wrp01data);
-    OB->WRP01 = tmp1;
-
-    tmp2 = (uint32_t)(~(wrp23data) << 16)|(wrp23data);
-    OB->WRP23 = tmp2;      
-  }
-  else
-  {
-    wrp01data = (uint16_t)(~WRP1OrPCROP1 & (WRP_MASK_LOW & OB->WRP01));
-    wrp23data = (uint16_t)((((~WRP1OrPCROP1 & WRP_MASK_HIGH)>>16 & OB->WRP23))); 
-
-    tmp1 = (uint32_t)((~wrp01data) << 16)|(wrp01data);
-    OB->WRP01 = tmp1;
-    
-    tmp2 = (uint32_t)((~wrp23data) << 16)|(wrp23data);
-    OB->WRP23 = tmp2;
-  }
-}
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
-  * @brief  Enable Write protects the desired pages of the second 128KB of the Flash.
-  * @note   This function can be used only for Cat3, Cat4  & Cat5 devices.
-  * @param  WRP2OrPCROP2: specifies the address of the pages to be write protected.
-  *   This parameter can be:
-  *     @arg  value between OB_WRP2/PCROP2_PAGES512TO527 and OB_WRP2/PCROP2_PAGES1008TO1023
-  *     @arg OB_WRP2/PCROP2_ALLPAGES
-  * @param  NewState: new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-static void FLASH_OB_WRPConfigWRP2OrPCROP2(uint32_t WRP2OrPCROP2, FunctionalState NewState)
-{
-  uint32_t wrp45data = 0, wrp67data = 0;
-  
-  uint32_t tmp1 = 0, tmp2 = 0;
-  
-  if (NewState != DISABLE)
-  {
-    wrp45data = (uint16_t)(((WRP2OrPCROP2 & WRP_MASK_LOW) | OB->WRP45));
-    wrp67data = (uint16_t)((((WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 | OB->WRP67))); 
-    tmp1 = (uint32_t)(~(wrp45data) << 16)|(wrp45data);
-    OB->WRP45 = tmp1;
-    
-    tmp2 = (uint32_t)(~(wrp67data) << 16)|(wrp67data);
-    OB->WRP67 = tmp2;
-  }
-  else
-  {
-    wrp45data = (uint16_t)(~WRP2OrPCROP2 & (WRP_MASK_LOW & OB->WRP45));
-    wrp67data = (uint16_t)((((~WRP2OrPCROP2 & WRP_MASK_HIGH)>>16 & OB->WRP67))); 
-    
-    tmp1 = (uint32_t)((~wrp45data) << 16)|(wrp45data);
-    OB->WRP45 = tmp1;
-    
-    tmp2 = (uint32_t)((~wrp67data) << 16)|(wrp67data);
-    OB->WRP67 = tmp2;
-  }
-}
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
-  * @brief  Enable Write protects the desired pages of the third 128KB of the Flash.
-  * @note   This function can be used only for STM32L151xD, STM32L152xD, STM32L162xD  & Cat5 devices.
-  * @param  WRP3: specifies the address of the pages to be write protected.
-  *   This parameter can be:
-  *     @arg  value between WRP3_PAGES1024TO1039 and OB_WRP3_PAGES1520TO1535
-  *     @arg OB_WRP3_ALLPAGES
-  * @param  NewState: new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-static void FLASH_OB_WRPConfigWRP3(uint32_t WRP3, FunctionalState NewState)
-{
-  uint32_t wrp89data = 0, wrp1011data = 0;
-  
-  uint32_t tmp1 = 0, tmp2 = 0;
-  
-  if (NewState != DISABLE)
-  {
-    wrp89data = (uint16_t)(((WRP3 & WRP_MASK_LOW) | OB->WRP89));
-    wrp1011data = (uint16_t)((((WRP3 & WRP_MASK_HIGH)>>16 | OB->WRP1011))); 
-    tmp1 = (uint32_t)(~(wrp89data) << 16)|(wrp89data);
-    OB->WRP89 = tmp1;
-
-    tmp2 = (uint32_t)(~(wrp1011data) << 16)|(wrp1011data);
-    OB->WRP1011 = tmp2;      
-  }
-  else
-  {
-    wrp89data = (uint16_t)(~WRP3 & (WRP_MASK_LOW & OB->WRP89));
-    wrp1011data = (uint16_t)((((~WRP3 & WRP_MASK_HIGH)>>16 & OB->WRP1011))); 
-
-    tmp1 = (uint32_t)((~wrp89data) << 16)|(wrp89data);
-    OB->WRP89 = tmp1;
-
-    tmp2 = (uint32_t)((~wrp1011data) << 16)|(wrp1011data);
-    OB->WRP1011 = tmp2;
-  }
-}
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
-  * @brief  Enable Write protects the desired pages of the Fourth 128KB of the Flash.
-  * @note   This function can be used only for Cat5 devices.
-  * @param  WRP4: specifies the address of the pages to be write protected.
-  *   This parameter can be:
-  *     @arg  value between OB_WRP4_PAGES1536TO1551 and OB_WRP4_PAGES2032TO2047
-  *     @arg OB_WRP4_ALLPAGES
-  * @param  NewState: new state of the specified FLASH Pages Wtite protection.
-  *   This parameter can be: ENABLE or DISABLE.
-  * @retval None
-  */
-static void FLASH_OB_WRPConfigWRP4(uint32_t WRP4, FunctionalState NewState)
-{
-  uint32_t wrp1213data = 0, wrp1415data = 0;
-  
-  uint32_t tmp1 = 0, tmp2 = 0;
-  
-  if (NewState != DISABLE)
-  {
-    wrp1213data = (uint16_t)(((WRP4 & WRP_MASK_LOW) | OB->WRP1213));
-    wrp1415data = (uint16_t)((((WRP4 & WRP_MASK_HIGH)>>16 | OB->WRP1415))); 
-    tmp1 = (uint32_t)(~(wrp1213data) << 16)|(wrp1213data);
-    OB->WRP1213 = tmp1;
-
-    tmp2 = (uint32_t)(~(wrp1415data) << 16)|(wrp1415data);
-    OB->WRP1415 = tmp2;      
-  }
-  else
-  {
-    wrp1213data = (uint16_t)(~WRP4 & (WRP_MASK_LOW & OB->WRP1213));
-    wrp1415data = (uint16_t)((((~WRP4 & WRP_MASK_HIGH)>>16 & OB->WRP1415))); 
-
-    tmp1 = (uint32_t)((~wrp1213data) << 16)|(wrp1213data);
-    OB->WRP1213 = tmp1;
-
-    tmp2 = (uint32_t)((~wrp1415data) << 16)|(wrp1415data);
-    OB->WRP1415 = tmp2;
-  }
-}
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-  * @param  OB_IWDG: Selects the WDG mode.
-  *   This parameter can be one of the following values:
-  *     @arg OB_IWDG_SW: Software WDG selected
-  *     @arg OB_IWDG_HW: Hardware WDG selected
-  * @param  OB_STOP: Reset event when entering STOP mode.
-  *   This parameter can be one of the following values:
-  *     @arg OB_STOP_NORST: No reset generated when entering in STOP
-  *     @arg OB_STOP_RST: Reset generated when entering in STOP
-  * @param  OB_STDBY: Reset event when entering Standby mode.
-  *   This parameter can be one of the following values:
-  *     @arg OB_STDBY_NORST: No reset generated when entering in STANDBY
-  *     @arg OB_STDBY_RST: Reset generated when entering in STANDBY
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
-{
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t tmp = 0, tmp1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
-  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
-  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
-
-  /* Get the User Option byte register */
-  tmp1 = (FLASH->OBR & FLASH_OBR_BOR_LEV) >> 16;
-  
-  /* Calculate the user option byte to write */ 
-  tmp = (uint32_t)(((uint32_t)~((uint32_t)((uint32_t)(OB_IWDG) | (uint32_t)(OB_STOP) | (uint32_t)(OB_STDBY) | tmp1))) << 16);
-  tmp |= ((uint32_t)(OB_IWDG) | ((uint32_t)OB_STOP) | (uint32_t)(OB_STDBY) | tmp1);
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {  
-    /* Write the User Option Byte */              
-    OB->USER = tmp; 
-  }
-  
-  /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-       
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
-  * @brief  Configures to boot from Bank1 or Bank2.
-  * @param  OB_BOOT: select the FLASH Bank to boot from.
-  *   This parameter can be one of the following values:
-  *     @arg OB_BOOT_BANK2: At startup, if boot pins are set in boot from user Flash
-  *        position and this parameter is selected the device will boot from Bank2 or Bank1,
-  *        depending on the activation of the bank. The active banks are checked in
-  *        the following order: Bank2, followed by Bank1.
-  *        The active bank is recognized by the value programmed at the base address
-  *        of the respective bank (corresponding to the initial stack pointer value
-  *        in the interrupt vector table).
-  *     @arg OB_BOOT_BANK1: At startup, if boot pins are set in boot from user Flash
-  *        position and this parameter is selected the device will boot from Bank1(Default).
-  *        For more information, please refer to AN2606 from www.st.com. 
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_OB_BootConfig(uint8_t OB_BOOT)
-{
-  HAL_StatusTypeDef status = HAL_OK; 
-  uint32_t tmp = 0, tmp1 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_OB_BOOT_BANK(OB_BOOT));
-
-  /* Get the User Option byte register  and BOR Level*/
-  tmp1 = (FLASH->OBR & (FLASH_OBR_nRST_STDBY | FLASH_OBR_nRST_STOP | FLASH_OBR_IWDG_SW | FLASH_OBR_BOR_LEV)) >> 16;
-     
-  /* Calculate the option byte to write */
-  tmp = (uint32_t)~(OB_BOOT | tmp1) << 16;
-  tmp |= (OB_BOOT | tmp1);
-    
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {  
-    /* Write the BOOT Option Byte */            
-    OB->USER = tmp; 
-  }
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-       
-  /* Return the Option Byte program Status */
-  return status;
-}
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/*
-==============================================================================
-              DATA
-==============================================================================
-*/
-
-/**
-  * @brief  Write a Byte at a specified address in data memory.
-  * @param  Address: specifies the address to be written.
-  * @param  Data: specifies the data to be written.
-  * @note   This function assumes that the is data word is already erased.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramByte(uint32_t Address, uint8_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-  uint32_t tmp = 0, tmpaddr = 0;
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address)); 
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-    
-  if(status == HAL_OK)
-  {
-    /* Clear the FTDW bit */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-    /* Possible only on Cat1 devices */
-    if(Data != (uint8_t)0x00) 
-    {
-      /* If the previous operation is completed, proceed to write the new Data */
-      *(__IO uint8_t *)Address = Data;
-            
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-    }
-    else
-    {
-      tmpaddr = Address & 0xFFFFFFFC;
-      tmp = * (__IO uint32_t *) tmpaddr;
-      tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
-      tmp &= ~tmpaddr;
-      status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
-      status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
-    }       
-#else /*!Cat1*/ 
-    /* If the previous operation is completed, proceed to write the new Data */
-    *(__IO uint8_t *)Address = Data;
-            
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Writes a half word at a specified address in data memory.
-  * @param  Address: specifies the address to be written.
-  * @param  Data: specifies the data to be written.
-  * @note   This function assumes that the is data word is already erased.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramHalfWord(uint32_t Address, uint16_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-  uint32_t tmp = 0, tmpaddr = 0;
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-    
-  if(status == HAL_OK)
-  {
-    /* Clear the FTDW bit */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-    /* Possible only on Cat1 devices */
-    if(Data != (uint16_t)0x0000) 
-    {
-      /* If the previous operation is completed, proceed to write the new data */
-      *(__IO uint16_t *)Address = Data;
-  
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-    }
-    else
-    {
-      if((Address & 0x3) != 0x3)
-      {
-        tmpaddr = Address & 0xFFFFFFFC;
-        tmp = * (__IO uint32_t *) tmpaddr;
-        tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
-        tmp &= ~tmpaddr;        
-        status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
-        status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
-      }
-      else
-      {
-        HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address, 0x00);
-        HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00);
-      }
-    }
-#else /* !Cat1 */
-    /* If the previous operation is completed, proceed to write the new data */
-    *(__IO uint16_t *)Address = Data;
-  
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a word at a specified address in data memory.
-  * @param  Address: specifies the address to be written.
-  * @param  Data: specifies the data to be written.
-  * @note   This function assumes that the is data word is already erased.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_FastProgramWord(uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* Clear the FTDW bit */
-    CLEAR_BIT(FLASH->PECR, FLASH_PECR_FTDW);
-  
-    /* If the previous operation is completed, proceed to program the new data */    
-    *(__IO uint32_t *)Address = Data;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);       
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Write a Byte at a specified address in data memory without erase.
-  * @param  Address: specifies the address to be written.
-  * @param  Data: specifies the data to be written.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramByte(uint32_t Address, uint8_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-  uint32_t tmp = 0, tmpaddr = 0;
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address)); 
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-    if(Data != (uint8_t) 0x00)
-    {  
-      *(__IO uint8_t *)Address = Data;
-    
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-
-    }
-    else
-    {
-      tmpaddr = Address & 0xFFFFFFFC;
-      tmp = * (__IO uint32_t *) tmpaddr;
-      tmpaddr = 0xFF << ((uint32_t) (0x8 * (Address & 0x3)));
-      tmp &= ~tmpaddr;        
-      status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
-      status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
-    }
-#else /* Not Cat1*/
-    *(__IO uint8_t *)Address = Data;
-    
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Writes a half word at a specified address in data memory without erase.
-  * @param  Address: specifies the address to be written.
-  * @param  Data: specifies the data to be written.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramHalfWord(uint32_t Address, uint16_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-  uint32_t tmp = 0, tmpaddr = 0;
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-    if(Data != (uint16_t)0x0000)
-    {
-      *(__IO uint16_t *)Address = Data;
-   
-      /* Wait for last operation to be completed */
-      status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-    }
-    else
-    {
-      if((Address & 0x3) != 0x3)
-      {
-        tmpaddr = Address & 0xFFFFFFFC;
-        tmp = * (__IO uint32_t *) tmpaddr;
-        tmpaddr = 0xFFFF << ((uint32_t) (0x8 * (Address & 0x3)));
-        tmp &= ~tmpaddr;          
-        status = HAL_FLASHEx_DATAEEPROM_Erase(TYPEERASEDATA_WORD, Address & 0xFFFFFFFC);
-        status = HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTWORD, (Address & 0xFFFFFFFC), tmp);
-      }
-      else
-      {
-        HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address, 0x00);
-        HAL_FLASHEx_DATAEEPROM_Program(TYPEPROGRAMDATA_FASTBYTE, Address + 1, 0x00);
-      }
-    }
-#else /* Not Cat1*/
-    *(__IO uint16_t *)Address = Data;
-   
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB  */
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @brief  Programs a word at a specified address in data memory without erase.
-  * @param  Address: specifies the address to be written.
-  * @param  Data: specifies the data to be written.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef FLASH_DATAEEPROM_ProgramWord(uint32_t Address, uint32_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the parameters */
-  assert_param(IS_FLASH_DATA_ADDRESS(Address));
-  
-  /* Wait for last operation to be completed */
-  status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    *(__IO uint32_t *)Address = Data;
-
-    /* Wait for last operation to be completed */
-    status = FLASH_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  }
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASH
-  * @{
-  */ 
-
-/** @addtogroup FLASH_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASH_Exported_Functions_Group1
- *  @brief   Interrupts  functions
- *
-@verbatim   
-  ==============================================================================
-              ##### Interrupts  functions #####
-  ==============================================================================    
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief This function handles FLASH interrupt request.
-  * @retval None
-  */
-void HAL_FLASH_IRQHandler(void)
-{
-  uint32_t temp;
-  
-  /* If the program operation is completed, disable the PROG Bit */
-  CLEAR_BIT(FLASH->PECR, FLASH_PECR_PROG);
-
-  /* If the erase operation is completed, disable the ERASE Bit */
-  CLEAR_BIT(FLASH->PECR, FLASH_PECR_ERASE);
-
-  /* Check FLASH End of Operation flag  */
-  if(__HAL_FLASH_GET_FLAG(FLASH_FLAG_EOP) != RESET)
-  {
-    if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
-    {
-      /*Nb of sector to erased can be decreased*/
-      ProcFlash.NbPagesToErase--;
-
-      /* Check if there are still sectors to erase*/
-      if(ProcFlash.NbPagesToErase != 0)
-      {
-        temp = ProcFlash.Page;
-        /*Indicate user which sector has been erased*/
-        HAL_FLASH_EndOfOperationCallback(temp);
-
-        /* Clear pending flags (if any) */  
-        __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK);  
-
-        /*Increment sector number*/
-        temp = ProcFlash.Page + FLASH_PAGE_SIZE;
-        ProcFlash.Page = ProcFlash.Page + FLASH_PAGE_SIZE;
-        FLASH_ErasePage(temp);
-      }
-      else
-      {
-        /*No more sectors to Erase, user callback can be called.*/
-        /*Reset Sector and stop Erase sectors procedure*/
-        ProcFlash.Page = temp = 0xFFFFFFFF;
-        ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(temp);
-        /* Clear FLASH End of Operation pending bit */
-        __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-      }
-    }
-    else 
-    {
-      if(ProcFlash.ProcedureOnGoing  == FLASH_PROC_PROGRAM)
-      {
-        /*Program ended. Return the selected address*/
-        /* FLASH EOP interrupt user callback */
-        HAL_FLASH_EndOfOperationCallback(ProcFlash.Address);
-      }
-      ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-      /* Clear FLASH End of Operation pending bit */
-      __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_EOP);
-    }
-
-  }
-  
-  /* Check FLASH operation error flags */
-  if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     != RESET) || 
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)     != RESET) || 
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)     != RESET) || 
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)      != RESET) || 
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || 
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)    != RESET) )
-  {
-    if(ProcFlash.ProcedureOnGoing == FLASH_PROC_PAGEERASE)
-    {
-      /*return the faulty sector*/
-      temp = ProcFlash.Page;
-      ProcFlash.Page = 0xFFFFFFFF;
-    }
-    else
-    {
-      /*retrun the faulty address*/
-      temp = ProcFlash.Address;
-    }
-    
-    /*Save the Error code*/
-    FLASH_SetErrorCode();
-
-    /* FLASH error interrupt user callback */
-    HAL_FLASH_OperationErrorCallback(temp);
-    
-    /* Clear FLASH error pending bits */
-    __HAL_FLASH_CLEAR_FLAG(FLASH_FLAG_MASK);
-
-    /*Stop the procedure ongoing*/
-    ProcFlash.ProcedureOnGoing = FLASH_PROC_NONE;
-  }
-  
-  if(ProcFlash.ProcedureOnGoing == FLASH_PROC_NONE)
-  {
-    /* Disable End of FLASH Operation interrupt */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_EOP);
-
-    /* Disable Error source interrupt */
-    __HAL_FLASH_DISABLE_IT(FLASH_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(&ProcFlash);
-  }
-    
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASH_Internal_Functions FLASH Internal function
-  * @{
-  */
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout: maximum flash operationtimeout
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
-{ 
-  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-     Even if the FLASH operation fails, the BUSY flag will be reset and an error
-     flag will be set */
-    
-  uint32_t tickstart = HAL_GetTick();   
-     
-  while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) != RESET) 
-  { 
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        return HAL_TIMEOUT;
-      }
-    } 
-  }
-  
-  if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     != RESET) || 
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)     != RESET) || 
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)     != RESET) || 
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)      != RESET) || 
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || 
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-      (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)    != RESET) )
-  {
-    /*Save the error code*/
-    FLASH_SetErrorCode();
-    return HAL_ERROR;
-  }
-
-  /* There is no error flag set */
-  return HAL_OK;
-}
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,975 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of Flash HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_FLASH_EX_H
-#define __STM32L1xx_HAL_FLASH_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup FLASHEx_Exported_Types FLASHEx Exported Types
-  * @{
-  */  
-
-/**
-  * @brief  FLASH Erase structure definition
-  */
-typedef struct
-{
-  uint32_t TypeErase;   /*!< TypeErase: Page Erase only.
-                              This parameter can be a value of @ref FLASHEx_Type_Erase */
-
-  uint32_t PageAddress;     /*!< PageAddress: Initial FLASH address to be erased
-                              This parameter must be a value belonging to FLASH Programm address (depending on the devices)  */
-  
-  uint32_t NbPages; /*!< NbPages: Number of pages to be erased.
-                              This parameter must be a value between 1 and (max number of pages - value of Initial page)*/
-  
-} FLASH_EraseInitTypeDef;
-
-/**
-  * @brief  FLASH Option Bytes PROGRAM structure definition
-  */
-typedef struct
-{
-  uint32_t  OptionType;     /*!< OptionType: Option byte to be configured.
-                              This parameter can be a value of @ref FLASHEx_Option_Type */
-
-  uint32_t  WRPState;      /*!< WRPState: Write protection activation or deactivation.
-                              This parameter can be a value of @ref FLASHEx_WRP_State */
-
-  uint32_t  WRPSector0To31;    /*!< WRPSector0To31: specifies the sector(s) which are write protected between Sector 0 to 31
-                              This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection1 */  
-  
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-  uint32_t  WRPSector32To63;    /*!< WRPSector32To63: specifies the sector(s) which are write protected between Sector 32 to 63
-                                This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection2 */  
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-  uint32_t  WRPSector64To95;    /*!< WRPSector64to95: specifies the sector(s) which are write protected between Sector 64 to 95
-                                This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection3 */  
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-  uint32_t  WRPSector96To127;    /*!< WRPSector96To127: specifies the sector(s) which are write protected between Sector 96 to 127
-                              This parameter can be a combination of @ref FLASHEx_Option_Bytes_Write_Protection4 */  
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
-                              
-  uint8_t   RDPLevel;     /*!< RDPLevel: Set the read protection level..
-                              This parameter can be a value of @ref FLASHEx_Option_Bytes_Read_Protection */
-
-  uint8_t   BORLevel;     /*!< BORLevel: Set the BOR Level.
-                              This parameter can be a value of @ref FLASHEx_Option_Bytes_BOR_Level */
-                                
-  uint8_t   USERConfig;     /*!< USERConfig: Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
-                              This parameter can be a combination of @ref FLASHEx_Option_Bytes_IWatchdog, @ref FLASHEx_Option_Bytes_nRST_STOP and @ref FLASHEx_Option_Bytes_nRST_STDBY*/
-} FLASH_OBProgramInitTypeDef;
-
-/**
-  * @brief  FLASH Advanced Option Bytes Program structure definition
-  */
-typedef struct
-{
-  uint32_t OptionType;     /*!< OptionType: Option byte to be configured for extension .
-                              This parameter can be a value of @ref FLASHEx_OptionAdv_Type */
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-  uint32_t PCROPState;    /*!< PCROPState: PCROP activation or deactivation.
-                              This parameter can be a value of @ref FLASHEx_PCROP_State */
-
-  uint32_t  PCROPSector0To31;    /*!< PCROPSector0To31: specifies the sector(s) set for PCROP
-                            This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 */
-  
-#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-  uint32_t  PCROPSector32To63;    /*!< PCROPSector32To63: specifies the sector(s) set for PCROP
-                            This parameter can be a value of @ref FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 */
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
- 
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-  uint16_t BootConfig;         /*!< BootConfig: specifies Option bytes for boot config
-                                This parameter can be a value of @ref FLASHEx_Option_Bytes_BOOT */
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
-} FLASH_AdvOBProgramInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-
-/** @defgroup FLASHEx_Exported_Constants FLASHEx Exported Constants
-  * @{
-  */  
-
-/** @defgroup FLASHEx_Type_Erase FLASHEx_Type_Erase
-  * @{
-  */
-#define TYPEERASE_PAGES           ((uint32_t)0x00)  /*!<Page erase only*/
- 
-#define IS_TYPEERASE(__VALUE__)   (((__VALUE__) == TYPEERASE_PAGES))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Type FLASHEx Option Type
-  * @{
-  */
-#define OPTIONBYTE_WRP            ((uint32_t)0x01)  /*!<WRP option byte configuration*/
-#define OPTIONBYTE_RDP            ((uint32_t)0x02)  /*!<RDP option byte configuration*/
-#define OPTIONBYTE_USER           ((uint32_t)0x04)  /*!<USER option byte configuration*/
-#define OPTIONBYTE_BOR            ((uint32_t)0x08)  /*!<BOR option byte configuration*/
-
-#define IS_OPTIONBYTE(__VALUE__)  (((__VALUE__) < (OPTIONBYTE_WRP|OPTIONBYTE_RDP|OPTIONBYTE_USER|OPTIONBYTE_BOR)))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_WRP_State FLASHEx WRP State
-  * @{
-  */
-#define WRPSTATE_DISABLE        ((uint32_t)0x00)  /*!<Disable the write protection of the desired bank 1 sectors*/
-#define WRPSTATE_ENABLE         ((uint32_t)0x01)  /*!<Enable the write protection of the desired bank 1 sectors*/
-
-#define IS_WRPSTATE(__VALUE__)  (((__VALUE__) == WRPSTATE_DISABLE) || \
-                                 ((__VALUE__) == WRPSTATE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Mask FLASHEx Option Bytes Write Mask
-  * @{
-  */ 
-#define WRP_MASK_LOW                 ((uint32_t)0x0000FFFF)
-#define WRP_MASK_HIGH                 ((uint32_t)0xFFFF0000)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection1 FLASHEx Option Bytes Write Protection1
-  * @{
-  */
-  
-/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
-#define OB_WRP1_PAGES0TO15    ((uint32_t)0x00000001) /* Write protection of Sector0 */  
-#define OB_WRP1_PAGES16TO31   ((uint32_t)0x00000002) /* Write protection of Sector1 */  
-#define OB_WRP1_PAGES32TO47   ((uint32_t)0x00000004) /* Write protection of Sector2 */  
-#define OB_WRP1_PAGES48TO63   ((uint32_t)0x00000008) /* Write protection of Sector3 */  
-#define OB_WRP1_PAGES64TO79   ((uint32_t)0x00000010) /* Write protection of Sector4 */  
-#define OB_WRP1_PAGES80TO95   ((uint32_t)0x00000020) /* Write protection of Sector5 */  
-#define OB_WRP1_PAGES96TO111  ((uint32_t)0x00000040) /* Write protection of Sector6 */  
-#define OB_WRP1_PAGES112TO127 ((uint32_t)0x00000080) /* Write protection of Sector7 */  
-#define OB_WRP1_PAGES128TO143 ((uint32_t)0x00000100) /* Write protection of Sector8 */  
-#define OB_WRP1_PAGES144TO159 ((uint32_t)0x00000200) /* Write protection of Sector9 */  
-#define OB_WRP1_PAGES160TO175 ((uint32_t)0x00000400) /* Write protection of Sector10 */ 
-#define OB_WRP1_PAGES176TO191 ((uint32_t)0x00000800) /* Write protection of Sector11 */ 
-#define OB_WRP1_PAGES192TO207 ((uint32_t)0x00001000) /* Write protection of Sector12 */ 
-#define OB_WRP1_PAGES208TO223 ((uint32_t)0x00002000) /* Write protection of Sector13 */ 
-#define OB_WRP1_PAGES224TO239 ((uint32_t)0x00004000) /* Write protection of Sector14 */ 
-#define OB_WRP1_PAGES240TO255 ((uint32_t)0x00008000) /* Write protection of Sector15 */ 
-#define OB_WRP1_PAGES256TO271 ((uint32_t)0x00010000) /* Write protection of Sector16 */ 
-#define OB_WRP1_PAGES272TO287 ((uint32_t)0x00020000) /* Write protection of Sector17 */ 
-#define OB_WRP1_PAGES288TO303 ((uint32_t)0x00040000) /* Write protection of Sector18 */ 
-#define OB_WRP1_PAGES304TO319 ((uint32_t)0x00080000) /* Write protection of Sector19 */ 
-#define OB_WRP1_PAGES320TO335 ((uint32_t)0x00100000) /* Write protection of Sector20 */ 
-#define OB_WRP1_PAGES336TO351 ((uint32_t)0x00200000) /* Write protection of Sector21 */ 
-#define OB_WRP1_PAGES352TO367 ((uint32_t)0x00400000) /* Write protection of Sector22 */ 
-#define OB_WRP1_PAGES368TO383 ((uint32_t)0x00800000) /* Write protection of Sector23 */ 
-#define OB_WRP1_PAGES384TO399 ((uint32_t)0x01000000) /* Write protection of Sector24 */ 
-#define OB_WRP1_PAGES400TO415 ((uint32_t)0x02000000) /* Write protection of Sector25 */ 
-#define OB_WRP1_PAGES416TO431 ((uint32_t)0x04000000) /* Write protection of Sector26 */ 
-#define OB_WRP1_PAGES432TO447 ((uint32_t)0x08000000) /* Write protection of Sector27 */ 
-#define OB_WRP1_PAGES448TO463 ((uint32_t)0x10000000) /* Write protection of Sector28 */ 
-#define OB_WRP1_PAGES464TO479 ((uint32_t)0x20000000) /* Write protection of Sector29 */ 
-#define OB_WRP1_PAGES480TO495 ((uint32_t)0x40000000) /* Write protection of Sector30 */ 
-#define OB_WRP1_PAGES496TO511 ((uint32_t)0x80000000) /* Write protection of Sector31 */ 
-  
-#define OB_WRP1_ALLPAGES      ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-  
-/**
-  * @}
-  */ 
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection2 FLASHEx Option Bytes Write Protection2
-  * @{
-  */
-  
-/* Pages for Cat3, Cat4 & Cat5 devices*/
-#define OB_WRP2_PAGES512TO527   ((uint32_t)0x00000001) /* Write protection of Sector32 */  
-#define OB_WRP2_PAGES528TO543   ((uint32_t)0x00000002) /* Write protection of Sector33 */  
-#define OB_WRP2_PAGES544TO559   ((uint32_t)0x00000004) /* Write protection of Sector34 */  
-#define OB_WRP2_PAGES560TO575   ((uint32_t)0x00000008) /* Write protection of Sector35 */  
-#define OB_WRP2_PAGES576TO591   ((uint32_t)0x00000010) /* Write protection of Sector36 */  
-#define OB_WRP2_PAGES592TO607   ((uint32_t)0x00000020) /* Write protection of Sector37 */  
-#define OB_WRP2_PAGES608TO623   ((uint32_t)0x00000040) /* Write protection of Sector38 */  
-#define OB_WRP2_PAGES624TO639   ((uint32_t)0x00000080) /* Write protection of Sector39 */  
-#define OB_WRP2_PAGES640TO655   ((uint32_t)0x00000100) /* Write protection of Sector40 */  
-#define OB_WRP2_PAGES656TO671   ((uint32_t)0x00000200) /* Write protection of Sector41 */  
-#define OB_WRP2_PAGES672TO687   ((uint32_t)0x00000400) /* Write protection of Sector42 */  
-#define OB_WRP2_PAGES688TO703   ((uint32_t)0x00000800) /* Write protection of Sector43 */  
-#define OB_WRP2_PAGES704TO719   ((uint32_t)0x00001000) /* Write protection of Sector44 */  
-#define OB_WRP2_PAGES720TO735   ((uint32_t)0x00002000) /* Write protection of Sector45 */  
-#define OB_WRP2_PAGES736TO751   ((uint32_t)0x00004000) /* Write protection of Sector46 */  
-#define OB_WRP2_PAGES752TO767   ((uint32_t)0x00008000) /* Write protection of Sector47 */  
-#define OB_WRP2_PAGES768TO783   ((uint32_t)0x00010000) /* Write protection of Sector48 */  
-#define OB_WRP2_PAGES784TO799   ((uint32_t)0x00020000) /* Write protection of Sector49 */  
-#define OB_WRP2_PAGES800TO815   ((uint32_t)0x00040000) /* Write protection of Sector50 */  
-#define OB_WRP2_PAGES816TO831   ((uint32_t)0x00080000) /* Write protection of Sector51 */  
-#define OB_WRP2_PAGES832TO847   ((uint32_t)0x00100000) /* Write protection of Sector52 */  
-#define OB_WRP2_PAGES848TO863   ((uint32_t)0x00200000) /* Write protection of Sector53 */  
-#define OB_WRP2_PAGES864TO879   ((uint32_t)0x00400000) /* Write protection of Sector54 */  
-#define OB_WRP2_PAGES880TO895   ((uint32_t)0x00800000) /* Write protection of Sector55 */  
-#define OB_WRP2_PAGES896TO911   ((uint32_t)0x01000000) /* Write protection of Sector56 */  
-#define OB_WRP2_PAGES912TO927   ((uint32_t)0x02000000) /* Write protection of Sector57 */  
-#define OB_WRP2_PAGES928TO943   ((uint32_t)0x04000000) /* Write protection of Sector58 */  
-#define OB_WRP2_PAGES944TO959   ((uint32_t)0x08000000) /* Write protection of Sector59 */  
-#define OB_WRP2_PAGES960TO975   ((uint32_t)0x10000000) /* Write protection of Sector60 */  
-#define OB_WRP2_PAGES976TO991   ((uint32_t)0x20000000) /* Write protection of Sector61 */  
-#define OB_WRP2_PAGES992TO1007  ((uint32_t)0x40000000) /* Write protection of Sector62 */
-#define OB_WRP2_PAGES1008TO1023 ((uint32_t)0x80000000) /* Write protection of Sector63 */
-
-#define OB_WRP2_ALLPAGES        ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection3 FLASHEx Option Bytes Write Protection3
-  * @{
-  */
-  
-/* Pages for devices with FLASH >= 256KB*/
-#define OB_WRP3_PAGES1024TO1039 ((uint32_t)0x00000001) /* Write protection of Sector64 */
-#define OB_WRP3_PAGES1040TO1055 ((uint32_t)0x00000002) /* Write protection of Sector65 */
-#define OB_WRP3_PAGES1056TO1071 ((uint32_t)0x00000004) /* Write protection of Sector66 */
-#define OB_WRP3_PAGES1072TO1087 ((uint32_t)0x00000008) /* Write protection of Sector67 */
-#define OB_WRP3_PAGES1088TO1103 ((uint32_t)0x00000010) /* Write protection of Sector68 */
-#define OB_WRP3_PAGES1104TO1119 ((uint32_t)0x00000020) /* Write protection of Sector69 */
-#define OB_WRP3_PAGES1120TO1135 ((uint32_t)0x00000040) /* Write protection of Sector70 */
-#define OB_WRP3_PAGES1136TO1151 ((uint32_t)0x00000080) /* Write protection of Sector71 */
-#define OB_WRP3_PAGES1152TO1167 ((uint32_t)0x00000100) /* Write protection of Sector72 */
-#define OB_WRP3_PAGES1168TO1183 ((uint32_t)0x00000200) /* Write protection of Sector73 */
-#define OB_WRP3_PAGES1184TO1199 ((uint32_t)0x00000400) /* Write protection of Sector74 */
-#define OB_WRP3_PAGES1200TO1215 ((uint32_t)0x00000800) /* Write protection of Sector75 */
-#define OB_WRP3_PAGES1216TO1231 ((uint32_t)0x00001000) /* Write protection of Sector76 */
-#define OB_WRP3_PAGES1232TO1247 ((uint32_t)0x00002000) /* Write protection of Sector77 */
-#define OB_WRP3_PAGES1248TO1263 ((uint32_t)0x00004000) /* Write protection of Sector78 */
-#define OB_WRP3_PAGES1264TO1279 ((uint32_t)0x00008000) /* Write protection of Sector79 */
-#define OB_WRP3_PAGES1280TO1295 ((uint32_t)0x00010000) /* Write protection of Sector80 */
-#define OB_WRP3_PAGES1296TO1311 ((uint32_t)0x00020000) /* Write protection of Sector81 */
-#define OB_WRP3_PAGES1312TO1327 ((uint32_t)0x00040000) /* Write protection of Sector82 */
-#define OB_WRP3_PAGES1328TO1343 ((uint32_t)0x00080000) /* Write protection of Sector83 */
-#define OB_WRP3_PAGES1344TO1359 ((uint32_t)0x00100000) /* Write protection of Sector84 */
-#define OB_WRP3_PAGES1360TO1375 ((uint32_t)0x00200000) /* Write protection of Sector85 */
-#define OB_WRP3_PAGES1376TO1391 ((uint32_t)0x00400000) /* Write protection of Sector86 */
-#define OB_WRP3_PAGES1392TO1407 ((uint32_t)0x00800000) /* Write protection of Sector87 */
-#define OB_WRP3_PAGES1408TO1423 ((uint32_t)0x01000000) /* Write protection of Sector88 */
-#define OB_WRP3_PAGES1424TO1439 ((uint32_t)0x02000000) /* Write protection of Sector89 */
-#define OB_WRP3_PAGES1440TO1455 ((uint32_t)0x04000000) /* Write protection of Sector90 */
-#define OB_WRP3_PAGES1456TO1471 ((uint32_t)0x08000000) /* Write protection of Sector91 */
-#define OB_WRP3_PAGES1472TO1487 ((uint32_t)0x10000000) /* Write protection of Sector92 */
-#define OB_WRP3_PAGES1488TO1503 ((uint32_t)0x20000000) /* Write protection of Sector93 */
-#define OB_WRP3_PAGES1504TO1519 ((uint32_t)0x40000000) /* Write protection of Sector94 */
-#define OB_WRP3_PAGES1520TO1535 ((uint32_t)0x80000000) /* Write protection of Sector95 */
-
-#define OB_WRP3_ALLPAGES        ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
-
-#if defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-/** @defgroup FLASHEx_Option_Bytes_Write_Protection4 FLASHEx Option Bytes Write Protection4
-  * @{
-  */
-  
-/* Pages for Cat5 devices*/
-#define OB_WRP4_PAGES1536TO1551 ((uint32_t)0x00000001)/* Write protection of Sector96*/   
-#define OB_WRP4_PAGES1552TO1567 ((uint32_t)0x00000002)/* Write protection of Sector97*/   
-#define OB_WRP4_PAGES1568TO1583 ((uint32_t)0x00000004)/* Write protection of Sector98*/   
-#define OB_WRP4_PAGES1584TO1599 ((uint32_t)0x00000008)/* Write protection of Sector99*/   
-#define OB_WRP4_PAGES1600TO1615 ((uint32_t)0x00000010) /* Write protection of Sector100*/ 
-#define OB_WRP4_PAGES1616TO1631 ((uint32_t)0x00000020) /* Write protection of Sector101*/ 
-#define OB_WRP4_PAGES1632TO1647 ((uint32_t)0x00000040) /* Write protection of Sector102*/ 
-#define OB_WRP4_PAGES1648TO1663 ((uint32_t)0x00000080) /* Write protection of Sector103*/ 
-#define OB_WRP4_PAGES1664TO1679 ((uint32_t)0x00000100) /* Write protection of Sector104*/ 
-#define OB_WRP4_PAGES1680TO1695 ((uint32_t)0x00000200) /* Write protection of Sector105*/ 
-#define OB_WRP4_PAGES1696TO1711 ((uint32_t)0x00000400) /* Write protection of Sector106*/ 
-#define OB_WRP4_PAGES1712TO1727 ((uint32_t)0x00000800) /* Write protection of Sector107*/ 
-#define OB_WRP4_PAGES1728TO1743 ((uint32_t)0x00001000) /* Write protection of Sector108*/ 
-#define OB_WRP4_PAGES1744TO1759 ((uint32_t)0x00002000) /* Write protection of Sector109*/ 
-#define OB_WRP4_PAGES1760TO1775 ((uint32_t)0x00004000) /* Write protection of Sector110*/ 
-#define OB_WRP4_PAGES1776TO1791 ((uint32_t)0x00008000) /* Write protection of Sector111*/ 
-#define OB_WRP4_PAGES1792TO1807 ((uint32_t)0x00010000) /* Write protection of Sector112*/ 
-#define OB_WRP4_PAGES1808TO1823 ((uint32_t)0x00020000) /* Write protection of Sector113*/ 
-#define OB_WRP4_PAGES1824TO1839 ((uint32_t)0x00040000) /* Write protection of Sector114*/ 
-#define OB_WRP4_PAGES1840TO1855 ((uint32_t)0x00080000) /* Write protection of Sector115*/ 
-#define OB_WRP4_PAGES1856TO1871 ((uint32_t)0x00100000) /* Write protection of Sector116*/ 
-#define OB_WRP4_PAGES1872TO1887 ((uint32_t)0x00200000) /* Write protection of Sector117*/ 
-#define OB_WRP4_PAGES1888TO1903 ((uint32_t)0x00400000) /* Write protection of Sector118*/ 
-#define OB_WRP4_PAGES1904TO1919 ((uint32_t)0x00800000) /* Write protection of Sector119*/ 
-#define OB_WRP4_PAGES1920TO1935 ((uint32_t)0x01000000) /* Write protection of Sector120*/ 
-#define OB_WRP4_PAGES1936TO1951 ((uint32_t)0x02000000) /* Write protection of Sector121*/ 
-#define OB_WRP4_PAGES1952TO1967 ((uint32_t)0x04000000) /* Write protection of Sector122*/ 
-#define OB_WRP4_PAGES1968TO1983 ((uint32_t)0x08000000) /* Write protection of Sector123*/ 
-#define OB_WRP4_PAGES1984TO1999 ((uint32_t)0x10000000) /* Write protection of Sector124*/ 
-#define OB_WRP4_PAGES2000TO2015 ((uint32_t)0x20000000) /* Write protection of Sector125*/ 
-#define OB_WRP4_PAGES2016TO2031 ((uint32_t)0x40000000) /* Write protection of Sector126*/ 
-#define OB_WRP4_PAGES2032TO2047 ((uint32_t)0x80000000) /* Write protection of Sector127*/ 
-
-#define OB_WRP4_ALLPAGES        ((uint32_t)0xFFFFFFFF) /*!< Write protection of all Sectors */
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xE || STM32L152xE || STM32L162xE */
-
-/** @defgroup FLASHEx_Option_Bytes_Read_Protection FLASHEx Option Bytes Read Protection
-  * @{
-  */ 
-#define OB_RDP_LEVEL0         ((uint8_t)0xAA)
-#define OB_RDP_LEVEL1         ((uint8_t)0xBB)
-/*#define OB_RDP_LEVEL2   ((uint8_t)0xCC)*/ /* Warning: When enabling read protection level 2 
-                                                it's no more possible to go back to level 1 or 0 */
-
-#define IS_OB_RDP(__LEVEL__)  (((__LEVEL__) == OB_RDP_LEVEL0)||\
-                               ((__LEVEL__) == OB_RDP_LEVEL1))/*||\
-                          ((__LEVEL__) == OB_RDP_LEVEL2))*/
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Option_Bytes_BOR_Level FLASHEx Option Bytes BOR Level
-  * @{
-  */
-
-#define OB_BOR_OFF       ((uint8_t)0x00) /*!< BOR is disabled at power down, the reset is asserted when the VDD 
-                                              power supply reaches the PDR(Power Down Reset) threshold (1.5V) */
-#define OB_BOR_LEVEL1    ((uint8_t)0x08) /*!< BOR Reset threshold levels for 1.7V - 1.8V VDD power supply    */
-#define OB_BOR_LEVEL2    ((uint8_t)0x09) /*!< BOR Reset threshold levels for 1.9V - 2.0V VDD power supply    */
-#define OB_BOR_LEVEL3    ((uint8_t)0x0A) /*!< BOR Reset threshold levels for 2.3V - 2.4V VDD power supply    */
-#define OB_BOR_LEVEL4    ((uint8_t)0x0B) /*!< BOR Reset threshold levels for 2.55V - 2.65V VDD power supply  */
-#define OB_BOR_LEVEL5    ((uint8_t)0x0C) /*!< BOR Reset threshold levels for 2.8V - 2.9V VDD power supply    */
-
-#define IS_OB_BOR_LEVEL(__LEVEL__)  ( ((__LEVEL__) == OB_BOR_OFF)     || \
-                                      ((__LEVEL__) == OB_BOR_LEVEL1)  || \
-                                      ((__LEVEL__) == OB_BOR_LEVEL2)  || \
-                                      ((__LEVEL__) == OB_BOR_LEVEL3)  || \
-                                      ((__LEVEL__) == OB_BOR_LEVEL4)  || \
-                                      ((__LEVEL__) == OB_BOR_LEVEL5))
-
-/**
-  * @}
-  */
-  
-/** @defgroup FLASHEx_Option_Bytes_IWatchdog FLASHEx Option Bytes IWatchdog
-  * @{
-  */
-
-#define OB_IWDG_SW                     ((uint8_t)0x10)  /*!< Software WDG selected */
-#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware WDG selected */
-
-#define IS_OB_IWDG_SOURCE(__SOURCE__) (((__SOURCE__) == OB_IWDG_SW) || ((__SOURCE__) == OB_IWDG_HW))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STOP FLASHEx Option Bytes nRST_STOP
-  * @{
-  */
-
-#define OB_STOP_NORST                  ((uint8_t)0x20) /*!< No reset generated when entering in STOP */
-#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
-#define IS_OB_STOP_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STOP_NORST) || ((__SOURCE__) == OB_STOP_RST))
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_nRST_STDBY FLASHEx Option Bytes nRST_STDBY
-  * @{
-  */
-
-#define OB_STDBY_NORST                 ((uint8_t)0x40) /*!< No reset generated when entering in STANDBY */
-#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
-#define IS_OB_STDBY_SOURCE(__SOURCE__) (((__SOURCE__) == OB_STDBY_NORST) || ((__SOURCE__) == OB_STDBY_RST))
-
-/**
-  * @}
-  */
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-    
-/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
-  * @{
-  */ 
-  
-#define OBEX_PCROP        ((uint32_t)0x01)  /*!<PCROP option byte configuration*/
-
-#define IS_OBEX(__VALUE__)        ((__VALUE__) == OBEX_PCROP)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-/** @defgroup FLASHEx_OptionAdv_Type FLASHEx Option Advanced Type
-  * @{
-  */ 
-  
-#define OBEX_BOOTCONFIG   ((uint32_t)0x02)  /*!<BOOTConfig option byte configuration*/
-
-#define IS_OBEX(__VALUE__)        ((__VALUE__) == OBEX_BOOTCONFIG)
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-
-/** @defgroup  FLASHEx_PCROP_State FLASHEx PCROP State
-  * @{
-  */
-#define PCROPSTATE_DISABLE        ((uint32_t)0x00)  /*!<Disable PCROP for selected sectors */
-#define PCROPSTATE_ENABLE         ((uint32_t)0x01)  /*!<Enable PCROP for selected sectors */
-    
-#define IS_PCROPSTATE(__VALUE__)  (((__VALUE__) == PCROPSTATE_DISABLE) || \
-                                   ((__VALUE__) == PCROPSTATE_ENABLE))  
-/**
-  * @}
-  */
-
-/** @defgroup  FLASHEx_Selection_Protection_Mode FLASHEx Selection Protection Mode
-  * @{
-  */
-#define OB_PCROP_DESELECTED     ((uint16_t)0x0000)            /*!< Disabled PCROP, nWPRi bits used for Write Protection on sector i */
-#define OB_PCROP_SELECTED       ((uint16_t)FLASH_OBR_SPRMOD)  /*!< Enable PCROP, nWPRi bits used for PCRoP Protection on sector i   */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection1 FLASHEx Option Bytes PC ReadWrite Protection 1
-  * @{
-  */
-  
-/* Common pages for Cat1, Cat2, Cat3, Cat4 & Cat5 devices */
-#define OB_PCROP1_PAGES0TO15    ((uint32_t)0x00000001) /* PC Read/Write  protection of Sector0 */  
-#define OB_PCROP1_PAGES16TO31   ((uint32_t)0x00000002) /* PC Read/Write  protection of Sector1 */  
-#define OB_PCROP1_PAGES32TO47   ((uint32_t)0x00000004) /* PC Read/Write  protection of Sector2 */  
-#define OB_PCROP1_PAGES48TO63   ((uint32_t)0x00000008) /* PC Read/Write  protection of Sector3 */  
-#define OB_PCROP1_PAGES64TO79   ((uint32_t)0x00000010) /* PC Read/Write  protection of Sector4 */  
-#define OB_PCROP1_PAGES80TO95   ((uint32_t)0x00000020) /* PC Read/Write  protection of Sector5 */  
-#define OB_PCROP1_PAGES96TO111  ((uint32_t)0x00000040) /* PC Read/Write  protection of Sector6 */  
-#define OB_PCROP1_PAGES112TO127 ((uint32_t)0x00000080) /* PC Read/Write  protection of Sector7 */  
-#define OB_PCROP1_PAGES128TO143 ((uint32_t)0x00000100) /* PC Read/Write  protection of Sector8 */  
-#define OB_PCROP1_PAGES144TO159 ((uint32_t)0x00000200) /* PC Read/Write  protection of Sector9 */  
-#define OB_PCROP1_PAGES160TO175 ((uint32_t)0x00000400) /* PC Read/Write  protection of Sector10 */ 
-#define OB_PCROP1_PAGES176TO191 ((uint32_t)0x00000800) /* PC Read/Write  protection of Sector11 */ 
-#define OB_PCROP1_PAGES192TO207 ((uint32_t)0x00001000) /* PC Read/Write  protection of Sector12 */ 
-#define OB_PCROP1_PAGES208TO223 ((uint32_t)0x00002000) /* PC Read/Write  protection of Sector13 */ 
-#define OB_PCROP1_PAGES224TO239 ((uint32_t)0x00004000) /* PC Read/Write  protection of Sector14 */ 
-#define OB_PCROP1_PAGES240TO255 ((uint32_t)0x00008000) /* PC Read/Write  protection of Sector15 */ 
-#define OB_PCROP1_PAGES256TO271 ((uint32_t)0x00010000) /* PC Read/Write  protection of Sector16 */ 
-#define OB_PCROP1_PAGES272TO287 ((uint32_t)0x00020000) /* PC Read/Write  protection of Sector17 */ 
-#define OB_PCROP1_PAGES288TO303 ((uint32_t)0x00040000) /* PC Read/Write  protection of Sector18 */ 
-#define OB_PCROP1_PAGES304TO319 ((uint32_t)0x00080000) /* PC Read/Write  protection of Sector19 */ 
-#define OB_PCROP1_PAGES320TO335 ((uint32_t)0x00100000) /* PC Read/Write  protection of Sector20 */ 
-#define OB_PCROP1_PAGES336TO351 ((uint32_t)0x00200000) /* PC Read/Write  protection of Sector21 */ 
-#define OB_PCROP1_PAGES352TO367 ((uint32_t)0x00400000) /* PC Read/Write  protection of Sector22 */ 
-#define OB_PCROP1_PAGES368TO383 ((uint32_t)0x00800000) /* PC Read/Write  protection of Sector23 */ 
-#define OB_PCROP1_PAGES384TO399 ((uint32_t)0x01000000) /* PC Read/Write  protection of Sector24 */ 
-#define OB_PCROP1_PAGES400TO415 ((uint32_t)0x02000000) /* PC Read/Write  protection of Sector25 */ 
-#define OB_PCROP1_PAGES416TO431 ((uint32_t)0x04000000) /* PC Read/Write  protection of Sector26 */ 
-#define OB_PCROP1_PAGES432TO447 ((uint32_t)0x08000000) /* PC Read/Write  protection of Sector27 */ 
-#define OB_PCROP1_PAGES448TO463 ((uint32_t)0x10000000) /* PC Read/Write  protection of Sector28 */ 
-#define OB_PCROP1_PAGES464TO479 ((uint32_t)0x20000000) /* PC Read/Write  protection of Sector29 */ 
-#define OB_PCROP1_PAGES480TO495 ((uint32_t)0x40000000) /* PC Read/Write  protection of Sector30 */ 
-#define OB_PCROP1_PAGES496TO511 ((uint32_t)0x80000000) /* PC Read/Write  protection of Sector31 */ 
-  
-#define OB_PCROP1_ALLPAGES      ((uint32_t)0xFFFFFFFF) /*!< PC Read/Write  protection of all Sectors */
-  
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-
-/** @defgroup FLASHEx_Option_Bytes_PC_ReadWrite_Protection2 FLASHEx Option Bytes PC ReadWrite Protection 2
-  * @{
-  */
-  
-/* Pages for Cat3, Cat4 & Cat5 devices*/
-#define OB_PCROP2_PAGES512TO527   ((uint32_t)0x00000001) /* PC Read/Write  protection of Sector32 */  
-#define OB_PCROP2_PAGES528TO543   ((uint32_t)0x00000002) /* PC Read/Write  protection of Sector33 */  
-#define OB_PCROP2_PAGES544TO559   ((uint32_t)0x00000004) /* PC Read/Write  protection of Sector34 */  
-#define OB_PCROP2_PAGES560TO575   ((uint32_t)0x00000008) /* PC Read/Write  protection of Sector35 */  
-#define OB_PCROP2_PAGES576TO591   ((uint32_t)0x00000010) /* PC Read/Write  protection of Sector36 */  
-#define OB_PCROP2_PAGES592TO607   ((uint32_t)0x00000020) /* PC Read/Write  protection of Sector37 */  
-#define OB_PCROP2_PAGES608TO623   ((uint32_t)0x00000040) /* PC Read/Write  protection of Sector38 */  
-#define OB_PCROP2_PAGES624TO639   ((uint32_t)0x00000080) /* PC Read/Write  protection of Sector39 */  
-#define OB_PCROP2_PAGES640TO655   ((uint32_t)0x00000100) /* PC Read/Write  protection of Sector40 */  
-#define OB_PCROP2_PAGES656TO671   ((uint32_t)0x00000200) /* PC Read/Write  protection of Sector41 */  
-#define OB_PCROP2_PAGES672TO687   ((uint32_t)0x00000400) /* PC Read/Write  protection of Sector42 */  
-#define OB_PCROP2_PAGES688TO703   ((uint32_t)0x00000800) /* PC Read/Write  protection of Sector43 */  
-#define OB_PCROP2_PAGES704TO719   ((uint32_t)0x00001000) /* PC Read/Write  protection of Sector44 */  
-#define OB_PCROP2_PAGES720TO735   ((uint32_t)0x00002000) /* PC Read/Write  protection of Sector45 */  
-#define OB_PCROP2_PAGES736TO751   ((uint32_t)0x00004000) /* PC Read/Write  protection of Sector46 */  
-#define OB_PCROP2_PAGES752TO767   ((uint32_t)0x00008000) /* PC Read/Write  protection of Sector47 */  
-#define OB_PCROP2_PAGES768TO783   ((uint32_t)0x00010000) /* PC Read/Write  protection of Sector48 */  
-#define OB_PCROP2_PAGES784TO799   ((uint32_t)0x00020000) /* PC Read/Write  protection of Sector49 */  
-#define OB_PCROP2_PAGES800TO815   ((uint32_t)0x00040000) /* PC Read/Write  protection of Sector50 */  
-#define OB_PCROP2_PAGES816TO831   ((uint32_t)0x00080000) /* PC Read/Write  protection of Sector51 */  
-#define OB_PCROP2_PAGES832TO847   ((uint32_t)0x00100000) /* PC Read/Write  protection of Sector52 */  
-#define OB_PCROP2_PAGES848TO863   ((uint32_t)0x00200000) /* PC Read/Write  protection of Sector53 */  
-#define OB_PCROP2_PAGES864TO879   ((uint32_t)0x00400000) /* PC Read/Write  protection of Sector54 */  
-#define OB_PCROP2_PAGES880TO895   ((uint32_t)0x00800000) /* PC Read/Write  protection of Sector55 */  
-#define OB_PCROP2_PAGES896TO911   ((uint32_t)0x01000000) /* PC Read/Write  protection of Sector56 */  
-#define OB_PCROP2_PAGES912TO927   ((uint32_t)0x02000000) /* PC Read/Write  protection of Sector57 */  
-#define OB_PCROP2_PAGES928TO943   ((uint32_t)0x04000000) /* PC Read/Write  protection of Sector58 */  
-#define OB_PCROP2_PAGES944TO959   ((uint32_t)0x08000000) /* PC Read/Write  protection of Sector59 */  
-#define OB_PCROP2_PAGES960TO975   ((uint32_t)0x10000000) /* PC Read/Write  protection of Sector60 */  
-#define OB_PCROP2_PAGES976TO991   ((uint32_t)0x20000000) /* PC Read/Write  protection of Sector61 */  
-#define OB_PCROP2_PAGES992TO1007  ((uint32_t)0x40000000) /* PC Read/Write  protection of Sector62 */
-#define OB_PCROP2_PAGES1008TO1023 ((uint32_t)0x80000000) /* PC Read/Write  protection of Sector63 */
-
-#define OB_PCROP2_ALLPAGES        ((uint32_t)0xFFFFFFFF) /*!< PC Read/Write  protection of all Sectors */
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
-
-/** @defgroup FLASHEx_Type_Erase_Data FLASHEx Type Erase Data
-  * @{
-  */
-#define TYPEERASEDATA_BYTE            ((uint32_t)0x00)  /*!<Erase byte (8-bit) at a specified address.*/
-#define TYPEERASEDATA_HALFWORD        ((uint32_t)0x01)  /*!<Erase a half-word (16-bit) at a specified address.*/
-#define TYPEERASEDATA_WORD            ((uint32_t)0x02)  /*!<Erase a word (32-bit) at a specified address.*/
-
-#define IS_TYPEERASEDATA(__VALUE__)   (((__VALUE__) == TYPEERASEDATA_BYTE) || \
-                                       ((__VALUE__) == TYPEERASEDATA_HALFWORD) || \
-                                       ((__VALUE__) == TYPEERASEDATA_WORD))
-/**
-  * @}
-  */
-
-/** @defgroup FLASHEx_Type_Program_Data FLASHEx Type Program Data
-  * @{
-  */
-#define TYPEPROGRAMDATA_BYTE            ((uint32_t)0x00)  /*!<Program byte (8-bit) at a specified address.*/
-#define TYPEPROGRAMDATA_HALFWORD        ((uint32_t)0x01)  /*!<Program a half-word (16-bit) at a specified address.*/
-#define TYPEPROGRAMDATA_WORD            ((uint32_t)0x02)  /*!<Program a word (32-bit) at a specified address.*/
-#define TYPEPROGRAMDATA_FASTBYTE        ((uint32_t)0x04)  /*!<Fast Program byte (8-bit) at a specified address.*/
-#define TYPEPROGRAMDATA_FASTHALFWORD    ((uint32_t)0x08)  /*!<Fast Program a half-word (16-bit) at a specified address.*/
-#define TYPEPROGRAMDATA_FASTWORD        ((uint32_t)0x10)  /*!<Fast Program a word (32-bit) at a specified address.*/
-
-#define IS_TYPEPROGRAMDATA(__VALUE__)   (((__VALUE__) == TYPEPROGRAMDATA_BYTE) || \
-                                         ((__VALUE__) == TYPEPROGRAMDATA_HALFWORD) || \
-                                         ((__VALUE__) == TYPEPROGRAMDATA_WORD) || \
-                                         ((__VALUE__) == TYPEPROGRAMDATA_FASTBYTE) || \
-                                         ((__VALUE__) == TYPEPROGRAMDATA_FASTHALFWORD) || \
-                                         ((__VALUE__) == TYPEPROGRAMDATA_FASTWORD))
-/**
-  * @}
-  */
-
-
-/** @defgroup FLASHEx_Address FLASHEx Address
-  * @{
-  */
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || \
-   defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA)
-     
-/******* Devices with FLASH 128K *******/
-#define FLASH_NBPAGES_MAX       512 /* 512 pages from page 0 to page 511 */
-
-#elif defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined (STM32L151xCA) || defined (STM32L152xCA) || defined (STM32L162xCA)
-
-/******* Devices with FLASH 256K *******/
-#define FLASH_NBPAGES_MAX       1025 /* 1025 pages from page 0 to page 1024 */
-
-#elif defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/******* Devices with FLASH 384K *******/
-#define FLASH_NBPAGES_MAX       1536 /* 1536 pages from page 0 to page 1535 */
-
-#elif defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-/******* Devices with FLASH 512K *******/
-#define FLASH_NBPAGES_MAX       2048 /* 2048 pages from page 0 to page 2047 */
-
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA */
-
-#define IS_FLASH_DATA_ADDRESS(__ADDRESS__)          (((__ADDRESS__) >= FLASH_EEPROM_BASE) && ((__ADDRESS__) <= FLASH_EEPROM_END))
-
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || \
-    defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined (STM32L151xCA) || defined (STM32L152xCA) || defined (STM32L162xCA)
-
-#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)       (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_END))  
-
-#else /*STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#define IS_FLASH_PROGRAM_ADDRESS(__ADDRESS__)       (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))  
-#define IS_FLASH_PROGRAM_BANK1_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BASE) && ((__ADDRESS__) <= FLASH_BANK1_END))  
-#define IS_FLASH_PROGRAM_BANK2_ADDRESS(__ADDRESS__) (((__ADDRESS__) >= FLASH_BANK2_BASE) && ((__ADDRESS__) <= FLASH_BANK2_END))  
-
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA || STM32L151xBA || STM32L152xBA  || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L152xCA || STM32L162xCA */
-
-#define IS_NBPAGES(_PAGES_) (((_PAGES_) >= 1) && ((_PAGES_) <= FLASH_NBPAGES_MAX)) 
-
-/**
-  * @}
-  */ 
-
-/** @defgroup FLASHEx_Flags FLASHEx Flags
-  * @{
-  */ 
-
-/* Cat2 & Cat3*/
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-    
-#define FLASH_FLAG_RDERR               FLASH_SR_RDERR    /*!< Read protected error flag  */
-
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-/* Cat3, Cat4 & Cat5*/
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-#define FLASH_FLAG_OPTVERRUSR          FLASH_SR_OPTVERRUSR /*!< FLASH Option User Validity error flag  */
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/* Cat1*/
-#if defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB) || defined (STM32L100xBA)
-
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR)
-
-#endif /* STM32L100xB || STM32L151xB || STM32L152xB || STM32L100xBA */
-
-/* RDERR only for STM32L151xBA & STM32L152xBA (Cat2)*/
-#if defined (STM32L151xBA) || defined (STM32L152xBA)
-
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
-                                  FLASH_FLAG_RDERR)
-
-#endif /* STM32L151xBA || STM32L152xBA */
-
-/* FLASH_FLAG_OPTVERRUSR & RDERR only for STM32L151xC, STM32L152xC & STM32L152xBA (Cat3) */
-#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
-                                  FLASH_FLAG_OPTVERRUSR | FLASH_FLAG_RDERR)
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC */
-
-/* FLASH_FLAG_OPTVERRUSR only for STM32L100xC (Cat3) */
-#if defined (STM32L100xC)
-
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
-                                  FLASH_FLAG_OPTVERRUSR)
-
-#endif /* STM32L100xC */
-
-/* Cat4 & Cat5 */
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-#define FLASH_FLAG_MASK         ( FLASH_FLAG_EOP        | FLASH_FLAG_ENDHV  | FLASH_FLAG_WRPERR | \
-                                  FLASH_FLAG_OPTVERR    | FLASH_FLAG_PGAERR | FLASH_FLAG_SIZERR | \
-                                  FLASH_FLAG_OPTVERRUSR)
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @}
-  */
-  
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-/** @defgroup FLASHEx_Option_Bytes_BOOT FLASHEx Option Bytes BOOT
-  * @{
-  */
-
-#define OB_BOOT_BANK2                 ((uint8_t)0x00) /*!< At startup, if boot pins are set in boot from user Flash position
-                                                            and this parameter is selected the device will boot from Bank 2 
-                                                            or Bank 1, depending on the activation of the bank */
-#define OB_BOOT_BANK1                 ((uint8_t)(FLASH_OBR_nRST_BFB2 >> 16)) /*!< At startup, if boot pins are set in boot from user Flash position
-                                                            and this parameter is selected the device will boot from Bank1(Default) */
-#define IS_OB_BOOT_BANK(__BANK__)     (((__BANK__) == OB_BOOT_BANK2) || ((__BANK__) == OB_BOOT_BANK1))
-
-/**
-  * @}
-  */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FLASHEx_Exported_Macros FLASHEx Exported Macros
- *  @{
- */
- 
-/**
-  * @brief  Set the FLASH Latency.
-  * @param  __LATENCY__: FLASH Latency
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_LATENCY_0:  FLASH Zero Latency cycle
-  *            @arg FLASH_LATENCY_1:  FLASH One Latency cycle
-  * @retval none
-  */ 
-#define __HAL_FLASH_SET_LATENCY(__LATENCY__)  do  { \
-                                                  if ((__LATENCY__) == FLASH_LATENCY_1) {__HAL_FLASH_ACC64_ENABLE();} \
-                                                  MODIFY_REG((FLASH->ACR), FLASH_ACR_LATENCY, (__LATENCY__)); \
-                                              } while(0)
-
-/**
-  * @brief  Get the FLASH Latency.
-  * @retval FLASH Latency                   
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_LATENCY_0:  FLASH Zero Latency cycle
-  *            @arg FLASH_LATENCY_1:  FLASH One Latency cycle
-  */ 
-#define __HAL_FLASH_GET_LATENCY()     (READ_BIT((FLASH->ACR), FLASH_ACR_LATENCY))
-
-  /**
-  * @brief  Enable the FLASH 64-bit access.
-  * @note    Read access 64 bit is used.
-  * @note    This bit cannot be written at the same time as the LATENCY and 
-  *          PRFTEN bits.
-  * @retval none
-  */ 
-#define __HAL_FLASH_ACC64_ENABLE()    (SET_BIT((FLASH->ACR), FLASH_ACR_ACC64))
-
-  /**
-  * @brief  Disable the FLASH 64-bit access.
-  * @note     Read access 32 bit is used
-  * @note     To reset this bit, the LATENCY should be zero wait state and the 
-  *               prefetch off.
-  * @retval none
-  */ 
-#define __HAL_FLASH_ACC64_DISABLE()   (CLEAR_BIT((FLASH->ACR), FLASH_ACR_ACC64))
-
-  /**
-  * @brief  Enable the FLASH prefetch buffer.
-  * @retval none
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_ENABLE()    do  { __HAL_FLASH_ACC64_ENABLE(); \
-                                                  SET_BIT((FLASH->ACR), FLASH_ACR_PRFTEN); \
-                                                } while(0)
-
-/**
-  * @brief  Disable the FLASH prefetch buffer.
-  * @retval none
-  */ 
-#define __HAL_FLASH_PREFETCH_BUFFER_DISABLE()     CLEAR_BIT((FLASH->ACR), FLASH_ACR_PRFTEN)
-
-/**
-  * @brief  Enable the FLASH power down during Sleep mode
-  * @retval none
-  */ 
-#define __HAL_FLASH_SLEEP_POWERDOWN_ENABLE()      SET_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
-  * @brief  Disable the FLASH power down during Sleep mode
-  * @retval none
-  */ 
-#define __HAL_FLASH_SLEEP_POWERDOWN_DISABLE()     CLEAR_BIT(FLASH->ACR, FLASH_ACR_SLEEP_PD)
-
-/**
-  * @brief  Macro to enable or disable the Flash Run power down mode.
-  * @note   Writing this bit  to 0 this bit, automatically the keys are
-  *         loss and a new unlock sequence is necessary to re-write it to 1.
-  */
-
-#define __HAL_FLASH_POWER_DOWN_ENABLE() do { FLASH->PDKEYR = FLASH_PDKEY1;    \
-                                             FLASH->PDKEYR = FLASH_PDKEY2;    \
-                                             SET_BIT((FLASH->ACR), FLASH_ACR_RUN_PD);  \
-                                           } while (0)
-
-#define __HAL_FLASH_POWER_DOWN_DISABLE() do { FLASH->PDKEYR = FLASH_PDKEY1;    \
-                                              FLASH->PDKEYR = FLASH_PDKEY2;    \
-                                             CLEAR_BIT((FLASH->ACR), FLASH_ACR_RUN_PD);  \
-                                            } while (0)
-                                            
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FLASHEx_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_Erase(FLASH_EraseInitTypeDef *pEraseInit, uint32_t *PageError);
-HAL_StatusTypeDef HAL_FLASHEx_Erase_IT(FLASH_EraseInitTypeDef *pEraseInit);
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_OBProgram(FLASH_OBProgramInitTypeDef *pOBInit);
-void              HAL_FLASHEx_OBGetConfig(FLASH_OBProgramInitTypeDef *pOBInit);
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-HAL_StatusTypeDef HAL_FLASHEx_AdvOBProgram (FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-void              HAL_FLASHEx_AdvOBGetConfig(FLASH_AdvOBProgramInitTypeDef *pAdvOBInit);
-
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-
-HAL_StatusTypeDef HAL_FLASHEx_OB_SelectPCROP(void);
-HAL_StatusTypeDef HAL_FLASHEx_OB_DeSelectPCROP(void);
-
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-
-/**
-  * @}
-  */
-
-/** @addtogroup FLASHEx_Exported_Functions_Group3
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Unlock(void);
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Lock(void);
-
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Erase(uint32_t TypeErase, uint32_t Address);
-HAL_StatusTypeDef HAL_FLASHEx_DATAEEPROM_Program(uint32_t TypeProgram, uint32_t Address, uint32_t Data);
-void              HAL_FLASHEx_DATAEEPROM_EnableFixedTimeProgram(void);
-void              HAL_FLASHEx_DATAEEPROM_DisableFixedTimeProgram(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_FLASH_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,545 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash_ramfunc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   FLASH RAMFUNC driver.
-  *          This file provides a Flash firmware functions which should be 
-  *          executed from internal SRAM
-  *
-  *  @verbatim
-
-    *** ARM Compiler ***
-    --------------------
-    [..] RAM functions are defined using the toolchain options. 
-         Functions that are be executed in RAM should reside in a separate
-         source module. Using the 'Options for File' dialog you can simply change
-         the 'Code / Const' area of a module to a memory space in physical RAM.
-         Available memory areas are declared in the 'Target' tab of the 
-         Options for Target' dialog.
-
-    *** ICCARM Compiler ***
-    -----------------------
-    [..] RAM functions are defined using a specific toolchain keyword "__ramfunc".
-
-    *** GNU Compiler ***
-    --------------------
-    [..] RAM functions are defined using a specific toolchain attribute
-         "__attribute__((section(".RamFunc")))".
-
-@endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FLASHRamfunc FLASHRamfunc
-  * @brief FLASH functions executed from RAM
-  * @{
-  */ 
-
-#ifdef HAL_FLASH_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static __RAM_FUNC FLASHRAM_WaitForLastOperation(uint32_t Timeout);
-
-/* Private functions ---------------------------------------------------------*/
- 
-/** @defgroup FLASHRamfunc_Exported_Functions FLASH RAM Exported Functions
- *
-@verbatim  
- ===============================================================================
-                      ##### ramfunc functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions that should be executed from RAM 
-    transfers.
-
-@endverbatim
-  * @{
-  */ 
-
-/** @defgroup FLASHRamfunc_Exported_Functions_Group1 FLASH RAM Peripheral  features functions 
-  * @{
-  */  
-
-/**
-  * @brief  Enable  the power down mode during RUN mode.
-  * @note  This function can be used only when the user code is running from Internal SRAM.
-  * @retval None
-  */
-__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void)
-{
-  /* Enable the Power Down in Run mode*/
-  __HAL_FLASH_POWER_DOWN_ENABLE();
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Disable the power down mode during RUN mode.
-  * @note  This function can be used only when the user code is running from Internal SRAM.
-  * @retval None
-  */
-__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void)
-{
-  /* Disable the Power Down in Run mode*/
-  __HAL_FLASH_POWER_DOWN_DISABLE();
-
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHRamfunc_Exported_Functions_Group2 FLASH RAM Programming and erasing operation functions 
- *
-@verbatim  
-@endverbatim
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
-  * @brief  Erases a specified 2 page in program memory in parallel.
-  * @note   This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5  devices.
-  *         To correctly run this function, the HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_Lock() to disable the flash memory access 
-  *        (recommended to protect the FLASH memory against possible unwanted operation).
-  * @param  Page_Address1: The page address in program memory to be erased in 
-  *         the first Bank (BANK1). This parameter should be between FLASH_BASE
-  *         and FLASH_BANK1_END.
-  * @param  Page_Address2: The page address in program memory to be erased in 
-  *         the second Bank (BANK2). This parameter should be between FLASH_BANK2_BASE
-  *         and FLASH_BANK2_END.
-  * @note   A Page is erased in the Program memory only if the address to load 
-  *         is the start address of a page (multiple of 256 bytes).
-  * @retval HAL Status: The returned value can be: 
-  *          HAL_ERROR, HAL_OK or HAL_TIMEOUT.
-  */
-__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* If the previous operation is completed, proceed to erase the page */
-
-    /* Set the PARALLBANK bit */
-    FLASH->PECR |= FLASH_PECR_PARALLBANK;
-    
-    /* Set the ERASE bit */
-    FLASH->PECR |= FLASH_PECR_ERASE;
-
-    /* Set PROG bit */
-    FLASH->PECR |= FLASH_PECR_PROG;
-  
-    /* Write 00000000h to the first word of the first program page to erase */
-    *(__IO uint32_t *)Page_Address1 = 0x00000000;
-    /* Write 00000000h to the first word of the second program page to erase */    
-    *(__IO uint32_t *)Page_Address2 = 0x00000000;    
- 
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-
-    /* If the erase operation is completed, disable the ERASE, PROG and PARALLBANK bits */
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);   
-  }     
-  /* Return the Erase Status */
-  return status;
-}
-
-/**
-  * @brief  Programs 2 half page in program memory in parallel.
-  * @note   This function can be used only for STM32L151xD, STM32L152xD), STM32L162xD and Cat5  devices.
-  * @param  Address1: specifies the first address to be written in the first bank 
-  *        (BANK1). This parameter should be between FLASH_BASE and (FLASH_BANK1_END - FLASH_PAGE_SIZE).
-  * @param  pBuffer1: pointer to the buffer  containing the data to be  written 
-  *         to the first half page in the first bank.
-  * @param  Address2: specifies the second address to be written in the second bank
-  *        (BANK2). This parameter should be between FLASH_BANK2_BASE and (FLASH_BANK2_END - FLASH_PAGE_SIZE).
-  * @param  pBuffer2: pointer to the buffer containing the data to be  written 
-  *         to the second half page in the second bank.
-  * @note   To correctly run this function, the HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_Lock() to disable the flash memory access  
-  *         (recommended to protect the FLASH memory against possible unwanted operation).
-  * @note   Half page write is possible only from SRAM.
-  * @note   If there are more than 32 words to write, after 32 words another 
-  *         Half Page programming operation starts and has to be finished.
-  * @note   A half page is written to the program memory only if the first 
-  *         address to load is the start address of a half page (multiple of 128 
-  *         bytes) and the 31 remaining words to load are in the same half page.
-  * @note   During the Program memory half page write all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @note   If a PGAERR is set during a Program memory half page write, the 
-  *         complete write operation is aborted. Software should then reset the 
-  *         FPRG and PROG/DATA bits and restart the write operation from the 
-  *         beginning.
-  * @retval HAL Status: The returned value can be:  
-  *          HAL_ERROR, HAL_OK or HAL_TIMEOUT.
-  */
-__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2)
-{
-  uint32_t count = 0; 
-   
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) 
-     This bit prevents the interruption of multicycle instructions and therefore 
-     will increase the interrupt latency. of Cortex-M3. */
-  SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
-
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* If the previous operation is completed, proceed to program the new  
-       half page */
-    FLASH->PECR |= FLASH_PECR_PARALLBANK;
-    FLASH->PECR |= FLASH_PECR_FPRG;
-    FLASH->PECR |= FLASH_PECR_PROG;
-    
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  if(status == HAL_OK)
-  {
-    /* Write the first half page directly with 32 different words */
-    while(count < 32)
-    {
-      *(__IO uint32_t*) ((uint32_t)(Address1 + (4 * count))) = *(pBuffer1++);
-      count ++;  
-    }
-    count = 0;
-
-    /* Write the second half page directly with 32 different words */
-    while(count < 32)
-    {
-      *(__IO uint32_t*) ((uint32_t)(Address2 + (4 * count))) = *(pBuffer2++);
-      count ++;  
-    }
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  } 
-    /* if the write operation is completed, disable the PROG, FPRG and PARALLBANK bits */
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_PARALLBANK);
-  }
-
-  SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
-    
-  /* Return the Write Status */
-  return status;
-}
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @brief  Programs a half page in program memory.
-  * @param  Address: specifies the address to be written.
-  * @param  pBuffer: pointer to the buffer  containing the data to be  written to 
-  *         the half page.
-  * @note   To correctly run this function, the HAL_FLASH_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_Lock() to disable the flash memory access  
-  *         (recommended to protect the FLASH memory against possible unwanted operation)
-  * @note   Half page write is possible only from SRAM.
-  * @note   If there are more than 32 words to write, after 32 words another 
-  *         Half Page programming operation starts and has to be finished.
-  * @note   A half page is written to the program memory only if the first 
-  *         address to load is the start address of a half page (multiple of 128 
-  *         bytes) and the 31 remaining words to load are in the same half page.
-  * @note   During the Program memory half page write all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @note   If a PGAERR is set during a Program memory half page write, the 
-  *         complete write operation is aborted. Software should then reset the 
-  *         FPRG and PROG/DATA bits and restart the write operation from the 
-  *         beginning.
-  * @retval HAL Status: The returned value can be:  
-  *    HAL_ERROR, HAL_OK or HAL_TIMEOUT. 
-  */
-__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer)
-{
-  uint32_t count = 0; 
-   
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) 
-     This bit prevents the interruption of multicycle instructions and therefore 
-     will increase the interrupt latency. of Cortex-M3. */
-  SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
-  
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* if the previous operation is completed, proceed to program the new  
-    half page */
-    FLASH->PECR |= FLASH_PECR_FPRG;
-    FLASH->PECR |= FLASH_PECR_PROG;
-    
-    /* Write one half page directly with 32 different words */
-    while(count < 32)
-    {
-      *(__IO uint32_t*) ((uint32_t)(Address + (4 * count))) = *(pBuffer++);
-      count ++;  
-    }
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
- 
-    /* if the write operation is completed, disable the PROG and FPRG bits */
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_PROG);
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
-  }
-
-  SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
-    
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHRamfunc_Exported_Functions_Group3 FLASH RAM DATA EEPROM functions
- *
-@verbatim  
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Erase a double word in data memory.
-  * @param  Address: specifies the address to be erased.
-  * @note   To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
-  *         and Flash program erase control register access(recommended to protect 
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @note   Data memory double word erase is possible only from SRAM.
-  * @note   A double word is erased to the data memory only if the first address 
-  *         to load is the start address of a double word (multiple of 8 bytes).
-  * @note   During the Data memory double word erase, all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @retval HAL Status: The returned value can be: 
-  *    HAL_ERROR, HAL_OK or HAL_TIMEOUT.
-  */
-
-__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) 
-     This bit prevents the interruption of multicycle instructions and therefore 
-     will increase the interrupt latency. of Cortex-M3. */
-  SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
-    
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* If the previous operation is completed, proceed to erase the next double word */
-    /* Set the ERASE bit */
-    FLASH->PECR |= FLASH_PECR_ERASE;
-
-    /* Set DATA bit */
-    FLASH->PECR |= FLASH_PECR_DATA;
-   
-    /* Write 00000000h to the 2 words to erase */
-    *(__IO uint32_t *)Address = 0x00000000;
-    Address += 4;
-    *(__IO uint32_t *)Address = 0x00000000;
-   
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-    
-    /* If the erase operation is completed, disable the ERASE and DATA bits */
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_ERASE);
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);
-  }  
-  
-  SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
-    
-  /* Return the erase status */
-  return status;
-}
-
-/**
-  * @brief  Write a double word in data memory without erase.
-  * @param  Address: specifies the address to be written.
-  * @param  Data: specifies the data to be written.
-  * @note   To correctly run this function, the HAL_FLASH_EEPROM_Unlock() function
-  *         must be called before.
-  *         Call the HAL_FLASH_EEPROM_Lock() to he data EEPROM access
-  *         and Flash program erase control register access(recommended to protect 
-  *         the DATA_EEPROM against possible unwanted operation).
-  * @note   Data memory double word write is possible only from SRAM.
-  * @note   A data memory double word is written to the data memory only if the 
-  *         first address to load is the start address of a double word (multiple 
-  *         of double word).
-  * @note   During the Data memory double word write, all read operations are 
-  *         forbidden (this includes DMA read operations and debugger read 
-  *         operations such as breakpoints, periodic updates, etc.).
-  * @retval HAL Status: The returned value can be: 
-  *    HAL_ERROR, HAL_OK or HAL_TIMEOUT. 
-  */ 
-__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Set the DISMCYCINT[0] bit in the Auxillary Control Register (0xE000E008) 
-     This bit prevents the interruption of multicycle instructions and therefore 
-     will increase the interrupt latency. of Cortex-M3. */
-  SCnSCB->ACTLR |= SCnSCB_ACTLR_DISMCYCINT_Msk;
-    
-  /* Wait for last operation to be completed */
-  status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-  
-  if(status == HAL_OK)
-  {
-    /* If the previous operation is completed, proceed to program the new data*/
-    FLASH->PECR |= FLASH_PECR_FPRG;
-    FLASH->PECR |= FLASH_PECR_DATA;
-    
-    /* Write the 2 words */  
-     *(__IO uint32_t *)Address = (uint32_t) Data;
-     Address += 4;
-     *(__IO uint32_t *)Address = (uint32_t) (Data >> 32);
-    
-    /* Wait for last operation to be completed */
-    status = FLASHRAM_WaitForLastOperation(HAL_FLASH_TIMEOUT_VALUE);
-    
-    /* If the write operation is completed, disable the FPRG and DATA bits */
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_FPRG);
-    FLASH->PECR &= (uint32_t)(~FLASH_PECR_DATA);     
-  }
-  
-  SCnSCB->ACTLR &= ~SCnSCB_ACTLR_DISMCYCINT_Msk;
-    
-  /* Return the Write Status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup FLASHRamfunc_Private_Functions FLASH RAM Private Functions
-  * @{
-  */ 
-
-/**
-  * @brief  Wait for a FLASH operation to complete.
-  * @param  Timeout: maximum flash operationtimeout
-  * @retval HAL status
-  */
-static __RAM_FUNC   FLASHRAM_WaitForLastOperation(uint32_t Timeout)
-{ 
-    /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
-       Even if the FLASH operation fails, the BUSY flag will be reset and an error
-       flag will be set */
-       
-    while(__HAL_FLASH_GET_FLAG(FLASH_FLAG_BSY) && (Timeout != 0x00)) 
-    { 
-      Timeout--;
-    }
-    
-    if(Timeout == 0x00 )
-    {
-      return HAL_TIMEOUT;
-    }
-    
-    if( (__HAL_FLASH_GET_FLAG(FLASH_FLAG_WRPERR)     != RESET) || 
-        (__HAL_FLASH_GET_FLAG(FLASH_FLAG_PGAERR)     != RESET) || 
-        (__HAL_FLASH_GET_FLAG(FLASH_FLAG_SIZERR)     != RESET) || 
-#if defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC)
-        (__HAL_FLASH_GET_FLAG(FLASH_FLAG_RDERR)      != RESET) || 
-#endif /* STM32L151xBA || STM32L152xBA || STM32L151xC || STM32L152xC || STM32L162xC */
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-        (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERRUSR) != RESET) || 
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-        (__HAL_FLASH_GET_FLAG(FLASH_FLAG_OPTVERR)    != RESET) )
-    {
-      return HAL_ERROR;
-    }
-  
-    /* If there is an error flag set */
-    return HAL_OK;
-}
-
-#endif /* HAL_FLASH_MODULE_ENABLED */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-     
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_flash_ramfunc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,130 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_flash_ramfunc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of FLASH RAMFUNC driver.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_FLASH_RAMFUNC_H
-#define __STM32L1xx_FLASH_RAMFUNC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FLASHRamfunc
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FLASHRamfunc_Exported_Functions
-  * @{
-  */
-
-/*
-  * @brief  FLASH memory functions that should be executed from internal SRAM.
-  *         These functions are defined inside the "stm32l1xx_hal_flash_ramfunc.c"
-  *         file.
-  */
-  
-/** @addtogroup FLASHRamfunc_Exported_Functions_Group1
-  * @{
-  */
-
-__RAM_FUNC HAL_FLASHEx_EnableRunPowerDown(void);
-__RAM_FUNC HAL_FLASHEx_DisableRunPowerDown(void);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASHRamfunc_Exported_Functions_Group2
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-__RAM_FUNC HAL_FLASHEx_EraseParallelPage(uint32_t Page_Address1, uint32_t Page_Address2);
-__RAM_FUNC HAL_FLASHEx_ProgramParallelHalfPage(uint32_t Address1, uint32_t* pBuffer1, uint32_t Address2, uint32_t* pBuffer2);
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-__RAM_FUNC HAL_FLASHEx_HalfPageProgram(uint32_t Address, uint32_t* pBuffer);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup FLASHRamfunc_Exported_Functions_Group3
-  * @{
-  */
-
-__RAM_FUNC HAL_FLASHEx_DATAEEPROM_EraseDoubleWord(uint32_t Address);
-__RAM_FUNC HAL_FLASHEx_DATAEEPROM_ProgramDoubleWord(uint32_t Address, uint64_t Data);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_FLASH_RAMFUNC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,540 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_gpio.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   GPIO HAL module driver.
-  *         This file provides firmware functions to manage the following 
-  *          functionalities of the General Purpose Input/Output (GPIO) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### GPIO Peripheral features #####
-  ==============================================================================         
-  [..] 
-  Each port bit of the general-purpose I/O (GPIO) ports can be individually 
-  configured by software in several modes:
-  (+) Input mode 
-  (+) Analog mode
-  (+) Output mode
-  (+) Alternate function mode
-  (+) External interrupt/event lines
- 
-  [..]  
-  During and just after reset, the alternate functions and external interrupt  
-  lines are not active and the I/O ports are configured in input floating mode.
-  
-  [..]   
-  All GPIO pins have weak internal pull-up and pull-down resistors, which can be 
-  activated or not.
-
-  [..]
-  In Output or Alternate mode, each IO can be configured on open-drain or push-pull
-  type and the IO speed can be selected depending on the VDD value.
-  
-  [..]
-  The microcontroller IO pins are connected to onboard peripherals/modules through a 
-  multiplexer that allows only one peripheral’s alternate function (AF) connected 
-  to an IO pin at a time. In this way, there can be no conflict between peripherals 
-  sharing the same IO pin. 
-
-  [..]  
-  All ports have external interrupt/event capability. To use external interrupt 
-  lines, the port must be configured in input mode. All available GPIO pins are 
-  connected to the 16 external interrupt/event lines from EXTI0 to EXTI15.
-  
-  [..]  
-  The external interrupt/event controller consists of up to 23 edge detectors 
-  (16 lines are connected to GPIO) for generating event/interrupt requests (each 
-  input line can be independently configured to select the type (interrupt or event) 
-  and the corresponding trigger event (rising or falling or both). Each line can 
-  also be masked independently. 
- 
-                     ##### How to use this driver #####
-  ==============================================================================  
- [..]             
-   (#) Enable the GPIO AHB clock using the following function : __GPIOx_CLK_ENABLE(). 
-   
-   (#) Configure the GPIO pin(s) using HAL_GPIO_Init().
-       (++) Configure the IO mode using "Mode" member from GPIO_InitTypeDef structure
-       (++) Activate Pull-up, Pull-down resistor using "Pull" member from GPIO_InitTypeDef 
-            structure.
-       (++) In case of Output or alternate function mode selection: the speed is 
-            configured through "Speed" member from GPIO_InitTypeDef structure
-       (++) If alternate mode is selected, the alternate function connected to the IO
-            is configured through "Alternate" member from GPIO_InitTypeDef structure
-       (++) Analog mode is required when a pin is to be used as ADC channel 
-            or DAC output.
-       (++) In case of external interrupt/event selection the "Mode" member from 
-            GPIO_InitTypeDef structure select the type (interrupt or event) and 
-            the corresponding trigger event (rising or falling or both).
-   
-   (#) In case of external interrupt/event mode selection, configure NVIC IRQ priority 
-       mapped to the EXTI line using HAL_NVIC_SetPriority() and enable it using
-       HAL_NVIC_EnableIRQ().
-         
-   (#) To get the level of a pin configured in input mode use HAL_GPIO_ReadPin().
-            
-   (#) To set/reset the level of a pin configured in output mode use 
-       HAL_GPIO_WritePin()/HAL_GPIO_TogglePin().
-  
-   (#) To lock pin configuration until next reset use HAL_GPIO_LockPin().
-                 
-   (#) During and just after reset, the alternate functions are not 
-       active and the GPIO pins are configured in input floating mode (except JTAG
-       pins).
-  
-   (#) The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as general purpose 
-       (PC14 and PC15, respectively) when the LSE oscillator is off. The LSE has 
-       priority over the GPIO function.
-  
-   (#) The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
-       general purpose PH0 and PH1, respectively, when the HSE oscillator is off. 
-       The HSE has priority over the GPIO function.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIO GPIO
-  * @brief GPIO HAL module driver
-  * @{
-  */
-
-#ifdef HAL_GPIO_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup GPIO_Private_Constants GPIO Private Constants
-  * @{
-  */
-
-#define GPIO_MODE             ((uint32_t)0x00000003)
-#define EXTI_MODE             ((uint32_t)0x10000000)
-#define GPIO_MODE_IT          ((uint32_t)0x00010000)
-#define GPIO_MODE_EVT         ((uint32_t)0x00020000)
-#define RISING_EDGE           ((uint32_t)0x00100000) 
-#define FALLING_EDGE          ((uint32_t)0x00200000) 
-#define GPIO_OUTPUT_TYPE      ((uint32_t)0x00000010) 
-#define GPIO_NUMBER           ((uint32_t)16)
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Functions GPIO Exported Functions
-  * @{
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init.
-  * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-  * @param  GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains
-  *         the configuration information for the specified GPIO peripheral.
-  * @retval None
-  */
-void HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init)
-{
-  uint32_t position;
-  uint32_t ioposition = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t temp = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Init->Pin));
-  assert_param(IS_GPIO_MODE(GPIO_Init->Mode));
-  assert_param(IS_GPIO_PULL(GPIO_Init->Pull)); 
-
-  /* Configure the port pins */
-  for (position = 0; position < GPIO_NUMBER; position++)
-  {
-    /* Get the IO position */
-    ioposition = ((uint32_t)0x01) << position;
-    /* Get the current IO position */
-    iocurrent = (uint32_t)(GPIO_Init->Pin) & ioposition;
-
-    if (iocurrent == ioposition)
-    {
-      /*--------------------- GPIO Mode Configuration ------------------------*/
-      /* In case of Alternate function mode selection */
-      if((GPIO_Init->Mode == GPIO_MODE_AF_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_OD)) 
-      {
-        /* Check the Alternate function parameter */
-        assert_param(IS_GPIO_AF(GPIO_Init->Alternate));
-        /* Configure Alternate function mapped with the current IO */ 
-        /* Identify AFRL or AFRH register based on IO position*/
-        temp = GPIOx->AFR[position >> 3];
-        CLEAR_BIT(temp, (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;      
-        SET_BIT(temp, (uint32_t)(GPIO_Init->Alternate) << (((uint32_t)position & (uint32_t)0x07) * 4));       
-        GPIOx->AFR[position >> 3] = temp;
-      } 
-
-      /* Configure IO Direction mode (Input, Output, Alternate or Analog) */
-      temp = GPIOx->MODER;
-      CLEAR_BIT(temp, GPIO_MODER_MODER0 << (position * 2));   
-      SET_BIT(temp, (GPIO_Init->Mode & GPIO_MODE) << (position * 2));
-      GPIOx->MODER = temp;
-
-      /* In case of Output or Alternate function mode selection */
-      if ((GPIO_Init->Mode == GPIO_MODE_OUTPUT_PP) || (GPIO_Init->Mode == GPIO_MODE_AF_PP) ||
-          (GPIO_Init->Mode == GPIO_MODE_OUTPUT_OD) || (GPIO_Init->Mode == GPIO_MODE_AF_OD))
-      {
-        /* Check the Speed parameter */
-        assert_param(IS_GPIO_SPEED(GPIO_Init->Speed));
-        /* Configure the IO Speed */
-        temp = GPIOx->OSPEEDR; 
-        CLEAR_BIT(temp, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-        SET_BIT(temp, GPIO_Init->Speed << (position * 2));
-        GPIOx->OSPEEDR = temp;
-
-        /* Configure the IO Output Type */
-        temp = GPIOx->OTYPER;
-        CLEAR_BIT(temp, GPIO_OTYPER_OT_0 << position) ;
-        SET_BIT(temp, ((GPIO_Init->Mode & GPIO_OUTPUT_TYPE) >> 4) << position);
-        GPIOx->OTYPER = temp;
-      }
-
-      /* Activate the Pull-up or Pull down resistor for the current IO */
-      temp = GPIOx->PUPDR;
-      CLEAR_BIT(temp, GPIO_PUPDR_PUPDR0 << (position * 2));
-      SET_BIT(temp, (GPIO_Init->Pull) << (position * 2));
-      GPIOx->PUPDR = temp;
-      
-      /*--------------------- EXTI Mode Configuration ------------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      if((GPIO_Init->Mode & EXTI_MODE) == EXTI_MODE) 
-      {
-        /* Enable SYSCFG Clock */
-        __SYSCFG_CLK_ENABLE();
-        
-        temp = SYSCFG->EXTICR[position >> 2];
-        CLEAR_BIT(temp, ((uint32_t)0x0F) << (4 * (position & 0x03)));
-        SET_BIT(temp, (GET_GPIO_INDEX(GPIOx)) << (4 * (position & 0x03)));
-        SYSCFG->EXTICR[position >> 2] = temp;
-        
-        /* Clear EXTI line configuration */
-        temp = EXTI->IMR;
-        CLEAR_BIT(temp, (uint32_t)iocurrent);
-        if((GPIO_Init->Mode & GPIO_MODE_IT) == GPIO_MODE_IT)
-        {
-          SET_BIT(temp, iocurrent); 
-        }
-        EXTI->IMR = temp;
-
-        temp = EXTI->EMR;
-        CLEAR_BIT(temp, (uint32_t)iocurrent);      
-        if((GPIO_Init->Mode & GPIO_MODE_EVT) == GPIO_MODE_EVT)
-        {
-          SET_BIT(temp, iocurrent); 
-        }
-        EXTI->EMR = temp;
-        
-        /* Clear Rising Falling edge configuration */
-        temp = EXTI->RTSR;
-        CLEAR_BIT(temp, (uint32_t)iocurrent); 
-        if((GPIO_Init->Mode & RISING_EDGE) == RISING_EDGE)
-        {
-          SET_BIT(temp, iocurrent); 
-        }
-        EXTI->RTSR = temp;
-
-        temp = EXTI->FTSR;
-        CLEAR_BIT(temp, (uint32_t)iocurrent); 
-        if((GPIO_Init->Mode & FALLING_EDGE) == FALLING_EDGE)
-        {
-          SET_BIT(temp, iocurrent); 
-        }
-        EXTI->FTSR = temp;
-      }    
-    }
-  }
-}
-
-/**
-  * @brief  De-initializes the GPIOx peripheral registers to their default reset values.
-  * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *         This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @retval None
-  */
-void HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin)
-{ 
-  uint32_t position;
-  uint32_t ioposition = 0x00;
-  uint32_t iocurrent = 0x00;
-  uint32_t tmp = 0x00;
- 
-  /* Check the parameters */
-  assert_param(IS_GPIO_ALL_INSTANCE(GPIOx));
-
-  /* Configure the port pins */
-  for (position = 0; position < GPIO_NUMBER; position++)
-  {
-    /* Get the IO position */
-    ioposition = ((uint32_t)0x01) << position;
-    /* Get the current IO position */
-    iocurrent = (GPIO_Pin) & ioposition;
-
-    if (iocurrent == ioposition)
-    {
-      /*------------------------- GPIO Mode Configuration --------------------*/
-      /* Configure IO Direction in Input Floting Mode */
-      CLEAR_BIT(GPIOx->MODER, GPIO_MODER_MODER0 << (position * 2)); 
-    
-      /* Configure the default Alternate Function in current IO */ 
-      CLEAR_BIT(GPIOx->AFR[position >> 3], (uint32_t)0xF << ((uint32_t)(position & (uint32_t)0x07) * 4)) ;
-     
-      /* Configure the default value for IO Speed */
-      CLEAR_BIT(GPIOx->OSPEEDR, GPIO_OSPEEDER_OSPEEDR0 << (position * 2));
-
-      /* Configure the default value IO Output Type */
-      CLEAR_BIT(GPIOx->OTYPER, GPIO_OTYPER_OT_0 << position) ;
-      
-      /* Deactivate the Pull-up oand Pull-down resistor for the current IO */
-      CLEAR_BIT(GPIOx->PUPDR, GPIO_PUPDR_PUPDR0 << (position * 2));
-      
-    
-      /*------------------------- EXTI Mode Configuration --------------------*/
-      /* Configure the External Interrupt or event for the current IO */
-      tmp = ((uint32_t)0x0F) << (4 * (position & 0x03));
-      CLEAR_BIT(SYSCFG->EXTICR[position >> 2], tmp);
-         
-      /* Clear EXTI line configuration */
-      CLEAR_BIT(EXTI->IMR, (uint32_t)iocurrent);
-      CLEAR_BIT(EXTI->EMR, (uint32_t)iocurrent);
-       
-      /* Clear Rising Falling edge configuration */
-      CLEAR_BIT(EXTI->RTSR, (uint32_t)iocurrent);
-      CLEAR_BIT(EXTI->FTSR, (uint32_t)iocurrent);
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIO_Exported_Functions_Group2 IO operation functions 
- *  @brief   GPIO Read and Write 
- *
-@verbatim   
- ===============================================================================
-                       ##### IO operation functions #####
- ===============================================================================  
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads the specified input port pin.
-  * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices 
-  * @param  GPIO_Pin: specifies the port bit to read.
-  *         This parameter can be GPIO_PIN_x where x can be (0..15).
-  * @retval The input port pin value.
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  GPIO_PinState bitstatus;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)GPIO_PIN_RESET)
-  {
-    bitstatus = GPIO_PIN_SET;
-  }
-  else
-  {
-    bitstatus = GPIO_PIN_RESET;
-  }
-  return bitstatus;
-}
-
-/**
-  * @brief  Sets or clears the selected data port bit.
-  * 
-  * @note   This function uses GPIOx_BSRR register to allow atomic read/modify 
-  *         accesses. In this way, there is no risk of an IRQ occurring between
-  *         the read and the modify access.
-  *               
-  * @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices
-  * @param  GPIO_Pin: specifies the port bit to be written.
-  *          This parameter can be one of GPIO_PIN_x where x can be (0..15).
-  * @param  PinState: specifies the value to be written to the selected bit.
-  *          This parameter can be one of the GPIO_PinState enum values:
-  *            @arg GPIO_BIT_RESET: to clear the port pin
-  *            @arg GPIO_BIT_SET: to set the port pin
-  * @retval None
-  */
-void HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-  assert_param(IS_GPIO_PIN_ACTION(PinState));
-
-  if(PinState != GPIO_PIN_RESET)
-  {
-    GPIOx->BSRR = GPIO_Pin;
-  }
-  else
-  {
-    GPIOx->BSRR = (uint32_t)GPIO_Pin << 16;
-  }
-}
-
-/**
-  * @brief  Toggles the specified GPIO pin
-  * @param  GPIOx: where x can be (A..Gdepending on device used) to select the GPIO peripheral for STM32L1XX family devices 
-  * @param  GPIO_Pin: Specifies the pins to be toggled.
-  * @retval None
-  */
-void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  /* Check the parameters */
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  GPIOx->ODR ^= GPIO_Pin;
-}
-
-/**
-* @brief  Locks GPIO Pins configuration registers.
-* @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
-*         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
-* @note   The configuration of the locked GPIO pins can no longer be modified
-*         until the next reset.
-* @param  GPIOx: where x can be (A..G depending on device used) to select the GPIO peripheral for STM32L1XX family devices 
-* @param  GPIO_Pin: specifies the port bit to be locked.
-*         This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
-* @retval None
-*/
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
-{
-  __IO uint32_t tmp = GPIO_LCKR_LCKK;
-
-  /* Check the parameters */
-  assert_param(IS_GPIO_LOCK_INSTANCE(GPIOx));
-  assert_param(IS_GPIO_PIN(GPIO_Pin));
-
-  /* Apply lock key write sequence */
-  SET_BIT(tmp, GPIO_Pin);
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Reset LCKx bit(s): LCKK='0' + LCK[15-0] */
-  GPIOx->LCKR = GPIO_Pin;
-  /* Set LCKx bit(s): LCKK='1' + LCK[15-0] */
-  GPIOx->LCKR = tmp;
-  /* Read LCKK bit*/
-  tmp = GPIOx->LCKR;
-
-  if((uint32_t)(GPIOx->LCKR & GPIO_LCKR_LCKK))
-  {
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief This function handles EXTI interrupt request.
-  * @param GPIO_Pin: Specifies the pins connected EXTI line
-  * @retval None
-  */
-void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin)
-{
-  /* EXTI line interrupt detected */
-  if(__HAL_GPIO_EXTI_GET_IT(GPIO_Pin) != RESET) 
-  { 
-    __HAL_GPIO_EXTI_CLEAR_IT(GPIO_Pin);
-    HAL_GPIO_EXTI_Callback(GPIO_Pin);
-  }
-}
-
-/**
-  * @brief  EXTI line detection callback
-  * @param GPIO_Pin: Specifies the pins connected EXTI line
-  * @retval None
-  */
-__weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_GPIO_EXTI_Callback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_GPIO_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,331 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_gpio.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of GPIO HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_GPIO_H
-#define __STM32L1xx_HAL_GPIO_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup GPIO
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Types GPIO Exported Types
-  * @{
-  */ 
-
-/** 
-  * @brief   GPIO Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Pin;       /*!< Specifies the GPIO pins to be configured.
-                           This parameter can be any value of @ref GPIO_pins_define */
-
-  uint32_t Mode;      /*!< Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref GPIO_mode_define */
-                           
-  uint32_t Pull;      /*!< Specifies the Pull-up or Pull-Down activation for the selected pins.
-                           This parameter can be a value of @ref GPIO_pull_define */
-                           
-  uint32_t Speed;     /*!< Specifies the speed for the selected pins.
-                           This parameter can be a value of @ref GPIO_speed_define */
-
-  uint32_t Alternate;  /*!< Peripheral to be connected to the selected pins 
-                            This parameter can be a value of @ref GPIOEx_Alternate_function_selection */
-}GPIO_InitTypeDef;
- 
-/** 
-  * @brief  GPIO Bit SET and Bit RESET enumeration 
-  */
-typedef enum
-{ 
-  GPIO_PIN_RESET = 0,
-  GPIO_PIN_SET
-}GPIO_PinState;
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIO_Exported_Constants GPIO Exported Constants
-  * @{
-  */ 
-
-/** @defgroup GPIO_pins_define GPIO pins define
-  * @{
-  */ 
-#define GPIO_PIN_0                 ((uint16_t)0x0001)  /* Pin 0 selected    */
-#define GPIO_PIN_1                 ((uint16_t)0x0002)  /* Pin 1 selected    */
-#define GPIO_PIN_2                 ((uint16_t)0x0004)  /* Pin 2 selected    */
-#define GPIO_PIN_3                 ((uint16_t)0x0008)  /* Pin 3 selected    */
-#define GPIO_PIN_4                 ((uint16_t)0x0010)  /* Pin 4 selected    */
-#define GPIO_PIN_5                 ((uint16_t)0x0020)  /* Pin 5 selected    */
-#define GPIO_PIN_6                 ((uint16_t)0x0040)  /* Pin 6 selected    */
-#define GPIO_PIN_7                 ((uint16_t)0x0080)  /* Pin 7 selected    */
-#define GPIO_PIN_8                 ((uint16_t)0x0100)  /* Pin 8 selected    */
-#define GPIO_PIN_9                 ((uint16_t)0x0200)  /* Pin 9 selected    */
-#define GPIO_PIN_10                ((uint16_t)0x0400)  /* Pin 10 selected   */
-#define GPIO_PIN_11                ((uint16_t)0x0800)  /* Pin 11 selected   */
-#define GPIO_PIN_12                ((uint16_t)0x1000)  /* Pin 12 selected   */
-#define GPIO_PIN_13                ((uint16_t)0x2000)  /* Pin 13 selected   */
-#define GPIO_PIN_14                ((uint16_t)0x4000)  /* Pin 14 selected   */
-#define GPIO_PIN_15                ((uint16_t)0x8000)  /* Pin 15 selected   */
-#define GPIO_PIN_All               ((uint16_t)0xFFFF)  /* All pins selected */
-
-#define GPIO_PIN_MASK              ((uint32_t)0x0000FFFF) /* PIN mask for assert test */
-/**
-  * @}
-  */ 
-
-     
-/** @defgroup GPIO_mode_define GPIO mode define
-  * @brief GPIO Configuration Mode 
-  *        Elements values convention: 0xX0yz00YZ
-  *           - X  : GPIO mode or EXTI Mode
-  *           - y  : External IT or Event trigger detection 
-  *           - z  : IO configuration on External IT or Event
-  *           - Y  : Output type (Push Pull or Open Drain)
-  *           - Z  : IO Direction mode (Input, Output, Alternate or Analog)
-  * @{
-  */ 
-#define  GPIO_MODE_INPUT                        ((uint32_t)0x00000000)   /*!< Input Floating Mode                   */
-#define  GPIO_MODE_OUTPUT_PP                    ((uint32_t)0x00000001)   /*!< Output Push Pull Mode                 */
-#define  GPIO_MODE_OUTPUT_OD                    ((uint32_t)0x00000011)   /*!< Output Open Drain Mode                */
-#define  GPIO_MODE_AF_PP                        ((uint32_t)0x00000002)   /*!< Alternate Function Push Pull Mode     */
-#define  GPIO_MODE_AF_OD                        ((uint32_t)0x00000012)   /*!< Alternate Function Open Drain Mode    */
-
-#define  GPIO_MODE_ANALOG                       ((uint32_t)0x00000003)   /*!< Analog Mode  */
-    
-#define  GPIO_MODE_IT_RISING                    ((uint32_t)0x10110000)   /*!< External Interrupt Mode with Rising edge trigger detection          */
-#define  GPIO_MODE_IT_FALLING                   ((uint32_t)0x10210000)   /*!< External Interrupt Mode with Falling edge trigger detection         */
-#define  GPIO_MODE_IT_RISING_FALLING            ((uint32_t)0x10310000)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection  */
- 
-#define  GPIO_MODE_EVT_RISING                   ((uint32_t)0x10120000)   /*!< External Event Mode with Rising edge trigger detection               */
-#define  GPIO_MODE_EVT_FALLING                  ((uint32_t)0x10220000)   /*!< External Event Mode with Falling edge trigger detection              */
-#define  GPIO_MODE_EVT_RISING_FALLING           ((uint32_t)0x10320000)   /*!< External Event Mode with Rising/Falling edge trigger detection       */
-
-/**
-  * @}
-  */
-
-                                                         
-/** @defgroup GPIO_speed_define GPIO speed define
-  * @brief GPIO Output Maximum frequency
-  * @{
-  */  
-#define  GPIO_SPEED_VERY_LOW         ((uint32_t)0x00000000)  /*!< Very Low speed     */
-#define  GPIO_SPEED_LOW              ((uint32_t)0x00000001)  /*!< Low speed  */
-#define  GPIO_SPEED_MEDIUM           ((uint32_t)0x00000002)  /*!< Medium speed    */
-#define  GPIO_SPEED_HIGH             ((uint32_t)0x00000003)  /*!< High speed         */
-
-/**
-  * @}
-  */
-
-
- /** @defgroup GPIO_pull_define GPIO pull define
-   * @brief GPIO Pull-Up or Pull-Down Activation
-   * @{
-   */  
-#define  GPIO_NOPULL        ((uint32_t)0x00000000)   /*!< No Pull-up or Pull-down activation  */
-#define  GPIO_PULLUP        ((uint32_t)0x00000001)   /*!< Pull-up activation                  */
-#define  GPIO_PULLDOWN      ((uint32_t)0x00000002)   /*!< Pull-down activation                */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-
-/* Private macros --------------------------------------------------------*/
-/** @addtogroup GPIO_Private_Macros
-  * @{
-  */
-
-#define IS_GPIO_PIN_ACTION(ACTION) (((ACTION) == GPIO_PIN_RESET) || ((ACTION) == GPIO_PIN_SET))
-
-#define IS_GPIO_PIN(PIN)           (((PIN) & GPIO_PIN_MASK ) != (uint32_t)0x00)
-
-#define IS_GPIO_PULL(PULL) (((PULL) == GPIO_NOPULL) || ((PULL) == GPIO_PULLUP) || \
-                            ((PULL) == GPIO_PULLDOWN))
-                            
-#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_SPEED_VERY_LOW)  || ((SPEED) == GPIO_SPEED_LOW) || \
-                                ((SPEED) == GPIO_SPEED_MEDIUM) || ((SPEED) == GPIO_SPEED_HIGH))
-
-#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_MODE_INPUT)              ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_PP)          ||\
-                            ((MODE) == GPIO_MODE_OUTPUT_OD)          ||\
-                            ((MODE) == GPIO_MODE_AF_PP)              ||\
-                            ((MODE) == GPIO_MODE_AF_OD)              ||\
-                            ((MODE) == GPIO_MODE_IT_RISING)          ||\
-                            ((MODE) == GPIO_MODE_IT_FALLING)         ||\
-                            ((MODE) == GPIO_MODE_IT_RISING_FALLING)  ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING)         ||\
-                            ((MODE) == GPIO_MODE_EVT_FALLING)        ||\
-                            ((MODE) == GPIO_MODE_EVT_RISING_FALLING) ||\
-                            ((MODE) == GPIO_MODE_ANALOG))
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup GPIO_Exported_Macros GPIO Exported Macros
-  * @{
-  */
-
-/**
-  * @brief  Checks whether the specified EXTI line flag is set or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line flag to check.
-  *         This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))   
-     
-/**
-  * @brief  Clears the EXTI's line pending flags.
-  * @param  __EXTI_LINE__: specifies the EXTI lines flags to clear.
-  *         This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Checks whether the specified EXTI line is asserted or not.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval The new state of __EXTI_LINE__ (SET or RESET).
-  */
-#define __HAL_GPIO_EXTI_GET_IT(__EXTI_LINE__) (EXTI->PR & (__EXTI_LINE__))   
-     
-/**
-  * @brief  Clears the EXTI's line pending bits.
-  * @param  __EXTI_LINE__: specifies the EXTI lines to clear.
-  *          This parameter can be any combination of GPIO_PIN_x where x can be (0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_CLEAR_IT(__EXTI_LINE__) (EXTI->PR = (__EXTI_LINE__))
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTI_LINE__: specifies the EXTI line to check.
-  *          This parameter can be GPIO_PIN_x where x can be(0..15)
-  * @retval None
-  */
-#define __HAL_GPIO_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER |= (__EXTI_LINE__))
-
-/* Include GPIO HAL Extension module */
-#include "stm32l1xx_hal_gpio_ex.h"
-/**
-  * @}
-  */
-
-
-
-/* Exported functions --------------------------------------------------------*/ 
-/* Initialization and de-initialization functions *******************************/
-/** @addtogroup GPIO_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup GPIO_Exported_Functions_Group1
- *  @brief    Initialization and Configuration functions 
- *
-  * @{
-  */
-
-void  HAL_GPIO_Init(GPIO_TypeDef  *GPIOx, GPIO_InitTypeDef *GPIO_Init);
-void  HAL_GPIO_DeInit(GPIO_TypeDef  *GPIOx, uint32_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/* IO operation functions *******************************************************/
-/** @addtogroup GPIO_Exported_Functions_Group2
- *  @brief    Initialization and Configuration functions 
- *
-  * @{
-  */
-GPIO_PinState HAL_GPIO_ReadPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void          HAL_GPIO_WritePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, GPIO_PinState PinState);
-void          HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-HAL_StatusTypeDef HAL_GPIO_LockPin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
-void          HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin);
-void          HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_GPIO_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_gpio_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,260 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_gpio_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of GPIO HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_GPIO_EX_H
-#define __STM32L1xx_HAL_GPIO_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup GPIOEx GPIOEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup GPIOEx_Exported_Constants GPIOEx Exported Constants
-  * @{
-  */ 
-  
-/** @defgroup GPIOEx_Alternate_function_selection GPIOEx Alternate function selection 
-  * @{
-  */
-  
-/** 
-  * @brief   AF 0 selection  
-  */ 
-#define GPIO_AF0_MCO           ((uint8_t)0x00)  /* MCO Alternate Function mapping                 */
-#define GPIO_AF0_TAMPER        ((uint8_t)0x00)  /* TAMPER  Alternate Function mapping             */
-#define GPIO_AF0_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping  */
-#define GPIO_AF0_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping               */
-#define GPIO_AF0_RTC_50Hz      ((uint8_t)0x00)  /* RTC_OUT Alternate Function mapping             */
-   
-/** 
-  * @brief   AF 1 selection  
-  */ 
-#define GPIO_AF1_TIM2           ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 2 selection  
-  */ 
-#define GPIO_AF2_TIM3           ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
-#define GPIO_AF2_TIM4           ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-#define GPIO_AF2_TIM5           ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
-
-#endif /*  STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD ...STM32L151xC */ 
-
-/** 
-  * @brief   AF 3 selection  
-  */ 
-#define GPIO_AF3_TIM9            ((uint8_t)0x03)  /* TIM9 Alternate Function mapping */
-#define GPIO_AF3_TIM10           ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
-#define GPIO_AF3_TIM11           ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
-
-
-/** 
-  * @brief   AF 4 selection  
-  */ 
-#define GPIO_AF4_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
-#define GPIO_AF4_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 5 selection  
-  */ 
-#define GPIO_AF5_SPI1          ((uint8_t)0x05)  /* SPI1/I2S1 Alternate Function mapping      */
-#define GPIO_AF5_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping */
-
-/** 
-  * @brief   AF 6 selection  
-  */ 
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L151xE) ||\
-    defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\
-    defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE)
-    
-#define GPIO_AF6_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping */
-
-#endif /* STM32L100xC || STM32L151xC || (...) || STM32L162xD || STM32L162xE */
-
-
-/** 
-  * @brief   AF 7 selection  
-  */ 
-#define GPIO_AF7_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping  */
-#define GPIO_AF7_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping  */
-#define GPIO_AF7_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping  */
-
-/** 
-  * @brief   AF 8 selection  
-  */ 
-#if defined (STM32L151xD) || defined (STM32L151xE) ||\
-    defined (STM32L152xD) || defined (STM32L152xE) ||\
-    defined (STM32L162xD) || defined (STM32L162xE)
-   
-#define GPIO_AF8_UART4        ((uint8_t)0x08)  /* UART4 Alternate Function mapping  */
-#define GPIO_AF8_UART5        ((uint8_t)0x08)  /* UART5 Alternate Function mapping  */
-
-#endif /* STM32L151xD || STM32L151xE || STM32L152xD || STM32L 152xE || STM32L162xD || STM32L162xE */
-
-
-/** 
-  * @brief   AF 9 selection 
-  */ 
-
-/** 
-  * @brief   AF 10 selection  
-  */ 
-
-/** 
-  * @brief   AF 11 selection  
-  */ 
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\
-    defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE)
-
-#define GPIO_AF11_LCD            ((uint8_t)0x0B)  /* LCD Alternate Function mapping */
-
-#endif /* STM32L100xB || STM32L100xBA || STM32L100xC || (...) || STM32L162xCA || STM32L162xD || STM32L162xE */
-
-/** 
-  * @brief   AF 12 selection  
-  */ 
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-    
-#define GPIO_AF12_FSMC            ((uint8_t)0x0C)  /* FSMC Alternate Function mapping */
-#define GPIO_AF12_SDIO            ((uint8_t)0x0C)  /* SDIO Alternate Function mapping */
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-/** 
-  * @brief   AF 13 selection  
-  */ 
-
-/** 
-  * @brief   AF 14 selection  
-  */ 
-#define GPIO_AF14_TIM_IC1         ((uint8_t)0x0E)  /* TIMER INPUT CAPTURE Alternate Function mapping */
-#define GPIO_AF14_TIM_IC2         ((uint8_t)0x0E)  /* TIMER INPUT CAPTURE Alternate Function mapping */
-#define GPIO_AF14_TIM_IC3         ((uint8_t)0x0E)  /* TIMER INPUT CAPTURE Alternate Function mapping */
-#define GPIO_AF14_TIM_IC4         ((uint8_t)0x0E)  /* TIMER INPUT CAPTURE Alternate Function mapping */
-
-/** 
-  * @brief   AF 15 selection  
-  */ 
-#define GPIO_AF15_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/** @defgroup GPIOEx_Private_Macros GPIOEx Private Macros
-  * @{
-  */
-
-
-#define IS_GPIO_AF(AF)   ((AF) <= (uint8_t)0x0F)
-
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :\
-                                   ((__GPIOx__) == (GPIOE))? 4U :\
-                                   ((__GPIOx__) == (GPIOF))? 5U :\
-                                   ((__GPIOx__) == (GPIOG))? 6U :\
-                                   ((__GPIOx__) == (GPIOH))? 7U : 8U)
-#endif 
-
-#if defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC)
-#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :\
-                                   ((__GPIOx__) == (GPIOE))? 4U :\
-                                   ((__GPIOx__) == (GPIOH))? 7U : 8U)
-#endif 
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC)
-#define GET_GPIO_INDEX(__GPIOx__) (((__GPIOx__) == (GPIOA))? 0U :\
-                                   ((__GPIOx__) == (GPIOB))? 1U :\
-                                   ((__GPIOx__) == (GPIOC))? 2U :\
-                                   ((__GPIOx__) == (GPIOD))? 3U :\
-                                   ((__GPIOx__) == (GPIOH))? 7U : 8U)
-#endif 
-
-
-
-/**
-  * @}
-  */
-
-
-
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/ 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_GPIO_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,3635 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_i2c.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   I2C HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Inter Integrated Circuit (I2C) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The I2C HAL driver can be used as follows:
-
-    (#) Declare a I2C_HandleTypeDef handle structure, for example:
-        I2C_HandleTypeDef  hi2c;
-
-    (#)Initialize the I2C low level resources by implement the HAL_I2C_MspInit() API:
-        (##) Enable the I2Cx interface clock
-        (##) I2C pins configuration
-            (+++) Enable the clock for the I2C GPIOs
-            (+++) Configure I2C pins as alternate function open-drain
-        (##) NVIC configuration if you need to use interrupt process
-            (+++) Configure the I2Cx interrupt priority
-            (+++) Enable the NVIC I2C IRQ Channel
-        (##) DMA Configuration if you need to use DMA process
-            (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
-            (+++) Enable the DMAx interface clock using
-            (+++) Configure the DMA handle parameters
-            (+++) Configure the DMA Tx or Rx Channel
-            (+++) Associate the initilalized DMA handle to the hi2c DMA Tx or Rx handle
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on 
-                  the DMA Tx or Rx Channel
-
-    (#) Configure the Communication Speed, Duty cycle, Addressing mode, Own Address1,
-        Dual Addressing mode, Own Address2, General call and Nostretch mode in the hi2c Init structure.
-
-    (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware 
-        (GPIO, CLOCK, NVIC...etc) by calling the customed HAL_I2C_MspInit(&hi2c) API.
-
-    (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
-
-    (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
-
-    *** Polling mode IO operation ***
-    =================================
-    [..]
-      (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
-      (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
-      (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
-      (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
-
-    *** Polling mode IO MEM operation ***
-    =====================================
-    [..]
-      (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
-      (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
-
-
-    *** Interrupt mode IO operation ***
-    ===================================
-    [..]
-      (+) Transmit in master mode an amount of data in non blocking mode using HAL_I2C_Master_Transmit_IT()
-      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
-      (+) Receive in master mode an amount of data in non blocking mode using HAL_I2C_Master_Receive_IT()
-      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
-      (+) Transmit in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Transmit_IT()
-      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
-      (+) Receive in slave mode an amount of data in non blocking mode using HAL_I2C_Slave_Receive_IT()
-      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
-
-    *** Interrupt mode IO MEM operation ***
-    =======================================
-    [..]
-      (+) Write an amount of data in no-blocking mode with Interrupt to a specific memory address using
-          HAL_I2C_Mem_Write_IT()
-      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
-      (+) Read an amount of data in no-blocking mode with Interrupt from a specific memory address using
-          HAL_I2C_Mem_Read_IT()
-      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
-
-    *** DMA mode IO operation ***
-    ==============================
-    [..]
-      (+) Transmit in master mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Master_Transmit_DMA()
-      (+) At transmission end of transfer HAL_I2C_MasterTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback
-      (+) Receive in master mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Master_Receive_DMA()
-      (+) At reception end of transfer HAL_I2C_MasterRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback
-      (+) Transmit in slave mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Slave_Transmit_DMA()
-      (+) At transmission end of transfer HAL_I2C_SlaveTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback
-      (+) Receive in slave mode an amount of data in non blocking mode (DMA) using
-          HAL_I2C_Slave_Receive_DMA()
-      (+) At reception end of transfer HAL_I2C_SlaveRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
-
-    *** DMA mode IO MEM operation ***
-    =================================
-    [..]
-      (+) Write an amount of data in no-blocking mode with DMA to a specific memory address using
-          HAL_I2C_Mem_Write_DMA()
-      (+) At MEM end of write transfer HAL_I2C_MemTxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback
-      (+) Read an amount of data in no-blocking mode with DMA from a specific memory address using
-          HAL_I2C_Mem_Read_DMA()
-      (+) At MEM end of read transfer HAL_I2C_MemRxCpltCallback is executed and user can
-           add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback
-      (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
-           add his own code by customization of function pointer HAL_I2C_ErrorCallback
-
-
-     *** I2C HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in I2C HAL driver.
-
-      (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
-      (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
-      (+) __HAL_I2C_GET_FLAG : Checks whether the specified I2C flag is set or not
-      (+) __HAL_I2C_CLEAR_FLAG : Clear the specified I2C pending flag
-      (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
-      (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
-
-     [..]
-       (@) You can refer to the I2C HAL driver header file for more useful macros
-
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2C I2C
-  * @brief I2C HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2C_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup I2C_Private_Constants I2C Private Constants
-  * @{
-  */
-#define I2C_TIMEOUT_FLAG          ((uint32_t)35)      /* 35 ms */
-#define I2C_TIMEOUT_ADDR_SLAVE    ((uint32_t)10000)   /* 10 s  */
-
-#define I2C_MIN_PCLK_FREQ         ((uint32_t)2000000) /* 2 MHz*/
-/**
-  * @}
-  */
-
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup I2C_Private_Functions I2C Private Functions
-  * @{
-  */
-
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma);
-static void I2C_DMAError(DMA_HandleTypeDef *hdma);
-
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout);
-
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c);
-
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c);
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Functions I2C Exported Functions
-  * @{
-  */
-
-/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- *  @brief    Initialization and Configuration functions
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and
-          de-initialiaze the I2Cx peripheral:
-
-      (+) User must Implement HAL_I2C_MspInit() function in which he configures
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC).
-
-      (+) Call the function HAL_I2C_Init() to configure the selected device with
-          the selected configuration:
-        (++) Communication Speed
-        (++) Duty cycle
-        (++) Addressing mode
-        (++) Own Address 1
-        (++) Dual Addressing mode
-        (++) Own Address 2
-        (++) General call mode
-        (++) Nostretch mode
-
-      (+) Call the function HAL_I2C_DeInit() to restore the default configuration
-          of the selected I2Cx periperal.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the I2C according to the specified parameters
-  *         in the I2C_InitTypeDef and create the associated handle.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t freqrange = 0;
-  uint32_t pclk1 = 0;
-
-  /* Check the I2C handle allocation */
-  if(hi2c == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-  assert_param(IS_I2C_CLOCK_SPEED(hi2c->Init.ClockSpeed));
-  assert_param(IS_I2C_DUTY_CYCLE(hi2c->Init.DutyCycle));
-  assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
-  assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
-  assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
-  assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
-  assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
-  assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
-
-  if(hi2c->State == HAL_I2C_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_I2C_MspInit(hi2c);
-  }
-
-  /* Get PCLK1 frequency */
-  pclk1 = HAL_RCC_GetPCLK1Freq();
-
-  /* The minimum allowed frequency is 2 MHz */
-  if(pclk1 < I2C_MIN_PCLK_FREQ)
-  {
-    return HAL_ERROR;
-  }
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disble the selected I2C peripheral */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /* Calculate frequency range */
-  freqrange = I2C_FREQRANGE(pclk1);
-
-  /*---------------------------- I2Cx CR2 Configuration ----------------------*/
-  /* Configure I2Cx: Frequency range */
-  MODIFY_REG(hi2c->Instance->CR2, I2C_CR2_FREQ, freqrange);
-
-  /*---------------------------- I2Cx TRISE Configuration --------------------*/
-  /* Configure I2Cx: Rise Time */
-  MODIFY_REG(hi2c->Instance->TRISE, I2C_TRISE_TRISE, I2C_RISE_TIME(freqrange, hi2c->Init.ClockSpeed));
-
-  /*---------------------------- I2Cx CCR Configuration ----------------------*/
-  /* Configure I2Cx: Speed */
-  MODIFY_REG(hi2c->Instance->CCR, (I2C_CCR_FS | I2C_CCR_DUTY | I2C_CCR_CCR), I2C_SPEED(pclk1, hi2c->Init.ClockSpeed, hi2c->Init.DutyCycle));
-
-  /*---------------------------- I2Cx CR1 Configuration ----------------------*/
-  /* Configure I2Cx: Generalcall and NoStretch mode */
-  MODIFY_REG(hi2c->Instance->CR1, (I2C_CR1_ENGC | I2C_CR1_NOSTRETCH), (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode));
-
-  /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
-  /* Configure I2Cx: Own Address1 and addressing mode */
-  MODIFY_REG(hi2c->Instance->OAR1, (I2C_OAR1_ADDMODE | I2C_OAR1_ADD8_9 | I2C_OAR1_ADD1_7 | I2C_OAR1_ADD0), (hi2c->Init.AddressingMode | hi2c->Init.OwnAddress1));
-
-  /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
-  /* Configure I2Cx: Dual mode and Own Address2 */
-  MODIFY_REG(hi2c->Instance->OAR2, (I2C_OAR2_ENDUAL | I2C_OAR2_ADD2), (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2));
-
-  /* Enable the selected I2C peripheral */
-  __HAL_I2C_ENABLE(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the I2C peripheral.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* Check the I2C handle allocation */
-  if(hi2c == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
-
-  hi2c->State = HAL_I2C_STATE_BUSY;
-
-  /* Disable the I2C Peripheral Clock */
-  __HAL_I2C_DISABLE(hi2c);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_I2C_MspDeInit(hi2c);
-
-  hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-  hi2c->State = HAL_I2C_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief I2C MSP Init.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
- __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief I2C MSP DeInit
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
- __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2C_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2C data
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode.
-            The status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode : The communication is performed using Interrupts
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the
-            dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2C_Master_Transmit()
-        (++) HAL_I2C_Master_Receive()
-        (++) HAL_I2C_Slave_Transmit()
-        (++) HAL_I2C_Slave_Receive()
-        (++) HAL_I2C_Mem_Write()
-        (++) HAL_I2C_Mem_Read()
-        (++) HAL_I2C_IsDeviceReady()
-
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2C_Master_Transmit_IT()
-        (++) HAL_I2C_Master_Receive_IT()
-        (++) HAL_I2C_Slave_Transmit_IT()
-        (++) HAL_I2C_Slave_Receive_IT()
-        (++) HAL_I2C_Mem_Write_IT()
-        (++) HAL_I2C_Mem_Read_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2C_Master_Transmit_DMA()
-        (++) HAL_I2C_Master_Receive_DMA()
-        (++) HAL_I2C_Slave_Transmit_DMA()
-        (++) HAL_I2C_Slave_Receive_DMA()
-        (++) HAL_I2C_Mem_Write_DMA()
-        (++) HAL_I2C_Mem_Read_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2C_MemTxCpltCallback()
-        (++) HAL_I2C_MemRxCpltCallback()
-        (++) HAL_I2C_MasterTxCpltCallback()
-        (++) HAL_I2C_MasterRxCpltCallback()
-        (++) HAL_I2C_SlaveTxCpltCallback()
-        (++) HAL_I2C_SlaveRxCpltCallback()
-        (++) HAL_I2C_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits in master mode an amount of data in blocking mode.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, Timeout) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    while(Size > 0)
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = (*pData++);
-      Size--;
-
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = (*pData++);
-        Size--;
-      }
-    }
-
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Generate Stop */
-    SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives in master mode an amount of data in blocking mode.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, Timeout) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(Size == 1)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_STOP);
-    }
-    else if(Size == 2)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Enable Pos */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while(Size > 0)
-    {
-      if(Size <= 3)
-      {
-        /* One byte */
-        if(Size == 1)
-        {
-          /* Wait until RXNE flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-        }
-        /* Two bytes */
-        else if(Size == 2)
-        {
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-        }
-        /* 3 Last bytes */
-        else
-        {
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-        }
-      }
-      else
-      {
-        /* Wait until RXNE flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        /* Read data from DR */
-        (*pData++) = hi2c->Instance->DR;
-        Size--;
-
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
-        {
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-        }
-      }
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmits in slave mode an amount of data in blocking mode.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* If 10bit addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
-    {
-      /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while(Size > 0)
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = (*pData++);
-      Size--;
-
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = (*pData++);
-        Size--;
-      }
-    }
-
-    /* Wait until AF flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear AF flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-    /* Disable Address Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in blocking mode
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    while(Size > 0)
-    {
-      /* Wait until RXNE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Read data from DR */
-      (*pData++) = hi2c->Instance->DR;
-      Size--;
-
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
-      {
-        /* Read data from DR */
-        (*pData++) = hi2c->Instance->DR;
-        Size--;
-      }
-    }
-
-    /* Wait until STOP flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
-    /* Disable Address Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in no-blocking mode with Interrupt
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in no-blocking mode with Interrupt
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(hi2c->XferCount == 1)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-    }
-    else if(hi2c->XferCount == 2)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Enable Pos */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in no-blocking mode with Interrupt
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in no-blocking mode with Interrupt
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in master mode an amount of data in no-blocking mode with DMA
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Set the I2C DMA transfert complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA Channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestWrite(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Enable DMA Request */
-    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in master mode an amount of data in no-blocking mode with DMA
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Set the I2C DMA transfert complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA Channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-
-    /* Send Slave Address */
-    if(I2C_MasterRequestRead(hi2c, DevAddress, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(Size == 1)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-    }
-    else
-    {
-      /* Enable Last DMA bit */
-      SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-    }
-
-    /* Enable DMA Request */
-    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit in slave mode an amount of data in no-blocking mode with DMA
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Set the I2C DMA transfert complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA Channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
-
-    /* Enable DMA Request */
-    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* If 7bit addressing mode is selected */
-    if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Wait until ADDR flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive in slave mode an amount of data in no-blocking mode with DMA
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
-{
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Set the I2C DMA transfert complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA Channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-
-    /* Enable DMA Request */
-    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-    /* Enable Address Acknowledge */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, I2C_TIMEOUT_ADDR_SLAVE) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in blocking mode to a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    while(Size > 0)
-    {
-      /* Wait until TXE flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Write data to DR */
-      hi2c->Instance->DR = (*pData++);
-      Size--;
-
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (Size != 0))
-      {
-        /* Write data to DR */
-        hi2c->Instance->DR = (*pData++);
-        Size--;
-      }
-    }
-
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Generate Stop */
-    SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in blocking mode from a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(Size == 1)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-    }
-    else if(Size == 2)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Enable Pos */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    while(Size > 0)
-    {
-      if(Size <= 3)
-      {
-        /* One byte */
-        if(Size== 1)
-        {
-          /* Wait until RXNE flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-        }
-        /* Two bytes */
-        else if(Size == 2)
-        {
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-        }
-        /* 3 Last bytes */
-        else
-        {
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Disable Acknowledge */
-          CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-
-          /* Wait until BTF flag is set */
-          if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          /* Generate Stop */
-          SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-        }
-      }
-      else
-      {
-        /* Wait until RXNE flag is set */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        /* Read data from DR */
-        (*pData++) = hi2c->Instance->DR;
-        Size--;
-
-        if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET)
-        {
-          /* Read data from DR */
-          (*pData++) = hi2c->Instance->DR;
-          Size--;
-        }
-      }
-    }
-
-    /* Disable Pos */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in no-blocking mode with Interrupt to a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Read an amount of data in no-blocking mode with Interrupt from a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(hi2c->XferCount == 1)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-    }
-    else if(hi2c->XferCount == 2)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Enable Pos */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_POS);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-    else
-    {
-      /* Enable Acknowledge */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-      /* Clear ADDR flag */
-      __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    /* Note : The I2C interrupts must be enabled after unlocking current process
-              to avoid the risk of I2C interrupt handle execution before current
-              process unlock */
-
-    /* Enable EVT, BUF and ERR interrupt */
-    __HAL_I2C_ENABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-/**
-  * @brief  Write an amount of data in no-blocking mode with DMA to a specific memory address
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_TX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Set the I2C DMA transfert complete callback */
-    hi2c->hdmatx->XferCpltCallback = I2C_DMAMemTransmitCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA Channel */
-    HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->DR, Size);
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Enable DMA Request */
-    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Reads an amount of data in no-blocking mode with DMA from a specific memory address.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be read
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
-{
-  /* Check the parameters */
-  assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_MEM_BUSY_RX;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    hi2c->pBuffPtr = pData;
-    hi2c->XferSize = Size;
-    hi2c->XferCount = Size;
-
-    /* Set the I2C DMA transfert complete callback */
-    hi2c->hdmarx->XferCpltCallback = I2C_DMAMemReceiveCplt;
-
-    /* Set the DMA error callback */
-    hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
-
-    /* Enable the DMA Channel */
-    HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->DR, (uint32_t)pData, Size);
-
-    /* Send Slave Address and Memory Address */
-    if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    if(Size == 1)
-    {
-      /* Disable Acknowledge */
-      CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-    }
-    else
-    {
-      /* Enable Last DMA bit */
-      SET_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-    }
-
-    /* Enable DMA Request */
-    SET_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Checks if target device is ready for communication.
-  * @note   This function is used with Memory devices
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  Trials: Number of trials
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
-  uint32_t tickstart = 0, I2C_Trials = 1;
-
-  if(hi2c->State == HAL_I2C_STATE_READY)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
-    {
-      return HAL_BUSY;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hi2c);
-
-    hi2c->State = HAL_I2C_STATE_BUSY;
-    hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
-    do
-    {
-      /* Generate Start */
-      SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-      /* Wait until SB flag is set */
-      if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-
-      /* Send slave address */
-      hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-      /* Wait until ADDR or AF flag are set */
-      /* Get tick */
-      tickstart = HAL_GetTick();
-
-      while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == RESET) && \
-            (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && \
-            (hi2c->State != HAL_I2C_STATE_TIMEOUT))
-      {
-        if(Timeout != HAL_MAX_DELAY)
-        {
-          if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-          {
-            hi2c->State = HAL_I2C_STATE_TIMEOUT;
-          }
-        }
-      }
-
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      /* Check if the ADDR flag has been set */
-      if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET)
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-        /* Clear ADDR Flag */
-        __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-        /* Wait until BUSY flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        hi2c->State = HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_OK;
-      }
-      else
-      {
-        /* Generate Stop */
-        SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-        /* Clear AF Flag */
-        __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-        /* Wait until BUSY flag is reset */
-        if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }while(I2C_Trials++ < Trials);
-
-    hi2c->State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2c);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  This function handles I2C event interrupt request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-  /* Master mode selected */
-  if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == SET)
-  {
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET)
-    {
-      /* TXE set and BTF reset -----------------------------------------------*/
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == SET) && \
-         (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \
-         (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
-      {
-        I2C_MasterTransmit_TXE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && \
-              (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET))
-      {
-        I2C_MasterTransmit_BTF(hi2c);
-      }
-    }
-    /* I2C in mode Receiver --------------------------------------------------*/
-    else
-    {
-      /* RXNE set and BTF reset -----------------------------------------------*/
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && \
-         (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \
-         (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
-      {
-        I2C_MasterReceive_RXNE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET))
-      {
-        I2C_MasterReceive_BTF(hi2c);
-      }
-    }
-  }
-  /* Slave mode selected */
-  else
-  {
-    /* ADDR set --------------------------------------------------------------*/
-    if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ADDR) == SET) && \
-       (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT)) == SET))
-    {
-      I2C_Slave_ADDR(hi2c);
-    }
-    /* STOPF set --------------------------------------------------------------*/
-    else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET) && \
-            (__HAL_I2C_GET_IT_SOURCE(hi2c, (I2C_IT_EVT)) == SET))
-    {
-      I2C_Slave_STOPF(hi2c);
-    }
-    /* I2C in mode Transmitter -----------------------------------------------*/
-    else if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TRA) == SET)
-    {
-      /* TXE set and BTF reset -----------------------------------------------*/
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == SET) && \
-         (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \
-         (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
-      {
-        I2C_SlaveTransmit_TXE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && \
-              (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET))
-      {
-        I2C_SlaveTransmit_BTF(hi2c);
-      }
-    }
-    /* I2C in mode Receiver --------------------------------------------------*/
-    else
-    {
-      /* RXNE set and BTF reset ----------------------------------------------*/
-      if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && \
-         (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_BUF) == SET) && \
-         (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == RESET))
-      {
-        I2C_SlaveReceive_RXNE(hi2c);
-      }
-      /* BTF set -------------------------------------------------------------*/
-      else if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BTF) == SET) && (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_EVT) == SET))
-      {
-        I2C_SlaveReceive_BTF(hi2c);
-      }
-    }
-  }
-}
-
-/**
-  * @brief  This function handles I2C error interrupt request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
-{
-
-  /* I2C Bus error interrupt occurred ----------------------------------------*/
-  if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BERR) == SET) && \
-     (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
-
-    /* Clear BERR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
-  }
-
-  /* I2C Arbitration Loss error interrupt occurred ---------------------------*/
-  if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_ARLO) == SET) && \
-     (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
-
-    /* Clear ARLO flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
-  }
-
-  /* I2C Acknowledge failure error interrupt occurred ------------------------*/
-  if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET) && \
-     (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET))
-  {
-    if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_MSL) == RESET) && \
-       (hi2c->XferCount == 0) && \
-       (hi2c->State == HAL_I2C_STATE_BUSY_TX))
-    {
-      I2C_Slave_AF(hi2c);
-    }
-    else
-    {
-      hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-      /* Clear AF flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-    }
-  }
-
-  /* I2C Over-Run/Under-Run interrupt occurred -------------------------------*/
-  if((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_OVR) == SET) && \
-     (__HAL_I2C_GET_IT_SOURCE(hi2c, I2C_IT_ERR) == SET))
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
-    /* Clear OVR flag */
-    __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
-  }
-
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    hi2c->State = HAL_I2C_STATE_READY;
-    
-    /* Disable EVT, BUF and ERR interrupts */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  Master Tx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
- __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterTxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Master Rx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-__weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MasterRxCpltCallback can be implemented in the user file
-   */
-}
-
-/** @brief  Slave Tx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
- __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveTxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Slave Rx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-__weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_SlaveRxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Tx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
- __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemTxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Memory Rx Transfer completed callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
-__weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_MemRxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  I2C error callbacks.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval None
-  */
- __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_I2C_ErrorCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Exported_Functions_Group3 Peripheral State and Errors functions
- *  @brief   Peripheral State and Errors functions
- *
-@verbatim
- ===============================================================================
-            ##### Peripheral State and Errors functions #####
- ===============================================================================
-    [..]
-    This subsection permits to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the I2C state.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL state
-  */
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->State;
-}
-
-/**
-  * @brief  Return the I2C error code
-  * @param  hi2c : pointer to a I2C_HandleTypeDef structure that contains
-  *              the configuration information for the specified I2C.
-* @retval I2C Error Code
-*/
-uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
-{
-  return hi2c->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup I2C_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  Handle TXE flag for Master
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterTransmit_TXE(I2C_HandleTypeDef *hi2c)
-{
-  /* Write data to DR */
-  hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-  hi2c->XferCount--;
-
-  if(hi2c->XferCount == 0)
-  {
-    /* Disable BUF interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Master transmitter
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
-  }
-  else
-  {
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Generate Stop */
-    SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_TX)
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MemTxCpltCallback(hi2c);
-    }
-    else
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MasterTxCpltCallback(hi2c);
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle RXNE flag for Master
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
-  uint32_t tmp = 0;
-
-  tmp = hi2c->XferCount;
-  if(tmp > 3)
-  {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  else if((tmp == 2) || (tmp == 3))
-  {
-    /* Disable BUF interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_BUF);
-  }
-  else
-  {
-    /* Disable EVT, BUF and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MemRxCpltCallback(hi2c);
-    }
-    else
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MasterRxCpltCallback(hi2c);
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Master receiver
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount == 3)
-  {
-    /* Disable Acknowledge */
-    CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  else if(hi2c->XferCount == 2)
-  {
-    /* Generate Stop */
-    SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-
-    /* Disable EVT and ERR interrupt */
-    __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_ERR);
-
-    /* Wait until BUSY flag is reset */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    if(hi2c->State == HAL_I2C_STATE_MEM_BUSY_RX)
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MemRxCpltCallback(hi2c);
-    }
-    else
-    {
-      hi2c->State = HAL_I2C_STATE_READY;
-
-      HAL_I2C_MasterRxCpltCallback(hi2c);
-    }
-  }
-  else
-  {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle TXE flag for Slave
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveTransmit_TXE(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Slave transmitter
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveTransmit_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0)
-  {
-    /* Write data to DR */
-    hi2c->Instance->DR = (*hi2c->pBuffPtr++);
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle RXNE flag for Slave
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveReceive_RXNE(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0)
-  {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle BTF flag for Slave receiver
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_SlaveReceive_BTF(I2C_HandleTypeDef *hi2c)
-{
-  if(hi2c->XferCount != 0)
-  {
-    /* Read data from DR */
-    (*hi2c->pBuffPtr++) = hi2c->Instance->DR;
-    hi2c->XferCount--;
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle ADD flag for Slave
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_ADDR(I2C_HandleTypeDef *hi2c)
-{
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handle STOPF flag for Slave
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_STOPF(I2C_HandleTypeDef *hi2c)
-{
-  /* Disable EVT, BUF and ERR interrupt */
-  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-  /* Clear STOPF flag */
-  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
-  /* Disable Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  HAL_I2C_SlaveRxCpltCallback(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_Slave_AF(I2C_HandleTypeDef *hi2c)
-{
-  /* Disable EVT, BUF and ERR interrupt */
-  __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
-
-  /* Clear AF flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-  /* Disable Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  HAL_I2C_SlaveTxCpltCallback(hi2c);
-
-  return HAL_OK;
-}
-
-/**
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterRequestWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
-{
-  /* Generate Start */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-  {
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-  }
-  else
-  {
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
-
-    /* Wait until ADD10 flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
-  }
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address for read request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_MasterRequestRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Timeout)
-{
-  /* Enable Acknowledge */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Generate Start */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
-  {
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
-  }
-  else
-  {
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_WRITE(DevAddress);
-
-    /* Wait until ADD10 flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADD10, Timeout) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Send slave address */
-    hi2c->Instance->DR = I2C_10BIT_ADDRESS(DevAddress);
-
-    /* Wait until ADDR flag is set */
-    if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
-    {
-      if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-      {
-        return HAL_ERROR;
-      }
-      else
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Clear ADDR flag */
-    __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-    /* Generate Restart */
-    SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-    /* Wait until SB flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Send header of slave address */
-    hi2c->Instance->DR = I2C_10BIT_HEADER_READ(DevAddress);
-  }
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for write request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
-{
-  /* Generate Start */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-  /* Wait until TXE flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Master sends target device address followed by internal memory address for read request.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  DevAddress: Target device address
-  * @param  MemAddress: Internal memory address
-  * @param  MemAddSize: Size of internal memory address
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout)
-{
-  /* Enable Acknowledge */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Generate Start */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_WRITE(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Clear ADDR flag */
-  __HAL_I2C_CLEAR_ADDRFLAG(hi2c);
-
-  /* Wait until TXE flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* If Memory address size is 8Bit */
-  if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
-  {
-    /* Send Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-  /* If Memory address size is 16Bit */
-  else
-  {
-    /* Send MSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_MSB(MemAddress);
-
-    /* Wait until TXE flag is set */
-    if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Send LSB of Memory Address */
-    hi2c->Instance->DR = I2C_MEM_ADD_LSB(MemAddress);
-  }
-
-  /* Wait until TXE flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TXE, RESET, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Generate Restart */
-  SET_BIT(hi2c->Instance->CR1, I2C_CR1_START);
-
-  /* Wait until SB flag is set */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_SB, RESET, Timeout) != HAL_OK)
-  {
-    return HAL_TIMEOUT;
-  }
-
-  /* Send slave address */
-  hi2c->Instance->DR = I2C_7BIT_ADD_READ(DevAddress);
-
-  /* Wait until ADDR flag is set */
-  if(I2C_WaitOnMasterAddressFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, Timeout) != HAL_OK)
-  {
-    if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DMA I2C master transmit process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until BTF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Generate Stop */
-  SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-  /* Disable DMA Request */
-  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-  hi2c->XferCount = 0;
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MasterTxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C slave transmit process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until AF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_AF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Clear AF flag */
-  __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-  /* Disable Address Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Disable DMA Request */
-  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-  hi2c->XferCount = 0;
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_SlaveTxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C master receive process complete callback
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Generate Stop */
-  SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-  /* Disable Last DMA */
-  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-
-  /* Disable Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Disable DMA Request */
-  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-  hi2c->XferCount = 0;
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MasterRxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C slave receive process complete callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until STOPF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Clear STOPF flag */
-  __HAL_I2C_CLEAR_STOPFLAG(hi2c);
-
-  /* Disable Address Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Disable DMA Request */
-  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-  hi2c->XferCount = 0;
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_SlaveRxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C Memory Write process complete callback
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMAMemTransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Wait until BTF flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BTF, RESET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  /* Generate Stop */
-  SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-  /* Disable DMA Request */
-  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-  hi2c->XferCount = 0;
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MemTxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C Memory Read process complete callback
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMAMemReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Generate Stop */
-  SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-  /* Disable Last DMA */
-  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_LAST);
-
-  /* Disable Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  /* Disable DMA Request */
-  CLEAR_BIT(hi2c->Instance->CR2, I2C_CR2_DMAEN);
-
-  hi2c->XferCount = 0;
-
-  /* Wait until BUSY flag is reset */
-  if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_FLAG) != HAL_OK)
-  {
-    hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
-  }
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  /* Check if Errors has been detected during transfer */
-  if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
-  {
-    HAL_I2C_ErrorCallback(hi2c);
-  }
-  else
-  {
-    HAL_I2C_MemRxCpltCallback(hi2c);
-  }
-}
-
-/**
-  * @brief  DMA I2C communication error callback.
-  * @param  hdma: DMA handle
-  * @retval None
-  */
-static void I2C_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Disable Acknowledge */
-  CLEAR_BIT(hi2c->Instance->CR1, I2C_CR1_ACK);
-
-  hi2c->XferCount = 0;
-
-  hi2c->State = HAL_I2C_STATE_READY;
-
-  hi2c->ErrorCode |= HAL_I2C_ERROR_DMA;
-
-  HAL_I2C_ErrorCallback(hi2c);
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  Flag: specifies the I2C flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          hi2c->State= HAL_I2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_I2C_GET_FLAG(hi2c, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          hi2c->State= HAL_I2C_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2c);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2C Communication Timeout for Master addressing phase.
-  * @param  hi2c: pointer to a I2C_HandleTypeDef structure that contains
-  *         the configuration information for I2C module
-  * @param  Flag: specifies the I2C flag to check.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2C_WaitOnMasterAddressFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  while(__HAL_I2C_GET_FLAG(hi2c, Flag) == RESET)
-  {
-    if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
-    {
-      /* Generate Stop */
-      SET_BIT(hi2c->Instance->CR1,I2C_CR1_STOP);
-
-      /* Clear AF Flag */
-      __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
-      hi2c->ErrorCode = HAL_I2C_ERROR_AF;
-      hi2c->State= HAL_I2C_STATE_READY;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hi2c);
-
-      return HAL_ERROR;
-    }
-
-    /* Check for the Timeout */
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hi2c->State= HAL_I2C_STATE_READY;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hi2c);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_I2C_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2c.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,538 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_i2c.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of I2C HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_I2C_H
-#define __STM32L1xx_HAL_I2C_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2C
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Types I2C Exported Types
-  * @{
-  */
-
-/**
-  * @brief  I2C Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSpeed;       /*!< Specifies the clock frequency.
-                                  This parameter must be set to a value lower than 400kHz */
-
-  uint32_t DutyCycle;        /*!< Specifies the I2C fast mode duty cycle.
-                                  This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
-
-  uint32_t OwnAddress1;      /*!< Specifies the first device own address.
-                                  This parameter can be a 7-bit or 10-bit address. */
-
-  uint32_t AddressingMode;   /*!< Specifies if 7-bit or 10-bit addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_addressing_mode */
-
-  uint32_t DualAddressMode;  /*!< Specifies if dual addressing mode is selected.
-                                  This parameter can be a value of @ref I2C_dual_addressing_mode */
-
-  uint32_t OwnAddress2;      /*!< Specifies the second device own address if dual addressing mode is selected
-                                  This parameter can be a 7-bit address. */
-
-  uint32_t GeneralCallMode;  /*!< Specifies if general call mode is selected.
-                                  This parameter can be a value of @ref I2C_general_call_addressing_mode */
-
-  uint32_t NoStretchMode;    /*!< Specifies if nostretch mode is selected.
-                                  This parameter can be a value of @ref I2C_nostretch_mode */
-
-}I2C_InitTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_I2C_STATE_RESET             = 0x00,  /*!< I2C not yet initialized or disabled         */
-  HAL_I2C_STATE_READY             = 0x01,  /*!< I2C initialized and ready for use           */
-  HAL_I2C_STATE_BUSY              = 0x02,  /*!< I2C internal process is ongoing             */
-  HAL_I2C_STATE_BUSY_TX           = 0x12,  /*!< Data Transmission process is ongoing        */
-  HAL_I2C_STATE_BUSY_RX           = 0x22,  /*!< Data Reception process is ongoing           */
-  HAL_I2C_STATE_MEM_BUSY_TX       = 0x32,  /*!< Memory Data Transmission process is ongoing */
-  HAL_I2C_STATE_MEM_BUSY_RX       = 0x42,  /*!< Memory Data Reception process is ongoing    */
-  HAL_I2C_STATE_TIMEOUT           = 0x03,  /*!< I2C timeout state                           */
-  HAL_I2C_STATE_ERROR             = 0x04   /*!< I2C error state                             */
-
-}HAL_I2C_StateTypeDef;
-
-/**
-  * @brief  HAL I2C Error Code structure definition
-  */
-typedef enum
-{
-  HAL_I2C_ERROR_NONE      = 0x00,    /*!< No error             */
-  HAL_I2C_ERROR_BERR      = 0x01,    /*!< BERR error           */
-  HAL_I2C_ERROR_ARLO      = 0x02,    /*!< ARLO error           */
-  HAL_I2C_ERROR_AF        = 0x04,    /*!< AF error             */
-  HAL_I2C_ERROR_OVR       = 0x08,    /*!< OVR error            */
-  HAL_I2C_ERROR_DMA       = 0x10,    /*!< DMA transfer error   */
-  HAL_I2C_ERROR_TIMEOUT   = 0x20     /*!< Timeout error        */
-
-}HAL_I2C_ErrorTypeDef;
-
-/**
-  * @brief  I2C handle Structure definition
-  */
-typedef struct
-{
-  I2C_TypeDef                *Instance;  /*!< I2C registers base address     */
-
-  I2C_InitTypeDef            Init;       /*!< I2C communication parameters   */
-
-  uint8_t                    *pBuffPtr;  /*!< Pointer to I2C transfer buffer */
-
-  uint16_t                   XferSize;   /*!< I2C transfer size              */
-
-  __IO uint16_t              XferCount;  /*!< I2C transfer counter           */
-
-  DMA_HandleTypeDef          *hdmatx;    /*!< I2C Tx DMA handle parameters   */
-
-  DMA_HandleTypeDef          *hdmarx;    /*!< I2C Rx DMA handle parameters   */
-
-  HAL_LockTypeDef            Lock;       /*!< I2C locking object             */
-
-  __IO HAL_I2C_StateTypeDef  State;      /*!< I2C communication state        */
-
-  __IO HAL_I2C_ErrorTypeDef  ErrorCode;         /* I2C Error code                 */
-
-}I2C_HandleTypeDef;
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup I2C_Exported_Constants I2C Exported Constants
-  * @{
-  */
-
-/** @defgroup I2C_duty_cycle_in_fast_mode I2C_duty_cycle_in_fast_mode
-  * @{
-  */
-#define I2C_DUTYCYCLE_2                 ((uint32_t)0x00000000)
-#define I2C_DUTYCYCLE_16_9              I2C_CCR_DUTY
-
-#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DUTYCYCLE_2) || \
-                                  ((CYCLE) == I2C_DUTYCYCLE_16_9))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_addressing_mode I2C_addressing_mode
-  * @{
-  */
-#define I2C_ADDRESSINGMODE_7BIT         ((uint32_t)0x00004000)
-#define I2C_ADDRESSINGMODE_10BIT        (I2C_OAR1_ADDMODE | ((uint32_t)0x00004000))
-
-#define IS_I2C_ADDRESSING_MODE(ADDRESS) (((ADDRESS) == I2C_ADDRESSINGMODE_7BIT) || \
-                                         ((ADDRESS) == I2C_ADDRESSINGMODE_10BIT))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_dual_addressing_mode I2C_dual_addressing_mode
-  * @{
-  */
-#define I2C_DUALADDRESS_DISABLED        ((uint32_t)0x00000000)
-#define I2C_DUALADDRESS_ENABLED         I2C_OAR2_ENDUAL
-
-#define IS_I2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == I2C_DUALADDRESS_DISABLED) || \
-                                      ((ADDRESS) == I2C_DUALADDRESS_ENABLED))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_general_call_addressing_mode I2C_general_call_addressing_mode
-  * @{
-  */
-#define I2C_GENERALCALL_DISABLED        ((uint32_t)0x00000000)
-#define I2C_GENERALCALL_ENABLED         I2C_CR1_ENGC
-
-#define IS_I2C_GENERAL_CALL(CALL) (((CALL) == I2C_GENERALCALL_DISABLED) || \
-                                   ((CALL) == I2C_GENERALCALL_ENABLED))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_nostretch_mode I2C_nostretch_mode
-  * @{
-  */
-#define I2C_NOSTRETCH_DISABLED          ((uint32_t)0x00000000)
-#define I2C_NOSTRETCH_ENABLED           I2C_CR1_NOSTRETCH
-
-#define IS_I2C_NO_STRETCH(STRETCH) (((STRETCH) == I2C_NOSTRETCH_DISABLED) || \
-                                    ((STRETCH) == I2C_NOSTRETCH_ENABLED))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Memory_Address_Size I2C_Memory_Address_Size
-  * @{
-  */
-#define I2C_MEMADD_SIZE_8BIT            ((uint32_t)0x00000001)
-#define I2C_MEMADD_SIZE_16BIT           ((uint32_t)0x00000010)
-
-#define IS_I2C_MEMADD_SIZE(SIZE) (((SIZE) == I2C_MEMADD_SIZE_8BIT) || \
-                                  ((SIZE) == I2C_MEMADD_SIZE_16BIT))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Interrupt_configuration_definition I2C_Interrupt_configuration_definition
-  * @{
-  */
-#define I2C_IT_BUF                      I2C_CR2_ITBUFEN
-#define I2C_IT_EVT                      I2C_CR2_ITEVTEN
-#define I2C_IT_ERR                      I2C_CR2_ITERREN
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Flag_definition I2C_Flag_definition
-  * @{
-  */
-#define I2C_FLAG_OVR                    ((uint32_t)(1 << 16 | I2C_SR1_OVR))
-#define I2C_FLAG_AF                     ((uint32_t)(1 << 16 | I2C_SR1_AF))
-#define I2C_FLAG_ARLO                   ((uint32_t)(1 << 16 | I2C_SR1_ARLO))
-#define I2C_FLAG_BERR                   ((uint32_t)(1 << 16 | I2C_SR1_BERR))
-#define I2C_FLAG_TXE                    ((uint32_t)(1 << 16 | I2C_SR1_TXE))
-#define I2C_FLAG_RXNE                   ((uint32_t)(1 << 16 | I2C_SR1_RXNE))
-#define I2C_FLAG_STOPF                  ((uint32_t)(1 << 16 | I2C_SR1_STOPF))
-#define I2C_FLAG_ADD10                  ((uint32_t)(1 << 16 | I2C_SR1_ADD10))
-#define I2C_FLAG_BTF                    ((uint32_t)(1 << 16 | I2C_SR1_BTF))
-#define I2C_FLAG_ADDR                   ((uint32_t)(1 << 16 | I2C_SR1_ADDR))
-#define I2C_FLAG_SB                     ((uint32_t)(1 << 16 | I2C_SR1_SB))
-#define I2C_FLAG_DUALF                  ((uint32_t)(2 << 16 | I2C_SR2_DUALF))
-#define I2C_FLAG_GENCALL                ((uint32_t)(2 << 16 | I2C_SR2_GENCALL))
-#define I2C_FLAG_TRA                    ((uint32_t)(2 << 16 | I2C_SR2_TRA))
-#define I2C_FLAG_BUSY                   ((uint32_t)(2 << 16 | I2C_SR2_BUSY))
-#define I2C_FLAG_MSL                    ((uint32_t)(2 << 16 | I2C_SR2_MSL))
-
-
-#define I2C_FLAG_MASK  ((uint32_t)0x0000FFFF)
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Clock_Speed_definition I2C_Clock_Speed_definition
-  * @{
-  */
-#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) > 0) && ((SPEED) <= 400000))
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Own_Address1_definition I2C_Own_Address1_definition
-  * @{
-  */
-#define IS_I2C_OWN_ADDRESS1(ADDRESS1) (((ADDRESS1) & (uint32_t)(0xFFFFFC00)) == 0)
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Own_Address2_definition I2C_Own_Address2_definition
-  * @{
-  */
-#define IS_I2C_OWN_ADDRESS2(ADDRESS2) (((ADDRESS2) & (uint32_t)(0xFFFFFF01)) == 0)
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2C_Exported_Macros I2C Exported Macros
-  * @{
-  */
-
-/** @brief Reset I2C handle state
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
-
-/** @brief  Enable or disable the specified I2C interrupts.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2C_IT_BUF: Buffer interrupt enable
-  *            @arg I2C_IT_EVT: Event interrupt enable
-  *            @arg I2C_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-
-#define __HAL_I2C_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__))
-#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Checks if the specified I2C interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @param  __INTERRUPT__: specifies the I2C interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2C_IT_BUF: Buffer interrupt enable
-  *            @arg I2C_IT_EVT: Event interrupt enable
-  *            @arg I2C_IT_ERR: Error interrupt enable
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2C flag is set or not.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag
-  *            @arg I2C_FLAG_AF: Acknowledge failure flag
-  *            @arg I2C_FLAG_ARLO: Arbitration lost flag
-  *            @arg I2C_FLAG_BERR: Bus error flag
-  *            @arg I2C_FLAG_TXE: Data register empty flag
-  *            @arg I2C_FLAG_RXNE: Data register not empty flag
-  *            @arg I2C_FLAG_STOPF: Stop detection flag
-  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag
-  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
-  *            @arg I2C_FLAG_ADDR: Address sent flag
-  *                                Address matched flag
-  *            @arg I2C_FLAG_SB: Start bit flag
-  *            @arg I2C_FLAG_DUALF: Dual flag
-  *            @arg I2C_FLAG_GENCALL: General call header flag
-  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
-  *            @arg I2C_FLAG_BUSY: Bus busy flag
-  *            @arg I2C_FLAG_MSL: Master/Slave flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2C_GET_FLAG(__HANDLE__, __FLAG__) ((((uint8_t)((__FLAG__) >> 16)) == 0x01)?((((__HANDLE__)->Instance->SR1) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)): \
-                                                 ((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
-
-/** @brief  Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be any combination of the following values:
-  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
-  *            @arg I2C_FLAG_AF: Acknowledge failure flag
-  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
-  *            @arg I2C_FLAG_BERR: Bus error flag
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
-
-/** @brief  Clears the I2C ADDR pending flag.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @retval None
-  */
-
-#define __HAL_I2C_CLEAR_ADDRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
-                                                (__HANDLE__)->Instance->SR2;}while(0)
-
-/** @brief  Clears the I2C STOPF pending flag.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_CLEAR_STOPFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR1;\
-                                                SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE);}while(0)
-
-/** @brief  Enable the I2C peripheral.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_ENABLE(__HANDLE__)                             SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
-
-/** @brief  Disable the I2C peripheral.
-  * @param  __HANDLE__: specifies the I2C Handle.
-  *         This parameter can be I2Cx where x: 1 or 2  to select the I2C peripheral.
-  * @retval None
-  */
-#define __HAL_I2C_DISABLE(__HANDLE__)                            CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE)
-
-/**
-  * @}
-  */
-
-/** @defgroup I2C_Private_Macros I2C Private Macros
-  * @{
-  */
-
-#define I2C_FREQRANGE(__PCLK__)                            ((__PCLK__)/1000000)
-#define I2C_RISE_TIME(__FREQRANGE__, __SPEED__)            (((__SPEED__) <= 100000) ? ((__FREQRANGE__) + 1) : ((((__FREQRANGE__) * 300) / 1000) + 1))
-#define I2C_SPEED_STANDARD(__PCLK__, __SPEED__)            (((((__PCLK__)/((__SPEED__) << 1)) & I2C_CCR_CCR) < 4)? 4:((__PCLK__) / ((__SPEED__) << 1)))
-#define I2C_SPEED_FAST(__PCLK__, __SPEED__, __DUTYCYCLE__) (((__DUTYCYCLE__) == I2C_DUTYCYCLE_2)? ((__PCLK__) / ((__SPEED__) * 3)) : (((__PCLK__) / ((__SPEED__) * 25)) | I2C_DUTYCYCLE_16_9))
-#define I2C_SPEED(__PCLK__, __SPEED__, __DUTYCYCLE__)      (((__SPEED__) <= 100000)? (I2C_SPEED_STANDARD((__PCLK__), (__SPEED__))) : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__)) & I2C_CCR_CCR) == 0)? 1 : \
-                                                                  ((I2C_SPEED_FAST((__PCLK__), (__SPEED__), (__DUTYCYCLE__))) | I2C_CCR_FS))
-
-#define I2C_7BIT_ADD_WRITE(__ADDRESS__)                    ((uint8_t)((__ADDRESS__) & (~I2C_OAR1_ADD0)))
-#define I2C_7BIT_ADD_READ(__ADDRESS__)                     ((uint8_t)((__ADDRESS__) | I2C_OAR1_ADD0))
-
-#define I2C_10BIT_ADDRESS(__ADDRESS__)                     ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-#define I2C_10BIT_HEADER_WRITE(__ADDRESS__)                ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF0))))
-#define I2C_10BIT_HEADER_READ(__ADDRESS__)                 ((uint8_t)((uint16_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0x0300))) >> 7) | (uint16_t)(0xF1))))
-
-#define I2C_MEM_ADD_MSB(__ADDRESS__)                       ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8)))
-#define I2C_MEM_ADD_LSB(__ADDRESS__)                       ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
-
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2C_Exported_Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup I2C_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */
-
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup I2C_Exported_Functions_Group2
-  * @{
-  */
-
-/******* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
-
-/******* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-/******* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size);
-
-/******* I2C IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
-void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c);
-void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c);
-
-/**
-  * @}
-  */
-
-
-/* Peripheral Control and State functions  **************************************/
-/** @addtogroup I2C_Exported_Functions_Group3
-  * @{
-  */
-
-HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c);
-uint32_t             HAL_I2C_GetError(I2C_HandleTypeDef *hi2c);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_I2C_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1384 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_i2s.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   I2S HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Integrated Interchip Sound (I2S) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  @verbatim
- ===============================================================================
-                  ##### How to use this driver #####
- ===============================================================================
- [..]
-    The I2S HAL driver can be used as follow:
-    
-    (#) Declare a I2S_HandleTypeDef handle structure.
-    (#) Initialize the I2S low level resources by implement the HAL_I2S_MspInit() API:
-        (##) Enable the SPIx interface clock.                      
-        (##) I2S pins configuration:
-            (+++) Enable the clock for the I2S GPIOs.
-            (+++) Configure these I2S pins as alternate function.
-        (##) NVIC configuration if you need to use interrupt process (HAL_I2S_Transmit_IT()
-             and HAL_I2S_Receive_IT() APIs).
-            (+++) Configure the I2Sx interrupt priority.
-            (+++) Enable the NVIC I2S IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_I2S_Transmit_DMA()
-             and HAL_I2S_Receive_DMA() APIs:
-            (+++) Declare a DMA handle structure for the Tx/Rx Channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.                
-            (+++) Configure the DMA Tx/Rx Channel.
-            (+++) Associate the initilalized DMA handle to the I2S DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the 
-                  DMA Tx/Rx Channel.
-
-   (#) Program the Mode, Standard, Data Format, MCLK Output, Audio frequency and Polarity
-       using HAL_I2S_Init() function.
-
-   -@- The specific I2S interrupts (Transmission complete interrupt, 
-       RXNE interrupt and Error Interrupts) will be managed using the macros
-       __HAL_I2S_ENABLE_IT() and __HAL_I2S_DISABLE_IT() inside the transmit and receive process.
-   -@- Make sure that either:
-       (+@) External clock source is configured after setting correctly 
-            the define constant HSE_VALUE in the stm32l1xx_hal_conf.h file. 
-
-    (#) Three mode of operations are available within this driver :     
-
-   *** Polling mode IO operation ***
-   =================================
-   [..]    
-     (+) Send an amount of data in blocking mode using HAL_I2S_Transmit() 
-     (+) Receive an amount of data in blocking mode using HAL_I2S_Receive()
-   
-   *** Interrupt mode IO operation ***
-   ===================================
-   [..]    
-     (+) Send an amount of data in non blocking mode using HAL_I2S_Transmit_IT() 
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode using HAL_I2S_Receive_IT() 
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-
-   *** DMA mode IO operation ***
-   ==============================
-   [..] 
-     (+) Send an amount of data in non blocking mode (DMA) using HAL_I2S_Transmit_DMA() 
-     (+) At transmission end of half transfer HAL_I2S_TxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxHalfCpltCallback 
-     (+) At transmission end of transfer HAL_I2S_TxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_TxCpltCallback
-     (+) Receive an amount of data in non blocking mode (DMA) using HAL_I2S_Receive_DMA() 
-     (+) At reception end of half transfer HAL_I2S_RxHalfCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxHalfCpltCallback 
-     (+) At reception end of transfer HAL_I2S_RxCpltCallback is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_RxCpltCallback
-     (+) In case of transfer Error, HAL_I2S_ErrorCallback() function is executed and user can 
-         add his own code by customization of function pointer HAL_I2S_ErrorCallback
-     (+) Pause the DMA Transfer using HAL_I2S_DMAPause()
-     (+) Resume the DMA Transfer using HAL_I2S_DMAResume()
-     (+) Stop the DMA Transfer using HAL_I2S_DMAStop()
-
-   *** I2S HAL driver macros list ***
-   =============================================
-   [..]
-     Below the list of most used macros in USART HAL driver.
-       
-      (+) __HAL_I2S_ENABLE: Enable the specified SPI peripheral (in I2S mode) 
-      (+) __HAL_I2S_DISABLE: Disable the specified SPI peripheral (in I2S mode)
-      (+) __HAL_I2S_ENABLE_IT : Enable the specified I2S interrupts
-      (+) __HAL_I2S_DISABLE_IT : Disable the specified I2S interrupts
-      (+) __HAL_I2S_GET_FLAG: Check whether the specified I2S flag is set or not
-
-    [..]
-      (@) You can refer to the I2S HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup I2S I2S
-  * @brief I2S HAL module driver
-  * @{
-  */
-
-#ifdef HAL_I2S_MODULE_ENABLED
-#if defined(STM32L100xC) || \
-    defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \
-    defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || \
-    defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-static void               I2S_DMATxCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma); 
-static void               I2S_DMARxCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void               I2S_DMAError(DMA_HandleTypeDef *hdma);
-static void               I2S_Transmit_IT(I2S_HandleTypeDef *hi2s);
-static void               I2S_Receive_IT(I2S_HandleTypeDef *hi2s);
-static HAL_StatusTypeDef  I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout);
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup I2S_Exported_Functions I2S Exported Functions
-  * @{
-  */
-
-/** @defgroup  I2S_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and 
-          de-initialiaze the I2Sx peripheral in simplex mode:
-
-      (+) User must Implement HAL_I2S_MspInit() function in which he configures 
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_I2S_Init() to configure the selected device with 
-          the selected configuration:
-        (++) Mode
-        (++) Standard 
-        (++) Data Format
-        (++) MCLK Output
-        (++) Audio frequency
-        (++) Polarity
-
-     (+) Call the function HAL_I2S_DeInit() to restore the default configuration 
-         of the selected I2Sx periperal. 
-  @endverbatim
-  * @{
-  */
-
-/**
-  * @brief Initializes the I2S according to the specified parameters 
-  *         in the I2S_InitTypeDef and create the associated handle.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s)
-{
-  uint32_t i2sdiv = 2, i2sodd = 0, packetlength = 1;
-  uint32_t tmp = 0, i2sclk = 0;
-  
-  /* Check the I2S handle allocation */
-  if(hi2s == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the I2S parameters */
-  assert_param(IS_I2S_ALL_INSTANCE(hi2s->Instance));
-  assert_param(IS_I2S_MODE(hi2s->Init.Mode));
-  assert_param(IS_I2S_STANDARD(hi2s->Init.Standard));
-  assert_param(IS_I2S_DATA_FORMAT(hi2s->Init.DataFormat));
-  assert_param(IS_I2S_MCLK_OUTPUT(hi2s->Init.MCLKOutput));
-  assert_param(IS_I2S_AUDIO_FREQ(hi2s->Init.AudioFreq));
-  assert_param(IS_I2S_CPOL(hi2s->Init.CPOL));  
-  
-  if(hi2s->State == HAL_I2S_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
-    HAL_I2S_MspInit(hi2s);
-  }
-  
-  hi2s->State = HAL_I2S_STATE_BUSY;
-
-  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
-  if(hi2s->Init.AudioFreq == I2S_AUDIOFREQ_DEFAULT)
-  {
-    i2sodd = (uint32_t)0;
-    i2sdiv = (uint32_t)2;   
-  }
-  /* If the requested audio frequency is not the default, compute the prescaler */
-  else
-  {
-    /* Check the frame length (For the Prescaler computing) *******************/
-    if(hi2s->Init.DataFormat == I2S_DATAFORMAT_16B)
-    {
-      /* Packet length is 16 bits */
-      packetlength = 1;
-    }
-    else
-    {
-      /* Packet length is 32 bits */
-      packetlength = 2;
-    }
-
-    /* Get the source clock value: based on System Clock value */
-    i2sclk = HAL_RCC_GetSysClockFreq();    
-
-    /* Compute the Real divider depending on the MCLK output state, with a floating point */
-    if(hi2s->Init.MCLKOutput == I2S_MCLKOUTPUT_ENABLE)
-    {
-      /* MCLK output is enabled */
-      tmp = (uint32_t)(((((i2sclk / 256) * 10) / hi2s->Init.AudioFreq)) + 5);
-    }
-    else
-    {
-      /* MCLK output is disabled */
-      tmp = (uint32_t)(((((i2sclk / (32 * packetlength)) *10 ) / hi2s->Init.AudioFreq)) + 5);
-    }
-
-    /* Remove the flatting point */
-    tmp = tmp / 10;  
-
-    /* Check the parity of the divider */
-    i2sodd = (uint32_t)(tmp & (uint32_t)1);
-
-    /* Compute the i2sdiv prescaler */
-    i2sdiv = (uint32_t)((tmp - i2sodd) / 2);
-
-    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
-    i2sodd = (uint32_t) (i2sodd << 8);
-  }
-
-  /* Test if the divider is 1 or 0 or greater than 0xFF */
-  if((i2sdiv < 2) || (i2sdiv > 0xFF))
-  {
-    /* Set the default values */
-    i2sdiv = 2;
-    i2sodd = 0;
-  }
-
-  /*----------------------- SPIx I2SCFGR & I2SPR Configuration ----------------*/
-  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
-  /* And configure the I2S with the I2S_InitStruct values                      */
-  MODIFY_REG( hi2s->Instance->I2SCFGR, (SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN |\
-                                        SPI_I2SCFGR_CKPOL | SPI_I2SCFGR_I2SSTD |\
-                                        SPI_I2SCFGR_PCMSYNC | SPI_I2SCFGR_I2SCFG |\
-                                        SPI_I2SCFGR_I2SE  | SPI_I2SCFGR_I2SMOD),\
-                                       (SPI_I2SCFGR_I2SMOD | hi2s->Init.Mode |\
-                                        hi2s->Init.Standard | hi2s->Init.DataFormat |\
-                                        hi2s->Init.CPOL));
-
-  /* Write to SPIx I2SPR register the computed value */
-  hi2s->Instance->I2SPR = (uint32_t)((uint32_t)i2sdiv | (uint32_t)(i2sodd | (uint32_t)hi2s->Init.MCLKOutput));
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State= HAL_I2S_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief DeInitializes the I2S peripheral 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* Check the I2S handle allocation */
-  if(hi2s == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  hi2s->State = HAL_I2S_STATE_BUSY;
-  
-  /* Disable the I2S Peripheral Clock */
-  __HAL_I2S_DISABLE(hi2s);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_I2S_MspDeInit(hi2s);
-
-  hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-  hi2s->State = HAL_I2S_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hi2s);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief I2S MSP Init
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief I2S MSP DeInit
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group2 IO operation functions 
-  *  @brief Data transfers functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    [..]
-    This subsection provides a set of functions allowing to manage the I2S data 
-    transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode : The communication is performed in the polling mode. 
-            The status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) No-Blocking mode : The communication is performed using Interrupts 
-            or DMA. These functions return the status of the transfer startup.
-            The end of the data processing will be indicated through the 
-            dedicated I2S IRQ when using Interrupt mode or the DMA IRQ when 
-            using DMA mode.
-
-    (#) Blocking mode functions are :
-        (++) HAL_I2S_Transmit()
-        (++) HAL_I2S_Receive()
-        
-    (#) No-Blocking mode functions with Interrupt are :
-        (++) HAL_I2S_Transmit_IT()
-        (++) HAL_I2S_Receive_IT()
-
-    (#) No-Blocking mode functions with DMA are :
-        (++) HAL_I2S_Transmit_DMA()
-        (++) HAL_I2S_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_I2S_TxCpltCallback()
-        (++) HAL_I2S_RxCpltCallback()
-        (++) HAL_I2S_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Transmit an amount of data in blocking mode
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @param  Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  if((pData == HAL_NULL ) || (Size == 0)) 
-  {
-    return  HAL_ERROR;                                    
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  { 
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = (Size << 1);
-      hi2s->TxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-     
-    /* Set state and reset error code */
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-    hi2s->pTxBuffPtr = pData;
-      
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-    
-    while(hi2s->TxXferCount > 0)
-    {
-      /* Wait until TXE flag is set */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
-      hi2s->TxXferCount--;   
-    } 
-
-    /* Wait until TXE flag is set, to confirm the end of the transcation */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_TXE, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    } 
-    /* Wait until Busy flag is reset */
-    if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_BSY, SET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    hi2s->State = HAL_I2S_STATE_READY; 
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in blocking mode 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @param Timeout: Timeout duration
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
-  *       in continouse way and as the I2S is not disabled at the end of the I2S transaction.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  if((pData == HAL_NULL ) || (Size == 0)) 
-  {
-    return  HAL_ERROR;
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  { 
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = (Size << 1);
-      hi2s->RxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-        
-    /* Set state and reset error code */
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-    hi2s->pRxBuffPtr = pData;
-    
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-     
-    /* Receive data */
-    while(hi2s->RxXferCount > 0)
-    {
-      /* Wait until RXNE flag is set */
-      if (I2S_WaitFlagStateUntilTimeout(hi2s, I2S_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-      {
-        return HAL_TIMEOUT;
-      }
-      
-      (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
-      hi2s->RxXferCount--;
-    }
-    
-    hi2s->State = HAL_I2S_STATE_READY; 
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  if((pData == HAL_NULL) || (Size == 0)) 
-  {
-    return  HAL_ERROR;
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-    
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    hi2s->pTxBuffPtr = pData;
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = (Size << 1);
-      hi2s->TxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-
-    /* Enable TXE and ERR interrupt */
-    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @note It is recommended to use DMA for the I2S receiver to avoid de-synchronisation 
-  * between Master and Slave otherwise the I2S interrupt should be optimized. 
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    hi2s->pRxBuffPtr = pData;
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = (Size << 1);
-      hi2s->RxXferCount = (Size << 1);
-    }  
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    
-    /* Enable TXE and ERR interrupt */
-    __HAL_I2S_ENABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-    
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY; 
-  } 
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with DMA
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Transmit data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  if((pData == HAL_NULL) || (Size == 0)) 
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {  
-    hi2s->pTxBuffPtr = pData;
-    hi2s->State = HAL_I2S_STATE_BUSY_TX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->TxXferSize = (Size << 1);
-      hi2s->TxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->TxXferSize = Size;
-      hi2s->TxXferCount = Size;
-    }
-
-    /* Set the I2S Tx DMA Half transfert complete callback */
-    hi2s->hdmatx->XferHalfCpltCallback = I2S_DMATxHalfCplt;
-
-    /* Set the I2S Tx DMA transfert complete callback */
-    hi2s->hdmatx->XferCpltCallback = I2S_DMATxCplt;
-
-    /* Set the DMA error callback */
-    hi2s->hdmatx->XferErrorCallback = I2S_DMAError;
-
-    /* Enable the Tx DMA Channel */
-    HAL_DMA_Start_IT(hi2s->hdmatx, (uint32_t)hi2s->pTxBuffPtr, (uint32_t)&hi2s->Instance->DR, hi2s->TxXferSize);
-
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-    /* Check if the I2S Tx request is already enabled */ 
-    if((hi2s->Instance->CR2 & SPI_CR2_TXDMAEN) != SPI_CR2_TXDMAEN)
-    {
-      /* Enable Tx DMA Request */  
-      SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with DMA 
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param pData: a 16-bit pointer to the Receive data buffer.
-  * @param Size: number of data sample to be sent:
-  * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
-  *       configuration phase, the Size parameter means the number of 16-bit data length 
-  *       in the transaction and when a 24-bit data frame or a 32-bit data frame is selected 
-  *       the Size parameter means the number of 16-bit data length. 
-  * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization 
-  *       between Master and Slave(example: audio streaming).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size)
-{
-  if((pData == HAL_NULL) || (Size == 0))
-  {
-    return  HAL_ERROR;
-  }
-
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-
-  if(hi2s->State == HAL_I2S_STATE_READY)
-  {
-    hi2s->pRxBuffPtr = pData;
-    hi2s->State = HAL_I2S_STATE_BUSY_RX;
-    hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
-
-    if(((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_24B)||\
-      ((hi2s->Instance->I2SCFGR & (SPI_I2SCFGR_DATLEN | SPI_I2SCFGR_CHLEN)) == I2S_DATAFORMAT_32B))
-    {
-      hi2s->RxXferSize = (Size << 1);
-      hi2s->RxXferCount = (Size << 1);
-    }
-    else
-    {
-      hi2s->RxXferSize = Size;
-      hi2s->RxXferCount = Size;
-    }
-    
-    
-    /* Set the I2S Rx DMA Half transfert complete callback */
-    hi2s->hdmarx->XferHalfCpltCallback = I2S_DMARxHalfCplt;
-    
-    /* Set the I2S Rx DMA transfert complete callback */
-    hi2s->hdmarx->XferCpltCallback = I2S_DMARxCplt;
-    
-    /* Set the DMA error callback */
-    hi2s->hdmarx->XferErrorCallback = I2S_DMAError;
-    
-    /* Check if Master Receiver mode is selected */
-    if((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SCFG) == I2S_MODE_MASTER_RX)
-    {
-      /* Clear the Overrun Flag by a read operation to the SPI_DR register followed by a read
-      access to the SPI_SR register. */ 
-      __HAL_I2S_CLEAR_OVRFLAG(hi2s);
-    }
-    
-    /* Enable the Rx DMA Channel */
-    HAL_DMA_Start_IT(hi2s->hdmarx, (uint32_t)&hi2s->Instance->DR, (uint32_t)hi2s->pRxBuffPtr, hi2s->RxXferSize);
-    
-    /* Check if the I2S is already enabled */ 
-    if((hi2s->Instance->I2SCFGR &SPI_I2SCFGR_I2SE) != SPI_I2SCFGR_I2SE)
-    {
-      /* Enable I2S peripheral */
-      __HAL_I2S_ENABLE(hi2s);
-    }
-
-     /* Check if the I2S Rx request is already enabled */ 
-    if((hi2s->Instance->CR2 &SPI_CR2_RXDMAEN) != SPI_CR2_RXDMAEN)
-    {
-      /* Enable Rx DMA Request */  
-      SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-
-    return HAL_OK;
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hi2s);
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Disable the I2S DMA Tx request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Disable the I2S DMA Rx request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  if(hi2s->State == HAL_I2S_STATE_BUSY_TX)
-  {
-    /* Enable the I2S DMA Tx request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  }
-  else if(hi2s->State == HAL_I2S_STATE_BUSY_RX)
-  {
-    /* Enable the I2S DMA Rx request */
-    SET_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  }
-  
-  /* If the I2S peripheral is still not enabled, enable it */
-  if ((hi2s->Instance->I2SCFGR & SPI_I2SCFGR_I2SE) == 0)
-  {
-    /* Enable I2S peripheral */    
-    __HAL_I2S_ENABLE(hi2s);
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Resumes the audio stream playing from the Media.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s)
-{
-  /* Process Locked */
-  __HAL_LOCK(hi2s);
-  
-  /* Disable the I2S Tx/Rx DMA requests */
-  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-  CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-  
-  /* Abort the I2S DMA Channel tx */
-  if(hi2s->hdmatx != HAL_NULL)
-  {
-    /* Disable the I2S DMA channel */
-    __HAL_DMA_DISABLE(hi2s->hdmatx);
-    HAL_DMA_Abort(hi2s->hdmatx);
-  }
-  /* Abort the I2S DMA Channel rx */
-  if(hi2s->hdmarx != HAL_NULL)
-  {
-    /* Disable the I2S DMA channel */
-    __HAL_DMA_DISABLE(hi2s->hdmarx);
-    HAL_DMA_Abort(hi2s->hdmarx);
-  }
-
-  /* Disable I2S peripheral */
-  __HAL_I2S_DISABLE(hi2s);
-  
-  hi2s->State = HAL_I2S_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hi2s);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles I2S interrupt request.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s)
-{  
-  uint32_t i2ssr = hi2s->Instance->SR;
-  
-  /* I2S in mode Receiver ------------------------------------------------*/
-  if(((i2ssr & I2S_FLAG_OVR) != I2S_FLAG_OVR) &&
-     ((i2ssr & I2S_FLAG_RXNE) == I2S_FLAG_RXNE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_RXNE) != RESET))
-  {
-    I2S_Receive_IT(hi2s);
-    return;
-  }
-
-  /* I2S in mode Tramitter -----------------------------------------------*/
-  if(((i2ssr & I2S_FLAG_TXE) == I2S_FLAG_TXE) && (__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_TXE) != RESET))
-  {     
-    I2S_Transmit_IT(hi2s);
-    return;
-  } 
-
-  /* I2S interrupt error -------------------------------------------------*/
-  if(__HAL_I2S_GET_IT_SOURCE(hi2s, I2S_IT_ERR) != RESET)
-  {
-    /* I2S Overrun error interrupt occured ---------------------------------*/
-    if((i2ssr & I2S_FLAG_OVR) == I2S_FLAG_OVR)
-    {
-      /* Disable RXNE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-      
-      /* Set the error code and execute error callback*/
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_OVR);
-    } 
-    
-    /* I2S Underrun error interrupt occured --------------------------------*/
-    if((i2ssr & I2S_FLAG_UDR) == I2S_FLAG_UDR)
-    {
-      /* Disable TXE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-      
-      /* Set the error code and execute error callback*/
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_UDR);
-    }
-    
-    /* I2S Frame format error interrupt occured --------------------------*/
-    if((i2ssr & I2S_FLAG_FRE) == I2S_FLAG_FRE)
-    {
-      /* Disable TXE and ERR interrupt */
-      __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_RXNE | I2S_IT_ERR));
-
-      /* Set the error code and execute error callback*/
-      SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_FRE);
-    }
-    
-    /* Set the I2S State ready */
-    hi2s->State = HAL_I2S_STATE_READY; 
-    /* Call the Error Callback */
-    HAL_I2S_ErrorCallback(hi2s);
-  }
-}
-
-/**
-  * @brief Tx Transfer Half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxHalfCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief Tx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_TxCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief Rx Transfer half completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-__weak void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief I2S error callbacks
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
- __weak void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_I2S_ErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   Peripheral State functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the I2S state
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval HAL state
-  */
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->State;
-}
-
-/**
-  * @brief  Return the I2S error code
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval I2S Error Code
-  */
-HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s)
-{
-  return hi2s->ErrorCode;
-}
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/** @defgroup I2S_Private_Functions I2S Private Functions
-  * @{
-  */
-/**
-  * @brief DMA I2S transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMATxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  {
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    hi2s->TxXferCount = 0;
-    hi2s->State = HAL_I2S_STATE_READY;
-  }
-  HAL_I2S_TxCpltCallback(hi2s);
-}
-
-/**
-  * @brief DMA I2S transmit process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_I2S_TxHalfCpltCallback(hi2s);
-}
-
-/**
-  * @brief DMA I2S receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMARxCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  {
-    /* Disable Rx DMA Request */
-    CLEAR_BIT(hi2s->Instance->CR2, SPI_CR2_RXDMAEN);
-    hi2s->RxXferCount = 0;
-    hi2s->State = HAL_I2S_STATE_READY;
-  }
-  HAL_I2S_RxCpltCallback(hi2s); 
-}
-
-/**
-  * @brief DMA I2S receive process half complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_I2S_RxHalfCpltCallback(hi2s); 
-}
-
-/**
-  * @brief DMA I2S communication error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void I2S_DMAError(DMA_HandleTypeDef *hdma)
-{
-  I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  /* Disable Rx and Tx DMA Request */
-  CLEAR_BIT(hi2s->Instance->CR2, (SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN));
-  hi2s->TxXferCount = 0;
-  hi2s->RxXferCount = 0;
-
-  hi2s->State= HAL_I2S_STATE_READY;
-
-  /* Set the error code and execute error callback*/
-  SET_BIT(hi2s->ErrorCode, HAL_I2S_ERROR_DMA);
-  HAL_I2S_ErrorCallback(hi2s);
-}
-
-/**
-  * @brief Transmit an amount of data in non-blocking mode with Interrupt
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @retval None
-  */
-static void I2S_Transmit_IT(I2S_HandleTypeDef *hi2s)
-{
-  /* Transmit data */
-  hi2s->Instance->DR = (*hi2s->pTxBuffPtr++);
-  hi2s->TxXferCount--;
-    
-  if(hi2s->TxXferCount == 0)
-  {
-    /* Disable TXE and ERR interrupt */
-    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_TXE | I2S_IT_ERR));
-
-    hi2s->State = HAL_I2S_STATE_READY;
-    HAL_I2S_TxCpltCallback(hi2s);
-  }
-}
-
-/**
-  * @brief Receive an amount of data in non-blocking mode with Interrupt
-  * @param hi2s: I2S handle
-  * @retval None
-  */
-static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
-{
-  /* Receive data */    
-  (*hi2s->pRxBuffPtr++) = hi2s->Instance->DR;
-  hi2s->RxXferCount--;
-  
-  if(hi2s->RxXferCount == 0)
-  {
-    /* Disable RXNE and ERR interrupt */
-    __HAL_I2S_DISABLE_IT(hi2s, (I2S_IT_RXNE | I2S_IT_ERR));
-
-    hi2s->State = HAL_I2S_STATE_READY;     
-    HAL_I2S_RxCpltCallback(hi2s); 
-  }
-}
-
-
-/**
-  * @brief This function handles I2S Communication Timeout.
-  * @param  hi2s: pointer to a I2S_HandleTypeDef structure that contains
-  *         the configuration information for I2S module
-  * @param Flag: Flag checked
-  * @param Status: Value of the flag expected
-  * @param Timeout: Duration of the timeout
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t Status, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-  
-  /* Get tick */
-  tickstart = HAL_GetTick();
-  
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_I2S_GET_FLAG(hi2s, Flag) == RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Set the I2S State ready */
-          hi2s->State= HAL_I2S_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2s);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_I2S_GET_FLAG(hi2s, Flag) != RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Set the I2S State ready */
-          hi2s->State= HAL_I2S_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hi2s);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-#endif /* STM32L100xC ||
-          STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\
-          STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE ||\\
-          STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
-#endif /* HAL_I2S_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_i2s.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,454 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_i2s.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of I2S HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_I2S_H
-#define __STM32L1xx_HAL_I2S_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined(STM32L100xC) || \
-    defined(STM32L151xC) || defined(STM32L151xCA) || defined(STM32L151xD) || defined(STM32L151xE) || \
-    defined(STM32L152xC) || defined(STM32L152xCA) || defined(STM32L152xD) || defined(STM32L152xE) || defined(STM32L151xE) || \
-    defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-    
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"  
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup I2S
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_Types I2S Exported Types
-  * @{
-  */
-
-/** 
-  * @brief I2S Init structure definition  
-  */
-typedef struct
-{
-  uint32_t Mode;         /*!< Specifies the I2S operating mode.
-                              This parameter can be a value of @ref I2S_Mode */
-
-  uint32_t Standard;     /*!< Specifies the standard used for the I2S communication.
-                              This parameter can be a value of @ref I2S_Standard */
-
-  uint32_t DataFormat;   /*!< Specifies the data format for the I2S communication.
-                              This parameter can be a value of @ref I2S_Data_Format */
-
-  uint32_t MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
-                              This parameter can be a value of @ref I2S_MCLK_Output */
-
-  uint32_t AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
-                              This parameter can be a value of @ref I2S_Audio_Frequency */
-
-  uint32_t CPOL;         /*!< Specifies the idle state of the I2S clock.
-                              This parameter can be a value of @ref I2S_Clock_Polarity */
-
-}I2S_InitTypeDef;
-
-/** 
-  * @brief  HAL State structures definition
-  */ 
-typedef enum
-{
-  HAL_I2S_STATE_RESET      = 0x00,  /*!< I2S not yet initialized or disabled                */
-  HAL_I2S_STATE_READY      = 0x01,  /*!< I2S initialized and ready for use                  */
-  HAL_I2S_STATE_BUSY       = 0x02,  /*!< I2S internal process is ongoing                    */   
-  HAL_I2S_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */ 
-  HAL_I2S_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
-  HAL_I2S_STATE_TIMEOUT    = 0x03,  /*!< I2S pause state: used in case of DMA               */ 
-  HAL_I2S_STATE_ERROR      = 0x04   /*!< I2S error state                                    */      
-}HAL_I2S_StateTypeDef;
-
-/** 
-  * @brief  HAL I2S Error Code structure definition  
-  */ 
-typedef enum
-{
-  HAL_I2S_ERROR_NONE      = 0x00,    /*!< No error                    */
-  HAL_I2S_ERROR_UDR       = 0x01,    /*!< I2S Underrun error          */
-  HAL_I2S_ERROR_OVR       = 0x02,    /*!< I2S Overrun error           */
-  HAL_I2S_ERROR_FRE       = 0x04,    /*!< I2S Frame format error      */
-  HAL_I2S_ERROR_DMA       = 0x08     /*!< DMA transfer error          */
-}HAL_I2S_ErrorTypeDef;
-
-/** 
-  * @brief I2S handle Structure definition  
-  */
-typedef struct
-{
-  SPI_TypeDef                *Instance;    /* I2S registers base address        */
-
-  I2S_InitTypeDef            Init;         /* I2S communication parameters      */
-  
-  uint16_t                   *pTxBuffPtr;  /* Pointer to I2S Tx transfer buffer */
-  
-  __IO uint16_t              TxXferSize;   /* I2S Tx transfer size              */
-  
-  __IO uint16_t              TxXferCount;  /* I2S Tx transfer Counter           */
-  
-  uint16_t                   *pRxBuffPtr;  /* Pointer to I2S Rx transfer buffer */
-  
-  __IO uint16_t              RxXferSize;   /* I2S Rx transfer size              */
-  
-  __IO uint16_t              RxXferCount;  /* I2S Rx transfer counter 
-                                              (This field is initialized at the 
-                                               same value as transfer size at the 
-                                               beginning of the transfer and 
-                                               decremented when a sample is received. 
-                                               NbSamplesReceived = RxBufferSize-RxBufferCount) */
-
-  DMA_HandleTypeDef          *hdmatx;      /* I2S Tx DMA handle parameters      */
-
-  DMA_HandleTypeDef          *hdmarx;      /* I2S Rx DMA handle parameters      */
-  
-  __IO HAL_LockTypeDef       Lock;         /* I2S locking object                */
-  
-  __IO HAL_I2S_StateTypeDef  State;        /* I2S communication state           */
-
-  __IO HAL_I2S_ErrorTypeDef  ErrorCode;    /* I2S Error code                    */
-
-}I2S_HandleTypeDef;
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup I2S_Exported_Constants I2S Exported Constants
-  * @{
-  */
-
-/** @defgroup I2S_Mode I2S Mode
-  * @{
-  */
-#define I2S_MODE_SLAVE_TX                ((uint32_t)0x00000000)
-#define I2S_MODE_SLAVE_RX                ((uint32_t)0x00000100)
-#define I2S_MODE_MASTER_TX               ((uint32_t)0x00000200)
-#define I2S_MODE_MASTER_RX               ((uint32_t)0x00000300)
-
-#define IS_I2S_MODE(MODE) (((MODE) == I2S_MODE_SLAVE_TX)  || \
-                           ((MODE) == I2S_MODE_SLAVE_RX)  || \
-                           ((MODE) == I2S_MODE_MASTER_TX) || \
-                           ((MODE) == I2S_MODE_MASTER_RX))
-/**
-  * @}
-  */
-  
-/** @defgroup I2S_Standard I2S Standard
-  * @{
-  */
-#define I2S_STANDARD_PHILIPS             ((uint32_t)0x00000000)
-#define I2S_STANDARD_MSB                 ((uint32_t) SPI_I2SCFGR_I2SSTD_0)
-#define I2S_STANDARD_LSB                 ((uint32_t) SPI_I2SCFGR_I2SSTD_1)
-#define I2S_STANDARD_PCM_SHORT           ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
-                                                     SPI_I2SCFGR_I2SSTD_1))
-#define I2S_STANDARD_PCM_LONG            ((uint32_t)(SPI_I2SCFGR_I2SSTD_0 |\
-                                                     SPI_I2SCFGR_I2SSTD_1 |\
-                                                     SPI_I2SCFGR_PCMSYNC))
-
-#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_STANDARD_PHILIPS)   || \
-                                   ((STANDARD) == I2S_STANDARD_MSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_LSB)       || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_SHORT) || \
-                                   ((STANDARD) == I2S_STANDARD_PCM_LONG))
-/** @defgroup I2S_Legacy I2S Legacy
-  * @{
-  */
-#define I2S_STANDARD_PHILLIPS      I2S_STANDARD_PHILIPS
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @defgroup I2S_Data_Format I2S Data Format
-  * @{
-  */
-#define I2S_DATAFORMAT_16B               ((uint32_t)0x00000000)
-#define I2S_DATAFORMAT_16B_EXTENDED      ((uint32_t) SPI_I2SCFGR_CHLEN)
-#define I2S_DATAFORMAT_24B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_0))
-#define I2S_DATAFORMAT_32B               ((uint32_t)(SPI_I2SCFGR_CHLEN | SPI_I2SCFGR_DATLEN_1))
-
-#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DATAFORMAT_16B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_16B_EXTENDED) || \
-                                    ((FORMAT) == I2S_DATAFORMAT_24B)          || \
-                                    ((FORMAT) == I2S_DATAFORMAT_32B))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_MCLK_Output I2S MCLK Output
-  * @{
-  */
-#define I2S_MCLKOUTPUT_ENABLE           ((uint32_t)SPI_I2SPR_MCKOE)
-#define I2S_MCLKOUTPUT_DISABLE          ((uint32_t)0x00000000)
-
-#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOUTPUT_ENABLE) || \
-                                    ((OUTPUT) == I2S_MCLKOUTPUT_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Audio_Frequency I2S Audio Frequency
-  * @{
-  */
-#define I2S_AUDIOFREQ_192K               ((uint32_t)192000)
-#define I2S_AUDIOFREQ_96K                ((uint32_t)96000)
-#define I2S_AUDIOFREQ_48K                ((uint32_t)48000)
-#define I2S_AUDIOFREQ_44K                ((uint32_t)44100)
-#define I2S_AUDIOFREQ_32K                ((uint32_t)32000)
-#define I2S_AUDIOFREQ_22K                ((uint32_t)22050)
-#define I2S_AUDIOFREQ_16K                ((uint32_t)16000)
-#define I2S_AUDIOFREQ_11K                ((uint32_t)11025)
-#define I2S_AUDIOFREQ_8K                 ((uint32_t)8000)
-#define I2S_AUDIOFREQ_DEFAULT            ((uint32_t)2)
-
-#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AUDIOFREQ_8K)    && \
-                                  ((FREQ) <= I2S_AUDIOFREQ_192K)) || \
-                                  ((FREQ) == I2S_AUDIOFREQ_DEFAULT))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Clock_Polarity I2S Clock Polarity
-  * @{
-  */
-#define I2S_CPOL_LOW                    ((uint32_t)0x00000000)
-#define I2S_CPOL_HIGH                   ((uint32_t)SPI_I2SCFGR_CKPOL)
-
-#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_LOW) || \
-                           ((CPOL) == I2S_CPOL_HIGH))
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Interrupt_configuration_definition I2S Interrupt configuration definition
-  * @{
-  */
-#define I2S_IT_TXE                      SPI_CR2_TXEIE
-#define I2S_IT_RXNE                     SPI_CR2_RXNEIE
-#define I2S_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup I2S_Flag_definition I2S Flag definition
-  * @{
-  */
-#define I2S_FLAG_TXE                    SPI_SR_TXE
-#define I2S_FLAG_RXNE                   SPI_SR_RXNE
-
-#define I2S_FLAG_UDR                    SPI_SR_UDR
-#define I2S_FLAG_OVR                    SPI_SR_OVR
-#define I2S_FLAG_FRE                    SPI_SR_FRE
-
-#define I2S_FLAG_CHSIDE                 SPI_SR_CHSIDE
-#define I2S_FLAG_BSY                    SPI_SR_BSY
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup I2S_Exported_macros I2S Exported Macros
-  * @{
-  */
-
-/** @brief  Reset I2S handle state
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
-
-/** @brief  Enable or disable the specified SPI peripheral (in I2S mode).
-  * @param  __HANDLE__: specifies the I2S Handle. 
-  * @retval None
-  */
-#define __HAL_I2S_ENABLE(__HANDLE__)    (SET_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-#define __HAL_I2S_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->I2SCFGR, SPI_I2SCFGR_I2SE))
-
-/** @brief  Enable or disable the specified I2S interrupts.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval None
-  */  
-#define __HAL_I2S_ENABLE_IT(__HANDLE__, __INTERRUPT__)    (SET_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
-#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CR2,(__INTERRUPT__)))
- 
-/** @brief  Checks if the specified I2S interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  *         This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
-  * @param  __INTERRUPT__: specifies the I2S interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg I2S_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg I2S_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Checks whether the specified I2S flag is set or not.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg I2S_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg I2S_FLAG_TXE: Transmit buffer empty flag
-  *            @arg I2S_FLAG_UDR: Underrun flag
-  *            @arg I2S_FLAG_OVR: Overrun flag
-  *            @arg I2S_FLAG_FRE: Frame error flag
-  *            @arg I2S_FLAG_CHSIDE: Channel Side flag
-  *            @arg I2S_FLAG_BSY: Busy flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief Clears the I2S OVR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */                                                                                                   
-#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) do{__IO uint32_t tmpreg = (__HANDLE__)->Instance->DR;\
-                                                             tmpreg = (__HANDLE__)->Instance->SR;\
-                                              }while(0)
-/** @brief Clears the I2S UDR pending flag.
-  * @param  __HANDLE__: specifies the I2S Handle.
-  * @retval None
-  */
-#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__)((__HANDLE__)->Instance->SR)
-/**
-  * @}
-  */ 
-                                                
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup I2S_Exported_Functions
-  * @{
-  */
-                                                
-/** @addtogroup I2S_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef HAL_I2S_Init(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DeInit (I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspInit(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_MspDeInit(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  ***************************************************/
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_I2S_Transmit(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_I2S_Receive(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size, uint32_t Timeout);
-
- /* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_I2S_Transmit_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_IT(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-void HAL_I2S_IRQHandler(I2S_HandleTypeDef *hi2s);
-
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_I2S_Transmit_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_I2S_Receive_DMA(I2S_HandleTypeDef *hi2s, uint16_t *pData, uint16_t Size);
-
-HAL_StatusTypeDef HAL_I2S_DMAPause(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAResume(I2S_HandleTypeDef *hi2s);
-HAL_StatusTypeDef HAL_I2S_DMAStop(I2S_HandleTypeDef *hi2s);
-
-/* Callbacks used in non blocking modes (Interrupt and DMA) *******************/
-void HAL_I2S_TxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_TxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_RxCpltCallback(I2S_HandleTypeDef *hi2s);
-void HAL_I2S_ErrorCallback(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/** @addtogroup I2S_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control and State functions  ************************************/
-HAL_I2S_StateTypeDef HAL_I2S_GetState(I2S_HandleTypeDef *hi2s);
-HAL_I2S_ErrorTypeDef HAL_I2S_GetError(I2S_HandleTypeDef *hi2s);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* STM32L100xC ||
-          STM32L151xC || STM32L151xCA || STM32L151xD || STM32L151xE ||\\
-          STM32L152xC || STM32L152xCA || STM32L152xD || STM32L152xE || STM32L151xE ||\\
-          STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_I2S_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1571 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_irda.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   IRDA HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the IrDA SIR ENDEC block (IrDA):
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The IRDA HAL driver can be used as follows:
-
-    (#) Declare a IRDA_HandleTypeDef handle structure.
-    (#) Initialize the IRDA low level resources by implementing the HAL_IRDA_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) IRDA pins configuration:
-            (+++) Enable the clock for the IRDA GPIOs.
-            (+++) Configure these IRDA pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_IRDA_Transmit_IT()
-             and HAL_IRDA_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_IRDA_Transmit_DMA()
-             and HAL_IRDA_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initilalized DMA handle to the IRDA DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
-    (#) Program the Baud Rate, Word Length, Parity, IrDA Mode, Prescaler 
-        and Mode(Receiver/Transmitter) in the hirda Init structure.
-
-    (#) Initialize the IRDA registers by calling the HAL_IRDA_Init() API:
-        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customed HAL_IRDA_MspInit() API.
-
-        -@@- The specific IRDA interrupts (Transmission complete interrupt, 
-             RXNE interrupt and Error Interrupts) will be managed using the macros
-             __HAL_IRDA_ENABLE_IT() and __HAL_IRDA_DISABLE_IT() inside the transmit and receive process.
-          
-    (#) Three operation modes are available within this driver :
- 
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Send an amount of data in blocking mode using HAL_IRDA_Transmit() 
-       (+) Receive an amount of data in blocking mode using HAL_IRDA_Receive()
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Send an amount of data in non blocking mode using HAL_IRDA_Transmit_IT() 
-       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_IRDA_Receive_IT() 
-       (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_IRDA_ErrorCallback
-
-     *** DMA mode IO operation ***    
-     ==============================
-     [..] 
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_IRDA_Transmit_DMA() 
-       (+) At transmission end of transfer HAL_IRDA_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_IRDA_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_IRDA_Receive_DMA() 
-       (+) At reception end of transfer HAL_IRDA_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_IRDA_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_IRDA_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_IRDA_ErrorCallback
-
-     *** IRDA HAL driver macros list ***
-     ====================================
-     [..]
-       Below the list of most used macros in IRDA HAL driver.
-       
-       (+) __HAL_IRDA_ENABLE: Enable the IRDA peripheral 
-       (+) __HAL_IRDA_DISABLE: Disable the IRDA peripheral     
-       (+) __HAL_IRDA_GET_FLAG : Check whether the specified IRDA flag is set or not
-       (+) __HAL_IRDA_CLEAR_FLAG : Clear the specified IRDA pending flag
-       (+) __HAL_IRDA_ENABLE_IT: Enable the specified IRDA interrupt
-       (+) __HAL_IRDA_DISABLE_IT: Disable the specified IRDA interrupt
-      
-     [..] 
-       (@) You can refer to the IRDA HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IRDA IRDA
-  * @brief HAL IRDA module driver
-  * @{
-  */
-
-#ifdef HAL_IRDA_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup IRDA_Private_Constants   IRDA Private Constants
-  * @{
-  */
-#define IRDA_TIMEOUT_VALUE  22000
-#define IRDA_DR_MASK_U16_7DATABITS  (uint16_t)0x007F
-#define IRDA_DR_MASK_U16_8DATABITS  (uint16_t)0x00FF
-#define IRDA_DR_MASK_U16_9DATABITS  (uint16_t)0x01FF
-
-#define IRDA_DR_MASK_U8_7DATABITS  (uint8_t)0x7F
-#define IRDA_DR_MASK_U8_8DATABITS  (uint8_t)0xFF
-
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup IRDA_Private_Functions   IRDA Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda);
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda);
-static void IRDA_SetConfig (IRDA_HandleTypeDef *hirda);
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma);
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup IRDA_Exported_Functions IRDA Exported Functions
-  * @{
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-  This subsection provides a set of functions allowing to initialize the USARTx or the UARTy 
-  in IrDA mode.
-  (+) For the asynchronous mode only these parameters can be configured: 
-      (++) Baud Rate
-      (++) Word Length 
-      (++) Parity: If the parity is enabled, then the MSB bit of the data written
-           in the data register is transmitted but is changed by the parity bit.
-           Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           the possible IRDA frame formats are as listed in the following table:
-   +-------------------------------------------------------------+
-   |   M bit |  PCE bit  |            IRDA frame                |
-   |---------------------|---------------------------------------|
-   |    0    |    0      |    | SB | 8 bit data | STB |          |
-   |---------|-----------|---------------------------------------|
-   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-   |---------|-----------|---------------------------------------|
-   |    1    |    0      |    | SB | 9 bit data | STB |          |
-   |---------|-----------|---------------------------------------|
-   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-   +-------------------------------------------------------------+
-      (++) Prescaler: A pulse of width less than two and greater than one PSC period(s) may or may
-           not be rejected. The receiver set up time should be managed by software. The IrDA physical layer
-           specification specifies a minimum of 10 ms delay between transmission and 
-           reception (IrDA is a half duplex protocol).
-      (++) Mode: Receiver/transmitter modes
-      (++) IrDAMode: the IrDA can operate in the Normal mode or in the Low power mode.
-
-  [..]
-    The HAL_IRDA_Init() function follows IRDA configuration procedures (details for the procedures
-    are available in reference manual (RM0038)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the IRDA mode according to the specified
-  *         parameters in the IRDA_InitTypeDef and create the associated handle.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda)
-{
-  /* Check the IRDA handle allocation */
-  if(hirda == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the IRDA instance parameters */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-  /* Check the IRDA mode parameter in the IRDA handle */
-  assert_param(IS_IRDA_POWERMODE(hirda->Init.IrDAMode)); 
-  
-  if(hirda->State == HAL_IRDA_STATE_RESET)
-  {
-    /* Init the low level hardware */
-    HAL_IRDA_MspInit(hirda);
-  }
-  
-  hirda->State = HAL_IRDA_STATE_BUSY;
-  
-  /* Disable the IRDA peripheral */
-  __HAL_IRDA_DISABLE(hirda);
-  
-  /* Set the IRDA communication parameters */
-  IRDA_SetConfig(hirda);
-  
-  /* In IrDA mode, the following bits must be kept cleared: 
-     - LINEN, STOP and CLKEN bits in the USART_CR2 register,
-     - SCEN and HDSEL bits in the USART_CR3 register.*/
-  CLEAR_BIT(hirda->Instance->CR2, (USART_CR2_LINEN | USART_CR2_STOP | USART_CR2_CLKEN));
-  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_SCEN | USART_CR3_HDSEL));
-  
-  /* Enable the IRDA peripheral */
-  __HAL_IRDA_ENABLE(hirda);
-  
-  /* Set the prescaler */
-  MODIFY_REG(hirda->Instance->GTPR, USART_GTPR_PSC, hirda->Init.Prescaler);
-  
-  /* Configure the IrDA mode */
-  MODIFY_REG(hirda->Instance->CR3, USART_CR3_IRLP, hirda->Init.IrDAMode);
-  
-  /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
-  SET_BIT(hirda->Instance->CR3, USART_CR3_IREN);
-  
-  /* Initialize the IRDA state*/
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-  hirda->State= HAL_IRDA_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the IRDA peripheral
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda)
-{
-  /* Check the IRDA handle allocation */
-  if(hirda == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-
-  hirda->State = HAL_IRDA_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_IRDA_DISABLE(hirda);
-
-  /* DeInit the low level hardware */
-  HAL_IRDA_MspDeInit(hirda);
-
-  hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-  hirda->State = HAL_IRDA_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hirda);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  IRDA MSP Init.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
- __weak void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_MspInit can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  IRDA MSP DeInit.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
- __weak void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_MspDeInit can be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group2 IO operation functions 
-  *  @brief   IRDA Transmit and Receive functions 
-  *
-@verbatim
-  ==============================================================================
-                         ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the IRDA data transfers.
-
-  [..]
-    IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
-    on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver 
-    is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
-    While receiving data, transmission should be avoided as the data to be transmitted
-    could be corrupted.
-
-    (#) There are two modes of transfer:
-        (++) Blocking mode: The communication is performed in polling mode. 
-             The HAL status of all data processing is returned by the same function 
-             after finishing transfer.  
-        (++) No-Blocking mode: The communication is performed using Interrupts 
-             or DMA, These API's return the HAL status.
-             The end of the data processing will be indicated through the 
-             dedicated IRDA IRQ when using Interrupt mode or the DMA IRQ when 
-             using DMA mode.
-             The HAL_IRDA_TxCpltCallback(), HAL_IRDA_RxCpltCallback() user callbacks 
-             will be executed respectivelly at the end of the transmit or Receive process
-             The HAL_IRDA_ErrorCallback() user callback will be executed when a communication 
-             error is detected
-
-    (#) Blocking mode APIs are :
-        (++) HAL_IRDA_Transmit()
-        (++) HAL_IRDA_Receive()
-        
-    (#) Non Blocking mode APIs with Interrupt are :
-        (++) HAL_IRDA_Transmit_IT()
-        (++) HAL_IRDA_Receive_IT()
-        (++) HAL_IRDA_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) HAL_IRDA_Transmit_DMA()
-        (++) HAL_IRDA_Receive_DMA()
-        (++) HAL_IRDA_DMAPause()
-        (++) HAL_IRDA_DMAResume()
-        (++) HAL_IRDA_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_IRDA_TxHalfCpltCallback()
-        (++) HAL_IRDA_TxCpltCallback()
-        (++) HAL_IRDA_RxHalfCpltCallback()
-        (++) HAL_IRDA_RxCpltCallback()
-        (++) HAL_IRDA_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Specify timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp = 0;
-  uint32_t  tmp1 = 0;
-
-  tmp1 = hirda->State;
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-    
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    if(hirda->State == HAL_IRDA_STATE_BUSY_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-    while(hirda->TxXferCount > 0)
-    {
-      if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
-      {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pData;
-        WRITE_REG(hirda->Instance->DR,(*tmp & IRDA_DR_MASK_U16_9DATABITS));
-        if(hirda->Init.Parity == IRDA_PARITY_NONE)
-        {
-          pData +=2;
-        }
-        else
-        {
-          pData +=1;
-        }
-      }
-      else
-      {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        WRITE_REG(hirda->Instance->DR, (*pData++ & IRDA_DR_MASK_U8_8DATABITS));
-      }
-      hirda->TxXferCount--;
-    }
-
-    if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_READY;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode. 
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @param  Timeout: Specify timeout value    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp = 0;
-  uint32_t  tmp1 = 0;
-  
-  tmp1 = hirda->State;
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-    
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_RX;
-    }
-    hirda->RxXferSize = Size;
-    hirda->RxXferCount = Size;
-    /* Check the remain data to be received */
-    while(hirda->RxXferCount > 0)
-    {
-      if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
-      {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pData ;
-        if(hirda->Init.Parity == IRDA_PARITY_NONE)
-        {
-          *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS);
-          pData +=2;
-        }
-        else
-        {
-          *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS);
-          pData +=1;
-        }
-      } 
-      else
-      {
-        if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        if(hirda->Init.Parity == IRDA_PARITY_NONE)
-        {
-          *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS);
-        }
-        else
-        {
-          *pData++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS);
-        }
-      }
-      hirda->RxXferCount--;
-    }
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_READY;
-    }
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;   
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non-blocking mode. 
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tmp = 0;
-  
-  tmp = hirda->State;
-  if((tmp == HAL_IRDA_STATE_READY) || (tmp == HAL_IRDA_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-    
-    hirda->pTxBuffPtr = pData;
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    if(hirda->State == HAL_IRDA_STATE_BUSY_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-
-    /* Enable the IRDA Parity Error Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
-    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    /* Enable the IRDA Transmit Data Register Empty Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TXE);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in non-blocking mode. 
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tmp = 0;
-  
-  tmp = hirda->State;
-  if((tmp == HAL_IRDA_STATE_READY) || (tmp == HAL_IRDA_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pRxBuffPtr = pData;
-    hirda->RxXferSize = Size;
-    hirda->RxXferCount = Size;
-
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_RX;
-    }
-
-    /* Enable the IRDA Data Register not empty Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_RXNE); 
-
-    /* Enable the IRDA Parity Error Interrupt */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_PE);
-
-    /* Enable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non-blocking mode. 
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp = 0;
-  uint32_t  tmp1 = 0;
-
-  tmp1 = hirda->State;
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pTxBuffPtr = pData;
-    hirda->TxXferSize = Size;
-    hirda->TxXferCount = Size;
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-
-    if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-
-    /* Set the IRDA DMA transfer complete callback */
-    hirda->hdmatx->XferCpltCallback = IRDA_DMATransmitCplt;
-
-    /* Set the IRDA DMA half transfert complete callback */
-    hirda->hdmatx->XferHalfCpltCallback = IRDA_DMATransmitHalfCplt;
-
-    /* Set the DMA error callback */
-    hirda->hdmatx->XferErrorCallback = IRDA_DMAError;
-
-    /* Enable the IRDA transmit DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hirda->hdmatx, *(uint32_t*)tmp, (uint32_t)&hirda->Instance->DR, Size);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode. 
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @note   When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp = 0;
-  uint32_t tmp1 = 0;
-
-  tmp1 = hirda->State;
-  if((tmp1 == HAL_IRDA_STATE_READY) || (tmp1 == HAL_IRDA_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hirda);
-
-    hirda->pRxBuffPtr = pData;
-    hirda->RxXferSize = Size;
-    hirda->ErrorCode = HAL_IRDA_ERROR_NONE;
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_RX;
-    }
-
-    /* Set the IRDA DMA transfer complete callback */
-    hirda->hdmarx->XferCpltCallback = IRDA_DMAReceiveCplt;
-
-    /* Set the IRDA DMA half transfert complete callback */
-    hirda->hdmarx->XferHalfCpltCallback = IRDA_DMAReceiveHalfCplt;
-
-    /* Set the DMA error callback */
-    hirda->hdmarx->XferErrorCallback = IRDA_DMAError;
-
-    /* Enable the DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hirda->hdmarx, (uint32_t)&hirda->Instance->DR, *(uint32_t*)tmp, Size);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the USART CR3 register */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the DMA Transfer.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda)
-{
-  /* Process Locked */
-  __HAL_LOCK(hirda);
-  
-  if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
-  {
-    /* Disable the UART DMA Tx request */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-  }
-  else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
-  {
-    /* Disable the UART DMA Rx request */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-  }
-  else if (hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
-  {
-    /* Disable the UART DMA Tx & Rx requests */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-  
-    return HAL_ERROR; 
-  }
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hirda);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief Resumes the DMA Transfer.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda)
-{
-  /* Process Locked */
-  __HAL_LOCK(hirda);
-  
-  if(hirda->State == HAL_IRDA_STATE_BUSY_TX)
-  {
-    /* Enable the UART DMA Tx request */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-  }
-  else if(hirda->State == HAL_IRDA_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resumming the Rx transfer*/
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-    /* Enable the UART DMA Rx request */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-  }
-  else if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
-  {
-    /* Clear the Overrun flag before resumming the Rx transfer*/
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-    /* Enable the UART DMA Tx & Rx request */
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-    SET_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(hirda);
-  
-    return HAL_ERROR; 
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hirda);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the DMA Transfer.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
-     */
-
-  /* Disable the UART Tx/Rx DMA requests */
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-  CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-  
-  /* Abort the UART DMA tx channel */
-  if(hirda->hdmatx != HAL_NULL)
-  {
-    HAL_DMA_Abort(hirda->hdmatx);
-  }
-  /* Abort the UART DMA rx channel */
-  if(hirda->hdmarx != HAL_NULL)
-  {
-    HAL_DMA_Abort(hirda->hdmarx);
-  }
-  
-  hirda->State = HAL_IRDA_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles IRDA interrupt request.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda)
-{
-  uint32_t  tmp1 = 0, tmp2 = 0;
-  
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_PE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_PE);
-  /* IRDA parity error interrupt occurred -----------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_IRDA_CLEAR_PEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_PE;
-  }
-
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_FE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA frame error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_IRDA_CLEAR_FEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_FE;
-  }
-
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_NE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA noise error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_IRDA_CLEAR_NEFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_NE;
-  }
-
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_ORE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_ERR);
-  /* IRDA Over-Run interrupt occurred ---------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_IRDA_CLEAR_OREFLAG(hirda);
-    hirda->ErrorCode |= HAL_IRDA_ERROR_ORE;
-  }
-
-  /* Call the Error call Back in case of Errors */
-  if(hirda->ErrorCode != HAL_IRDA_ERROR_NONE)
-  {
-    /* Disable PE and ERR interrupt */
-    __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-    __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-    __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-    
-    /* Set the IRDA state ready to be able to start again the process */
-    hirda->State = HAL_IRDA_STATE_READY;
-    HAL_IRDA_ErrorCallback(hirda);
-  }
-
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_RXNE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_RXNE);
-  /* IRDA in mode Receiver --------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    IRDA_Receive_IT(hirda);
-  }
-
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TXE);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TXE);
-  /* IRDA in mode Transmitter -----------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    IRDA_Transmit_IT(hirda);
-  }
-
-  tmp1 = __HAL_IRDA_GET_FLAG(hirda, IRDA_FLAG_TC);
-  tmp2 = __HAL_IRDA_GET_IT_SOURCE(hirda, IRDA_IT_TC);
-  /* IRDA in mode Transmitter (transmission end) -----------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    IRDA_EndTransmit_IT(hirda);
-  }   
-  
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
- __weak void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_TxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval None
-  */
- __weak void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_TxHalfCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_RxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer complete callbacks.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-__weak void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* NOTE : This function should not be modified, when the callback is needed,
-            the HAL_IRDA_RxHalfCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  IRDA error callbacks.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
- __weak void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_IRDA_ErrorCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   IRDA State and Errors functions 
-  *
-@verbatim   
-  ==============================================================================
-                  ##### Peripheral State and Errors functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to return the State of IrDA 
-    communication process and also return Peripheral Errors occurred during communication process
-     (+) HAL_IRDA_GetState() API can be helpful to check in run-time the state 
-         of the IRDA peripheral.
-     (+) HAL_IRDA_GetError() check in run-time errors that could be occurred during 
-         communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the IRDA state.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL state
-  */
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda)
-{
-  return hirda->State;
-}
-
-/**
-  * @brief  Return the IRDA error code
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval IRDA Error Code
-  */
-uint32_t HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda)
-{
-  return hirda->ErrorCode;
-}
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Private_Functions   IRDA Private Functions
-  *  @brief   IRDA Private functions 
-  * @{
-  */
-/**
-  * @brief  DMA IRDA transmit process complete callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* DMA Normal mode */
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  {
-    hirda->TxXferCount = 0;
-
-    /* Disable the DMA transfer for transmit request by setting the DMAT bit
-       in the IRDA CR3 register */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAT);
-
-    /* Wait for IRDA TC Flag */
-    if(IRDA_WaitOnFlagUntilTimeout(hirda, IRDA_FLAG_TC, RESET, IRDA_TIMEOUT_VALUE) != HAL_OK)
-    {
-      /* Timeout occurred */ 
-      hirda->State = HAL_IRDA_STATE_TIMEOUT;
-      HAL_IRDA_ErrorCallback(hirda);
-    }
-    else
-    {
-      /* No Timeout */
-      /* Check if a receive process is ongoing or not */
-      if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX)
-      {
-        hirda->State = HAL_IRDA_STATE_BUSY_RX;
-      }
-      else
-      {
-        hirda->State = HAL_IRDA_STATE_READY;
-      }
-      HAL_IRDA_TxCpltCallback(hirda);
-    }
-  }
-  /* DMA Circular mode */
-  else
-  {
-    HAL_IRDA_TxCpltCallback(hirda);
-  }
-}
-
-/**
-  * @brief DMA IRDA receive process half complete callback 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMATransmitHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_IRDA_TxHalfCpltCallback(hirda); 
-}
-
-/**
-  * @brief  DMA IRDA receive process complete callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)   
-{
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* DMA Normal mode */
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  {
-    hirda->RxXferCount = 0;
-
-    /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the IRDA CR3 register */
-    CLEAR_BIT(hirda->Instance->CR3, USART_CR3_DMAR);
-
-    if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-    {
-      hirda->State = HAL_IRDA_STATE_BUSY_TX;
-    }
-    else
-    {
-      hirda->State = HAL_IRDA_STATE_READY;
-    }
-  }
-
-  HAL_IRDA_RxCpltCallback(hirda);
-}
-
-/**
-  * @brief DMA IRDA receive process half complete callback 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMAReceiveHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_IRDA_RxHalfCpltCallback(hirda); 
-}
-
-/**
-  * @brief  DMA IRDA communication error callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void IRDA_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  IRDA_HandleTypeDef* hirda = ( IRDA_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  hirda->RxXferCount = 0;
-  hirda->TxXferCount = 0;
-  hirda->ErrorCode |= HAL_IRDA_ERROR_DMA; 
-  hirda->State= HAL_IRDA_STATE_READY;
-  
-  HAL_IRDA_ErrorCallback(hirda);
-}
-
-/**
-  * @brief  This function handles IRDA Communication Timeout.
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @param  Flag: specifies the IRDA flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_WaitOnFlagUntilTimeout(IRDA_HandleTypeDef *hirda, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_IRDA_GET_FLAG(hirda, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
-          hirda->State= HAL_IRDA_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hirda);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_IRDA_GET_FLAG(hirda, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-          __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
-          hirda->State= HAL_IRDA_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hirda);
-        
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Send an amount of data in non-blocking mode. 
-  *         Function called under interruption only, once
-  *         interruptions have been enabled by HAL_IRDA_Transmit_IT()      
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda)
-{
-  uint16_t* tmp = 0;
-  uint32_t  tmp1 = 0;
-
-  tmp1 = hirda->State;
-  if((tmp1 == HAL_IRDA_STATE_BUSY_TX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
-  {
-    if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) hirda->pTxBuffPtr;
-      WRITE_REG(hirda->Instance->DR, (uint16_t)(*tmp & IRDA_DR_MASK_U16_9DATABITS));
-      if(hirda->Init.Parity == IRDA_PARITY_NONE)
-      {
-        hirda->pTxBuffPtr += 2;
-      }
-      else
-      {
-        hirda->pTxBuffPtr += 1;
-      }
-    } 
-    else
-    {
-      WRITE_REG(hirda->Instance->DR, (uint8_t)(*hirda->pTxBuffPtr++ & IRDA_DR_MASK_U8_8DATABITS));
-    }
-    
-    if(--hirda->TxXferCount == 0)
-    {
-      /* Disable the IRDA Transmit Data Register Empty Interrupt */
-      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TXE);
-     
-      /* Enable the IRDA Transmit Complete Interrupt */    
-      __HAL_IRDA_ENABLE_IT(hirda, IRDA_IT_TC);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  hirda: pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_EndTransmit_IT(IRDA_HandleTypeDef *hirda)
-{
-  /* Disable the IRDA Transmit Complete Interrupt */    
-  __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_TC);
-  
-  /* Check if a receive process is ongoing or not */
-  if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-  {
-    hirda->State = HAL_IRDA_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
-    /* Disable the IRDA Parity Error Interrupt */
-    __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-
-    hirda->State = HAL_IRDA_STATE_READY;
-  }
-  
-  HAL_IRDA_TxCpltCallback(hirda);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode. 
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef IRDA_Receive_IT(IRDA_HandleTypeDef *hirda)
-{
-  uint16_t* tmp = 0;
-  uint32_t tmp1 = 0;
-
-  tmp1 = hirda->State;  
-  if((tmp1 == HAL_IRDA_STATE_BUSY_RX) || (tmp1 == HAL_IRDA_STATE_BUSY_TX_RX))
-  {
-    if(hirda->Init.WordLength == IRDA_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) hirda->pRxBuffPtr;
-      if(hirda->Init.Parity == IRDA_PARITY_NONE)
-      {
-        *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_9DATABITS);
-        hirda->pRxBuffPtr += 2;
-      }
-      else
-      {
-        *tmp = (uint16_t)(hirda->Instance->DR & IRDA_DR_MASK_U16_8DATABITS);
-        hirda->pRxBuffPtr += 1;
-      }
-    } 
-    else
-    {
-      if(hirda->Init.Parity == IRDA_PARITY_NONE)
-      {
-        *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_8DATABITS);
-      }
-      else
-      {
-        *hirda->pRxBuffPtr++ = (uint8_t)(hirda->Instance->DR & IRDA_DR_MASK_U8_7DATABITS);
-      }
-    }
-
-    if(--hirda->RxXferCount == 0)
-    {
-
-      __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_RXNE);
-      
-      if(hirda->State == HAL_IRDA_STATE_BUSY_TX_RX) 
-      {
-        hirda->State = HAL_IRDA_STATE_BUSY_TX;
-      }
-      else
-      {
-        /* Disable the IRDA Parity Error Interrupt */
-        __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_PE);
-
-        /* Disable the IRDA Error Interrupt: (Frame error, noise error, overrun error) */
-        __HAL_IRDA_DISABLE_IT(hirda, IRDA_IT_ERR);
-
-        hirda->State = HAL_IRDA_STATE_READY;
-      }
-      HAL_IRDA_RxCpltCallback(hirda);
-
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Configures the IRDA peripheral. 
-  * @param  hirda: Pointer to a IRDA_HandleTypeDef structure that contains
-  *                the configuration information for the specified IRDA module.
-  * @retval None
-  */
-static void IRDA_SetConfig(IRDA_HandleTypeDef *hirda)
-{
-  /* Check the parameters */
-  assert_param(IS_IRDA_INSTANCE(hirda->Instance));
-  assert_param(IS_IRDA_BAUDRATE(hirda->Init.BaudRate));  
-  assert_param(IS_IRDA_WORD_LENGTH(hirda->Init.WordLength));
-  assert_param(IS_IRDA_PARITY(hirda->Init.Parity));
-  assert_param(IS_IRDA_MODE(hirda->Init.Mode));
-  
-  /*-------------------------- IRDA CR2 Configuration ------------------------*/
-  /* Clear STOP[13:12] bits */
-  CLEAR_BIT(hirda->Instance->CR2, USART_CR2_STOP);
-  
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Configure the USART Word Length, Parity and mode: 
-     Set the M bits according to hirda->Init.WordLength value 
-     Set PCE and PS bits according to hirda->Init.Parity value
-     Set TE and RE bits according to hirda->Init.Mode value */
-  MODIFY_REG(hirda->Instance->CR1,
-             ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)),
-             (uint32_t)hirda->Init.WordLength | hirda->Init.Parity | hirda->Init.Mode);
-  
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
-  /* Clear CTSE and RTSE bits */
-  CLEAR_BIT(hirda->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
-  
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  if(hirda->Instance == USART1)
-  {
-    hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK2Freq(), hirda->Init.BaudRate);
-  }
-  else
-  {
-    hirda->Instance->BRR = IRDA_BRR(HAL_RCC_GetPCLK1Freq(), hirda->Init.BaudRate);
-  }
-}
-/**
-  * @}
-  */
-
-#endif /* HAL_IRDA_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_irda.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,535 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_irda.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   This file contains all the functions prototypes for the IRDA 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_IRDA_H
-#define __STM32L1xx_HAL_IRDA_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup IRDA
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup IRDA_Exported_Types IRDA Exported Types
-  * @{
-  */ 
-
-/**
-  * @brief IRDA Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the IRDA communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (hirda->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref IRDA_Word_Length */
-
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref IRDA_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref IRDA_Transfer_Mode */
-                                            
-  uint8_t  Prescaler;                 /*!< Specifies the Prescaler */
-  
-  uint32_t IrDAMode;                  /*!< Specifies the IrDA mode
-                                           This parameter can be a value of @ref IRDA_Low_Power */
-}IRDA_InitTypeDef;
-
-/** 
-  * @brief HAL IRDA State structures definition  
-  */ 
-typedef enum
-{
-  HAL_IRDA_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized */
-  HAL_IRDA_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_IRDA_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
-  HAL_IRDA_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
-  HAL_IRDA_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
-  HAL_IRDA_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_IRDA_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_IRDA_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_IRDA_StateTypeDef;
-
-/** 
-  * @brief  HAL IRDA Error Code structure definition  
-  */ 
-typedef enum
-{
-  HAL_IRDA_ERROR_NONE      = 0x00,    /*!< No error            */
-  HAL_IRDA_ERROR_PE        = 0x01,    /*!< Parity error        */
-  HAL_IRDA_ERROR_NE        = 0x02,    /*!< Noise error         */
-  HAL_IRDA_ERROR_FE        = 0x04,    /*!< frame error         */
-  HAL_IRDA_ERROR_ORE       = 0x08,    /*!< Overrun error       */
-  HAL_IRDA_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
-}HAL_IRDA_ErrorTypeDef;
-
-/** 
-  * @brief  IRDA handle Structure definition  
-  */  
-typedef struct
-{
-  USART_TypeDef               *Instance;        /* USART registers base address       */
-  
-  IRDA_InitTypeDef            Init;             /* IRDA communication parameters      */
-  
-  uint8_t                     *pTxBuffPtr;      /* Pointer to IRDA Tx transfer Buffer */
-  
-  uint16_t                    TxXferSize;       /* IRDA Tx Transfer size              */
-  
-  uint16_t                    TxXferCount;      /* IRDA Tx Transfer Counter           */
-  
-  uint8_t                     *pRxBuffPtr;      /* Pointer to IRDA Rx transfer Buffer */
-  
-  uint16_t                    RxXferSize;       /* IRDA Rx Transfer size              */
-  
-  uint16_t                    RxXferCount;      /* IRDA Rx Transfer Counter           */  
-  
-  DMA_HandleTypeDef           *hdmatx;          /* IRDA Tx DMA Handle parameters      */
-    
-  DMA_HandleTypeDef           *hdmarx;          /* IRDA Rx DMA Handle parameters      */
-  
-  HAL_LockTypeDef             Lock;            /* Locking object                     */
-  
-  __IO HAL_IRDA_StateTypeDef  State;           /* IRDA communication state            */
-  
-  __IO HAL_IRDA_ErrorTypeDef  ErrorCode;        /* IRDA Error code                    */
-  
-}IRDA_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Constants IRDA Exported constants
-  * @{
-  */
-
-/** @defgroup IRDA_Word_Length IRDA Word Length
-  * @{
-  */
-#define IRDA_WORDLENGTH_8B                  ((uint32_t)0x00000000)
-#define IRDA_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-#define IS_IRDA_WORD_LENGTH(LENGTH) (((LENGTH) == IRDA_WORDLENGTH_8B) || \
-                                     ((LENGTH) == IRDA_WORDLENGTH_9B))
-/**
-  * @}
-  */
-
-
-/** @defgroup IRDA_Parity IRDA Parity 
-  * @{
-  */ 
-#define IRDA_PARITY_NONE                    ((uint32_t)0x00000000)
-#define IRDA_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define IRDA_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-#define IS_IRDA_PARITY(PARITY) (((PARITY) == IRDA_PARITY_NONE) || \
-                                ((PARITY) == IRDA_PARITY_EVEN) || \
-                                ((PARITY) == IRDA_PARITY_ODD))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup IRDA_Transfer_Mode IRDA Transfer Mode  
-  * @{
-  */ 
-#define IRDA_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define IRDA_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define IRDA_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_IRDA_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x000000))
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Low_Power IRDA Low Power 
-  * @{
-  */
-#define IRDA_POWERMODE_LOWPOWER                  ((uint32_t)USART_CR3_IRLP)
-#define IRDA_POWERMODE_NORMAL                    ((uint32_t)0x00000000)
-#define IS_IRDA_POWERMODE(MODE) (((MODE) == IRDA_POWERMODE_LOWPOWER) || \
-                                 ((MODE) == IRDA_POWERMODE_NORMAL))
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Flags IRDA Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define IRDA_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define IRDA_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define IRDA_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define IRDA_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define IRDA_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define IRDA_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define IRDA_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define IRDA_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Interrupt_definition IRDA Interrupt Definitions
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the XX register
-  *           - Y  : Interrupt source register (4 bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *
-  * @{
-  */
-
-#define IRDA_IT_PE                          ((uint32_t)0x10000100)
-#define IRDA_IT_TXE                         ((uint32_t)0x10000080)
-#define IRDA_IT_TC                          ((uint32_t)0x10000040)
-#define IRDA_IT_RXNE                        ((uint32_t)0x10000020)
-#define IRDA_IT_IDLE                        ((uint32_t)0x10000010)
-
-#define IRDA_IT_LBD                         ((uint32_t)0x20000040)
-
-#define IRDA_IT_CTS                         ((uint32_t)0x30000400)
-#define IRDA_IT_ERR                         ((uint32_t)0x30000001)
-
-/**
-  * @}
-  */
-
-/** @defgroup IRDA_Interruption_Mask    IRDA interruptions flag mask
-  * @{
-  */ 
-#define IRDA_IT_MASK  ((uint32_t)0x0000FFFF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup IRDA_Exported_Macros IRDA Exported Macros
-  * @{
-  */
-
-/** @brief Reset IRDA handle state
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
-
-/** @brief  Flushs the IRDA DR register 
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  */
-#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Checks whether the specified IRDA flag is set or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg IRDA_FLAG_TXE:  Transmit data register empty flag
-  *            @arg IRDA_FLAG_TC:   Transmission Complete flag
-  *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag
-  *            @arg IRDA_FLAG_IDLE: Idle Line detection flag
-  *            @arg IRDA_FLAG_ORE:  OverRun Error flag
-  *            @arg IRDA_FLAG_NE:   Noise Error flag
-  *            @arg IRDA_FLAG_FE:   Framing Error flag
-  *            @arg IRDA_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clears the specified IRDA pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg IRDA_FLAG_TC:   Transmission Complete flag.
-  *            @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the IRDA PE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
-                                               (__HANDLE__)->Instance->DR;}while(0)
-/** @brief  Clear the IRDA FE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA NE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA ORE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the IRDA IDLE pending flag.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enables the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to enable.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:   Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_PE:   Parity Error interrupt
-  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                        (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & IRDA_IT_MASK)))
-
-/** @brief  Disables the specified IRDA interrupt.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __INTERRUPT__: specifies the IRDA interrupt source to disable.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:   Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg IRDA_IT_PE:   Parity Error interrupt
-  *            @arg IRDA_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                        (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & IRDA_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
-    
-/** @brief  Checks whether the specified IRDA interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __IT__: specifies the IRDA interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg IRDA_IT_TC:  Transmission complete interrupt
-  *            @arg IRDA_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg IRDA_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_ERR: Error interrupt
-  *            @arg IRDA_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_IRDA_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
-
-/** @brief  Enable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */ 
-#define __HAL_IRDA_ENABLE(__HANDLE__)                   (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/** @brief  Disable UART/USART associated to IRDA Handle
-  * @param  __HANDLE__: specifies the IRDA Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_IRDA_DISABLE(__HANDLE__)                  (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup IRDA_Private_Macros   IRDA Private Macros
-  * @{
-  */
-
-#define IRDA_DIV(__PCLK__, __BAUD__)                    (((__PCLK__)*25)/(4*(__BAUD__)))
-#define IRDA_DIVMANT(__PCLK__, __BAUD__)                (IRDA_DIV((__PCLK__), (__BAUD__))/100)
-#define IRDA_DIVFRAQ(__PCLK__, __BAUD__)                (((IRDA_DIV((__PCLK__), (__BAUD__)) - (IRDA_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-#define IRDA_BRR(__PCLK__, __BAUD__)                    ((IRDA_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(IRDA_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
-
-/** @brief  Ensure that IRDA Baud rate is less or equal to maximum value
-  * @param  __BAUDRATE__: specifies the IRDA Baudrate set by the user.
-  * @retval True or False
-  */   
-#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
-                                
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IRDA_Exported_Functions IRDA Exported Functions
-  * @{
-  */
-  
-/** @addtogroup IRDA_Exported_Functions_Group1 IrDA Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_IRDA_Init(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DeInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspInit(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_MspDeInit(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group2 IO operation functions 
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_Receive_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);
-HAL_StatusTypeDef HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_IRQHandler(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef *hirda);
-void HAL_IRDA_ErrorCallback(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/** @addtogroup IRDA_Exported_Functions_Group3 Peripheral State and Errors functions 
-  * @{
-  */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_IRDA_StateTypeDef HAL_IRDA_GetState(IRDA_HandleTypeDef *hirda);
-uint32_t              HAL_IRDA_GetError(IRDA_HandleTypeDef *hirda);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_IRDA_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,360 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_iwdg.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   IWDG HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the IWDG peripheral:
-  *           + Initialization and Configuration functions
-  *           + IO operation functions
-  *           + Peripheral State functions
-  *         
-  @verbatim 
-  
-================================================================================
-                    ##### IWDG specific features #####
-================================================================================
-    [..] 
-    (+) The IWDG can be started by either software or hardware (configurable
-         through option byte).
-    (+) The IWDG is clocked by its own dedicated Low-Speed clock (LSI) and
-         thus stays active even if the main clock fails.
-      (+) Once the IWDG is started, the LSI is forced ON and cannot be disabled
-         (LSI cannot be disabled too), and the counter starts counting down from 
-         the reset value of 0xFFF. When it reaches the end of count value (0x000)
-         a system reset is generated.
-    (+) The IWDG counter should be refreshed at regular intervals, otherwise the
-         watchdog generates an MCU reset when the counter reaches 0.          
-    (+) The IWDG is implemented in the VDD voltage domain that is still functional
-         in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).
-      (+) IWDGRST flag in RCC_CSR register can be used to inform when an IWDG
-         reset occurs.
-
-    (+) Min-max timeout value @37KHz (LSI): ~108us / ~28.3s
-         The IWDG timeout may vary due to LSI frequency dispersion. STM32L1xx
-         devices provide the capability to measure the LSI frequency (LSI clock
-         connected internally to TIM10 CH1 input capture). The measured value
-         can be used to have an IWDG timeout with an acceptable accuracy. 
-         For more information, please refer to the STM32L1xx Reference manual.
-
-                     ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      (+) Set the IWDG prescaler and reload value 
-          using HAL_IWDG_Init() function.
-      (+) Use IWDG using HAL_IWDG_Start() function to:
-          (++) Enable write access to IWDG_PR and IWDG_RLR registers.   
-          (++) Configure the IWDG prescaler and counter reload values.
-          (++) Reload IWDG counter with value defined in the IWDG_RLR register.
-          (++) Start the IWDG, when the IWDG is used in software mode (no need 
-               to enable the LSI, it will be enabled by hardware).
-      (+) Then the application program must refresh the IWDG counter at regular
-          intervals during normal operation to prevent an MCU reset, using
-          HAL_IWDG_Refresh() function.  
-     
-     *** IWDG HAL driver macros list ***
-     ====================================
-     [..]
-       Below the list of most used macros in IWDG HAL driver.
-       
-      (+) __HAL_IWDG_START: Enable the IWDG peripheral
-      (+) __HAL_IWDG_RELOAD_COUNTER: Reloads IWDG counter with value defined in the reload register    
-      (+) __HAL_IWDG_ENABLE_WRITE_ACCESS : Enable write access to IWDG_PR and IWDG_RLR registers
-      (+) __HAL_IWDG_DISABLE_WRITE_ACCESS : Disable write access to IWDG_PR and IWDG_RLR registers
-      (+) __HAL_IWDG_GET_FLAG: Get the selected IWDG's flag status
-      (+) __HAL_IWDG_CLEAR_FLAG: Clear the IWDG's pending flags      
-            
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup IWDG IWDG
-  * @brief IWDG HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_IWDG_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup IWDG_Private_Defines IWDG Private Defines
-  * @{
-  */
-
-#define HAL_IWDG_DEFAULT_TIMEOUT (uint32_t)1000
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Functions IWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
- ===============================================================================
-          ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
-      (+) Initialize the IWDG according to the specified parameters 
-          in the IWDG_InitTypeDef and create the associated handle
-      (+) Initialize the IWDG MSP
-      (+) DeInitialize IWDG MSP 
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the IWDG according to the specified
-  *         parameters in the IWDG_InitTypeDef and creates the associated handle.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg)
-{
-  /* Check the IWDG handle allocation */
-  if(hiwdg == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_IWDG_ALL_INSTANCE(hiwdg->Instance));
-  assert_param(IS_IWDG_PRESCALER(hiwdg->Init.Prescaler));
-  assert_param(IS_IWDG_RELOAD(hiwdg->Init.Reload));
-  
-  /* Check pending flag, if previous update not done, return error */
-  if((__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_PVU) != RESET)
-     &&(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET))
-  {
-    return HAL_ERROR;
-  }
-    
-  if(hiwdg->State == HAL_IWDG_STATE_RESET)
-  {  
-    /* Init the low level hardware */
-    HAL_IWDG_MspInit(hiwdg);
-  }
-  
-  /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_BUSY;  
-  
-  /* Enable write access to IWDG_PR and IWDG_RLR registers */  
-  __HAL_IWDG_ENABLE_WRITE_ACCESS(hiwdg);
-  
-  /* Write to IWDG registers the IWDG_Prescaler & IWDG_Reload values to work with */
-  MODIFY_REG(hiwdg->Instance->PR, IWDG_PR_PR, hiwdg->Init.Prescaler);
-  MODIFY_REG(hiwdg->Instance->RLR, IWDG_RLR_RL, hiwdg->Init.Reload);
- 
-  /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the IWDG MSP.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval None
-  */
-__weak void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_IWDG_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group2 IO operation functions  
- *  @brief   IO operation functions  
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) Start the IWDG.
-      (+) Refresh the IWDG.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the IWDG.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg)
-{
-  /* Process Locked */
-  __HAL_LOCK(hiwdg); 
-  
-    /* Change IWDG peripheral state */  
-  hiwdg->State = HAL_IWDG_STATE_BUSY;
-
-  /* Start the IWDG peripheral */
-  __HAL_IWDG_START(hiwdg);
-  
-    /* Reload IWDG counter with value defined in the RLR register */
-  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-
-  /* Change IWDG peripheral state */    
-  hiwdg->State = HAL_IWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hiwdg);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Refreshes the IWDG.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg)
-{
-  uint32_t tickstart = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hiwdg); 
-  
-    /* Change IWDG peripheral state */
-  hiwdg->State = HAL_IWDG_STATE_BUSY;
-  
-  tickstart = HAL_GetTick();
-
-  /* Wait until RVU flag is RESET */
-  while(__HAL_IWDG_GET_FLAG(hiwdg, IWDG_FLAG_RVU) != RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > HAL_IWDG_DEFAULT_TIMEOUT)
-    { 
-      /* Set IWDG state */
-      hiwdg->State = HAL_IWDG_STATE_TIMEOUT;
-
-       /* Process unlocked */
-      __HAL_UNLOCK(hiwdg);
-
-      return HAL_TIMEOUT;
-    } 
-  }
-  
-  /* Reload IWDG counter with value defined in the reload register */
-  __HAL_IWDG_RELOAD_COUNTER(hiwdg);
-    
-  /* Change IWDG peripheral state */    
-  hiwdg->State = HAL_IWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hiwdg);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions 
- *  @brief    Peripheral State functions. 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the IWDG state.
-  * @param  hiwdg: pointer to a IWDG_HandleTypeDef structure that contains
-  *                the configuration information for the specified IWDG module.
-  * @retval HAL state
-  */
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg)
-{
-  return hiwdg->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_IWDG_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_iwdg.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,291 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_iwdg.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of IWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_IWDG_H
-#define __STM32L1xx_HAL_IWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup IWDG
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Types IWDG Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  IWDG HAL State Structure definition  
-  */ 
-typedef enum
-{
-  HAL_IWDG_STATE_RESET     = 0x00,  /*!< IWDG not yet initialized or disabled */
-  HAL_IWDG_STATE_READY     = 0x01,  /*!< IWDG initialized and ready for use   */
-  HAL_IWDG_STATE_BUSY      = 0x02,  /*!< IWDG internal process is ongoing     */
-  HAL_IWDG_STATE_TIMEOUT   = 0x03,  /*!< IWDG timeout state                   */
-  HAL_IWDG_STATE_ERROR     = 0x04   /*!< IWDG error state                     */
-    
-}HAL_IWDG_StateTypeDef;
-
-/** 
-  * @brief  IWDG Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Select the prescaler of the IWDG.  
-                            This parameter can be a value of @ref IWDG_Prescaler */
-  
-  uint32_t Reload;     /*!< Specifies the IWDG down-counter reload value. 
-                            This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
-
-}IWDG_InitTypeDef;
-
-/** 
-  * @brief  IWDG Handle Structure definition  
-  */ 
-typedef struct
-{
-  IWDG_TypeDef                 *Instance;  /*!< Register base address    */ 
-  
-  IWDG_InitTypeDef             Init;       /*!< IWDG required parameters */
-  
-  HAL_LockTypeDef              Lock;      /*!< IWDG Locking object      */
-  
-  __IO HAL_IWDG_StateTypeDef   State;      /*!< IWDG communication state */
-  
-}IWDG_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Constants IWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup IWDG_Registers_BitMask IWDG_Registers_BitMask
-  * @brief IWDG registers bit mask
-  * @{
-  */
-/* --- KR Register ---*/
-/* KR register bit mask */
-#define KR_KEY_RELOAD           ((uint32_t)0xAAAA)  /*!< IWDG Reload Counter Enable   */
-#define KR_KEY_ENABLE           ((uint32_t)0xCCCC)  /*!< IWDG Peripheral Enable       */
-#define KR_KEY_EWA              ((uint32_t)0x5555)  /*!< IWDG KR Write Access Enable  */
-#define KR_KEY_DWA              ((uint32_t)0x0000)  /*!< IWDG KR Write Access Disable */
-
-#define IS_IWDG_KR(__KR__) (((__KR__) == KR_KEY_RELOAD) || \
-                            ((__KR__) == KR_KEY_ENABLE))|| \
-                            ((__KR__) == KR_KEY_EWA))   || \
-                            ((__KR__) == KR_KEY_DWA))
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Flag_definition IWDG_Flag_definition
-  * @{
-  */ 
-#define IWDG_FLAG_PVU   ((uint32_t)IWDG_SR_PVU)  /*!< Watchdog counter prescaler value update Flag */
-#define IWDG_FLAG_RVU   ((uint32_t)IWDG_SR_RVU)  /*!< Watchdog counter reload value update Flag    */
-  
-/**
-  * @}
-  */
-
-/** @defgroup IWDG_Prescaler IWDG_Prescaler
-  * @{
-  */ 
-#define IWDG_PRESCALER_4     ((uint8_t)0x00)                            /*!< IWDG prescaler set to 4   */
-#define IWDG_PRESCALER_8     ((uint8_t)(IWDG_PR_PR_0))                  /*!< IWDG prescaler set to 8   */
-#define IWDG_PRESCALER_16    ((uint8_t)(IWDG_PR_PR_1))                  /*!< IWDG prescaler set to 16  */
-#define IWDG_PRESCALER_32    ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 32  */
-#define IWDG_PRESCALER_64    ((uint8_t)(IWDG_PR_PR_2))                  /*!< IWDG prescaler set to 64  */
-#define IWDG_PRESCALER_128   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0))   /*!< IWDG prescaler set to 128 */
-#define IWDG_PRESCALER_256   ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1))   /*!< IWDG prescaler set to 256 */
-
-#define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4)  || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_8)  || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_16) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_32) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_64) || \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
-                                          ((__PRESCALER__) == IWDG_PRESCALER_256))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup IWDG_Reload_Value IWDG_Reload_Value
-  * @{
-  */ 
-#define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup IWDG_Exported_Macros IWDG Exported Macros
-  * @{
-  */
-
-/** @brief Reset IWDG handle state
-  * @param  __HANDLE__: IWDG handle.
-  * @retval None
-  */
-#define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__)   ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
-
-/**
-  * @brief  Enables the IWDG peripheral.
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_START(__HANDLE__)                WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_ENABLE)
-
-/**
-  * @brief  Reloads IWDG counter with value defined in the reload register
-  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__)       WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_RELOAD)
-
-/**
-  * @brief  Enables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_ENABLE_WRITE_ACCESS(__HANDLE__)  WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_EWA)
-
-/**
-  * @brief  Disables write access to IWDG_PR and IWDG_RLR registers.
-  * @param  __HANDLE__: IWDG handle
-  * @retval None
-  */
-#define __HAL_IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, KR_KEY_DWA)
-
-/**
-  * @brief  Gets the selected IWDG's flag status.
-  * @param  __HANDLE__: IWDG handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
-  *            @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup IWDG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup IWDG_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  ********************************/
-HAL_StatusTypeDef     HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
-void                  HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup IWDG_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ****************************************************/
-HAL_StatusTypeDef     HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
-HAL_StatusTypeDef     HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup IWDG_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  ************************************************/
-HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_IWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,610 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_lcd.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   LCD Controller HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the LCD Controller (LCD) peripheral:
-  *           + Initialization/de-initialization methods
-  *           + I/O operation methods
-  *           + Peripheral State methods
-  *           
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================   
-      [..] The LCD HAL driver can be used as follows:
-    
-      (#) Declare a LCD_HandleTypeDef handle structure.
-
-      (#) Initialize the LCD low level resources by implement the HAL_LCD_MspInit() API:
-          (##) Enable the LCDCLK (same as RTCCLK): to configure the RTCCLK/LCDCLK, proceed as follows:
-               (+) Use RCC function HAL_RCCEx_PeriphCLKConfig in indicating RCC_PERIPHCLK_LCD and 
-                  selected clock source (HSE, LSI or LSE)
-             
-      -@- The frequency generator allows you to achieve various LCD frame rates 
-            starting from an LCD input clock frequency (LCDCLK) which can vary 
-            from 32 kHz up to 1 MHz.
-          (##) LCD pins configuration:
-              (+) Enable the clock for the LCD GPIOs.
-              (+) Configure these LCD pins as alternate function no-pull.
-          (##) Enable the LCD interface clock.
-
-      (#) Program the Prescaler, Divider, Blink mode, Blink Frequency Duty, Bias,
-           Voltage Source, Dead Time, Pulse On Duration and Contrast in the hlcd Init structure.
-
-      (#) Initialize the LCD registers by calling the HAL_LCD_Init() API.
-
-      -@- The HAL_LCD_Init() API configures also the low level Hardware GPIO, CLOCK, ...etc)
-          by calling the custumed HAL_LCD_MspInit() API.
-      -@- After calling the HAL_LCD_Init() the LCD RAM memory is cleared
-
-      (#) Optionally you can update the LCD configuration using these macros:
-              (+) LCD High Drive using the __HAL_LCD_HIGHDRIVER_ENABLE() and __HAL_LCD_HIGHDRIVER_DISABLE() macros
-              (+) LCD Pulse ON Duration using the __HAL_LCD_PULSEONDURATION_CONFIG() macro
-              (+) LCD Dead Time using the __HAL_LCD_DEADTIME_CONFIG() macro  
-              (+) The LCD Blink mode and frequency using the __HAL_LCD_BLINK_CONFIG() macro
-              (+) The LCD Contrast using the __HAL_LCD_CONTRAST_CONFIG() macro  
-
-      (#) Write to the LCD RAM memory using the HAL_LCD_Write() API, this API can be called
-          more time to update the different LCD RAM registers before calling 
-          HAL_LCD_UpdateDisplayRequest() API.
-
-      (#) The HAL_LCD_Clear() API can be used to clear the LCD RAM memory.
-
-      (#) When LCD RAM memory is updated enable the update display request using
-          the HAL_LCD_UpdateDisplayRequest() API.
-
-      [..] LCD and low power modes:
-           (#) The LCD remain active during STOP mode.
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#ifdef HAL_LCD_MODULE_ENABLED
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\
-    defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE)
-
-/** @defgroup LCD LCD
-  * @brief LCD HAL module driver
-  * @{
-  */
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup LCD_Private_Defines LCD Private Defines
-  * @{
-  */
-
-#define LCD_TIMEOUT_VALUE             1000
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Functions LCD Exported Functions
-  * @{
-  */
-
-/** @defgroup LCD_Exported_Functions_Group1 Initialization/de-initialization methods 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim    
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================  
-    [..]
-
-@endverbatim
-  * @{
-  */
- 
-/**
-  * @brief  DeInitializes the LCD peripheral. 
-  * @param  hlcd: LCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd)
-{
-  /* Check the LCD handle allocation */
-  if(hlcd == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
-
-  hlcd->State = HAL_LCD_STATE_BUSY;
-  
-  /* DeInit the low level hardware */
-  HAL_LCD_MspDeInit(hlcd);
-  
-  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
-  hlcd->State = HAL_LCD_STATE_RESET;
-    
-  /* Release Lock */
-  __HAL_UNLOCK(hlcd);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Initializes the LCD peripheral according to the specified parameters 
-  *         in the LCD_InitStruct.
-  * @note   This function can be used only when the LCD is disabled.  
-  * @param  hlcd: LCD handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Init(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00;
-  uint8_t counter = 0;
-    
-  /* Check the LCD handle allocation */
-  if(hlcd == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check function parameters */
-  assert_param(IS_LCD_ALL_INSTANCE(hlcd->Instance));
-  assert_param(IS_LCD_PRESCALER(hlcd->Init.Prescaler));
-  assert_param(IS_LCD_DIVIDER(hlcd->Init.Divider));
-  assert_param(IS_LCD_DUTY(hlcd->Init.Duty));
-  assert_param(IS_LCD_BIAS(hlcd->Init.Bias));  
-  assert_param(IS_LCD_VOLTAGE_SOURCE(hlcd->Init.VoltageSource));
-  assert_param(IS_LCD_PULSE_ON_DURATION(hlcd->Init.PulseOnDuration));
-  assert_param(IS_LCD_DEAD_TIME(hlcd->Init.DeadTime));
-  assert_param(IS_LCD_CONTRAST(hlcd->Init.Contrast)); 
-  assert_param(IS_LCD_BLINK_FREQUENCY(hlcd->Init.BlinkFrequency)); 
-  assert_param(IS_LCD_BLINK_MODE(hlcd->Init.BlinkMode)); 
-  assert_param(IS_LCD_MUXSEGMENT(hlcd->Init.MuxSegment));
-  
-  if(hlcd->State == HAL_LCD_STATE_RESET)
-  {
-    /* Initialize the low level hardware (MSP) */
-    HAL_LCD_MspInit(hlcd);
-  }
-  
-  hlcd->State = HAL_LCD_STATE_BUSY;
-  
-  /* Disable the peripheral */
-  __HAL_LCD_DISABLE(hlcd);
-  
-  /* Clear the LCD_RAM registers and enable the display request by setting the UDR bit
-     in the LCD_SR register */
-  for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
-  {
-    hlcd->Instance->RAM[counter] = 0;
-  }
-  /* Enable the display request */
-  hlcd->Instance->SR |= LCD_SR_UDR;
-  
-  /* Configure the LCD Prescaler, Divider, Blink mode and Blink Frequency: 
-  Set PS[3:0] bits according to hlcd->Init.Prescaler value 
-     Set DIV[3:0] bits according to hlcd->Init.Divider value
-     Set BLINK[1:0] bits according to hlcd->Init.BlinkMode value
-     Set BLINKF[2:0] bits according to hlcd->Init.BlinkFrequency value
-     Set DEAD[2:0] bits according to hlcd->Init.DeadTime value
-     Set PON[2:0] bits according to hlcd->Init.PulseOnDuration value 
-     Set CC[2:0] bits according to hlcd->Init.Contrast value */
-   MODIFY_REG(hlcd->Instance->FCR, \
-      (LCD_FCR_PS | LCD_FCR_DIV | LCD_FCR_BLINK| LCD_FCR_BLINKF | \
-       LCD_FCR_DEAD | LCD_FCR_PON | LCD_FCR_CC), \
-      (hlcd->Init.Prescaler | hlcd->Init.Divider | hlcd->Init.BlinkMode | hlcd->Init.BlinkFrequency | \
-       hlcd->Init.DeadTime | hlcd->Init.PulseOnDuration | hlcd->Init.Contrast));
-
-  /* Wait until LCD Frame Control Register Synchronization flag (FCRSF) is set in the LCD_SR register 
-     This bit is set by hardware each time the LCD_FCR register is updated in the LCDCLK
-     domain. It is cleared by hardware when writing to the LCD_FCR register.*/
-  LCD_WaitForSynchro(hlcd);
-  
-  /* Configure the LCD Duty, Bias, Voltage Source, Dead Time, Pulse On Duration and Contrast: 
-     Set DUTY[2:0] bits according to hlcd->Init.Duty value 
-     Set BIAS[1:0] bits according to hlcd->Init.Bias value
-     Set VSEL bit according to hlcd->Init.VoltageSource value
-     Set MUX_SEG bit according to hlcd->Init.MuxSegment value */
-  MODIFY_REG(hlcd->Instance->CR, \
-    (LCD_CR_DUTY | LCD_CR_BIAS | LCD_CR_VSEL | LCD_CR_MUX_SEG), \
-    (hlcd->Init.Duty | hlcd->Init.Bias | hlcd->Init.VoltageSource | hlcd->Init.MuxSegment));
-  
-  /* Enable the peripheral */
-  __HAL_LCD_ENABLE(hlcd);
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-      
-  /* Wait Until the LCD is enabled */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_ENS) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    { 
-      hlcd->ErrorCode = HAL_LCD_ERROR_ENS;     
-      return HAL_TIMEOUT;
-    } 
-  }
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-  
-  /*!< Wait Until the LCD Booster is ready */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_RDY) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    {   
-      hlcd->ErrorCode = HAL_LCD_ERROR_RDY;  
-      return HAL_TIMEOUT;
-    } 
-  }
- 
-  /* Initialize the LCD state */
-  hlcd->ErrorCode = HAL_LCD_ERROR_NONE;
-  hlcd->State= HAL_LCD_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  LCD MSP DeInit.
-  * @param  hlcd: LCD handle
-  * @retval None
-  */
- __weak void HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_LCD_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  LCD MSP Init.
-  * @param  hlcd: LCD handle
-  * @retval None
-  */
- __weak void HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_LCD_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Exported_Functions_Group2 IO operation methods 
-  *  @brief LCD RAM functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
- [..] Using its double buffer memory the LCD controller ensures the coherency of the 
- displayed information without having to use interrupts to control LCD_RAM 
- modification.
- The application software can access the first buffer level (LCD_RAM) through 
- the APB interface. Once it has modified the LCD_RAM using the HAL_LCD_Write() API,
- it sets the UDR flag in the LCD_SR register using the HAL_LCD_UpdateDisplayRequest() API.
- This UDR flag (update display request) requests the updated information to be 
- moved into the second buffer level (LCD_DISPLAY).
- This operation is done synchronously with the frame (at the beginning of the 
- next frame), until the update is completed, the LCD_RAM is write protected and 
- the UDR flag stays high.
- Once the update is completed another flag (UDD - Update Display Done) is set and
- generates an interrupt if the UDDIE bit in the LCD_FCR register is set.
- The time it takes to update LCD_DISPLAY is, in the worst case, one odd and one 
- even frame.
- The update will not occur (UDR = 1 and UDD = 0) until the display is 
- enabled (LCDEN = 1).
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Writes a word in the specific LCD RAM.
-  * @param  hlcd: LCD handle
-  * @param  RAMRegisterIndex: specifies the LCD RAM Register.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_RAM_REGISTER0: LCD RAM Register 0
-  *     @arg LCD_RAM_REGISTER1: LCD RAM Register 1
-  *     @arg LCD_RAM_REGISTER2: LCD RAM Register 2
-  *     @arg LCD_RAM_REGISTER3: LCD RAM Register 3
-  *     @arg LCD_RAM_REGISTER4: LCD RAM Register 4
-  *     @arg LCD_RAM_REGISTER5: LCD RAM Register 5
-  *     @arg LCD_RAM_REGISTER6: LCD RAM Register 6 
-  *     @arg LCD_RAM_REGISTER7: LCD RAM Register 7  
-  *     @arg LCD_RAM_REGISTER8: LCD RAM Register 8
-  *     @arg LCD_RAM_REGISTER9: LCD RAM Register 9
-  *     @arg LCD_RAM_REGISTER10: LCD RAM Register 10
-  *     @arg LCD_RAM_REGISTER11: LCD RAM Register 11
-  *     @arg LCD_RAM_REGISTER12: LCD RAM Register 12 
-  *     @arg LCD_RAM_REGISTER13: LCD RAM Register 13 
-  *     @arg LCD_RAM_REGISTER14: LCD RAM Register 14 
-  *     @arg LCD_RAM_REGISTER15: LCD RAM Register 15
-  * @param  RAMRegisterMask: specifies the LCD RAM Register Data Mask.
-  * @param  Data: specifies LCD Data Value to be written.
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data)
-{
-  uint32_t tickstart = 0x00; 
-  
-  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
-  {
-    /* Check the parameters */
-    assert_param(IS_LCD_RAM_REGISTER(RAMRegisterIndex));
-    
-    if(hlcd->State == HAL_LCD_STATE_READY)
-    {
-      /* Process Locked */
-      __HAL_LOCK(hlcd);
-      hlcd->State = HAL_LCD_STATE_BUSY;
-      
-      /* Get timeout */
-      tickstart = HAL_GetTick();
-      
-      /*!< Wait Until the LCD is ready */
-      while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-        { 
-          hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
-          
-          /* Process Unlocked */
-          __HAL_UNLOCK(hlcd);
-          
-          return HAL_TIMEOUT;
-        } 
-      }
-    }
-    
-    /* Copy the new Data bytes to LCD RAM register */
-    MODIFY_REG(hlcd->Instance->RAM[RAMRegisterIndex], ~(RAMRegisterMask), Data);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief Clears the LCD RAM registers.
-  * @param hlcd: LCD handle
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_Clear(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00; 
-  uint32_t counter = 0;
-  
-  if((hlcd->State == HAL_LCD_STATE_READY) || (hlcd->State == HAL_LCD_STATE_BUSY))
-  {
-    /* Process Locked */
-    __HAL_LOCK(hlcd);
-    
-    hlcd->State = HAL_LCD_STATE_BUSY;
-    
-    /* Get timeout */
-    tickstart = HAL_GetTick();
-    
-    /*!< Wait Until the LCD is ready */
-    while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDR) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-      { 
-        hlcd->ErrorCode = HAL_LCD_ERROR_UDR;
-        
-        /* Process Unlocked */
-        __HAL_UNLOCK(hlcd);
-        
-        return HAL_TIMEOUT;
-      } 
-    }
-    /* Clear the LCD_RAM registers */
-    for(counter = LCD_RAM_REGISTER0; counter <= LCD_RAM_REGISTER15; counter++)
-    {
-      hlcd->Instance->RAM[counter] = 0;
-    }
-    
-    /* Update the LCD display */
-    HAL_LCD_UpdateDisplayRequest(hlcd);     
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Enables the Update Display Request.
-  * @param  hlcd: LCD handle
-  * @note   Each time software modifies the LCD_RAM it must set the UDR bit to 
-  *         transfer the updated data to the second level buffer. 
-  *         The UDR bit stays set until the end of the update and during this 
-  *         time the LCD_RAM is write protected. 
-  * @note   When the display is disabled, the update is performed for all 
-  *         LCD_DISPLAY locations.
-  *         When the display is enabled, the update is performed only for locations 
-  *         for which commons are active (depending on DUTY). For example if 
-  *         DUTY = 1/2, only the LCD_DISPLAY of COM0 and COM1 will be updated.    
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00;
-  
-  /* Clear the Update Display Done flag before starting the update display request */
-  __HAL_LCD_CLEAR_FLAG(hlcd, LCD_FLAG_UDD);
-  
-  /* Enable the display request */
-  hlcd->Instance->SR |= LCD_SR_UDR;
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-  
-  /*!< Wait Until the LCD display is done */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_UDD) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    { 
-      hlcd->ErrorCode = HAL_LCD_ERROR_UDD;
-      
-      /* Process Unlocked */
-      __HAL_UNLOCK(hlcd);
-  
-      return HAL_TIMEOUT;
-    }
-  }
-
-  hlcd->State = HAL_LCD_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hlcd);
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Exported_Functions_Group3 Peripheral State methods 
-  *  @brief   LCD State functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-     This subsection provides a set of functions allowing to control the LCD:
-      (+) HAL_LCD_GetState() API can be helpful to check in run-time the state of the LCD peripheral State. 
-      (+) HAL_LCD_GetError() API to return the LCD error code. 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Returns the LCD state.
-  * @param hlcd: LCD handle
-  * @retval HAL state
-  */
-HAL_LCD_StateTypeDef HAL_LCD_GetState(LCD_HandleTypeDef *hlcd)
-{
-  return hlcd->State;
-}
-
-/**
-  * @brief Return the LCD error code
-  * @param hlcd: LCD handle
-  * @retval LCD Error Code
-  */
-uint32_t HAL_LCD_GetError(LCD_HandleTypeDef *hlcd)
-{
-  return hlcd->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/** @defgroup LCD_Private_Functions LCD Private Functions
-  * @{
-  */
-
-/**
-  * @brief  Waits until the LCD FCR register is synchronized in the LCDCLK domain.
-  *   This function must be called after any write operation to LCD_FCR register.
-  * @retval None
-  */
-HAL_StatusTypeDef LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd)
-{
-  uint32_t tickstart = 0x00; 
-  
-  /* Get timeout */
-  tickstart = HAL_GetTick();
-
-  /* Loop until FCRSF flag is set */
-  while(__HAL_LCD_GET_FLAG(hlcd, LCD_FLAG_FCRSF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) > LCD_TIMEOUT_VALUE)
-    {
-      hlcd->ErrorCode = HAL_LCD_ERROR_FCRSF;
-      return HAL_TIMEOUT;
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE */
-
-#endif /* HAL_LCD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_lcd.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,763 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_lcd.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of LCD Controller HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_LCD_H
-#define __STM32L1xx_HAL_LCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L152xE) ||\
-    defined (STM32L162xC) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L162xE)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup LCD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Types LCD Exported Types
-  * @{
-  */
-
-/** 
-  * @brief LCD Init structure definition
-  */
-
-typedef struct
-{
-  uint32_t Prescaler;       /*!< Configures the LCD Prescaler. 
-                                 This parameter can be one value of @ref LCD_Prescaler */
-  uint32_t Divider;         /*!< Configures the LCD Divider.
-                                 This parameter can be one value of @ref LCD_Divider */
-  uint32_t Duty;            /*!< Configures the LCD Duty.
-                                 This parameter can be one value of @ref LCD_Duty */
-  uint32_t Bias;            /*!< Configures the LCD Bias.
-                                 This parameter can be one value of @ref LCD_Bias */ 
-  uint32_t VoltageSource;   /*!< Selects the LCD Voltage source.
-                                 This parameter can be one value of @ref LCD_Voltage_Source */  
-  uint32_t Contrast;        /*!< Configures the LCD Contrast.
-                                 This parameter can be one value of @ref LCD_Contrast */
-  uint32_t DeadTime;        /*!< Configures the LCD Dead Time.
-                                 This parameter can be one value of @ref LCD_DeadTime */
-  uint32_t PulseOnDuration; /*!< Configures the LCD Pulse On Duration.
-                                 This parameter can be one value of @ref LCD_PulseOnDuration */
-  uint32_t BlinkMode;       /*!< Configures the LCD Blink Mode.
-                                 This parameter can be one value of @ref LCD_BlinkMode */
-  uint32_t BlinkFrequency;  /*!< Configures the LCD Blink frequency.
-                                 This parameter can be one value of @ref LCD_BlinkFrequency */
-  uint32_t MuxSegment;      /*!< Enable or disable mux segment.
-                                 This parameter can be set to ENABLE or DISABLE. */ 
-}LCD_InitTypeDef;
-
-/** 
-  * @brief HAL LCD State structures definition
-  */ 
-typedef enum
-{
-  HAL_LCD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
-  HAL_LCD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_LCD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
-  HAL_LCD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_LCD_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_LCD_StateTypeDef;
-
-/** 
-  * @brief  HAL LCD Error Code structure definition
-  */ 
-typedef enum
-{
-  HAL_LCD_ERROR_NONE      = 0x00,    /*!< No error */
-  HAL_LCD_ERROR_FCRSF     = 0x01,    /*!< Synchro flag timeout error */
-  HAL_LCD_ERROR_UDR       = 0x02,    /*!< Update display request flag timeout error */
-  HAL_LCD_ERROR_UDD       = 0x04,    /*!< Update display done flag timeout error */
-  HAL_LCD_ERROR_ENS       = 0x08,    /*!< LCD enabled status flag timeout error */
-  HAL_LCD_ERROR_RDY       = 0x10     /*!< LCD Booster ready timeout error */
-}HAL_LCD_ErrorTypeDef;
-
-/** 
-  * @brief  UART handle Structure definition
-  */  
-typedef struct
-{
-  LCD_TypeDef                   *Instance;  /* LCD registers base address */
-  
-  LCD_InitTypeDef               Init;       /* LCD communication parameters */
-
-  HAL_LockTypeDef               Lock;       /* Locking object */
-
-  __IO HAL_LCD_StateTypeDef     State;      /* LCD communication state */
-  
-  __IO HAL_LCD_ErrorTypeDef     ErrorCode;  /* LCD Error code */
-  
-}LCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Constants LCD Exported Constants
-  * @{
-  */
-
-/** @defgroup LCD_Prescaler LCD Prescaler
-  * @{
-  */
-
-#define LCD_PRESCALER_1        ((uint32_t)0x00000000)  /*!< CLKPS = LCDCLK        */
-#define LCD_PRESCALER_2        ((uint32_t)0x00400000)  /*!< CLKPS = LCDCLK/2      */
-#define LCD_PRESCALER_4        ((uint32_t)0x00800000)  /*!< CLKPS = LCDCLK/4      */
-#define LCD_PRESCALER_8        ((uint32_t)0x00C00000)  /*!< CLKPS = LCDCLK/8      */
-#define LCD_PRESCALER_16       ((uint32_t)0x01000000)  /*!< CLKPS = LCDCLK/16     */
-#define LCD_PRESCALER_32       ((uint32_t)0x01400000)  /*!< CLKPS = LCDCLK/32     */
-#define LCD_PRESCALER_64       ((uint32_t)0x01800000)  /*!< CLKPS = LCDCLK/64     */
-#define LCD_PRESCALER_128      ((uint32_t)0x01C00000)  /*!< CLKPS = LCDCLK/128    */
-#define LCD_PRESCALER_256      ((uint32_t)0x02000000)  /*!< CLKPS = LCDCLK/256    */
-#define LCD_PRESCALER_512      ((uint32_t)0x02400000)  /*!< CLKPS = LCDCLK/512    */
-#define LCD_PRESCALER_1024     ((uint32_t)0x02800000)  /*!< CLKPS = LCDCLK/1024   */
-#define LCD_PRESCALER_2048     ((uint32_t)0x02C00000)  /*!< CLKPS = LCDCLK/2048   */
-#define LCD_PRESCALER_4096     ((uint32_t)0x03000000)  /*!< CLKPS = LCDCLK/4096   */
-#define LCD_PRESCALER_8192     ((uint32_t)0x03400000)  /*!< CLKPS = LCDCLK/8192   */
-#define LCD_PRESCALER_16384    ((uint32_t)0x03800000)  /*!< CLKPS = LCDCLK/16384  */
-#define LCD_PRESCALER_32768    ((uint32_t)LCD_FCR_PS)  /*!< CLKPS = LCDCLK/32768  */
-
-#define IS_LCD_PRESCALER(__PRESCALER__) (((__PRESCALER__) == LCD_PRESCALER_1)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_2)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_4)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_8)     || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_16)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_32)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_64)    || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_128)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_256)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_512)   || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_1024)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_2048)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_4096)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_8192)  || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_16384) || \
-                                         ((__PRESCALER__) == LCD_PRESCALER_32768))
-
-/**
-  * @}
-  */
-  
-/** @defgroup LCD_Divider LCD Divider
-  * @{
-  */
-
-#define LCD_DIVIDER_16    ((uint32_t)0x00000000)  /*!< LCD frequency = CLKPS/16 */
-#define LCD_DIVIDER_17    ((uint32_t)0x00040000)  /*!< LCD frequency = CLKPS/17 */
-#define LCD_DIVIDER_18    ((uint32_t)0x00080000)  /*!< LCD frequency = CLKPS/18 */
-#define LCD_DIVIDER_19    ((uint32_t)0x000C0000)  /*!< LCD frequency = CLKPS/19 */
-#define LCD_DIVIDER_20    ((uint32_t)0x00100000)  /*!< LCD frequency = CLKPS/20 */
-#define LCD_DIVIDER_21    ((uint32_t)0x00140000)  /*!< LCD frequency = CLKPS/21 */
-#define LCD_DIVIDER_22    ((uint32_t)0x00180000)  /*!< LCD frequency = CLKPS/22 */
-#define LCD_DIVIDER_23    ((uint32_t)0x001C0000)  /*!< LCD frequency = CLKPS/23 */
-#define LCD_DIVIDER_24    ((uint32_t)0x00200000)  /*!< LCD frequency = CLKPS/24 */
-#define LCD_DIVIDER_25    ((uint32_t)0x00240000)  /*!< LCD frequency = CLKPS/25 */
-#define LCD_DIVIDER_26    ((uint32_t)0x00280000)  /*!< LCD frequency = CLKPS/26 */
-#define LCD_DIVIDER_27    ((uint32_t)0x002C0000)  /*!< LCD frequency = CLKPS/27 */
-#define LCD_DIVIDER_28    ((uint32_t)0x00300000)  /*!< LCD frequency = CLKPS/28 */
-#define LCD_DIVIDER_29    ((uint32_t)0x00340000)  /*!< LCD frequency = CLKPS/29 */
-#define LCD_DIVIDER_30    ((uint32_t)0x00380000)  /*!< LCD frequency = CLKPS/30 */
-#define LCD_DIVIDER_31    ((uint32_t)LCD_FCR_DIV) /*!< LCD frequency = CLKPS/31 */
-
-#define IS_LCD_DIVIDER(__DIVIDER__) (((__DIVIDER__) == LCD_DIVIDER_16) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_17) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_18) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_19) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_20) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_21) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_22) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_23) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_24) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_25) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_26) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_27) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_28) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_29) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_30) || \
-                                     ((__DIVIDER__) == LCD_DIVIDER_31))
-
-/**
-  * @}
-  */
-
-
-/** @defgroup LCD_Duty LCD Duty
-  * @{
-  */
-  
-#define LCD_DUTY_STATIC                 ((uint32_t)0x00000000)            /*!< Static duty */
-#define LCD_DUTY_1_2                    (LCD_CR_DUTY_0)                   /*!< 1/2 duty    */
-#define LCD_DUTY_1_3                    (LCD_CR_DUTY_1)                   /*!< 1/3 duty    */
-#define LCD_DUTY_1_4                    ((LCD_CR_DUTY_1 | LCD_CR_DUTY_0)) /*!< 1/4 duty    */
-#define LCD_DUTY_1_8                    (LCD_CR_DUTY_2)                   /*!< 1/8 duty    */
-
-#define IS_LCD_DUTY(__DUTY__) (((__DUTY__) == LCD_DUTY_STATIC)  || \
-                               ((__DUTY__) == LCD_DUTY_1_2)     || \
-                               ((__DUTY__) == LCD_DUTY_1_3)     || \
-                               ((__DUTY__) == LCD_DUTY_1_4)     || \
-                               ((__DUTY__) == LCD_DUTY_1_8))
-
-/**
-  * @}
-  */ 
-  
-
-/** @defgroup LCD_Bias LCD Bias
-  * @{
-  */
-  
-#define LCD_BIAS_1_4                    ((uint32_t)0x00000000)  /*!< 1/4 Bias */
-#define LCD_BIAS_1_2                    LCD_CR_BIAS_0           /*!< 1/2 Bias */
-#define LCD_BIAS_1_3                    LCD_CR_BIAS_1           /*!< 1/3 Bias */
-
-#define IS_LCD_BIAS(__BIAS__) (((__BIAS__) == LCD_BIAS_1_4) || \
-                               ((__BIAS__) == LCD_BIAS_1_2) || \
-                               ((__BIAS__) == LCD_BIAS_1_3))
-/**
-  * @}
-  */ 
-    
-/** @defgroup LCD_Voltage_Source LCD Voltage Source
-  * @{
-  */
-  
-#define LCD_VOLTAGESOURCE_INTERNAL      ((uint32_t)0x00000000)  /*!< Internal voltage source for the LCD */
-#define LCD_VOLTAGESOURCE_EXTERNAL      LCD_CR_VSEL             /*!< External voltage source for the LCD */
-
-#define IS_LCD_VOLTAGE_SOURCE(SOURCE) (((SOURCE) == LCD_VOLTAGESOURCE_INTERNAL) || \
-                                       ((SOURCE) == LCD_VOLTAGESOURCE_EXTERNAL))
-
-/**
-  * @}
-  */  
-
-/** @defgroup LCD_Interrupts LCD Interrupts
-  * @{
-  */
-#define LCD_IT_SOF                      LCD_FCR_SOFIE
-#define LCD_IT_UDD                      LCD_FCR_UDDIE
-
-/**
-  * @}
-  */
-
-/** @defgroup LCD_PulseOnDuration LCD Pulse On Duration
-  * @{
-  */
-
-#define LCD_PULSEONDURATION_0           ((uint32_t)0x00000000)          /*!< Pulse ON duration = 0 pulse   */
-#define LCD_PULSEONDURATION_1           (LCD_FCR_PON_0)                 /*!< Pulse ON duration = 1/CK_PS  */
-#define LCD_PULSEONDURATION_2           (LCD_FCR_PON_1)                 /*!< Pulse ON duration = 2/CK_PS  */
-#define LCD_PULSEONDURATION_3           (LCD_FCR_PON_1 | LCD_FCR_PON_0) /*!< Pulse ON duration = 3/CK_PS  */
-#define LCD_PULSEONDURATION_4           (LCD_FCR_PON_2)                 /*!< Pulse ON duration = 4/CK_PS  */
-#define LCD_PULSEONDURATION_5           (LCD_FCR_PON_2 | LCD_FCR_PON_0) /*!< Pulse ON duration = 5/CK_PS  */
-#define LCD_PULSEONDURATION_6           (LCD_FCR_PON_2 | LCD_FCR_PON_1) /*!< Pulse ON duration = 6/CK_PS  */
-#define LCD_PULSEONDURATION_7           (LCD_FCR_PON)                   /*!< Pulse ON duration = 7/CK_PS  */
-
-#define IS_LCD_PULSE_ON_DURATION(__DURATION__) (((__DURATION__) == LCD_PULSEONDURATION_0) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_1) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_2) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_3) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_4) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_5) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_6) || \
-                                                ((__DURATION__) == LCD_PULSEONDURATION_7))
-/**
-  * @}
-  */
-
-
-/** @defgroup LCD_DeadTime LCD Dead Time
-  * @{
-  */
-
-#define LCD_DEADTIME_0                  ((uint32_t)0x00000000)            /*!< No dead Time  */
-#define LCD_DEADTIME_1                  (LCD_FCR_DEAD_0)                  /*!< One Phase between different couple of Frame   */
-#define LCD_DEADTIME_2                  (LCD_FCR_DEAD_1)                  /*!< Two Phase between different couple of Frame   */
-#define LCD_DEADTIME_3                  (LCD_FCR_DEAD_1 | LCD_FCR_DEAD_0) /*!< Three Phase between different couple of Frame */
-#define LCD_DEADTIME_4                  (LCD_FCR_DEAD_2)                  /*!< Four Phase between different couple of Frame  */
-#define LCD_DEADTIME_5                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_0) /*!< Five Phase between different couple of Frame  */
-#define LCD_DEADTIME_6                  (LCD_FCR_DEAD_2 | LCD_FCR_DEAD_1) /*!< Six Phase between different couple of Frame   */
-#define LCD_DEADTIME_7                  (LCD_FCR_DEAD)                    /*!< Seven Phase between different couple of Frame */
-
-#define IS_LCD_DEAD_TIME(__TIME__) (((__TIME__) == LCD_DEADTIME_0) || \
-                                    ((__TIME__) == LCD_DEADTIME_1) || \
-                                    ((__TIME__) == LCD_DEADTIME_2) || \
-                                    ((__TIME__) == LCD_DEADTIME_3) || \
-                                    ((__TIME__) == LCD_DEADTIME_4) || \
-                                    ((__TIME__) == LCD_DEADTIME_5) || \
-                                    ((__TIME__) == LCD_DEADTIME_6) || \
-                                    ((__TIME__) == LCD_DEADTIME_7))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_BlinkMode LCD Blink Mode
-  * @{
-  */
-
-#define LCD_BLINKMODE_OFF               ((uint32_t)0x00000000)  /*!< Blink disabled            */
-#define LCD_BLINKMODE_SEG0_COM0         (LCD_FCR_BLINK_0)       /*!< Blink enabled on SEG[0], COM[0] (1 pixel)   */
-#define LCD_BLINKMODE_SEG0_ALLCOM       (LCD_FCR_BLINK_1)       /*!< Blink enabled on SEG[0], all COM (up to 
-                                                                    8 pixels according to the programmed duty)  */
-#define LCD_BLINKMODE_ALLSEG_ALLCOM     (LCD_FCR_BLINK)         /*!< Blink enabled on all SEG and all COM (all pixels)  */
-
-#define IS_LCD_BLINK_MODE(__MODE__) (((__MODE__) == LCD_BLINKMODE_OFF)            || \
-                                     ((__MODE__) == LCD_BLINKMODE_SEG0_COM0)      || \
-                                     ((__MODE__) == LCD_BLINKMODE_SEG0_ALLCOM)    || \
-                                     ((__MODE__) == LCD_BLINKMODE_ALLSEG_ALLCOM))
-/**
-  * @}
-  */    
-
-/** @defgroup LCD_BlinkFrequency LCD Blink Frequency
-  * @{
-  */
-
-#define LCD_BLINKFREQUENCY_DIV8         ((uint32_t)0x00000000)                /*!< The Blink frequency = fLCD/8    */
-#define LCD_BLINKFREQUENCY_DIV16        (LCD_FCR_BLINKF_0)                    /*!< The Blink frequency = fLCD/16   */
-#define LCD_BLINKFREQUENCY_DIV32        (LCD_FCR_BLINKF_1)                    /*!< The Blink frequency = fLCD/32   */
-#define LCD_BLINKFREQUENCY_DIV64        (LCD_FCR_BLINKF_1 | LCD_FCR_BLINKF_0) /*!< The Blink frequency = fLCD/64   */
-#define LCD_BLINKFREQUENCY_DIV128       (LCD_FCR_BLINKF_2)                    /*!< The Blink frequency = fLCD/128  */
-#define LCD_BLINKFREQUENCY_DIV256       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_0)  /*!< The Blink frequency = fLCD/256  */
-#define LCD_BLINKFREQUENCY_DIV512       (LCD_FCR_BLINKF_2 |LCD_FCR_BLINKF_1)  /*!< The Blink frequency = fLCD/512  */
-#define LCD_BLINKFREQUENCY_DIV1024      (LCD_FCR_BLINKF)                      /*!< The Blink frequency = fLCD/1024 */
-
-#define IS_LCD_BLINK_FREQUENCY(__FREQUENCY__) (((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV8)   || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV16)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV32)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV64)  || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV128) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV256) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV512) || \
-                                               ((__FREQUENCY__) == LCD_BLINKFREQUENCY_DIV1024))
-/**
-  * @}
-  */
-
-/** @defgroup LCD_Contrast LCD Contrast
-  * @{
-  */
-
-#define LCD_CONTRASTLEVEL_0               ((uint32_t)0x00000000)        /*!< Maximum Voltage = 2.60V    */
-#define LCD_CONTRASTLEVEL_1               (LCD_FCR_CC_0)                /*!< Maximum Voltage = 2.73V    */
-#define LCD_CONTRASTLEVEL_2               (LCD_FCR_CC_1)                /*!< Maximum Voltage = 2.86V    */
-#define LCD_CONTRASTLEVEL_3               (LCD_FCR_CC_1 | LCD_FCR_CC_0) /*!< Maximum Voltage = 2.99V    */
-#define LCD_CONTRASTLEVEL_4               (LCD_FCR_CC_2)                /*!< Maximum Voltage = 3.12V    */
-#define LCD_CONTRASTLEVEL_5               (LCD_FCR_CC_2 | LCD_FCR_CC_0) /*!< Maximum Voltage = 3.25V    */
-#define LCD_CONTRASTLEVEL_6               (LCD_FCR_CC_2 | LCD_FCR_CC_1) /*!< Maximum Voltage = 3.38V    */
-#define LCD_CONTRASTLEVEL_7               (LCD_FCR_CC)                  /*!< Maximum Voltage = 3.51V    */
-
-#define IS_LCD_CONTRAST(__CONTRAST__) (((__CONTRAST__) == LCD_CONTRASTLEVEL_0) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_1) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_2) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_3) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_4) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_5) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_6) || \
-                                       ((__CONTRAST__) == LCD_CONTRASTLEVEL_7))
-/**
-  * @}
-  */
-      
-/** @defgroup LCD_MuxSegment LCD Mux Segment
-  * @{
-  */
-
-#define LCD_MUXSEGMENT_DISABLE            ((uint32_t)0x00000000)        /*!< SEG pin multiplexing disabled */
-#define LCD_MUXSEGMENT_ENABLE             (LCD_CR_MUX_SEG)              /*!< SEG[31:28] are multiplexed with SEG[43:40]    */
-
-#define IS_LCD_MUXSEGMENT(__VALUE__) (((__VALUE__) == LCD_MUXSEGMENT_ENABLE) || \
-                                      ((__VALUE__) == LCD_MUXSEGMENT_DISABLE))
-/**
-  * @}
-  */
-      
-/** @defgroup LCD_Flag LCD Flag
-  * @{
-  */
-
-#define LCD_FLAG_ENS                    LCD_SR_ENS
-#define LCD_FLAG_SOF                    LCD_SR_SOF
-#define LCD_FLAG_UDR                    LCD_SR_UDR
-#define LCD_FLAG_UDD                    LCD_SR_UDD
-#define LCD_FLAG_RDY                    LCD_SR_RDY
-#define LCD_FLAG_FCRSF                  LCD_SR_FCRSR
-
-/**
-  * @}
-  */   
-
-/** @defgroup LCD_RAMRegister LCD RAMRegister
-  * @{
-  */
-
-#define LCD_RAM_REGISTER0               ((uint32_t)0x00000000) /*!< LCD RAM Register 0  */
-#define LCD_RAM_REGISTER1               ((uint32_t)0x00000001) /*!< LCD RAM Register 1  */
-#define LCD_RAM_REGISTER2               ((uint32_t)0x00000002) /*!< LCD RAM Register 2  */
-#define LCD_RAM_REGISTER3               ((uint32_t)0x00000003) /*!< LCD RAM Register 3  */
-#define LCD_RAM_REGISTER4               ((uint32_t)0x00000004) /*!< LCD RAM Register 4  */
-#define LCD_RAM_REGISTER5               ((uint32_t)0x00000005) /*!< LCD RAM Register 5  */
-#define LCD_RAM_REGISTER6               ((uint32_t)0x00000006) /*!< LCD RAM Register 6  */
-#define LCD_RAM_REGISTER7               ((uint32_t)0x00000007) /*!< LCD RAM Register 7  */
-#define LCD_RAM_REGISTER8               ((uint32_t)0x00000008) /*!< LCD RAM Register 8  */
-#define LCD_RAM_REGISTER9               ((uint32_t)0x00000009) /*!< LCD RAM Register 9  */
-#define LCD_RAM_REGISTER10              ((uint32_t)0x0000000A) /*!< LCD RAM Register 10 */
-#define LCD_RAM_REGISTER11              ((uint32_t)0x0000000B) /*!< LCD RAM Register 11 */
-#define LCD_RAM_REGISTER12              ((uint32_t)0x0000000C) /*!< LCD RAM Register 12 */
-#define LCD_RAM_REGISTER13              ((uint32_t)0x0000000D) /*!< LCD RAM Register 13 */
-#define LCD_RAM_REGISTER14              ((uint32_t)0x0000000E) /*!< LCD RAM Register 14 */
-#define LCD_RAM_REGISTER15              ((uint32_t)0x0000000F) /*!< LCD RAM Register 15 */
-
-#define IS_LCD_RAM_REGISTER(__REGISTER__) (((__REGISTER__) == LCD_RAM_REGISTER0)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER1)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER2)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER3)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER4)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER5)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER6)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER7)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER8)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER9)  || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER10) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER11) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER12) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER13) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER14) || \
-                                           ((__REGISTER__) == LCD_RAM_REGISTER15))
-
-/**
-  * @}
-  */  
-   
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup LCD_Exported_Macros LCD Exported Macros
-  * @{
-  */
-
-/** @brief Reset LCD handle state
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @retval None
-  */
-#define __HAL_LCD_RESET_HANDLE_STATE(__HANDLE__)  ((__HANDLE__)->State = HAL_LCD_STATE_RESET)
-
-/** @brief  macros to enables or disables the LCD
-  * @param  __HANDLE__: specifies the LCD Handle.  
-  * @retval None
-  */     
-#define __HAL_LCD_ENABLE(__HANDLE__)              (SET_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
-#define __HAL_LCD_DISABLE(__HANDLE__)             (CLEAR_BIT((__HANDLE__)->Instance->CR, LCD_CR_LCDEN))
-
-/** @brief  Macros to enable or disable the low resistance divider. Displays with high 
-  *         internal resistance may need a longer drive time to achieve 
-  *         satisfactory contrast. This function is useful in this case if some 
-  *         additional power consumption can be tolerated.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @note   When this mode is enabled, the PulseOn Duration (PON) have to be 
-  *         programmed to 1/CK_PS (LCD_PULSEONDURATION_1).
-  * @retval None
-  */
-#define __HAL_LCD_HIGHDRIVER_ENABLE(__HANDLE__)                                \
-                              do{                                              \
-                                  SET_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
-                                  LCD_WaitForSynchro(__HANDLE__);              \
-                                 }while(0)
-
-#define __HAL_LCD_HIGHDRIVER_DISABLE(__HANDLE__)                               \
-                              do{                                              \
-                                  CLEAR_BIT((__HANDLE__)->Instance->FCR, LCD_FCR_HD); \
-                                  LCD_WaitForSynchro(__HANDLE__);              \
-                                 }while(0)
-
-/**
-  * @brief  Macro to configure the LCD pulses on duration.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @param  __DURATION__: specifies the LCD pulse on duration in terms of 
-  *         CK_PS (prescaled LCD clock period) pulses.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_PULSEONDURATION_0: 0 pulse
-  *     @arg LCD_PULSEONDURATION_1: Pulse ON duration = 1/CK_PS
-  *     @arg LCD_PULSEONDURATION_2: Pulse ON duration = 2/CK_PS
-  *     @arg LCD_PULSEONDURATION_3: Pulse ON duration = 3/CK_PS
-  *     @arg LCD_PULSEONDURATION_4: Pulse ON duration = 4/CK_PS
-  *     @arg LCD_PULSEONDURATION_5: Pulse ON duration = 5/CK_PS
-  *     @arg LCD_PULSEONDURATION_6: Pulse ON duration = 6/CK_PS
-  *     @arg LCD_PULSEONDURATION_7: Pulse ON duration = 7/CK_PS
-  * @retval None
-  */
-#define __HAL_LCD_PULSEONDURATION_CONFIG(__HANDLE__, __DURATION__)                \
-        do{                                                                       \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_PON, (__DURATION__)); \
-            LCD_WaitForSynchro(__HANDLE__);                                       \
-           }while(0)
-
-/**
-  * @brief  Macro to configure the LCD dead time.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @param  __DEADTIME__: specifies the LCD dead time.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_DEADTIME_0: No dead Time
-  *     @arg LCD_DEADTIME_1: One Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_2: Two Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_3: Three Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_4: Four Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_5: Five Phase between different couple of Frame
-  *     @arg LCD_DEADTIME_6: Six Phase between different couple of Frame 
-  *     @arg LCD_DEADTIME_7: Seven Phase between different couple of Frame
-  * @retval None
-  */
-#define __HAL_LCD_DEADTIME_CONFIG(__HANDLE__, __DEADTIME__)                        \
-        do{                                                                        \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_DEAD, (__DEADTIME__)); \
-            LCD_WaitForSynchro(__HANDLE__);                                        \
-           }while(0)
-
-/**
-  * @brief  Macro to configure the LCD Contrast.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @param  __CONTRAST__: specifies the LCD Contrast.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_CONTRASTLEVEL_0: Maximum Voltage = 2.60V
-  *     @arg LCD_CONTRASTLEVEL_1: Maximum Voltage = 2.73V
-  *     @arg LCD_CONTRASTLEVEL_2: Maximum Voltage = 2.86V
-  *     @arg LCD_CONTRASTLEVEL_3: Maximum Voltage = 2.99V
-  *     @arg LCD_CONTRASTLEVEL_4: Maximum Voltage = 3.12V
-  *     @arg LCD_CONTRASTLEVEL_5: Maximum Voltage = 3.25V
-  *     @arg LCD_CONTRASTLEVEL_6: Maximum Voltage = 3.38V
-  *     @arg LCD_CONTRASTLEVEL_7: Maximum Voltage = 3.51V
-  * @retval None
-  */
-#define __HAL_LCD_CONTRAST_CONFIG(__HANDLE__, __CONTRAST__)                       \
-        do{                                                                       \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, LCD_FCR_CC, (__CONTRAST__));  \
-            LCD_WaitForSynchro(__HANDLE__);                                       \
-           } while(0) 
-
-/**
-  * @brief  Macro to configure the LCD Blink mode and Blink frequency.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @param  __BLINKMODE__: specifies the LCD blink mode.
-  *   This parameter can be one of the following values:
-  *     @arg LCD_BLINKMODE_OFF:           Blink disabled
-  *     @arg LCD_BLINKMODE_SEG0_COM0:     Blink enabled on SEG[0], COM[0] (1 pixel)
-  *     @arg LCD_BLINKMODE_SEG0_ALLCOM:   Blink enabled on SEG[0], all COM (up to 8 
-  *                                       pixels according to the programmed duty)
-  *     @arg LCD_BLINKMODE_ALLSEG_ALLCOM: Blink enabled on all SEG and all COM 
-  *                                       (all pixels)
-  * @param  __BLINKFREQUENCY__: specifies the LCD blink frequency.
-  *     @arg LCD_BLINKFREQUENCY_DIV8:    The Blink frequency = fLcd/8
-  *     @arg LCD_BLINKFREQUENCY_DIV16:   The Blink frequency = fLcd/16
-  *     @arg LCD_BLINKFREQUENCY_DIV32:   The Blink frequency = fLcd/32
-  *     @arg LCD_BLINKFREQUENCY_DIV64:   The Blink frequency = fLcd/64 
-  *     @arg LCD_BLINKFREQUENCY_DIV128:  The Blink frequency = fLcd/128
-  *     @arg LCD_BLINKFREQUENCY_DIV256:  The Blink frequency = fLcd/256
-  *     @arg LCD_BLINKFREQUENCY_DIV512:  The Blink frequency = fLcd/512
-  *     @arg LCD_BLINKFREQUENCY_DIV1024: The Blink frequency = fLcd/1024
-  * @retval None
-  */
-#define __HAL_LCD_BLINK_CONFIG(__HANDLE__, __BLINKMODE__, __BLINKFREQUENCY__)  \
-        do{                                                                    \
-            MODIFY_REG((__HANDLE__)->Instance->FCR, (LCD_FCR_BLINKF | LCD_FCR_BLINK), ((__BLINKMODE__) | (__BLINKFREQUENCY__))); \
-            LCD_WaitForSynchro(__HANDLE__);                                    \
-          }while(0)
-
-/** @brief  Enables or disables the specified LCD interrupt.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @param  __INTERRUPT__: specifies the LCD interrupt source to be enabled or disabled.
-  *          This parameter can be one of the following values:
-  *     @arg LCD_IT_SOF: Start of Frame Interrupt
-  *     @arg LCD_IT_UDD: Update Display Done Interrupt
-  * @retval None
-  */
-#define __HAL_LCD_ENABLE_IT(__HANDLE__, __INTERRUPT__)                                \
-                         do{                                                          \
-                             SET_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__));   \
-                             LCD_WaitForSynchro(__HANDLE__);                          \
-                            }while(0)         
-#define __HAL_LCD_DISABLE_IT(__HANDLE__, __INTERRUPT__)                               \
-                         do{                                                          \
-                             CLEAR_BIT((__HANDLE__)->Instance->FCR, (__INTERRUPT__)); \
-                             LCD_WaitForSynchro(__HANDLE__);                          \
-                            }while(0)
-
-/** @brief  Checks whether the specified LCD interrupt is enabled or not.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @param  __IT__: specifies the LCD interrupt source to check.
-  *        This parameter can be one of the following values:
-  *        @arg LCD_IT_SOF: Start of Frame Interrupt
-  *        @arg LCD_IT_UDD: Update Display Done Interrupt.
-  * @note If the device is in STOP mode (PCLK not provided) UDD will not 
-  *          generate an interrupt even if UDDIE = 1. 
-  *          If the display is not enabled the UDD interrupt will never occur.
-  * @retval The state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_LCD_GET_IT_SOURCE(__HANDLE__, __IT__) (((__HANDLE__)->Instance->FCR) & (__IT__))
-
-/** @brief  Checks whether the specified LCD flag is set or not.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *        @arg LCD_FLAG_ENS: LCD Enabled flag. It indicates the LCD controller status.
-  * @note  The ENS bit is set immediately when the LCDEN bit in the LCD_CR 
-  *             goes from 0 to 1. On deactivation it reflects the real status of 
-  *             LCD so it becomes 0 at the end of the last displayed frame.  
-  *        @arg LCD_FLAG_SOF: Start of Frame flag. This flag is set by hardware at 
-  *             the beginning of a new frame, at the same time as the display data is 
-  *             updated.
-  *        @arg LCD_FLAG_UDR: Update Display Request flag.
-  *        @arg LCD_FLAG_UDD: Update Display Done flag. 
-  *        @arg LCD_FLAG_RDY: Step_up converter Ready flag. It indicates the status 
-  *             of the step-up converter.
-  *        @arg LCD_FLAG_FCRSF: LCD Frame Control Register Synchronization Flag. 
-  *             This flag is set by hardware each time the LCD_FCR register is updated 
-  *             in the LCDCLK domain. 
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_LCD_GET_FLAG(__HANDLE__, __FLAG__)    (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
-
-/** @brief  Clears the specified LCD pending flag.
-  * @param  __HANDLE__: specifies the LCD Handle.
-  * @param  __FLAG__: specifies the flag to clear.
-  *        This parameter can be any combination of the following values:
-  *        @arg LCD_FLAG_SOF: Start of Frame Interrupt
-  *        @arg LCD_FLAG_UDD: Update Display Done Interrupt
-  * @retval None
-  */
-#define __HAL_LCD_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->CLR = (__FLAG__))
-
-/**
-  * @}
-  */
-  
-/* Exported functions ------------------------------------------------------- */
-
-/** @addtogroup LCD_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization/de-initialization methods  **********************************/
-HAL_StatusTypeDef     HAL_LCD_DeInit(LCD_HandleTypeDef *hlcd);
-HAL_StatusTypeDef     HAL_LCD_Init(LCD_HandleTypeDef *hlcd);
-void                  HAL_LCD_MspInit(LCD_HandleTypeDef *hlcd);
-void                  HAL_LCD_MspDeInit(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group2
-  * @{
-  */
-
-/* IO operation methods *******************************************************/
-HAL_StatusTypeDef     HAL_LCD_Write(LCD_HandleTypeDef *hlcd, uint32_t RAMRegisterIndex, uint32_t RAMRegisterMask, uint32_t Data);
-HAL_StatusTypeDef     HAL_LCD_Clear(LCD_HandleTypeDef *hlcd);
-HAL_StatusTypeDef     HAL_LCD_UpdateDisplayRequest(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Exported_Functions_Group3
-  * @{
-  */
-
-/* Peripheral State methods  **************************************************/
-HAL_LCD_StateTypeDef  HAL_LCD_GetState(LCD_HandleTypeDef *hlcd);
-uint32_t              HAL_LCD_GetError(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup LCD_Private_Functions
-  * @{
-  */
-
-/* Private functions ---------------------------------------------------------*/
-HAL_StatusTypeDef     LCD_WaitForSynchro(LCD_HandleTypeDef *hlcd);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L100xB || STM32L100xBA || STM32L100xC ||... || STM32L162xD || STM32L162xE */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_LCD_H */
-
-/******************* (C) COPYRIGHT 2014 STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,838 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_nor.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   NOR HAL module driver.
-  *          This file provides a generic firmware to drive NOR memories mounted 
-  *          as external device.
-  *         
-  @verbatim
-  ==============================================================================
-                     ##### How to use this driver #####
-  ==============================================================================       
-    [..]
-      This driver is a generic layered driver which contains a set of APIs used to 
-      control NOR flash memories. It uses the FSMC layer functions to interface 
-      with NOR devices. This driver is used as follows:
-    
-      (+) NOR flash memory configuration sequence using the function HAL_NOR_Init() 
-          with control and timing parameters for both normal and extended mode.
-            
-      (+) Read NOR flash memory manufacturer code and device IDs using the function
-          HAL_NOR_Read_ID(). The read information is stored in the NOR_ID_TypeDef 
-          structure declared by the function caller. 
-        
-      (+) Access NOR flash memory by read/write data unit operations using the functions
-          HAL_NOR_Read(), HAL_NOR_Program().
-        
-      (+) Perform NOR flash erase block/chip operations using the functions 
-          HAL_NOR_Erase_Block() and HAL_NOR_Erase_Chip().
-        
-      (+) Read the NOR flash CFI (common flash interface) IDs using the function
-          HAL_NOR_Read_CFI(). The read information is stored in the NOR_CFI_TypeDef
-          structure declared by the function caller.
-        
-      (+) You can also control the NOR device by calling the control APIs HAL_NOR_WriteOperation_Enable()/
-          HAL_NOR_WriteOperation_Disable() to respectively enable/disable the NOR write operation  
-       
-      (+) You can monitor the NOR device HAL state by calling the function
-          HAL_NOR_GetState() 
-    [..]
-     (@) This driver is a set of generic APIs which handle standard NOR flash operations.
-         If a NOR flash device contains different operations and/or implementations, 
-         it should be implemented separately.
-
-     *** NOR HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in NOR HAL driver.
-       
-      (+) __NOR_WRITE : NOR memory write data to specified address
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup NOR NOR
-  * @brief NOR driver modules
-  * @{
-  */
-#ifdef HAL_NOR_MODULE_ENABLED
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-
-/** @defgroup NOR_Private_Variables NOR Private Variables
-  * @{
-  */
-
-static uint32_t uwNORAddress            = NOR_MEMORY_ADRESS1;
-static uint32_t uwNORMememoryDataWidth  = NOR_MEMORY_8B;
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup NOR_Exported_Functions NOR Exported Functions
-  * @{
-  */
-
-/** @defgroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @brief    Initialization and Configuration functions 
-  *
-  @verbatim    
-  ==============================================================================
-           ##### NOR Initialization and de_initialization functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to initialize/de-initialize
-    the NOR memory
-  
-@endverbatim
-  * @{
-  */
-    
-/**
-  * @brief  Perform the NOR memory Initialization sequence
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  Timing: pointer to NOR control timing structure 
-  * @param  ExtTiming: pointer to NOR extended mode timing structure    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
-{
-  /* Check the NOR handle parameter */
-  if(hnor == HAL_NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  if(hnor->State == HAL_NOR_STATE_RESET)
-  {
-    /* Initialize the low level hardware (MSP) */
-    HAL_NOR_MspInit(hnor);
-  }
-
-  /* Initialize NOR control Interface */
-  FSMC_NORSRAM_Init(hnor->Instance, &(hnor->Init));
-
-  /* Initialize NOR timing Interface */
-  FSMC_NORSRAM_Timing_Init(hnor->Instance, Timing, hnor->Init.NSBank); 
-
-  /* Initialize NOR extended mode timing Interface */
-  FSMC_NORSRAM_Extended_Timing_Init(hnor->Extended, ExtTiming, hnor->Init.NSBank, hnor->Init.ExtendedMode);
-
-  /* Enable the NORSRAM device */
-  __FSMC_NORSRAM_ENABLE(hnor->Instance, hnor->Init.NSBank);  
-
-  /* Initialize NOR address mapped by FSMC */
-  if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM1)
-  {
-    uwNORAddress = NOR_MEMORY_ADRESS1;
-  }
-  else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM2)
-  {
-    uwNORAddress = NOR_MEMORY_ADRESS2;
-  }
-  else if (hnor->Init.NSBank == FSMC_BANK1_NORSRAM3)
-  {
-    uwNORAddress = NOR_MEMORY_ADRESS3;
-  }
-  else
-  {
-    uwNORAddress = NOR_MEMORY_ADRESS4;
-  }
-
-  /* Initialize NOR Memory Data Width*/
-  if (hnor->Init.MemoryDataWidth == FSMC_NORSRAM_MEM_BUS_WIDTH_8)
-  {
-    uwNORMememoryDataWidth = NOR_MEMORY_8B;
-  }
-  else
-  {
-    uwNORMememoryDataWidth = NOR_MEMORY_16B;
-  }
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY; 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Perform NOR memory De-Initialization sequence
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor)  
-{
-  /* De-Initialize the low level hardware (MSP) */
-  HAL_NOR_MspDeInit(hnor);
- 
-  /* Configure the NOR registers with their reset values */
-  FSMC_NORSRAM_DeInit(hnor->Instance, hnor->Extended, hnor->Init.NSBank);
-  
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hnor);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  NOR MSP Init
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval None
-  */
-__weak void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_NOR_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  NOR MSP DeInit
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval None
-  */
-__weak void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_NOR_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  NOR BSP Wait fro Ready/Busy signal
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  Timeout: Maximum timeout value
-  * @retval None
-  */
-__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_NOR_BspWait could be implemented in the user file
-   */ 
-}
-  
-/**
-  * @}
-  */
-
-/** @defgroup NOR_Exported_Functions_Group2 Input and Output functions 
-  * @brief    Input Output and memory control functions 
-  *
-  @verbatim    
-  ==============================================================================
-                ##### NOR Input and Output functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to use and control the NOR memory
-  
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Read NOR flash IDs
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  pNOR_ID : pointer to NOR ID structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send read ID command */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0090);
-
-  /* Read the NOR IDs */
-  pNOR_ID->ManufacturerCode = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, MC_ADDRESS);
-  pNOR_ID->DeviceCode1      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE1_ADDR);
-  pNOR_ID->DeviceCode2      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE2_ADDR);
-  pNOR_ID->DeviceCode3      = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, DEVICE_CODE3_ADDR);
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);   
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Returns the NOR memory to Read mode.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-  
-  __NOR_WRITE(uwNORAddress, 0x00F0);
-
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);   
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Read data from NOR memory 
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  pAddress: pointer to Device address
-  * @param  pData : pointer to read data  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send read data command */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA); 
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055);  
-  __NOR_WRITE(*pAddress, 0x00F0);
-
-  /* Read the data */
-  *pData = *(__IO uint32_t *)pAddress;
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Program data to NOR memory 
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  pAddress: Device address
-  * @param  pData : pointer to the data to write   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send program data command */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00A0);
-
-  /* Write the data */
-  __NOR_WRITE(pAddress, *pData);
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Reads a block of data from the FSMC NOR memory.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  uwAddress: NOR memory internal address to read from.
-  * @param  pData: pointer to the buffer that receives the data read from the 
-  *         NOR memory.
-  * @param  uwBufferSize : number of Half word to read.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send read data command */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x00555), 0x00AA); 
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x002AA), 0x0055);  
-  __NOR_WRITE(uwAddress, 0x00F0);
-  
-  /* Read buffer */
-  while( uwBufferSize > 0) 
-  {
-    *pData++ = *(__IO uint16_t *)uwAddress;
-    uwAddress += 2;
-    uwBufferSize--;
-  } 
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Writes a half-word buffer to the FSMC NOR memory. This function 
-  *         must be used only with S29GL128P NOR memory. 
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  uwAddress: NOR memory internal address from which the data 
-  * @param  pData: pointer to source data buffer. 
-  * @param  uwBufferSize: number of Half words to write. The maximum allowed 
-  * @retval HAL status
-  */ 
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
-{
-  uint32_t lastloadedaddress = 0;
-  uint32_t currentaddress = 0;
-  uint32_t endaddress = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Initialize variables */
-  currentaddress    = uwAddress;
-  endaddress        = uwAddress + uwBufferSize - 1;
-  lastloadedaddress = uwAddress;
-
-  /* Issue unlock command sequence */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055); 
-
-  /* Write Buffer Load Command */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), 0x25); 
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, uwAddress), (uwBufferSize - 1)); 
-
-  /* Load Data into NOR Buffer */
-  while(currentaddress <= endaddress)
-  {
-    /* Store last loaded address & data value (for polling) */
-    lastloadedaddress = currentaddress;
- 
-    __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, currentaddress), *pData++);
-    
-    currentaddress += 1; 
-  }
-
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, lastloadedaddress), 0x29); 
-  
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK; 
-  
-}
-
-/**
-  * @brief  Erase the specified block of the NOR memory 
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  BlockAddress : Block to erase address 
-  * @param  Address: Device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send block erase command sequence */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
-  __NOR_WRITE((uint32_t)(BlockAddress + Address), 0x30);
-
-  /* Check the NOR memory status and update the controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-    
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;
- 
-}
-
-/**
-  * @brief  Erase the entire NOR chip.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  Address : Device address  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;  
-    
-  /* Send NOR chip erase command sequence */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0080);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x00AA);
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x02AA), 0x0055);  
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0555), 0x0010);
-  
-  /* Check the NOR memory status and update the controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-    
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Read NOR flash CFI IDs
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @param  pNOR_CFI : pointer to NOR CFI IDs structure  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-  
-  /* Check the NOR controller state */
-  if(hnor->State == HAL_NOR_STATE_BUSY)
-  {
-     return HAL_BUSY;
-  }
-    
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-  
-  /* Send read CFI query command */
-  __NOR_WRITE(__NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, 0x0055), 0x0098);
-
-  /* read the NOR CFI information */
-  pNOR_CFI->CFI1 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI1_ADDRESS);
-  pNOR_CFI->CFI2 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI2_ADDRESS);
-  pNOR_CFI->CFI3 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI3_ADDRESS);
-  pNOR_CFI->CFI4 = *(__IO uint16_t *) __NOR_ADDR_SHIFT(uwNORAddress, uwNORMememoryDataWidth, CFI4_ADDRESS);
-
-  /* Check the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor);
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup NOR_Exported_Functions_Group3 Control functions 
- *  @brief   management functions 
- *
-@verbatim   
-  ==============================================================================
-                        ##### NOR Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the NOR interface.
-
-@endverbatim
-  * @{
-  */
-    
-/**
-  * @brief  Enables dynamically NOR write operation.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-
-  /* Enable write operation */
-  FSMC_NORSRAM_WriteOperation_Enable(hnor->Instance, hnor->Init.NSBank); 
-  
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Disables dynamically NOR write operation.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor)
-{
-  /* Process Locked */
-  __HAL_LOCK(hnor);
-
-  /* Update the SRAM controller state */
-  hnor->State = HAL_NOR_STATE_BUSY;
-    
-  /* Disable write operation */
-  FSMC_NORSRAM_WriteOperation_Disable(hnor->Instance, hnor->Init.NSBank); 
-  
-  /* Update the NOR controller state */
-  hnor->State = HAL_NOR_STATE_PROTECTED;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hnor); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */  
-  
-/** @defgroup NOR_Exported_Functions_Group4 State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### NOR State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in run-time the status of the NOR controller 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  return the NOR controller state
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.
-  * @retval NOR controller state
-  */
-HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor)
-{
-  return hnor->State;
-}
-
-/**
-  * @brief  Returns the NOR operation status.
-  * @param  hnor: pointer to a NOR_HandleTypeDef structure that contains
-  *                the configuration information for NOR module.   
-  * @param  Address: Device address
-  * @param  Timeout: NOR progamming Timeout
-  * @retval NOR_Status: The returned value can be: NOR_SUCCESS, NOR_ERROR
-  *         or NOR_TIMEOUT
-  */
-NOR_StatusTypedef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout)
-{ 
-  NOR_StatusTypedef status = NOR_ONGOING;
-  uint16_t tmpSR1 = 0, tmpSR2 = 0;
-  uint32_t tickstart = 0;
-
-  /* Poll on NOR memory Ready/Busy signal ------------------------------------*/
-  HAL_NOR_MspWait(hnor, Timeout);
-  
-  /* Get the NOR memory operation status -------------------------------------*/
-  while(status != NOR_TIMEOUT)
-  {
-    /* Get tick */
-    tickstart = HAL_GetTick();
-    
-    if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-    {
-      status = NOR_TIMEOUT; 
-    }  
-    
-    /* Read NOR status register (DQ6 and DQ5) */
-    tmpSR1 = *(__IO uint16_t *)Address;
-    tmpSR2 = *(__IO uint16_t *)Address;
-
-    /* If DQ6 did not toggle between the two reads then return NOR_Success */
-    if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) 
-    {
-      return NOR_SUCCESS;
-    }
-    
-    if((tmpSR1 & 0x0020) == 0x0020)
-    {
-      return NOR_ONGOING;
-    }
-    
-    tmpSR1 = *(__IO uint16_t *)Address;
-    tmpSR2 = *(__IO uint16_t *)Address;
-
-    /* If DQ6 did not toggle between the two reads then return NOR_Success */
-    if((tmpSR1 & 0x0040) == (tmpSR2 & 0x0040)) 
-    {
-      return NOR_SUCCESS;
-    }
-    
-    if((tmpSR1 & 0x0020) == 0x0020)
-    {
-      return NOR_ERROR;
-    } 
-  }
-
-  /* Return the operation status */
-  return status;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-#endif /* HAL_NOR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_nor.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,307 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_nor.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of NOR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_NOR_H
-#define __STM32L1xx_HAL_NOR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_fsmc.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup NOR
-  * @{
-  */ 
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/* Exported typedef ----------------------------------------------------------*/ 
-
-/** @defgroup NOR_Exported_typedef NOR Exported typedef
-  * @{
-  */ 
-  
-/** 
-  * @brief  HAL SRAM State structures definition  
-  */ 
-typedef enum
-{  
-  HAL_NOR_STATE_RESET             = 0x00,  /*!< NOR not yet initialized or disabled  */
-  HAL_NOR_STATE_READY             = 0x01,  /*!< NOR initialized and ready for use    */
-  HAL_NOR_STATE_BUSY              = 0x02,  /*!< NOR internal processing is ongoing   */
-  HAL_NOR_STATE_ERROR             = 0x03,  /*!< NOR error state                      */ 
-  HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected  */
-
-}HAL_NOR_StateTypeDef;    
-
-/**
-  * @brief  FSMC NOR Status typedef
-  */
-typedef enum
-{
-  NOR_SUCCESS = 0,
-  NOR_ONGOING,
-  NOR_ERROR,
-  NOR_TIMEOUT
-
-}NOR_StatusTypedef; 
-
-/**
-  * @brief  FSMC NOR ID typedef
-  */
-typedef struct
-{
-  uint16_t ManufacturerCode;  /*!< Defines the device's manufacturer code used to identify the memory       */
-  
-  uint16_t DeviceCode1;  
-  
-  uint16_t DeviceCode2;                      
-        
-  uint16_t DeviceCode3;       /*!< Defines the devices' codes used to identify the memory. 
-                                    These codes can be accessed by performing read operations with specific 
-                                    control signals and addresses set.They can also be accessed by issuing 
-                                    an Auto Select command                                                   */    
-  
-}NOR_IDTypeDef;
-
-
-/**
-  * @brief  FSMC NOR CFI typedef
-  */
-typedef struct
-{
-  /*!< Defines the information stored in the memory's Common flash interface
-       which contains a description of various electrical and timing parameters, 
-       density information and functions supported by the memory                   */
-  
-  uint16_t CFI1;            
-  
-  uint16_t CFI2;          
-  
-  uint16_t CFI3;                      
-  
-  uint16_t CFI4;                     
-  
-}NOR_CFITypeDef;
-
-/** 
-  * @brief  NOR handle Structure definition  
-  */ 
-typedef struct
-{
-  FSMC_NORSRAM_TYPEDEF          *Instance;    /*!< Register base address                        */ 
-  
-  FSMC_NORSRAM_EXTENDED_TYPEDEF *Extended;    /*!< Extended mode register base address          */
-  
-  FSMC_NORSRAM_InitTypeDef      Init;         /*!< NOR device control configuration parameters  */
-
-  HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */ 
-  
-  __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
-   
-}NOR_HandleTypeDef; 
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup NOR_Exported_Constants NOR Exported Constants
-  * @{
-  */
-
-/* NOR device IDs addresses */
-#define MC_ADDRESS               ((uint16_t)0x0000)
-#define DEVICE_CODE1_ADDR        ((uint16_t)0x0001)
-#define DEVICE_CODE2_ADDR        ((uint16_t)0x000E)
-#define DEVICE_CODE3_ADDR        ((uint16_t)0x000F)
-
-/* NOR CFI IDs addresses */
-#define CFI1_ADDRESS             ((uint16_t)0x10)
-#define CFI2_ADDRESS             ((uint16_t)0x11)
-#define CFI3_ADDRESS             ((uint16_t)0x12)
-#define CFI4_ADDRESS             ((uint16_t)0x13)
-
-/* NOR operation wait timeout */
-#define NOR_TMEOUT               ((uint16_t)0xFFFF)
-   
-/* NOR memory data width */
-#define NOR_MEMORY_8B            ((uint8_t)0x0)
-#define NOR_MEMORY_16B           ((uint8_t)0x1)
-
-/* NOR memory device read/write start address */
-#define NOR_MEMORY_ADRESS1       ((uint32_t)0x60000000)
-#define NOR_MEMORY_ADRESS2       ((uint32_t)0x64000000)
-#define NOR_MEMORY_ADRESS3       ((uint32_t)0x68000000)
-#define NOR_MEMORY_ADRESS4       ((uint32_t)0x6C000000)
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup NOR_Exported_macro NOR Exported macro
-  * @{
-  */
-
-/** @brief Reset NOR handle state
-  * @param  __HANDLE__: NOR handle
-  * @retval None
-  */
-#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
-
-
-/**
-  * @brief  NOR memory address shifting.
-  * @param  __NOR_ADDRESS: NOR base address 
-  * @param  __NOR_MEMORY_WIDTH_: NOR memory width
-  * @param  __ADDRESS__: NOR memory address 
-  * @retval NOR shifted address value
-  */
-#define __NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
-            ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
-              ((uint32_t)((__NOR_ADDRESS) + (2 * (__ADDRESS__)))):              \
-              ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
-
-/**
-  * @brief  NOR memory write data to specified address.
-  * @param  __ADDRESS__: NOR memory address 
-  * @param  __DATA__: Data to write
-  * @retval None
-  */
-#define __NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup NOR_Exported_Functions
- *  @{
- */
-
-/** @addtogroup NOR_Exported_Functions_Group1
- *  @{
- */
-
-/* Initialization/de-initialization functions  **********************************/  
-HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
-void              HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
-void              HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
-void              HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup NOR_Exported_Functions_Group2
- *  @{
- */
-
-/* I/O operation functions  *****************************************************/
-HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
-HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
-
-HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
-
-HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
-HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup NOR_Exported_Functions_Group3
- *  @{
- */
-
-/* NOR Control functions  *******************************************************/
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
-HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
-
-/**
-  * @}
-  */
-  
-/** @addtogroup NOR_Exported_Functions_Group4
- *  @{
- */
-
-/* NOR State functions **********************************************************/
-HAL_NOR_StateTypeDef  HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
-NOR_StatusTypedef     HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_NOR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1004 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_opamp.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   OPAMP HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the operational amplifiers (OPAMP1 ,... ,OPAMP3) 
-  *          peripheral: 
-  *           + OPAMP configuration
-  *           + OPAMP calibration
-  *
-  *          Thanks to
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions
-  *           + Peripheral State functions
-  *         
-  @verbatim
-================================================================================
-          ##### OPAMP Peripheral Features #####
-================================================================================
-           
-  [..] The device integrates up to 3 operational amplifiers OPAMP1, OPAMP2,
-       OPAMP3 (OPAMP3 availability depends on device category)
-       
-       (#) The OPAMP(s) provides several exclusive running modes.
-       (+) Standalone mode
-       (+) Follower mode
-
-       (#) The OPAMP(s) provide(s) calibration capabilities.  
-       (+) Calibration aims at correcting some offset for running mode.
-       (+) The OPAMP uses either factory calibration settings OR user defined 
-           calibration (trimming) settings (i.e. trimming mode).
-       (+) The user defined settings can be figured out using self calibration 
-           handled by HAL_OPAMP_SelfCalibrate, HAL_OPAMPEx_SelfCalibrateAll
-       (+) HAL_OPAMP_SelfCalibrate:
-       (++) Runs automatically the calibration in 2 steps: for transistors 
-            differential pair high (PMOS) or low (NMOS)
-       (++) Enables the user trimming mode
-       (++) Updates the init structure with trimming values with fresh calibration 
-            results.
-            The user may store the calibration results for larger 
-            (ex monitoring the trimming as a function of temperature 
-            for instance)
-       (++) for devices having several OPAMPs, HAL_OPAMPEx_SelfCalibrateAll
-            runs calibration of all OPAMPs in parallel to save trimming search
-            wait time.
-             
-       (#) Running mode: Standalone mode 
-       (+) Gain is set externally (gain depends on external loads).
-       (+) Follower mode also possible externally by connecting the inverting input to
-           the output.
-       
-       (#) Running mode: Follower mode
-       (+) No Inverting Input is connected.
-       (+) The OPAMP(s) output(s) are internally connected to inverting input
-        
-       (#) The OPAMPs inverting input can be selected among the list shown
-           in table below.
-       
-       (#) The OPAMPs non inverting input can be selected among the list shown
-           in table below.
-       
-   [..] Table 1.  OPAMPs inverting/non-inverting inputs for STM32L1 devices:
-     
-    +--------------------------------------------------------------------------+
-    |                | HAL param  |    OPAMP1    |    OPAMP2    |   OPAMP3(4)  |
-    |                |   name     |              |              |              |
-    |----------------|------------|--------------|--------------|--------------|
-    |   Inverting    |    VM0     |     PA2      |     PA7      |     PC2      |
-    |    input (1)   |    VM1     | VINM pin (2) | VINM pin (2) | VINM pin (2) |
-    |----------------|------------|--------------|--------------|--------------|
-    |  Non Inverting |    VP0     |     PA1      |     PA6      |     PC1      |
-    |    input       | DAC_CH1 (3)|   DAC_CH1    |   DAC_CH1    |     ---      |
-    |                | DAC_CH2 (3)|     ---      |   DAC_CH2    |   DAC_CH2    |
-    +--------------------------------------------------------------------------+
-    (1): NA in follower mode.
-    (2): OPAMP input OPAMPx_VINM are dedicated OPAMP pins, their availability
-         depends on device package.
-    (3): DAC channels 1 and 2 are connected internally to OPAMP. Nevertheless,
-         I/O pins connected to DAC can still be used as DAC output (pins PA4 
-         and PA5).
-    (4): OPAMP3 availability depends on device category.
-
-
-   [..] Table 2.  OPAMPs outputs for STM32L1 devices:
-
-    +--------------------------------------------------------+
-    |                 |   OPAMP1   |   OPAMP2   |  OPAMP3(4) | 
-    |-----------------|------------|------------|------------|
-    | Output          |    PA3     |    PB0     |    PC3     |
-    +--------------------------------------------------------+
-    (4) : OPAMP3 availability depends on device category
-
-
-            ##### How to use this driver #####
-================================================================================
-  [..] 
-     
-    *** Calibration ***
-    ============================================
-      To run the opamp calibration self calibration:
-
-      (#) Start calibration using HAL_OPAMP_SelfCalibrate. 
-           Store the calibration results.
-
-    *** Running mode ***
-    ============================================
-      
-      To use the opamp, perform the following steps:
-            
-      (#) Fill in the HAL_OPAMP_MspInit() to
-      (+) Enable the OPAMP Peripheral clock using macro "__OPAMP_CLK_ENABLE()"
-      (++) Configure the opamp input AND output in analog mode using 
-           HAL_GPIO_Init() to map the opamp output to the GPIO pin.
-  
-      (#) Configure the opamp using HAL_OPAMP_Init() function:
-      (+) Select the mode
-      (+) Select the inverting input
-      (+) Select the non-inverting input 
-      (+) Select either factory or user defined trimming mode.
-      (+) If the user defined trimming mode is enabled, select PMOS & NMOS trimming values
-          (typ. settings returned by HAL_OPAMP_SelfCalibrate function).
-      
-      (#) Enable the opamp using HAL_OPAMP_Start() function.
-           
-      (#) Disable the opamp using HAL_OPAMP_Stop() function.
-      
-      (#) Lock the opamp in running mode using HAL_OPAMP_Lock() function.
-          Caution: On STM32L1, HAL OPAMP lock is software lock only (not 
-          hardware lock as on some other STM32 devices)
-
-      (#) If needed, unlock the opamp using HAL_OPAMPEx_Unlock() function.
-
-    *** Running mode: change of configuration while OPAMP ON  ***
-    ============================================
-    To Re-configure OPAMP when OPAMP is ON (change on the fly)
-      (#) If needed, Fill in the HAL_OPAMP_MspInit()
-      (+) This is the case for instance if you wish to use new OPAMP I/O
-
-      (#) Configure the opamp using HAL_OPAMP_Init() function:
-      (+) As in configure case, selects first the parameters you wish to modify.
-      
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-    
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup OPAMP OPAMP
-  * @brief OPAMP HAL module driver
-  * @{
-  */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup OPAMP_Exported_Functions OPAMP Exported Functions
-  * @{
-  */
-
-/** @defgroup OPAMP_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the OPAMP according to the specified
-  *         parameters in the OPAMP_InitTypeDef and create the associated handle.
-  * @note   If the selected opamp is locked, initialization can't be performed.
-  *         To unlock the configuration, perform a system reset.
-  * @param  hopamp: OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef* hopamp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  uint32_t tmp_csr = 0;       /* Temporary variable to update register CSR, except bits ANAWSSELx, S7SEL2, OPA_RANGE, OPAxCALOUT */
-  
-  /* Check the OPAMP handle allocation and lock status */
-  /* Init not allowed if calibration is ongoing */
-  if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED)
-                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY) )
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-       
-    /* Set OPAMP parameters */
-    assert_param(IS_OPAMP_FUNCTIONAL_NORMALMODE(hopamp->Init.Mode));
-    assert_param(IS_OPAMP_NONINVERTING_INPUT(hopamp->Init.NonInvertingInput));       
-    assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-    assert_param(IS_OPAMP_POWER_SUPPLY_RANGE(hopamp->Init.PowerSupplyRange));
-    assert_param(IS_OPAMP_TRIMMING(hopamp->Init.UserTrimming));
-    
-    if (hopamp->Init.Mode != OPAMP_FOLLOWER_MODE)
-    {
-      assert_param(IS_OPAMP_INVERTING_INPUT(hopamp->Init.InvertingInput));
-    }
-    
-    if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
-    {
-      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueP));
-        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueN));
-      }
-      else
-      {
-        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValuePLowPower));
-        assert_param(IS_OPAMP_TRIMMINGVALUE(hopamp->Init.TrimmingValueNLowPower));
-      }
-    }
-    
-    /* Call MSP init function */
-    HAL_OPAMP_MspInit(hopamp);
-    
-    
-    /* Set OPAMP parameters                                                   */
-    /* - Set internal switches in function of:                                */
-    /*   - OPAMP selected mode: standalone or follower.                       */
-    /*   - Non-inverting input connection                                     */
-    /*   - Inverting input connection                                         */
-    /* - Set power supply range                                               */
-    /* - Set power mode and associated calibration parameters                 */
-    
-    /* Get OPAMP CSR register into temporary variable */
-    tmp_csr = OPAMP->CSR;
-    
-    /* Open all switches on non-inverting input, inverting input and output   */
-    /* feedback.                                                              */
-    CLEAR_BIT(tmp_csr, __OPAMP_CSR_ALL_SWITCHES(hopamp));
-    
-    /* Set internal switches in function of OPAMP mode selected: standalone   */
-    /* or follower.                                                           */
-    /* If follower mode is selected, feedback switch S3 is closed and         */
-    /* inverting inputs switches are let opened.                              */
-    /* If standalone mode is selected, feedback switch S3 is let opened and   */
-    /* the selected inverting inputs switch is closed.                        */
-    if (hopamp->Init.Mode == OPAMP_FOLLOWER_MODE)
-    {
-      /* Follower mode: Close switches S3 and SanB */
-      SET_BIT(tmp_csr, __OPAMP_CSR_S3SELX(hopamp));
-    }
-    else
-    {
-      /* Set internal switches in function of inverting input selected:       */
-      /* Close switch to connect comparator inverting input to the selected   */
-      /* input: dedicated IO pin or alternative IO pin available on some      */
-      /* device packages.                                                     */
-      if (hopamp->Init.InvertingInput == OPAMP_INVERTINGINPUT_VM0)
-      {
-        /* Close switch to connect comparator non-inverting input to          */
-        /* dedicated IO pin low-leakage.                                      */
-        SET_BIT(tmp_csr, __OPAMP_CSR_S4SELX(hopamp));
-      }
-      else
-      {
-        /* Close switch to connect comparator inverting input to alternative  */
-        /* IO pin available on some device packages.                          */
-        SET_BIT(tmp_csr, __OPAMP_CSR_ANAWSELX(hopamp));
-      }
-    }
-    
-    /* Set internal switches in function of non-inverting input selected:     */
-    /* Close switch to connect comparator non-inverting input to the selected */
-    /* input: dedicated IO pin or DAC channel.                                */
-    if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_VP0)
-    {
-      /* Close switch to connect comparator non-inverting input to            */
-      /* dedicated IO pin low-leakage.                                        */
-      SET_BIT(tmp_csr, __OPAMP_CSR_S5SELX(hopamp));
-    }
-    else if (hopamp->Init.NonInvertingInput == OPAMP_NONINVERTINGINPUT_DAC_CH1)
-    {
-      
-      /* Particular case for connection to DAC channel 1:                     */
-      /* OPAMP_NONINVERTINGINPUT_DAC_CH1 available on OPAMP1 and OPAMP2 only  */
-      /* (OPAMP3 availability depends on device category).                    */
-      if ((hopamp->Instance == OPAMP1) || (hopamp->Instance == OPAMP2))
-      {
-        /* Close switch to connect comparator non-inverting input to          */
-        /* DAC channel 1.                                                     */
-        SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp));
-      }
-      else
-      {
-        /* Set HAL status to error if another OPAMP instance as OPAMP1 or     */
-        /* OPAMP2 is intended to be connected to DAC channel 2.               */
-        status = HAL_ERROR;
-      }
-    }
-    else /* if (hopamp->Init.NonInvertingInput ==                             */
-         /*     OPAMP_NONINVERTINGINPUT_DAC_CH2  )                            */
-    {
-      /* Particular case for connection to DAC channel 2:                     */
-      /* OPAMP_NONINVERTINGINPUT_DAC_CH2 available on OPAMP2 and OPAMP3 only  */
-      /* (OPAMP3 availability depends on device category).                    */
-      if (hopamp->Instance == OPAMP2)
-      {
-        /* Close switch to connect comparator non-inverting input to          */
-        /* DAC channel 2.                                                     */
-        SET_BIT(tmp_csr, OPAMP_CSR_S7SEL2);
-      }
-      /* If OPAMP3 is selected (if available) */
-      else if (hopamp->Instance != OPAMP1)
-      {
-        /* Close switch to connect comparator non-inverting input to          */
-        /* DAC channel 2.                                                     */
-        SET_BIT(tmp_csr, __OPAMP_CSR_S6SELX(hopamp));
-      }
-      else
-      {
-        /* Set HAL status to error if another OPAMP instance as OPAMP2 or     */
-        /* OPAMP3 (if available) is intended to be connected to DAC channel 2.*/
-        status = HAL_ERROR;
-      }
-    }
-    
-    /* Continue OPAMP configuration if settings of switches are correct */
-    if (status != HAL_ERROR)
-    {
-      /* Set power mode and associated calibration parameters */
-      if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Set normal mode */
-        CLEAR_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp));
-        
-        if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
-        {
-          /* Set calibration mode (factory or user) and values for            */
-          /* transistors differential pair high (PMOS) and low (NMOS) for     */
-          /* normal mode.                                                     */
-          MODIFY_REG(OPAMP->OTR, OPAMP_OTR_OT_USER                                                                     |
-                                 __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK)       |
-                                 __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK)        ,
-                                 hopamp->Init.UserTrimming                                                             |
-                                 __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueN) |
-                                 __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValueP)  );
-        }
-        else
-        {
-          /* Set calibration mode to factory */
-          CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-        }
-        
-      }
-      else
-      {
-        /* Set low power mode */
-        SET_BIT(tmp_csr, __OPAMP_CSR_OPAXLPM(hopamp));
-        
-        if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER)
-        {
-          /* Set calibration mode to user trimming */
-          SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-          
-          /* Set values for transistors differential pair high (PMOS) and low */
-          /* (NMOS) for low power mode.                                       */
-          MODIFY_REG(OPAMP->LPOTR, __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, OPAMP_TRIM_VALUE_MASK)               |
-                                   __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, OPAMP_TRIM_VALUE_MASK)                ,
-                                   __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_N, hopamp->Init.TrimmingValueNLowPower) |
-                                   __OPAMP_OFFSET_TRIM_SET(hopamp, OPAMP_FACTORYTRIMMING_P, hopamp->Init.TrimmingValuePLowPower)  );
-        }
-        else
-        {
-          /* Set calibration mode to factory trimming */
-          CLEAR_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-        }
-        
-      }
-      
-      
-      /* Configure the power supply range */
-      MODIFY_REG(tmp_csr, OPAMP_CSR_AOP_RANGE,
-                          hopamp->Init.PowerSupplyRange);
-      
-      /* Set OPAMP CSR register from temporary variable */
-      /* This allows to apply all changes on one time, in case of update on   */
-      /* the fly with OPAMP previously set and running:                       */
-      /*  - to avoid hazardous transient switches settings (risk of short     */
-      /*    circuit)                                                          */
-      /*  - to avoid interruption of input signal                             */
-      OPAMP->CSR = tmp_csr;
-
-                
-      /* Update the OPAMP state */
-      /* If coming from state reset: Update from state RESET to state READY */
-      /* else: remain in state READY or BUSY (no update) */
-      if (hopamp->State == HAL_OPAMP_STATE_RESET)
-      {
-        hopamp->State = HAL_OPAMP_STATE_READY;
-      }
-    }
-  }
-  
-  return status;
-}
-
-
-/**
-  * @brief  DeInitializes the OPAMP peripheral 
-  * @note   Deinitialization can't be performed if the OPAMP configuration is locked.
-  *         To unlock the configuration, perform a system reset.
-  * @param  hopamp: OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_DeInit(OPAMP_HandleTypeDef* hopamp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  /* DeInit not allowed if calibration is ongoing */
-  if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
-                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-    
-    /* Open all switches on non-inverting input, inverting input and output   */
-    /* feedback.                                                              */
-    CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp));
-
-    /* DeInit the low level hardware */
-    HAL_OPAMP_MspDeInit(hopamp);
-
-  /* Update the OPAMP state*/
-    hopamp->State = HAL_OPAMP_STATE_RESET;
-  }
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hopamp);
-  
-  return status;
-}
-
-
-/**
-  * @brief  Initializes the OPAMP MSP.
-  * @param  hopamp: OPAMP handle
-  * @retval None
-  */
-__weak void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef* hopamp)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the function "HAL_OPAMP_MspInit()" must be implemented in the user file.
-  */
-}
-
-/**
-  * @brief  DeInitializes OPAMP MSP.
-  * @param  hopamp: OPAMP handle
-  * @retval None
-  */
-__weak void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef* hopamp)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the function "HAL_OPAMP_MspDeInit()" must be implemented in the user file.
-  */
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group2 IO operation functions 
-  * @brief   IO operation functions 
-  *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the OPAMP
-    start, stop and calibration actions.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Start the opamp
-  * @param  hopamp: OPAMP handle
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef* hopamp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-    
-    if(hopamp->State == HAL_OPAMP_STATE_READY)
-    {
-      /* Enable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp));
-      
-      /* Update the OPAMP state */
-      /* From HAL_OPAMP_STATE_READY to HAL_OPAMP_STATE_BUSY */
-      hopamp->State = HAL_OPAMP_STATE_BUSY;   
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-    
-   }
-  return status;
-}
-
-/**
-  * @brief  Stop the opamp 
-  * @param  hopamp: OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef* hopamp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-    
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  /* Check if OPAMP calibration ongoing */
-  if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED) \
-                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY))  
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
-    if(hopamp->State == HAL_OPAMP_STATE_BUSY)
-    {
-      /* Disable the selected opamp */
-      SET_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp)); 
-      
-      /* Update the OPAMP state*/     
-      /* From  HAL_OPAMP_STATE_BUSY to HAL_OPAMP_STATE_READY*/
-      hopamp->State = HAL_OPAMP_STATE_READY;
-    }
-    else
-    {
-      status = HAL_ERROR;
-    }
-  }
-  return status;
-}
-
-/**
-  * @brief  Run the self calibration of one OPAMP
-  * @note   Trimming values (PMOS & NMOS) are updated and user trimming is 
-  *         enabled is calibration is succesful.
-  * @note   Calibration is performed in the mode specified in OPAMP init
-  *         structure (mode normal or low-power). To perform calibration for
-  *         both modes, repeat this function twice after OPAMP init structure
-  *         accordingly updated.
-  * @note   Calibration runs about 10 ms (5 dichotmy steps, repeated for P  
-  *         and N transistors: 10 steps with 1 ms for each step).
-  * @param  hopamp: handle
-  * @retval Updated offset trimming values (PMOS & NMOS), user trimming is enabled
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef* hopamp)
-{ 
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  uint32_t* opamp_trimmingvalue = 0;
-  uint32_t opamp_trimmingvaluen = 0;
-  uint32_t opamp_trimmingvaluep = 0;
-  
-  uint32_t trimming_diff_pair = 0;           /* Selection of differential transistors pair high or low */
-
-  __IO uint32_t* tmp_opamp_reg_trimming;     /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  uint32_t tmp_opamp_otr_otuser = 0;         /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */
-
-  uint32_t tmp_Opaxcalout_DefaultSate = 0;   /* Bit OPAMP_CSR_OPAXCALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-
-  uint32_t tmp_OpaxSwitchesContextBackup = 0;
-  
-  uint8_t trimming_diff_pair_iteration_count = 0;
-  uint8_t delta = 0;
-
-  
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-  
-    /* Check if OPAMP in calibration mode and calibration not yet enable */
-    if(hopamp->State == HAL_OPAMP_STATE_READY)
-    {
-      /* Check the parameter */
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-      assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-      
-      /* Update OPAMP state */
-      hopamp->State = HAL_OPAMP_STATE_CALIBBUSY;
-      
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp));
-  
-      /* Open all switches on non-inverting input, inverting input and output */
-      /* feedback.                                                            */
-      CLEAR_BIT(OPAMP->CSR, __OPAMP_CSR_ALL_SWITCHES(hopamp));
-
-      /* Set calibration mode to user programmed trimming values */
-      SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-
-      
-      /* Select trimming settings depending on power mode */
-      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp_otr_otuser = 0x00000000;
-        tmp_opamp_reg_trimming = &OPAMP->LPOTR;
-      }
-
-      
-      /* Enable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, __OPAMP_CSR_OPAXPD(hopamp));
-
-      /* Perform trimming for both differential transistors pair high and low */
-      for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++)
-      {
-        if (trimming_diff_pair_iteration_count == 0)
-        {
-          /* Calibration of transistors differential pair high (NMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_N;
-          opamp_trimmingvalue = &opamp_trimmingvaluen;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opaxcalout_DefaultSate = RESET;
-
-          /* Enable calibration for N differential pair */
-          MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_L(hopamp),
-                                 __OPAMP_CSR_OPAXCAL_H(hopamp) );
-        }
-        else /* (trimming_diff_pair_iteration_count == 1) */
-        {
-          /* Calibration of transistors differential pair low (PMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_P;
-          opamp_trimmingvalue = &opamp_trimmingvaluep;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opaxcalout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp);
-          
-          /* Enable calibration for P differential pair */
-          MODIFY_REG(OPAMP->CSR, __OPAMP_CSR_OPAXCAL_H(hopamp),
-                                 __OPAMP_CSR_OPAXCAL_L(hopamp) );
-        }
-        
-      
-        /* Perform calibration parameter search by dichotomy sweep */
-        /*  - Delta initial value 16: for 5 dichotomy steps: 16 for the       */
-        /*    initial range, then successive delta sweeps (8, 4, 2, 1).       */
-        /*    can extend the search range to +/- 15 units.                    */
-        /*  - Trimming initial value 15: search range will go from 0 to 30    */
-        /*    (Trimming value 31 is forbidden).                               */
-        *opamp_trimmingvalue = 15;
-        delta = 16;
-
-        while (delta != 0)
-        {
-          /* Set candidate trimming */               
-          MODIFY_REG(*tmp_opamp_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                              __OPAMP_OFFSET_TRIM_SET(hopamp, trimming_diff_pair, *opamp_trimmingvalue) | tmp_opamp_otr_otuser);
-          
-          /* Offset trimming time: during calibration, minimum time needed    */
-          /* between two steps to have 1 mV accuracy.                         */
-          HAL_Delay(OPAMP_TRIMMING_DELAY);
-
-          /* Divide range by 2 to continue dichotomy sweep */
-          delta >>= 1;
-            
-          /* Set trimming values for next iteration in function of trimming   */
-          /* result toggle (versus initial state).                            */
-          if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp)) != tmp_Opaxcalout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp_trimmingvalue += delta;
-          }
-        }
-        
-      }
-       
-      /* Disable calibration for P and N differential pairs */
-      /* Disable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, (__OPAMP_CSR_OPAXCAL_H(hopamp) | 
-                              __OPAMP_CSR_OPAXCAL_L(hopamp) |
-                              __OPAMP_CSR_OPAXPD(hopamp))    );
-
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup);
-      
-      /* Self calibration is successful */
-      /* Store calibration (user trimming) results in init structure. */
-      
-      /* Set user trimming mode */  
-      hopamp->Init.UserTrimming = OPAMP_TRIMMING_USER;
-      
-      /* Affect calibration parameters depending on mode normal/low power */
-      if (hopamp->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Write calibration result N */
-        hopamp->Init.TrimmingValueN = opamp_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp->Init.TrimmingValueP = opamp_trimmingvaluep;
-      }
-      else
-      {
-        /* Write calibration result N */
-        hopamp->Init.TrimmingValueNLowPower = opamp_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp->Init.TrimmingValuePLowPower = opamp_trimmingvaluep;
-      }
-      
-      /* Update OPAMP state */
-      hopamp->State = HAL_OPAMP_STATE_READY;
-
-    }
-    else
-    {
-      /* OPAMP can not be calibrated from this mode */ 
-      status = HAL_ERROR;
-    }
-  }
-
-  return status;
-}
-
-/**
-  * @brief  Return the OPAMP factory trimming value
-  *         Caution: On STM32L1 OPAMP, user can retrieve factory trimming if 
-  *                  OPAMP has never been set to user trimming before.
-  *                  Therefore, this fonction must be called when OPAMP init  
-  *                  parameter "UserTrimming" is set to trimming factory, 
-  *                  and before OPAMP  calibration (function 
-  *                  "HAL_OPAMP_SelfCalibrate()").
-  *                  Otherwise, factory triming value cannot be retrieved and 
-  *                  error status is returned.
-  * @param  hopamp : OPAMP handle
-  * @param  trimmingoffset : Trimming offset (P or N)
-  *         This parameter must be a value of @ref OPAMP_FactoryTrimming
-  * @note   Calibration parameter retrieved is corresponding to the mode 
-  *         specified in OPAMP init structure (mode normal or low-power). 
-  *         To retrieve calibration parameters for both modes, repeat this 
-  *         function after OPAMP init structure accordingly updated.
-  * @retval Trimming value (P or N): range: 0->31
-  *         or OPAMP_FACTORYTRIMMING_DUMMY if trimming value is not available
-  * @{
-  */
-OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset)
-{ 
-  OPAMP_TrimmingValueTypeDef trimmingvalue;
-  __IO uint32_t* tmp_opamp_reg_trimming;  /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  
-  /* Check the OPAMP handle allocation */
-  /* Value can be retrieved in HAL_OPAMP_STATE_READY state */
-  if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET)
-                      || (hopamp->State == HAL_OPAMP_STATE_BUSY)
-                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
-                      || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
-  {
-    trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-    assert_param(IS_OPAMP_FACTORYTRIMMING(trimmingoffset));
-    assert_param(IS_OPAMP_POWERMODE(hopamp->Init.PowerMode));
-    
-    /* Check the trimming mode */
-    if (hopamp->Init.UserTrimming == OPAMP_TRIMMING_USER) 
-    {
-      /* This fonction must called when OPAMP init parameter "UserTrimming"   */
-      /* is set to trimming factory, and before OPAMP calibration (function   */
-      /* "HAL_OPAMP_SelfCalibrate()").                                        */
-      /* Otherwise, factory triming value cannot be retrieved and error       */
-      /* status is returned.                                                  */
-      trimmingvalue = OPAMP_FACTORYTRIMMING_DUMMY;
-    }
-    else
-    {
-      /* Select trimming settings depending on power mode */
-      if (hopamp->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp_reg_trimming = &OPAMP->LPOTR;
-      }
-        
-      /* Get factory trimming  */
-      trimmingvalue = ((*tmp_opamp_reg_trimming >> __OPAMP_OFFSET_TRIM_BITSPOSITION(hopamp, trimmingoffset)) & OPAMP_TRIM_VALUE_MASK);
-      }
-  }
-  
-  return trimmingvalue;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-      
-/** @defgroup OPAMP_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Lock the selected opamp configuration.
-  *         Caution: On STM32L1, HAL OPAMP lock is software lock only (not 
-  *         hardware lock as on some other STM32 devices)
-  * @param  hopamp: OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef* hopamp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  /* OPAMP can be locked when enabled and running in normal mode */ 
-  /*   It is meaningless otherwise */
-  if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET) \
-                      || (hopamp->State == HAL_OPAMP_STATE_READY) \
-                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)\
-                      || (hopamp->State == HAL_OPAMP_STATE_BUSYLOCKED))
-  
-  {
-    status = HAL_ERROR;
-  }
-  
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-  
-   /* OPAMP state changed to locked */
-    hopamp->State = HAL_OPAMP_STATE_BUSYLOCKED;
-  }
-  return status; 
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup OPAMP_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time the status of the peripheral.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the OPAMP state
-  * @param  hopamp : OPAMP handle
-  * @retval HAL state
-  */
-HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef* hopamp)
-{
-  /* Check the OPAMP handle allocation */
-  if(hopamp == HAL_NULL)
-  {
-    return HAL_OPAMP_STATE_RESET;
-  }
-
-  /* Check the parameter */
-  assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-
-  return hopamp->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,533 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_opamp.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of OPAMP HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_OPAMP_H
-#define __STM32L1xx_HAL_OPAMP_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup OPAMP
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup OPAMP_Exported_Types OPAMP Exported Types
-  * @{
-  */
-/** 
-  * @brief  OPAMP Init structure definition  
-  */
-  
-typedef struct
-{
-  uint32_t PowerSupplyRange;            /*!< Specifies the power supply range: above or under 2.4V.
-                                             This parameter must be a value of @ref OPAMP_PowerSupplyRange
-                                             Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */
-  
-  uint32_t UserTrimming;                /*!< Specifies the trimming mode 
-                                             This parameter must be a value of @ref OPAMP_UserTrimming 
-                                             UserTrimming is either factory or user trimming.
-                                             Caution: This parameter is common to all OPAMP instances: a modification of this parameter for the selected OPAMP impacts the other OPAMP instances. */
-  
-  uint32_t Mode;                        /*!< Specifies the OPAMP mode
-                                             This parameter must be a value of @ref OPAMP_Mode 
-                                             mode is either Standalone or Follower */
-
-  uint32_t InvertingInput;              /*!< Specifies the inverting input in Standalone mode
-                                               - In Standalone mode:   i.e when mode is OPAMP_STANDALONE_MODE
-                                                 This parameter must be a value of @ref OPAMP_InvertingInput 
-                                                 InvertingInput is either VM0 or VM1
-                                               - In Follower mode:     i.e when mode is OPAMP_FOLLOWER_MODE
-                                                 This parameter is Not Applicable */ 
-
-  uint32_t NonInvertingInput;           /*!< Specifies the non inverting input of the opamp: 
-                                             This parameter must be a value of @ref OPAMP_NonInvertingInput 
-                                             NonInvertingInput is either VP0, VP1 or VP2 */                                   
-
-  uint32_t PowerMode;                   /*!< Specifies the power mode Normal or Low-Power.
-                                             This parameter must be a value of @ref OPAMP_PowerMode */
-
-  uint32_t TrimmingValueP;              /*!< Specifies the offset trimming value (PMOS)
-                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
-                                             This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */
-
-  uint32_t TrimmingValueN;              /*!< Specifies the offset trimming value (NMOS)
-                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
-                                             This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */
-
-  uint32_t TrimmingValuePLowPower;      /*!< Specifies the offset trimming value (PMOS)
-                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
-                                             This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */
-
-  uint32_t TrimmingValueNLowPower;      /*!< Specifies the offset trimming value (NMOS)
-                                             i.e. when UserTrimming is OPAMP_TRIMMING_USER. 
-                                             This parameter must be a number between Min_Data = 0 and Max_Data = 30 (Trimming value 31 is forbidden) */
-
-}OPAMP_InitTypeDef;
-
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-
-typedef enum
-{
-  HAL_OPAMP_STATE_RESET               = 0x00000000, /*!< OPMAP is not yet Initialized          */
-  
-  HAL_OPAMP_STATE_READY               = 0x00000001, /*!< OPAMP is initialized and ready for use */
-  HAL_OPAMP_STATE_CALIBBUSY           = 0x00000002, /*!< OPAMP is enabled in auto calibration mode */
- 
-  HAL_OPAMP_STATE_BUSY                = 0x00000004, /*!< OPAMP is enabled and running in normal mode */                                                                           
-  HAL_OPAMP_STATE_BUSYLOCKED          = 0x00000005, /*!< OPAMP is locked
-                                                         only system reset allows reconfiguring the opamp. */
-    
-}HAL_OPAMP_StateTypeDef;
-
-/** 
-  * @brief  OPAMP Handle Structure definition 
-  */ 
-typedef struct
-{
-  OPAMP_TypeDef       *Instance;                    /*!< OPAMP instance's registers base address   */
-  OPAMP_InitTypeDef   Init;                         /*!< OPAMP required parameters */
-  HAL_StatusTypeDef Status;                         /*!< OPAMP peripheral status   */
-  HAL_LockTypeDef   Lock;                           /*!< Locking object          */
-  __IO HAL_OPAMP_StateTypeDef  State;               /*!< OPAMP communication state */
-  
-} OPAMP_HandleTypeDef;
-
-/** 
-  * @brief OPAMP_TrimmingValueTypeDef @brief   definition 
-  */ 
-
-typedef  uint32_t OPAMP_TrimmingValueTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup OPAMP_Exported_Constants OPAMP Exported Constants
-  * @{
-  */
-
-/**
-  * OTR register Mask 
-  */
-#define OPAMP_TRIM_VALUE_MASK   OPAMP_OTR_AO1_OPT_OFFSET_TRIM_LOW
-    
-/**
-  * CSR register Mask 
-  */
-#define OPAMP_CSR_INSTANCE_OFFSET   ((uint32_t)  8) /* Offset of each OPAMP instance into register CSR */
-#define OPAMP_OTR_INSTANCE_OFFSET   ((uint32_t) 10) /* Offset of each OPAMP instance into register OTR */
-    
-        
-/** @defgroup OPAMP_Mode OPAMP Mode
-  * @{
-  */
-#define OPAMP_STANDALONE_MODE            ((uint32_t)0x00000000) /*!< OPAMP standalone mode */
-#define OPAMP_FOLLOWER_MODE              ((uint32_t)0x00000001) /*!< OPAMP follower mode */
-
-#define IS_OPAMP_FUNCTIONAL_NORMALMODE(INPUT) (((INPUT) == OPAMP_STANDALONE_MODE) || \
-                                               ((INPUT) == OPAMP_FOLLOWER_MODE))
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_NonInvertingInput OPAMP NonInvertingInput
-  * @{
-  */
-#define OPAMP_NONINVERTINGINPUT_VP0      ((uint32_t)0x00000000)  /*!< Comparator non-inverting input connected to dedicated IO pin low-leakage */
-#define OPAMP_NONINVERTINGINPUT_DAC_CH1  ((uint32_t)0x00000001)  /*!< Comparator non-inverting input connected internally to DAC channel 1 */
-#define OPAMP_NONINVERTINGINPUT_DAC_CH2  ((uint32_t)0x00000002)  /*!< Comparator non-inverting input connected internally to DAC channel 2. Available on OPAMP2 only. */
-
-#define IS_OPAMP_NONINVERTING_INPUT(INPUT) (((INPUT) == OPAMP_NONINVERTINGINPUT_VP0)     || \
-                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH1) || \
-                                            ((INPUT) == OPAMP_NONINVERTINGINPUT_DAC_CH2)   )
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_InvertingInput OPAMP InvertingInput
-  * @{
-  */
-#define OPAMP_INVERTINGINPUT_VM0         ((uint32_t)0x00000000)  /*!< Comparator inverting input connected to dedicated IO pin low-leakage */
-#define OPAMP_INVERTINGINPUT_VM1         ((uint32_t)0x00000001)  /*!< Comparator inverting input connected to alternative IO pin available on some device packages */
-
-#define OPAMP_INVERTINGINPUT_VINM        OPAMP_INVERTINGINPUT_VM1  /*!< Alternate name for comparator inverting input connected to alternative IO pin available on some device packages */
-
-#define IOPAMP_INVERTINGINPUT_VM0        OPAMP_INVERTINGINPUT_VM0  /* For compatibility with other STM32 devices */
-#define IOPAMP_INVERTINGINPUT_VM1        OPAMP_INVERTINGINPUT_VM1  /* For compatibility with other STM32 devices */
-
-#define IS_OPAMP_INVERTING_INPUT(INPUT) (((INPUT) == OPAMP_INVERTINGINPUT_VM0) || \
-                                         ((INPUT) == OPAMP_INVERTINGINPUT_VM1)   )
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_PowerMode OPAMP PowerMode
-  * @{
-  */
-#define OPAMP_POWERMODE_NORMAL        ((uint32_t)0x00000000)
-#define OPAMP_POWERMODE_LOWPOWER      ((uint32_t)0x00000001)
-
-#define IS_OPAMP_POWERMODE(TRIMMING) (((TRIMMING) == OPAMP_POWERMODE_NORMAL) || \
-                                      ((TRIMMING) == OPAMP_POWERMODE_LOWPOWER) )
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_PowerSupplyRange OPAMP PowerSupplyRange
-  * @{
-  */
-#define OPAMP_POWERSUPPLY_LOW          ((uint32_t)0x00000000)  /*!< Power supply range low (VDDA lower than 2.4V) */
-#define OPAMP_POWERSUPPLY_HIGH         OPAMP_CSR_AOP_RANGE     /*!< Power supply range high (VDDA higher than 2.4V) */
-
-#define IS_OPAMP_POWER_SUPPLY_RANGE(RANGE) (((RANGE) == OPAMP_POWERSUPPLY_LOW) || \
-                                            ((RANGE) == OPAMP_POWERSUPPLY_HIGH)  )
-/**
-  * @}
-  */ 
-
-/** @defgroup OPAMP_UserTrimming OPAMP UserTrimming
-  * @{
-  */
-#define OPAMP_TRIMMING_FACTORY        ((uint32_t)0x00000000)                          /*!< Factory trimming */
-#define OPAMP_TRIMMING_USER           OPAMP_OTR_OT_USER                               /*!< User trimming */
-
-#define IS_OPAMP_TRIMMING(TRIMMING) (((TRIMMING) == OPAMP_TRIMMING_FACTORY) || \
-                                     ((TRIMMING) == OPAMP_TRIMMING_USER))
-/**
-  * @}
-  */
-
-/** @defgroup OPAMP_FactoryTrimming OPAMP FactoryTrimming
-  * @{
-  */
-#define OPAMP_FACTORYTRIMMING_DUMMY    ((uint32_t)0xFFFFFFFF)                           /*!< Dummy value if trimming value could not be retrieved */
-
-#define OPAMP_FACTORYTRIMMING_P        ((uint32_t)0x00000000)                           /*!< Offset trimming P */
-#define OPAMP_FACTORYTRIMMING_N        POSITION_VAL(OPAMP_OTR_AO1_OPT_OFFSET_TRIM_HIGH) /*!< Offset trimming N */
-
-#define IS_OPAMP_FACTORYTRIMMING(TRIMMING) (((TRIMMING) == OPAMP_FACTORYTRIMMING_N) || \
-                                            ((TRIMMING) == OPAMP_FACTORYTRIMMING_P)   )
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private constants ---------------------------------------------------------*/
-/** @defgroup OPAMP_Private_Constants OPAMP Private Constants
-  * @{
-  */
-
-/* Offset trimming time: during calibration, minimum time needed between two  */
-/* steps to have 1 mV accuracy.                                               */
-/* Refer to datasheet, electrical characteristics: parameter tOFFTRIM Typ=1ms.*/
-/* Unit: ms.                                                                  */
-#define OPAMP_TRIMMING_DELAY               ((uint32_t) 1)
-
-/**
-  * @}
-  */
-
-    
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup OPAMP_Private_Macro OPAMP Private Macro
-  * @{
-  */
-    
-/** @brief Reset OPAMP handle state
-  * @param  __HANDLE__: OPAMP handle.
-  * @retval None
-  */
-#define __HAL_OPAMP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_OPAMP_STATE_RESET)
-    
-/**
-  * @}
-  */
-
-    
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup OPAMP_Private_Macro OPAMP Private Macro
-  * @{
-  */
-
-/**
-  * @brief Select the OPAMP bit OPAxPD (power-down) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_OPAXPD(__HANDLE__)                                         \
-  (OPAMP_CSR_OPA1PD << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-    
-/**
-  * @brief Select the OPAMP bit S3SELx (switch 3) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_S3SELX(__HANDLE__)                                         \
-  (OPAMP_CSR_S3SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit S4SELx (switch 4) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_S4SELX(__HANDLE__)                                         \
-  (OPAMP_CSR_S4SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit S5SELx (switch 5) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_S5SELX(__HANDLE__)                                         \
-  (OPAMP_CSR_S5SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit S3SELx (switch 6) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_S6SELX(__HANDLE__)                                         \
-  (OPAMP_CSR_S6SEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit OPAxCAL_L (offset calibration for differential 
-  * pair P) corresponding to the selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_OPAXCAL_L(__HANDLE__)                                      \
-  (OPAMP_CSR_OPA1CAL_L << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-    
-/**
-  * @brief Select the OPAMP bit OPAxCAL_H (offset calibration for differential 
-  * pair N) corresponding to the selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_OPAXCAL_H(__HANDLE__)                                      \
-  (OPAMP_CSR_OPA1CAL_H << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-
-/**
-  * @brief Select the OPAMP bit OPAxLPM (low power mode) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_OPAXLPM(__HANDLE__)                                        \
-  (OPAMP_CSR_OPA1LPM << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))
-    
-/**
-  * @brief Select the OPAMP bits of all switches corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_ALL_SWITCHES(__HANDLE__)                                   \
-  ( ( ((__HANDLE__)->Instance != OPAMP2)                                       \
-    )?                                                                         \
-     (                                                                         \
-       ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))  \
-       |                                                                       \
-       (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__)))        \
-     )                                                                         \
-    :                                                                          \
-     (                                                                         \
-       ((OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1) << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__) * OPAMP_CSR_INSTANCE_OFFSET))  \
-       |                                                                       \
-       (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__)))        \
-       |                                                                       \
-       (OPAMP_CSR_S7SEL2)                                                      \
-     )                                                                         \
-  )
-    
-/**
-  * @brief Select the OPAMP bit ANAWSELx (switch SanA) corresponding to the
-  * selected OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_ANAWSELX(__HANDLE__)                                       \
-  (OPAMP_CSR_ANAWSEL1 << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__)))
-
-/**
-  * @brief Select the OPAMP bit OPAxCALOUT in function of the selected 
-  * OPAMP instance.
-  * @param __HANDLE__: OPAMP handle
-  * @retval None
-  */
-#define __OPAMP_CSR_OPAXCALOUT(__HANDLE__)                                     \
-  (OPAMP_CSR_OPA1CALOUT << (__OPAMP_INSTANCE_DECIMAL__(__HANDLE__)))
-
-/**
-  * @brief Select the OPAMP trimming bits position value (position of LSB) 
-  * in register OPAMP_OTR or register OPAMP_LPOTR in function of the selected
-  * OPAMP instance and the transistors differential pair high (PMOS) or 
-  * low (NMOS).
-  * @param __HANDLE__: OPAMP handle
-  * @param __TRIM_HIGH_LOW__: transistors differential pair high or low.
-  * Must be a value of @ref OPAMP_FactoryTrimming.
-  * @retval None
-  */
-#define __OPAMP_OFFSET_TRIM_BITSPOSITION(__HANDLE__, __TRIM_HIGH_LOW__)        \
-  ((__OPAMP_INSTANCE_DECIMAL__((__HANDLE__)) * OPAMP_OTR_INSTANCE_OFFSET) + (__TRIM_HIGH_LOW__))
-    
-/**
-  * @brief Shift the OPAMP trimming bits to register OPAMP_OTR or register 
-  * OPAMP_LPOTR in function of the selected OPAMP instance and the transistors
-  * differential pair high (PMOS) or low (NMOS).
-  * @param __HANDLE__: OPAMP handle
-  * @param __TRIM_HIGH_LOW__: transistors differential pair high or low.
-  * Must be a value of @ref OPAMP_FactoryTrimming.
-  * @param __TRIMMING_VALUE__: Trimming value
-  * @retval None
-  */
-#define __OPAMP_OFFSET_TRIM_SET(__HANDLE__, __TRIM_HIGH_LOW__, __TRIMMING_VALUE__) \
-  ((__TRIMMING_VALUE__) << (__OPAMP_OFFSET_TRIM_BITSPOSITION((__HANDLE__), (__TRIM_HIGH_LOW__))))
-    
-/**
-  * @brief Check that trimming value is within correct range
-  * @param TRIMMINGVALUE: OPAMP trimming value
-  * @retval None
-  */
-#define IS_OPAMP_TRIMMINGVALUE(TRIMMINGVALUE) ((TRIMMINGVALUE) <= 0x1E)
-
-/**
-  * @}
-  */
-
-    
-/* Include OPAMP HAL Extension module */
-#include "stm32l1xx_hal_opamp_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup OPAMP_Exported_Functions
-  * @{
-  */ 
-
-/** @addtogroup OPAMP_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_OPAMP_Init(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_DeInit (OPAMP_HandleTypeDef *hopamp);
-void HAL_OPAMP_MspInit(OPAMP_HandleTypeDef *hopamp);
-void HAL_OPAMP_MspDeInit(OPAMP_HandleTypeDef *hopamp);
-/**
-  * @}
-  */
-
-/** @addtogroup OPAMP_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions  *****************************************************/
-HAL_StatusTypeDef HAL_OPAMP_Start(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_Stop(OPAMP_HandleTypeDef *hopamp);
-HAL_StatusTypeDef HAL_OPAMP_SelfCalibrate(OPAMP_HandleTypeDef *hopamp);
-OPAMP_TrimmingValueTypeDef HAL_OPAMP_GetTrimOffset (OPAMP_HandleTypeDef *hopamp, uint32_t trimmingoffset);
-/**
-  * @}
-  */
-
-/** @addtogroup OPAMP_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_OPAMP_Lock(OPAMP_HandleTypeDef *hopamp);
-/**
-  * @}
-  */
-
-/** @addtogroup OPAMP_Exported_Functions_Group4
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_OPAMP_StateTypeDef HAL_OPAMP_GetState(OPAMP_HandleTypeDef *hopamp);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_OPAMP_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,757 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_opamp_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Extended OPAMP HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (OPAMP) peripheral:
-  *           + Extended Initialization and de-initialization functions
-  *           + Extended Peripheral Control functions
-  *         
-  @verbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup OPAMPEx OPAMPEx
-  * @brief OPAMP Extended HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_OPAMP_MODULE_ENABLED
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-  
-/** @addtogroup OPAMPEx_Exported_Functions OPAMPEx Exported Functions
-  * @{
-  */
-
-/** @addtogroup OPAMPEx_Exported_Functions_Group1
-  * @brief    Extended operation functions
-  *
-@verbatim
- ===============================================================================
-              ##### Extended IO operation functions #####
- ===============================================================================
-  [..]
-      (+) OPAMP Self calibration. 
-
-@endverbatim
-  * @{
-  */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/*  3 OPAMPS available */
-/*  3 OPAMPS can be calibrated in parallel */
-
-/**
-  * @brief  Run the self calibration of the 3 OPAMPs in parallel.
-  * @note   Trimming values (PMOS & NMOS) are updated and user trimming is 
-  *         enabled is calibration is succesful.
-  * @note   Calibration is performed in the mode specified in OPAMP init
-  *         structure (mode normal or low-power). To perform calibration for
-  *         both modes, repeat this function twice after OPAMP init structure
-  *         accordingly updated.
-  * @note   Calibration runs about 10 ms (5 dichotmy steps, repeated for P  
-  *         and N transistors: 10 steps with 1 ms for each step).
-  * @param  hopamp1 handle
-  * @param  hopamp2 handle
-  * @param  hopamp3 handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  uint32_t* opamp1_trimmingvalue = 0;
-  uint32_t opamp1_trimmingvaluen = 0;
-  uint32_t opamp1_trimmingvaluep = 0;
-  
-  uint32_t* opamp2_trimmingvalue = 0;
-  uint32_t opamp2_trimmingvaluen = 0;
-  uint32_t opamp2_trimmingvaluep = 0;
-  
-  uint32_t* opamp3_trimmingvalue = 0;
-  uint32_t opamp3_trimmingvaluen = 0;
-  uint32_t opamp3_trimmingvaluep = 0;
-  
-  uint32_t trimming_diff_pair = 0;          /* Selection of differential transistors pair high or low */
-
-  __IO uint32_t* tmp_opamp1_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  __IO uint32_t* tmp_opamp2_reg_trimming;
-  __IO uint32_t* tmp_opamp3_reg_trimming;
-  uint32_t tmp_opamp1_otr_otuser = 0;       /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */
-  uint32_t tmp_opamp2_otr_otuser = 0;
-  uint32_t tmp_opamp3_otr_otuser = 0;
-  
-  uint32_t tmp_Opa1calout_DefaultSate = 0;  /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-  uint32_t tmp_Opa2calout_DefaultSate = 0;  /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-  uint32_t tmp_Opa3calout_DefaultSate = 0;  /* Bit OPAMP_CSR_OPA3CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-
-  uint32_t tmp_OpaxSwitchesContextBackup = 0;
-  
-  uint8_t trimming_diff_pair_iteration_count = 0;
-  uint8_t delta = 0;
-
-  
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  if((hopamp1 == HAL_NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) ||
-     (hopamp2 == HAL_NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED) ||
-     (hopamp3 == HAL_NULL) || (hopamp3->State == HAL_OPAMP_STATE_BUSYLOCKED)   ) 
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-  
-    /* Check if OPAMP in calibration mode and calibration not yet enable */
-    if((hopamp1->State == HAL_OPAMP_STATE_READY) &&
-       (hopamp2->State == HAL_OPAMP_STATE_READY) &&
-       (hopamp3->State == HAL_OPAMP_STATE_READY)   )
-    {
-      /* Check the parameter */
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp3->Instance));
-      assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
-      assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
-      assert_param(IS_OPAMP_POWERMODE(hopamp3->Init.PowerMode));
-      
-      /* Update OPAMP state */
-      hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY;
-      hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY;
-      hopamp3->State = HAL_OPAMP_STATE_CALIBBUSY;
-      
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);
-      
-      /* Open all switches on non-inverting input, inverting input and output */
-      /* feedback.                                                            */
-      CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);
-      
-      /* Set calibration mode to user programmed trimming values */
-      SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-      
-      /* Select trimming settings depending on power mode */
-      if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp1_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp1_otr_otuser = 0x00000000;
-        tmp_opamp1_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp2_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp2_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp2_otr_otuser = 0x00000000;
-        tmp_opamp2_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      if (hopamp3->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp3_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp3_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp3_otr_otuser = 0x00000000;
-        tmp_opamp3_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      /* Enable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL);
-      
-      /* Perform trimming for both differential transistors pair high and low */
-      for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++)
-      {
-        if (trimming_diff_pair_iteration_count == 0)
-        {
-          /* Calibration of transistors differential pair high (NMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_N;
-          opamp1_trimmingvalue = &opamp1_trimmingvaluen;
-          opamp2_trimmingvalue = &opamp2_trimmingvaluen;
-          opamp3_trimmingvalue = &opamp3_trimmingvaluen;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opa1calout_DefaultSate = RESET;
-          tmp_Opa2calout_DefaultSate = RESET;
-          tmp_Opa3calout_DefaultSate = RESET;
-          
-          /* Enable calibration for N differential pair */
-          MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL,
-                                 OPAMP_CSR_OPAXCAL_H_ALL);
-        }
-        else /* (trimming_diff_pair_iteration_count == 1) */
-        {
-          /* Calibration of transistors differential pair low (PMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_P;
-          opamp1_trimmingvalue = &opamp1_trimmingvaluep;
-          opamp2_trimmingvalue = &opamp2_trimmingvaluep;
-          opamp3_trimmingvalue = &opamp3_trimmingvaluep;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opa1calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp1);
-          tmp_Opa2calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp2);
-          tmp_Opa3calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp3);
-          
-          /* Enable calibration for P differential pair */
-          MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL,
-                                 OPAMP_CSR_OPAXCAL_L_ALL);
-        }
-        
-      
-        /* Perform calibration parameter search by dichotomy sweep */
-        /*  - Delta initial value 16: for 5 dichotomy steps: 16 for the       */
-        /*    initial range, then successive delta sweeps (8, 4, 2, 1).       */
-        /*    can extend the search range to +/- 15 units.                    */
-        /*  - Trimming initial value 15: search range will go from 0 to 30    */
-        /*    (Trimming value 31 is forbidden).                               */
-        *opamp1_trimmingvalue = 15;
-        *opamp2_trimmingvalue = 15;
-        *opamp3_trimmingvalue = 15;
-        delta = 16;
-        
-        while (delta != 0)
-        {
-          /* Set candidate trimming */
-
-          MODIFY_REG(*tmp_opamp1_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                               __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser);
-
-          MODIFY_REG(*tmp_opamp2_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                               __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser);
-
-          MODIFY_REG(*tmp_opamp3_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                               __OPAMP_OFFSET_TRIM_SET(hopamp3, trimming_diff_pair, *opamp3_trimmingvalue) | tmp_opamp3_otr_otuser);
-
-          
-          /* Offset trimming time: during calibration, minimum time needed    */
-          /* between two steps to have 1 mV accuracy.                         */
-          HAL_Delay(OPAMP_TRIMMING_DELAY);
-          
-          /* Divide range by 2 to continue dichotomy sweep */
-          delta >>= 1;
-          
-          /* Set trimming values for next iteration in function of trimming   */
-          /* result toggle (versus initial state).                            */
-          /* Trimming values update with dichotomy delta of previous          */
-          /* iteration.                                                       */
-          if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp1_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp1_trimmingvalue += delta;
-          }
-          
-          /* Set trimming values for next iteration in function of trimming   */
-          /* result toggle (versus initial state).                            */
-          /* Trimming values update with dichotomy delta of previous          */
-          /* iteration.                                                       */
-          if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp2_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp2_trimmingvalue += delta;
-          }
-            
-          /* Set trimming values for next iteration in function of trimming   */
-          /* result toggle (versus initial state).                            */
-          /* Trimming values update with dichotomy delta of previous          */
-          /* iteration.                                                       */
-          if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp3)) != tmp_Opa3calout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp3_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp3_trimmingvalue += delta;
-          }
-          
-        }
-      }
-       
-
-      /* Disable calibration for P and N differential pairs */
-      /* Disable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | 
-                              OPAMP_CSR_OPAXCAL_L_ALL |
-                              OPAMP_CSR_OPAXPD_ALL     ));
-      
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup);
-      
-      /* Self calibration is successful */
-      /* Store calibration (user trimming) results in init structure. */
-      
-      /* Set user trimming mode */  
-      hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
-      hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
-      hopamp3->Init.UserTrimming = OPAMP_TRIMMING_USER;
-      
-      /* Affect calibration parameters depending on mode normal/low power */
-      if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Write calibration result N */
-        hopamp1->Init.TrimmingValueN = opamp1_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp1->Init.TrimmingValueP = opamp1_trimmingvaluep;
-      }
-      else
-      {
-        /* Write calibration result N */
-        hopamp1->Init.TrimmingValueNLowPower = opamp1_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp1->Init.TrimmingValuePLowPower = opamp1_trimmingvaluep;
-      }
-      
-      if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Write calibration result N */
-        hopamp2->Init.TrimmingValueN = opamp2_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp2->Init.TrimmingValueP = opamp2_trimmingvaluep;
-      }
-      else
-      {
-        /* Write calibration result N */
-        hopamp2->Init.TrimmingValueNLowPower = opamp2_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp2->Init.TrimmingValuePLowPower = opamp2_trimmingvaluep;
-      }
-      
-      if (hopamp3->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Write calibration result N */
-        hopamp3->Init.TrimmingValueN = opamp3_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp3->Init.TrimmingValueP = opamp3_trimmingvaluep;
-      }
-      else
-      {
-        /* Write calibration result N */
-        hopamp3->Init.TrimmingValueNLowPower = opamp3_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp3->Init.TrimmingValuePLowPower = opamp3_trimmingvaluep;
-      }
-
-      /* Update OPAMP state */
-      hopamp1->State = HAL_OPAMP_STATE_READY;
-      hopamp2->State = HAL_OPAMP_STATE_READY;
-      hopamp3->State = HAL_OPAMP_STATE_READY;
-
-    }
-    else
-    {
-      /* OPAMP can not be calibrated from this mode */ 
-      status = HAL_ERROR;
-    }
-  }
-
-  return status;
-}
-
-#else
-
-/*  2 OPAMPS available */
-/*  2 OPAMPS can be calibrated in parallel */
-
-/**
-  * @brief  Run the self calibration of the 2 OPAMPs in parallel.
-  * @note   Trimming values (PMOS & NMOS) are updated and user trimming is 
-  *         enabled is calibration is succesful.
-  * @note   Calibration is performed in the mode specified in OPAMP init
-  *         structure (mode normal or low-power). To perform calibration for
-  *         both modes, repeat this function twice after OPAMP init structure
-  *         accordingly updated.
-  * @note   Calibration runs about 10 ms (5 dichotmy steps, repeated for P  
-  *         and N transistors: 10 steps with 1 ms for each step).
-  * @param  hopamp1 handle
-  * @param  hopamp2 handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-  
-  uint32_t* opamp1_trimmingvalue = 0;
-  uint32_t opamp1_trimmingvaluen = 0;
-  uint32_t opamp1_trimmingvaluep = 0;
-  
-  uint32_t* opamp2_trimmingvalue = 0;
-  uint32_t opamp2_trimmingvaluen = 0;
-  uint32_t opamp2_trimmingvaluep = 0;
-  
-  uint32_t trimming_diff_pair = 0;          /* Selection of differential transistors pair high or low */
-
-  __IO uint32_t* tmp_opamp1_reg_trimming;   /* Selection of register of trimming depending on power mode: OTR or LPOTR */
-  __IO uint32_t* tmp_opamp2_reg_trimming;
-  uint32_t tmp_opamp1_otr_otuser = 0;       /* Selection of bit OPAMP_OTR_OT_USER depending on trimming register pointed: OTR or LPOTR */
-  uint32_t tmp_opamp2_otr_otuser = 0;
-  
-  uint32_t tmp_Opa1calout_DefaultSate = 0;  /* Bit OPAMP_CSR_OPA1CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-  uint32_t tmp_Opa2calout_DefaultSate = 0;  /* Bit OPAMP_CSR_OPA2CALOUT default state when trimming value is 00000b. Used to detect the bit toggling */
-
-  uint32_t tmp_OpaxSwitchesContextBackup = 0;
-  
-  uint8_t trimming_diff_pair_iteration_count = 0;
-  uint8_t delta = 0;
-
-  
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  if((hopamp1 == HAL_NULL) || (hopamp1->State == HAL_OPAMP_STATE_BUSYLOCKED) ||
-     (hopamp2 == HAL_NULL) || (hopamp2->State == HAL_OPAMP_STATE_BUSYLOCKED)   ) 
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-  
-    /* Check if OPAMP in calibration mode and calibration not yet enable */
-    if((hopamp1->State == HAL_OPAMP_STATE_READY) &&
-       (hopamp2->State == HAL_OPAMP_STATE_READY)   )
-    {
-      /* Check the parameter */
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp1->Instance));
-      assert_param(IS_OPAMP_ALL_INSTANCE(hopamp2->Instance));
-      assert_param(IS_OPAMP_POWERMODE(hopamp1->Init.PowerMode));
-      assert_param(IS_OPAMP_POWERMODE(hopamp2->Init.PowerMode));
-      
-      /* Update OPAMP state */
-      hopamp1->State = HAL_OPAMP_STATE_CALIBBUSY;
-      hopamp2->State = HAL_OPAMP_STATE_CALIBBUSY;
-      
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      tmp_OpaxSwitchesContextBackup = READ_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);
-      
-      /* Open all switches on non-inverting input, inverting input and output */
-      /* feedback.                                                            */
-      CLEAR_BIT(OPAMP->CSR, OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS);
-      
-      /* Set calibration mode to user programmed trimming values */
-      SET_BIT(OPAMP->OTR, OPAMP_OTR_OT_USER);
-      
-      /* Select trimming settings depending on power mode */
-      if (hopamp1->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp1_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp1_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp1_otr_otuser = 0x00000000;
-        tmp_opamp1_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      if (hopamp2->Init.PowerMode == OPAMP_POWERMODE_NORMAL)
-      {
-        tmp_opamp2_otr_otuser = OPAMP_OTR_OT_USER;
-        tmp_opamp2_reg_trimming = &OPAMP->OTR;
-      }
-      else
-      {
-        tmp_opamp2_otr_otuser = 0x00000000;
-        tmp_opamp2_reg_trimming = &OPAMP->LPOTR;
-      }
-      
-      /* Enable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, OPAMP_CSR_OPAXPD_ALL);
-      
-      /* Perform trimming for both differential transistors pair high and low */
-      for (trimming_diff_pair_iteration_count = 0; trimming_diff_pair_iteration_count <=1; trimming_diff_pair_iteration_count++)
-      {
-        if (trimming_diff_pair_iteration_count == 0)
-        {
-          /* Calibration of transistors differential pair high (NMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_N;
-          opamp1_trimmingvalue = &opamp1_trimmingvaluen;
-          opamp2_trimmingvalue = &opamp2_trimmingvaluen;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opa1calout_DefaultSate = RESET;
-          tmp_Opa2calout_DefaultSate = RESET;
-          
-          /* Enable calibration for N differential pair */
-          MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_L_ALL,
-                                 OPAMP_CSR_OPAXCAL_H_ALL);
-        }
-        else /* (trimming_diff_pair_iteration_count == 1) */
-        {
-          /* Calibration of transistors differential pair low (PMOS) */
-          trimming_diff_pair = OPAMP_FACTORYTRIMMING_P;
-          opamp1_trimmingvalue = &opamp1_trimmingvaluep;
-          opamp2_trimmingvalue = &opamp2_trimmingvaluep;
-          
-          /* Set bit OPAMP_CSR_OPAXCALOUT default state when trimming value   */
-          /* is 00000b. Used to detect the bit toggling during trimming.      */
-          tmp_Opa1calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp1);
-          tmp_Opa2calout_DefaultSate = __OPAMP_CSR_OPAXCALOUT(hopamp2);
-          
-          /* Enable calibration for P differential pair */
-          MODIFY_REG(OPAMP->CSR, OPAMP_CSR_OPAXCAL_H_ALL,
-                                 OPAMP_CSR_OPAXCAL_L_ALL);
-        }
-        
-      
-        /* Perform calibration parameter search by dichotomy sweep */
-        /*  - Delta initial value 16: for 5 dichotomy steps: 16 for the       */
-        /*    initial range, then successive delta sweeps (8, 4, 2, 1).       */
-        /*    can extend the search range to +/- 15 units.                    */
-        /*  - Trimming initial value 15: search range will go from 0 to 30    */
-        /*    (Trimming value 31 is forbidden).                               */
-        *opamp1_trimmingvalue = 15;
-        *opamp2_trimmingvalue = 15;
-        delta = 16;
-        
-        while (delta != 0)
-        {
-          /* Set candidate trimming */
-
-          MODIFY_REG(*tmp_opamp1_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                               __OPAMP_OFFSET_TRIM_SET(hopamp1, trimming_diff_pair, *opamp1_trimmingvalue) | tmp_opamp1_otr_otuser);
-
-          MODIFY_REG(*tmp_opamp2_reg_trimming, __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, OPAMP_TRIM_VALUE_MASK) ,
-                                               __OPAMP_OFFSET_TRIM_SET(hopamp2, trimming_diff_pair, *opamp2_trimmingvalue) | tmp_opamp2_otr_otuser);
-
-          
-          /* Offset trimming time: during calibration, minimum time needed    */
-          /* between two steps to have 1 mV accuracy.                         */
-          HAL_Delay(OPAMP_TRIMMING_DELAY);
-          
-          /* Divide range by 2 to continue dichotomy sweep */
-          delta >>= 1;
-          
-          /* Set trimming values for next iteration in function of trimming   */
-          /* result toggle (versus initial state).                            */
-          if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp1)) != tmp_Opa1calout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp1_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp1_trimmingvalue += delta;
-          }
-          
-          /* Set trimming values for next iteration in function of trimming   */
-          /* result toggle (versus initial state).                            */
-          if (READ_BIT(OPAMP->CSR, __OPAMP_CSR_OPAXCALOUT(hopamp2)) != tmp_Opa2calout_DefaultSate)
-          {
-            /* If calibration output is has toggled, try lower trimming */
-            *opamp2_trimmingvalue -= delta;
-          }
-          else
-          {
-            /* If calibration output is has not toggled, try higher trimming */
-            *opamp2_trimmingvalue += delta;
-          }
-          
-        }
-      }
-       
-
-      /* Disable calibration for P and N differential pairs */
-      /* Disable the selected opamp */
-      CLEAR_BIT (OPAMP->CSR, (OPAMP_CSR_OPAXCAL_H_ALL | 
-                              OPAMP_CSR_OPAXCAL_L_ALL |
-                              OPAMP_CSR_OPAXPD_ALL     ));
-      
-      /* Backup of switches configuration to restore it at the end of the     */
-      /* calibration.                                                         */
-      SET_BIT(OPAMP->CSR, tmp_OpaxSwitchesContextBackup);
-      
-      /* Self calibration is successful */
-      /* Store calibration (user trimming) results in init structure. */
-      
-      /* Set user trimming mode */  
-      hopamp1->Init.UserTrimming = OPAMP_TRIMMING_USER;
-      hopamp2->Init.UserTrimming = OPAMP_TRIMMING_USER;
-      
-      /* Affect calibration parameters depending on mode normal/low power */
-      if (hopamp1->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Write calibration result N */
-        hopamp1->Init.TrimmingValueN = opamp1_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp1->Init.TrimmingValueP = opamp1_trimmingvaluep;
-      }
-      else
-      {
-        /* Write calibration result N */
-        hopamp1->Init.TrimmingValueNLowPower = opamp1_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp1->Init.TrimmingValuePLowPower = opamp1_trimmingvaluep;
-      }
-      
-      if (hopamp2->Init.PowerMode != OPAMP_POWERMODE_LOWPOWER)
-      {
-        /* Write calibration result N */
-        hopamp2->Init.TrimmingValueN = opamp2_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp2->Init.TrimmingValueP = opamp2_trimmingvaluep;
-      }
-      else
-      {
-        /* Write calibration result N */
-        hopamp2->Init.TrimmingValueNLowPower = opamp2_trimmingvaluen;
-        /* Write calibration result P */
-        hopamp2->Init.TrimmingValuePLowPower = opamp2_trimmingvaluep;
-      }
-
-      /* Update OPAMP state */
-      hopamp1->State = HAL_OPAMP_STATE_READY;
-      hopamp2->State = HAL_OPAMP_STATE_READY;
-
-    }
-    else
-    {
-      /* OPAMP can not be calibrated from this mode */ 
-      status = HAL_ERROR;
-    }
-  }
-
-  return status;
-}
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-/** @defgroup OPAMPEx_Exported_Functions_Group2 Extended Peripheral Control functions 
- *  @brief   Extended control functions 
- *
-@verbatim   
- ===============================================================================
-             ##### Peripheral Control functions #####
- ===============================================================================
-    [..]
-      (+) OPAMP unlock. 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Unlock the selected opamp configuration.
-  *         This function must be called only when OPAMP is in state "locked".
-  * @param  hopamp: OPAMP handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef* hopamp)
-{
-  HAL_StatusTypeDef status = HAL_OK;
-
-  /* Check the OPAMP handle allocation */
-  /* Check if OPAMP locked */
-  if((hopamp == HAL_NULL) || (hopamp->State == HAL_OPAMP_STATE_RESET)
-                      || (hopamp->State == HAL_OPAMP_STATE_READY)
-                      || (hopamp->State == HAL_OPAMP_STATE_CALIBBUSY)
-                      || (hopamp->State == HAL_OPAMP_STATE_BUSY))
-  
-  {
-    status = HAL_ERROR;
-  }
-  else
-  {
-    /* Check the parameter */
-    assert_param(IS_OPAMP_ALL_INSTANCE(hopamp->Instance));
-  
-   /* OPAMP state changed to locked */
-    hopamp->State = HAL_OPAMP_STATE_BUSY;
-  }
-  return status; 
-}
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-
-#endif /* HAL_OPAMP_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_opamp_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,225 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_opamp_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of OPAMP HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_OPAMP_EX_H
-#define __STM32L1xx_HAL_OPAMP_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-   
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup OPAMPEx
-  * @{
-  */
-
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants ---------------------------------------------------------*/
-/** @defgroup OPAMPEx_Exported_Constants OPAMPEx Exported Constants
-  * @{
-  */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-#define OPAMP_CSR_OPAXPD_ALL                                                   \
-  (OPAMP_CSR_OPA1PD | OPAMP_CSR_OPA2PD | OPAMP_CSR_OPA3PD)
-    
-#define OPAMP_CSR_OPAXCAL_L_ALL                                                \
-  (OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA2CAL_L | OPAMP_CSR_OPA3CAL_L)
-
-#define OPAMP_CSR_OPAXCAL_H_ALL                                                \
-  (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA2CAL_H | OPAMP_CSR_OPA3CAL_H)
-    
-#define OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS                                      \
-  (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | \
-   OPAMP_CSR_ANAWSEL1                                                        | \
-   OPAMP_CSR_S3SEL2 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S5SEL2 | OPAMP_CSR_S6SEL2 | \
-   OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_S7SEL2                                     | \
-   OPAMP_CSR_S3SEL3 | OPAMP_CSR_S4SEL3 | OPAMP_CSR_S5SEL3 | OPAMP_CSR_S6SEL3 | \
-   OPAMP_CSR_ANAWSEL3                                                         )
-#else
-#define OPAMP_CSR_OPAXPD_ALL                                                   \
-  (OPAMP_CSR_OPA1PD | OPAMP_CSR_OPA2PD)
-    
-#define OPAMP_CSR_OPAXCAL_L_ALL                                                \
-  (OPAMP_CSR_OPA1CAL_L | OPAMP_CSR_OPA2CAL_L)
-
-#define OPAMP_CSR_OPAXCAL_H_ALL                                                \
-  (OPAMP_CSR_OPA1CAL_H | OPAMP_CSR_OPA2CAL_H)
-    
-#define OPAMP_CSR_ALL_SWITCHES_ALL_OPAMPS                                      \
-  (OPAMP_CSR_S3SEL1 | OPAMP_CSR_S4SEL1 | OPAMP_CSR_S5SEL1 | OPAMP_CSR_S6SEL1 | \
-   OPAMP_CSR_ANAWSEL1                                                        | \
-   OPAMP_CSR_S3SEL2 | OPAMP_CSR_S4SEL2 | OPAMP_CSR_S5SEL2 | OPAMP_CSR_S6SEL2 | \
-   OPAMP_CSR_ANAWSEL2 | OPAMP_CSR_S7SEL2                                      )
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-    
-/** @defgroup OPAMPEx_Exported_Macro OPAMPEx Exported Macro
-  * @{
-  */
-    
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-/**
-  * @brief Enable internal analog switch SW1 to connect OPAMP3 ouput to ADC
-  * switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting input
-  * (OPAMP3 available on STM32L1 devices Cat.4 only).
-  * @retval None
-  */
-#define __HAL_OPAMP_OPAMP3OUT_CONNECT_ADC_COMP1()    __HAL_RI_SWITCH_COMP1_SW1_CLOSE()
-
-/**
-  * @brief Disable internal analog switch SW1 to disconnect OPAMP3 ouput from 
-  * ADC switch matrix (ADC channel VCOMP, channel 26) and COMP1 non-inverting
-  * input.
-  * @retval None
-  */
-#define __HAL_OPAMP_OPAMP3OUT_DISCONNECT_ADC_COMP1() __HAL_RI_SWITCH_COMP1_SW1_OPEN()
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-    
-/**
-  * @}
-  */
-      
-/* Private macro -------------------------------------------------------------*/
-
-/** @defgroup OPAMPEx_Private_Macro OPAMPEx Private Macro
-  * @{
-  */
-   
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-/**
-  * @brief Get the OPAMP instance in decimal number for further
-  * processing needs by HAL OPAMP driver functions.
-  * @param __HANDLE__: OPAMP handle
-  * @retval "0" for OPAMP1, "1" for OPAMP2, "2" for OPAMP3
-  */
-#define __OPAMP_INSTANCE_DECIMAL__(__HANDLE__)                                 \
-  ( ( ((__HANDLE__)->Instance == OPAMP1)                                       \
-    )?                                                                         \
-     ((uint32_t)0)                                                             \
-     :                                                                         \
-     ( ( ((__HANDLE__)->Instance == OPAMP2)                                    \
-       )?                                                                      \
-        ((uint32_t)1)                                                          \
-        :                                                                      \
-        ((uint32_t)2)                                                          \
-     )                                                                         \
-  )
-#else
-/**
-  * @brief Get the OPAMP instance in decimal number for further
-  * processing needs by HAL OPAMP driver functions.
-  * @param __HANDLE__: OPAMP handle
-  * @retval "0" for OPAMP1, "1" for OPAMP2
-  */
-#define __OPAMP_INSTANCE_DECIMAL__(__HANDLE__)                                 \
-  ( ( ((__HANDLE__)->Instance == OPAMP1)                                       \
-    )?                                                                         \
-     ((uint32_t)0)                                                             \
-     :                                                                         \
-     ((uint32_t)1)                                                             \
-  )
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-    
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup OPAMPEx_Exported_Functions
-  * @{
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @defgroup OPAMPEx_Exported_Functions_Group1 Extended IO operation functions
-  * @{
-  */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2, OPAMP_HandleTypeDef *hopamp3);
-#else
-HAL_StatusTypeDef HAL_OPAMPEx_SelfCalibrateAll(OPAMP_HandleTypeDef *hopamp1, OPAMP_HandleTypeDef *hopamp2);
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-/**
-  * @}
-  */
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup OPAMPEx_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_OPAMPEx_Unlock(OPAMP_HandleTypeDef *hopamp); 
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_OPAMP_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1345 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pcd.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   PCD HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the USB Peripheral Controller:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                    ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The PCD HAL driver can be used as follows:
-
-     (#) Declare a PCD_HandleTypeDef handle structure, for example:
-         PCD_HandleTypeDef  hpcd;
-        
-     (#) Fill parameters of Init structure in HCD handle
-  
-     (#) Call HAL_PCD_Init() API to initialize the HCD peripheral (Core, Device core, ...) 
-
-     (#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
-         (##) Enable the PCD/USB Low Level interface clock using 
-              (+++) __USB_CLK_ENABLE);
-           
-         (##) Initialize the related GPIO clocks
-         (##) Configure PCD pin-out
-         (##) Configure PCD NVIC interrupt
-    
-     (#)Associate the Upper USB device stack to the HAL PCD Driver:
-         (##) hpcd.pData = pdev;
-
-     (#)Enable HCD transmission and reception:
-         (##) HAL_PCD_Start();
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCD PCD
-  * @brief PCD HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup PCD_Private_Constants PCD Private Constants
-  * @{
-  */ 
-#define BTABLE_ADDRESS                  (0x000)  
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup PCD_Private_Functions PCD Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd);
-static void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-static void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes);
-
-/**
-  * @}
-  */
-
-
-/** @defgroup PCD_Exported_Functions PCD Exported Functions
-  * @{
-  */
-
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim
- ===============================================================================
-            ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the PCD according to the specified
-  *         parameters in the PCD_InitTypeDef and create the associated handle.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{ 
-  uint32_t i = 0;
-
-  uint32_t wInterrupt_Mask = 0;
-  
-  /* Check the PCD handle allocation */
-  if(hpcd == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
-
-  hpcd->State = PCD_BUSY;
-  
-  /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-  HAL_PCD_MspInit(hpcd);
-
- /* Init endpoints structures */
- for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
- {
-   /* Init ep structure */
-   hpcd->IN_ep[i].is_in = 1;
-   hpcd->IN_ep[i].num = i;
-   /* Control until ep is actvated */
-   hpcd->IN_ep[i].type = PCD_EP_TYPE_CTRL;
-   hpcd->IN_ep[i].maxpacket =  0;
-   hpcd->IN_ep[i].xfer_buff = 0;
-   hpcd->IN_ep[i].xfer_len = 0;
- }
- 
- for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
- {
-   hpcd->OUT_ep[i].is_in = 0;
-   hpcd->OUT_ep[i].num = i;
-   /* Control until ep is activated */
-   hpcd->OUT_ep[i].type = PCD_EP_TYPE_CTRL;
-   hpcd->OUT_ep[i].maxpacket = 0;
-   hpcd->OUT_ep[i].xfer_buff = 0;
-   hpcd->OUT_ep[i].xfer_len = 0;
- }
-  
- /* Init Device */
- /*CNTR_FRES = 1*/
- hpcd->Instance->CNTR = USB_CNTR_FRES;
- 
- /*CNTR_FRES = 0*/
- hpcd->Instance->CNTR = 0;
- 
- /*Clear pending interrupts*/
- hpcd->Instance->ISTR = 0;
- 
-  /*Set Btable Adress*/
- hpcd->Instance->BTABLE = BTABLE_ADDRESS;
-  
-  /*set wInterrupt_Mask global variable*/
-  wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
-    | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-  
-  /*Set interrupt mask*/
-  hpcd->Instance->CNTR = wInterrupt_Mask;
-  
-  hpcd->USB_Address = 0;
-  hpcd->State= PCD_READY;
-
- return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the PCD peripheral 
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* Check the PCD handle allocation */
-  if(hpcd == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  hpcd->State = PCD_BUSY;
-  
-  /* Stop Device */
-  HAL_PCD_Stop(hpcd);
-    
-  /* DeInit the low level hardware */
-  HAL_PCD_MspDeInit(hpcd);
-  
-  hpcd->State = PCD_READY; 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the PCD MSP.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_MspInit could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes PCD MSP.
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
-__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_MspDeInit could be implenetd in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PCD_Exported_Functions_Group2 IO operation functions 
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the PCD data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Start The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{ 
-  HAL_PCDEx_SetConnectionState (hpcd, 1);
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop The USB OTG Device.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{ 
-  __HAL_LOCK(hpcd); 
-  
-    /* disable all interrupts and force USB reset */
-  hpcd->Instance->CNTR = USB_CNTR_FRES;
-  
-  /* clear interrupt status register */
-  hpcd->Instance->ISTR = 0;
-  
-  /* switch-off device */
-  hpcd->Instance->CNTR = (USB_CNTR_FRES | USB_CNTR_PDWN);
-  
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles PCD interrupt request.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
-{
-  uint32_t wInterrupt_Mask = 0;
-  
-  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_CTR))
-  {
-    /* servicing of the endpoint correct transfer interrupt */
-    /* clear of the CTR flag into the sub */
-    PCD_EP_ISR_Handler(hpcd);
-  }
-
-  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_RESET))
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_RESET);
-    HAL_PCD_ResetCallback(hpcd);
-    HAL_PCD_SetAddress(hpcd, 0);
-  }
-
-  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_PMAOVRM))
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_PMAOVRM);    
-  }
-  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ERR))
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ERR); 
-  }
-
-  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP))
-  {  
-    hpcd->Instance->CNTR &= ~(USB_CNTR_LP_MODE);
-    
-    /*set wInterrupt_Mask global variable*/
-    wInterrupt_Mask = USB_CNTR_CTRM  | USB_CNTR_WKUPM | USB_CNTR_SUSPM | USB_CNTR_ERRM \
-      | USB_CNTR_ESOFM | USB_CNTR_RESETM;
-    
-    /*Set interrupt mask*/
-    hpcd->Instance->CNTR = wInterrupt_Mask;
-    
-    HAL_PCD_ResumeCallback(hpcd);
-    
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_WKUP);     
-  }
-
-  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SUSP))
-  {    
-    /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SUSP);  
-    
-    /* Force low-power mode in the macrocell */
-    hpcd->Instance->CNTR |= USB_CNTR_FSUSP;
-    hpcd->Instance->CNTR |= USB_CNTR_LP_MODE;
-    if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_WKUP) == 0)
-    {
-      HAL_PCD_SuspendCallback(hpcd);
-    }
-  }
-
-  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_SOF))
-  {
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_SOF); 
-    HAL_PCD_SOFCallback(hpcd);
-  }
-
-  if (__HAL_PCD_GET_FLAG (hpcd, USB_ISTR_ESOF))
-  {
-    /* clear ESOF flag in ISTR */
-    __HAL_PCD_CLEAR_FLAG(hpcd, USB_ISTR_ESOF); 
-  }
-}
-
-/**
-  * @brief  Data out stage callbacks
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DataOutStageCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @brief  Data IN stage callbacks
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DataInStageCallback could be implenetd in the user file
-   */ 
-}
-/**
-  * @brief  Setup stage callback
-  * @param  hpcd: ppp handle
-  * @retval None
-  */
- __weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SetupStageCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @brief  USB Start Of Frame callbacks
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SOFCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @brief  USB Reset callbacks
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ResetCallback could be implenetd in the user file
-   */ 
-}
-
-
-/**
-  * @brief  Suspend event callbacks
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_SuspendCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @brief  Resume event callbacks
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ResumeCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @brief  Incomplete ISO OUT callbacks
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ISOOUTIncompleteCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @brief  Incomplete ISO IN  callbacks
-  * @param  hpcd: PCD handle
-  * @param  epnum: endpoint number
-  * @retval None
-  */
- __weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ISOINIncompleteCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @brief  Connection event callbacks
-  * @param  hpcd: PCD handle
-  * @retval None
-  */
- __weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_ConnectCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @brief  Disconnection event callbacks
-  * @param  hpcd: ppp handle
-  * @retval None
-  */
- __weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCD_DisconnectCallback could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the PCD data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Connect the USB device 
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd); 
-  
-  /* Enabling DP Pull-Down bit to Connect internal pull-up on USB DP line */
-   HAL_PCDEx_SetConnectionState (hpcd, 1);
-  
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disconnect the USB device 
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
-{
-  __HAL_LOCK(hpcd); 
-  
-  /* Disable DP Pull-Down bit*/
-  HAL_PCDEx_SetConnectionState (hpcd, 0);
-  
-  __HAL_UNLOCK(hpcd); 
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set the USB Device address 
-  * @param  hpcd: PCD handle
-  * @param  address: new device address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
-{
-   __HAL_LOCK(hpcd); 
-
-   if(address == 0) 
-   {
-     /* set device address and enable function */
-     hpcd->Instance->DADDR = USB_DADDR_EF;
-   }
-   else /* USB Address will be applied later */
-   {
-     hpcd->USB_Address = address;
-   }
-
-  __HAL_UNLOCK(hpcd);   
-  return HAL_OK;
-}
-/**
-  * @brief  Open and configure an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  ep_mps: endpoint max packert size
-  * @param  ep_type: endpoint type   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
-{
-  HAL_StatusTypeDef  ret = HAL_OK;
-  PCD_EPTypeDef *ep;
-  
-  if ((ep_addr & 0x80) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  }
-  ep->num   = ep_addr & 0x7F;
-  
-  ep->is_in = (0x80 & ep_addr) != 0;
-  ep->maxpacket = ep_mps;
-  ep->type = ep_type;
-  
-  __HAL_LOCK(hpcd); 
-
-/* initialize Endpoint */
-  switch (ep->type)
-  {
-  case PCD_EP_TYPE_CTRL:
-    PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_CONTROL);
-    break;
-  case PCD_EP_TYPE_BULK:
-    PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_BULK);
-    break;
-  case PCD_EP_TYPE_INTR:
-    PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_INTERRUPT);
-    break;
-  case PCD_EP_TYPE_ISOC:
-    PCD_SET_EPTYPE(hpcd->Instance, ep->num, USB_EP_ISOCHRONOUS);
-    break;
-  default:
-      break;
-  } 
-  
-  PCD_SET_EP_ADDRESS(hpcd->Instance, ep->num, ep->num);
-  
-  if (ep->doublebuffer == 0) 
-  {
-    if (ep->is_in)
-    {
-      /*Set the endpoint Transmit buffer address */
-      PCD_SET_EP_TX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
-      /* Configure NAK status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_NAK); 
-    }
-    else
-    {
-      /*Set the endpoint Receive buffer address */
-      PCD_SET_EP_RX_ADDRESS(hpcd->Instance, ep->num, ep->pmaadress);
-      /*Set the endpoint Receive buffer counter*/
-      PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, ep->maxpacket);
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      /* Configure VALID status for the Endpoint*/
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
-    }
-  }
-  /*Double Buffer*/
-  else
-  {
-    /*Set the endpoint as double buffered*/
-    PCD_SET_EP_DBUF(hpcd->Instance, ep->num);
-    /*Set buffer address for double buffered mode*/
-    PCD_SET_EP_DBUF_ADDR(hpcd->Instance, ep->num,ep->pmaaddr0, ep->pmaaddr1);
-    
-    if (ep->is_in==0)
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
-      
-      /* Reset value of the data toggle bits for the endpoint out*/
-      PCD_TX_DTOG(hpcd->Instance, ep->num);
-      
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
-    }
-    else
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
-      PCD_RX_DTOG(hpcd->Instance, ep->num);
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
-    }
-  } 
-  
-  __HAL_UNLOCK(hpcd);   
-  return ret;
-}
-
-
-/**
-  * @brief  Deactivate an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{  
-  PCD_EPTypeDef *ep;
-  
-  if ((ep_addr & 0x80) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  }
-  ep->num   = ep_addr & 0x7F;
-  
-  ep->is_in = (0x80 & ep_addr) != 0;
-  
-  __HAL_LOCK(hpcd); 
-
-  if (ep->doublebuffer == 0) 
-  {
-    if (ep->is_in)
-    {
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS); 
-    }
-    else
-    {
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
-    }
-  }
-  /*Double Buffer*/
-  else
-  { 
-    if (ep->is_in==0)
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
-      
-      /* Reset value of the data toggle bits for the endpoint out*/
-      PCD_TX_DTOG(hpcd->Instance, ep->num);
-      
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
-    }
-    else
-    {
-      /* Clear the data toggle bits for the endpoint IN/OUT*/
-      PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-      PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
-      PCD_RX_DTOG(hpcd->Instance, ep->num);
-      /* Configure DISABLE status for the Endpoint*/
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_DIS);
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_DIS);
-    }
-  } 
-  
-  __HAL_UNLOCK(hpcd);   
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Receive an amount of data  
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the reception buffer   
-  * @param  len: amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  
- PCD_EPTypeDef *ep;
-  
-  ep = &hpcd->OUT_ep[ep_addr & 0x7F];
-  
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;  
-  ep->xfer_len = len;
-  ep->xfer_count = 0;
-  ep->is_in = 0;
-  ep->num = ep_addr & 0x7F;
-   
-  __HAL_LOCK(hpcd); 
-   
-  /* Multi packet transfer*/
-  if (ep->xfer_len > ep->maxpacket)
-  {
-    len=ep->maxpacket;
-    ep->xfer_len-=len; 
-  }
-  else
-  {
-    len=ep->xfer_len;
-    ep->xfer_len =0;
-  }
-  
-  /* configure and validate Rx endpoint */
-  if (ep->doublebuffer == 0) 
-  {
-    /*Set RX buffer count*/
-    PCD_SET_EP_RX_CNT(hpcd->Instance, ep->num, len);
-  }
-  else
-  {
-    /*Set the Double buffer counter*/
-    PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-  } 
-  
-  PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
-  
-  __HAL_UNLOCK(hpcd); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get Received Data Size
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval Data Size
-  */
-uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  return hpcd->OUT_ep[ep_addr & 0x7F].xfer_count;
-}
-/**
-  * @brief  Send an amount of data  
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @param  pBuf: pointer to the transmission buffer   
-  * @param  len: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
-{
-  PCD_EPTypeDef *ep;
-  uint16_t pmabuffer = 0;
-    
-  ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  
-  /*setup and start the Xfer */
-  ep->xfer_buff = pBuf;  
-  ep->xfer_len = len;
-  ep->xfer_count = 0;
-  ep->is_in = 1;
-  ep->num = ep_addr & 0x7F;
-  
-  __HAL_LOCK(hpcd); 
-  
-  /*Multi packet transfer*/
-  if (ep->xfer_len > ep->maxpacket)
-  {
-    len=ep->maxpacket;
-    ep->xfer_len-=len; 
-  }
-  else
-  {  
-    len=ep->xfer_len;
-    ep->xfer_len =0;
-  }
-  
-  /* configure and validate Tx endpoint */
-  if (ep->doublebuffer == 0) 
-  {
-    PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, len);
-    PCD_SET_EP_TX_CNT(hpcd->Instance, ep->num, len);
-  }
-  else
-  {
-    /*Set the Double buffer counter*/
-    PCD_SET_EP_DBUF1_CNT(hpcd->Instance, ep->num, ep->is_in, len);
-    
-    /*Write the data to the USB endpoint*/
-    if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num)& USB_EP_DTOG_TX)
-    {
-      pmabuffer = ep->pmaaddr1;
-    }
-    else
-    {
-      pmabuffer = ep->pmaaddr0;
-    }
-    PCD_WritePMA(hpcd->Instance, ep->xfer_buff, pmabuffer, len);
-    PCD_FreeUserBuffer(hpcd->Instance, ep->num, ep->is_in);
-  }
-
-  PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
-  
-  __HAL_UNLOCK(hpcd);
-     
-  return HAL_OK;
-}
-
-/**
-  * @brief  Set a STALL condition over an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  PCD_EPTypeDef *ep;
-   
-  __HAL_LOCK(hpcd); 
-   
-  if ((0x80 & ep_addr) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-  
-  ep->is_stall = 1;
-  ep->num   = ep_addr & 0x7F;
-  ep->is_in = ((ep_addr & 0x80) == 0x80);
-  
-  if (ep->num == 0)
-  {
-    /* This macro sets STALL status for RX & TX*/ 
-    PCD_SET_EP_TXRX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_STALL, USB_EP_TX_STALL); 
-  }
-  else
-  {
-    if (ep->is_in)
-    {
-      PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num , USB_EP_TX_STALL); 
-    }
-    else
-    {
-      PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num , USB_EP_RX_STALL);
-    }
-  }
-  __HAL_UNLOCK(hpcd); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Clear a STALL condition over in an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
-  PCD_EPTypeDef *ep;
-  
-  if ((0x80 & ep_addr) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-  
-  ep->is_stall = 0;
-  ep->num   = ep_addr & 0x7F;
-  ep->is_in = ((ep_addr & 0x80) == 0x80);
-  
-  __HAL_LOCK(hpcd); 
-  
-  if (ep->is_in)
-  {
-    PCD_CLEAR_TX_DTOG(hpcd->Instance, ep->num);
-    PCD_SET_EP_TX_STATUS(hpcd->Instance, ep->num, USB_EP_TX_VALID);
-  }
-  else
-  {
-    PCD_CLEAR_RX_DTOG(hpcd->Instance, ep->num);
-    PCD_SET_EP_RX_STATUS(hpcd->Instance, ep->num, USB_EP_RX_VALID);
-  }
-  __HAL_UNLOCK(hpcd); 
-    
-  return HAL_OK;
-}
-
-/**
-  * @brief  Flush an endpoint
-  * @param  hpcd: PCD handle
-  * @param  ep_addr: endpoint address
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{ 
-  return HAL_OK;
-}
-
-/**
-  * @brief  HAL_PCD_ActiveRemoteWakeup : active remote wakeup signalling
-  * @param  hpcd: PCD handle
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  hpcd->Instance->CNTR |= USB_CNTR_RESUME;
-  return HAL_OK;  
-}
-
-/**
-  * @brief  HAL_PCD_DeActiveRemoteWakeup : de-active remote wakeup signalling
-  * @param  hpcd: PCD handle
-  * @retval status
-  */
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd)
-{
-  hpcd->Instance->CNTR &= ~(USB_CNTR_RESUME);
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection permit to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @brief  Return the PCD state
-  * @param  hpcd : PCD handle
-  * @retval HAL state
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
-{
-  return hpcd->State;
-}
-
-
-/**
-  * @brief  Software Device Connection
-  * @param  hpcd: PCD handle
-  * @param  state: Device state
-  * @retval None
-  */
- __weak void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PCDEx_SetConnectionState could be implenetd in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @addtogroup PCD_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  This function handles PCD Endpoint interrupt request.
-  * @param  hpcd: PCD handle
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef PCD_EP_ISR_Handler(PCD_HandleTypeDef *hpcd)
-{
-  PCD_EPTypeDef *ep;
-  uint16_t count=0;
-  uint8_t EPindex;
-  __IO uint16_t wIstr;  
-  __IO uint16_t wEPVal = 0;
-  
-  /* stay in loop while pending interrupts */
-  while (((wIstr = hpcd->Instance->ISTR) & USB_ISTR_CTR) != 0)
-  {
-    /* extract highest priority endpoint number */
-    EPindex = (uint8_t)(wIstr & USB_ISTR_EP_ID);
-    
-    if (EPindex == 0)
-    {
-      /* Decode and service control endpoint interrupt */
-      
-      /* DIR bit = origin of the interrupt */   
-      if ((wIstr & USB_ISTR_DIR) == 0)
-      {
-        /* DIR = 0 */
-        
-        /* DIR = 0      => IN  int */
-        /* DIR = 0 implies that (EP_CTR_TX = 1) always  */
-        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-        ep = &hpcd->IN_ep[0];
-        
-        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
-        ep->xfer_buff += ep->xfer_count;
- 
-        /* TX COMPLETE */
-        HAL_PCD_DataInStageCallback(hpcd, 0);
-        
-        
-        if((hpcd->USB_Address > 0)&& ( ep->xfer_len == 0))
-        {
-          hpcd->Instance->DADDR = (hpcd->USB_Address | USB_DADDR_EF);
-          hpcd->USB_Address = 0;
-        }
-        
-      }
-      else
-      {
-        /* DIR = 1 */
-        
-        /* DIR = 1 & CTR_RX       => SETUP or OUT int */
-        /* DIR = 1 & (CTR_TX | CTR_RX) => 2 int pending */
-        ep = &hpcd->OUT_ep[0];
-        wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, PCD_ENDP0);
-        
-        if ((wEPVal & USB_EP_SETUP) != 0)
-        {
-          /* Get SETUP Packet*/
-          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-          PCD_ReadPMA(hpcd->Instance, (uint8_t*)hpcd->Setup ,ep->pmaadress , ep->xfer_count);       
-          /* SETUP bit kept frozen while CTR_RX = 1*/ 
-          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0); 
-          
-          /* Process SETUP Packet*/
-          HAL_PCD_SetupStageCallback(hpcd);
-        }
-        
-        else if ((wEPVal & USB_EP_CTR_RX) != 0)
-        {
-          PCD_CLEAR_RX_EP_CTR(hpcd->Instance, PCD_ENDP0);
-          /* Get Control Data OUT Packet*/
-          ep->xfer_count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-          
-          if (ep->xfer_count != 0)
-          {
-            PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
-            ep->xfer_buff+=ep->xfer_count;
-          }
-          
-          /* Process Control Data OUT Packet*/
-           HAL_PCD_DataOutStageCallback(hpcd, 0);
-          
-          PCD_SET_EP_RX_CNT(hpcd->Instance, PCD_ENDP0, ep->maxpacket);
-          PCD_SET_EP_RX_STATUS(hpcd->Instance, PCD_ENDP0, USB_EP_RX_VALID);
-        }
-      }
-    }
-    else
-    {
-      
-      /* Decode and service non control endpoints interrupt  */
-      
-      /* process related endpoint register */
-      wEPVal = PCD_GET_ENDPOINT(hpcd->Instance, EPindex);
-      if ((wEPVal & USB_EP_CTR_RX) != 0)
-      {  
-        /* clear int flag */
-        PCD_CLEAR_RX_EP_CTR(hpcd->Instance, EPindex);
-        ep = &hpcd->OUT_ep[EPindex];
-        
-        /* OUT double Buffering*/
-        if (ep->doublebuffer == 0)
-        {
-          count = PCD_GET_EP_RX_CNT(hpcd->Instance, ep->num);
-          if (count != 0)
-          {
-            PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, count);
-          }
-        }
-        else
-        {
-          if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_RX)
-          {
-            /*read from endpoint BUF0Addr buffer*/
-            count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-            if (count != 0)
-            {
-              PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, count);
-            }
-          }
-          else
-          {
-            /*read from endpoint BUF1Addr buffer*/
-            count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-            if (count != 0)
-            {
-              PCD_ReadPMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, count);
-            }
-          }
-          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_OUT);  
-        }
-        /*multi-packet on the NON control OUT endpoint*/
-        ep->xfer_count+=count;
-        ep->xfer_buff+=count;
-       
-        if ((ep->xfer_len == 0) || (count < ep->maxpacket))
-        {
-          /* RX COMPLETE */
-          HAL_PCD_DataOutStageCallback(hpcd, ep->num);
-        }
-        else
-        {
-          HAL_PCD_EP_Receive(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
-        }
-        
-      } /* if((wEPVal & EP_CTR_RX) */
-      
-      if ((wEPVal & USB_EP_CTR_TX) != 0)
-      {
-        ep = &hpcd->IN_ep[EPindex];
-        
-        /* clear int flag */
-        PCD_CLEAR_TX_EP_CTR(hpcd->Instance, EPindex);
-        
-        /* IN double Buffering*/
-        if (ep->doublebuffer == 0)
-        {
-          ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
-          if (ep->xfer_count != 0)
-          {
-            PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaadress, ep->xfer_count);
-          }
-        }
-        else
-        {
-          if (PCD_GET_ENDPOINT(hpcd->Instance, ep->num) & USB_EP_DTOG_TX)
-          {
-            /*read from endpoint BUF0Addr buffer*/
-            ep->xfer_count = PCD_GET_EP_DBUF0_CNT(hpcd->Instance, ep->num);
-            if (ep->xfer_count != 0)
-            {
-              PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr0, ep->xfer_count);
-            }
-          }
-          else
-          {
-            /*read from endpoint BUF1Addr buffer*/
-            ep->xfer_count = PCD_GET_EP_DBUF1_CNT(hpcd->Instance, ep->num);
-            if (ep->xfer_count != 0)
-            {
-              PCD_WritePMA(hpcd->Instance, ep->xfer_buff, ep->pmaaddr1, ep->xfer_count);
-            }
-          }
-          PCD_FreeUserBuffer(hpcd->Instance, ep->num, PCD_EP_DBUF_IN);  
-        }
-        /*multi-packet on the NON control IN endpoint*/
-        ep->xfer_count = PCD_GET_EP_TX_CNT(hpcd->Instance, ep->num);
-        ep->xfer_buff+=ep->xfer_count;
-       
-        /* Zero Length Packet? */
-        if (ep->xfer_len == 0)
-        {
-          /* TX COMPLETE */
-          HAL_PCD_DataInStageCallback(hpcd, ep->num);
-        }
-        else
-        {
-          HAL_PCD_EP_Transmit(hpcd, ep->num, ep->xfer_buff, ep->xfer_len);
-        }
-      } 
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief Copy a buffer from user memory area to packet memory area (PMA)
-  * @param   USBx    = pointer to USB register.
-  * @param   pbUsrBuf: pointer to user memory area.
-  * @param   wPMABufAddr: address into PMA.
-  * @param   wNBytes: no. of bytes to be copied.
-  * @retval None
-  */
-static void PCD_WritePMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
-  uint32_t n = (wNBytes + 1) >> 1;   /* n = (wNBytes + 1) / 2 */
-  uint32_t i, temp1, temp2;
-  uint16_t *pdwVal;
-  pdwVal = (uint16_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
-  for (i = n; i != 0; i--)
-  {
-    temp1 = (uint16_t) * pbUsrBuf;
-    pbUsrBuf++;
-    temp2 = temp1 | (uint16_t) * pbUsrBuf << 8;
-    *pdwVal++ = temp2;
-    pdwVal++;
-    pbUsrBuf++;
-  }
-}
-
-/**
-  * @brief Copy a buffer from user memory area to packet memory area (PMA)
-  * @param   USBx    = pointer to USB register.
-  * @param   pbUsrBuf    = pointer to user memory area.
-  * @param   wPMABufAddr: address into PMA.
-  * @param   wNBytes: no. of bytes to be copied.
-  * @retval None
-  */
-static void PCD_ReadPMA(USB_TypeDef  *USBx, uint8_t *pbUsrBuf, uint16_t wPMABufAddr, uint16_t wNBytes)
-{
-  uint32_t n = (wNBytes + 1) >> 1;/* /2*/
-  uint32_t i;
-  uint32_t *pdwVal;
-  pdwVal = (uint32_t *)(wPMABufAddr * 2 + (uint32_t)USBx + 0x400);
-  for (i = n; i != 0; i--)
-  {
-    *(uint16_t*)pbUsrBuf++ = *pdwVal++;
-    pbUsrBuf++;
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,833 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pcd.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_PCD_H
-#define __STM32L1xx_HAL_PCD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup PCD_Exported_Types PCD Exported Types
-  * @{
-  */
-
-   /** 
-  * @brief  PCD State structures definition  
-  */  
-typedef enum 
-{
-  PCD_READY    = 0x00,
-  PCD_ERROR    = 0x01,
-  PCD_BUSY     = 0x02,
-  PCD_TIMEOUT  = 0x03
-} PCD_StateTypeDef;
-
-typedef enum
-{
-  /* double buffered endpoint direction */
-  PCD_EP_DBUF_OUT,
-  PCD_EP_DBUF_IN,
-  PCD_EP_DBUF_ERR,
-}PCD_EP_DBUF_DIR;
-
-/* endpoint buffer number */
-typedef enum 
-{
-  PCD_EP_NOBUF,
-  PCD_EP_BUF0,
-  PCD_EP_BUF1
-}PCD_EP_BUF_NUM;  
-
-/** 
-  * @brief  PCD Initialization Structure definition  
-  */
-typedef struct
-{
-  uint32_t dev_endpoints;        /*!< Device Endpoints number.
-                                      This parameter depends on the used USB core.   
-                                      This parameter must be a number between Min_Data = 1 and Max_Data = 15 */    
-
-  uint32_t speed;                /*!< USB Core speed.
-                                      This parameter can be any value of @ref USB_Core_Speed                 */        
-                             
-  uint32_t ep0_mps;              /*!< Set the Endpoint 0 Max Packet size. 
-                                      This parameter can be any value of @ref USB_EP0_MPS                    */              
-                       
-  uint32_t phy_itface;           /*!< Select the used PHY interface.
-                                      This parameter can be any value of @ref USB_Core_PHY                   */ 
-                                
-  uint32_t Sof_enable;           /*!< Enable or disable the output of the SOF signal.                        */  
-  
-  uint32_t low_power_enable;       /*!< Enable or disable Low Power mode                                      */ 
-  
-  uint32_t lpm_enable;             /*!< Enable or disable Battery charging.                                  */    
-
-  uint32_t battery_charging_enable; /*!< Enable or disable Battery charging.                                  */    
-                                
-}PCD_InitTypeDef;
-
-typedef struct
-{
-  uint8_t   num;            /*!< Endpoint number
-                                This parameter must be a number between Min_Data = 1 and Max_Data = 15    */ 
-                                
-  uint8_t   is_in;          /*!< Endpoint direction
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
-  
-  uint8_t   is_stall;       /*!< Endpoint stall condition
-                                This parameter must be a number between Min_Data = 0 and Max_Data = 1     */ 
-  
-  uint8_t   type;           /*!< Endpoint type
-                                 This parameter can be any value of @ref USB_EP_Type                      */ 
-                                
-  uint16_t  pmaadress;      /*!< PMA Address
-                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */ 
-  
-  
-  uint16_t  pmaaddr0;       /*!< PMA Address0
-                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */   
-  
-  
-  uint16_t  pmaaddr1;        /*!< PMA Address1
-                                 This parameter can be any value between Min_addr = 0 and Max_addr = 1K   */   
-  
-  
-  uint8_t   doublebuffer;    /*!< Double buffer enable
-                                 This parameter can be 0 or 1                                             */    
-                                
-  uint32_t  maxpacket;      /*!< Endpoint Max packet size
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 64KB */
-
-  uint8_t   *xfer_buff;     /*!< Pointer to transfer buffer                                               */
-                                
-  
-  uint32_t  xfer_len;       /*!< Current transfer length                                                  */
-  
-  uint32_t  xfer_count;     /*!< Partial transfer length in case of multi packet transfer                 */
-
-}PCD_EPTypeDef;
-
-typedef   USB_TypeDef PCD_TypeDef; 
-
-/** 
-  * @brief  PCD Handle Structure definition  
-  */ 
-typedef struct
-{
-  PCD_TypeDef             *Instance;   /*!< Register base address              */ 
-  PCD_InitTypeDef         Init;       /*!< PCD required parameters            */
-  __IO uint8_t            USB_Address; /*!< USB Address            */  
-  PCD_EPTypeDef           IN_ep[8];  /*!< IN endpoint parameters             */
-  PCD_EPTypeDef           OUT_ep[8]; /*!< OUT endpoint parameters            */ 
-  HAL_LockTypeDef         Lock;       /*!< PCD peripheral status              */
-  __IO PCD_StateTypeDef   State;      /*!< PCD communication state            */
-  uint32_t                Setup[12];  /*!< Setup packet buffer                */
-  void                    *pData;      /*!< Pointer to upper stack Handler     */    
-  
-} PCD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-#include "stm32l1xx_hal_pcd_ex.h"    
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup PCD_Exported_Constants PCD Exported Constants
-  * @{
-  */
-
-/** @defgroup USB_Exti_Line_Wakeup USB_Exti_Line_Wakeup
-  * @{
-  */
-
-#define  USB_EXTI_LINE_WAKEUP              ((uint32_t)0x00040000)  /*!< External interrupt line 18 Connected to the USB FS EXTI Line */
-/**
-  * @}
-  */
-
-
-/** @defgroup USB_Core_Speed USB Core Speed
-  * @{
-  */
-#define PCD_SPEED_HIGH               0 /* Not Supported */
-#define PCD_SPEED_FULL               2
-/**
-  * @}
-  */
-  
-  /** @defgroup USB_Core_PHY USB Core PHY
-  * @{
-  */
-#define PCD_PHY_EMBEDDED             2
-/**
-  * @}
-  */
-
-/** @defgroup USB_EP0_MPS USB EP0 MPS
-  * @{
-  */
-#define DEP0CTL_MPS_64                         0
-#define DEP0CTL_MPS_32                         1
-#define DEP0CTL_MPS_16                         2
-#define DEP0CTL_MPS_8                          3
-
-#define PCD_EP0MPS_64                          DEP0CTL_MPS_64
-#define PCD_EP0MPS_32                          DEP0CTL_MPS_32
-#define PCD_EP0MPS_16                          DEP0CTL_MPS_16
-#define PCD_EP0MPS_08                          DEP0CTL_MPS_8 
-/**
-  * @}
-  */ 
-
-/** @defgroup USB_EP_Type USB EP Type
-  * @{
-  */
-#define PCD_EP_TYPE_CTRL                                 0
-#define PCD_EP_TYPE_ISOC                                 1
-#define PCD_EP_TYPE_BULK                                 2
-#define PCD_EP_TYPE_INTR                                 3
-/**
-  * @}
-  */ 
-
-/** @defgroup USB_ENDP_Type USB_ENDP_Type
-  * @{
-  */
-
-#define PCD_ENDP0                             ((uint8_t)0)
-#define PCD_ENDP1                             ((uint8_t)1)
-#define PCD_ENDP2                             ((uint8_t)2)
-#define PCD_ENDP3                             ((uint8_t)3)
-#define PCD_ENDP4                             ((uint8_t)4)
-#define PCD_ENDP5                             ((uint8_t)5)
-#define PCD_ENDP6                             ((uint8_t)6)
-#define PCD_ENDP7                             ((uint8_t)7)
-
-/*  Endpoint Kind */
-#define PCD_SNG_BUF                                      0
-#define PCD_DBL_BUF                                      1
-
-#define IS_PCD_ALL_INSTANCE                              IS_USB_ALL_INSTANCE                          
-
-/**
-  * @}
-  */ 
-
-
-/**
-  * @}
-  */ 
-  
-/* Exported macros -----------------------------------------------------------*/
-
-/** @defgroup PCD_Exported_Macros PCD Exported Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-#define __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)      ((((__HANDLE__)->Instance->ISTR) & (__INTERRUPT__)) == (__INTERRUPT__))
-#define __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__)    (((__HANDLE__)->Instance->ISTR) &= ~(__INTERRUPT__))
-
-#define __HAL_USB_EXTI_ENABLE_IT()    EXTI->IMR |= USB_EXTI_LINE_WAKEUP
-#define __HAL_USB_EXTI_DISABLE_IT()   EXTI->IMR &= ~(USB_EXTI_LINE_WAKEUP)
-#define __HAL_USB_EXTI_GET_FLAG()     EXTI->PR & (USB_EXTI_LINE_WAKEUP)
-#define __HAL_USB_EXTI_CLEAR_FLAG()   EXTI->PR = USB_EXTI_LINE_WAKEUP
-
-#define __HAL_USB_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->FTSR &= ~(USB_EXTI_LINE_WAKEUP);\
-                                                    EXTI->RTSR |= USB_EXTI_LINE_WAKEUP
-
-                                                      
-#define __HAL_USB_EXTI_SET_FALLING_EDGE_TRIGGER()  EXTI->FTSR |= (USB_EXTI_LINE_WAKEUP);\
-                                                      EXTI->RTSR &= ~(USB_EXTI_LINE_WAKEUP)
-
-
-#define __HAL_USB_EXTI_SET_FALLINGRISING_TRIGGER()  EXTI->RTSR &= ~(USB_EXTI_LINE_WAKEUP);\
-                                                       EXTI->FTSR &= ~(USB_EXTI_LINE_WAKEUP);\
-                                                       EXTI->RTSR |= USB_EXTI_LINE_WAKEUP;\
-                                                       EXTI->FTSR |= USB_EXTI_LINE_WAKEUP                                                  
-
-/**
-  * @}
-  */
-
-/* Internal macros -----------------------------------------------------------*/
-
-/** @defgroup PCD_Private_Macros PCD Private Macros
- *  @brief macros to handle interrupts and specific clock configurations
- * @{
- */
-
-/* SetENDPOINT */
-#define PCD_SET_ENDPOINT(USBx, bEpNum,wRegValue)  (*(&(USBx)->EP0R + (bEpNum) * 2)= (uint16_t)(wRegValue))
-
-/* GetENDPOINT */
-#define PCD_GET_ENDPOINT(USBx, bEpNum)        (*(&(USBx)->EP0R + (bEpNum) * 2))
-
-
-
-/**
-  * @brief  sets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wType: Endpoint Type.
-  * @retval None
-  */
-#define PCD_SET_EPTYPE(USBx, bEpNum,wType) (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                  ((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_MASK) | (wType) )))
-
-/**
-  * @brief  gets the type in the endpoint register(bits EP_TYPE[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval Endpoint Type
-  */
-#define PCD_GET_EPTYPE(USBx, bEpNum) (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_T_FIELD)
-
-
-/**
-  * @brief free buffer used from the application realizing it to the line
-          toggles bit SW_BUF in the double buffered endpoint register
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bDir: Direction
-  * @retval None
-  */
-#define PCD_FreeUserBuffer(USBx, bEpNum, bDir)\
-{\
-  if ((bDir) == PCD_EP_DBUF_OUT)\
-  { /* OUT double buffered endpoint */\
-    PCD_TX_DTOG((USBx), (bEpNum));\
-  }\
-  else if ((bDir) == PCD_EP_DBUF_IN)\
-  { /* IN double buffered endpoint */\
-    PCD_RX_DTOG((USBx), (bEpNum));\
-  }\
-}
-
-/**
-  * @brief gets direction of the double buffered endpoint
-  * @param   USBx: USB peripheral instance register address.
-  * @param   bEpNum: Endpoint Number.
-  * @retval EP_DBUF_OUT, EP_DBUF_IN,
-  *         EP_DBUF_ERR if the endpoint counter not yet programmed.
-  */
-#define PCD_GET_DB_DIR(USBx, bEpNum)\
-{\
-  if ((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum)) & 0xFC00) != 0)\
-    return(PCD_EP_DBUF_OUT);\
-  else if (((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x03FF) != 0)\
-    return(PCD_EP_DBUF_IN);\
-  else\
-    return(PCD_EP_DBUF_ERR);\
-}
-
-/**
-  * @brief  sets the status for tx transfer (bits STAT_TX[1:0]).
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wState: new state
-  * @retval None
-  */
-#define PCD_SET_EP_TX_STATUS(USBx, bEpNum, wState) { register uint16_t _wRegVal;\
-   \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_DTOGMASK;\
-   /* toggle first bit ? */     \
-   if((USB_EPTX_DTOG1 & (wState))!= 0)      \
-   {                                                                            \
-     _wRegVal ^= USB_EPTX_DTOG1;        \
-   }                                                                            \
-   /* toggle second bit ?  */         \
-   if((USB_EPTX_DTOG2 & (wState))!= 0)      \
-   {                                                                            \
-     _wRegVal ^= USB_EPTX_DTOG2;        \
-   }                                                                            \
-   PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX));    \
-  } /* PCD_SET_EP_TX_STATUS */
-
-/**
-  * @brief  sets the status for rx transfer (bits STAT_TX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wState: new state
-  * @retval None
-  */
-#define PCD_SET_EP_RX_STATUS(USBx, bEpNum,wState) {\
-    register uint16_t _wRegVal;   \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_DTOGMASK;\
-    /* toggle first bit ? */  \
-    if((USB_EPRX_DTOG1 & (wState))!= 0) \
-    {                                                                             \
-      _wRegVal ^= USB_EPRX_DTOG1;  \
-    }                                                                             \
-    /* toggle second bit ? */  \
-    if((USB_EPRX_DTOG2 & (wState))!= 0) \
-    {                                                                             \
-      _wRegVal ^= USB_EPRX_DTOG2;  \
-    }                                                                             \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), (_wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX)); \
-  } /* PCD_SET_EP_RX_STATUS */
-
-/**
-  * @brief  sets the status for rx & tx (bits STAT_TX[1:0] & STAT_RX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wStaterx: new state.
-  * @param  wStatetx: new state.
-  * @retval None
-  */
-#define PCD_SET_EP_TXRX_STATUS(USBx,bEpNum,wStaterx,wStatetx) {\
-    register uint32_t _wRegVal;   \
-    \
-    _wRegVal = PCD_GET_ENDPOINT((USBx), (bEpNum)) & (USB_EPRX_DTOGMASK |USB_EPTX_STAT) ;\
-    /* toggle first bit ? */  \
-    if((USB_EPRX_DTOG1 & ((wStaterx)))!= 0) \
-    {                                                                                    \
-      _wRegVal ^= USB_EPRX_DTOG1;  \
-    }                                                                                    \
-    /* toggle second bit ? */  \
-    if((USB_EPRX_DTOG2 & (wStaterx))!= 0) \
-    {                                                                                    \
-      _wRegVal ^= USB_EPRX_DTOG2;  \
-    }                                                                                    \
-    /* toggle first bit ? */     \
-    if((USB_EPTX_DTOG1 & (wStatetx))!= 0)      \
-    {                                                                                    \
-      _wRegVal ^= USB_EPTX_DTOG1;        \
-    }                                                                                    \
-    /* toggle second bit ?  */         \
-    if((USB_EPTX_DTOG2 & (wStatetx))!= 0)      \
-    {                                                                                    \
-      _wRegVal ^= USB_EPTX_DTOG2;        \
-    }                                                                                    \
-    PCD_SET_ENDPOINT((USBx), (bEpNum), _wRegVal | USB_EP_CTR_RX|USB_EP_CTR_TX);    \
-  } /* PCD_SET_EP_TXRX_STATUS */
-
-/**
-  * @brief  gets the status for tx/rx transfer (bits STAT_TX[1:0]
-  *         /STAT_RX[1:0])
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval status
-  */
-#define PCD_GET_EP_TX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPTX_STAT)
-
-#define PCD_GET_EP_RX_STATUS(USBx, bEpNum) ((uint16_t)PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPRX_STAT)
-
-/**
-  * @brief  sets directly the VALID tx/rx-status into the endpoint register
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_TX_VALID(USBx, bEpNum)     (PCD_SET_EP_TX_STATUS((USBx), (bEpNum), USB_EP_TX_VALID))
-
-#define PCD_SET_EP_RX_VALID(USBx, bEpNum)     (PCD_SET_EP_RX_STATUS((USBx), (bEpNum), USB_EP_RX_VALID))
-
-/**
-  * @brief  checks stall condition in an endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval TRUE = endpoint in stall condition.
-  */
-#define PCD_GET_EP_TX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_TX_STATUS((USBx), (bEpNum)) \
-                                   == USB_EP_TX_STALL)
-#define PCD_GET_EP_RX_STALL_STATUS(USBx, bEpNum) (PCD_GET_EP_RX_STATUS((USBx), (bEpNum)) \
-                                   == USB_EP_RX_STALL)
-
-/**
-  * @brief  set & clear EP_KIND bit.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_KIND(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                (USB_EP_CTR_RX|USB_EP_CTR_TX|((PCD_GET_ENDPOINT((USBx), (bEpNum)) | USB_EP_KIND) & USB_EPREG_MASK))))
-#define PCD_CLEAR_EP_KIND(USBx, bEpNum)  (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                (USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPKIND_MASK))))
-
-/**
-  * @brief  Sets/clears directly STATUS_OUT bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_OUT_STATUS(USBx, bEpNum)    PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_OUT_STATUS(USBx, bEpNum)  PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
-  * @brief  Sets/clears directly EP_KIND bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF(USBx, bEpNum)   PCD_SET_EP_KIND((USBx), (bEpNum))
-#define PCD_CLEAR_EP_DBUF(USBx, bEpNum) PCD_CLEAR_EP_KIND((USBx), (bEpNum))
-
-/**
-  * @brief  Clears bit CTR_RX / CTR_TX in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_CLEAR_RX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0x7FFF & USB_EPREG_MASK))
-#define PCD_CLEAR_TX_EP_CTR(USBx, bEpNum)   (PCD_SET_ENDPOINT((USBx), (bEpNum),\
-                                   PCD_GET_ENDPOINT((USBx), (bEpNum)) & 0xFF7F & USB_EPREG_MASK))
-
-/**
-  * @brief  Toggles DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_RX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_RX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
-#define PCD_TX_DTOG(USBx, bEpNum)    (PCD_SET_ENDPOINT((USBx), (bEpNum), \
-                                   USB_EP_CTR_RX|USB_EP_CTR_TX|USB_EP_DTOG_TX | (PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK)))
-
-/**
-  * @brief  Clears DTOG_RX / DTOG_TX bit in the endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_CLEAR_RX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_RX) != 0)\
-                                         {                                                              \
-                                           PCD_RX_DTOG((USBx), (bEpNum));                               \
-                                         }
-#define PCD_CLEAR_TX_DTOG(USBx, bEpNum)  if((PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EP_DTOG_TX) != 0)\
-                                         {                                                              \
-                                            PCD_TX_DTOG((USBx), (bEpNum));                              \
-                                         }
-      
-/**
-  * @brief  Sets address in an endpoint register.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bAddr: Address.
-  * @retval None
-  */
-#define PCD_SET_EP_ADDRESS(USBx, bEpNum,bAddr) PCD_SET_ENDPOINT((USBx), (bEpNum),\
-    USB_EP_CTR_RX|USB_EP_CTR_TX|(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPREG_MASK) | (bAddr))
-
-#define PCD_GET_EP_ADDRESS(USBx, bEpNum) ((uint8_t)(PCD_GET_ENDPOINT((USBx), (bEpNum)) & USB_EPADDR_FIELD))
-
-#define PCD_EP_TX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8)*2+     ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_TX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+2)*2+  ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_RX_ADDRESS(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+4)*2+  ((uint32_t)(USBx) + 0x400)))
-#define PCD_EP_RX_CNT(USBx, bEpNum) ((uint32_t *)(((USBx)->BTABLE+(bEpNum)*8+6)*2+  ((uint32_t)(USBx) + 0x400)))
-      
-#define PCD_SET_EP_RX_CNT(USBx, bEpNum,wCount) {\
-    uint32_t *pdwReg = PCD_EP_RX_CNT((USBx), (bEpNum)); \
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
-  }
-
-/**
-  * @brief  sets address of the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wAddr: address to be set (must be word aligned).
-  * @retval None
-  */
-#define PCD_SET_EP_TX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_TX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
-#define PCD_SET_EP_RX_ADDRESS(USBx, bEpNum,wAddr) (*PCD_EP_RX_ADDRESS((USBx), (bEpNum)) = (((wAddr) >> 1) << 1))
-
-/**
-  * @brief  Gets address of the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval address of the buffer.
-  */
-#define PCD_GET_EP_TX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_RX_ADDRESS(USBx, bEpNum) ((uint16_t)*PCD_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
-  * @brief  Sets counter of rx buffer with no. of blocks.
-  * @param  dwReg: Register
-  * @param  wCount: Counter.
-  * @param  wNBlocks: no. of Blocks.
-  * @retval None
-  */
-#define PCD_CALC_BLK32(dwReg,wCount,wNBlocks) {\
-    (wNBlocks) = (wCount) >> 5;\
-    if(((wCount) & 0x1f) == 0)\
-    {                                                  \
-      (wNBlocks)--;\
-    }                                                  \
-    *pdwReg = (uint16_t)((uint16_t)((wNBlocks) << 10) | 0x8000); \
-  }/* PCD_CALC_BLK32 */
-
-#define PCD_CALC_BLK2(dwReg,wCount,wNBlocks) {\
-    (wNBlocks) = (wCount) >> 1;\
-    if(((wCount) & 0x1) != 0)\
-    {                                                  \
-      (wNBlocks)++;\
-    }                                                  \
-    *pdwReg = (uint16_t)((wNBlocks) << 10);\
-  }/* PCD_CALC_BLK2 */
-
-#define PCD_SET_EP_CNT_RX_REG(dwReg,wCount)  {\
-    uint16_t wNBlocks;\
-    if((wCount) > 62)                                \
-    {                                                \
-      PCD_CALC_BLK32((dwReg),(wCount),wNBlocks);     \
-    }                                                \
-    else                                             \
-    {                                                \
-      PCD_CALC_BLK2((dwReg),(wCount),wNBlocks);      \
-    }                                                \
-  }/* PCD_SET_EP_CNT_RX_REG */
-
-#define PCD_SET_EP_RX_DBUF0_CNT(USBx, bEpNum,wCount) {\
-    uint16_t *pdwReg = PCD_EP_TX_CNT((USBx), (bEpNum)); \
-    PCD_SET_EP_CNT_RX_REG(pdwReg, (wCount));\
-  }
-/**
-  * @brief  sets counter for the tx/rx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wCount: Counter value.
-  * @retval None
-  */
-#define PCD_SET_EP_TX_CNT(USBx, bEpNum,wCount) (*PCD_EP_TX_CNT((USBx), (bEpNum)) = (wCount))
-
-
-/**
-  * @brief  gets counter of the tx buffer.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval Counter value
-  */
-#define PCD_GET_EP_TX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_TX_CNT((USBx), (bEpNum))) & 0x3ff)
-#define PCD_GET_EP_RX_CNT(USBx, bEpNum)((uint16_t)(*PCD_EP_RX_CNT((USBx), (bEpNum))) & 0x3ff)
-
-/**
-  * @brief  Sets buffer 0/1 address in a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wBuf0Addr: buffer 0 address.
-  * @retval Counter value
-  */
-#define PCD_SET_EP_DBUF0_ADDR(USBx, bEpNum,wBuf0Addr) {PCD_SET_EP_TX_ADDRESS((USBx), (bEpNum), (wBuf0Addr));}
-#define PCD_SET_EP_DBUF1_ADDR(USBx, bEpNum,wBuf1Addr) {PCD_SET_EP_RX_ADDRESS((USBx), (bEpNum), (wBuf1Addr));}
-
-/**
-  * @brief  Sets addresses in a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  wBuf0Addr: buffer 0 address.
-  * @param  wBuf1Addr = buffer 1 address.
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF_ADDR(USBx, bEpNum,wBuf0Addr,wBuf1Addr) { \
-    PCD_SET_EP_DBUF0_ADDR((USBx), (bEpNum), (wBuf0Addr));\
-    PCD_SET_EP_DBUF1_ADDR((USBx), (bEpNum), (wBuf1Addr));\
-  } /* PCD_SET_EP_DBUF_ADDR */
-
-/**
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_DBUF0_ADDR(USBx, bEpNum) (PCD_GET_EP_TX_ADDRESS((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_ADDR(USBx, bEpNum) (PCD_GET_EP_RX_ADDRESS((USBx), (bEpNum)))
-
-/**
-  * @brief  Gets buffer 0/1 address of a double buffer endpoint.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @param  bDir: endpoint dir  EP_DBUF_OUT = OUT 
-  *         EP_DBUF_IN  = IN 
-  * @param  wCount: Counter value 
-  * @retval None
-  */
-#define PCD_SET_EP_DBUF0_CNT(USBx, bEpNum, bDir, wCount)  { \
-    if((bDir) == PCD_EP_DBUF_OUT)\
-      /* OUT endpoint */ \
-    {PCD_SET_EP_RX_DBUF0_CNT((USBx), (bEpNum),(wCount));} \
-    else if((bDir) == PCD_EP_DBUF_IN)\
-      /* IN endpoint */ \
-      *PCD_EP_TX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount);  \
-  } /* SetEPDblBuf0Count*/
-
-#define PCD_SET_EP_DBUF1_CNT(USBx, bEpNum, bDir, wCount)  { \
-    if((bDir) == PCD_EP_DBUF_OUT)\
-    {/* OUT endpoint */                                       \
-      PCD_SET_EP_RX_CNT((USBx), (bEpNum),(wCount));           \
-    }                                                         \
-    else if((bDir) == PCD_EP_DBUF_IN)\
-    {/* IN endpoint */                                        \
-      *PCD_EP_RX_CNT((USBx), (bEpNum)) = (uint32_t)(wCount); \
-    }                                                         \
-  } /* SetEPDblBuf1Count */
-
-#define PCD_SET_EP_DBUF_CNT(USBx, bEpNum, bDir, wCount) {\
-    PCD_SET_EP_DBUF0_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-    PCD_SET_EP_DBUF1_CNT((USBx), (bEpNum), (bDir), (wCount)); \
-  } /* PCD_SET_EP_DBUF_CNT  */
-
-/**
-  * @brief  Gets buffer 0/1 rx/tx counter for double buffering.
-  * @param  USBx: USB peripheral instance register address.
-  * @param  bEpNum: Endpoint Number.
-  * @retval None
-  */
-#define PCD_GET_EP_DBUF0_CNT(USBx, bEpNum) (PCD_GET_EP_TX_CNT((USBx), (bEpNum)))
-#define PCD_GET_EP_DBUF1_CNT(USBx, bEpNum) (PCD_GET_EP_RX_CNT((USBx), (bEpNum)))
-
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PCD_Exported_Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-
-
-/** @addtogroup PCD_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeInit (PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd);
-
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/* Non-Blocking mode: Interrupt */
-/** @addtogroup PCD_Exported_Functions_Group2
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd);
-
-void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum);
-void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd);
-void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd);
-
-/**
-  * @}
-  */
-
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup PCD_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address);
-HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type);
-HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len);
-uint16_t          HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr);
-HAL_StatusTypeDef HAL_PCD_ActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-HAL_StatusTypeDef HAL_PCD_DeActiveRemoteWakeup(PCD_HandleTypeDef *hpcd);
-/**
-  * @}
-  */
-
-
-/* Peripheral State functions  **************************************************/
-/** @addtogroup PCD_Exported_Functions_Group4
-  * @{
-  */
-PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd);
-void HAL_PCDEx_SetConnectionState(PCD_HandleTypeDef *hpcd, uint8_t state);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_PCD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,147 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pcd_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Extended PCD HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the USB Peripheral Controller:
-  *           + Configururation of the PMA for EP
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PCDEx PCDEx
-  * @brief PCDEx HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PCD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-
-/** @defgroup PCDEx_Exported_Functions PCDEx Exported Functions
-  * @{
-  */
-
-/*
-@verbatim    
- ===============================================================================
-                 ##### Peripheral extended features functions #####
- ===============================================================================
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief Configure PMA for EP
-  * @param  hpcd : Device instance
-  * @param  ep_addr: endpoint address
-  * @param  ep_kind: endpoint Kind
-  *                  USB_SNG_BUF: Single Buffer used
-  *                  USB_DBL_BUF: Double Buffer used
-  * @param  pmaadress: EP address in The PMA: In case of single buffer endpoint
-  *                   this parameter is 16-bit value providing the address
-  *                   in PMA allocated to endpoint.
-  *                   In case of double buffer endpoint this parameter
-  *                   is a 32-bit value providing the endpoint buffer 0 address
-  *                   in the LSB part of 32-bit value and endpoint buffer 1 address
-  *                   in the MSB part of 32-bit value.
-  * @retval : status
-  */
-
-HAL_StatusTypeDef  HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, 
-                        uint16_t ep_addr,
-                        uint16_t ep_kind,
-                        uint32_t pmaadress)
-
-{
-  PCD_EPTypeDef *ep;
-  
-  /* initialize ep structure*/
-  if ((0x80 & ep_addr) == 0x80)
-  {
-    ep = &hpcd->IN_ep[ep_addr & 0x7F];
-  }
-  else
-  {
-    ep = &hpcd->OUT_ep[ep_addr];
-  }
-  
-  /* Here we check if the endpoint is single or double Buffer*/
-  if (ep_kind == PCD_SNG_BUF)
-  {
-    /*Single Buffer*/
-    ep->doublebuffer = 0;
-    /*Configure te PMA*/
-    ep->pmaadress = (uint16_t)pmaadress;
-  }
-  else /*USB_DBL_BUF*/
-  {
-    /*Double Buffer Endpoint*/
-    ep->doublebuffer = 1;
-    /*Configure the PMA*/
-    ep->pmaaddr0 =  pmaadress & 0xFFFF;
-    ep->pmaaddr1 =  (pmaadress & 0xFFFF0000) >> 16;
-  }
-  
-  return HAL_OK; 
-}
-
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PCD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pcd_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,89 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pcd.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of PCD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_PCD_EX_H
-#define __STM32L1xx_HAL_PCD_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"  
-   
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PCDEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-/* Exported macros -----------------------------------------------------------*/
-/* Internal macros -----------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup PCDEx_Exported_Functions
-  * @{
-  */
-HAL_StatusTypeDef HAL_PCDEx_PMAConfig(PCD_HandleTypeDef *hpcd, 
-                                     uint16_t ep_addr,
-                                     uint16_t ep_kind,
-                                     uint32_t pmaadress);
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_PCD_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,612 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pwr.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   PWR HAL module driver.
-  *
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions 
-  *
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWR PWR
-  * @brief    PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-#define PVD_MODE_IT               ((uint32_t)0x00010000)
-#define PVD_MODE_EVT              ((uint32_t)0x00020000)
-#define PVD_RISING_EDGE           ((uint32_t)0x00000001)
-#define PVD_FALLING_EDGE          ((uint32_t)0x00000002)
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-
-/** @defgroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief   Initialization and de-initialization functions
-  *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]
-      After reset, the backup domain (RTC registers, RTC backup data
-      registers) is protected against possible unwanted
-      write accesses.
-      To enable access to the RTC Domain and RTC registers, proceed as follows:
-        (+) Enable the Power Controller (PWR) APB1 interface clock using the
-            __PWR_CLK_ENABLE() macro.
-        (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deinitializes the PWR peripheral registers to their default reset values.
-  * @note   Before calling this function, the VOS[1:0] bits should be configured 
-  *         to "10" and the system frequency has to be configured accordingly. 
-  *         To configure the VOS[1:0] bits, use the PWR_VoltageScalingConfig()
-  *         function.      
-  * @note   ULP and FWU bits are not reset by this function.    
-  * @retval None
-  */
-void HAL_PWR_DeInit(void)
-{
-  __PWR_FORCE_RESET();
-  __PWR_RELEASE_RESET();
-}
-
-/**
-  * @brief  Enables access to the backup domain (RTC registers, RTC
-  *         backup data registers ).
-  * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_EnableBkUpAccess(void)
-{
-  /* Enable access to RTC and backup registers */
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables access to the backup domain (RTC registers, RTC
-  *         backup data registers).
-  * @note   If the HSE divided by 2, 4, 8 or 16 is used as the RTC clock, the
-  *         Backup Domain Access should be kept enabled.
-  * @retval None
-  */
-void HAL_PWR_DisableBkUpAccess(void)
-{
-  /* Disable access to RTC and backup registers */
-  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Exported_Functions_Group2 Peripheral Control functions 
-  * @brief    Low Power modes configuration functions
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral Control functions #####
- ===============================================================================
-     
-    *** PVD configuration ***
-    =========================
-    [..]
-      (+) The PVD is used to monitor the VDD power supply by comparing it to a
-          threshold selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
-      (+) The PVD can use an external input analog voltage (PVD_IN) which is compared 
-      internally to VREFINT. The PVD_IN (PB7) has to be configured in Analog mode 
-      when PWR_PVDLevel_7 is selected (PLS[2:0] = 111).
-
-      (+) A PVDO flag is available to indicate if VDD/VDDA is higher or lower
-          than the PVD threshold. This event is internally connected to the EXTI
-          line16 and can generate an interrupt if enabled. This is done through
-          __HAL_PVD_EXTI_ENABLE_IT() macro.
-      (+) The PVD is stopped in Standby mode.
-
-    *** WakeUp pin configuration ***
-    ================================
-    [..]
-      (+) WakeUp pin is used to wake up the system from Standby mode. This pin is
-          forced in input pull-down configuration and is active on rising edges.
-      (+) There are two or three WakeUp pins:
-          WakeUp Pin 1 on PA.00.
-          WakeUp Pin 2 on PC.13.
-          WakeUp Pin 3 on PE.06. : Only on product with GPIOE available 
-
-    [..]
-    *** Main and Backup Regulators configuration ***
-    ================================================
-
-      (+) The main internal regulator can be configured to have a tradeoff between
-          performance and power consumption when the device does not operate at
-          the maximum frequency. This is done through __HAL_PWR_VOLTAGESCALING_CONFIG()
-          macro which configure VOS bit in PWR_CR register:
-        (++) When this bit is set (Regulator voltage output Scale 1 mode selected)
-             the System frequency can go up to 32 MHz.
-        (++) When this bit is reset (Regulator voltage output Scale 2 mode selected)
-             the System frequency can go up to 16 MHz.
-        (++) When this bit is reset (Regulator voltage output Scale 3 mode selected)
-             the System frequency can go up to 4.2 MHz.
-              
-        Refer to the datasheets for more details.
-
-    *** Low Power modes configuration ***
-    =====================================
-     [..]
-      The device features 5 low-power modes:
-      (+) Low power run mode: regulator in low power mode, limited clock frequency, 
-        limited number of peripherals running.
-      (+) Sleep mode: Cortex-M3 core stopped, peripherals kept running.
-      (+) Low power sleep mode: Cortex-M3 core stopped, limited clock frequency, 
-         limited number of peripherals running, regulator in low power mode.
-      (+) Stop mode: All clocks are stopped, regulator running, regulator in low power mode.
-      (+) Standby mode: VCORE domain powered off
-  
-   *** Low power run mode ***
-   =========================
-    [..]
-       To further reduce the consumption when the system is in Run mode, the regulator can be
-        configured in low power mode. In this mode, the system frequency should not exceed
-        MSI frequency range1.
-        In Low power run mode, all I/O pins keep the same state as in Run mode.
-  
-      (+) Entry:
-        (++) VCORE in range2
-        (++) Decrease the system frequency tonot exceed the frequency of MSI frequency range1.
-        (++) The regulator is forced in low power mode using the HAL_PWREx_EnableLowPowerRunMode()
-             function.
-      (+) Exit:
-        (++) The regulator is forced in Main regulator mode using the HAL_PWREx_DisableLowPowerRunMode()
-              function.
-        (++) Increase the system frequency if needed.
-  
-   *** Sleep mode ***
-   ==================
-    [..]
-      (+) Entry:
-          The Sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFx)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-     
-      (+) Exit:
-        (++) Any peripheral interrupt acknowledged by the nested vectored interrupt
-              controller (NVIC) can wake up the device from Sleep mode.
-
-   *** Low power sleep mode ***
-   ============================
-    [..]
-      (+) Entry:
-          The Low power sleep mode is entered by using the HAL_PWR_EnterSLEEPMode(PWR_LOWPOWERREGULATOR_ON, PWR_SLEEPENTRY_WFx)
-              functions with
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-       (+) The Flash memory can be switched off by using the control bits (SLEEP_PD in the FLASH_ACR register. 
-             This reduces power consumption but increases the wake-up time.
-         
-      (+) Exit:
-        (++) If the WFI instruction was used to enter Low power sleep mode, any peripheral interrupt
-              acknowledged by the nested vectored interrupt controller (NVIC) can wake up the device
-              from Low power sleep mode. If the WFE instruction was used to enter Low power sleep mode,
-              the MCU exits Sleep mode as soon as an event occurs. 
-                
-   *** Stop mode ***
-   =================
-    [..]
-      The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral
-      clock gating. The voltage regulator can be configured either in normal or low-power mode.
-      In Stop mode, all clocks in the VCORE domain are stopped, the PLL, the MSI, the HSI and
-      the HSE RC oscillators are disabled. Internal SRAM and register contents are preserved.
-      To get the lowest consumption in Stop mode, the internal Flash memory also enters low
-      power mode. When the Flash memory is in power-down mode, an additional startup delay is
-      incurred when waking up from Stop mode.
-      To minimize the consumption In Stop mode, VREFINT, the BOR, PVD, and temperature
-      sensor can be switched off before entering Stop mode. They can be switched on again by
-      software after exiting Stop mode using the ULP bit in the PWR_CR register.
-      In Stop mode, all I/O pins keep the same state as in Run mode.
-
-      (+) Entry:
-           The Stop mode is entered using the HAL_PWR_EnterSTOPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI )
-             function with:
-          (++) Main regulator ON.
-          (++) Low Power regulator ON.
-          (++) PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-          (++) PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-      (+) Exit:
-        (++) By issuing an interrupt or a wakeup event, the MSI RC oscillator is selected as system clock.
-
-   *** Standby mode ***
-   ====================
-     [..]
-      The Standby mode allows to achieve the lowest power consumption. It is based on the
-      Cortex-M3 deepsleep mode, with the voltage regulator disabled. The VCORE domain is
-      consequently powered off. The PLL, the MSI, the HSI oscillator and the HSE oscillator are
-      also switched off. SRAM and register contents are lost except for the RTC registers, RTC
-      backup registers and Standby circuitry.
-      
-      To minimize the consumption In Standby mode, VREFINT, the BOR, PVD, and temperature
-       sensor can be switched off before entering the Standby mode. They can be switched 
-       on again by software after exiting the Standby mode.
-       function.
-      
-      (+) Entry:
-        (++) The Standby mode is entered using the HAL_PWR_EnterSTANDBYMode() function.
-      (+) Exit:
-        (++) WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
-             tamper event, time-stamp event, external reset in NRST pin, IWDG reset.
-
-   *** Auto-wakeup (AWU) from low-power mode ***
-   =============================================
-    [..]
-      The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
-      Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
-      without depending on an external interrupt (Auto-wakeup mode).
-
-    (+) RTC auto-wakeup (AWU) from the Stop mode
-        (++) To wake up from the Stop mode with an RTC alarm event, it is necessary to:
-             (+++) Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
-                   or Event modes) and Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT()
-                   function
-             (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() 
-                   and HAL_RTC_SetTime() functions.
-        (++) To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
-             is necessary to:
-             (+++) Configure the EXTI Line 19 to be sensitive to rising edges (Interrupt or Event modes) and
-                   Enable the RTC Tamper or time stamp Interrupt using the HAL_RTCEx_SetTamper_IT() 
-                   or HAL_RTCEx_SetTimeStamp_IT() functions.
-        (++) To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
-             (+++) Configure the EXTI Line 20 to be sensitive to rising edges (Interrupt or Event modes) and
-                   Enable the RTC WakeUp Interrupt using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-             (+++) Configure the RTC to generate the RTC WakeUp event using the HAL_RTCEx_SetWakeUpTimer() 
-                   function.
-
-    (+) RTC auto-wakeup (AWU) from the Standby mode
-        (++) To wake up from the Standby mode with an RTC alarm event, it is necessary to:
-             (+++) Enable the RTC Alarm Interrupt using the HAL_RTC_SetAlarm_IT() function.
-             (+++) Configure the RTC to generate the RTC alarm using the HAL_RTC_Init() 
-                   and HAL_RTC_SetTime() functions.
-        (++) To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
-             is necessary to:
-             (+++) Enable the RTC Tamper or time stamp Interrupt and Configure the RTC to 
-                   detect the tamper or time stamp event using the HAL_RTCEx_SetTimeStamp_IT()
-                   or HAL_RTCEx_SetTamper_IT()functions.
-        (++) To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
-             (+++) Enable the RTC WakeUp Interrupt and Configure the RTC to generate the RTC WakeUp event 
-                   using the HAL_RTCEx_SetWakeUpTimer_IT() and HAL_RTCEx_SetWakeUpTimer() functions.
-
-    (+) Comparator auto-wakeup (AWU) from the Stop mode
-        (++) To wake up from the Stop mode with an comparator 1 or comparator 2 wakeup
-             event, it is necessary to:
-             (+++) Configure the EXTI Line 21 or EXTI Line 22 for comparator to be sensitive to to the 
-                   selected edges (falling, rising or falling and rising) (Interrupt or Event modes) using 
-                   the COMP functions.
-             (+++) Configure the comparator to generate the event.      
-        
-            
-        
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
-  * @param  sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
-  *         information for the PVD.
-  * @note   Refer to the electrical characteristics of your device datasheet for
-  *         more details about the voltage threshold corresponding to each
-  *         detection level.
-  * @retval None
-  */
-void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_PVD_LEVEL(sConfigPVD->PVDLevel));
-  assert_param(IS_PWR_PVD_MODE(sConfigPVD->Mode));
-
-  /* Set PLS[7:5] bits according to PVDLevel value */
-  MODIFY_REG(PWR->CR, PWR_CR_PLS, sConfigPVD->PVDLevel);
-  
-  /* Clear any previous config. Keep it clear if no event or IT mode is selected */
-  __HAL_PWR_PVD_EXTI_DISABLE_EVENT();
-  __HAL_PWR_PVD_EXTI_DISABLE_IT();
-  __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER();
-
-  /* Configure interrupt mode */
-  if((sConfigPVD->Mode & PVD_MODE_IT) == PVD_MODE_IT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_IT();
-  }
-  
-  /* Configure event mode */
-  if((sConfigPVD->Mode & PVD_MODE_EVT) == PVD_MODE_EVT)
-  {
-    __HAL_PWR_PVD_EXTI_ENABLE_EVENT();
-  }
-  
-  /* Configure the edge */
-  if((sConfigPVD->Mode & PVD_RISING_EDGE) == PVD_RISING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER();
-  }
-  
-  if((sConfigPVD->Mode & PVD_FALLING_EDGE) == PVD_FALLING_EDGE)
-  {
-    __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER();
-  }
-}
-
-/**
-  * @brief  Enables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_EnablePVD(void)
-{
-  /* Enable the power voltage detector */
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Power Voltage Detector(PVD).
-  * @retval None
-  */
-void HAL_PWR_DisablePVD(void)
-{
-  /* Disable the power voltage detector */
-  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
-  *        This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2
-  *           @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available 
-  * @retval None
-  */
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-  /* Enable the EWUPx pin */
-  *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief Disables the WakeUp PINx functionality.
-  * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
-  *        This parameter can be one of the following values:
-  *           @arg PWR_WAKEUP_PIN1
-  *           @arg PWR_WAKEUP_PIN2  
-  *           @arg PWR_WAKEUP_PIN3: Only on product with GPIOE available 
-  * @retval None
-  */
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
-{
-  /* Check the parameter */
-  assert_param(IS_PWR_WAKEUP_PIN(WakeUpPinx));
-  /* Disable the EWUPx pin */
-  *(__IO uint32_t *) CSR_EWUP_BB(WakeUpPinx) = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief Enters Sleep mode.
-  * @note  In Sleep mode, all I/O pins keep the same state as in Run mode.
-  * @param Regulator: Specifies the regulator state in SLEEP mode.
-  *         This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
-  * @param SLEEPEntry: Specifies if SLEEP mode is entered with WFI or WFE instruction.
-  *           When WFI entry is used, tick interrupt have to be disabled if not desired as 
-  *           the interrupt wake up source.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
-  *            @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
-  * @retval None
-  */
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_SLEEP_ENTRY(SLEEPEntry));
-
-  /* Select the regulator state in Sleep mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
-
-  /* Clear SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select SLEEP mode entry -------------------------------------------------*/
-  if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-}
-
-/**
-  * @brief Enters Stop mode. 
-  * @note  In Stop mode, all I/O pins keep the same state as in Run mode.
-  * @note  When exiting Stop mode by using an interrupt or a wakeup event,
-  *        MSI RC oscillator is selected as system clock.
-  * @note  When the voltage regulator operates in low power mode, an additional
-  *         startup delay is incurred when waking up from Stop mode. 
-  *         By keeping the internal regulator ON during Stop mode, the consumption
-  *         is higher although the startup time is reduced.    
-  * @param Regulator: Specifies the regulator state in Stop mode.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
-  *            @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
-  * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
-  *            @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction   
-  * @retval None
-  */
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
-{
-  /* Check the parameters */
-  assert_param(IS_PWR_REGULATOR(Regulator));
-  assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
-  /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
-  MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), Regulator);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* Select Stop mode entry --------------------------------------------------*/
-  if(STOPEntry == PWR_STOPENTRY_WFI)
-  {
-    /* Request Wait For Interrupt */
-    __WFI();
-  }
-  else
-  {
-    /* Request Wait For Event */
-    __SEV();
-    __WFE();
-    __WFE();
-  }
-  /* Reset SLEEPDEEP bit of Cortex System Control Register */
-  CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-}
-
-/**
-  * @brief Enters Standby mode.
-  * @note  In Standby mode, all I/O pins are high impedance except for:
-  *          - Reset pad (still available) 
-  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC
-  *            Alarm out, or RTC clock calibration out.
-  *          - WKUP pin 1 (PA0) if enabled.
-  *          - WKUP pin 2 (PC13) if enabled.
-  *          - WKUP pin 3 (PE6) if enabled.
-  * @retval None
-  */
-void HAL_PWR_EnterSTANDBYMode(void)
-{
-  /* Select Standby mode */
-  SET_BIT(PWR->CR, PWR_CR_PDDS);
-
-  /* Set SLEEPDEEP bit of Cortex System Control Register */
-  SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-  /* This option is used to ensure that store operations are completed */
-#if defined ( __CC_ARM)
-  __force_stores();
-#endif
-  /* Request Wait For Interrupt */
-  __WFI();
-}
-
-/**
-  * @brief  This function handles the PWR PVD interrupt request.
-  * @note   This API should be called under the PVD_IRQHandler().
-  * @retval None
-  */
-void HAL_PWR_PVD_IRQHandler(void)
-{
-  /* Check PWR exti flag */
-  if(__HAL_PWR_PVD_EXTI_GET_FLAG() != RESET)
-  {
-    /* PWR PVD interrupt user callback */
-    HAL_PWR_PVDCallback();
-
-    /* Clear PWR Exti pending bit */
-    __HAL_PWR_PVD_EXTI_CLEAR_FLAG();
-  }
-}
-
-/**
-  * @brief  PWR PVD interrupt callback
-  * @retval None
-  */
-__weak void HAL_PWR_PVDCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_PWR_PVDCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,431 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pwr.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of PWR HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_PWR_H
-#define __STM32L1xx_HAL_PWR_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWR
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Types PWR Exported Types
-  * @{
-  */ 
-
-/**
-  * @brief  PWR PVD configuration structure definition
-  */
-typedef struct
-{
-  uint32_t PVDLevel;   /*!< PVDLevel: Specifies the PVD detection level.
-                            This parameter can be a value of @ref PWR_PVD_detection_level */
-
-  uint32_t Mode;      /*!< Mode: Specifies the operating mode for the selected pins.
-                           This parameter can be a value of @ref PWR_PVD_Mode */
-}PWR_PVDTypeDef;
-
-/**
-  * @}
-  */
-  
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWR_Exported_Constants PWR Exported Constants
-  * @{
-  */ 
-
-/** @defgroup PWR_register_alias_address PWR Register alias address
-  * @{
-  */
-/* ------------- PWR registers bit address in the alias region ---------------*/
-#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
-#define PWR_CR_OFFSET            0x00
-#define PWR_CSR_OFFSET           0x04
-#define PWR_CR_OFFSET_BB         (PWR_OFFSET + PWR_CR_OFFSET)
-#define PWR_CSR_OFFSET_BB        (PWR_OFFSET + PWR_CSR_OFFSET)
-/**
-  * @}
-  */
-  
-/** @defgroup PWR_CR_register_alias PWR CR Register alias address
-  * @{
-  */  
-/* --- CR Register ---*/
-/* Alias word address of LPSDSR bit */
-#define LPSDSR_BIT_NUMBER        POSITION_VAL(PWR_CR_LPSDSR)
-#define CR_LPSDSR_BB             ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
-
-/* Alias word address of DBP bit */
-#define DBP_BIT_NUMBER           POSITION_VAL(PWR_CR_DBP)
-#define CR_DBP_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
-
-/* Alias word address of LPRUN bit */
-#define LPRUN_BIT_NUMBER         POSITION_VAL(PWR_CR_LPRUN)
-#define CR_LPRUN_BB              ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4)))
-
-/* Alias word address of PVDE bit */
-#define PVDE_BIT_NUMBER          POSITION_VAL(PWR_CR_PVDE)
-#define CR_PVDE_BB               ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
-
-/* Alias word address of FWU bit */
-#define FWU_BIT_NUMBER           POSITION_VAL(PWR_CR_FWU)
-#define CR_FWU_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4)))
-
-/* Alias word address of ULP bit */
-#define ULP_BIT_NUMBER           POSITION_VAL(PWR_CR_ULP)
-#define CR_ULP_BB                ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4)))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
-  * @{
-  */
-
-/* --- CSR Register ---*/
-/* Alias word address of EWUP1, EWUP2 and EWUP3 bits */
-#define CSR_EWUP_BB(VAL)         ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
-/**
-  * @}
-  */
-  
-/** @defgroup PWR_PVD_detection_level PWR PVD detection level
-  * @{
-  */
-#define PWR_PVDLEVEL_0                  PWR_CR_PLS_LEV0
-#define PWR_PVDLEVEL_1                  PWR_CR_PLS_LEV1
-#define PWR_PVDLEVEL_2                  PWR_CR_PLS_LEV2
-#define PWR_PVDLEVEL_3                  PWR_CR_PLS_LEV3
-#define PWR_PVDLEVEL_4                  PWR_CR_PLS_LEV4
-#define PWR_PVDLEVEL_5                  PWR_CR_PLS_LEV5
-#define PWR_PVDLEVEL_6                  PWR_CR_PLS_LEV6
-#define PWR_PVDLEVEL_7                  PWR_CR_PLS_LEV7  /* External input analog voltage 
-                                                            (Compare internally to VREFINT) */
-#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
-                                 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_PVD_Mode PWR PVD Mode
-  * @{
-  */
-#define PWR_PVD_MODE_NORMAL                 ((uint32_t)0x00000000)   /*!< basic mode is used */
-#define PWR_PVD_MODE_IT_RISING              ((uint32_t)0x00010001)   /*!< External Interrupt Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_IT_FALLING             ((uint32_t)0x00010002)   /*!< External Interrupt Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_IT_RISING_FALLING      ((uint32_t)0x00010003)   /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING           ((uint32_t)0x00020001)   /*!< Event Mode with Rising edge trigger detection */
-#define PWR_PVD_MODE_EVENT_FALLING          ((uint32_t)0x00020002)   /*!< Event Mode with Falling edge trigger detection */
-#define PWR_PVD_MODE_EVENT_RISING_FALLING   ((uint32_t)0x00020003)   /*!< Event Mode with Rising/Falling edge trigger detection */
-
-#define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
-                              ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
-                              ((MODE) == PWR_PVD_MODE_NORMAL))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
-  * @{
-  */
-#define PWR_MAINREGULATOR_ON           ((uint32_t)0x00000000)
-#define PWR_LOWPOWERREGULATOR_ON       PWR_CR_LPSDSR
-
-#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
-                                     ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
-  * @{
-  */
-#define PWR_SLEEPENTRY_WFI             ((uint8_t)0x01)
-#define PWR_SLEEPENTRY_WFE             ((uint8_t)0x02)
-#define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
-  * @{
-  */
-#define PWR_STOPENTRY_WFI              ((uint8_t)0x01)
-#define PWR_STOPENTRY_WFE              ((uint8_t)0x02)
-#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
-  * @{
-  */
-
-#define PWR_REGULATOR_VOLTAGE_SCALE1       PWR_CR_VOS_0
-#define PWR_REGULATOR_VOLTAGE_SCALE2       PWR_CR_VOS_1
-#define PWR_REGULATOR_VOLTAGE_SCALE3       PWR_CR_VOS
-
-#define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
-                                             ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
-/**
-  * @}
-  */
-
-/** @defgroup PWR_Flag PWR Flag
-  * @{
-  */
-#define PWR_FLAG_WU                    PWR_CSR_WUF
-#define PWR_FLAG_SB                    PWR_CSR_SBF
-#define PWR_FLAG_PVDO                  PWR_CSR_PVDO
-#define PWR_FLAG_VREFINTRDY            PWR_CSR_VREFINTRDYF
-#define PWR_FLAG_VOS                   PWR_CSR_VOSF
-#define PWR_FLAG_REGLP                 PWR_CSR_REGLPF
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup PWR_Exported_Macro PWR Exported Macro
-  * @{
-  */
-
-/** @brief  macros configure the main internal regulator output voltage.
-  * @param  __REGULATOR__: specifies the regulator output voltage to achieve
-  *         a tradeoff between performance and power consumption when the device does
-  *         not operate at the maximum frequency (refer to the datasheets for more details).
-  *          This parameter can be one of the following values:
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
-  *                                                System frequency up to 32 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
-  *                                                System frequency up to 16 MHz.
-  *            @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
-  *                                                System frequency up to 4.2 MHz
-  * @retval None
-  */
-#define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
-
-/** @brief  Check PWR flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *           This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
-  *                  was received from the WKUP pin or from the RTC alarm (Alarm B),
-  *                  RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
-  *                  An additional wakeup event is detected if the WKUP pin is enabled
-  *                  (by setting the EWUP bit) when the WKUP pin level is already high.
-  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
-  *                  resumed from StandBy mode.
-  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
-  *                  by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
-  *                  For this reason, this bit is equal to 0 after Standby or reset
-  *                  until the PVDE bit is set.
-  *            @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
-  *                 This bit indicates the state of the internal voltage reference, VREFINT.
-  *            @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
-  *                 the internal regulator to be ready after the voltage range is changed.
-  *                 The VOSF bit indicates that the regulator has reached the voltage level
-  *                 defined with bits VOS of PWR_CR register.
-  *            @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
-  *                 mode, this bit stays at 1 until the regulator is ready in main mode.
-  *                 A polling on this bit is recommended to wait for the regulator main mode.
-  *                 This bit is reset by hardware when the regulator is ready.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the PWR's pending flags.
-  * @param  __FLAG__: specifies the flag to clear.
-  *          This parameter can be one of the following values:
-  *            @arg PWR_FLAG_WU: Wake Up flag
-  *            @arg PWR_FLAG_SB: StandBy flag
-  */
-#define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |=  (__FLAG__) << 2)
-
-#define PWR_EXTI_LINE_PVD  ((uint32_t)0x00010000)  /*!< External interrupt line 16 Connected to the PVD EXTI Line */
-
-/**
-  * @brief Enable interrupt on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_IT()      (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Disable interrupt on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_IT()     (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Enable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_ENABLE_EVENT()   (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Disable event on PVD Exti Line 16.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_DISABLE_EVENT()  (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief  PVD EXTI line configuration: clear falling edge trigger and set rising edge.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER()   EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \
-                                                  EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief  PVD EXTI line configuration: set falling edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER()  EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief  PVD EXTI line configuration: set rising edge trigger.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER()   EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
-
-/**
-  * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
-  * @retval EXTI PVD Line Status.
-  */
-#define __HAL_PWR_PVD_EXTI_GET_FLAG()       (EXTI->PR & (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Clear the PVD EXTI flag.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_CLEAR_FLAG()     (EXTI->PR = (PWR_EXTI_LINE_PVD))
-
-/**
-  * @brief Generate a Software interrupt on selected EXTI line.
-  * @retval None.
-  */
-#define __HAL_PWR_PVD_EXTI_GENERATE_SWIT()  (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
-/**
-  * @}
-  */
-
-/* Include PWR HAL Extension module */
-#include "stm32l1xx_hal_pwr_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup PWR_Exported_Functions PWR Exported Functions
-  * @{
-  */
-  
-/** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization and de-initialization functions *******************************/
-void HAL_PWR_DeInit(void);
-void HAL_PWR_EnableBkUpAccess(void);
-void HAL_PWR_DisableBkUpAccess(void);
-
-/**
-  * @}
-  */
-
-/** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions 
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
-void HAL_PWR_EnablePVD(void);
-void HAL_PWR_DisablePVD(void);
-
-/* WakeUp pins configuration functions ****************************************/
-void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
-void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
-
-/* Low Power modes configuration functions ************************************/
-void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
-void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
-void HAL_PWR_EnterSTANDBYMode(void);
-
-void HAL_PWR_PVD_IRQHandler(void);
-void HAL_PWR_PVDCallback(void);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_PWR_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,168 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pwr_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Extended PWR HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Power Controller (PWR) peripheral:
-  *           + Extended Initialization and de-initialization functions
-  *           + Extended Peripheral Control functions
-  *         
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup PWREx PWREx
-  * @brief    PWR HAL module driver
-  * @{
-  */
-
-#ifdef HAL_PWR_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
-  * @{
-  */
-
-/** @defgroup PWREx_Exported_Functions_Group1 Peripheral Extended Features Functions
-  * @brief    Low Power modes configuration functions
-  *
-@verbatim
-
- ===============================================================================
-                 ##### Peripheral extended features functions #####
- ===============================================================================
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Enables the Fast WakeUp from Ultra Low Power mode.
-  * @note   This bit works in conjunction with ULP bit. 
-  *         Means, when ULP = 1 and FWU = 1 :VREFINT startup time is ignored when 
-  *         exiting from low power mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableFastWakeUp(void)
-{
-  /* Enable the fast wake up */
-  *(__IO uint32_t *) CR_FWU_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Fast WakeUp from Ultra Low Power mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableFastWakeUp(void)
-{
-  /* Disable the fast wake up */
-  *(__IO uint32_t *) CR_FWU_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Enables the Ultra Low Power mode
-  * @retval None
-  */
-void HAL_PWREx_EnableUltraLowPower(void)
-{
-  /* Enable the Ultra Low Power mode */
-  *(__IO uint32_t *) CR_ULP_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Ultra Low Power mode
-  * @retval None
-  */
-void HAL_PWREx_DisableUltraLowPower(void)
-{
-  /* Disable the Ultra Low Power mode */
-  *(__IO uint32_t *) CR_ULP_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Enters the Low Power Run mode.
-  * @note   Low power run mode can only be entered when VCORE is in range 2.
-  *         In addition, the dynamic voltage scaling must not be used when Low
-  *         power run mode is selected. Only Stop and Sleep modes with regulator
-  *         configured in Low power mode is allowed when Low power run mode is 
-  *         selected.
-  * @note   In Low power run mode, all I/O pins keep the same state as in Run mode.
-  * @retval None
-  */
-void HAL_PWREx_EnableLowPowerRunMode(void)
-{
-  /* Enters the Low Power Run mode */
-  *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)ENABLE;
-  *(__IO uint32_t *) CR_LPRUN_BB  = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Exits the Low Power Run mode.
-  * @retval None
-  */
-void HAL_PWREx_DisableLowPowerRunMode(void)
-{
-  /* Exits the Low Power Run mode */
-  *(__IO uint32_t *) CR_LPRUN_BB  = (uint32_t)DISABLE;
-  *(__IO uint32_t *) CR_LPSDSR_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_PWR_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_pwr_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,135 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_pwr_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of PWR HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_PWR_EX_H
-#define __STM32L1xx_HAL_PWR_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup PWREx
-  * @{
-  */
-
-
-/* Exported types ------------------------------------------------------------*/
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Constants PWREx Exported Constants
- *  @{
- */
-
-
-/** @defgroup PWR_WakeUp_Pins PWREx Wakeup Pins
-  * @{
-  */
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L151xB) || defined (STM32L151xBA) || defined (STM32L151xC) || defined (STM32L152xB) || defined (STM32L152xBA) || defined (STM32L152xC) || defined (STM32L162xC)
-
-#define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP1
-#define PWR_WAKEUP_PIN2                 PWR_CSR_EWUP2
-#define PWR_WAKEUP_PIN3                 PWR_CSR_EWUP3
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN2) || \
-                                ((PIN) == PWR_WAKEUP_PIN3))
-#else
-#define PWR_WAKEUP_PIN1                 PWR_CSR_EWUP1
-#define PWR_WAKEUP_PIN2                 PWR_CSR_EWUP2
-#define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1) || \
-                                ((PIN) == PWR_WAKEUP_PIN2))
-#endif
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
-
-/** @defgroup PWREx_Exported_Functions PWREx Exported Functions
- *  @{
- */
- 
-/** @addtogroup PWREx_Exported_Functions_Group1
-  * @{
-  */
-  
-/* Peripheral Control methods  ************************************************/
-void HAL_PWREx_EnableFastWakeUp(void);
-void HAL_PWREx_DisableFastWakeUp(void);
-void HAL_PWREx_EnableUltraLowPower(void);
-void HAL_PWREx_DisableUltraLowPower(void);
-void HAL_PWREx_EnableLowPowerRunMode(void);
-void HAL_PWREx_DisableLowPowerRunMode(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_PWR_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1313 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rcc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   RCC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Reset and Clock Control (RCC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + Peripheral Control functions
-  *       
-  @verbatim                
-  ==============================================================================
-                      ##### RCC specific features #####
-  ==============================================================================
-    [..]  
-      After reset the device is running from multispeed internal oscillator clock 
-      (MSI 2.097MHz) with Flash 0 wait state and Flash prefetch buffer is disabled, 
-      and all peripherals are off except internal SRAM, Flash and JTAG.
-      (+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
-          all peripherals mapped on these busses are running at MSI speed.
-      (+) The clock for all peripherals is switched off, except the SRAM and FLASH.
-      (+) All GPIOs are in input floating state, except the JTAG pins which
-          are assigned to be used for debug purpose.
-    [..] Once the device started from reset, the user application has to:
-      (+) Configure the clock source to be used to drive the System clock
-          (if the application needs higher frequency/performance)
-      (+) Configure the System clock frequency and Flash settings  
-      (+) Configure the AHB and APB busses prescalers
-      (+) Enable the clock for the peripheral(s) to be used
-      (+) Configure the clock source(s) for peripherals whose clocks are not
-          derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG) 
-          (*) SDIO only for STM32L1xxxD devices
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-*/ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCC RCC
-* @brief RCC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup RCC_Private_Defines RCC Private Defines
-  * @{
-  */
-
-#define HSE_TIMEOUT_VALUE          HSE_STARTUP_TIMEOUT
-#define MSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
-#define HSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
-#define LSI_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
-#define PLL_TIMEOUT_VALUE          ((uint32_t)100)  /* 100 ms */
-#define CLOCKSWITCH_TIMEOUT_VALUE  ((uint32_t)5000) /* 5 s    */
-
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/** @defgroup RCC_Private_Macros RCC Private Macros
-  * @{
-  */
-
-#define __MCO1_CLK_ENABLE()   __GPIOA_CLK_ENABLE()
-#define MCO1_GPIO_PORT        GPIOA
-#define MCO1_PIN              GPIO_PIN_8
-
-/**
-  * @}
-  */
-
-/* Private variables ---------------------------------------------------------*/
-/** @defgroup RCC_Private_Variables RCC Private Variables
-  * @{
-  */
-const uint8_t aAPBAHBPrescTable[16]       = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
-const uint8_t aPLLDivisionFactorTable[4]  = {1, 2, 3, 4};
-const uint8_t aPLLMulFactorTable[9]       = {3, 4, 6, 8, 12, 16, 24, 32, 48};
-
-/**
-  * @}
-  */
-
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCC_Private_Functions RCC Exported Functions
-  * @{
-  */
-
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
-  *
-  @verbatim    
-  ===============================================================================
-##### Initialization and de-initialization functions #####
-  ===============================================================================
-    [..]
-      This section provides functions allowing to configure the internal/external oscillators
-      (MSI, HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1 
-      and APB2).
-
-    [..] Internal/external clock and PLL configuration
-      (#) MSI (Multispeed internal), Seven frequency ranges are available: 65.536 kHz, 
-          131.072 kHz, 262.144 kHz, 524.288 kHz, 1.048 MHz, 2.097 MHz (default value) and 4.194 MHz.
-
-      (#) HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
-          the PLL as System clock source.
-
-      (#) LSI (low-speed internal), ~37 KHz low consumption RC used as IWDG and/or RTC
-          clock source.
-
-      (#) HSE (high-speed external), 1 to 24 MHz crystal oscillator used directly or
-          through the PLL as System clock source. Can be used also as RTC clock source.
-
-      (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
-
-      (#) PLL (clocked by HSI or HSE), featuring two different output clocks:
-        (++) The first output is used to generate the high speed system clock (up to 32 MHz)
-        (++) The second output is used to generate the clock for the USB OTG FS (48 MHz)
-
-      (#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
-          and if a HSE clock failure occurs(HSE used directly or through PLL as System 
-          clock source), the System clockis automatically switched to MSI and an interrupt
-          is generated if enabled. The interrupt is linked to the Cortex-M3 NMI 
-          (Non-Maskable Interrupt) exception vector.   
-
-      (#) MCO1 (microcontroller clock output), used to output SYSCLK, HSI, LSI, MSI, LSE, 
-          HSE or PLL clock (through a configurable prescaler) on PA8 pin.
-
-    [..] System, AHB and APB busses clocks configuration  
-      (#) Several clock sources can be used to drive the System clock (SYSCLK): MSI, HSI,
-          HSE and PLL.
-          The AHB clock (HCLK) is derived from System clock through configurable 
-          prescaler and used to clock the CPU, memory and peripherals mapped 
-          on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived 
-          from AHB clock through configurable prescalers and used to clock 
-          the peripherals mapped on these busses. You can use 
-          "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.  
-
-      -@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
-          (+@) RTC: RTC clock can be derived either from the LSI, LSE or HSE clock
-              divided by 2 to 16. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
-              macros to configure this clock. 
-          (+@) LCD: LCD clock can be derived either from the LSI, LSE or HSE clock
-              divided by 2 to 16. You have to use __HAL_RCC_LCD_CONFIG()
-              macros to configure this clock. 
-          (+@) USB OTG FS and RTC: USB OTG FS require a frequency equal to 48 MHz
-              to work correctly. This clock is derived of the main PLL through PLL Multiplier.
-          (+@) IWDG clock which is always the LSI clock.
-
-      (#) The maximum frequency of the SYSCLK and HCLK is 32 MHz, PCLK2 32 MHz 
-          and PCLK1 32 MHz. Depending on the device voltage range, the maximum 
-          frequency should be adapted accordingly:
-  +----------------------------------------------------------------------+     
-  | Latency       |                HCLK clock frequency (MHz)            |
-  |               |------------------------------------------------------|     
-  |               | voltage range 1  | voltage range 2 | voltage range 3 |
-  |               |      1.8 V       |     1.5 V       |      1.2 V      |
-  |---------------|------------------|-----------------|-----------------|              
-  |0WS(1CPU cycle)| 0 < HCLK <= 16   | 0 < HCLK <= 8   | 0 < HCLK <= 2   |
-  |---------------|------------------|-----------------|-----------------| 
-  |1WS(2CPU cycle)| 16 < HCLK <= 32  | 8 < HCLK <= 16  | 2 < HCLK <= 4   | 
-  +----------------------------------------------------------------------+     
-      (#) The following table gives the different clock source frequencies depending on the product
-      voltage range:
-  +------------------------------------------------------------------------------------------+     
-  | Product voltage |                    Clock frequency                                     |
-  |                 |------------------|-----------------------------|-----------------------|              
-  |      range      |   MSI   |   HSI  |              HSE            |          PLL          |
-  |-----------------|---------|--------|-----------------------------|-----------------------|              
-  | Range 1 (1.8 V) | 4.2 MHz | 16 MHz | HSE 32 MHz (external clock) |         32 MHz        |
-  |                 |         |        |      or 24 MHz (crystal)    | (PLLVCO max = 96 MHz) |
-  |-----------------|---------|--------|-----------------------------|-----------------------|              
-  | Range 2 (1.5 V) | 4.2 MHz | 16 MHz |         16 MHz              |         16 MHz        |
-  |                 |         |        |                             | (PLLVCO max = 48 MHz) |
-  |-----------------|---------|--------|-----------------------------|-----------------------|              
-  | Range 3 (1.2 V) | 4.2 MHz |   NA   |         8 MHz               |           4 MHz       |
-  |                 |         |        |                             | (PLLVCO max = 24 MHz) |
-  +------------------------------------------------------------------------------------------+     
-
-  @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Resets the RCC clock configuration to the default reset state.
-  * @note   The default reset state of the clock configuration is given below:
-  *            - MSI ON and used as system clock source
-  *            - HSI, HSE and PLL  OFF
-  *            - AHB, APB1 and APB2 prescaler set to 1.
-  *            - CSS and MCO1 OFF
-  *            - All interrupts disabled
-  * @note   This function doesn't modify the configuration of the
-  *            - Peripheral clocks  
-  *            - LSI, LSE and RTC clocks 
-  * @retval None
-  */
-void HAL_RCC_DeInit(void)
-{
-  /* Set MSION bit */
-  SET_BIT(RCC->CR, RCC_CR_MSION);
-  
-  /* Switch SYSCLK to MSI*/
-  CLEAR_BIT(RCC->CFGR, RCC_CFGR_SW);
-  
-  /* Reset HSION, HSEON, CSSON, HSEBYP & PLLON bits */
-  CLEAR_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_HSEBYP);
-  
-  /* Reset CFGR register */
-  CLEAR_REG(RCC->CFGR);
-  
-  /* Set MSIClockRange & MSITRIM[4:0] bits to the reset value */
-  MODIFY_REG(RCC->ICSCR, (RCC_ICSCR_MSIRANGE | RCC_ICSCR_MSITRIM), (((uint32_t)0 << POSITION_VAL(RCC_ICSCR_MSITRIM)) | RCC_ICSCR_MSIRANGE_5));
-  
-  /* Set HSITRIM bits to the reset value */
-  MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, ((uint32_t)0x10 << POSITION_VAL(RCC_ICSCR_HSITRIM)));
-  
-  /* Disable all interrupts */
-  CLEAR_REG(RCC->CIR);
-}
-
-/**
-  * @brief  Initializes the RCC Oscillators according to the specified parameters in the
-  *         RCC_OscInitTypeDef.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC Oscillators.
-  * @note   The PLL is not disabled when used as system clock.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-   uint32_t tickstart = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-  
-  /*------------------------------- HSE Configuration ------------------------*/ 
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
-    /* When the HSE is used as system clock or clock source for PLL in these cases it is not allowed to be disabled */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSE) 
-       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSE)))
-    {
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState != RCC_HSE_ON))
-      {
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Reset HSEON and HSEBYP bits before configuring the HSE --------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_HSE_OFF);
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till HSE is disabled */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-      
-      /* Set the new HSE configuration ---------------------------------------*/
-      __HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-      
-      /* Check the HSE State */
-      if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till HSE is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till HSE is bypassed or disabled */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
-        {
-           if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- HSI Configuration --------------------------*/ 
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
-    assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-    
-    /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */ 
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) 
-       || ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && (__HAL_RCC_GET_PLL_OSCSOURCE() == RCC_PLLSOURCE_HSI)))
-    {
-      /* When HSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) && (RCC_OscInitStruct->HSIState != RCC_HSI_ON))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the HSI State */
-      if((RCC_OscInitStruct->HSIState)!= RCC_HSI_OFF)
-      {
-        /* Enable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_ENABLE();
-        
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till HSI is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-                
-        /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
-        __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Internal High Speed oscillator (HSI). */
-        __HAL_RCC_HSI_DISABLE();
-        
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till HSI is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-  }
-  /*----------------------------- MSI Configuration --------------------------*/ 
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_MSI(RCC_OscInitStruct->MSIState));
-    assert_param(IS_RCC_MSIRANGE(RCC_OscInitStruct->MSIClockRange));
-    
-    /* Configures the Internal Multi Speed oscillator (MSI) clock range. */
-    __HAL_RCC_MSI_RANGE_CONFIG(RCC_OscInitStruct->MSIClockRange);
-    
-    /* Check if MSI is used as system clock */
-    if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_MSI))
-    {
-      /* When MSI is used as system clock it will not disabled */
-      if((__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET) && (RCC_OscInitStruct->MSIState != RCC_MSI_ON))
-      {
-        return HAL_ERROR;
-      }
-      /* Otherwise, just the calibration is allowed */
-      else
-      {
-        /* Adjusts the Multi Speed oscillator (MSI) calibration value. */
-        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-      }
-    }
-    else
-    {
-      /* Check the MSI State */
-      if((RCC_OscInitStruct->MSIState)!= RCC_MSI_OFF)
-      {
-        /* Enable the Multi Speed oscillator (MSI). */
-        __HAL_RCC_MSI_ENABLE();
-        
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till MSI is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-        
-        /* Adjusts the Multi Speed oscillator (MSI) calibration value. */
-        __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->MSICalibrationValue);
-      }
-      else
-      {
-        /* Disable the Multi Speed oscillator (MSI). */
-        __HAL_RCC_MSI_DISABLE();
-        
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till MSI is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > MSI_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        } 
-      }
-    }
-  }  
-  /*------------------------------ LSI Configuration -------------------------*/ 
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSI(RCC_OscInitStruct->LSIState));
-    
-    /* Check the LSI State */
-    if((RCC_OscInitStruct->LSIState)!= RCC_LSI_OFF)
-    {
-      /* Enable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_ENABLE();
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Disable the Internal Low Speed oscillator (LSI). */
-      __HAL_RCC_LSI_DISABLE();
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSI is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*------------------------------ LSE Configuration -------------------------*/ 
-  if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
-  {
-    /* Check the parameters */
-    assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-    
-    /* Enable Power Clock*/
-    __PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    SET_BIT(PWR->CR, PWR_CR_DBP);
-
-    /* Wait for Backup domain Write protection disable */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }      
-    }
-    
-    /* Reset LSEON and LSEBYP bits before configuring the LSE ----------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_LSE_OFF);
-    
-    /* Get Start Tick*/
-    tickstart = HAL_GetTick();
-    
-    /* Wait till LSE is ready */  
-    while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }
-    }
-    
-    /* Set the new LSE configuration -----------------------------------------*/
-    __HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
-    /* Check the LSE State */
-    if((RCC_OscInitStruct->LSEState) == RCC_LSE_ON)
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-    else
-    {
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  /*-------------------------------- PLL Configuration -----------------------*/
-  /* Check the parameters */
-  assert_param(IS_RCC_PLL(RCC_OscInitStruct->PLL.PLLState));
-  if ((RCC_OscInitStruct->PLL.PLLState) != RCC_PLL_NONE)
-  {
-    /* Check if the PLL is used as system clock or not */
-    if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-    { 
-      if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
-      {
-        /* Check the parameters */
-        assert_param(IS_RCC_PLLSOURCE(RCC_OscInitStruct->PLL.PLLSource));
-        assert_param(IS_RCC_PLL_MUL(RCC_OscInitStruct->PLL.PLLMUL));
-        assert_param(IS_RCC_PLL_DIV(RCC_OscInitStruct->PLL.PLLDIV));
-        
-        
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
-        
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-        
-        /* Configure the main PLL clock source, multiplication and division factors. */
-        __HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
-                             RCC_OscInitStruct->PLL.PLLMUL,
-                             RCC_OscInitStruct->PLL.PLLDIV);
-        /* Enable the main PLL. */
-        __HAL_RCC_PLL_ENABLE();
-        
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  == RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else
-      {
-        /* Disable the main PLL. */
-        __HAL_RCC_PLL_DISABLE();
- 
-        /* Get Start Tick*/
-        tickstart = HAL_GetTick();
-        
-        /* Wait till PLL is ready */  
-        while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY)  != RESET)
-        {
-          if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }
-    else
-    {
-      return HAL_ERROR;
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the CPU, AHB and APB busses clocks according to the specified 
-  *         parameters in the RCC_ClkInitStruct.
-  * @param  RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
-  *         contains the configuration information for the RCC peripheral.
-  * @param  FLatency: FLASH Latency                   
-  *          This parameter can be one of the following values:
-  *            @arg FLASH_LATENCY_0:  FLASH Zero Latency cycle
-  *            @arg FLASH_LATENCY_1:  FLASH One Latency cycle
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
-  *         and updated by HAL_RCC_GetHCLKFreq() function called within this function
-  *
-  * @note   The MSI is used (enabled by hardware) as system clock source after
-  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
-  *         of failure of the HSE used directly or indirectly as system clock
-  *         (if the Clock Security System CSS is enabled).
-  *           
-  * @note   A switch from one clock source to another occurs only if the target
-  *         clock source is ready (clock stable after startup delay or PLL locked). 
-  *         If a clock source which is not yet ready is selected, the switch will
-  *         occur when the clock source will be ready. 
-  *         You can use HAL_RCC_GetClockConfig() function to know which clock is
-  *         currently used as system clock source.
-  * @note   Depending on the device voltage range, the software has to set correctly
-  *         HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
-  *         (for more details refer to section above "Initialization/de-initialization functions")
-  * @retval None
-  */
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency)
-{
-  uint32_t tickstart = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
-  assert_param(IS_FLASH_LATENCY(FLatency));
-  
-  /* To correctly read data from FLASH memory, the number of wait states (LATENCY) 
-  must be correctly programmed according to the frequency of the CPU clock 
-  (HCLK) and the supply voltage of the device. */
-  
-  /* Increasing the CPU frequency */
-  if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
-  {    
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-    
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
-    {
-      return HAL_ERROR;
-    }
-    
-    /*-------------------------- HCLK Configuration --------------------------*/
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-    {
-      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-    }
-
-    /*------------------------- SYSCLK Configuration ---------------------------*/ 
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-    {    
-      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-      
-      /* HSE is selected as System Clock Source */
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-      {
-        /* Check the HSE ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* PLL is selected as System Clock Source */
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-      {
-        /* Check the PLL ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* HSI is selected as System Clock Source */
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
-      {
-        /* Check the HSI ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* MSI is selected as System Clock Source */
-      else
-      {
-        /* Check the MSI ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-      {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-      {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
-      {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }      
-      else
-      {
-        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    }    
-  }
-  /* Decreasing the CPU frequency */
-  else
-  {
-    /*-------------------------- HCLK Configuration --------------------------*/
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
-    {
-      assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
-    }
-    
-    /*------------------------- SYSCLK Configuration -------------------------*/
-    if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
-    {    
-      assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-      
-      /* HSE is selected as System Clock Source */
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-      {
-        /* Check the HSE ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* PLL is selected as System Clock Source */
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-      {
-        /* Check the PLL ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* HSI is selected as System Clock Source */
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
-      {
-        /* Check the HSI ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      /* MSI is selected as System Clock Source */
-      else
-      {
-        /* Check the MSI ready flag */  
-        if(__HAL_RCC_GET_FLAG(RCC_FLAG_MSIRDY) == RESET)
-        {
-          return HAL_ERROR;
-        }
-      }
-      MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
-      
-      /* Get Start Tick*/
-      tickstart = HAL_GetTick();
-      
-      if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
-      {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSE)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
-      {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-      else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSI)
-      {
-        while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_HSI)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }      
-      else
-      {
-        while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_MSI)
-        {
-          if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
-          {
-            return HAL_TIMEOUT;
-          }
-        }
-      }
-    } 
-    
-    /* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
-    __HAL_FLASH_SET_LATENCY(FLatency);
-    
-    /* Check that the new number of wait states is taken into account to access the Flash
-    memory by reading the FLASH_ACR register */
-    if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
-    {
-      return HAL_ERROR;
-    }
-  }
-  
-  /*-------------------------- PCLK1 Configuration ---------------------------*/ 
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
-  }
-  
-  /*-------------------------- PCLK2 Configuration ---------------------------*/ 
-  if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
-  {
-    assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
-    MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, ((RCC_ClkInitStruct->APB2CLKDivider) << 3));
-  }
-  
-  /* Configure the source of time base considering new system clocks settings*/
-  HAL_InitTick (TICK_INT_PRIORITY);
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions 
-  *  @brief   RCC clocks control functions 
-  *
-  @verbatim   
-  ===============================================================================
-                  ##### Peripheral Control functions #####
-  ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks 
-    frequencies.
-
-  @endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Selects the clock source to output on MCO pin.
-  * @note   MCO pin should be configured in alternate function mode.
-  * @param  RCC_MCOx: specifies the output direction for the clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCO: Clock source to output on MCO1 pin(PA8).
-  * @param  RCC_MCOSource: specifies the clock source to output.
-  *          This parameter can be one of the following values:
-  *     @arg RCC_MCO1SOURCE_NOCLOCK: No clock selected
-  *     @arg RCC_MCO1SOURCE_SYSCLK: System clock selected
-  *     @arg RCC_MCO1SOURCE_HSI: HSI oscillator clock selected
-  *     @arg RCC_MCO1SOURCE_MSI: MSI oscillator clock selected  
-  *     @arg RCC_MCO1SOURCE_HSE: HSE oscillator clock selected
-  *     @arg RCC_MCO1SOURCE_PLLCLK: PLL clock selected
-  *     @arg RCC_MCO1SOURCE_LSI: LSI clock selected
-  *     @arg RCC_MCO1SOURCE_LSE: LSE clock selected    
-  * @param  RCC_MCODiv: specifies the MCO DIV.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_MCODIV_1: no division applied to MCO clock
-  *            @arg RCC_MCODIV_2: division by 2 applied to MCO clock
-  *            @arg RCC_MCODIV_4: division by 4 applied to MCO clock
-  *            @arg RCC_MCODIV_8: division by 8 applied to MCO clock
-  *            @arg RCC_MCODIV_16: division by 16 applied to MCO clock
-  * @retval None
-  */
-void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv)
-{
-  GPIO_InitTypeDef gpio;
-  
-  /* Check the parameters */
-  assert_param(IS_RCC_MCO(RCC_MCOx));
-  assert_param(IS_RCC_MCODIV(RCC_MCODiv));
-  assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-  
-  /* MCO Clock Enable */
-  __MCO1_CLK_ENABLE();
-  
-  /* Configure the MCO1 pin in alternate function mode */    
-  gpio.Pin = MCO1_PIN;
-  gpio.Mode = GPIO_MODE_AF_PP;
-  gpio.Speed = GPIO_SPEED_HIGH;
-  gpio.Pull = GPIO_NOPULL;
-  gpio.Alternate = GPIO_AF0_MCO;
-  HAL_GPIO_Init(MCO1_GPIO_PORT, &gpio);
-  
-  /* Mask MCO and MCOPRE[2:0] bits then Select MCO clock source and prescaler */
-  MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCOSEL | RCC_CFGR_MCOPRE), (RCC_MCOSource | RCC_MCODiv));
-}
-
-/**
-  * @brief  Enables the Clock Security System.
-  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
-  *         is automatically disabled and an interrupt is generated to inform the
-  *         software about the failure (Clock Security System Interrupt, CSSI),
-  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
-  *         the Cortex-M3 NMI (Non-Maskable Interrupt) exception vector.  
-  * @retval None
-  */
-void HAL_RCC_EnableCSS(void)
-{
-  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the Clock Security System.
-  * @retval None
-  */
-void HAL_RCC_DisableCSS(void)
-{
-  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)DISABLE;
-}
-
-/**
-  * @brief  Returns the SYSCLK frequency     
-  *        
-  * @note   The system frequency computed by this function is not the real 
-  *         frequency in the chip. It is calculated based on the predefined 
-  *         constant and the selected clock source:
-  * @note     If SYSCLK source is MSI, function returns values based on MSI
-  *             Value as defined by the MSI range.
-  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
-  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
-  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 
-  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
-  * @note     (*) HSI_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value
-  *               16 MHz) but the real value may vary depending on the variations
-  *               in voltage and temperature.
-  * @note     (**) HSE_VALUE is a constant defined in stm32l1xx_hal_conf.h file (default value
-  *                8 MHz), user has to ensure that HSE_VALUE is same as the real
-  *                frequency of the crystal used. Otherwise, this function may
-  *                have wrong result.
-  *                  
-  * @note   The result of this function could be not correct when using fractional
-  *         value for HSE crystal.
-  *           
-  * @note   This function can be used by the user application to compute the 
-  *         baudrate for the communication peripherals or configure other parameters.
-  *           
-  * @note   Each time SYSCLK changes, this function must be called to update the
-  *         right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
-  *         
-  *               
-  * @retval SYSCLK frequency
-  */
-uint32_t HAL_RCC_GetSysClockFreq(void)
-{
-  uint32_t tmpreg = 0, pllm = 0, plld = 0, pllvco = 0, msiclkrange = 0;
-  uint32_t sysclockfreq = 0;
-  
-  tmpreg = RCC->CFGR;
-  
-  /* Get SYSCLK source -------------------------------------------------------*/
-  switch (tmpreg & RCC_CFGR_SWS)
-  {
-  case RCC_CFGR_SWS_HSI:  /* HSI used as system clock source */
-    {
-      sysclockfreq = HSI_VALUE;
-      break;
-    }
-    case RCC_CFGR_SWS_HSE:  /* HSE used as system clock */
-    {
-      sysclockfreq = HSE_VALUE;
-      break;
-    }
-    case RCC_CFGR_SWS_PLL:  /* PLL used as system clock */
-    {
-      pllm = aPLLMulFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLMUL) >> POSITION_VAL(RCC_CFGR_PLLMUL)];
-      plld = aPLLDivisionFactorTable[(uint32_t)(tmpreg & RCC_CFGR_PLLDIV) >> POSITION_VAL(RCC_CFGR_PLLDIV)];
-      if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
-      {
-        /* HSE used as PLL clock source */
-        pllvco = HSE_VALUE * (pllm / plld);
-      }
-      else
-      {
-        /* HSI used as PLL clock source */
-        pllvco = HSI_VALUE * (pllm / plld);
-      }
-      sysclockfreq = pllvco;
-      break;
-    }
-  case RCC_CFGR_SWS_MSI:  /* MSI used as system clock source */
-  default: /* MSI used as system clock */
-    {
-      msiclkrange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE ) >> POSITION_VAL(RCC_ICSCR_MSIRANGE);
-      sysclockfreq = (32768 * (1 << (msiclkrange + 1)));
-      break;
-    }
-  }
-  return sysclockfreq;
-}
-
-/**
-  * @brief  Returns the HCLK frequency     
-  * @note   Each time HCLK changes, this function must be called to update the
-  *         right HCLK value. Otherwise, any configuration based on this function will be incorrect.
-  * 
-  * @note   The SystemCoreClock CMSIS variable is used to store System Clock Frequency 
-  *         and updated within this function
-  * @retval HCLK frequency
-  */
-uint32_t HAL_RCC_GetHCLKFreq(void)
-{
-  SystemCoreClock = HAL_RCC_GetSysClockFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
-  return SystemCoreClock;
-}
-
-/**
-  * @brief  Returns the PCLK1 frequency     
-  * @note   Each time PCLK1 changes, this function must be called to update the
-  *         right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK1 frequency
-  */
-uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
-  /* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq() >> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
-}    
-
-/**
-  * @brief  Returns the PCLK2 frequency     
-  * @note   Each time PCLK2 changes, this function must be called to update the
-  *         right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
-  * @retval PCLK2 frequency
-  */
-uint32_t HAL_RCC_GetPCLK2Freq(void)
-{
-  /* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
-  return (HAL_RCC_GetHCLKFreq()>> aAPBAHBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
-} 
-
-/**
-  * @brief  Configures the RCC_OscInitStruct according to the internal 
-  * RCC configuration registers.
-  * @param  RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that 
-  * will be configured.
-  * @retval None
-  */
-void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct)
-{
-  /* Set all possible values for the Oscillator type parameter ---------------*/
-  RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI  \
-                  | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_MSI;
-  
-  /* Get the HSE configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_BYPASS;
-  }
-  else if((RCC->CR &RCC_CR_HSEON) == RCC_CR_HSEON)
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
-  }
-  
-  /* Get the HSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
-  }
-  
-  RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_HSITRIM) >> POSITION_VAL(RCC_ICSCR_HSITRIM));
-  
-  /* Get the MSI configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_MSION) == RCC_CR_MSION)
-  {
-    RCC_OscInitStruct->MSIState = RCC_MSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->MSIState = RCC_MSI_OFF;
-  }
-  
-  RCC_OscInitStruct->MSICalibrationValue = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSITRIM) >> POSITION_VAL(RCC_ICSCR_MSITRIM));
-  RCC_OscInitStruct->MSIClockRange = (uint32_t)((RCC->ICSCR & RCC_ICSCR_MSIRANGE));
-  
-  /* Get the LSE configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSEBYP) == RCC_CSR_LSEBYP)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_BYPASS;
-  }
-  else if((RCC->CSR &RCC_CSR_LSEON) == RCC_CSR_LSEON)
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
-  }
-  
-  /* Get the LSI configuration -----------------------------------------------*/
-  if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
-  }
-  
-  /* Get the PLL configuration -----------------------------------------------*/
-  if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_ON;
-  }
-  else
-  {
-    RCC_OscInitStruct->PLL.PLLState = RCC_PLL_OFF;
-  }
-  RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLSRC);
-  RCC_OscInitStruct->PLL.PLLMUL = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLMUL);
-  RCC_OscInitStruct->PLL.PLLDIV = (uint32_t)(RCC->CFGR & RCC_CFGR_PLLDIV);
-}
-
-/**
-  * @brief  Configures the RCC_ClkInitStruct according to the internal 
-  * RCC configuration registers.
-  * @param  RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that 
-  * will be configured.
-  * @param  pFLatency: Pointer on the Flash Latency.
-  * @retval None
-  */
-void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency)
-{
-  /* Set all possible values for the Clock type parameter --------------------*/
-  RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-  
-  /* Get the SYSCLK configuration --------------------------------------------*/ 
-  RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-  
-  /* Get the HCLK configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE); 
-  
-  /* Get the APB1 configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);   
-  
-  /* Get the APB2 configuration ----------------------------------------------*/ 
-  RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
-  
-  /* Get the Flash Wait State (Latency) configuration ------------------------*/   
-  *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY); 
-}
-
-/**
-  * @brief This function handles the RCC CSS interrupt request.
-  * @note This API should be called under the NMI_Handler().
-  * @retval None
-  */
-void HAL_RCC_NMI_IRQHandler(void)
-{
-  /* Check RCC CSSF flag  */
-  if(__HAL_RCC_GET_IT(RCC_IT_CSS))
-  {
-    /* RCC Clock Security System interrupt user callback */
-    HAL_RCC_CCSCallback();
-    
-    /* Clear RCC CSS pending bit */
-    __HAL_RCC_CLEAR_IT(RCC_IT_CSS);
-  }
-}
-
-/**
-  * @brief  RCC Clock Security System interrupt callback
-  * @retval none
-  */
-__weak void HAL_RCC_CCSCallback(void)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-    the HAL_RCC_CCSCallback could be implemented in the user file
-    */ 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1227 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rcc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of RCC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_RCC_H
-#define __STM32L1xx_HAL_RCC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup RCC_Exported_Types RCC Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  RCC PLL configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t PLLState;     /*!< The new state of the PLL.
-                              This parameter can be a value of @ref RCC_PLL_Config */
-
-  uint32_t PLLSource;    /*!< PLLSource: PLL entry clock source.
-                              This parameter must be a value of @ref RCC_PLL_Clock_Source */           
-
-  uint32_t PLLMUL;         /*!< PLLMUL: Multiplication factor for PLL VCO input clock
-                              This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/        
-
-  uint32_t PLLDIV;         /*!< PLLDIV: Division factor for PLL VCO input clock
-                              This parameter must be a value of @ref RCC_PLL_Division_Factor*/        
-} RCC_PLLInitTypeDef;
-   
-/** 
-  * @brief  RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t OscillatorType;       /*!< The oscillators to be configured.
-                                       This parameter can be a value of @ref RCC_Oscillator_Type */
-
-  uint32_t HSEState;              /*!< The new state of the HSE.
-                                       This parameter can be a value of @ref RCC_HSE_Config */
-                          
-  uint32_t LSEState;              /*!<  The new state of the LSE.
-                                        This parameter can be a value of @ref RCC_LSE_Config */
-                                          
-  uint32_t HSIState;              /*!< The new state of the HSI.
-                                       This parameter can be a value of @ref RCC_HSI_Config */
-
-  uint32_t HSICalibrationValue;   /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
-                               
-  uint32_t LSIState;              /*!<  The new state of the LSI.
-                                        This parameter can be a value of @ref RCC_LSI_Config */
-
-  uint32_t MSIState;              /*!<  The new state of the MSI.
-                                        This parameter can be a value of @ref RCC_MSI_Config */
-
-  uint32_t MSICalibrationValue;   /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
-                                       This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
-                               
-  uint32_t MSIClockRange;         /*!< The MSI  frequency  range.
-                                        This parameter can be a value of @ref RCC_MSI_Clock_Range */
-
-  RCC_PLLInitTypeDef PLL;         /*!< PLL structure parameters */      
-
-} RCC_OscInitTypeDef;
-
-/** 
-  * @brief  RCC System, AHB and APB busses clock configuration structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockType;             /*!< The clock to be configured.
-                                       This parameter can be a value of @ref RCC_System_Clock_Type */
-  
-  uint32_t SYSCLKSource;          /*!< The clock source (SYSCLKS) used as system clock.
-                                       This parameter can be a value of @ref RCC_System_Clock_Source */
-
-  uint32_t AHBCLKDivider;         /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
-                                       This parameter can be a value of @ref RCC_AHB_Clock_Source */
-  
-  uint32_t APB1CLKDivider;        /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-  
-  uint32_t APB2CLKDivider;        /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
-                                       This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
-
-} RCC_ClkInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RCC_Exported_Constants RCC Exported Constants
-  * @{
-  */
-#define DBP_TIMEOUT_VALUE          ((uint32_t)100)
-#define LSE_TIMEOUT_VALUE          LSE_STARTUP_TIMEOUT
-
-/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
-  * @brief RCC registers bit address in the alias region
-  * @{
-  */
-#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
-#define RCC_CR_OFFSET             0x00
-#define RCC_CFGR_OFFSET           0x08
-#define RCC_CIR_OFFSET            0x0C
-#define RCC_CSR_OFFSET            0x34
-#define RCC_CR_OFFSET_BB          (RCC_OFFSET + RCC_CR_OFFSET)
-#define RCC_CFGR_OFFSET_BB        (RCC_OFFSET + RCC_CFGR_OFFSET)
-#define RCC_CIR_OFFSET_BB         (RCC_OFFSET + RCC_CIR_OFFSET)
-#define RCC_CSR_OFFSET_BB         (RCC_OFFSET + RCC_CSR_OFFSET)
-
-/* --- CR Register ---*/
-/* Alias word address of HSION bit */
-#define HSION_BITNUMBER           POSITION_VAL(RCC_CR_HSION)
-#define CR_HSION_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
-/* Alias word address of MSION bit */
-#define MSION_BITNUMBER           POSITION_VAL(RCC_CR_MSION)
-#define CR_MSION_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (MSION_BITNUMBER * 4)))
-/* Alias word address of HSEON bit */
-#define HSEON_BITNUMBER           POSITION_VAL(RCC_CR_HSEON)
-#define CR_HSEON_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
-/* Alias word address of CSSON bit */
-#define CSSON_BITNUMBER           POSITION_VAL(RCC_CR_CSSON)
-#define CR_CSSON_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
-/* Alias word address of PLLON bit */
-#define PLLON_BITNUMBER           POSITION_VAL(RCC_CR_PLLON)
-#define CR_PLLON_BB               ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
-
-/* --- CSR Register ---*/
-/* Alias word address of LSION bit */
-#define LSION_BITNUMBER           POSITION_VAL(RCC_CSR_LSION)
-#define CSR_LSION_BB              ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
-
-/* Alias word address of LSEON bit */
-#define LSEON_BITNUMBER           POSITION_VAL(RCC_CSR_LSEON)
-#define CSR_LSEON_BB              ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
-
-/* Alias word address of LSEON bit */
-#define LSEBYP_BITNUMBER          POSITION_VAL(RCC_CSR_LSEBYP)
-#define CSR_LSEBYP_BB             ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
-
-/* Alias word address of RTCEN bit */
-#define RTCEN_BITNUMBER           POSITION_VAL(RCC_CSR_RTCEN)
-#define CSR_RTCEN_BB              ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
-
-/* Alias word address of RTCRST bit */
-#define RTCRST_BITNUMBER          POSITION_VAL(RCC_CSR_RTCRST)
-#define CSR_RTCRST_BB             ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCRST_BITNUMBER * 4)))
-
-/* CR register byte 2 (Bits[23:16]) base address */
-#define CR_BYTE2_ADDRESS          ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
-
-/* CIR register byte 1 (Bits[15:8]) base address */
-#define CIR_BYTE1_ADDRESS         ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
-
-/* CIR register byte 2 (Bits[23:16]) base address */
-#define CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
-  * @{
-  */
-
-#define RCC_PLLSOURCE_HSI           RCC_CFGR_PLLSRC_HSI
-#define RCC_PLLSOURCE_HSE           RCC_CFGR_PLLSRC_HSE
- 
-#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) || \
-                                      ((__SOURCE__) == RCC_PLLSOURCE_HSE))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
-  * @{
-  */
-#define RCC_OSCILLATORTYPE_NONE            ((uint32_t)0x00000000)
-#define RCC_OSCILLATORTYPE_HSE             ((uint32_t)0x00000001)
-#define RCC_OSCILLATORTYPE_HSI             ((uint32_t)0x00000002)
-#define RCC_OSCILLATORTYPE_LSE             ((uint32_t)0x00000004)
-#define RCC_OSCILLATORTYPE_LSI             ((uint32_t)0x00000008)
-#define RCC_OSCILLATORTYPE_MSI             ((uint32_t)0x00000010)
-
-#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE)                           || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) || \
-                                               (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSE_Config RCC HSE Config
-  * @{
-  */
-#define RCC_HSE_OFF                      ((uint32_t)0x00000000)
-#define RCC_HSE_ON                       ((uint32_t)0x00000001)
-#define RCC_HSE_BYPASS                   ((uint32_t)0x00000005)
-
-#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
-                             ((__HSE__) == RCC_HSE_BYPASS))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSE_Config RCC LSE Config
-  * @{
-  */
-#define RCC_LSE_OFF                      ((uint32_t)0x00000000)
-#define RCC_LSE_ON                       ((uint32_t)0x00000001)
-#define RCC_LSE_BYPASS                   ((uint32_t)0x00000005)
-
-#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
-                             ((__LSE__) == RCC_LSE_BYPASS))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_HSI_Config RCC HSI Config
-  * @{
-  */
-#define RCC_HSI_OFF                      ((uint32_t)0x00000000)
-#define RCC_HSI_ON                       ((uint32_t)0x00000001)
-
-#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
-
-#define RCC_HSICALIBRATION_DEFAULT       ((uint32_t)0x10)   /* Default HSI calibration trimming value */
-
-#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
-  * @{
-  */
-
-#define RCC_MSIRANGE_0                   ((uint32_t)RCC_ICSCR_MSIRANGE_0) /*!< MSI = 65.536 KHz  */
-#define RCC_MSIRANGE_1                   ((uint32_t)RCC_ICSCR_MSIRANGE_1) /*!< MSI = 131.072 KHz */
-#define RCC_MSIRANGE_2                   ((uint32_t)RCC_ICSCR_MSIRANGE_2) /*!< MSI = 262.144 KHz */
-#define RCC_MSIRANGE_3                   ((uint32_t)RCC_ICSCR_MSIRANGE_3) /*!< MSI = 524.288 KHz */
-#define RCC_MSIRANGE_4                   ((uint32_t)RCC_ICSCR_MSIRANGE_4) /*!< MSI = 1.048 MHz   */
-#define RCC_MSIRANGE_5                   ((uint32_t)RCC_ICSCR_MSIRANGE_5) /*!< MSI = 2.097 MHz   */
-#define RCC_MSIRANGE_6                   ((uint32_t)RCC_ICSCR_MSIRANGE_6) /*!< MSI = 4.194 MHz   */
-
-#define IS_RCC_MSIRANGE(__RANGE__)  (((__RANGE__) == RCC_MSIRANGE_0) || \
-                                     ((__RANGE__) == RCC_MSIRANGE_1) || \
-                                     ((__RANGE__) == RCC_MSIRANGE_2) || \
-                                     ((__RANGE__) == RCC_MSIRANGE_3) || \
-                                     ((__RANGE__) == RCC_MSIRANGE_4) || \
-                                     ((__RANGE__) == RCC_MSIRANGE_5) || \
-                                     ((__RANGE__) == RCC_MSIRANGE_6))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_LSI_Config RCC LSI Config
-  * @{
-  */
-#define RCC_LSI_OFF                      ((uint32_t)0x00000000)
-#define RCC_LSI_ON                       ((uint32_t)0x00000001)
-
-#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
-/**
-  * @}
-  */
-
-    
-/** @defgroup RCC_MSI_Config RCC MSI Config
-  * @{
-  */
-#define RCC_MSI_OFF                      ((uint32_t)0x00000000)
-#define RCC_MSI_ON                       ((uint32_t)0x00000001)
-
-#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) || ((__MSI__) == RCC_MSI_ON))
-
-#define RCC_MSICALIBRATION_DEFAULT       ((uint32_t)0x00)   /* Default MSI calibration trimming value */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Config RCC PLL Config
-  * @{
-  */
-#define RCC_PLL_NONE                      ((uint32_t)0x00000000)
-#define RCC_PLL_OFF                       ((uint32_t)0x00000001)
-#define RCC_PLL_ON                        ((uint32_t)0x00000002)
-
-#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
-                             ((__PLL__) == RCC_PLL_ON))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Division_Factor RCC PLL Division Factor
-  * @{
-  */
-
-#define RCC_PLL_DIV2                    RCC_CFGR_PLLDIV2
-#define RCC_PLL_DIV3                    RCC_CFGR_PLLDIV3
-#define RCC_PLL_DIV4                    RCC_CFGR_PLLDIV4
-
-#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) || \
-                                 ((__DIV__) == RCC_PLL_DIV3) || ((__DIV__) == RCC_PLL_DIV4))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
-  * @{
-  */
-
-#define RCC_PLL_MUL3                    RCC_CFGR_PLLMUL3
-#define RCC_PLL_MUL4                    RCC_CFGR_PLLMUL4
-#define RCC_PLL_MUL6                    RCC_CFGR_PLLMUL6
-#define RCC_PLL_MUL8                    RCC_CFGR_PLLMUL8
-#define RCC_PLL_MUL12                   RCC_CFGR_PLLMUL12
-#define RCC_PLL_MUL16                   RCC_CFGR_PLLMUL16
-#define RCC_PLL_MUL24                   RCC_CFGR_PLLMUL24
-#define RCC_PLL_MUL32                   RCC_CFGR_PLLMUL32
-#define RCC_PLL_MUL48                   RCC_CFGR_PLLMUL48
-
-#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3)  || ((__MUL__) == RCC_PLL_MUL4)  || \
-                                 ((__MUL__) == RCC_PLL_MUL6)  || ((__MUL__) == RCC_PLL_MUL8)  || \
-                                 ((__MUL__) == RCC_PLL_MUL12) || ((__MUL__) == RCC_PLL_MUL16) || \
-                                 ((__MUL__) == RCC_PLL_MUL24) || ((__MUL__) == RCC_PLL_MUL32) || \
-                                 ((__MUL__) == RCC_PLL_MUL48))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_System_Clock_Type RCC System Clock Type
-  * @{
-  */
-#define RCC_CLOCKTYPE_SYSCLK             ((uint32_t)0x00000001)
-#define RCC_CLOCKTYPE_HCLK               ((uint32_t)0x00000002)
-#define RCC_CLOCKTYPE_PCLK1              ((uint32_t)0x00000004)
-#define RCC_CLOCKTYPE_PCLK2              ((uint32_t)0x00000008)
-
-#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_System_Clock_Source RCC System Clock Source
-  * @{
-  */
-#define RCC_SYSCLKSOURCE_MSI             ((uint32_t)RCC_CFGR_SW_MSI)
-#define RCC_SYSCLKSOURCE_HSI             ((uint32_t)RCC_CFGR_SW_HSI)
-#define RCC_SYSCLKSOURCE_HSE             ((uint32_t)RCC_CFGR_SW_HSE)
-#define RCC_SYSCLKSOURCE_PLLCLK          ((uint32_t)RCC_CFGR_SW_PLL)
-
-#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
-                                         ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
-  * @{
-  */
-#define RCC_SYSCLK_DIV1                  ((uint32_t)RCC_CFGR_HPRE_DIV1)
-#define RCC_SYSCLK_DIV2                  ((uint32_t)RCC_CFGR_HPRE_DIV2)
-#define RCC_SYSCLK_DIV4                  ((uint32_t)RCC_CFGR_HPRE_DIV4)
-#define RCC_SYSCLK_DIV8                  ((uint32_t)RCC_CFGR_HPRE_DIV8)
-#define RCC_SYSCLK_DIV16                 ((uint32_t)RCC_CFGR_HPRE_DIV16)
-#define RCC_SYSCLK_DIV64                 ((uint32_t)RCC_CFGR_HPRE_DIV64)
-#define RCC_SYSCLK_DIV128                ((uint32_t)RCC_CFGR_HPRE_DIV128)
-#define RCC_SYSCLK_DIV256                ((uint32_t)RCC_CFGR_HPRE_DIV256)
-#define RCC_SYSCLK_DIV512                ((uint32_t)RCC_CFGR_HPRE_DIV512)
-
-#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
-                               ((__HCLK__) == RCC_SYSCLK_DIV512))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
-  * @{
-  */
-#define RCC_HCLK_DIV1                    ((uint32_t)RCC_CFGR_PPRE1_DIV1)
-#define RCC_HCLK_DIV2                    ((uint32_t)RCC_CFGR_PPRE1_DIV2)
-#define RCC_HCLK_DIV4                    ((uint32_t)RCC_CFGR_PPRE1_DIV4)
-#define RCC_HCLK_DIV8                    ((uint32_t)RCC_CFGR_PPRE1_DIV8)
-#define RCC_HCLK_DIV16                   ((uint32_t)RCC_CFGR_PPRE1_DIV16)
-
-#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
-                               ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
-                               ((__PCLK__) == RCC_HCLK_DIV16))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_RTC_LCD_Clock_Source RCC RTC LCD Clock Source
-  * @{
-  */
-#define RCC_RTCCLKSOURCE_LSE             ((uint32_t)RCC_CSR_RTCSEL_LSE)
-#define RCC_RTCCLKSOURCE_LSI             ((uint32_t)RCC_CSR_RTCSEL_LSI)
-#define RCC_RTCCLKSOURCE_HSE_DIV2        ((uint32_t)RCC_CSR_RTCSEL_HSE)
-#define RCC_RTCCLKSOURCE_HSE_DIV4        ((uint32_t)(RCC_CR_RTCPRE_0 | RCC_CSR_RTCSEL_HSE))
-#define RCC_RTCCLKSOURCE_HSE_DIV8        ((uint32_t)(RCC_CR_RTCPRE_1 | RCC_CSR_RTCSEL_HSE))
-#define RCC_RTCCLKSOURCE_HSE_DIV16       ((uint32_t)(RCC_CR_RTCPRE | RCC_CSR_RTCSEL_HSE))
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_MCO_Index RCC MCO Index
-  * @{
-  */
-#define RCC_MCO1                         ((uint32_t)0x00000000)
-#define RCC_MCO                          RCC_MCO1
-
-#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
-  * @{
-  */
-#define RCC_MCODIV_1                    ((uint32_t)RCC_CFGR_MCO_DIV1)
-#define RCC_MCODIV_2                    ((uint32_t)RCC_CFGR_MCO_DIV2)
-#define RCC_MCODIV_4                    ((uint32_t)RCC_CFGR_MCO_DIV4)
-#define RCC_MCODIV_8                    ((uint32_t)RCC_CFGR_MCO_DIV8)
-#define RCC_MCODIV_16                   ((uint32_t)RCC_CFGR_MCO_DIV16)
-
-#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) || ((__DIV__) == RCC_MCODIV_2) || \
-                                ((__DIV__) == RCC_MCODIV_4) || ((__DIV__) == RCC_MCODIV_8) || \
-                                ((__DIV__) == RCC_MCODIV_16)) 
-/**
-  * @}
-  */ 
-
-/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
-  * @{
-  */
-#define RCC_MCO1SOURCE_NOCLOCK           ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
-#define RCC_MCO1SOURCE_SYSCLK            ((uint32_t)RCC_CFGR_MCO_SYSCLK)
-#define RCC_MCO1SOURCE_MSI               ((uint32_t)RCC_CFGR_MCO_MSI)
-#define RCC_MCO1SOURCE_HSI               ((uint32_t)RCC_CFGR_MCO_HSI)
-#define RCC_MCO1SOURCE_LSE               ((uint32_t)RCC_CFGR_MCO_LSE)
-#define RCC_MCO1SOURCE_LSI               ((uint32_t)RCC_CFGR_MCO_LSI)
-#define RCC_MCO1SOURCE_HSE               ((uint32_t)RCC_CFGR_MCO_HSE)
-#define RCC_MCO1SOURCE_PLLCLK            ((uint32_t)RCC_CFGR_MCO_PLL)
-
-#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_HSI)    || ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_LSI)    || ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
-                                    || ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) || ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Interrupt RCC Interrupt
-  * @{
-  */
-#define RCC_IT_LSIRDY                    ((uint8_t)RCC_CIR_LSIRDYF)
-#define RCC_IT_LSERDY                    ((uint8_t)RCC_CIR_LSERDYF)
-#define RCC_IT_HSIRDY                    ((uint8_t)RCC_CIR_HSIRDYF)
-#define RCC_IT_HSERDY                    ((uint8_t)RCC_CIR_HSERDYF)
-#define RCC_IT_PLLRDY                    ((uint8_t)RCC_CIR_PLLRDYF)
-#define RCC_IT_MSIRDY                    ((uint8_t)RCC_CIR_MSIRDYF)
-#define RCC_IT_LSECSS                    ((uint8_t)RCC_CIR_LSECSS)
-#define RCC_IT_CSS                       ((uint8_t)RCC_CIR_CSSF)
-/**
-  * @}
-  */  
-  
-/** @defgroup RCC_Flag RCC Flag
-  *        Elements values convention: 0XXYYYYYb
-  *           - YYYYY  : Flag position in the register
-  *           - XX  : Register index
-  *                 - 01: CR register
-  *                 - 11: CSR register
-  * @{
-  */
-#define CR_REG_INDEX                     ((uint8_t)1)    
-#define CSR_REG_INDEX                    ((uint8_t)3)
-
-/* Flags in the CR register */
-#define RCC_FLAG_HSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSIRDY)))
-#define RCC_FLAG_MSIRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_MSIRDY)))
-#define RCC_FLAG_HSERDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_HSERDY)))
-#define RCC_FLAG_PLLRDY                  ((uint8_t)((CR_REG_INDEX << 5) | POSITION_VAL(RCC_CR_PLLRDY)))
-
-/* Flags in the CSR register */
-#define RCC_FLAG_LSIRDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSIRDY)))
-#define RCC_FLAG_LSERDY                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSERDY)))
-#define RCC_FLAG_LSECSS                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LSECSSD)))
-#define RCC_FLAG_RMV                     ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_RMVF)))
-#define RCC_FLAG_OBLRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_OBLRSTF)))
-#define RCC_FLAG_PINRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PINRSTF)))
-#define RCC_FLAG_PORRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_PORRSTF)))
-#define RCC_FLAG_SFTRST                  ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_SFTRSTF)))
-#define RCC_FLAG_IWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_IWDGRSTF)))
-#define RCC_FLAG_WWDGRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_WWDGRSTF)))
-#define RCC_FLAG_LPWRRST                 ((uint8_t)((CSR_REG_INDEX << 5) | POSITION_VAL(RCC_CSR_LPWRRSTF)))
-
-#define RCC_FLAG_MASK                    ((uint8_t)0x1F)
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */   
-  
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup RCC_Exported_Macros RCC Exported Macros
-  * @{
-  */
-
-/** @defgroup RCC_Peripheral_Clock_Enable_Disable RCC Peripheral Clock Enable Disable
-  * @brief  Enable or disable the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.   
-  * @{
-  */
-#define __GPIOA_CLK_ENABLE()      (RCC->AHBENR |= (RCC_AHBENR_GPIOAEN))
-#define __GPIOB_CLK_ENABLE()      (RCC->AHBENR |= (RCC_AHBENR_GPIOBEN))
-#define __GPIOC_CLK_ENABLE()      (RCC->AHBENR |= (RCC_AHBENR_GPIOCEN))
-#define __GPIOD_CLK_ENABLE()      (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
-#define __GPIOH_CLK_ENABLE()      (RCC->AHBENR |= (RCC_AHBENR_GPIOHEN))
-
-#define __CRC_CLK_ENABLE()        (RCC->AHBENR |= (RCC_AHBENR_CRCEN))
-#define __FLITF_CLK_ENABLE()      (RCC->AHBENR |= (RCC_AHBENR_FLITFEN))
-#define __DMA1_CLK_ENABLE()       (RCC->AHBENR |= (RCC_AHBENR_DMA1EN))
-
-#define __GPIOA_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
-#define __GPIOB_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
-#define __GPIOC_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
-#define __GPIOD_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
-#define __GPIOH_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
-
-#define __CRC_CLK_DISABLE()       (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
-#define __FLITF_CLK_DISABLE()     (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
-#define __DMA1_CLK_DISABLE()      (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
-
-/** @brief  Enable or disable the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  */
-#define __TIM2_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
-#define __TIM3_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_TIM3EN))
-#define __TIM4_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_TIM4EN))
-#define __TIM6_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
-#define __TIM7_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
-#define __WWDG_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_WWDGEN))
-#define __SPI2_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
-#define __USART2_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
-#define __USART3_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
-#define __I2C1_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_I2C1EN))
-#define __I2C2_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
-#define __USB_CLK_ENABLE()        (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
-#define __PWR_CLK_ENABLE()        (RCC->APB1ENR |= (RCC_APB1ENR_PWREN))
-#define __DAC_CLK_ENABLE()        (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
-#define __COMP_CLK_ENABLE()       (RCC->APB1ENR |= (RCC_APB1ENR_COMPEN))
-
-#define __TIM2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
-#define __TIM3_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
-#define __TIM4_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
-#define __TIM6_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
-#define __TIM7_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
-#define __WWDG_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
-#define __SPI2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
-#define __USART2_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
-#define __USART3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
-#define __I2C1_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
-#define __I2C2_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __USB_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
-#define __PWR_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
-#define __DAC_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
-#define __COMP_CLK_DISABLE()      (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
-
-/** @brief  Enable or disable the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  */
-#define __SYSCFG_CLK_ENABLE()     (RCC->APB2ENR |= (RCC_APB2ENR_SYSCFGEN))
-#define __TIM9_CLK_ENABLE()       (RCC->APB2ENR |= (RCC_APB2ENR_TIM9EN))
-#define __TIM10_CLK_ENABLE()      (RCC->APB2ENR |= (RCC_APB2ENR_TIM10EN))
-#define __TIM11_CLK_ENABLE()      (RCC->APB2ENR |= (RCC_APB2ENR_TIM11EN))
-#define __ADC1_CLK_ENABLE()       (RCC->APB2ENR |= (RCC_APB2ENR_ADC1EN))
-#define __SPI1_CLK_ENABLE()       (RCC->APB2ENR |= (RCC_APB2ENR_SPI1EN))
-#define __USART1_CLK_ENABLE()     (RCC->APB2ENR |= (RCC_APB2ENR_USART1EN))
-
-#define __SYSCFG_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
-#define __TIM9_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
-#define __TIM10_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
-#define __TIM11_CLK_DISABLE()     (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
-#define __ADC1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
-#define __SPI1_CLK_DISABLE()      (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
-#define __USART1_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
-
-/**
-  * @}
-  */
-  
-/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
-  * @brief  Force or release AHB peripheral reset.
-  * @{
-  */  
-#define __AHB_FORCE_RESET()       (RCC->AHBRSTR = 0xFFFFFFFF)
-#define __GPIOA_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOARST))
-#define __GPIOB_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOBRST))
-#define __GPIOC_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOCRST))
-#define __GPIOD_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
-#define __GPIOH_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOHRST))
-
-#define __CRC_FORCE_RESET()       (RCC->AHBRSTR |= (RCC_AHBRSTR_CRCRST))
-#define __FLITF_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_FLITFRST))
-#define __DMA1_FORCE_RESET()      (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA1RST))
-
-#define __AHB_RELEASE_RESET()     (RCC->AHBRSTR = 0x00)
-#define __GPIOA_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
-#define __GPIOB_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
-#define __GPIOC_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
-#define __GPIOD_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
-#define __GPIOH_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
-
-#define __CRC_RELEASE_RESET()     (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
-#define __FLITF_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
-#define __DMA1_RELEASE_RESET()    (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
-
-/** @brief  Force or release APB1 peripheral reset.
-  */
-#define __APB1_FORCE_RESET()      (RCC->APB1RSTR = 0xFFFFFFFF)  
-#define __TIM2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
-#define __TIM3_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
-#define __TIM4_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM4RST))
-#define __TIM6_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
-#define __TIM7_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
-#define __WWDG_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
-#define __SPI2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
-#define __USART2_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
-#define __USART3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
-#define __I2C1_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
-#define __I2C2_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
-#define __USB_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
-#define __PWR_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __DAC_FORCE_RESET()       (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
-#define __COMP_FORCE_RESET()      (RCC->APB1RSTR |= (RCC_APB1RSTR_COMPRST))
-
-#define __APB1_RELEASE_RESET()    (RCC->APB1RSTR = 0x00) 
-#define __TIM2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
-#define __TIM3_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
-#define __TIM4_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
-#define __TIM6_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
-#define __TIM7_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
-#define __WWDG_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
-#define __SPI2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
-#define __USART2_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
-#define __USART3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
-#define __I2C1_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
-#define __I2C2_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
-#define __USB_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
-#define __PWR_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
-#define __DAC_RELEASE_RESET()     (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
-#define __COMP_RELEASE_RESET()    (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
-
-/** @brief  Force or release APB2 peripheral reset.
-  */
-#define __APB2_FORCE_RESET()      (RCC->APB2RSTR = 0xFFFFFFFF)  
-#define __SYSCFG_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SYSCFGRST))
-#define __TIM9_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM9RST))
-#define __TIM10_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM10RST))
-#define __TIM11_FORCE_RESET()     (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM11RST))
-#define __ADC1_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
-#define __SPI1_FORCE_RESET()      (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
-#define __USART1_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
-
-#define __APB2_RELEASE_RESET()    (RCC->APB2RSTR = 0x00)
-#define __SYSCFG_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
-#define __TIM9_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
-#define __TIM10_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
-#define __TIM11_RELEASE_RESET()   (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
-#define __ADC1_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
-#define __SPI1_RELEASE_RESET()    (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
-#define __USART1_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
-
-/**
-  * @}
-  */
-
-/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#define __GPIOA_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOALPEN))
-#define __GPIOB_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOBLPEN))
-#define __GPIOC_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOCLPEN))
-#define __GPIOD_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIODLPEN))
-#define __GPIOH_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOHLPEN))
-
-#define __CRC_CLK_SLEEP_ENABLE()      (RCC->AHBLPENR |= (RCC_AHBLPENR_CRCLPEN))
-#define __FLITF_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_FLITFLPEN))
-#define __DMA1_CLK_SLEEP_ENABLE()     (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA1LPEN))
-
-#define __GPIOA_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
-#define __GPIOB_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
-#define __GPIOC_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
-#define __GPIOD_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
-#define __GPIOH_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
-
-#define __CRC_CLK_SLEEP_DISABLE()     (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
-#define __FLITF_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
-#define __DMA1_CLK_SLEEP_DISABLE()    (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
-
-/** @brief  Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *           power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __TIM2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM2LPEN))
-#define __TIM3_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM3LPEN))
-#define __TIM4_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM4LPEN))
-#define __TIM6_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM6LPEN))
-#define __TIM7_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM7LPEN))
-#define __WWDG_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_WWDGLPEN))
-#define __SPI2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI2LPEN))
-#define __USART2_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_USART2LPEN))
-#define __USART3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_USART3LPEN))
-#define __I2C1_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C1LPEN))
-#define __I2C2_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_I2C2LPEN))
-#define __USB_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_USBLPEN))
-#define __PWR_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_PWRLPEN))
-#define __DAC_CLK_SLEEP_ENABLE()      (RCC->APB1LPENR |= (RCC_APB1LPENR_DACLPEN))
-#define __COMP_CLK_SLEEP_ENABLE()     (RCC->APB1LPENR |= (RCC_APB1LPENR_COMPLPEN))
-
-#define __TIM2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
-#define __TIM3_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
-#define __TIM4_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
-#define __TIM6_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
-#define __TIM7_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
-#define __WWDG_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
-#define __SPI2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
-#define __USART2_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
-#define __USART3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
-#define __I2C1_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
-#define __I2C2_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
-#define __USB_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
-#define __PWR_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
-#define __DAC_CLK_SLEEP_DISABLE()     (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
-#define __COMP_CLK_SLEEP_DISABLE()    (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
-
-/** @brief  Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *           power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#define __SYSCFG_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SYSCFGLPEN))
-#define __TIM9_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM9LPEN))
-#define __TIM10_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM10LPEN))
-#define __TIM11_CLK_SLEEP_ENABLE()    (RCC->APB2LPENR |= (RCC_APB2LPENR_TIM11LPEN))
-#define __ADC1_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_ADC1LPEN))
-#define __SPI1_CLK_SLEEP_ENABLE()     (RCC->APB2LPENR |= (RCC_APB2LPENR_SPI1LPEN))
-#define __USART1_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_USART1LPEN))
-
-#define __SYSCFG_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
-#define __TIM9_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
-#define __TIM10_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
-#define __TIM11_CLK_SLEEP_DISABLE()   (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
-#define __ADC1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
-#define __SPI1_CLK_SLEEP_DISABLE()    (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
-#define __USART1_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
-
-/**
-  * @}
-  */
-
-/** @brief  Macros to enable or disable the Internal High Speed oscillator (HSI).
-  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
-  * @note   HSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the HSI.  
-  * @note   After enabling the HSI, the application software should wait on HSIRDY
-  *         flag to be set indicating that HSI clock is stable and can be used as
-  *         system clock source.  
-  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
-  *         clock cycles.  
-  */
-#define __HAL_RCC_HSI_ENABLE()  (*(__IO uint32_t *) CR_HSION_BB = ENABLE)
-#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) CR_HSION_BB = DISABLE)
-
-/** @brief Macros to enable or disable the External High Speed oscillator (HSE).
-  * @param  __HSE_STATE__: specifies the new state of the HSE.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
-  *                              6 HSE oscillator clock cycles.
-  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
-  *            @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
-  */
-#define __HAL_RCC_HSE_CONFIG(__HSE_STATE__) (*(__IO uint8_t *) CR_BYTE2_ADDRESS = (__HSE_STATE__))
-
-/** @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
-  * @note   The MSI is stopped by hardware when entering STOP and STANDBY modes.
-  *         It is used (enabled by hardware) as system clock source after startup
-  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
-  *         of the HSE used directly or indirectly as system clock (if the Clock
-  *         Security System CSS is enabled).             
-  * @note   MSI can not be stopped if it is used as system clock source. In this case,
-  *         you have to select another source of the system clock then stop the MSI.  
-  * @note   After enabling the MSI, the application software should wait on MSIRDY
-  *         flag to be set indicating that MSI clock is stable and can be used as
-  *         system clock source.  
-  * @note   When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
-  *         clock cycles.  
-  */
-#define __HAL_RCC_MSI_ENABLE()  (*(__IO uint32_t *) CR_MSION_BB = ENABLE)
-#define __HAL_RCC_MSI_DISABLE() (*(__IO uint32_t *) CR_MSION_BB = DISABLE)
-                                       
-/** @brief  macro to adjust the Internal High Speed oscillator (HSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal HSI RC.
-  * @param  _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
-  *         (default is RCC_HSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0x1F.
-  */   
-#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
-          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM)))
-
-/** @brief  macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
-  * @note   The calibration is used to compensate for the variations in voltage
-  *         and temperature that influence the frequency of the internal MSI RC.
-  * @param  _MSICALIBRATIONVALUE_: specifies the calibration trimming value.
-  *         (default is RCC_MSICALIBRATION_DEFAULT).
-  *         This parameter must be a number between 0 and 0x1F.
-  */   
-#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
-          (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM)))
-
-/* @brief  Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
-  * @note     After restart from Reset or wakeup from STANDBY, the MSI clock is 
-  *           around 2.097 MHz. The MSI clock does not change after wake-up from
-  *           STOP mode.
-  * @note    The MSI clock range can be modified on the fly.     
-  * @param  _MSIRANGEVALUE_: specifies the MSI Clock range.
-  *   This parameter must be one of the following values:
-  *     @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
-  *     @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
-  *     @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
-  *     @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
-  *     @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
-  *     @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
-  *     @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
-  */   
-#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
-
-                                       
-/** @brief Macros to enable or disable  the Internal Low Speed oscillator (LSI).
-  * @note   After enabling the LSI, the application software should wait on 
-  *         LSIRDY flag to be set indicating that LSI clock is stable and can
-  *         be used to clock the IWDG and/or the RTC.
-  * @note   LSI can not be disabled if the IWDG is running.  
-  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
-  *         clock cycles. 
-  */
-#define __HAL_RCC_LSI_ENABLE()  (*(__IO uint32_t *) CSR_LSION_BB = ENABLE)
-#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) CSR_LSION_BB = DISABLE)
-                                       
-/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
-  */
-#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
-                                       do{ \
-                                         if ((__LSE_STATE__) == RCC_LSE_OFF) \
-                                         { \
-                                           *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \
-                                           *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \
-                                         } \
-                                         else if ((__LSE_STATE__) == RCC_LSE_ON) \
-                                         { \
-                                           *(__IO uint32_t *) CSR_LSEBYP_BB = DISABLE; \
-                                           *(__IO uint32_t *) CSR_LSEON_BB = ENABLE; \
-                                         } \
-                                         else \
-                                         { \
-                                           *(__IO uint32_t *) CSR_LSEON_BB = DISABLE; \
-                                           *(__IO uint32_t *) CSR_LSEBYP_BB = ENABLE; \
-                                         } \
-                                       }while(0)
-                                       
-/** @brief Macros to enable or disable the the RTC clock.
-  * @note   These macros must be used only after the RTC clock source was selected.
-  */
-#define __HAL_RCC_RTC_ENABLE()          (*(__IO uint32_t *) CSR_RTCEN_BB = ENABLE)
-#define __HAL_RCC_RTC_DISABLE()         (*(__IO uint32_t *) CSR_RTCEN_BB = DISABLE)
-
-/** @brief  Macros to force or release the Backup domain reset.
-  * @note   This function resets the RTC peripheral (including the backup registers)
-  *         and the RTC clock source selection in RCC_CSR register.
-  * @note   The BKPSRAM is not affected by this reset.   
-  */
-#define __HAL_RCC_BACKUPRESET_FORCE()   (*(__IO uint32_t *) CSR_RTCRST_BB = ENABLE)
-#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) CSR_RTCRST_BB = DISABLE)
-
-
-/** @brief Macro to configures the RTC clock (RTCCLK).
-  * @note   As the RTC clock configuration bits are in the Backup domain and write
-  *         access is denied to this domain after reset, you have to enable write
-  *         access using the Power Backup Access macro before to configure
-  *         the RTC clock source (to be done once after reset).    
-  * @note   Once the RTC clock is configured it can't be changed unless the  
-  *         Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
-  *         a Power On Reset (POR).
-  * @note   RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
-  *
-  * @param  __RTC_CLKSOURCE__: specifies the RTC clock source.
-  *          This parameter can be one of the following values:
-  *             @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
-  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
-  *         work in STOP and STANDBY modes, and can be used as wakeup source.
-  *         However, when the HSE clock is used as RTC clock source, the RTC
-  *         cannot be used in STOP and STANDBY modes.    
-  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
-  *         RTC clock source).
-  */
-#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
-            if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE)          \
-            {                                                                             \
-              MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE));  \
-            }                                                                             \
-          } while (0)
-
-#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
-                                      __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__);      \
-                                      RCC->CSR |= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
-                                    } while (0)
-                                                   
-/** @brief macros to get the RTC clock source.
-  */
-#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
-
-/** @brief Macros to enable or disable the main PLL.
-  * @note   After enabling the main PLL, the application software should wait on 
-  *         PLLRDY flag to be set indicating that PLL clock is stable and can
-  *         be used as system clock source.
-  * @note   The main PLL can not be disabled if it is used as system clock source
-  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
-  */
-#define __HAL_RCC_PLL_ENABLE()          (*(__IO uint32_t *) CR_PLLON_BB = ENABLE)
-#define __HAL_RCC_PLL_DISABLE()         (*(__IO uint32_t *) CR_PLLON_BB = DISABLE)
-
-/** @brief macros to configure the main PLL clock source, multiplication and division factors.
-  * @note   This function must be used only when the main PLL is disabled.
-  *  
-  * @param  __RCC_PLLSOURCE__: specifies the PLL entry clock source.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
-  *            @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
-  * @param  __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
-  *          This parameter can be one of the following values:
-  *             @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3
-  *             @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
-  *             @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
-  *             @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
-  *             @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12
-  *             @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16
-  *             @arg RCC_PLL_MUL24: PLLVCO = PLL clock entry x 24
-  *             @arg RCC_PLL_MUL32: PLLVCO = PLL clock entry x 32
-  *             @arg RCC_PLL_MUL48: PLLVCO = PLL clock entry x 48
-  * @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
-  *          Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
-  *          in Range 3.
-  *   
-  * @param  __PLLDIV__: specifies the division factor for PLL VCO input clock
-  *          This parameter can be one of the following values:
-  *             @arg RCC_PLL_DIV2: PLL clock output = PLLVCO / 2
-  *             @arg RCC_PLL_DIV3: PLL clock output = PLLVCO / 3
-  *             @arg RCC_PLL_DIV4: PLL clock output = PLLVCO / 4
-  *  
-  */
-#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
-          MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC|RCC_CFGR_PLLMUL|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) | (__PLLMUL__) | (__PLLDIV__)))
-
-/** @brief  Macro to get the clock source used as system clock.
-  * @retval The clock source used as system clock. The returned value can be one
-  *         of the following:
-  *             @arg RCC_CFGR_SWS_MSI: MSI used as system clock
-  *             @arg RCC_CFGR_SWS_HSI: HSI used as system clock
-  *             @arg RCC_CFGR_SWS_HSE: HSE used as system clock
-  *             @arg RCC_CFGR_SWS_PLL: PLL used as system clock
-  */     
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
-                              
-/** @brief macros to manage the specified RCC Flags and interrupts.
-  */
-
-/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
-  *        the selected interrupts.).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt
-  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
-  *            @arg RCC_IT_MSIRDY: MSI ready interrupt
-  *            @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device)
-  */
-#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable 
-  *        the selected interrupts).
-  * @param  __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
-  *          This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt
-  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
-  *            @arg RCC_IT_MSIRDY: MSI ready interrupt
-  *            @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device)
-  */
-#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
-
-/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
-  *        bits to clear the selected interrupt pending bits.
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *          This parameter can be any combination of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_MSIRDY: MSI ready interrupt.
-  *            @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device)
-  *            @arg RCC_IT_CSS: Clock Security System interrupt
-  */
-#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
-
-/** @brief Check the RCC's interrupt has occurred or not.
-  * @param  __INTERRUPT__: specifies the RCC interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_IT_LSIRDY: LSI ready interrupt.
-  *            @arg RCC_IT_LSERDY: LSE ready interrupt.
-  *            @arg RCC_IT_HSIRDY: HSI ready interrupt.
-  *            @arg RCC_IT_HSERDY: HSE ready interrupt.
-  *            @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
-  *            @arg RCC_IT_MSIRDY: MSI ready interrupt.
-  *            @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB || STM32L151xB || STM32L152xB device)
-  *            @arg RCC_IT_CSS: Clock Security System interrupt
-  * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
-  * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
-  */
-#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
-
-/** @brief  Check RCC flag is set or not.
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be one of the following values:
-  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
-  *            @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready.
-  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
-  *            @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
-  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
-  *            @arg RCC_FLAG_LSECSS: CSS on LSE failure Detection (*)
-  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
-  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
-  *            @arg RCC_FLAG_PINRST: Pin reset.
-  *            @arg RCC_FLAG_PORRST: POR/PDR reset.
-  *            @arg RCC_FLAG_SFTRST: Software reset.
-  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
-  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
-  *            @arg RCC_FLAG_LPWRRST: Low Power reset.
-  * @note (*) This bit is available in high and medium+ density devices only.
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))   
-
-     
-/** @brief  Get oscillator clock selected as PLL input clock
-  * @retval The clock source used for PLL entry. The returned value can be one
-  *         of the following:
-  *             @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL input clock
-  *             @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
-  */
-#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
-
-/**
-  * @}
-  */   
-
-/* Include RCC HAL Extension module */
-#include "stm32l1xx_hal_rcc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCC_Private_Functions
-  * @{
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group1
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-void              HAL_RCC_DeInit(void);
-HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
-HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t FLatency);
-
-/**
-  * @}
-  */
-
-/** @addtogroup RCC_Exported_Functions_Group2
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-void              HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
-void              HAL_RCC_EnableCSS(void);
-void              HAL_RCC_DisableCSS(void);
-uint32_t          HAL_RCC_GetSysClockFreq(void);
-uint32_t          HAL_RCC_GetHCLKFreq(void);
-uint32_t          HAL_RCC_GetPCLK1Freq(void);
-uint32_t          HAL_RCC_GetPCLK2Freq(void);
-void              HAL_RCC_GetOscConfig(RCC_OscInitTypeDef  *RCC_OscInitStruct);
-void              HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef  *RCC_ClkInitStruct, uint32_t *pFLatency);
-
-/* CSS NMI IRQ handler */
-void              HAL_RCC_NMI_IRQHandler(void);
-
-/* User Callbacks in non blocking mode (IT mode) */ 
-void              HAL_RCC_CCSCallback(void);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_RCC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
-

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,277 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rcc_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Extended RCC HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities RCC extension peripheral:
-  *           + Extended Peripheral Control functions
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RCCEx RCCEx
-  * @brief RCC Extension HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RCC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup RCCEx_Private_Functions RCCEx Exported Functions
-  * @{
-  */
-
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions 
- *  @brief  Extended Peripheral Control functions  
- *
-@verbatim   
- ===============================================================================
-                ##### Extended Peripheral Control functions  #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the RCC Clocks 
-    frequencies.
-    [..] 
-    (@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
-        select the RTC clock source; in this case the Backup domain will be reset in  
-        order to modify the RTC Clock source, as consequence RTC registers (including 
-        the backup registers) and RCC_BDCR register are set to their reset values.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the RCC extended peripherals clocks according to the specified parameters in the
-  *         RCC_PeriphCLKInitTypeDef.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
-  *         contains the configuration information for the Extended Peripherals clocks(RTC/LCD clock).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t tickstart = 0;   
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-  
-  /*------------------------------- RTC/LCD Configuration ------------------------*/ 
-  if ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == RCC_PERIPHCLK_RTC) 
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-    || (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LCD) == RCC_PERIPHCLK_LCD)
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-    )
-    {
-    /* Enable Power Controller clock */
-    __PWR_CLK_ENABLE();
-    
-    /* Enable write access to Backup domain */
-    SET_BIT(PWR->CR, PWR_CR_DBP);
-
-    /* Wait for Backup domain Write protection disable */
-    tickstart = HAL_GetTick();
-    
-    while((PWR->CR & PWR_CR_DBP) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) > DBP_TIMEOUT_VALUE)
-      {
-        return HAL_TIMEOUT;
-      }      
-    }
-    
-    tmpreg = (RCC->CSR & RCC_CSR_RTCSEL);
-    /* Reset the Backup domain only if the RTC Clock source selection is modified */ 
-    if((tmpreg != (PeriphClkInit->RTCClockSelection & RCC_CSR_RTCSEL))
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-    || (tmpreg != (PeriphClkInit->LCDClockSelection & RCC_CSR_RTCSEL))
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-    )
-    {
-      /* Store the content of CSR register before the reset of Backup Domain */
-      tmpreg = (RCC->CSR & ~(RCC_CSR_RTCSEL));
-      /* RTC Clock selection can be changed only if the Backup Domain is reset */
-      __HAL_RCC_BACKUPRESET_FORCE();
-      __HAL_RCC_BACKUPRESET_RELEASE();
-      /* Restore the Content of CSR register */
-      RCC->CSR = tmpreg;
-    }
-
-    /* If LSE is selected as RTC clock source, wait for LSE reactivation */
-    if ((PeriphClkInit->RTCClockSelection == RCC_RTCCLKSOURCE_LSE)
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-    || (PeriphClkInit->LCDClockSelection == RCC_RTCCLKSOURCE_LSE)
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-      )
-    {
-      /* Get timeout */   
-      tickstart = HAL_GetTick();
-      
-      /* Wait till LSE is ready */  
-      while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
-      {
-        if((HAL_GetTick() - tickstart ) > LSE_TIMEOUT_VALUE)
-        {
-          return HAL_TIMEOUT;
-        }      
-      }  
-    }
-
-    __HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get the PeriphClkInit according to the internal
-  * RCC configuration registers.
-  * @param  PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that 
-  *         returns the configuration information for the Extended Peripherals clocks(RTC/LCD clocks).
-  * @retval None
-  */
-void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit)
-{
-  uint32_t srcclk = 0;
-  
-  /* Set all possible values for the extended clock type parameter------------*/
-  PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_RTC;
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-  PeriphClkInit->PeriphClockSelection |= RCC_PERIPHCLK_LCD;
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-
-  /* Get the RTC/LCD configuration -----------------------------------------------*/
-  srcclk = __HAL_RCC_GET_RTC_SOURCE();
-  if (srcclk != RCC_RTCCLKSOURCE_HSE_DIV2)
-  {
-    /* Source clock is LSE or LSI*/
-    PeriphClkInit->RTCClockSelection = srcclk;
-  }
-  else
-  {
-    /* Source clock is HSE. Need to get the prescaler value*/
-    PeriphClkInit->RTCClockSelection = srcclk | (READ_BIT(RCC->CR, RCC_CR_RTCPRE));
-  }
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-  PeriphClkInit->LCDClockSelection = PeriphClkInit->RTCClockSelection;
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-/**
-  * @brief  Enables the LSE Clock Security System.
-  * @note   If a failure is detected on the external 32 kHz oscillator, the LSE clock is no longer supplied
-  *         to the RTC but no hardware action is made to the registers.
-  *         In Standby mode a wakeup is generated. In other modes an interrupt can be sent to wakeup
-  *         the software (see Section 5.3.4: Clock interrupt register (RCC_CIR) on page 104).
-  *         The software MUST then disable the LSECSSON bit, stop the defective 32 kHz oscillator
-  *         (disabling LSEON), and can change the RTC clock source (no clock or LSI or HSE, with
-  *         RTCSEL), or take any required action to secure the application.  
-  * @note   LSE CSS available only for high density and medium+ devices
-  * @retval None
-  */
-void HAL_RCCEx_EnableLSECSS(void)
-{
-  *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)ENABLE;
-}
-
-/**
-  * @brief  Disables the LSE Clock Security System.
-  * @note   Once enabled this bit cannot be disabled, except after an LSE failure detection 
-  *         (LSECSSD=1). In that case the software MUST disable the LSECSSON bit.
-  *         Reset by power on reset and RTC software reset (RTCRST bit).
-  * @note   LSE CSS available only for high density and medium+ devices
-  * @retval None
-  */
-void HAL_RCCEx_DisableLSECSS(void)
-{
-  *(__IO uint32_t *) CSR_LSECSSON_BB = (uint32_t)DISABLE;
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RCC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rcc_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,573 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rcc_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of RCC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_RCC_EX_H
-#define __STM32L1xx_HAL_RCC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RCCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-
-/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  RCC extended clocks structure definition  
-  */
-typedef struct
-{
-  uint32_t PeriphClockSelection;                /*!< The Extended Clock to be configured.
-                                      This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
-
-  uint32_t RTCClockSelection;         /*!< specifies the RTC clock source.
-                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-
-  uint32_t LCDClockSelection;         /*!< specifies the LCD clock source.
-                                       This parameter can be a value of @ref RCC_RTC_LCD_Clock_Source */
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-} RCC_PeriphCLKInitTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
-  * @{
-  */
-
-/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
-  * @{
-  */
-#define RCC_PERIPHCLK_RTC           ((uint32_t)0x00000001)
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-
-#define RCC_PERIPHCLK_LCD           ((uint32_t)0x00000002)
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((RCC_PERIPHCLK_RTC <= (__CLK__)) && ((__CLK__) <= RCC_PERIPHCLK_LCD))
-
-#else /* Not LCD LINE */
-
-#define IS_RCC_PERIPHCLOCK(__CLK__) ((__CLK__) == RCC_PERIPHCLK_RTC)
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-/* Alias word address of LSECSSON bit */
-#define LSECSSON_BITNUMBER      POSITION_VAL(RCC_CSR_LSECSSON)
-#define CSR_LSECSSON_BB         ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSECSSON_BITNUMBER * 4)))
-
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
- * @{
- */
-
-/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
-  * @brief  Enables or disables the AHB1 peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.   
-  * @{
-  */
-#if defined (STM32L151xB) || defined (STM32L152xB) || \
-    defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-#define __GPIOE_CLK_ENABLE()    (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
-#define __GPIOE_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
-
-#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __GPIOF_CLK_ENABLE()    (RCC->AHBENR |= (RCC_AHBENR_GPIOFEN))
-#define __GPIOG_CLK_ENABLE()    (RCC->AHBENR |= (RCC_AHBENR_GPIOGEN))
-
-#define __GPIOF_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
-#define __GPIOG_CLK_DISABLE()   (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-#define __DMA2_CLK_ENABLE()     (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
-#define __DMA2_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-
-#define __CRYP_CLK_ENABLE()     (RCC->AHBENR |= (RCC_AHBENR_AESEN))
-#define __CRYP_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_AESEN))
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-  
-#define __FSMC_CLK_ENABLE()     (RCC->AHBENR |= (RCC_AHBENR_FSMCEN))
-#define __FSMC_CLK_DISABLE()    (RCC->AHBENR &= ~(RCC_AHBENR_FSMCEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-    
-#define __LCD_CLK_ENABLE()        (RCC->APB1ENR |= (RCC_APB1ENR_LCDEN))
-#define __LCD_CLK_DISABLE()       (RCC->APB1ENR &= ~(RCC_APB1ENR_LCDEN))
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-
-/** @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it. 
-  */
-#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __TIM5_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_TIM5EN))
-#define __TIM5_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __SPI3_CLK_ENABLE()     (RCC->APB1ENR |= (RCC_APB1ENR_SPI3EN))
-#define __SPI3_CLK_DISABLE()    (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __UART4_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_UART4EN))
-#define __UART5_CLK_ENABLE()    (RCC->APB1ENR |= (RCC_APB1ENR_UART5EN))
-
-#define __UART4_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
-#define __UART5_CLK_DISABLE()   (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-
-#define __OPAMP_CLK_ENABLE()      __COMP_CLK_ENABLE()   /* Peripherals COMP and OPAMP share the same clock domain */
-#define __OPAMP_CLK_DISABLE()     __COMP_CLK_DISABLE()  /* Peripherals COMP and OPAMP share the same clock domain */
-      
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-      
-/** @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
-  * @note   After reset, the peripheral clock (used for registers read/write access)
-  *         is disabled and the application software has to enable this clock before 
-  *         using it.
-  */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-#define __SDIO_CLK_ENABLE()     (RCC->APB2ENR |= (RCC_APB2ENR_SDIOEN))
-#define __SDIO_CLK_DISABLE()    (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-    * @}
-    */
-  
-
-/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
-  * @brief  Forces or releases AHB peripheral reset.
-  * @{
-  */  
-#if defined (STM32L151xB) || defined (STM32L152xB) || \
-    defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-#define __GPIOE_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
-#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
-
-#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __GPIOF_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOFRST))
-#define __GPIOG_FORCE_RESET()   (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOGRST))
-
-#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
-#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-#define __DMA2_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_DMA2RST))
-#define __DMA2_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA2RST))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-
-#define __CRYP_FORCE_RESET()     (RCC->AHBRSTR |= (RCC_AHBRSTR_AESRST))
-#define __CRYP_RELEASE_RESET()   (RCC->AHBRSTR &= ~(RCC_AHBRSTR_AESRST))
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-  
-#define __FSMC_FORCE_RESET()    (RCC->AHBRSTR |= (RCC_AHBRSTR_FSMCRST))
-#define __FSMC_RELEASE_RESET()  (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FSMCRST))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-    
-#define __LCD_FORCE_RESET()     (RCC->APB1RSTR |= (RCC_APB1RSTR_LCDRST))
-#define __LCD_RELEASE_RESET()   (RCC->APB1RSTR &= ~(RCC_APB1RSTR_LCDRST))
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-
-/** @brief  Forces or releases APB1 peripheral reset.
-  */
-#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-      defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-      defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __TIM5_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
-#define __TIM5_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __SPI3_FORCE_RESET()    (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI3RST))
-#define __SPI3_RELEASE_RESET()  (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __UART4_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART4RST))
-#define __UART5_FORCE_RESET()   (RCC->APB1RSTR |= (RCC_APB1RSTR_UART5RST))
-
-#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
-#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) || defined (STM32L162xC) || defined (STM32L152xC) || defined (STM32L151xC)
-
-#define __OPAMP_FORCE_RESET()     __COMP_FORCE_RESET()   /* Peripherals COMP and OPAMP share the same clock domain */
-#define __OPAMP_RELEASE_RESET()   __COMP_RELEASE_RESET() /* Peripherals COMP and OPAMP share the same clock domain */
-      
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE || STM32L162xC || STM32L152xC || STM32L151xC */
-      
-/** @brief  Forces or releases APB2 peripheral reset.
-  */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-#define __SDIO_FORCE_RESET()    (RCC->APB2RSTR |= (RCC_APB2RSTR_SDIORST))
-#define __SDIO_RELEASE_RESET()  (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-/** @defgroup RCCEx_Peripheral_Clock_Sleep_Enable_Disable RCCEx Peripheral Clock Sleep Enable Disable
-  * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *         power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  * @{
-  */
-#if defined (STM32L151xB) || defined (STM32L152xB) || \
-    defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-#define __GPIOE_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOELPEN))
-#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOELPEN))
-
-#endif /* STM32L151xB || STM32L152xB || ... || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __GPIOF_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOFLPEN))
-#define __GPIOG_CLK_SLEEP_ENABLE()  (RCC->AHBLPENR |= (RCC_AHBLPENR_GPIOGLPEN))
-
-#define __GPIOF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOFLPEN))
-#define __GPIOG_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOGLPEN))
-
-#endif /* STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-    
-#define __DMA2_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_DMA2LPEN))
-#define __DMA2_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA2LPEN))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L162xC) || defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L162xE)
-
-#define __CRYP_CLK_SLEEP_ENABLE()    (RCC->AHBLPENR |= (RCC_AHBLPENR_AESLPEN))
-#define __CRYP_CLK_SLEEP_DISABLE()   (RCC->AHBLPENR &= ~(RCC_AHBLPENR_AESLPEN))
-
-#endif /* STM32L162xC || STM32L162xCA || STM32L162xD || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-  
-#define __FSMC_CLK_SLEEP_ENABLE()   (RCC->AHBLPENR |= (RCC_AHBLPENR_FSMCLPEN))
-#define __FSMC_CLK_SLEEP_DISABLE()  (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FSMCLPEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-    
-#define __LCD_CLK_SLEEP_ENABLE()    (RCC->APB1LPENR |= (RCC_APB1LPENR_LCDLPEN))
-#define __LCD_CLK_SLEEP_DISABLE()   (RCC->APB1LPENR &= ~(RCC_APB1LPENR_LCDLPEN))
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-
-/** @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *           power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#if defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __TIM5_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_TIM5LPEN))
-#define __TIM5_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
-
-#endif /* STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __SPI3_CLK_SLEEP_ENABLE()   (RCC->APB1LPENR |= (RCC_APB1LPENR_SPI3LPEN))
-#define __SPI3_CLK_SLEEP_DISABLE()  (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
-
-#endif /* STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-#define __UART4_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART4LPEN))
-#define __UART5_CLK_SLEEP_ENABLE()  (RCC->APB1LPENR |= (RCC_APB1LPENR_UART5LPEN))
-
-#define __UART4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART4LPEN))
-#define __UART5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_UART5LPEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/** @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
-  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
-  *           power consumption.
-  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
-  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
-  */
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-#define __SDIO_CLK_SLEEP_ENABLE()   (RCC->APB2LPENR |= (RCC_APB2LPENR_SDIOLPEN))
-#define __SDIO_CLK_SLEEP_DISABLE()  (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */
-
-#if defined (STM32L100xB) || defined (STM32L100xBA) || defined (STM32L100xC) ||\
-    defined(STM32L152xB) || defined(STM32L152xBA) || defined(STM32L152xC) || \
-    defined(STM32L162xC) || defined(STM32L152xCA) || defined(STM32L152xD) || \
-    defined(STM32L162xCA) || defined(STM32L162xD) || defined(STM32L152xE) || \
-    defined(STM32L162xE)
-    
-
-/** @brief Macro to configures LCD clock (LCDCLK).
-  *  @note   LCD and RTC use the same configuration
-  *  @note   LCD can however be used in the Stop low power mode if the LSE or LSI is used as the
-  *   LCD clock source.
-  *    
-  *  @param  __LCD_CLKSOURCE__: specifies the LCD clock source.
-  *          This parameter can be one of the following values:
-  *             @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
-  *             @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
-  */
-#define __HAL_RCC_LCD_CONFIG(__LCD_CLKSOURCE__) __HAL_RCC_RTC_CONFIG(__LCD_CLKSOURCE__)
-
-/** @brief macros to get the LCD clock source.
-  */
-#define __HAL_RCC_GET_LCD_SOURCE()              __HAL_RCC_GET_RTC_SOURCE()
-
-#endif /* STM32L100xB || STM32L152xBA || ... || STM32L152xE || STM32L162xE */
-
-/**
-  * @}
-  */
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RCCEx_Private_Functions
-  * @{
-  */
-
-/** @addtogroup RCCEx_Exported_Functions_Group1
-  * @{
-  */
-
-HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-void              HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef  *PeriphClkInit);
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || \
-    defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || \
-    defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || \
-    defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-
-void              HAL_RCCEx_EnableLSECSS(void);
-void              HAL_RCCEx_DisableLSECSS(void);
-
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE*/
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_RCC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,902 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rtc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   RTC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Real Time Clock (RTC) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + RTC Time and Date functions
-  *           + RTC Alarm functions
-  *           + Peripheral Control functions   
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-              ##### Backup Domain Operating Condition #####
-  ==============================================================================
-  [..] The real-time clock (RTC) and the RTC backup registers can be powered
-       from the VBAT voltage when the main VDD supply is powered off.
-       To retain the content of the RTC backup registers and supply the RTC 
-       when VDD is turned off, VBAT pin can be connected to an optional 
-       standby voltage supplied by a battery or by another source.
-
-  [..] To allow the RTC operating even when the main digital supply (VDD) is turned
-       off, the VBAT pin powers the following blocks:
-    (#) The RTC
-    (#) The LSE oscillator
-    (#) PC13 to PC15 I/Os (when available)
-  
-  [..] When the backup domain is supplied by VDD (analog switch connected to VDD),
-       the following pins are available:
-    (#) PC14 and PC15 can be used as either GPIO or LSE pins
-    (#) PC13 can be used as a GPIO or as the RTC_AF1 pin
-  
-  [..] When the backup domain is supplied by VBAT (analog switch connected to VBAT 
-       because VDD is not present), the following pins are available:
-    (#) PC14 and PC15 can be used as LSE pins only
-    (#) PC13 can be used as the RTC_AF1 pin 
-             
-                   ##### Backup Domain Reset #####
-  ==================================================================
-  [..] The backup domain reset sets all RTC registers and the RCC_BDCR register
-       to their reset values. 
-  [..] A backup domain reset is generated when one of the following events occurs:
-    (#) Software reset, triggered by setting the BDRST bit in the 
-        RCC Backup domain control register (RCC_BDCR). 
-    (#) VDD or VBAT power on, if both supplies have previously been powered off.  
-
-                   ##### Backup Domain Access #####
-  ==================================================================
-  [..] After reset, the backup domain (RTC registers, RTC backup data 
-       registers and backup SRAM) is protected against possible unwanted write 
-       accesses. 
-  [..] To enable access to the RTC Domain and RTC registers, proceed as follows:
-    (+) Enable the Power Controller (PWR) APB1 interface clock using the
-        __PWR_CLK_ENABLE() function.
-    (+) Enable access to RTC domain using the HAL_PWR_EnableBkUpAccess() function.
-    (+) Select the RTC clock source using the __HAL_RCC_RTC_CONFIG() function.
-    (+) Enable RTC Clock using the __HAL_RCC_RTC_ENABLE() function.
-  
-  
-                  ##### How to use this driver #####
-  ==================================================================
-  [..] 
-    (+) Enable the RTC domain access (see description in the section above).
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
-        format using the HAL_RTC_Init() function.
-  
-  *** Time and Date configuration ***
-  ===================================
-  [..] 
-    (+) To configure the RTC Calendar (Time and Date) use the HAL_RTC_SetTime() 
-        and HAL_RTC_SetDate() functions.
-    (+) To read the RTC Calendar, use the HAL_RTC_GetTime() and HAL_RTC_GetDate() functions. 
-  
-  *** Alarm configuration ***
-  ===========================
-  [..]
-    (+) To configure the RTC Alarm use the HAL_RTC_SetAlarm() function. 
-        You can also configure the RTC Alarm with interrupt mode using the HAL_RTC_SetAlarm_IT() function.
-    (+) To read the RTC Alarm, use the HAL_RTC_GetAlarm() function.
-  
-                  ##### RTC and low power modes #####
-  ==================================================================
-  [..] The MCU can be woken up from a low power mode by an RTC alternate 
-       function.
-  [..] The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
-       RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
-       These RTC alternate functions can wake up the system from the Stop and 
-       Standby low power modes.
-  [..] The system can also wake up from low power modes without depending 
-       on an external interrupt (Auto-wakeup mode), by using the RTC alarm 
-       or the RTC wakeup events.
-  [..] The RTC provides a programmable time base for waking up from the 
-       Stop or Standby mode at regular intervals.
-       Wakeup from STOP and STANDBY modes is possible only when the RTC clock source
-       is LSE or LSI.
-     
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup RTC RTC
-  * @brief RTC HAL module driver
-  * @{
-  */
-
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup RTC_Exported_Functions RTC Exported Functions
-  * @{
-  */
-  
-/** @defgroup RTC_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-   [..] This section provides functions allowing to initialize and configure the 
-         RTC Prescaler (Synchronous and Asynchronous), RTC Hour format, disable 
-         RTC registers Write protection, enter and exit the RTC initialization mode, 
-         RTC registers synchronization check and reference clock detection enable.
-         (#) The RTC Prescaler is programmed to generate the RTC 1Hz time base. 
-             It is split into 2 programmable prescalers to minimize power consumption.
-             (++) A 7-bit asynchronous prescaler and a 13-bit synchronous prescaler.
-             (++) When both prescalers are used, it is recommended to configure the 
-                 asynchronous prescaler to a high value to minimize power consumption.
-         (#) All RTC registers are Write protected. Writing to the RTC registers
-             is enabled by writing a key into the Write Protection register, RTC_WPR.
-         (#) To configure the RTC Calendar, user application should enter 
-             initialization mode. In this mode, the calendar counter is stopped 
-             and its value can be updated. When the initialization sequence is 
-             complete, the calendar restarts counting after 4 RTCCLK cycles.
-         (#) To read the calendar through the shadow registers after Calendar 
-             initialization, calendar update or after wakeup from low power modes 
-             the software must first clear the RSF flag. The software must then 
-             wait until it is set again before reading the calendar, which means 
-             that the calendar registers have been correctly copied into the 
-             RTC_TR and RTC_DR shadow registers.The HAL_RTC_WaitForSynchro() function 
-             implements the above software sequence (RSF clear and RSF check).
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the RTC peripheral 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc)
-{
-  /* Check the RTC peripheral state */
-  if(hrtc == HAL_NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-  assert_param(IS_RTC_HOUR_FORMAT(hrtc->Init.HourFormat));
-  assert_param(IS_RTC_ASYNCH_PREDIV(hrtc->Init.AsynchPrediv));
-  assert_param(IS_RTC_SYNCH_PREDIV(hrtc->Init.SynchPrediv));
-  assert_param(IS_RTC_OUTPUT(hrtc->Init.OutPut));
-  assert_param(IS_RTC_OUTPUT_POL(hrtc->Init.OutPutPolarity));
-  assert_param(IS_RTC_OUTPUT_TYPE(hrtc->Init.OutPutType));
-    
-  if(hrtc->State == HAL_RTC_STATE_RESET)
-  {
-    /* Initialize RTC MSP */
-    HAL_RTC_MspInit(hrtc);
-  }
-  
-  /* Set RTC state */  
-  hrtc->State = HAL_RTC_STATE_BUSY;  
-       
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    return HAL_ERROR;
-  } 
-  else
-  { 
-    /* Clear RTC_CR FMT, OSEL and POL Bits */
-    hrtc->Instance->CR &= ((uint32_t)~(RTC_CR_FMT | RTC_CR_OSEL | RTC_CR_POL));
-    /* Set RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(hrtc->Init.HourFormat | hrtc->Init.OutPut | hrtc->Init.OutPutPolarity);
-    
-    /* Configure the RTC PRER */
-    hrtc->Instance->PRER = (uint32_t)(hrtc->Init.SynchPrediv);
-    hrtc->Instance->PRER |= (uint32_t)(hrtc->Init.AsynchPrediv << 16);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-    
-    hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
-    hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType); 
-    
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_READY;
-    
-    return HAL_OK;
-  }
-}
-
-/**
-  * @brief  DeInitializes the RTC peripheral 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   This function doesn't reset the RTC Backup Data registers.   
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
-  /* Note : This function is defined into this file for library reference. */
-  /*        Function content is located into file stm32l1xx_hal_rtc_ex.c   */
-  
-  /* Return function status */
-  return HAL_ERROR;
-}
-
-/**
-  * @brief  Initializes the RTC MSP.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @retval None
-  */
-__weak void HAL_RTC_MspInit(RTC_HandleTypeDef* hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DeInitializes the RTC MSP.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @retval None
-  */
-__weak void HAL_RTC_MspDeInit(RTC_HandleTypeDef* hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group2 RTC Time and Date functions
- *  @brief   RTC Time and Date functions
- *
-@verbatim   
- ===============================================================================
-                 ##### RTC Time and Date functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure Time and Date features
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets RTC current time.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg FORMAT_BIN: Binary data format 
-  *            @arg FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg = 0;
-  
- /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_RTC_DAYLIGHT_SAVING(sTime->DayLightSaving));
-  assert_param(IS_RTC_STORE_OPERATION(sTime->StoreOperation));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sTime->Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat));
-    } 
-    else
-    {
-      sTime->TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sTime->Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sTime->Minutes));
-    assert_param(IS_RTC_SECONDS(sTime->Seconds));
-    
-    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(sTime->Hours) << 16) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Minutes) << 8) | \
-                        ((uint32_t)RTC_ByteToBcd2(sTime->Seconds)) | \
-                        (((uint32_t)sTime->TimeFormat) << 16));  
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sTime->Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sTime->TimeFormat)); 
-    } 
-    else
-    {
-      sTime->TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sTime->Hours)));
-    }
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sTime->Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sTime->Seconds)));
-    tmpreg = (((uint32_t)(sTime->Hours) << 16) | \
-              ((uint32_t)(sTime->Minutes) << 8) | \
-              ((uint32_t)sTime->Seconds) | \
-              ((uint32_t)(sTime->TimeFormat) << 16));   
-  }
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  {
-    /* Set the RTC_TR register */
-    hrtc->Instance->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
-     
-    /* Clear the bits to be configured */
-    hrtc->Instance->CR &= (uint32_t)~RTC_CR_BCK;
-    
-    /* Configure the RTC_CR register */
-    hrtc->Instance->CR |= (uint32_t)(sTime->DayLightSaving | sTime->StoreOperation);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  
-    
-    /* Wait for synchro */
-    if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-    {       
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-      
-      hrtc->State = HAL_RTC_STATE_ERROR;
-      
-      /* Process Unlocked */ 
-      __HAL_UNLOCK(hrtc);
-      
-      return HAL_ERROR;
-    }
-    
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-    
-   hrtc->State = HAL_RTC_STATE_READY;
-  
-   __HAL_UNLOCK(hrtc); 
-     
-   return HAL_OK;
-  }
-}
-
-
-/**
-  * @brief  Sets RTC current date.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sDate: Pointer to date structure
-  * @param  Format: specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg FORMAT_BIN: Binary data format 
-  *            @arg FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg = 0;
-  
- /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  
- /* Process Locked */ 
- __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY; 
-  
-  if((Format == FORMAT_BIN) && ((sDate->Month & 0x10) == 0x10))
-  {
-    sDate->Month = (uint8_t)((sDate->Month & (uint8_t)~(0x10)) + (uint8_t)0x0A);
-  }
-  
-  assert_param(IS_RTC_WEEKDAY(sDate->WeekDay));
-  
-  if(Format == FORMAT_BIN)
-  {   
-    assert_param(IS_RTC_YEAR(sDate->Year));
-    assert_param(IS_RTC_MONTH(sDate->Month));
-    assert_param(IS_RTC_DATE(sDate->Date)); 
-    
-   datetmpreg = (((uint32_t)RTC_ByteToBcd2(sDate->Year) << 16) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Month) << 8) | \
-                 ((uint32_t)RTC_ByteToBcd2(sDate->Date)) | \
-                 ((uint32_t)sDate->WeekDay << 13));   
-  }
-  else
-  {   
-    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Month);
-    assert_param(IS_RTC_MONTH(datetmpreg));
-    datetmpreg = RTC_Bcd2ToByte(sDate->Date);
-    assert_param(IS_RTC_DATE(datetmpreg));
-    
-    datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
-                  (((uint32_t)sDate->Month) << 8) | \
-                  ((uint32_t)sDate->Date) | \
-                  (((uint32_t)sDate->WeekDay) << 13));  
-  }
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  {
-    /* Set the RTC_DR register */
-    hrtc->Instance->DR = (uint32_t)(datetmpreg & RTC_DR_RESERVED_MASK);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;  
-    
-    /* Wait for synchro */
-    if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-      
-      hrtc->State = HAL_RTC_STATE_ERROR;
-      
-      /* Process Unlocked */ 
-      __HAL_UNLOCK(hrtc);
-      
-      return HAL_ERROR;
-    }
-    
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-    
-    hrtc->State = HAL_RTC_STATE_READY ;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_OK;    
-  }
-}
-
-/**
-  * @brief  Gets RTC current date.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sDate: Pointer to Date structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg FORMAT_BIN:  Binary data format 
-  *            @arg FORMAT_BCD:  BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format)
-{
-  uint32_t datetmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-          
-  /* Get the DR register */
-  datetmpreg = (uint32_t)(hrtc->Instance->DR & RTC_DR_RESERVED_MASK); 
-
-  /* Fill the structure fields with the read parameters */
-  sDate->Year = (uint8_t)((datetmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
-  sDate->Month = (uint8_t)((datetmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
-  sDate->Date = (uint8_t)(datetmpreg & (RTC_DR_DT | RTC_DR_DU));
-  sDate->WeekDay = (uint8_t)((datetmpreg & (RTC_DR_WDU)) >> 13); 
-
-  /* Check the input parameters format */
-  if(Format == FORMAT_BIN)
-  {    
-    /* Convert the date structure parameters to Binary format */
-    sDate->Year = (uint8_t)RTC_Bcd2ToByte(sDate->Year);
-    sDate->Month = (uint8_t)RTC_Bcd2ToByte(sDate->Month);
-    sDate->Date = (uint8_t)RTC_Bcd2ToByte(sDate->Date);  
-  }
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group3 RTC Alarm functions
- *  @brief   RTC Alarm functions
- *
-@verbatim   
- ===============================================================================
-                 ##### RTC Alarm functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure Alarm feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Deactive the specified RTC Alarm 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Alarm: Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *            @arg RTC_ALARM_A:  AlarmA
-  *            @arg RTC_ALARM_B:  AlarmB
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm)
-{
-  uint32_t tickstart = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_ALARM(Alarm));
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  if(Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-    
-    tickstart = HAL_GetTick();
-    
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      { 
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }      
-    }
-  }
-  else
-  {
-    /* AlarmB */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc,RTC_IT_ALRB);
-    
-    tickstart = HAL_GetTick();
-    
-    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }    
-    }
-  }
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);  
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  This function handles Alarm interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef* hrtc)
-{  
-  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRA))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRA) != (uint32_t)RESET)
-    {
-      /* AlarmA callback */ 
-      HAL_RTC_AlarmAEventCallback(hrtc);
-      
-      /* Clear the Alarm interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRAF);
-    }
-  }
-  
-  if(__HAL_RTC_ALARM_GET_IT(hrtc, RTC_IT_ALRB))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_ALRB) != (uint32_t)RESET)
-    {
-      /* AlarmB callback */ 
-      HAL_RTCEx_AlarmBEventCallback(hrtc);
-      
-      /* Clear the Alarm interrupt pending bit */
-      __HAL_RTC_ALARM_CLEAR_FLAG(hrtc,RTC_FLAG_ALRBF);
-    }
-  }
-  
-  /* Clear the EXTI's line Flag for RTC Alarm */
-  __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_ALARM_EVENT);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-}
-
-/**
-  * @brief  Alarm A callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTC_AlarmAEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles AlarmA Polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-
-  uint32_t tickstart = HAL_GetTick();   
-  
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear the Alarm interrupt pending bit */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Exported_Functions_Group5 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
- ===============================================================================
-                     ##### Peripheral State functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Get RTC state
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Returns the RTC state.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL state
-  */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef* hrtc)
-{
-  return hrtc->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Internal_Functions RTC Internal function
-  * @{
-  */
-  
-/**
-  * @brief  Enters the RTC Initialization mode.
-  * @note   The RTC Initialization mode is write protected, use the
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef RTC_EnterInitMode(RTC_HandleTypeDef* hrtc)
-{
-  uint32_t tickstart = 0;
-  
-  /* Check if the Initialization mode is set */
-  if((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-  {
-    /* Set the Initialization mode */
-    hrtc->Instance->ISR = (uint32_t)RTC_INIT_MASK;
-    
-    tickstart = HAL_GetTick();
-    /* Wait till RTC is in INIT state and if Time out is reached exit */
-    while((hrtc->Instance->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
-    {
-      if((HAL_GetTick() - tickstart) >  RTC_TIMEOUT_VALUE)
-      {       
-        return HAL_TIMEOUT;
-      } 
-    }
-  }
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Converts a 2 digit decimal to BCD format.
-  * @param  Value: Byte to be converted
-  * @retval Converted byte
-  */
-uint8_t RTC_ByteToBcd2(uint8_t Value)
-{
-  uint32_t bcdhigh = 0;
-  
-  while(Value >= 10)
-  {
-    bcdhigh++;
-    Value -= 10;
-  }
-  
-  return  ((uint8_t)(bcdhigh << 4) | Value);
-}
-
-/**
-  * @brief  Converts from 2 digit BCD to Binary.
-  * @param  Value: BCD value to be converted
-  * @retval Converted word
-  */
-uint8_t RTC_Bcd2ToByte(uint8_t Value)
-{
-  uint32_t tmp = 0;
-  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
-  return (tmp + (Value & (uint8_t)0x0F));
-}
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,641 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rtc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of RTC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_RTC_H
-#define __STM32L1xx_HAL_RTC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTC
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup RTC_Exported_Types RTC Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  HAL State structures definition  
-  */ 
-typedef enum
-{
-  HAL_RTC_STATE_RESET             = 0x00,  /*!< RTC not yet initialized or disabled */
-  HAL_RTC_STATE_READY             = 0x01,  /*!< RTC initialized and ready for use   */
-  HAL_RTC_STATE_BUSY              = 0x02,  /*!< RTC process is ongoing              */     
-  HAL_RTC_STATE_TIMEOUT           = 0x03,  /*!< RTC timeout state                   */  
-  HAL_RTC_STATE_ERROR             = 0x04   /*!< RTC error state                     */      
-                                                                        
-}HAL_RTCStateTypeDef;
-
-/** 
-  * @brief  RTC Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t HourFormat;      /*!< Specifies the RTC Hour Format.
-                                 This parameter can be a value of @ref RTC_Hour_Formats */         
-
-  uint32_t AsynchPrediv;    /*!< Specifies the RTC Asynchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7F */        
-                               
-  uint32_t SynchPrediv;     /*!< Specifies the RTC Synchronous Predivider value.
-                                 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x7FFF */   
-  
-  uint32_t OutPut;          /*!< Specifies which signal will be routed to the RTC output.   
-                                 This parameter can be a value of @ref RTCEx_Output_selection_Definitions */      
-  
-  uint32_t OutPutPolarity;  /*!< Specifies the polarity of the output signal.  
-                                 This parameter can be a value of @ref RTC_Output_Polarity_Definitions */ 
-  
-  uint32_t OutPutType;      /*!< Specifies the RTC Output Pin mode.   
-                                 This parameter can be a value of @ref RTC_Output_Type_ALARM_OUT */             
-}RTC_InitTypeDef;
-  
-/** 
-  * @brief  RTC Date structure definition  
-  */
-typedef struct
-{
-  uint8_t WeekDay;  /*!< Specifies the RTC Date WeekDay.
-                         This parameter can be a value of @ref RTC_WeekDay_Definitions */
-  
-  uint8_t Month;    /*!< Specifies the RTC Date Month (in BCD format).
-                         This parameter can be a value of @ref RTC_Month_Date_Definitions */
-
-  uint8_t Date;     /*!< Specifies the RTC Date.
-                         This parameter must be a number between Min_Data = 1 and Max_Data = 31 */
-  
-  uint8_t Year;     /*!< Specifies the RTC Date Year.
-                         This parameter must be a number between Min_Data = 0 and Max_Data = 99 */
-                        
-}RTC_DateTypeDef;
-
-/** 
-  * @brief  Time Handle Structure definition  
-  */ 
-typedef struct
-{
-  RTC_TypeDef                 *Instance;  /*!< Register base address    */
-
-  RTC_InitTypeDef             Init;       /*!< RTC required parameters  */ 
-
-  HAL_LockTypeDef             Lock;       /*!< RTC locking object       */
-
-  __IO HAL_RTCStateTypeDef    State;      /*!< Time communication state */
-
-}RTC_HandleTypeDef;
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTC_Exported_Constants RTC Exported Constants
-  * @{
-  */ 
-  
-/** @defgroup RTC_Timeout_Value Default Timeout Value
-  * @{
-  */ 
-#define RTC_TIMEOUT_VALUE  1000
-/**
-  * @}
-  */  
-  
-/** @defgroup RTC_Hour_Formats Hour Formats
-  * @{
-  */ 
-#define RTC_HOURFORMAT_24              ((uint32_t)0x00000000)
-#define RTC_HOURFORMAT_12              ((uint32_t)0x00000040)
-
-#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HOURFORMAT_12) || \
-                                        ((FORMAT) == RTC_HOURFORMAT_24))
-/**
-  * @}
-  */ 
-  
-/** @defgroup RTC_Output_Polarity_Definitions Outpout Polarity
-  * @{
-  */ 
-#define RTC_OUTPUT_POLARITY_HIGH       ((uint32_t)0x00000000)
-#define RTC_OUTPUT_POLARITY_LOW        ((uint32_t)0x00100000)
-
-#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OUTPUT_POLARITY_HIGH) || \
-                                ((POL) == RTC_OUTPUT_POLARITY_LOW))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Output_Type_ALARM_OUT Alarm Output Type
-  * @{
-  */ 
-#define RTC_OUTPUT_TYPE_OPENDRAIN      ((uint32_t)0x00000000)
-#define RTC_OUTPUT_TYPE_PUSHPULL       ((uint32_t)0x00040000)
-
-#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OUTPUT_TYPE_OPENDRAIN) || \
-                                  ((TYPE) == RTC_OUTPUT_TYPE_PUSHPULL))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Asynchronous_Predivider Asynchronous Predivider 
-  * @{
-  */ 
-#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= (uint32_t)0x7F)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Time_Definitions Time Definitions 
-  * @{
-  */ 
-#define IS_RTC_HOUR12(HOUR)            (((HOUR) > (uint32_t)0) && ((HOUR) <= (uint32_t)12))
-#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= (uint32_t)23)
-#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= (uint32_t)59)
-#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= (uint32_t)59)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_AM_PM_Definitions AM PM Definitions 
-  * @{
-  */ 
-#define RTC_HOURFORMAT12_AM            ((uint8_t)0x00)
-#define RTC_HOURFORMAT12_PM            ((uint8_t)0x40)
-
-#define IS_RTC_HOURFORMAT12(PM)  (((PM) == RTC_HOURFORMAT12_AM) || ((PM) == RTC_HOURFORMAT12_PM))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_DayLightSaving_Definitions DayLightSaving
-  * @{
-  */ 
-#define RTC_DAYLIGHTSAVING_SUB1H       ((uint32_t)0x00020000)
-#define RTC_DAYLIGHTSAVING_ADD1H       ((uint32_t)0x00010000)
-#define RTC_DAYLIGHTSAVING_NONE        ((uint32_t)0x00000000)
-
-#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DAYLIGHTSAVING_SUB1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_ADD1H) || \
-                                      ((SAVE) == RTC_DAYLIGHTSAVING_NONE))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_StoreOperation_Definitions StoreOperation
-  * @{
-  */ 
-#define RTC_STOREOPERATION_RESET        ((uint32_t)0x00000000)
-#define RTC_STOREOPERATION_SET          ((uint32_t)0x00040000)
-
-#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_STOREOPERATION_RESET) || \
-                                           ((OPERATION) == RTC_STOREOPERATION_SET))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Input_parameter_format_definitions Input Parameter Format
-  * @{
-  */ 
-#define FORMAT_BIN                      ((uint32_t)0x000000000)
-#define FORMAT_BCD                      ((uint32_t)0x000000001)
-
-#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == FORMAT_BIN) || ((FORMAT) == FORMAT_BCD))
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Year_Date_Definitions Year Definitions
-  * @{
-  */ 
-#define IS_RTC_YEAR(YEAR)              ((YEAR) <= (uint32_t)99)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Month_Date_Definitions Month Definitions
-  * @{
-  */ 
-
-/* Coded in BCD format */
-#define RTC_MONTH_JANUARY              ((uint8_t)0x01)
-#define RTC_MONTH_FEBRUARY             ((uint8_t)0x02)
-#define RTC_MONTH_MARCH                ((uint8_t)0x03)
-#define RTC_MONTH_APRIL                ((uint8_t)0x04)
-#define RTC_MONTH_MAY                  ((uint8_t)0x05)
-#define RTC_MONTH_JUNE                 ((uint8_t)0x06)
-#define RTC_MONTH_JULY                 ((uint8_t)0x07)
-#define RTC_MONTH_AUGUST               ((uint8_t)0x08)
-#define RTC_MONTH_SEPTEMBER            ((uint8_t)0x09)
-#define RTC_MONTH_OCTOBER              ((uint8_t)0x10)
-#define RTC_MONTH_NOVEMBER             ((uint8_t)0x11)
-#define RTC_MONTH_DECEMBER             ((uint8_t)0x12)
-
-#define IS_RTC_MONTH(MONTH)            (((MONTH) >= (uint32_t)1) && ((MONTH) <= (uint32_t)12))
-#define IS_RTC_DATE(DATE)              (((DATE) >= (uint32_t)1) && ((DATE) <= (uint32_t)31))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_WeekDay_Definitions WeekDay Definitions 
-  * @{
-  */ 
-#define RTC_WEEKDAY_MONDAY             ((uint8_t)0x01)
-#define RTC_WEEKDAY_TUESDAY            ((uint8_t)0x02)
-#define RTC_WEEKDAY_WEDNESDAY          ((uint8_t)0x03)
-#define RTC_WEEKDAY_THURSDAY           ((uint8_t)0x04)
-#define RTC_WEEKDAY_FRIDAY             ((uint8_t)0x05)
-#define RTC_WEEKDAY_SATURDAY           ((uint8_t)0x06)
-#define RTC_WEEKDAY_SUNDAY             ((uint8_t)0x07)
-
-#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                 ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-/**
-  * @}
-  */ 
-                                    
-/** @defgroup RTC_Alarm_Definitions Alarm Definitions
-  * @{
-  */ 
-#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) >(uint32_t) 0) && ((DATE) <= (uint32_t)31))
-#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_WEEKDAY_MONDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_TUESDAY)   || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_WEDNESDAY) || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_THURSDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_FRIDAY)    || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SATURDAY)  || \
-                                                    ((WEEKDAY) == RTC_WEEKDAY_SUNDAY))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_AlarmDateWeekDay_Definitions AlarmDateWeekDay Definitions 
-  * @{
-  */ 
-#define RTC_ALARMDATEWEEKDAYSEL_DATE      ((uint32_t)0x00000000)
-#define RTC_ALARMDATEWEEKDAYSEL_WEEKDAY   ((uint32_t)0x40000000)
-
-#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_ALARMDATEWEEKDAYSEL_DATE) || \
-                                            ((SEL) == RTC_ALARMDATEWEEKDAYSEL_WEEKDAY))
-/**
-  * @}
-  */ 
-
-
-/** @defgroup RTC_AlarmMask_Definitions Alarm Mask Definitions
-  * @{
-  */ 
-#define RTC_ALARMMASK_NONE                ((uint32_t)0x00000000)
-#define RTC_ALARMMASK_DATEWEEKDAY         RTC_ALRMAR_MSK4
-#define RTC_ALARMMASK_HOURS               RTC_ALRMAR_MSK3
-#define RTC_ALARMMASK_MINUTES             RTC_ALRMAR_MSK2
-#define RTC_ALARMMASK_SECONDS             RTC_ALRMAR_MSK1
-#define RTC_ALARMMASK_ALL                 ((uint32_t)0x80808080)
-
-#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Alarms_Definitions Alarms Definitions 
-  * @{
-  */ 
-#define RTC_ALARM_A                       RTC_CR_ALRAE
-#define RTC_ALARM_B                       RTC_CR_ALRBE
-
-#define IS_ALARM(ALARM)      (((ALARM) == RTC_ALARM_A) || ((ALARM) == RTC_ALARM_B))
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTC_Exported_macros RTC Exported Macros
-  * @{
-  */
-  
-/** @brief  Reset RTC handle state
-  * @param  __HANDLE__: RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
- 
-/**
-  * @brief  Disable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__)             \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xCA;   \
-                            (__HANDLE__)->Instance->WPR = 0x53;   \
-                          } while(0)
-
-/**
-  * @brief  Enable the write protection for RTC registers.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__)              \
-                        do{                                       \
-                            (__HANDLE__)->Instance->WPR = 0xFF;   \
-                          } while(0)                            
- 
-/**
-  * @brief  Enable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
-
-/**
-  * @brief  Disable the RTC ALARMA peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
-
-/**
-  * @brief  Enable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__)                           ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
-
-/**
-  * @brief  Disable the RTC ALARMB peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__)                          ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
-
-/**
-  * @brief  Enable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
-  *          This parameter can be any combination of the following values:
-  *             @arg RTC_IT_ALRA: Alarm A interrupt
-  *             @arg RTC_IT_ALRB: Alarm B interrupt  
-  * @retval None
-  */   
-#define __HAL_RTC_ALARM_ENABLE_IT(__HANDLE__, __INTERRUPT__)          ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC Alarm interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. 
-  *         This parameter can be any combination of the following values:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_DISABLE_IT(__HANDLE__, __INTERRUPT__)         ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified RTC Alarm interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_ALRA: Alarm A interrupt
-  *            @arg RTC_IT_ALRB: Alarm B interrupt  
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_IT(__HANDLE__, __FLAG__)                  ((((((__HANDLE__)->Instance->ISR)& ((__FLAG__)>> 4)) & 0x0000FFFF) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Alarm's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *          This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  *            @arg RTC_FLAG_ALRBF
-  *            @arg RTC_FLAG_ALRAWF     
-  *            @arg RTC_FLAG_ALRBWF    
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Clear the RTC Alarm's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_ALRAF
-  *            @arg RTC_FLAG_ALRBF 
-  * @retval None
-  */
-#define __HAL_RTC_ALARM_CLEAR_FLAG(__HANDLE__, __FLAG__)                  ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-  
-#define RTC_EXTI_LINE_ALARM_EVENT             ((uint32_t)0x00020000)  /*!< External interrupt line 17 Connected to the RTC Alarm event */
-#define RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT  ((uint32_t)0x00080000)  /*!< External interrupt line 19 Connected to the RTC Tamper and Time Stamp events */                                               
-#define RTC_EXTI_LINE_WAKEUPTIMER_EVENT       ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the RTC Wakeup event */                                               
-
-/**
-  * @brief  Enable the RTC Exti line.
-  * @param  __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_EXTI_LINE_ALARM_EVENT   
-  *            @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT 
-  *            @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT      
-  * @retval None
-  */                                         
-#define __HAL_RTC_EXTI_ENABLE_IT(__EXTILINE__)   (EXTI->IMR |= (__EXTILINE__))
-
-/* alias define maintained for legacy */
-#define __HAL_RTC_ENABLE_IT   __HAL_RTC_EXTI_ENABLE_IT
-
-/**
-  * @brief  Disable the RTC Exti line.
-  * @param  __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_EXTI_LINE_ALARM_EVENT   
-  *            @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT 
-  *            @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT     
-  * @retval None
-  */
-#define __HAL_RTC_EXTI_DISABLE_IT(__EXTILINE__)  (EXTI->IMR &= ~(__EXTILINE__))
-
-/* alias define maintained for legacy */
-#define __HAL_RTC_DISABLE_IT   __HAL_RTC_EXTI_DISABLE_IT
-
-/**
-  * @brief  Generates a Software interrupt on selected EXTI line.
-  * @param  __EXTILINE__: specifies the RTC Exti sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_EXTI_LINE_ALARM_EVENT
-  *            @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT
-  *            @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT
-  * @retval None
-  */
-#define __HAL_RTC_EXTI_GENERATE_SWIT(__EXTILINE__) (EXTI->SWIER |= (__EXTILINE__))
-
-/**
-  * @brief  Clear the RTC Exti flags.
-  * @param  __FLAG__: specifies the RTC Exti sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_EXTI_LINE_ALARM_EVENT   
-  *            @arg RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT 
-  *            @arg RTC_EXTI_LINE_WAKEUPTIMER_EVENT      
-  * @retval None
-  */
-#define __HAL_RTC_EXTI_CLEAR_FLAG(__FLAG__)  (EXTI->PR = (__FLAG__))
-
-/* alias define maintained for legacy */
-#define __HAL_RTC_CLEAR_FLAG   __HAL_RTC_EXTI_CLEAR_FLAG
-
-/**
-  * @}
-  */
-  
-/* Include RTC HAL Extension module */
-#include "stm32l1xx_hal_rtc_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTC_Exported_Functions
-  * @{
-  */
-
-
-/* Initialization and de-initialization functions  ****************************/
-/** @addtogroup RTC_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTC_Init(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_MspInit(RTC_HandleTypeDef *hrtc);
-void              HAL_RTC_MspDeInit(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-  
-/* RTC Time and Date functions ************************************************/
-/** @addtogroup RTC_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTC_SetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_GetDate(RTC_HandleTypeDef *hrtc, RTC_DateTypeDef *sDate, uint32_t Format);
-/**
-  * @}
-  */
-
-/* RTC Alarm functions ********************************************************/
-/** @addtogroup RTC_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format);
-HAL_StatusTypeDef HAL_RTC_DeactivateAlarm(RTC_HandleTypeDef *hrtc, uint32_t Alarm);
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format);
-void              HAL_RTC_AlarmIRQHandler(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-void              HAL_RTC_AlarmAEventCallback(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/* Peripheral Control functions ***********************************************/
-/** @addtogroup RTC_Exported_Functions_Group3
-  * @{
-  */
-HAL_StatusTypeDef   HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc);
-/**
-  * @}
-  */
-
-/* Peripheral State functions *************************************************/
-/** @addtogroup RTC_Exported_Functions_Group5
-  * @{
-  */
-HAL_RTCStateTypeDef HAL_RTC_GetState(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/* Private functions **********************************************************/
-/** @addtogroup RTC_Internal_Functions
-  * @{
-  */
-HAL_StatusTypeDef  RTC_EnterInitMode(RTC_HandleTypeDef* hrtc);
-uint8_t            RTC_ByteToBcd2(uint8_t Value);
-uint8_t            RTC_Bcd2ToByte(uint8_t Value);
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_RTC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2482 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rtc_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Extended RTC HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Real Time Clock (RTC) Extension peripheral:
-  *           + RTC Time Stamp functions
-  *           + RTC Tamper functions 
-  *           + RTC Wake-up functions
-  *           + Extension Control functions
-  *           + Extension RTC features functions    
-  *         
-  @verbatim
-  ==============================================================================
-                  ##### How to use this driver #####
-  ==============================================================================
-  [..] 
-    (+) Enable the RTC domain access.
-    (+) Configure the RTC Prescaler (Asynchronous and Synchronous) and RTC hour 
-        format using the HAL_RTC_Init() function.
-  
-  *** RTC Wakeup configuration ***
-  ================================
-  [..] 
-    (+) To configure the RTC Wakeup Clock source and Counter use the HAL_RTCEx_SetWakeUpTimer()
-        function. You can also configure the RTC Wakeup timer with interrupt mode 
-        using the HAL_RTCEx_SetWakeUpTimer_IT() function.
-    (+) To read the RTC WakeUp Counter register, use the HAL_RTCEx_GetWakeUpTimer()
-        function.
-  
-  *** TimeStamp configuration ***
-  ===============================
-  [..]
-    (+) Configure the RTC_AFx trigger and enable the RTC TimeStamp using the 
-        HAL_RTCEx_SetTimeStamp() function. You can also configure the RTC TimeStamp with
-        interrupt mode using the HAL_RTCEx_SetTimeStamp_IT() function.
-    (+) To read the RTC TimeStamp Time and Date register, use the HAL_RTCEx_GetTimeStamp()
-        function.
-    (+) The TIMESTAMP alternate function can be mapped to RTC_AF1 (PC13).
-  
-  *** Tamper configuration ***
-  ============================
-  [..]
-    (+) Enable the RTC Tamper and configure the Tamper filter count, trigger Edge 
-        or Level according to the Tamper filter (if equal to 0 Edge else Level) 
-        value, sampling frequency, precharge or discharge and Pull-UP using the 
-        HAL_RTCEx_SetTamper() function. You can configure RTC Tamper with interrupt
-        mode using HAL_RTCEx_SetTamper_IT() function.
-    (+) The TAMPER1 alternate function can be mapped to RTC_AF1 (PC13).
-
-  *** Backup Data Registers configuration ***
-  ===========================================
-  [..]
-    (+) To write to the RTC Backup Data registers, use the HAL_RTCEx_BKUPWrite()
-        function.  
-    (+) To read the RTC Backup Data registers, use the HAL_RTCEx_BKUPRead()
-        function.
-     
-   @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-  
-/** @addtogroup RTC
-  * @{
-  */
-  
-#ifdef HAL_RTC_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup RTC_Exported_Functions
-  * @{
-  */
-
-
-/** @addtogroup RTC_Exported_Functions_Group1
-  * @{
-  */
-  
-/**
-  * @brief  DeInitializes the RTC peripheral 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   This function does not reset the RTC Backup Data registers.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_DeInit(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_ALL_INSTANCE(hrtc->Instance));
-
-  /* Set RTC state */
-  hrtc->State = HAL_RTC_STATE_BUSY; 
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state */
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    return HAL_ERROR;
-  }  
-  else
-  {
-    /* Reset TR, DR and CR registers */
-    hrtc->Instance->TR = (uint32_t)0x00000000;
-    hrtc->Instance->DR = (uint32_t)0x00002101;
-    /* Reset All CR bits except CR[2:0] */
-    hrtc->Instance->CR &= (uint32_t)0x00000007;
-    
-    tickstart = HAL_GetTick();
-    
-    /* Wait till WUTWF flag is set and if Time out is reached exit */
-    while(((hrtc->Instance->ISR) & RTC_ISR_WUTWF) == (uint32_t)RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      { 
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-        
-        /* Set RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        
-        return HAL_TIMEOUT;
-      } 
-    }
-    
-    /* Reset all RTC CR register bits */
-    hrtc->Instance->CR &= (uint32_t)0x00000000;
-    hrtc->Instance->WUTR = (uint32_t)0x0000FFFF;
-    hrtc->Instance->PRER = (uint32_t)0x007F00FF;
-    hrtc->Instance->CALIBR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMAR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBR = (uint32_t)0x00000000;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-    hrtc->Instance->SHIFTR = (uint32_t)0x00000000;
-    hrtc->Instance->CALR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMASSR = (uint32_t)0x00000000;
-    hrtc->Instance->ALRMBSSR = (uint32_t)0x00000000;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-    /* Reset ISR register and exit initialization mode */
-    hrtc->Instance->ISR = (uint32_t)0x00000000;
-    
-    /* Reset Tamper and alternate functions configuration register */
-    hrtc->Instance->TAFCR = 0x00000000;
-    
-    /* Wait for synchro */
-    if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-      
-      hrtc->State = HAL_RTC_STATE_ERROR;
-      
-      return HAL_ERROR;
-    }  
-  }
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* De-Initialize RTC MSP */
-  HAL_RTC_MspDeInit(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_RESET; 
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group2
-  * @{
-  */
-  
-/**
-  * @brief  Gets RTC current time.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTime: Pointer to Time structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *            @arg FORMAT_BIN: Binary data format 
-  *            @arg FORMAT_BCD: BCD data format
-  * @note   Call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values 
-  *         in the higher-order calendar shadow registers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetTime(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTime, uint32_t Format)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-  /* Get subseconds values from the correspondent registers*/
-  sTime->SubSeconds = (uint32_t)((hrtc->Instance->SSR) & RTC_SSR_SS);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Get the TR register */
-  tmpreg = (uint32_t)(hrtc->Instance->TR & RTC_TR_RESERVED_MASK); 
-  
-  /* Fill the structure fields with the read parameters */
-  sTime->Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  sTime->Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
-  sTime->Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
-  sTime->TimeFormat = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16); 
-  
-  /* Check the input parameters format */
-  if(Format == FORMAT_BIN)
-  {
-    /* Convert the time structure parameters to Binary format */
-    sTime->Hours = (uint8_t)RTC_Bcd2ToByte(sTime->Hours);
-    sTime->Minutes = (uint8_t)RTC_Bcd2ToByte(sTime->Minutes);
-    sTime->Seconds = (uint8_t)RTC_Bcd2ToByte(sTime->Seconds);  
-  }
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @addtogroup RTC_Exported_Functions_Group3
-  * @{
-  */
-
-/**
-  * @brief  Sets the specified RTC Alarm.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg FORMAT_BIN: Binary data format 
-  *             @arg FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0;
-  
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-  uint32_t subsecondtmpreg = 0;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_ALARM(sAlarm->Alarm));
-  assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-    
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask)); 
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-    
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
-    }  
-    
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));   
-  }
-  
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRA);
-         
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }   
-    }
-    
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-    
-    /* In case of interrupt mode is used, the interrupt source must disabled */ 
-    __HAL_RTC_ALARM_DISABLE_IT(hrtc, RTC_IT_ALRB);
-       
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }  
-    }    
-    
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc); 
-  }
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);   
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets the specified RTC Alarm with Interrupt 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Alarm structure
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg FORMAT_BIN: Binary data format 
-  *             @arg FORMAT_BCD: BCD data format
-  * @note   The Alarm register can only be written when the corresponding Alarm
-  *         is disabled (Use the HAL_RTC_DeactivateAlarm()).   
-  * @note   The HAL_RTC_SetTime() must be called before enabling the Alarm feature.   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
-{
-  uint32_t tickstart = 0;
-  uint32_t tmpreg = 0;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  uint32_t subsecondtmpreg = 0;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_ALARM(sAlarm->Alarm));
-  assert_param(IS_ALARM_MASK(sAlarm->AlarmMask));
-  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(sAlarm->AlarmDateWeekDaySel));
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(sAlarm->AlarmTime.SubSeconds));
-  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(sAlarm->AlarmSubSecondMask));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  if(Format == FORMAT_BIN)
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      assert_param(IS_RTC_HOUR12(sAlarm->AlarmTime.Hours));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
-    }
-    assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
-    assert_param(IS_RTC_SECONDS(sAlarm->AlarmTime.Seconds));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(sAlarm->AlarmDateWeekDay));
-    }
-    else
-    {
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
-    }
-    tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask)); 
-  }
-  else
-  {
-    if((hrtc->Instance->CR & RTC_CR_FMT) != (uint32_t)RESET)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-      assert_param(IS_RTC_HOUR12(tmpreg));
-      assert_param(IS_RTC_HOURFORMAT12(sAlarm->AlarmTime.TimeFormat));
-    } 
-    else
-    {
-      sAlarm->AlarmTime.TimeFormat = 0x00;
-      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
-    }
-    
-    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes)));
-    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds)));
-    
-    if(sAlarm->AlarmDateWeekDaySel == RTC_ALARMDATEWEEKDAYSEL_DATE)
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
-    }
-    else
-    {
-      tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
-    }
-    tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
-              ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
-              ((uint32_t) sAlarm->AlarmTime.Seconds) | \
-              ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
-              ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
-              ((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
-              ((uint32_t)sAlarm->AlarmMask));     
-  }
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-  /* Configure the Alarm A or Alarm B Sub Second registers */
-  subsecondtmpreg = (uint32_t)((uint32_t)(sAlarm->AlarmTime.SubSeconds) | (uint32_t)(sAlarm->AlarmSubSecondMask));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-  
-  /* Configure the Alarm register */
-  if(sAlarm->Alarm == RTC_ALARM_A)
-  {
-    /* Disable the Alarm A interrupt */
-    __HAL_RTC_ALARMA_DISABLE(hrtc);
-
-    /* Clear flag alarm A */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }  
-    }
-    
-    hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-    /* Configure the Alarm A Sub Second register */
-    hrtc->Instance->ALRMASSR = subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMA_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc,RTC_IT_ALRA);
-  }
-  else
-  {
-    /* Disable the Alarm B interrupt */
-    __HAL_RTC_ALARMB_DISABLE(hrtc);
-
-    /* Clear flag alarm B */
-    __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-
-    tickstart = HAL_GetTick();
-    /* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
-    while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-        
-        hrtc->State = HAL_RTC_STATE_TIMEOUT; 
-        
-        /* Process Unlocked */ 
-        __HAL_UNLOCK(hrtc);
-        
-        return HAL_TIMEOUT;
-      }  
-    }
-
-    hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-    /* Configure the Alarm B Sub Second register */
-    hrtc->Instance->ALRMBSSR = subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-    /* Configure the Alarm state: Enable Alarm */
-    __HAL_RTC_ALARMB_ENABLE(hrtc);
-    /* Configure the Alarm interrupt */
-    __HAL_RTC_ALARM_ENABLE_IT(hrtc, RTC_IT_ALRB);
-  }
-
-  /* RTC Alarm Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_ALARM_EVENT);
-  
-  EXTI->RTSR |= RTC_EXTI_LINE_ALARM_EVENT;
-  
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);  
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);  
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets the RTC Alarm value and masks.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sAlarm: Pointer to Date structure
-  * @param  Alarm: Specifies the Alarm.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_ALARM_A: AlarmA
-  *             @arg RTC_ALARM_B: AlarmB  
-  * @param  Format: Specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             @arg FORMAT_BIN: Binary data format 
-  *             @arg FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_GetAlarm(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Alarm, uint32_t Format)
-{
-  uint32_t tmpreg = 0;
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  uint32_t subsecondtmpreg = 0;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-  assert_param(IS_ALARM(Alarm));
-  
-  if(Alarm == RTC_ALARM_A)
-  {
-    /* AlarmA */
-    sAlarm->Alarm = RTC_ALARM_A;
-    
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMAR);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMASSR) & RTC_ALRMASSR_SS);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */    
-  }
-  else
-  {
-    sAlarm->Alarm = RTC_ALARM_B;
-    
-    tmpreg = (uint32_t)(hrtc->Instance->ALRMBR);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-    subsecondtmpreg = (uint32_t)((hrtc->Instance->ALRMBSSR) & RTC_ALRMBSSR_SS);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */    
-  }
-    
-  /* Fill the structure with the read parameters */
-  sAlarm->AlarmTime.Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | RTC_ALRMAR_HU)) >> 16);
-  sAlarm->AlarmTime.Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | RTC_ALRMAR_MNU)) >> 8);
-  sAlarm->AlarmTime.Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | RTC_ALRMAR_SU));
-  sAlarm->AlarmTime.TimeFormat = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  sAlarm->AlarmTime.SubSeconds = (uint32_t) subsecondtmpreg;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */  
-  sAlarm->AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
-  sAlarm->AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
-  sAlarm->AlarmMask = (uint32_t)(tmpreg & RTC_ALARMMASK_ALL);
-    
-  if(Format == FORMAT_BIN)
-  {
-    sAlarm->AlarmTime.Hours = RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours);
-    sAlarm->AlarmTime.Minutes = RTC_Bcd2ToByte(sAlarm->AlarmTime.Minutes);
-    sAlarm->AlarmTime.Seconds = RTC_Bcd2ToByte(sAlarm->AlarmTime.Seconds);
-    sAlarm->AlarmDateWeekDay = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
-  }  
-    
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-
-/** @defgroup RTC_Exported_Functions_Group6 Peripheral Control functions 
- *  @brief   Peripheral Control functions 
- *
-@verbatim   
- ===============================================================================
-                     ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Wait for RTC Time and Date Synchronization
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
-  *         synchronized with RTC APB clock.
-  * @note   The RTC Resynchronization mode is write protected, use the 
-  *         __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
-  * @note   To read the calendar through the shadow registers after Calendar 
-  *         initialization, calendar update or after wakeup from low power modes 
-  *         the software must first clear the RSF flag. 
-  *         The software must then wait until it is set again before reading 
-  *         the calendar, which means that the calendar registers have been 
-  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTC_WaitForSynchro(RTC_HandleTypeDef* hrtc)
-{
-  uint32_t tickstart = 0;
-  
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  /* If RTC_CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
-  if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  {
-    /* Clear RSF flag */
-    hrtc->Instance->ISR &= (uint32_t)RTC_RSF_MASK;
-    
-  tickstart = HAL_GetTick();
-
-    /* Wait the registers to be synchronised */
-    while((hrtc->Instance->ISR & RTC_ISR_RSF) == (uint32_t)RESET)
-    {
-    if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      {       
-        return HAL_TIMEOUT;
-      } 
-    }
-  }
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-    
-/** @defgroup RTCEx RTCEx
-  * @brief RTC Extended HAL module driver
-  * @{
-  */
-  
-/** @defgroup RTCEx_Exported_Functions RTCEx Exported Functions
-  * @{
-  */
-  
-/** @defgroup RTCEx_Exported_Functions_Group4 RTC TimeStamp and Tamper functions
-  * @brief    RTC TimeStamp and Tamper functions
-  *
-@verbatim   
- ===============================================================================
-                 ##### RTC TimeStamp and Tamper functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure TimeStamp feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets TimeStamp.
-  * @note   This API must be called before enabling the TimeStamp feature. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
-  *                                         falling edge of the related pin.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg|= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets TimeStamp with Interrupt. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @note   This API must be called before enabling the TimeStamp feature.
-  * @param  TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
-  *         activated.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the  
-  *                                        rising edge of the related pin.
-  *             @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the 
-  *                                         falling edge of the related pin.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIMESTAMP_EDGE(TimeStampEdge));
-
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  tmpreg |= TimeStampEdge;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  __HAL_RTC_TIMESTAMP_ENABLE(hrtc);
-
-  /* Enable IT timestamp */
-  __HAL_RTC_TIMESTAMP_ENABLE_IT(hrtc,RTC_IT_TS);
-
-  /* RTC timestamp Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
-
-  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates TimeStamp. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tmpreg = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_TIMESTAMP_DISABLE_IT(hrtc, RTC_IT_TS);
-
-  /* Get the RTC_CR register and clear the bits to be configured */
-  tmpreg = (uint32_t)(hrtc->Instance->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
-
-  /* Configure the Time Stamp TSEDGE and Enable bits */
-  hrtc->Instance->CR = (uint32_t)tmpreg;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets the RTC TimeStamp value.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTimeStamp: Pointer to Time structure
-  * @param  sTimeStampDate: Pointer to Date structure  
-  * @param  Format: specifies the format of the entered parameters.
-  *          This parameter can be one of the following values:
-  *             FORMAT_BIN: Binary data format 
-  *             FORMAT_BCD: BCD data format
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
-{
-  uint32_t tmptime = 0, tmpdate = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_FORMAT(Format));
-
-  /* Get the TimeStamp time and date registers values */
-  tmptime = (uint32_t)(hrtc->Instance->TSTR & RTC_TR_RESERVED_MASK);
-  tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
-
-  /* Fill the Time structure fields with the read parameters */
-  sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
-  sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
-  sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
-  sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  sTimeStamp->SubSeconds = (uint32_t)((hrtc->Instance->TSSSR) & RTC_TSSSR_SS);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-  /* Fill the Date structure fields with the read parameters */
-  sTimeStampDate->Year = 0;
-  sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
-  sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
-  sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
-
-  /* Check the input parameters format */
-  if(Format == FORMAT_BIN)
-  {
-    /* Convert the TimeStamp structure parameters to Binary format */
-    sTimeStamp->Hours = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Hours);
-    sTimeStamp->Minutes = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Minutes);
-    sTimeStamp->Seconds = (uint8_t)RTC_Bcd2ToByte(sTimeStamp->Seconds);
-
-    /* Convert the DateTimeStamp structure parameters to Binary format */
-    sTimeStampDate->Month = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Month);
-    sTimeStampDate->Date = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->Date);
-    sTimeStampDate->WeekDay = (uint8_t)RTC_Bcd2ToByte(sTimeStampDate->WeekDay);
-  }
-
-  /* Clear the TIMESTAMP Flag */
-  __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSF);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets Tamper
-  * @note   By calling this API we disable the tamper interrupt for all tampers. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTamper: Pointer to Tamper Structure.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TAMPER(sTamper->Tamper));
-  assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  assert_param(IS_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE))
-  {
-    /* Configure the RTC_TAFCR register */
-    sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE;
-  }
-  else
-  {
-    sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
-  }
-
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
-            (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
-            (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
-                                       (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAFCR_TAMPPUDIS | (uint32_t)RTC_TAFCR_TAMPIE);
-#else
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Trigger));
-
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG);
-
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  hrtc->Instance->TAFCR |= tmpreg;
-  
-  hrtc->State = HAL_RTC_STATE_READY; 
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets Tamper with interrupt.
-  * @note   By calling this API we force the tamper interrupt for all tampers.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  sTamper: Pointer to RTC Tamper.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
-{
-  uint32_t tmpreg = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TAMPER(sTamper->Tamper)); 
-  assert_param(IS_TAMPER_TRIGGER(sTamper->Trigger));
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  assert_param(IS_TAMPER_FILTER(sTamper->Filter));
-  assert_param(IS_TAMPER_SAMPLING_FREQ(sTamper->SamplingFrequency));
-  assert_param(IS_TAMPER_PRECHARGE_DURATION(sTamper->PrechargeDuration));
-  assert_param(IS_TAMPER_PULLUP_STATE(sTamper->TamperPullUp));
-  assert_param(IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(sTamper->TimeStampOnTamperDetection));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  /* Configure the tamper trigger */
-  if((sTamper->Trigger == RTC_TAMPERTRIGGER_RISINGEDGE))
-  {
-    sTamper->Trigger = RTC_TAMPERTRIGGER_RISINGEDGE;
-  }
-  else
-  {
-    sTamper->Trigger = (uint32_t) (sTamper->Tamper<<1);
-  }
-
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger | (uint32_t)sTamper->Filter |\
-            (uint32_t)sTamper->SamplingFrequency | (uint32_t)sTamper->PrechargeDuration |\
-            (uint32_t)sTamper->TamperPullUp | sTamper->TimeStampOnTamperDetection);
-
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)sTamper->Tamper | (uint32_t)(sTamper->Tamper << 1) | (uint32_t)RTC_TAFCR_TAMPTS |\
-                                       (uint32_t)RTC_TAFCR_TAMPFREQ | (uint32_t)RTC_TAFCR_TAMPFLT | (uint32_t)RTC_TAFCR_TAMPPRCH |\
-                                       (uint32_t)RTC_TAFCR_TAMPPUDIS);
-#else
-  tmpreg = ((uint32_t)sTamper->Tamper | (uint32_t)sTamper->Trigger);
-
-  hrtc->Instance->TAFCR &= (uint32_t)~((uint32_t)RTC_TAFCR_TAMP1E | (uint32_t)RTC_TAFCR_TAMP1TRG | (uint32_t)RTC_TAFCR_TAMPIE);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  hrtc->Instance->TAFCR |= tmpreg;
-
-  /* Configure the Tamper Interrupt in the RTC_TAFCR */
-  hrtc->Instance->TAFCR |= (uint32_t)RTC_TAFCR_TAMPIE;
-
-  /* RTC Tamper Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
-
-  EXTI->RTSR |= RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT;
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates Tamper.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Tamper: Selected tamper pin.
-  *          This parameter can be a value of @ref RTCEx_Tamper_Pins_Definitions
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper)
-{
-  assert_param(IS_TAMPER(Tamper));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the selected Tamper pin */
-  hrtc->Instance->TAFCR &= (uint32_t)~Tamper;
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles TimeStamp interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc)
-{  
-  if(__HAL_RTC_TIMESTAMP_GET_IT(hrtc, RTC_IT_TS))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_TS) != (uint32_t)RESET)
-    {
-      /* TIMESTAMP callback */ 
-      HAL_RTCEx_TimeStampEventCallback(hrtc);
-  
-      /* Clear the TIMESTAMP interrupt pending bit */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc,RTC_FLAG_TSF);
-    }
-  }
-
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_IT(hrtc,RTC_IT_TAMP1))
-  {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if(((hrtc->Instance->TAFCR & (RTC_TAFCR_TAMPIE))) != (uint32_t)RESET)
-    {
-      /* Tamper callback */ 
-      HAL_RTCEx_Tamper1EventCallback(hrtc);
-  
-      /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-    }
-  }
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP2))
-  {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
-    {
-      /* Tamper callback */ 
-      HAL_RTCEx_Tamper2EventCallback(hrtc);
-  
-      /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP2F);
-    }
-  }
-
-  /* Get the status of the Interrupt */
-  if(__HAL_RTC_TAMPER_GET_IT(hrtc, RTC_IT_TAMP3))
-  {
-    /* Get the TAMPER Interrupt enable bit and pending bit */
-    if(((hrtc->Instance->TAFCR & RTC_TAFCR_TAMPIE)) != (uint32_t)RESET)
-    {
-      /* Tamper callback */
-      HAL_RTCEx_Tamper3EventCallback(hrtc);
-
-      /* Clear the Tamper interrupt pending bit */
-      __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc, RTC_FLAG_TAMP3F);
-    }
-  }
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-  /* Clear the EXTI s Flag for RTC TimeStamp and Tamper */
-  __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_TAMPER_TIMESTAMP_EVENT);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  TimeStamp callback. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_TimeStampEventCallback could be implemented in the user file
-  */
-}
-
-/**
-  * @brief  Tamper 1 callback. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper1EventCallback could be implemented in the user file
-   */
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-/**
-  * @brief  Tamper 2 callback. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper2EventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tamper 3 callback. 
-  * @param  hrtc: RTC handle
-  * @retval None
-  */
-__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_Tamper3EventCallback could be implemented in the user file
-   */
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @brief  This function handles TimeStamp polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSF) == RESET)
-  {
-    if(__HAL_RTC_TIMESTAMP_GET_FLAG(hrtc, RTC_FLAG_TSOVF) != RESET)
-    {
-      /* Clear the TIMESTAMP OverRun Flag */
-      __HAL_RTC_TIMESTAMP_CLEAR_FLAG(hrtc, RTC_FLAG_TSOVF);
-
-      /* Change TIMESTAMP state */
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      return HAL_ERROR;
-    }
-
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Tamper1 Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP1F)== RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP1F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-/**
-  * @brief  This function handles Tamper2 Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP2F) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP2F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles Tamper3 Polling.
-  * @param  hrtc: RTC handle
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = HAL_GetTick();
-
-  /* Get the status of the Interrupt */
-  while(__HAL_RTC_TAMPER_GET_FLAG(hrtc,RTC_FLAG_TAMP3F) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the Tamper Flag */
-  __HAL_RTC_TAMPER_CLEAR_FLAG(hrtc,RTC_FLAG_TAMP3F);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @}
-  */
-  
-/** @defgroup RTCEx_Exported_Functions_Group5 RTC Wake-up functions
-  * @brief    RTC Wake-up functions
-  *
-@verbatim   
- ===============================================================================
-                        ##### RTC Wake-up functions #####
- ===============================================================================  
- 
- [..] This section provides functions allowing to configure Wake-up feature
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sets wake up timer. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-     
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-   /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sets wake up timer with interrupt
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  WakeUpCounter: Wake up counter
-  * @param  WakeUpClock: Wake up clock  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_WAKEUP_CLOCK(WakeUpClock));
-  assert_param(IS_WAKEUP_COUNTER(WakeUpCounter));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  tickstart = HAL_GetTick();
-
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Configure the Wakeup Timer counter */
-  hrtc->Instance->WUTR = (uint32_t)WakeUpCounter;
-
-  /* Clear the Wakeup Timer clock source bits in CR register */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_WUCKSEL;
-
-  /* Configure the clock source */
-  hrtc->Instance->CR |= (uint32_t)WakeUpClock;
-
-  /* RTC WakeUpTimer Interrupt Configuration: EXTI configuration */
-  __HAL_RTC_ENABLE_IT(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
-
-  EXTI->RTSR |= RTC_EXTI_LINE_WAKEUPTIMER_EVENT;
-
-  /* Configure the Interrupt in the RTC_CR register */
-  __HAL_RTC_WAKEUPTIMER_ENABLE_IT(hrtc,RTC_IT_WUT);
-
-  /* Enable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates wake up timer counter.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @retval HAL status
-  */
-uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  uint32_t tickstart = 0;
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Disable the Wakeup Timer */
-  __HAL_RTC_WAKEUPTIMER_DISABLE(hrtc);
-
-  /* In case of interrupt mode is used, the interrupt source must disabled */
-  __HAL_RTC_WAKEUPTIMER_DISABLE_IT(hrtc,RTC_IT_WUT);
-
-  tickstart = HAL_GetTick();
-  /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTWF) == RESET)
-  {
-    if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_TIMEOUT;
-    }
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Gets wake up timer counter.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @retval Counter value
-  */
-uint32_t HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc)
-{
-  /* Get the counter value */
-  return ((uint32_t)(hrtc->Instance->WUTR & RTC_WUTR_WUT));
-}
-
-/**
-  * @brief  This function handles Wake Up Timer interrupt request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-void HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc)
-{
-  if(__HAL_RTC_WAKEUPTIMER_GET_IT(hrtc, RTC_IT_WUT))
-  {
-    /* Get the status of the Interrupt */
-    if((uint32_t)(hrtc->Instance->CR & RTC_IT_WUT) != (uint32_t)RESET)
-    {
-      /* WAKEUPTIMER callback */
-      HAL_RTCEx_WakeUpTimerEventCallback(hrtc);
-
-      /* Clear the WAKEUPTIMER interrupt pending bit */
-      __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-    }
-  }
-
-  /* Clear the EXTI s line Flag for RTC WakeUpTimer */
-  __HAL_RTC_CLEAR_FLAG(RTC_EXTI_LINE_WAKEUPTIMER_EVENT);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-}
-
-/**
-  * @brief  Wake Up Timer callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_WakeUpTimerEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles Wake Up Timer Polling.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{
-  uint32_t tickstart = HAL_GetTick();
-
-  while(__HAL_RTC_WAKEUPTIMER_GET_FLAG(hrtc, RTC_FLAG_WUTF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-      
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Clear the WAKEUPTIMER Flag */
-  __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(hrtc, RTC_FLAG_WUTF);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Exported_Functions_Group7 Extended Peripheral Control functions
-  * @brief    Extended Peripheral Control functions
-  *
-@verbatim   
- ===============================================================================
-              ##### Extension Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides functions allowing to
-      (+) Writes a data in a specified RTC Backup data register
-      (+) Read a data in a specified RTC Backup data register
-      (+) Sets the Coarse calibration parameters.
-      (+) Deactivates the Coarse calibration parameters
-      (+) Sets the Smooth calibration parameters.
-      (+) Configures the Synchronization Shift Control Settings.
-      (+) Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-      (+) Enables the RTC reference clock detection.
-      (+) Disable the RTC reference clock detection.
-      (+) Enables the Bypass Shadow feature.
-      (+) Disables the Bypass Shadow feature.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Writes a data in a specified RTC Backup data register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
-  *                                 specify the register.
-  * @param  Data: Data to be written in the specified RTC Backup data register.                     
-  * @retval None
-  */
-void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-  
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4);
-
-  /* Write the specified register */
-  *(__IO uint32_t *)tmp = (uint32_t)Data;
-}
-
-/**
-  * @brief  Reads data from the specified RTC Backup data Register.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC. 
-  * @param  BackupRegister: RTC Backup data Register number.
-  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
-  *                                 specify the register.                   
-  * @retval Read value
-  */
-uint32_t HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_BKP(BackupRegister));
-
-  tmp = (uint32_t)&(hrtc->Instance->BKP0R);
-  tmp += (BackupRegister * 4);
-
-  /* Read the specified register */
-  return (*(__IO uint32_t *)tmp);
-}
-
-/**
-  * @brief  Sets the Coarse calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @param  CalibSign: Specifies the sign of the coarse calibration value.
-  *          This parameter can be  one of the following values :
-  *             @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive 
-  *             @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative
-  * @param  Value: value of coarse calibration expressed in ppm (coded on 5 bits).
-  *    
-  * @note   This Calibration value should be between 0 and 63 when using negative
-  *         sign with a 2-ppm step.
-  *           
-  * @note   This Calibration value should be between 0 and 126 when using positive
-  *         sign with a 4-ppm step.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef* hrtc, uint32_t CalibSign, uint32_t Value)
-{
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_SIGN(CalibSign));
-  assert_param(IS_RTC_CALIB_VALUE(Value)); 
-  
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  { 
-    /* Enable the Coarse Calibration */
-    __HAL_RTC_COARSE_CALIB_ENABLE(hrtc);
-    
-    /* Set the coarse calibration value */
-    hrtc->Instance->CALIBR = (uint32_t)(CalibSign|Value);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-  } 
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Coarse calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef* hrtc)
-{ 
-  /* Process Locked */ 
-  __HAL_LOCK(hrtc);
-  
-  hrtc->State = HAL_RTC_STATE_BUSY;
-  
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc); 
-    
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-    
-    /* Process Unlocked */ 
-    __HAL_UNLOCK(hrtc);
-    
-    return HAL_ERROR;
-  } 
-  else
-  { 
-    /* Enable the Coarse Calibration */
-    __HAL_RTC_COARSE_CALIB_DISABLE(hrtc);
-    
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT; 
-  } 
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-  
-  /* Change state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  /* Process Unlocked */ 
-  __HAL_UNLOCK(hrtc);
-  
-  return HAL_OK;
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-/**
-  * @brief  Sets the Smooth calibration parameters.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @param  SmoothCalibPeriod: Select the Smooth Calibration Period.
-  *          This parameter can be can be one of the following values :
-  *             @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration periode is 32s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration periode is 16s.
-  *             @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibartion periode is 8s.
-  * @param  SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
-  *          This parameter can be one of the following values:
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK puls every 2*11 pulses.
-  *             @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
-  * @param  SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
-  *          This parameter can be one any value from 0 to 0x000001FF.
-  * @note   To deactivate the smooth calibration, the field SmoothCalibPlusPulses 
-  *         must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field 
-  *         SmouthCalibMinusPulsesValue must be equal to 0.  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef* hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(SmoothCalibPeriod));
-  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(SmoothCalibPlusPulses));
-  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(SmouthCalibMinusPulsesValue));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* check if a calibration is pending*/
-  if((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
-  {
-    tickstart = HAL_GetTick();
-
-    /* check if a calibration is pending*/
-    while((hrtc->Instance->ISR & RTC_ISR_RECALPF) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        /* Change RTC state */
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-
-  /* Configure the Smooth calibration settings */
-  hrtc->Instance->CALR = (uint32_t)((uint32_t)SmoothCalibPeriod | (uint32_t)SmoothCalibPlusPulses | (uint32_t)SmouthCalibMinusPulsesValue);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the Synchronization Shift Control Settings.
-  * @note   When REFCKON is set, firmware must not write to Shift control register. 
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @param  ShiftAdd1S: Select to add or not 1 second to the time calendar.
-  *          This parameter can be one of the following values :
-  *             @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar. 
-  *             @arg RTC_SHIFTADD1S_RESET: No effect.
-  * @param  ShiftSubFS: Select the number of Second Fractions to substitute.
-  *          This parameter can be one any value from 0 to 0x7FFF.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef* hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS)
-{
-  uint32_t tickstart = 0;
-
-  /* Check the parameters */
-  assert_param(IS_RTC_SHIFT_ADD1S(ShiftAdd1S));
-  assert_param(IS_RTC_SHIFT_SUBFS(ShiftSubFS));
-
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-    tickstart = HAL_GetTick();
-
-    /* Wait until the shift is completed*/
-    while((hrtc->Instance->ISR & RTC_ISR_SHPF) != RESET)
-    {
-      if((HAL_GetTick() - tickstart ) >  RTC_TIMEOUT_VALUE)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_TIMEOUT;
-      }
-    }
-
-    /* Check if the reference clock detection is disabled */
-    if((hrtc->Instance->CR & RTC_CR_REFCKON) == RESET)
-    {
-      /* Configure the Shift settings */
-      hrtc->Instance->SHIFTR = (uint32_t)(uint32_t)(ShiftSubFS) | (uint32_t)(ShiftAdd1S);
-
-      /* Wait for synchro */
-      if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
-      {
-        /* Enable the write protection for RTC registers */
-        __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-        hrtc->State = HAL_RTC_STATE_ERROR;
-
-        /* Process Unlocked */
-        __HAL_UNLOCK(hrtc);
-
-        return HAL_ERROR;
-      }
-    }
-    else
-    {
-      /* Enable the write protection for RTC registers */
-      __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-      /* Change RTC state */
-      hrtc->State = HAL_RTC_STATE_ERROR;
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hrtc);
-
-      return HAL_ERROR;
-    }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-/**
-  * @brief  Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @param  CalibOutput : Select the Calibration output Selection .
-  *          This parameter can be one of the following values:
-  *             @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz. 
-  *             @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc, uint32_t CalibOutput)
-#else
-/**
-  * @brief  Configure the Calibration Pinout (RTC_CALIB).
-  * @param  hrtc : RTC handle    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef* hrtc)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-{
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  /* Check the parameters */
-  assert_param(IS_RTC_CALIB_OUTPUT(CalibOutput));
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  /* Clear flags before config */
-  hrtc->Instance->CR &= (uint32_t)~RTC_CR_COSEL;
-
-  /* Configure the RTC_CR register */
-  hrtc->Instance->CR |= (uint32_t)CalibOutput;
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(hrtc);
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Enables the RTC reference clock detection.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_ENABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-   /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disable the RTC reference clock detection.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set Initialization mode */
-  if(RTC_EnterInitMode(hrtc) != HAL_OK)
-  {
-    /* Enable the write protection for RTC registers */
-    __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-    /* Set RTC state*/
-    hrtc->State = HAL_RTC_STATE_ERROR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hrtc);
-
-    return HAL_ERROR;
-  }
-  else
-  {
-    __HAL_RTC_CLOCKREF_DETECTION_DISABLE(hrtc);
-
-    /* Exit Initialization mode */
-    hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-  }
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-/**
-  * @brief  Enables the Bypass Shadow feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @note   When the Bypass Shadow is enabled the calendar value are taken 
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Set the BYPSHAD bit */
-  hrtc->Instance->CR |= (uint8_t)RTC_CR_BYPSHAD;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Disables the Bypass Shadow feature.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.  
-  * @note   When the Bypass Shadow is enabled the calendar value are taken
-  *         directly from the Calendar counter.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef* hrtc)
-{
-  /* Process Locked */
-  __HAL_LOCK(hrtc);
-
-  hrtc->State = HAL_RTC_STATE_BUSY;
-
-  /* Disable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_DISABLE(hrtc);
-
-  /* Reset the BYPSHAD bit */
-  hrtc->Instance->CR &= (uint8_t)~RTC_CR_BYPSHAD;
-
-  /* Enable the write protection for RTC registers */
-  __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY;
-
-  /* Process Unlocked */
-  __HAL_UNLOCK(hrtc);
-
-  return HAL_OK;
-}
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Exported_Functions_Group8 Extended features functions
-  * @brief    Extended features functions
-  *
-@verbatim   
- ===============================================================================
-                 ##### Extended features functions #####
- ===============================================================================  
-    [..]  This section provides functions allowing to:
-      (+) RTC Alram B callback
-      (+) RTC Poll for Alarm B request
-               
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Alarm B callback.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @retval None
-  */
-__weak void HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_RTCEx_AlarmBEventCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  This function handles AlarmB Polling request.
-  * @param  hrtc: pointer to a RTC_HandleTypeDef structure that contains
-  *                the configuration information for RTC.
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
-{  
-  uint32_t tickstart = HAL_GetTick();
-  
-  while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBF) == RESET)
-  {
-    if(Timeout != HAL_MAX_DELAY)
-    {
-      if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-      {
-        hrtc->State = HAL_RTC_STATE_TIMEOUT;
-        return HAL_TIMEOUT;
-      }
-    }
-  }
-  
-  /* Clear the Alarm Flag */
-  __HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
-  
-  /* Change RTC state */
-  hrtc->State = HAL_RTC_STATE_READY; 
-  
-  return HAL_OK; 
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-#endif /* HAL_RTC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_rtc_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,973 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_rtc_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of RTC HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************  
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_RTC_EX_H
-#define __STM32L1xx_HAL_RTC_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup RTCEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup RTCEx_Exported_Types RTCEx Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  RTC Tamper structure definition  
-  */
-typedef struct 
-{
-  uint32_t Tamper;                      /*!< Specifies the Tamper Pin.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Pins_Definitions */
-  
-  uint32_t Trigger;                     /*!< Specifies the Tamper Trigger.
-                                             This parameter can be a value of @ref  RTCEx_Tamper_Trigger_Definitions */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-  uint32_t Filter;                      /*!< Specifies the RTC Filter Tamper.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Filter_Definitions */
-  
-  uint32_t SamplingFrequency;           /*!< Specifies the sampling frequency.
-                                             This parameter can be a value of @ref RTCEx_Tamper_Sampling_Frequencies_Definitions */
-                                      
-  uint32_t PrechargeDuration;           /*!< Specifies the Precharge Duration .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pin_Precharge_Duration_Definitions */ 
- 
-  uint32_t TamperPullUp;                /*!< Specifies the Tamper PullUp .
-                                             This parameter can be a value of @ref RTCEx_Tamper_Pull_Up_Definitions */           
- 
-  uint32_t TimeStampOnTamperDetection;  /*!< Specifies the TimeStampOnTamperDetection.
-                                             This parameter can be a value of @ref RTCEx_Tamper_TimeStampOnTamperDetection_Definitions */                      
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-}RTC_TamperTypeDef;
-
-/** 
-  * @brief  RTC Time structure definition  
-  */
-typedef struct
-{
-  uint8_t Hours;            /*!< Specifies the RTC Time Hour.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 12 if the RTC_HourFormat_12 is selected
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HourFormat_24 is selected  */
-
-  uint8_t Minutes;          /*!< Specifies the RTC Time Minutes.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-  
-  uint8_t Seconds;          /*!< Specifies the RTC Time Seconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-  
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-  uint32_t SubSeconds;      /*!< Specifies the RTC Time SubSeconds.
-                                 This parameter must be a number between Min_Data = 0 and Max_Data = 59 */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-  
-  uint8_t TimeFormat;       /*!< Specifies the RTC AM/PM Time.
-                                 This parameter can be a value of @ref RTC_AM_PM_Definitions */ 
-  
-  uint32_t DayLightSaving;  /*!< Specifies RTC_DayLightSaveOperation: the value of hour adjustment. 
-                                 This parameter can be a value of @ref RTC_DayLightSaving_Definitions */
-  
-  uint32_t StoreOperation;  /*!< Specifies RTC_StoreOperation value to be written in the BCK bit 
-                                 in CR register to store the operation.
-                                 This parameter can be a value of @ref RTC_StoreOperation_Definitions */
-}RTC_TimeTypeDef; 
-
-/** 
-  * @brief  RTC Alarm structure definition  
-  */
-typedef struct
-{
-  RTC_TimeTypeDef AlarmTime;     /*!< Specifies the RTC Alarm Time members */
-    
-  uint32_t AlarmMask;            /*!< Specifies the RTC Alarm Masks.
-                                      This parameter can be a value of @ref RTC_AlarmMask_Definitions */
-  
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-  uint32_t AlarmSubSecondMask;   /*!< Specifies the RTC Alarm SubSeconds Masks.
-                                      This parameter can be a value of @ref RTC_Alarm_Sub_Seconds_Masks_Definitions */                                   
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-  uint32_t AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
-                                      This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
-  
-  uint8_t AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
-                                      If the Alarm Date is selected, this parameter must be set to a value in the 1-31 range.
-                                      If the Alarm WeekDay is selected, this parameter can be a value of @ref RTC_WeekDay_Definitions */
-                                                                     
-  uint32_t Alarm;                /*!< Specifies the alarm .
-                                      This parameter can be a value of @ref RTC_Alarms_Definitions */                            
-}RTC_AlarmTypeDef;
-/**
-  * @}
-  */ 
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Constants RTCEx Exported Constants
-  * @{
-  */ 
-  
-/** @defgroup RTC_Masks_Definitions Masks Definitions
-  * @{
-  */  
-#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
-#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
-#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
-#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \
-                                            RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \
-                                            RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \
-                                            RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
-                                            RTC_FLAG_TAMP1F | RTC_FLAG_TAMP2F | RTC_FLAG_TAMP3F | \
-                                            RTC_FLAG_RECALPF))
-#else
-#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_ALRAWF | RTC_FLAG_ALRBWF | RTC_FLAG_WUTWF | \
-                                            RTC_FLAG_SHPF | RTC_FLAG_INITS | RTC_FLAG_RSF | \
-                                            RTC_FLAG_INITF | RTC_FLAG_ALRAF | RTC_FLAG_ALRBF | \
-                                            RTC_FLAG_WUTF | RTC_FLAG_TSF | RTC_FLAG_TSOVF | \
-                                            RTC_FLAG_TAMP1F | \
-                                            RTC_FLAG_RECALPF))
-
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-  
-/** @defgroup RTC_Synchronous_Predivider Synchronous Predivider 
-  * @{
-  */ 
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x7FFF)
-#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= (uint32_t)0x1FFF)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */ 
-
-/** @defgroup RTC_Interrupts_Definitions Interrupts Definitions 
-  * @{
-  */ 
-#define RTC_IT_TS                         ((uint32_t)0x00008000)
-#define RTC_IT_WUT                        ((uint32_t)0x00004000)
-#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
-#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
-#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-#define RTC_IT_TAMP2                      ((uint32_t)0x00040000)
-#define RTC_IT_TAMP3                      ((uint32_t)0x00080000)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Flags_Definitions Flags Definitions 
-  * @{
-  */ 
-#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-#define RTC_FLAG_TAMP3F                   ((uint32_t)0x00008000)
-#define RTC_FLAG_TAMP2F                   ((uint32_t)0x00004000)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
-#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
-#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
-#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
-#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
-#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
-#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
-#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
-#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
-#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
-#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Output_selection_Definitions Output selection Definitions 
-  * @{
-  */ 
-#define RTC_OUTPUT_DISABLE             ((uint32_t)0x00000000)
-#define RTC_OUTPUT_ALARMA              ((uint32_t)0x00200000)
-#define RTC_OUTPUT_ALARMB              ((uint32_t)0x00400000)
-#define RTC_OUTPUT_WAKEUP              ((uint32_t)0x00600000)
- 
-#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_OUTPUT_DISABLE) || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMA)  || \
-                               ((OUTPUT) == RTC_OUTPUT_ALARMB)  || \
-                               ((OUTPUT) == RTC_OUTPUT_WAKEUP))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTCEx_Backup_Registers_Definitions Backup Registers Definitions 
-  * @{
-  */
-#if RTC_BKP_NUMBER > 0
-#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
-#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
-#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
-#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
-#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
-#endif /* RTC_BKP_NUMBER > 0 */
-   
-#if RTC_BKP_NUMBER > 5
-#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
-#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
-#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
-#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
-#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
-#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
-#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
-#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
-#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
-#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
-#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
-#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
-#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
-#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
-#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
-#endif /* RTC_BKP_NUMBER > 5 */
-   
-#if RTC_BKP_NUMBER > 20
-#define RTC_BKP_DR20                      ((uint32_t)0x00000014)
-#define RTC_BKP_DR21                      ((uint32_t)0x00000015)
-#define RTC_BKP_DR22                      ((uint32_t)0x00000016)
-#define RTC_BKP_DR23                      ((uint32_t)0x00000017)
-#define RTC_BKP_DR24                      ((uint32_t)0x00000018)
-#define RTC_BKP_DR25                      ((uint32_t)0x00000019)
-#define RTC_BKP_DR26                      ((uint32_t)0x0000001A)
-#define RTC_BKP_DR27                      ((uint32_t)0x0000001B)
-#define RTC_BKP_DR28                      ((uint32_t)0x0000001C)
-#define RTC_BKP_DR29                      ((uint32_t)0x0000001D)
-#define RTC_BKP_DR30                      ((uint32_t)0x0000001E)
-#define RTC_BKP_DR31                      ((uint32_t)0x0000001F)
-#endif /* RTC_BKP_NUMBER > 20 */
-   
-#define IS_RTC_BKP(BKP)                   ((BKP) < (uint32_t) RTC_BKP_NUMBER)
-/**
-  * @}
-  */ 
-
-/** @defgroup RTCEx_Time_Stamp_Edges_Definitions Time Stamp Edges Definitions
-  * @{
-  */
-#define RTC_TIMESTAMPEDGE_RISING          ((uint32_t)0x00000000)
-#define RTC_TIMESTAMPEDGE_FALLING         ((uint32_t)0x00000008)
-
-#define IS_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TIMESTAMPEDGE_RISING) || \
-                                 ((EDGE) == RTC_TIMESTAMPEDGE_FALLING))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pins_Definitions Tamper Pins Definitions
-  * @{
-  */
-#define RTC_TAMPER_1                    RTC_TAFCR_TAMP1E
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-#define RTC_TAMPER_2                    RTC_TAFCR_TAMP2E
-#define RTC_TAMPER_3                    RTC_TAFCR_TAMP3E
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define IS_TAMPER(TAMPER) (((~(RTC_TAMPER_1|RTC_TAMPER_2|RTC_TAMPER_3) & (TAMPER)) == (uint32_t)RESET) && ((TAMPER) != (uint32_t)RESET))
-#else
-#define IS_TAMPER(TAMPER) ((TAMPER) == RTC_TAMPER_1)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Trigger_Definitions Tamper Trigger Definitions 
-  * @{
-  */ 
-#define RTC_TAMPERTRIGGER_RISINGEDGE       ((uint32_t)0x00000000)
-#define RTC_TAMPERTRIGGER_FALLINGEDGE      ((uint32_t)0x00000002)
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-#define RTC_TAMPERTRIGGER_LOWLEVEL         RTC_TAMPERTRIGGER_RISINGEDGE
-#define RTC_TAMPERTRIGGER_HIGHLEVEL        RTC_TAMPERTRIGGER_FALLINGEDGE
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_LOWLEVEL) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_HIGHLEVEL)) 
-#elif defined(STM32L100xB) || defined (STM32L151xB) || defined (STM32L152xB)
-#define IS_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TAMPERTRIGGER_RISINGEDGE) || \
-                                        ((TRIGGER) == RTC_TAMPERTRIGGER_FALLINGEDGE)) 
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */  
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-/** @defgroup RTCEx_Tamper_Filter_Definitions Tamper Filter Definitions 
-  * @{
-  */ 
-#define RTC_TAMPERFILTER_DISABLE   ((uint32_t)0x00000000)  /*!< Tamper filter is disabled */
-
-#define RTC_TAMPERFILTER_2SAMPLE   ((uint32_t)0x00000800)  /*!< Tamper is activated after 2 
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_4SAMPLE   ((uint32_t)0x00001000)  /*!< Tamper is activated after 4 
-                                                                consecutive samples at the active level */
-#define RTC_TAMPERFILTER_8SAMPLE   ((uint32_t)0x00001800)  /*!< Tamper is activated after 8 
-                                                                consecutive samples at the active level. */
-
-#define IS_TAMPER_FILTER(FILTER)  (((FILTER) == RTC_TAMPERFILTER_DISABLE) || \
-                                   ((FILTER) == RTC_TAMPERFILTER_2SAMPLE) || \
-                                   ((FILTER) == RTC_TAMPERFILTER_4SAMPLE) || \
-                                   ((FILTER) == RTC_TAMPERFILTER_8SAMPLE))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Sampling_Frequencies_Definitions Tamper Sampling Frequencies 
-  * @{
-  */ 
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768  ((uint32_t)0x00000000)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 32768 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384  ((uint32_t)0x00000100)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 16384 */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192   ((uint32_t)0x00000200)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 8192  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096   ((uint32_t)0x00000300)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 4096  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048   ((uint32_t)0x00000400)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 2048  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024   ((uint32_t)0x00000500)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 1024  */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512    ((uint32_t)0x00000600)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 512   */
-#define RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256    ((uint32_t)0x00000700)  /*!< Each of the tamper inputs are sampled
-                                                                             with a frequency =  RTCCLK / 256   */
-
-#define IS_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV32768)|| \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV16384)|| \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV8192) || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV4096) || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV2048) || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV1024) || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV512)  || \
-                                       ((FREQ) == RTC_TAMPERSAMPLINGFREQ_RTCCLK_DIV256))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pin_Precharge_Duration_Definitions Tamper Pin Precharge Duration
-  * @{
-  */
-#define RTC_TAMPERPRECHARGEDURATION_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 1 RTCCLK cycle */
-#define RTC_TAMPERPRECHARGEDURATION_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 2 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 4 RTCCLK cycles */
-#define RTC_TAMPERPRECHARGEDURATION_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before
-                                                                         sampling during 8 RTCCLK cycles */
-
-#define IS_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TAMPERPRECHARGEDURATION_1RTCCLK) || \
-                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_2RTCCLK) || \
-                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_4RTCCLK) || \
-                                                ((DURATION) == RTC_TAMPERPRECHARGEDURATION_8RTCCLK))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_TimeStampOnTamperDetection_Definitions TimeStampOnTamperDetection Definitions
-  * @{
-  */
-#define RTC_TIMESTAMPONTAMPERDETECTION_ENABLE  ((uint32_t)RTC_TAFCR_TAMPTS)  /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TIMESTAMPONTAMPERDETECTION_DISABLE ((uint32_t)0x00000000)        /*!< TimeStamp on Tamper Detection event is not saved */
-
-#define IS_TAMPER_TIMESTAMPONTAMPER_DETECTION(DETECTION) (((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_ENABLE) || \
-                                                          ((DETECTION) == RTC_TIMESTAMPONTAMPERDETECTION_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Tamper_Pull_Up_Definitions Tamper Pull-Up Definitions
-  * @{
-  */
-#define RTC_TAMPER_PULLUP_ENABLE  ((uint32_t)0x00000000)            /*!< TimeStamp on Tamper Detection event saved */
-#define RTC_TAMPER_PULLUP_DISABLE ((uint32_t)RTC_TAFCR_TAMPPUDIS)   /*!< TimeStamp on Tamper Detection event is not saved */
-
-#define IS_TAMPER_PULLUP_STATE(STATE) (((STATE) == RTC_TAMPER_PULLUP_ENABLE) || \
-                                       ((STATE) == RTC_TAMPER_PULLUP_DISABLE))
-/**
-  * @}
-  */
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/** @defgroup RTCEx_Wakeup_Timer_Definitions Wakeup Timer Definitions
-  * @{
-  */
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV16        ((uint32_t)0x00000000)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV8         ((uint32_t)0x00000001)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV4         ((uint32_t)0x00000002)
-#define RTC_WAKEUPCLOCK_RTCCLK_DIV2         ((uint32_t)0x00000003)
-#define RTC_WAKEUPCLOCK_CK_SPRE_16BITS      ((uint32_t)0x00000004)
-#define RTC_WAKEUPCLOCK_CK_SPRE_17BITS      ((uint32_t)0x00000006)
-
-#define IS_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV16)   || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV8)    || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV4)    || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_RTCCLK_DIV2)    || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_16BITS) || \
-                                ((CLOCK) == RTC_WAKEUPCLOCK_CK_SPRE_17BITS))
-
-#define IS_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Digital_Calibration_Definitions Digital Calibration Definitions 
-  * @{
-  */ 
-#define RTC_CALIBSIGN_POSITIVE            ((uint32_t)0x00000000) 
-#define RTC_CALIBSIGN_NEGATIVE            ((uint32_t)0x00000080)
-
-#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CALIBSIGN_POSITIVE) || \
-                                 ((SIGN) == RTC_CALIBSIGN_NEGATIVE))
-
-#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_Calib_Period_Definitions Smooth Calib Period Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PERIOD_32SEC   ((uint32_t)0x00000000) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
-                                                                    period is 32s,  else 2exp20 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_16SEC   ((uint32_t)0x00002000) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
-                                                                    period is 16s, else 2exp19 RTCCLK seconds */
-#define RTC_SMOOTHCALIB_PERIOD_8SEC    ((uint32_t)0x00004000) /*!<  If RTCCLK = 32768 Hz, Smooth calibation
-                                                                    period is 8s, else 2exp18 RTCCLK seconds */
-
-#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SMOOTHCALIB_PERIOD_32SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_16SEC) || \
-                                            ((PERIOD) == RTC_SMOOTHCALIB_PERIOD_8SEC))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_Calib_Plus_Pulses_Definitions Smooth Calib Plus Pulses Definitions
-  * @{
-  */
-#define RTC_SMOOTHCALIB_PLUSPULSES_SET    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added
-                                                                       during a X -second window = Y - CALM[8:0]
-                                                                       with Y = 512, 256, 128 when X = 32, 16, 8 */
-#define RTC_SMOOTHCALIB_PLUSPULSES_RESET  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
-                                                                       during a 32-second window =   CALM[8:0] */
-
-#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_SET) || \
-                                        ((PLUS) == RTC_SMOOTHCALIB_PLUSPULSES_RESET))
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Smooth_Calib_Minus_Pulses_Definitions Smooth Calib Minus Pulses Definitions
-  * @{
-  */
-#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Add_1_Second_Parameter_Definitions Add 1 Second Parameter Definitions
-  * @{
-  */ 
-#define RTC_SHIFTADD1S_RESET      ((uint32_t)0x00000000)
-#define RTC_SHIFTADD1S_SET        ((uint32_t)0x80000000)
-
-#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_SHIFTADD1S_RESET) || \
-                                 ((SEL) == RTC_SHIFTADD1S_SET))
-/**
-  * @}
-  */ 
-
-/** @defgroup RTCEx_Substract_Fraction_Of_Second_Value Substract Fraction Of Second Value
-  * @{
-  */ 
-#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
-/**
-  * @}
-  */
-
-/** @defgroup RTCEx_Calib_Output_Selection_Definitions Calib Output Selection Definitions 
-  * @{
-  */ 
-#define RTC_CALIBOUTPUT_512HZ            ((uint32_t)0x00000000) 
-#define RTC_CALIBOUTPUT_1HZ              ((uint32_t)0x00080000)
-
-#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CALIBOUTPUT_512HZ) || \
-                                      ((OUTPUT) == RTC_CALIBOUTPUT_1HZ))
-/**
-  * @}
-  */ 
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) 
-/** @defgroup RTC_Alarm_Sub_Seconds_Value Alarm Sub Seconds Value
-  * @{
-  */ 
-#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= (uint32_t)0x00007FFF)
-/**
-  * @}
-  */
-
-/** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions Alarm Sub Seconds Masks Definitions
-  * @{
-  */ 
-#define RTC_ALARMSUBSECONDMASK_ALL         ((uint32_t)0x00000000)  /*!< All Alarm SS fields are masked. 
-                                                                        There is no comparison on sub seconds 
-                                                                        for Alarm */
-#define RTC_ALARMSUBSECONDMASK_SS14_1      ((uint32_t)0x01000000)  /*!< SS[14:1] are don't care in Alarm 
-                                                                        comparison. Only SS[0] is compared.    */
-#define RTC_ALARMSUBSECONDMASK_SS14_2      ((uint32_t)0x02000000)  /*!< SS[14:2] are don't care in Alarm 
-                                                                        comparison. Only SS[1:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_3      ((uint32_t)0x03000000)  /*!< SS[14:3] are don't care in Alarm 
-                                                                        comparison. Only SS[2:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_4      ((uint32_t)0x04000000)  /*!< SS[14:4] are don't care in Alarm 
-                                                                        comparison. Only SS[3:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_5      ((uint32_t)0x05000000)  /*!< SS[14:5] are don't care in Alarm 
-                                                                        comparison. Only SS[4:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_6      ((uint32_t)0x06000000)  /*!< SS[14:6] are don't care in Alarm 
-                                                                        comparison. Only SS[5:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_7      ((uint32_t)0x07000000)  /*!< SS[14:7] are don't care in Alarm 
-                                                                        comparison. Only SS[6:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_8      ((uint32_t)0x08000000)  /*!< SS[14:8] are don't care in Alarm 
-                                                                        comparison. Only SS[7:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_9      ((uint32_t)0x09000000)  /*!< SS[14:9] are don't care in Alarm 
-                                                                        comparison. Only SS[8:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_10     ((uint32_t)0x0A000000)  /*!< SS[14:10] are don't care in Alarm 
-                                                                        comparison. Only SS[9:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_11     ((uint32_t)0x0B000000)  /*!< SS[14:11] are don't care in Alarm 
-                                                                        comparison. Only SS[10:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14_12     ((uint32_t)0x0C000000)  /*!< SS[14:12] are don't care in Alarm 
-                                                                        comparison.Only SS[11:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_SS14_13     ((uint32_t)0x0D000000)  /*!< SS[14:13] are don't care in Alarm 
-                                                                        comparison. Only SS[12:0] are compared */
-#define RTC_ALARMSUBSECONDMASK_SS14        ((uint32_t)0x0E000000)  /*!< SS[14] is don't care in Alarm 
-                                                                        comparison.Only SS[13:0] are compared  */
-#define RTC_ALARMSUBSECONDMASK_NONE        ((uint32_t)0x0F000000)  /*!< SS[14:0] are compared and must match 
-                                                                        to activate alarm. */
-
-#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_ALARMSUBSECONDMASK_ALL) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_1) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_2) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_3) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_4) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_5) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_6) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_7) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_8) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_9) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_10) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_11) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_12) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14_13) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_SS14) || \
-                                              ((MASK) == RTC_ALARMSUBSECONDMASK_NONE))
-/**
-  * @}
-  */   
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup RTCEx_Exported_Macros RTCEx Exported Macros
-  * @{
-  */
-  
-/**
-  * @brief Enable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
-
-/**
-  * @brief Enable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__)                        ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
-
-/**
-  * @brief Disable the RTC WakeUp Timer peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__)                     ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
-
-/**
-  * @brief Disable the RTC TimeStamp peripheral.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
-
-/**
-  * @brief  Enable the Coarse calibration process.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__)                       ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
-
-/**
-  * @brief  Disable the Coarse calibration process.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__)                      ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
-
-/**
-  * @brief  Enable the RTC calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
-
-/**
-  * @brief  Disable the calibration output.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
-
-/**
-  * @brief  Enable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
-
-/**
-  * @brief  Disable the clock reference detection.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @retval None
-  */
-#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__)                ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
-
-/**
-  * @brief  Enable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
-  *         This parameter can be:
-  *             @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_ENABLE_IT(__HANDLE__, __INTERRUPT__)      ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Enable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC TimeStamp interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. 
-  *          This parameter can be:
-  *             @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_DISABLE_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Disable the RTC WakeUpTimer interrupt.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. 
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1
-  *            @arg  RTC_IT_TAMP2
-  *            @arg  RTC_IT_TAMP3
-  * @retval None
-  */
-#else
-/**
-  * @brief  Check whether the specified RTC Tamper interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg  RTC_IT_TAMP1
-  * @retval None
-  */
-#endif
-#define __HAL_RTC_TAMPER_GET_IT(__HANDLE__, __FLAG__)                 (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_WUT:  WakeUpTimer A interrupt
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_IT(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Check whether the specified RTC TimeStamp interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_IT_TS: TimeStamp interrupt
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_IT(__HANDLE__, __FLAG__)              (((((__HANDLE__)->Instance->ISR) & ((__FLAG__)>> 4)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC TimeStamp's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC TimeStamp Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TSF   
-  *            @arg RTC_FLAG_TSOVF     
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_GET_FLAG(__HANDLE__, __FLAG__)            (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC WakeUpTimer's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC WakeUpTimer Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF   
-  *            @arg RTC_FLAG_WUTWF     
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_GET_FLAG(__HANDLE__, __FLAG__)          (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-/**
-  * @brief  Get the selected RTC Tamper's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TAMP1F      
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_GET_FLAG(__HANDLE__, __FLAG__)               (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-/**
-  * @brief  Get the selected RTC shift operation's flag status.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC shift operation Flag is pending or not.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_SHPF   
-  * @retval None
-  */
-#define __HAL_RTC_SHIFT_GET_FLAG(__HANDLE__, __FLAG__)                (((((__HANDLE__)->Instance->ISR) & (__FLAG__)) != RESET)? SET : RESET)
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-
-/**
-  * @brief  Clear the RTC Time Stamp's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TSF  
-  * @retval None
-  */
-#define __HAL_RTC_TIMESTAMP_CLEAR_FLAG(__HANDLE__, __FLAG__)              ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Clear the RTC Tamper's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_TAMP1F  
-  * @retval None
-  */
-#define __HAL_RTC_TAMPER_CLEAR_FLAG(__HANDLE__, __FLAG__)                 ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT))
-
-/**
-  * @brief  Clear the RTC Wake Up timer's pending flags.
-  * @param  __HANDLE__: specifies the RTC handle.
-  * @param  __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
-  *         This parameter can be:
-  *            @arg RTC_FLAG_WUTF   
-  * @retval None
-  */
-#define __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(__HANDLE__, __FLAG__)            ((__HANDLE__)->Instance->ISR) = (~(((__FLAG__) | RTC_ISR_INIT)& 0x0000FFFF)|((__HANDLE__)->Instance->ISR & RTC_ISR_INIT)) 
-
-/**
-  * @}
-  */ 
-  
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup RTCEx_Exported_Functions
-  * @{
-  */
-  
-/* RTC TimeStamp and Tamper functions *****************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group4
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge);
-HAL_StatusTypeDef HAL_RTCEx_SetTimeStamp_IT(RTC_HandleTypeDef *hrtc, uint32_t TimeStampEdge);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef *sTimeStamp, RTC_DateTypeDef *sTimeStampDate, uint32_t Format);
-
-HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateTamper(RTC_HandleTypeDef *hrtc, uint32_t Tamper);
-void              HAL_RTCEx_TamperTimeStampIRQHandler(RTC_HandleTypeDef *hrtc);
-
-void              HAL_RTCEx_Tamper1EventCallback(RTC_HandleTypeDef *hrtc);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-void              HAL_RTCEx_Tamper2EventCallback(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-void              HAL_RTCEx_TimeStampEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-/**
-  * @}
-  */
-  
-/* RTC Wake-up functions ******************************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group5
-  * @{
-  */
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock);
-uint32_t          HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc);
-uint32_t          HAL_RTCEx_GetWakeUpTimer(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerIRQHandler(RTC_HandleTypeDef *hrtc);
-void              HAL_RTCEx_WakeUpTimerEventCallback(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */ 
-  
-/* Extension Control functions ************************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group7
-  * @{
-  */
-void              HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data);
-uint32_t          HAL_RTCEx_BKUPRead(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister);
-
-HAL_StatusTypeDef HAL_RTCEx_SetCoarseCalib(RTC_HandleTypeDef *hrtc, uint32_t CalibSign, uint32_t Value);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCoarseCalib(RTC_HandleTypeDef *hrtc);
-#if defined(STM32L100xBA) || defined (STM32L151xBA) || defined (STM32L152xBA) || defined(STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined(STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined(STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)   
-HAL_StatusTypeDef HAL_RTCEx_SetSmoothCalib(RTC_HandleTypeDef *hrtc, uint32_t SmoothCalibPeriod, uint32_t SmoothCalibPlusPulses, uint32_t SmouthCalibMinusPulsesValue);
-HAL_StatusTypeDef HAL_RTCEx_SetSynchroShift(RTC_HandleTypeDef *hrtc, uint32_t ShiftAdd1S, uint32_t ShiftSubFS);
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc, uint32_t CalibOutput);
-#else
-HAL_StatusTypeDef HAL_RTCEx_SetCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-#endif /* STM32L100xBA || STM32L151xBA || STM32L152xBA || STM32L100xC || STM32L151xC || STM32L152xC || STM32L162xC || STM32L151xCA || STM32L151xD || STM32L152xCA || STM32L152xD || STM32L162xCA || STM32L162xD || STM32L151xE || STM32L152xE || STM32L162xE */
-HAL_StatusTypeDef HAL_RTCEx_DeactivateCalibrationOutPut(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_SetRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DeactivateRefClock(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_EnableBypassShadow(RTC_HandleTypeDef *hrtc);
-HAL_StatusTypeDef HAL_RTCEx_DisableBypassShadow(RTC_HandleTypeDef *hrtc);
-/**
-  * @}
-  */ 
-  
-/* Extension RTC features functions *******************************************/
-/** @addtogroup RTCEx_Exported_Functions_Group8
-  * @{
-  */
-void              HAL_RTCEx_AlarmBEventCallback(RTC_HandleTypeDef *hrtc); 
-HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout);
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_RTC_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,3439 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_sd.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   SD card HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Secure Digital (SD) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    This driver implements a high level communication layer for read and write from/to 
-    this memory. The needed STM32 hardware resources (SDIO and GPIO) are performed by 
-    the user in HAL_SD_MspInit() function (MSP layer).                             
-    Basically, the MSP layer configuration should be the same as we provide in the 
-    examples.
-    You can easily tailor this configuration according to hardware resources.
-
-  [..]
-    This driver is a generic layered driver for SDIO memories which uses the HAL 
-    SDIO driver functions to interface with SD and uSD cards devices. 
-    It is used as follows:
- 
-    (#)Initialize the SDIO low level resources by implement the HAL_SD_MspInit() API:
-        (##) Enable the SDIO interface clock using __SDIO_CLK_ENABLE(); 
-        (##) SDIO pins configuration for SD card
-            (+++) Enable the clock for the SDIO GPIOs using the functions __GPIOx_CLK_ENABLE();   
-            (+++) Configure these SDIO pins as alternate function pull-up using HAL_GPIO_Init()
-                  and according to your pin assignment;
-        (##) DMA Configuration if you need to use DMA process (HAL_SD_ReadBlocks_DMA()
-             and HAL_SD_WriteBlocks_DMA() APIs).
-            (+++) Enable the DMAx interface clock using __DMAx_CLK_ENABLE(); 
-            (+++) Configure the DMA using the function HAL_DMA_Init() with predeclared and filled. 
-        (##) NVIC configuration if you need to use interrupt process when using DMA transfer.
-            (+++) Configure the SDIO and DMA interrupt priorities using functions
-                  HAL_NVIC_SetPriority(); DMA priority is superior to SDIO's priority
-            (+++) Enable the NVIC DMA and SDIO IRQs using function HAL_NVIC_EnableIRQ()
-            (+++) SDIO interrupts are managed using the macros __HAL_SD_SDIO_ENABLE_IT() 
-                  and __HAL_SD_SDIO_DISABLE_IT() inside the communication process.
-            (+++) SDIO interrupts pending bits are managed using the macros __HAL_SD_SDIO_GET_IT()
-                  and __HAL_SD_SDIO_CLEAR_IT()
-    (#) At this stage, you can perform SD read/write/erase operations after SD card initialization  
-
-         
-  *** SD Card Initialization and configuration ***
-  ================================================    
-  [..]
-    To initialize the SD Card, use the HAL_SD_Init() function.  It Initializes 
-    the SD Card and put it into StandBy State (Ready for data transfer). 
-    This function provide the following operations:
-  
-    (#) Apply the SD Card initialization process at 400KHz and check the SD Card 
-        type (Standard Capacity or High Capacity). You can change or adapt this 
-        frequency by adjusting the "ClockDiv" field. 
-        The SD Card frequency (SDIO_CK) is computed as follows:
-  
-           SDIO_CK = SDIOCLK / (ClockDiv + 2)
-  
-        In initialization mode and according to the SD Card standard, 
-        make sure that the SDIO_CK frequency doesn't exceed 400KHz.
-  
-    (#) Get the SD CID and CSD data. All these information are managed by the SDCardInfo 
-        structure. This structure provide also ready computed SD Card capacity 
-        and Block size.
-        
-        -@- These information are stored in SD handle structure in case of future use.  
-  
-    (#) Configure the SD Card Data transfer frequency. By Default, the card transfer 
-        frequency is set to 48MHz / (SDIO_TRANSFER_CLK_DIV + 2) = 8MHz. You can change or adapt this frequency by adjusting 
-        the "ClockDiv" field.
-        The SD Card frequency (SDIO_CK) is computed as follows:
-
-           SDIO_CK = SDIOCLK / (ClockDiv + 2) 
-
-        In transfer mode and according to the SD Card standard, make sure that the 
-        SDIO_CK frequency doesn't exceed 25MHz and 50MHz in High-speed mode switch.
-        To be able to use a frequency higher than 24MHz, you should use the SDIO 
-        peripheral in bypass mode. Refer to the corresponding reference manual 
-        for more details.
-  
-    (#) Select the corresponding SD Card according to the address read with the step 2.
-    
-    (#) Configure the SD Card in wide bus mode: 4-bits data.
-  
-  *** SD Card Read operation ***
-  ==============================
-  [..] 
-    (+) You can read from SD card in polling mode by using function HAL_SD_ReadBlocks(). 
-        This function support only 512-byte block length (the block size should be 
-        chosen as 512 byte).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-
-    (+) You can read from SD card in DMA mode by using function HAL_SD_ReadBlocks_DMA().
-        This function support only 512-byte block length (the block size should be 
-        chosen as 512 byte).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckReadOperation(), to insure
-        that the read transfer is done correctly in both DMA and SD sides.
-  
-  *** SD Card Write operation ***
-  =============================== 
-  [..] 
-    (+) You can write to SD card in polling mode by using function HAL_SD_WriteBlocks(). 
-        This function support only 512-byte block length (the block size should be 
-        chosen as 512 byte).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-
-    (+) You can write to SD card in DMA mode by using function HAL_SD_WriteBlocks_DMA().
-        This function support only 512-byte block length (the block size should be 
-        chosen as 512 byte).
-        You can choose either one block read operation or multiple block read operation 
-        by adjusting the "NumberOfBlocks" parameter.
-        After this, you have to call the function HAL_SD_CheckWriteOperation(), to insure
-        that the write transfer is done correctly in both DMA and SD sides.  
-  
-  *** SD card status ***
-  ====================== 
-  [..]
-    (+) At any time, you can check the SD Card status and get the SD card state 
-        by using the HAL_SD_GetStatus() function. This function checks first if the 
-        SD card is still connected and then get the internal SD Card transfer state.     
-    (+) You can also get the SD card SD Status register by using the HAL_SD_SendSDStatus() 
-        function.    
-
-  *** SD HAL driver macros list ***
-  ==================================
-  [..]
-    Below the list of most used macros in SD HAL driver.
-       
-    (+) __HAL_SD_SDIO_ENABLE : Enable the SD device
-    (+) __HAL_SD_SDIO_DISABLE : Disable the SD device
-    (+) __HAL_SD_SDIO_DMA_ENABLE: Enable the SDIO DMA transfer
-    (+) __HAL_SD_SDIO_DMA_DISABLE: Disable the SDIO DMA transfer
-    (+) __HAL_SD_SDIO_ENABLE_IT: Enable the SD device interrupt
-    (+) __HAL_SD_SDIO_DISABLE_IT: Disable the SD device interrupt
-    (+) __HAL_SD_SDIO_GET_FLAG:Check whether the specified SD flag is set or not
-    (+) __HAL_SD_SDIO_CLEAR_FLAG: Clear the SD's pending flags
-      
-    (@) You can refer to the SD HAL driver header file for more useful macros 
-      
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SD SD
-  * @brief SD HAL module driver
-  * @{
-  */
-
-#ifdef HAL_SD_MODULE_ENABLED
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-
-/** @defgroup SD_Private_Define SD Private Define
-  * @{
-  */
-  
-/** 
-  * @brief  SDIO Static flags, TimeOut, FIFO Address  
-  */
-#define SDIO_STATIC_FLAGS               ((uint32_t)(SDIO_FLAG_CCRCFAIL | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_CTIMEOUT |\
-                                                    SDIO_FLAG_DTIMEOUT | SDIO_FLAG_TXUNDERR | SDIO_FLAG_RXOVERR  |\
-                                                    SDIO_FLAG_CMDREND  | SDIO_FLAG_CMDSENT  | SDIO_FLAG_DATAEND  |\
-                                                    SDIO_FLAG_DBCKEND))  
-
-#define SDIO_CMD0TIMEOUT                ((uint32_t)0x00010000)
-
-/** 
-  * @brief  Mask for errors Card Status R1 (OCR Register) 
-  */
-#define SD_OCR_ADDR_OUT_OF_RANGE        ((uint32_t)0x80000000)
-#define SD_OCR_ADDR_MISALIGNED          ((uint32_t)0x40000000)
-#define SD_OCR_BLOCK_LEN_ERR            ((uint32_t)0x20000000)
-#define SD_OCR_ERASE_SEQ_ERR            ((uint32_t)0x10000000)
-#define SD_OCR_BAD_ERASE_PARAM          ((uint32_t)0x08000000)
-#define SD_OCR_WRITE_PROT_VIOLATION     ((uint32_t)0x04000000)
-#define SD_OCR_LOCK_UNLOCK_FAILED       ((uint32_t)0x01000000)
-#define SD_OCR_COM_CRC_FAILED           ((uint32_t)0x00800000)
-#define SD_OCR_ILLEGAL_CMD              ((uint32_t)0x00400000)
-#define SD_OCR_CARD_ECC_FAILED          ((uint32_t)0x00200000)
-#define SD_OCR_CC_ERROR                 ((uint32_t)0x00100000)
-#define SD_OCR_GENERAL_UNKNOWN_ERROR    ((uint32_t)0x00080000)
-#define SD_OCR_STREAM_READ_UNDERRUN     ((uint32_t)0x00040000)
-#define SD_OCR_STREAM_WRITE_OVERRUN     ((uint32_t)0x00020000)
-#define SD_OCR_CID_CSD_OVERWRIETE       ((uint32_t)0x00010000)
-#define SD_OCR_WP_ERASE_SKIP            ((uint32_t)0x00008000)
-#define SD_OCR_CARD_ECC_DISABLED        ((uint32_t)0x00004000)
-#define SD_OCR_ERASE_RESET              ((uint32_t)0x00002000)
-#define SD_OCR_AKE_SEQ_ERROR            ((uint32_t)0x00000008)
-#define SD_OCR_ERRORBITS                ((uint32_t)0xFDFFE008)
-
-/** 
-  * @brief  Masks for R6 Response 
-  */
-#define SD_R6_GENERAL_UNKNOWN_ERROR     ((uint32_t)0x00002000)
-#define SD_R6_ILLEGAL_CMD               ((uint32_t)0x00004000)
-#define SD_R6_COM_CRC_FAILED            ((uint32_t)0x00008000)
-
-#define SD_VOLTAGE_WINDOW_SD            ((uint32_t)0x80100000)
-#define SD_HIGH_CAPACITY                ((uint32_t)0x40000000)
-#define SD_STD_CAPACITY                 ((uint32_t)0x00000000)
-#define SD_CHECK_PATTERN                ((uint32_t)0x000001AA)
-
-#define SD_MAX_VOLT_TRIAL               ((uint32_t)0x0000FFFF)
-#define SD_ALLZERO                      ((uint32_t)0x00000000)
-
-#define SD_WIDE_BUS_SUPPORT             ((uint32_t)0x00040000)
-#define SD_SINGLE_BUS_SUPPORT           ((uint32_t)0x00010000)
-#define SD_CARD_LOCKED                  ((uint32_t)0x02000000)
-
-#define SD_DATATIMEOUT                  ((uint32_t)0xFFFFFFFF)
-#define SD_0TO7BITS                     ((uint32_t)0x000000FF)
-#define SD_8TO15BITS                    ((uint32_t)0x0000FF00)
-#define SD_16TO23BITS                   ((uint32_t)0x00FF0000)
-#define SD_24TO31BITS                   ((uint32_t)0xFF000000)
-#define SD_MAX_DATA_LENGTH              ((uint32_t)0x01FFFFFF)
-
-#define SD_HALFFIFO                     ((uint32_t)0x00000008)
-#define SD_HALFFIFOBYTES                ((uint32_t)0x00000020)
-
-/** 
-  * @brief  Command Class Supported 
-  */
-#define SD_CCCC_LOCK_UNLOCK             ((uint32_t)0x00000080)
-#define SD_CCCC_WRITE_PROT              ((uint32_t)0x00000040)
-#define SD_CCCC_ERASE                   ((uint32_t)0x00000020)
-
-/** 
-  * @brief  Following commands are SD Card Specific commands.
-  *         SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_SDIO_SEND_IF_COND            ((uint32_t)SD_CMD_HS_SEND_EXT_CSD)
-
-/**
-  * @}
-  */
-  
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SD_Private_Functions SD Private Functions
-  * @{
-  */
-  
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr);
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd); 
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus);
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus);
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD);
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA);
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd);
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR);  
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma);
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */
-  
-/** @defgroup SD_Exported_Functions SD Exported Functions
-  * @{
-  */
-
-/** @defgroup SD_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-  [..]  
-    This section provides functions allowing to initialize/de-initialize the SD
-    card device to be ready for use.
-      
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SD card according to the specified parameters in the 
-            SD_HandleTypeDef and create the associated handle.
-  * @param  hsd: SD handle
-  * @param  SDCardInfo: HAL_SD_CardInfoTypedef structure for SD card information   
-  * @retval HAL SD error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo)
-{ 
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SD_InitTypeDef tmpinit;
-  
-  /* Initialize the low level hardware (MSP) */
-  HAL_SD_MspInit(hsd);
-  
-  /* Default SDIO peripheral configuration for SD card initialization */
-  tmpinit.ClockEdge           = SDIO_CLOCK_EDGE_RISING;
-  tmpinit.ClockBypass         = SDIO_CLOCK_BYPASS_DISABLE;
-  tmpinit.ClockPowerSave      = SDIO_CLOCK_POWER_SAVE_DISABLE;
-  tmpinit.BusWide             = SDIO_BUS_WIDE_1B;
-  tmpinit.HardwareFlowControl = SDIO_HARDWARE_FLOW_CONTROL_DISABLE;
-  tmpinit.ClockDiv            = SDIO_INIT_CLK_DIV;
-  
-  /* Initialize SDIO peripheral interface with default configuration */
-  SDIO_Init(hsd->Instance, tmpinit);
-  
-  /* Identify card operating voltage */
-  errorstate = SD_PowerON(hsd); 
-  
-  if(errorstate != SD_OK)     
-  {
-    return errorstate;
-  }
-  
-  /* Initialize the present SDIO card(s) and put them in idle state */
-  errorstate = SD_Initialize_Cards(hsd);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Read CSD/CID MSD registers */
-  errorstate = HAL_SD_Get_CardInfo(hsd, SDCardInfo);
-  
-  if (errorstate == SD_OK)
-  {
-    /* Select the Card */
-    errorstate = SD_Select_Deselect(hsd, (uint32_t)(((uint32_t)SDCardInfo->RCA) << 16));
-  }
-  
-  /* Configure SDIO peripheral interface */
-  SDIO_Init(hsd->Instance, hsd->Init);   
-  
-  return errorstate;
-}
-
-/**
-  * @brief  De-Initializes the SD card.
-  * @param  hsd: SD handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
-{
-  
-  /* Set SD power state to off */ 
-  SD_PowerOFF(hsd);
-  
-  /* De-Initialize the MSP layer */
-  HAL_SD_MspDeInit(hsd);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initializes the SD MSP.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  De-Initialize SD MSP.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group2 IO operation functions 
- *  @brief   Data transfer functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### IO operation functions #####
- =============================================================================== 
-  [..]
-    This subsection provides a set of functions allowing to manage the data 
-    transfer from/to SD card.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
-  *         is managed by polling mode.  
-  * @param  hsd: SD handle
-  * @param  pReadBuffer: pointer to the buffer that will contain the received data
-  * @param  ReadAddr: Address from where data is to be read  
-  * @param  BlockSize: SD card Data block size 
-  *          This parameter should be 512
-  * @param  NumberOfBlocks: Number of SD blocks to read   
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0, *tempbuff = (uint32_t *)pReadBuffer;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr /= 512;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t) BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdio_datainitstructure.DataBlockSize = (uint32_t)(9 << 4);
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;    
-  }
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)ReadAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Read block(s) in polling mode */
-  if(NumberOfBlocks > 1)
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Poll on SDIO flags */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-      {
-        /* Read data from SDIO Rx FIFO */
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8;
-      }
-    }      
-  }
-  else
-  {
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK); 
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }    
-    
-    /* In case of single block transfer, no need of stop transfer at all */
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-      {
-        /* Read data from SDIO Rx FIFO */
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8;
-      }
-    }
-  }
-  
-  /* Send stop transmission command in case of multiblock read */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
-  {    
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) ||\
-      (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-        (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-    {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
-    }
-  }
-  
-  /* Get error state */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  count = SD_DATATIMEOUT;
-  
-  /* Empty FIFO if there is still any data */
-  while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
-  {
-    *tempbuff = SDIO_ReadFIFO(hsd->Instance);
-    tempbuff++;
-    count--;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Allows to write block(s) to a specified address in a card. The Data
-  *         transfer is managed by polling mode.  
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  WriteAddr: Address from where data is to be written 
-  * @param  BlockSize: SD card Data block size 
-  *          This parameter should be 512.
-  * @param  NumberOfBlocks: Number of SD blocks to write 
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t totalnumberofbytes = 0, bytestransferred = 0, count = 0, restwords = 0;
-  uint32_t *tempbuff = (uint32_t *)pWriteBuffer;
-  uint8_t cardstate  = 0;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr /= 512;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }  
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Set total number of bytes to write */
-  totalnumberofbytes = NumberOfBlocks * BlockSize;
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = NumberOfBlocks * BlockSize;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Write block(s) in polling mode */
-  if(NumberOfBlocks > 1)
-  {
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DATAEND | SDIO_FLAG_STBITERR))
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
-      {
-        if ((totalnumberofbytes - bytestransferred) < 32)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
-          
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0; count < restwords; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++;
-            bytestransferred += 4;
-          }
-        }
-        else
-        {
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0; count < 8; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-          
-          tempbuff += 8;
-          bytestransferred += 32;
-        }
-      }
-    }   
-  }
-  else
-  {
-    /* In case of single data block transfer no need of stop command at all */ 
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXFIFOHE))
-      {
-        if ((totalnumberofbytes - bytestransferred) < 32)
-        {
-          restwords = ((totalnumberofbytes - bytestransferred) % 4 == 0) ? ((totalnumberofbytes - bytestransferred) / 4) : (( totalnumberofbytes -  bytestransferred) / 4 + 1);
-          
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0; count < restwords; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, tempbuff);
-            tempbuff++; 
-            bytestransferred += 4;
-          }
-        }
-        else
-        {
-          /* Write data to SDIO Tx FIFO */
-          for (count = 0; count < 8; count++)
-          {
-            SDIO_WriteFIFO(hsd->Instance, (tempbuff + count));
-          }
-          
-          tempbuff += 8;
-          bytestransferred += 32;
-        }
-      }
-    }  
-  }
-  
-  /* Send stop transmission command in case of multiblock write */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DATAEND) && (NumberOfBlocks > 1))
-  {    
-    if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-      (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-    {
-      /* Send stop transmission command */
-      errorstate = HAL_SD_StopTransfer(hsd);
-    }
-  }
-  
-  /* Get error state */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXUNDERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
-    
-    errorstate = SD_TX_UNDERRUN;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Wait till the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  
-  while ((errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Reads block(s) from a specified address in a card. The Data transfer 
-  *         is managed by DMA mode. 
-  * @note   This API should be followed by the function HAL_SD_CheckReadOperation()
-  *         to check the completion of the read process   
-  * @param  hsd: SD handle                 
-  * @param  pReadBuffer: Pointer to the buffer that will contain the received data
-  * @param  ReadAddr: Address from where data is to be read  
-  * @param  BlockSize: SD card Data block size 
-  *         This paramater should be 512.
-  * @param  NumberOfBlocks: Number of blocks to read.
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0;
-  hsd->DmaTransferCplt = 0;
-  hsd->SdTransferErr   = SD_OK; 
-  
-  /* Initialize SD Read operation */
-  if(NumberOfBlocks > 1)
-  {
-    hsd->SdOperation = SD_READ_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_READ_SINGLE_BLOCK;
-  }
-  
-  /* Enable transfer interrupts */
-  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
-                                SDIO_IT_DTIMEOUT |\
-                                SDIO_IT_DATAEND  |\
-                                SDIO_IT_RXOVERR  |\
-                                SDIO_IT_STBITERR));
-  
-  /* Enable SDIO DMA transfer */
-  __HAL_SD_SDIO_DMA_ENABLE();
-  
-  /* Configure DMA user callbacks */
-  hsd->hdmarx->XferCpltCallback  = SD_DMA_RxCplt;
-  hsd->hdmarx->XferErrorCallback = SD_DMA_RxError;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsd->hdmarx, (uint32_t)&hsd->Instance->FIFO, (uint32_t)pReadBuffer, (uint32_t)(BlockSize * NumberOfBlocks));
-  
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    ReadAddr /= 512;
-  }
-  
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Check number of blocks command */
-  if(NumberOfBlocks > 1)
-  {
-    /* Send CMD18 READ_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_MULT_BLOCK;
-  }
-  else
-  {
-    /* Send CMD17 READ_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_READ_SINGLE_BLOCK;
-  }
-  
-  sdio_cmdinitstructure.Argument = (uint32_t)ReadAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_READ_SINGLE_BLOCK);
-  }
-  
-  /* Update the SD transfer error in SD handle */
-  hsd->SdTransferErr = errorstate;
-  
-  return errorstate;
-}
-
-
-/**
-  * @brief  Writes block(s) to a specified address in a card. The Data transfer 
-  *         is managed by DMA mode. 
-  * @note   This API should be followed by the function HAL_SD_CheckWriteOperation()
-  *         to check the completion of the write process (by SD current status polling).  
-  * @param  hsd: SD handle
-  * @param  pWriteBuffer: pointer to the buffer that will contain the data to transmit
-  * @param  WriteAddr: Address from where data is to be read   
-  * @param  BlockSize: the SD card Data block size 
-  *          This parameter should be 512.
-  * @param  NumberOfBlocks: Number of blocks to write
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Initialize data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Initialize handle flags */
-  hsd->SdTransferCplt  = 0;
-  hsd->DmaTransferCplt = 0;
-  hsd->SdTransferErr   = SD_OK;
-  
-  /* Initialize SD Write operation */
-  if(NumberOfBlocks > 1)
-  {
-    hsd->SdOperation = SD_WRITE_MULTIPLE_BLOCK;
-  }
-  else
-  {
-    hsd->SdOperation = SD_WRITE_SINGLE_BLOCK;
-  }  
-  
-  /* Enable transfer interrupts */
-  __HAL_SD_SDIO_ENABLE_IT(hsd, (SDIO_IT_DCRCFAIL |\
-                                SDIO_IT_DTIMEOUT |\
-                                SDIO_IT_DATAEND  |\
-                                SDIO_IT_TXUNDERR |\
-                                SDIO_IT_STBITERR)); 
-  
-  /* Configure DMA user callbacks */
-  hsd->hdmatx->XferCpltCallback  = SD_DMA_TxCplt;
-  hsd->hdmatx->XferErrorCallback = SD_DMA_TxError;
-  
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsd->hdmatx, (uint32_t)pWriteBuffer, (uint32_t)&hsd->Instance->FIFO, (uint32_t)(BlockSize * NumberOfBlocks));
-
-  /* Enable SDIO DMA transfer */
-  __HAL_SD_SDIO_DMA_ENABLE();
-  
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    BlockSize = 512;
-    WriteAddr /= 512;
-  }
-
-  /* Set Block Size for Card */ 
-  sdio_cmdinitstructure.Argument         = (uint32_t)BlockSize;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Check number of blocks command */
-  if(NumberOfBlocks <= 1)
-  {
-    /* Send CMD24 WRITE_SINGLE_BLOCK */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_SINGLE_BLOCK;
-  }
-  else
-  {
-    /* Send CMD25 WRITE_MULT_BLOCK with argument data address */
-    sdio_cmdinitstructure.CmdIndex = SD_CMD_WRITE_MULT_BLOCK;
-  }
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)WriteAddr;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-
-  /* Check for error conditions */
-  if(NumberOfBlocks > 1)
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_MULT_BLOCK);
-  }
-  else
-  {
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_WRITE_SINGLE_BLOCK);
-  }
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = BlockSize * NumberOfBlocks;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_512B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_CARD;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  hsd->SdTransferErr = errorstate;
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function waits until the SD DMA data read transfer is finished. 
-  *         This API should be called after HAL_SD_ReadBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the 
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-  
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt; 
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    
-  while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0))
-  {
-    tmp1 = hsd->DmaTransferCplt; 
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;    
-    timeout--;
-  }
-  
-  timeout = Timeout;
-  
-  /* Wait until the Rx transfer is no longer active */
-  while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXACT)) && (timeout > 0))
-  {
-    timeout--;  
-  }
-  
-  /* Send stop command in multiblock read */
-  if (hsd->SdOperation == SD_READ_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-  
-  if ((timeout == 0) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function waits until the SD DMA data write transfer is finished. 
-  *         This API should be called after HAL_SD_WriteBlocks_DMA() function
-  *         to insure that all data sent by the card is already transferred by the 
-  *         DMA controller.
-  * @param  hsd: SD handle
-  * @param  Timeout: Timeout duration  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout = Timeout;
-  uint32_t tmp1, tmp2;
-  HAL_SD_ErrorTypedef tmp3;
-
-  /* Wait for DMA/SD transfer end or SD error variables to be in SD handle */
-  tmp1 = hsd->DmaTransferCplt; 
-  tmp2 = hsd->SdTransferCplt;
-  tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    
-  while ((tmp1 == 0) && (tmp2 == 0) && (tmp3 == SD_OK) && (timeout > 0))
-  {
-    tmp1 = hsd->DmaTransferCplt; 
-    tmp2 = hsd->SdTransferCplt;
-    tmp3 = (HAL_SD_ErrorTypedef)hsd->SdTransferErr;
-    timeout--;
-  }
-  
-  timeout = Timeout;
-  
-  /* Wait until the Tx transfer is no longer active */
-  while((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_TXACT))  && (timeout > 0))
-  {
-    timeout--;  
-  }
-
-  /* Send stop command in multiblock write */
-  if (hsd->SdOperation == SD_WRITE_MULTIPLE_BLOCK)
-  {
-    errorstate = HAL_SD_StopTransfer(hsd);
-  }
-  
-  if ((timeout == 0) && (errorstate == SD_OK))
-  {
-    errorstate = SD_DATA_TIMEOUT;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* Return error state */
-  if (hsd->SdTransferErr != SD_OK)
-  {
-    return (HAL_SD_ErrorTypedef)(hsd->SdTransferErr);
-  }
-  
-  /* Wait until write is complete */
-  while(HAL_SD_GetStatus(hsd) != SD_TRANSFER_OK)
-  {    
-  }
-
-  return errorstate; 
-}
-
-/**
-  * @brief  Erases the specified memory area of the given SD card.
-  * @param  hsd: SD handle 
-  * @param  startaddr: Start byte address
-  * @param  endaddr: End byte address
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  
-  uint32_t delay         = 0;
-  __IO uint32_t maxdelay = 0;
-  uint8_t cardstate      = 0;
-  
-  /* Check if the card command class supports erase command */
-  if (((hsd->CSD[1] >> 20) & SD_CCCC_ERASE) == 0)
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-  
-  /* Get max delay value */
-  maxdelay = 120000 / (((hsd->Instance->CLKCR) & 0xFF) + 2);
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get start and end block for high capacity cards */
-  if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    startaddr /= 512;
-    endaddr   /= 512;
-  }
-  
-  /* According to sd-card spec 1.0 ERASE_GROUP_START (CMD32) and erase_group_end(CMD33) */
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD32 SD_ERASE_GRP_START with argument as addr  */
-    sdio_cmdinitstructure.Argument         =(uint32_t)startaddr;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_START;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_START);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send CMD33 SD_ERASE_GRP_END with argument as addr  */
-    sdio_cmdinitstructure.Argument         = (uint32_t)endaddr;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_ERASE_GRP_END;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_ERASE_GRP_END);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-  }
-  
-  /* Send CMD38 ERASE */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_ERASE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_ERASE);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  for (; delay < maxdelay; delay++)
-  {
-  }
-  
-  /* Wait untill the card is in programming state */
-  errorstate = SD_IsCardProgramming(hsd, &cardstate);
-  
-  delay = SD_DATATIMEOUT;
-  
-  while ((delay > 0) && (errorstate == SD_OK) && ((cardstate == SD_CARD_PROGRAMMING) || (cardstate == SD_CARD_RECEIVING)))
-  {
-    errorstate = SD_IsCardProgramming(hsd, &cardstate);
-    delay--;
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  This function handles SD card interrupt request.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
-{  
-  /* Check for SDIO interrupt flags */
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DATAEND))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_IT_DATAEND);  
-      
-    /* SD transfer is complete */
-    hsd->SdTransferCplt = 1;
-
-    /* No transfer error */ 
-    hsd->SdTransferErr  = SD_OK;
-
-    HAL_SD_XferCpltCallback(hsd);  
-  }  
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    hsd->SdTransferErr = SD_DATA_CRC_FAIL;
-    
-    HAL_SD_XferErrorCallback(hsd);
-    
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    hsd->SdTransferErr = SD_DATA_TIMEOUT;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    hsd->SdTransferErr = SD_RX_OVERRUN;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_TXUNDERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_TXUNDERR);
-    
-    hsd->SdTransferErr = SD_TX_UNDERRUN;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_IT_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    hsd->SdTransferErr = SD_START_BIT_ERR;
-    
-    HAL_SD_XferErrorCallback(hsd);
-  }
-  else
-  {
-    /* No error flag set */
-  }
-
-  /* Disable all SDIO peripheral interrupt sources */
-  __HAL_SD_SDIO_DISABLE_IT(hsd, SDIO_IT_DCRCFAIL | SDIO_IT_DTIMEOUT | SDIO_IT_DATAEND  |\
-                                SDIO_IT_TXFIFOHE | SDIO_IT_RXFIFOHF | SDIO_IT_TXUNDERR |\
-                                SDIO_IT_RXOVERR  | SDIO_IT_STBITERR);                               
-}
-
-
-/**
-  * @brief  SD end of transfer callback.
-  * @param  hsd: SD handle 
-  * @retval None
-  */
-__weak void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_XferCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer Error callback.
-  * @param  hsd: SD handle
-  * @retval None
-  */
-__weak void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_XferErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer complete Rx callback in non blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxCpltCallback could be implemented in the user file
-   */ 
-}  
-
-/**
-  * @brief  SD DMA transfer complete Rx error callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_RxErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SD Transfer complete Tx callback in non blocking mode.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxCpltCallback could be implemented in the user file
-   */ 
-}  
-
-/**
-  * @brief  SD DMA transfer complete error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-__weak void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SD_DMA_TxErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group3 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control the SD card 
-    operations.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns information about specific card.
-  * @param  hsd: SD handle
-  * @param  pCardInfo: Pointer to a HAL_SD_CardInfoTypedef structure that  
-  *         contains all SD cardinformation  
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0;
-  
-  pCardInfo->CardType = (uint8_t)(hsd->CardType);
-  pCardInfo->RCA      = (uint16_t)(hsd->RCA);
-  
-  /* Byte 0 */
-  tmp = (hsd->CSD[0] & 0xFF000000) >> 24;
-  pCardInfo->SD_csd.CSDStruct      = (uint8_t)((tmp & 0xC0) >> 6);
-  pCardInfo->SD_csd.SysSpecVersion = (uint8_t)((tmp & 0x3C) >> 2);
-  pCardInfo->SD_csd.Reserved1      = tmp & 0x03;
-  
-  /* Byte 1 */
-  tmp = (hsd->CSD[0] & 0x00FF0000) >> 16;
-  pCardInfo->SD_csd.TAAC = (uint8_t)tmp;
-  
-  /* Byte 2 */
-  tmp = (hsd->CSD[0] & 0x0000FF00) >> 8;
-  pCardInfo->SD_csd.NSAC = (uint8_t)tmp;
-  
-  /* Byte 3 */
-  tmp = hsd->CSD[0] & 0x000000FF;
-  pCardInfo->SD_csd.MaxBusClkFrec = (uint8_t)tmp;
-  
-  /* Byte 4 */
-  tmp = (hsd->CSD[1] & 0xFF000000) >> 24;
-  pCardInfo->SD_csd.CardComdClasses = (uint16_t)(tmp << 4);
-  
-  /* Byte 5 */
-  tmp = (hsd->CSD[1] & 0x00FF0000) >> 16;
-  pCardInfo->SD_csd.CardComdClasses |= (uint16_t)((tmp & 0xF0) >> 4);
-  pCardInfo->SD_csd.RdBlockLen       = (uint8_t)(tmp & 0x0F);
-  
-  /* Byte 6 */
-  tmp = (hsd->CSD[1] & 0x0000FF00) >> 8;
-  pCardInfo->SD_csd.PartBlockRead   = (uint8_t)((tmp & 0x80) >> 7);
-  pCardInfo->SD_csd.WrBlockMisalign = (uint8_t)((tmp & 0x40) >> 6);
-  pCardInfo->SD_csd.RdBlockMisalign = (uint8_t)((tmp & 0x20) >> 5);
-  pCardInfo->SD_csd.DSRImpl         = (uint8_t)((tmp & 0x10) >> 4);
-  pCardInfo->SD_csd.Reserved2       = 0; /*!< Reserved */
-  
-  if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0))
-  {
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x03) << 10;
-    
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
-    pCardInfo->SD_csd.DeviceSize |= (tmp) << 2;
-    
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
-    pCardInfo->SD_csd.DeviceSize |= (tmp & 0xC0) >> 6;
-    
-    pCardInfo->SD_csd.MaxRdCurrentVDDMin = (tmp & 0x38) >> 3;
-    pCardInfo->SD_csd.MaxRdCurrentVDDMax = (tmp & 0x07);
-    
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
-    pCardInfo->SD_csd.MaxWrCurrentVDDMin = (tmp & 0xE0) >> 5;
-    pCardInfo->SD_csd.MaxWrCurrentVDDMax = (tmp & 0x1C) >> 2;
-    pCardInfo->SD_csd.DeviceSizeMul      = (tmp & 0x03) << 1;
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
-    pCardInfo->SD_csd.DeviceSizeMul |= (tmp & 0x80) >> 7;
-    
-    pCardInfo->CardCapacity  = (pCardInfo->SD_csd.DeviceSize + 1) ;
-    pCardInfo->CardCapacity *= (1 << (pCardInfo->SD_csd.DeviceSizeMul + 2));
-    pCardInfo->CardBlockSize = 1 << (pCardInfo->SD_csd.RdBlockLen);
-    pCardInfo->CardCapacity *= pCardInfo->CardBlockSize;
-  }
-  else if (hsd->CardType == HIGH_CAPACITY_SD_CARD)
-  {
-    /* Byte 7 */
-    tmp = (uint8_t)(hsd->CSD[1] & 0x000000FF);
-    pCardInfo->SD_csd.DeviceSize = (tmp & 0x3F) << 16;
-    
-    /* Byte 8 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0xFF000000) >> 24);
-    
-    pCardInfo->SD_csd.DeviceSize |= (tmp << 8);
-    
-    /* Byte 9 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x00FF0000) >> 16);
-    
-    pCardInfo->SD_csd.DeviceSize |= (tmp);
-    
-    /* Byte 10 */
-    tmp = (uint8_t)((hsd->CSD[2] & 0x0000FF00) >> 8);
-    
-    pCardInfo->CardCapacity  = ((pCardInfo->SD_csd.DeviceSize + 1)) * 512 * 1024;
-    pCardInfo->CardBlockSize = 512;    
-  }
-  else
-  {
-    /* Not supported card type */
-    errorstate = SD_ERROR;
-  }
-    
-  pCardInfo->SD_csd.EraseGrSize = (tmp & 0x40) >> 6;
-  pCardInfo->SD_csd.EraseGrMul  = (tmp & 0x3F) << 1;
-  
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CSD[2] & 0x000000FF);
-  pCardInfo->SD_csd.EraseGrMul     |= (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.WrProtectGrSize = (tmp & 0x7F);
-  
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0xFF000000) >> 24);
-  pCardInfo->SD_csd.WrProtectGrEnable = (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.ManDeflECC        = (tmp & 0x60) >> 5;
-  pCardInfo->SD_csd.WrSpeedFact       = (tmp & 0x1C) >> 2;
-  pCardInfo->SD_csd.MaxWrBlockLen     = (tmp & 0x03) << 2;
-  
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0x00FF0000) >> 16);
-  pCardInfo->SD_csd.MaxWrBlockLen      |= (tmp & 0xC0) >> 6;
-  pCardInfo->SD_csd.WriteBlockPaPartial = (tmp & 0x20) >> 5;
-  pCardInfo->SD_csd.Reserved3           = 0;
-  pCardInfo->SD_csd.ContentProtectAppli = (tmp & 0x01);
-  
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CSD[3] & 0x0000FF00) >> 8);
-  pCardInfo->SD_csd.FileFormatGrouop = (tmp & 0x80) >> 7;
-  pCardInfo->SD_csd.CopyFlag         = (tmp & 0x40) >> 6;
-  pCardInfo->SD_csd.PermWrProtect    = (tmp & 0x20) >> 5;
-  pCardInfo->SD_csd.TempWrProtect    = (tmp & 0x10) >> 4;
-  pCardInfo->SD_csd.FileFormat       = (tmp & 0x0C) >> 2;
-  pCardInfo->SD_csd.ECC              = (tmp & 0x03);
-  
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CSD[3] & 0x000000FF);
-  pCardInfo->SD_csd.CSD_CRC   = (tmp & 0xFE) >> 1;
-  pCardInfo->SD_csd.Reserved4 = 1;
-  
-  /* Byte 0 */
-  tmp = (uint8_t)((hsd->CID[0] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ManufacturerID = tmp;
-  
-  /* Byte 1 */
-  tmp = (uint8_t)((hsd->CID[0] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.OEM_AppliID = tmp << 8;
-  
-  /* Byte 2 */
-  tmp = (uint8_t)((hsd->CID[0] & 0x000000FF00) >> 8);
-  pCardInfo->SD_cid.OEM_AppliID |= tmp;
-  
-  /* Byte 3 */
-  tmp = (uint8_t)(hsd->CID[0] & 0x000000FF);
-  pCardInfo->SD_cid.ProdName1 = tmp << 24;
-  
-  /* Byte 4 */
-  tmp = (uint8_t)((hsd->CID[1] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 16;
-  
-  /* Byte 5 */
-  tmp = (uint8_t)((hsd->CID[1] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.ProdName1 |= tmp << 8;
-  
-  /* Byte 6 */
-  tmp = (uint8_t)((hsd->CID[1] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ProdName1 |= tmp;
-  
-  /* Byte 7 */
-  tmp = (uint8_t)(hsd->CID[1] & 0x000000FF);
-  pCardInfo->SD_cid.ProdName2 = tmp;
-  
-  /* Byte 8 */
-  tmp = (uint8_t)((hsd->CID[2] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdRev = tmp;
-  
-  /* Byte 9 */
-  tmp = (uint8_t)((hsd->CID[2] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.ProdSN = tmp << 24;
-  
-  /* Byte 10 */
-  tmp = (uint8_t)((hsd->CID[2] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ProdSN |= tmp << 16;
-  
-  /* Byte 11 */
-  tmp = (uint8_t)(hsd->CID[2] & 0x000000FF);
-  pCardInfo->SD_cid.ProdSN |= tmp << 8;
-  
-  /* Byte 12 */
-  tmp = (uint8_t)((hsd->CID[3] & 0xFF000000) >> 24);
-  pCardInfo->SD_cid.ProdSN |= tmp;
-  
-  /* Byte 13 */
-  tmp = (uint8_t)((hsd->CID[3] & 0x00FF0000) >> 16);
-  pCardInfo->SD_cid.Reserved1   |= (tmp & 0xF0) >> 4;
-  pCardInfo->SD_cid.ManufactDate = (tmp & 0x0F) << 8;
-  
-  /* Byte 14 */
-  tmp = (uint8_t)((hsd->CID[3] & 0x0000FF00) >> 8);
-  pCardInfo->SD_cid.ManufactDate |= tmp;
-  
-  /* Byte 15 */
-  tmp = (uint8_t)(hsd->CID[3] & 0x000000FF);
-  pCardInfo->SD_cid.CID_CRC   = (tmp & 0xFE) >> 1;
-  pCardInfo->SD_cid.Reserved2 = 1;
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enables wide bus operation for the requested card if supported by 
-  *         card.
-  * @param  hsd: SD handle       
-  * @param  WideMode: Specifies the SD card wide bus mode 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_BUS_WIDE_8B: 8-bit data transfer (Only for MMC)
-  *            @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
-  *            @arg SDIO_BUS_WIDE_1B: 1-bit data transfer
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_InitTypeDef init;
-  
-  /* MMC Card does not support this feature */
-  if (hsd->CardType == MULTIMEDIA_CARD)
-  {
-    errorstate = SD_UNSUPPORTED_FEATURE;
-  }
-  else if ((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1) || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-    (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    if (WideMode == SDIO_BUS_WIDE_8B)
-    {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    }
-    else if (WideMode == SDIO_BUS_WIDE_4B)
-    {
-      errorstate = SD_WideBus_Enable(hsd);
-    }
-    else if (WideMode == SDIO_BUS_WIDE_1B)
-    {
-      errorstate = SD_WideBus_Disable(hsd);
-    }
-    else
-    {
-      /* WideMode is not a valid argument*/
-      errorstate = SD_INVALID_PARAMETER;
-    }
-      
-    if (errorstate == SD_OK)
-    {
-      /* Configure the SDIO peripheral */
-      init.ClockEdge           = hsd->Init.ClockEdge;
-      init.ClockBypass         = hsd->Init.ClockBypass;
-      init.ClockPowerSave      = hsd->Init.ClockPowerSave;
-      init.BusWide             = WideMode;
-      init.HardwareFlowControl = hsd->Init.HardwareFlowControl;
-      init.ClockDiv            = hsd->Init.ClockDiv;
-      
-      /* Configure SDIO peripheral interface */
-      SDIO_Init(hsd->Instance, init);
-    }
-    else
-    {
-      /* An error occured while enabling/disabling the wide bus*/
-    }
-  }
-  else
-  {
-    /* Not supported card type */
-    errorstate = SD_ERROR;
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Aborts an ongoing data transfer.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Send CMD12 STOP_TRANSMISSION  */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_STOP_TRANSMISSION;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_STOP_TRANSMISSION);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Switches the SD card to High Speed mode.
-  *         This API must be used after "Transfer State"
-  * @note   This operation should be followed by the configuration 
-  *         of PLL to have SDIOCK clock between 67 and 75 MHz
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  
-  uint8_t SD_hs[64]  = {0};
-  uint32_t SD_scr[2] = {0, 0};
-  uint32_t SD_SPEC   = 0 ;
-  uint32_t count = 0, *tempbuff = (uint32_t *)SD_hs;
-  
-  /* Initialize the Data control register */
-  hsd->Instance->DCTRL = 0;
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, SD_scr);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Test the Version supported by the card*/ 
-  SD_SPEC = (SD_scr[1]  & 0x01000000) | (SD_scr[1]  & 0x02000000);
-  
-  if (SD_SPEC != SD_ALLZERO)
-  {
-    /* Set Block Size for Card */
-    sdio_cmdinitstructure.Argument         = (uint32_t)64;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Configure the SD DPSM (Data Path State Machine) */
-    sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-    sdio_datainitstructure.DataLength    = 64;
-    sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B ;
-    sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-    sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-    sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-    SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-    
-    /* Send CMD6 switch mode */
-    sdio_cmdinitstructure.Argument         = 0x80FFFF01;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_HS_SWITCH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure); 
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_HS_SWITCH);
-    
-    if (errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-        
-    while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-    {
-      if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-      {
-        for (count = 0; count < 8; count++)
-        {
-          *(tempbuff + count) = SDIO_ReadFIFO(hsd->Instance);
-        }
-        
-        tempbuff += 8;
-      }
-    }
-    
-    if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-    {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-      
-      errorstate = SD_DATA_TIMEOUT;
-      
-      return errorstate;
-    }
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-    {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-      
-      errorstate = SD_DATA_CRC_FAIL;
-      
-      return errorstate;
-    }
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-    {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-      
-      errorstate = SD_RX_OVERRUN;
-      
-      return errorstate;
-    }
-    else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-    {
-      __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-      
-      errorstate = SD_START_BIT_ERR;
-      
-      return errorstate;
-    }
-    else
-    {
-      /* No error flag set */
-    }
-    
-    count = SD_DATATIMEOUT;
-    
-    while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
-    {
-      *tempbuff = SDIO_ReadFIFO(hsd->Instance);
-      tempbuff++;
-      count--;
-    }
-    
-    /* Clear all the static flags */
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-    
-    /* Test if the switch mode HS is ok */
-    if ((SD_hs[13]& 2) != 2)
-    {
-      errorstate = SD_UNSUPPORTED_FEATURE;
-    } 
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SD_Exported_Functions_Group4 Peripheral State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in runtime the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the current SD card's status.
-  * @param  hsd: SD handle
-  * @param  pSDstatus: Pointer to the buffer that will contain the SD card status 
-  *         SD Status register)
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus)
-{
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t count = 0;
-  
-  /* Check SD response */
-  if ((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Set block size for card if it is not equal to current block size for card */
-  sdio_cmdinitstructure.Argument         = 64;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Send CMD55 */
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Configure the SD DPSM (Data Path State Machine) */ 
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = 64;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_64B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Send ACMD13 (SD_APP_STAUS)  with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_STAUS;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_STAUS);
-  
-  if (errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Get status data */
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-  {
-    if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXFIFOHF))
-    {
-      for (count = 0; count < 8; count++)
-      {
-        *(pSDstatus + count) = SDIO_ReadFIFO(hsd->Instance);
-      }
-      
-      pSDstatus += 8;
-    }
-  }
-  
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  count = SD_DATATIMEOUT;
-  while ((__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL)) && (count > 0))
-  {
-    *pSDstatus = SDIO_ReadFIFO(hsd->Instance);
-    pSDstatus++;
-    count--;
-  }
-  
-  /* Clear all the static status flags*/
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Gets the current sd card data status.
-  * @param  hsd: SD handle
-  * @retval Data Transfer state
-  */
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_CardStateTypedef cardstate =  SD_CARD_TRANSFER;
-
-  /* Get SD card state */
-  cardstate = SD_GetState(hsd);
-  
-  /* Find SD status according to card state*/
-  if (cardstate == SD_CARD_TRANSFER)
-  {
-    return SD_TRANSFER_OK;
-  }
-  else if(cardstate == SD_CARD_ERROR)
-  {
-    return SD_TRANSFER_ERROR;
-  }
-  else
-  {
-    return SD_TRANSFER_BUSY;
-  }
-}
-
-/**
-  * @brief  Gets the SD card status.
-  * @param  hsd: SD handle      
-  * @param  pCardStatus: Pointer to the HAL_SD_CardStatusTypedef structure that 
-  *         will contain the SD card status information 
-  * @retval SD Card error state
-  */
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t tmp = 0;
-  uint32_t sd_status[16];
-  
-  errorstate = HAL_SD_SendSDStatus(hsd, sd_status);
-  
-  if (errorstate  != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Byte 0 */
-  tmp = (sd_status[0] & 0xC0) >> 6;
-  pCardStatus->DAT_BUS_WIDTH = (uint8_t)tmp;
-  
-  /* Byte 0 */
-  tmp = (sd_status[0] & 0x20) >> 5;
-  pCardStatus->SECURED_MODE = (uint8_t)tmp;
-  
-  /* Byte 2 */
-  tmp = (sd_status[2] & 0xFF);
-  pCardStatus->SD_CARD_TYPE = (uint8_t)(tmp << 8);
-  
-  /* Byte 3 */
-  tmp = (sd_status[3] & 0xFF);
-  pCardStatus->SD_CARD_TYPE |= (uint8_t)tmp;
-  
-  /* Byte 4 */
-  tmp = (sd_status[4] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA = (uint8_t)(tmp << 24);
-  
-  /* Byte 5 */
-  tmp = (sd_status[5] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 16);
-  
-  /* Byte 6 */
-  tmp = (sd_status[6] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)(tmp << 8);
-  
-  /* Byte 7 */
-  tmp = (sd_status[7] & 0xFF);
-  pCardStatus->SIZE_OF_PROTECTED_AREA |= (uint8_t)tmp;
-  
-  /* Byte 8 */
-  tmp = (sd_status[8] & 0xFF);
-  pCardStatus->SPEED_CLASS = (uint8_t)tmp;
-  
-  /* Byte 9 */
-  tmp = (sd_status[9] & 0xFF);
-  pCardStatus->PERFORMANCE_MOVE = (uint8_t)tmp;
-  
-  /* Byte 10 */
-  tmp = (sd_status[10] & 0xF0) >> 4;
-  pCardStatus->AU_SIZE = (uint8_t)tmp;
-  
-  /* Byte 11 */
-  tmp = (sd_status[11] & 0xFF);
-  pCardStatus->ERASE_SIZE = (uint8_t)(tmp << 8);
-  
-  /* Byte 12 */
-  tmp = (sd_status[12] & 0xFF);
-  pCardStatus->ERASE_SIZE |= (uint8_t)tmp;
-  
-  /* Byte 13 */
-  tmp = (sd_status[13] & 0xFC) >> 2;
-  pCardStatus->ERASE_TIMEOUT = (uint8_t)tmp;
-  
-  /* Byte 13 */
-  tmp = (sd_status[13] & 0x3);
-  pCardStatus->ERASE_OFFSET = (uint8_t)tmp;
-  
-  return errorstate;
-}
-         
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/** @addtogroup SD_Private_Functions
-  * @{
-  */
-
-/**
-  * @brief  SD DMA transfer complete Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1;
-  
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0)
-  {
-  }
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxCpltCallback(hsd->hdmarx);   
-}
-
-/**
-  * @brief  SD DMA transfer Error Rx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_RxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_RxErrorCallback(hsd->hdmarx);
-}
-
-/**
-  * @brief  SD DMA transfer complete Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxCplt(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = (SD_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-  
-  /* DMA transfer is complete */
-  hsd->DmaTransferCplt = 1;
-  
-  /* Wait until SD transfer is complete */
-  while(hsd->SdTransferCplt == 0)
-  {
-  }
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxCpltCallback(hsd->hdmatx);  
-}
-
-/**
-  * @brief  SD DMA transfer Error Tx callback.
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SD_DMA_TxError(DMA_HandleTypeDef *hdma)
-{
-  SD_HandleTypeDef *hsd = ( SD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  /* Transfer complete user callback */
-  HAL_SD_DMA_TxErrorCallback(hsd->hdmatx);
-}
-
-/**
-  * @brief  Returns the SD current state.
-  * @param  hsd: SD handle
-  * @retval SD card current state
-  */
-static HAL_SD_CardStateTypedef SD_GetState(SD_HandleTypeDef *hsd)
-{
-  uint32_t resp1 = 0;
-  
-  if (SD_SendStatus(hsd, &resp1) != SD_OK)
-  {
-    return SD_CARD_ERROR;
-  }
-  else
-  {
-    return (HAL_SD_CardStateTypedef)((resp1 >> 9) & 0x0F);
-  }
-}
-
-/**
-  * @brief  Initializes all cards or single card as the case may be Card(s) come 
-  *         into standby state.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Initialize_Cards(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure; 
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint16_t sd_rca = 1;
-  
-  if(SDIO_GetPowerState(hsd->Instance) == 0) /* Power off */
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-  
-  if(hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Send CMD2 ALL_SEND_CID */
-    sdio_cmdinitstructure.Argument         = 0;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_ALL_SEND_CID;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_LONG;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Get Card identification number data */
-    hsd->CID[0] = SDIO_GetResponse(SDIO_RESP1);
-    hsd->CID[1] = SDIO_GetResponse(SDIO_RESP2);
-    hsd->CID[2] = SDIO_GetResponse(SDIO_RESP3);
-    hsd->CID[3] = SDIO_GetResponse(SDIO_RESP4);
-  }
-  
-  if((hsd->CardType == STD_CAPACITY_SD_CARD_V1_1)    || (hsd->CardType == STD_CAPACITY_SD_CARD_V2_0) ||\
-     (hsd->CardType == SECURE_DIGITAL_IO_COMBO_CARD) || (hsd->CardType == HIGH_CAPACITY_SD_CARD))
-  {
-    /* Send CMD3 SET_REL_ADDR with argument 0 */
-    /* SD Card publishes its RCA. */
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_REL_ADDR;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp6Error(hsd, SD_CMD_SET_REL_ADDR, &sd_rca);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-  }
-  
-  if (hsd->CardType != SECURE_DIGITAL_IO_CARD)
-  {
-    /* Get the SD card RCA */
-    hsd->RCA = sd_rca;
-    
-    /* Send CMD9 SEND_CSD with argument as card's RCA */
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_CSD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_LONG;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp2Error(hsd);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Get Card Specific Data */
-    hsd->CSD[0] = SDIO_GetResponse(SDIO_RESP1);
-    hsd->CSD[1] = SDIO_GetResponse(SDIO_RESP2);
-    hsd->CSD[2] = SDIO_GetResponse(SDIO_RESP3);
-    hsd->CSD[3] = SDIO_GetResponse(SDIO_RESP4);
-  }
-  
-  /* All cards are initialized */
-  return errorstate;
-}
-
-/**
-  * @brief  Selects od Deselects the corresponding card.
-  * @param  hsd: SD handle
-  * @param  addr: Address of the card to be selected  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_Select_Deselect(SD_HandleTypeDef *hsd, uint64_t addr)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Send CMD7 SDIO_SEL_DESEL_CARD */
-  sdio_cmdinitstructure.Argument         = (uint32_t)addr;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEL_DESEL_CARD;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEL_DESEL_CARD);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enquires cards about their operating voltage and configures clock
-  *         controls and stores SD information that will be needed in future
-  *         in the SD handle.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_PowerON(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure; 
-  __IO HAL_SD_ErrorTypedef errorstate = SD_OK; 
-  uint32_t response = 0, count = 0, validvoltage = 0;
-  uint32_t sdtype = SD_STD_CAPACITY;
-  
-  /* Power ON Sequence -------------------------------------------------------*/
-  /* Disable SDIO Clock */
-  __HAL_SD_SDIO_DISABLE(); 
-  
-  /* Set Power State to ON */
-  SDIO_PowerState_ON(hsd->Instance);
-  
-  /* Enable SDIO Clock */
-  __HAL_SD_SDIO_ENABLE();
-  
-  /* CMD0: GO_IDLE_STATE -----------------------------------------------------*/
-  /* No CMD response required */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_GO_IDLE_STATE;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_NO;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdError(hsd);
-  
-  if(errorstate != SD_OK)
-  {
-    /* CMD Response TimeOut (wait for CMDSENT flag) */
-    return errorstate;
-  }
-  
-  /* CMD8: SEND_IF_COND ------------------------------------------------------*/
-  /* Send CMD8 to verify SD card interface operating condition */
-  /* Argument: - [31:12]: Reserved (shall be set to '0')
-  - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V)
-  - [7:0]: Check Pattern (recommended 0xAA) */
-  /* CMD Response: R7 */
-  sdio_cmdinitstructure.Argument         = SD_CHECK_PATTERN;
-  sdio_cmdinitstructure.CmdIndex         = SD_SDIO_SEND_IF_COND;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */ 
-  errorstate = SD_CmdResp7Error(hsd);
-  
-  if (errorstate == SD_OK)
-  {
-    /* SD Card 2.0 */
-    hsd->CardType = STD_CAPACITY_SD_CARD_V2_0; 
-    sdtype        = SD_HIGH_CAPACITY;
-  }
-  
-  /* Send CMD55 */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  /* If errorstate is Command TimeOut, it is a MMC card */
-  /* If errorstate is SD_OK it is a SD card: SD card 2.0 (voltage range mismatch)
-     or SD card 1.x */
-  if(errorstate == SD_OK)
-  {
-    /* SD CARD */
-    /* Send ACMD41 SD_APP_OP_COND with Argument 0x80100000 */
-    while((!validvoltage) && (count < SD_MAX_VOLT_TRIAL))
-    {
-      
-      /* SEND CMD55 APP_CMD with RCA as 0 */
-      sdio_cmdinitstructure.Argument         = 0;
-      sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-      sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-      sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-      sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-      SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-      
-      /* Check for error conditions */
-      errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-      
-      if(errorstate != SD_OK)
-      {
-        return errorstate;
-      }
-      
-      /* Send CMD41 */
-      sdio_cmdinitstructure.Argument         = SD_VOLTAGE_WINDOW_SD | sdtype;
-      sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_OP_COND;
-      sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-      sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-      sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-      SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-      
-      /* Check for error conditions */
-      errorstate = SD_CmdResp3Error(hsd);
-      
-      if(errorstate != SD_OK)
-      {
-        return errorstate;
-      }
-      
-      /* Get command response */
-      response = SDIO_GetResponse(SDIO_RESP1);
-      
-      /* Get operating voltage*/
-      validvoltage = (((response >> 31) == 1) ? 1 : 0);
-      
-      count++;
-    }
-    
-    if(count >= SD_MAX_VOLT_TRIAL)
-    {
-      errorstate = SD_INVALID_VOLTRANGE;
-      
-      return errorstate;
-    }
-    
-    if((response & SD_HIGH_CAPACITY) == SD_HIGH_CAPACITY) /* (response &= SD_HIGH_CAPACITY) */
-    {
-      hsd->CardType = HIGH_CAPACITY_SD_CARD;
-    }
-    
-  } /* else MMC Card */
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Turns the SDIO output signals off.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_PowerOFF(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  /* Set Power State to OFF */
-  SDIO_PowerState_OFF(hsd->Instance);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Returns the current card's status.
-  * @param  hsd: SD handle
-  * @param  pCardStatus: pointer to the buffer that will contain the SD card 
-  *         status (Card Status register)  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_SendStatus(SD_HandleTypeDef *hsd, uint32_t *pCardStatus)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  if(pCardStatus == HAL_NULL)
-  {
-    errorstate = SD_INVALID_PARAMETER;
-    
-    return errorstate;
-  }
-  
-  /* Send Status command */
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SEND_STATUS);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Get SD card status */
-  *pCardStatus = SDIO_GetResponse(SDIO_RESP1);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for CMD0.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdError(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t timeout, tmp;
-  
-  timeout = SDIO_CMD0TIMEOUT;
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
-    
-  while((timeout > 0) && (!tmp))
-  {
-    tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDSENT);
-    timeout--;
-  }
-  
-  if(timeout == 0)
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R7 response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp7Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_ERROR;
-  uint32_t timeout = SDIO_CMD0TIMEOUT, tmp;
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT); 
-  
-  while((!tmp) && (timeout > 0))
-  {
-    tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT);
-    timeout--;
-  }
-  
-  tmp = __HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT); 
-  
-  if((timeout == 0) || tmp)
-  {
-    /* Card is not V2.0 compliant or card does not support the set voltage range */
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CMDREND))
-  {
-    /* Card is SD V2.0 compliant */
-    errorstate = SD_OK;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CMDREND);
-    
-    return errorstate;
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R1 response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp1Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Check response received is of desired command */
-  if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* We have received response, retrieve it for analysis  */
-  response_r1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  if((response_r1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-  
-  if((response_r1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-  
-  if((response_r1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-  
-  if((response_r1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-  
-  if((response_r1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-  
-  if((response_r1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-  
-  if((response_r1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-  
-  if((response_r1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((response_r1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-  
-  if((response_r1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-  
-  if((response_r1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((response_r1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-  
-  if((response_r1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-  
-  if((response_r1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-  
-  if((response_r1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-  
-  if((response_r1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-  
-  if((response_r1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-  
-  if((response_r1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R3 (OCR) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp3Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R2 (CID or CSD) response.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp2Error(SD_HandleTypeDef *hsd)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  while (!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-    
-  if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if (__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks for error conditions for R6 (RCA) response.
-  * @param  hsd: SD handle
-  * @param  SD_CMD: The sent command index
-  * @param  pRCA: Pointer to the variable that will contain the SD card relative 
-  *         address RCA   
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_CmdResp6Error(SD_HandleTypeDef *hsd, uint8_t SD_CMD, uint16_t *pRCA)
-{
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t response_r1;
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Check response received is of desired command */
-  if(SDIO_GetCommandResponse(hsd->Instance) != SD_CMD)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  /* We have received response, retrieve it.  */
-  response_r1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  if((response_r1 & (SD_R6_GENERAL_UNKNOWN_ERROR | SD_R6_ILLEGAL_CMD | SD_R6_COM_CRC_FAILED)) == SD_ALLZERO)
-  {
-    *pRCA = (uint16_t) (response_r1 >> 16);
-    
-    return errorstate;
-  }
-  
-  if((response_r1 & SD_R6_GENERAL_UNKNOWN_ERROR) == SD_R6_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((response_r1 & SD_R6_ILLEGAL_CMD) == SD_R6_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((response_r1 & SD_R6_COM_CRC_FAILED) == SD_R6_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Enables the SDIO wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_WideBus_Enable(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  uint32_t scr[2] = {0, 0};
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* If requested card supports wide bus operation */
-  if((scr[1] & SD_WIDE_BUS_SUPPORT) != SD_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA.*/
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send ACMD6 APP_CMD with argument as 2 for wide bus mode */
-    sdio_cmdinitstructure.Argument         = 2;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    return errorstate;
-  }
-  else
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-}   
-
-/**
-  * @brief  Disables the SDIO wide bus mode.
-  * @param  hsd: SD handle
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_WideBus_Disable(SD_HandleTypeDef *hsd)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  
-  uint32_t scr[2] = {0, 0};
-  
-  if((SDIO_GetResponse(SDIO_RESP1) & SD_CARD_LOCKED) == SD_CARD_LOCKED)
-  {
-    errorstate = SD_LOCK_UNLOCK_FAILED;
-    
-    return errorstate;
-  }
-  
-  /* Get SCR Register */
-  errorstate = SD_FindSCR(hsd, scr);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* If requested card supports 1 bit mode operation */
-  if((scr[1] & SD_SINGLE_BUS_SUPPORT) != SD_ALLZERO)
-  {
-    /* Send CMD55 APP_CMD with argument as card's RCA */
-    sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-    sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-    sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-    sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    /* Send ACMD6 APP_CMD with argument as 0 for single bus mode */
-    sdio_cmdinitstructure.Argument         = 0;
-    sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_SD_SET_BUSWIDTH;
-    SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-    
-    /* Check for error conditions */
-    errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_SD_SET_BUSWIDTH);
-    
-    if(errorstate != SD_OK)
-    {
-      return errorstate;
-    }
-    
-    return errorstate;
-  }
-  else
-  {
-    errorstate = SD_REQUEST_NOT_APPLICABLE;
-    
-    return errorstate;
-  }
-}
-  
-  
-/**
-  * @brief  Finds the SD card SCR register value.
-  * @param  hsd: SD handle
-  * @param  pSCR: pointer to the buffer that will contain the SCR value  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
-{
-  SDIO_CmdInitTypeDef  sdio_cmdinitstructure;
-  SDIO_DataInitTypeDef sdio_datainitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  uint32_t index = 0;
-  uint32_t tempscr[2] = {0, 0};
-  
-  /* Set Block Size To 8 Bytes */
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = (uint32_t)8;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SET_BLOCKLEN;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SET_BLOCKLEN);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  /* Send CMD55 APP_CMD with argument as card's RCA */
-  sdio_cmdinitstructure.Argument         = (uint32_t)((hsd->RCA) << 16);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_APP_CMD;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_APP_CMD);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  sdio_datainitstructure.DataTimeOut   = SD_DATATIMEOUT;
-  sdio_datainitstructure.DataLength    = 8;
-  sdio_datainitstructure.DataBlockSize = SDIO_DATABLOCK_SIZE_8B;
-  sdio_datainitstructure.TransferDir   = SDIO_TRANSFER_DIR_TO_SDIO;
-  sdio_datainitstructure.TransferMode  = SDIO_TRANSFER_MODE_BLOCK;
-  sdio_datainitstructure.DPSM          = SDIO_DPSM_ENABLE;
-  SDIO_DataConfig(hsd->Instance, &sdio_datainitstructure);
-  
-  /* Send ACMD51 SD_APP_SEND_SCR with argument as 0 */
-  sdio_cmdinitstructure.Argument         = 0;
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SD_APP_SEND_SCR;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  /* Check for error conditions */
-  errorstate = SD_CmdResp1Error(hsd, SD_CMD_SD_APP_SEND_SCR);
-  
-  if(errorstate != SD_OK)
-  {
-    return errorstate;
-  }
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR | SDIO_FLAG_DCRCFAIL | SDIO_FLAG_DTIMEOUT | SDIO_FLAG_DBCKEND | SDIO_FLAG_STBITERR))
-  {
-    if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXDAVL))
-    {
-      *(tempscr + index) = SDIO_ReadFIFO(hsd->Instance);
-      index++;
-    }
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DTIMEOUT))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DTIMEOUT);
-    
-    errorstate = SD_DATA_TIMEOUT;
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_DCRCFAIL))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_DCRCFAIL);
-    
-    errorstate = SD_DATA_CRC_FAIL;
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_RXOVERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_RXOVERR);
-    
-    errorstate = SD_RX_OVERRUN;
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_STBITERR))
-  {
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_STBITERR);
-    
-    errorstate = SD_START_BIT_ERR;
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  *(pSCR + 1) = ((tempscr[0] & SD_0TO7BITS) << 24)  | ((tempscr[0] & SD_8TO15BITS) << 8) |\
-    ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24);
-  
-  *(pSCR) = ((tempscr[1] & SD_0TO7BITS) << 24)  | ((tempscr[1] & SD_8TO15BITS) << 8) |\
-    ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24);
-  
-  return errorstate;
-}
-
-/**
-  * @brief  Checks if the SD card is in programming state.
-  * @param  hsd: SD handle
-  * @param  pStatus: pointer to the variable that will contain the SD card state  
-  * @retval SD Card error state
-  */
-static HAL_SD_ErrorTypedef SD_IsCardProgramming(SD_HandleTypeDef *hsd, uint8_t *pStatus)
-{
-  SDIO_CmdInitTypeDef sdio_cmdinitstructure;
-  HAL_SD_ErrorTypedef errorstate = SD_OK;
-  __IO uint32_t responseR1 = 0;
-  
-  sdio_cmdinitstructure.Argument         = (uint32_t)(hsd->RCA << 16);
-  sdio_cmdinitstructure.CmdIndex         = SD_CMD_SEND_STATUS;
-  sdio_cmdinitstructure.Response         = SDIO_RESPONSE_SHORT;
-  sdio_cmdinitstructure.WaitForInterrupt = SDIO_WAIT_NO;
-  sdio_cmdinitstructure.CPSM             = SDIO_CPSM_ENABLE;
-  SDIO_SendCommand(hsd->Instance, &sdio_cmdinitstructure);
-  
-  while(!__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL | SDIO_FLAG_CMDREND | SDIO_FLAG_CTIMEOUT))
-  {
-  }
-  
-  if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CTIMEOUT))
-  {
-    errorstate = SD_CMD_RSP_TIMEOUT;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CTIMEOUT);
-    
-    return errorstate;
-  }
-  else if(__HAL_SD_SDIO_GET_FLAG(hsd, SDIO_FLAG_CCRCFAIL))
-  {
-    errorstate = SD_CMD_CRC_FAIL;
-    
-    __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_FLAG_CCRCFAIL);
-    
-    return errorstate;
-  }
-  else
-  {
-    /* No error flag set */
-  }
-  
-  /* Check response received is of desired command */
-  if((uint32_t)SDIO_GetCommandResponse(hsd->Instance) != SD_CMD_SEND_STATUS)
-  {
-    errorstate = SD_ILLEGAL_CMD;
-    
-    return errorstate;
-  }
-  
-  /* Clear all the static flags */
-  __HAL_SD_SDIO_CLEAR_FLAG(hsd, SDIO_STATIC_FLAGS);
-  
-  
-  /* We have received response, retrieve it for analysis */
-  responseR1 = SDIO_GetResponse(SDIO_RESP1);
-  
-  /* Find out card status */
-  *pStatus = (uint8_t)((responseR1 >> 9) & 0x0000000F);
-  
-  if((responseR1 & SD_OCR_ERRORBITS) == SD_ALLZERO)
-  {
-    return errorstate;
-  }
-  
-  if((responseR1 & SD_OCR_ADDR_OUT_OF_RANGE) == SD_OCR_ADDR_OUT_OF_RANGE)
-  {
-    return(SD_ADDR_OUT_OF_RANGE);
-  }
-  
-  if((responseR1 & SD_OCR_ADDR_MISALIGNED) == SD_OCR_ADDR_MISALIGNED)
-  {
-    return(SD_ADDR_MISALIGNED);
-  }
-  
-  if((responseR1 & SD_OCR_BLOCK_LEN_ERR) == SD_OCR_BLOCK_LEN_ERR)
-  {
-    return(SD_BLOCK_LEN_ERR);
-  }
-  
-  if((responseR1 & SD_OCR_ERASE_SEQ_ERR) == SD_OCR_ERASE_SEQ_ERR)
-  {
-    return(SD_ERASE_SEQ_ERR);
-  }
-  
-  if((responseR1 & SD_OCR_BAD_ERASE_PARAM) == SD_OCR_BAD_ERASE_PARAM)
-  {
-    return(SD_BAD_ERASE_PARAM);
-  }
-  
-  if((responseR1 & SD_OCR_WRITE_PROT_VIOLATION) == SD_OCR_WRITE_PROT_VIOLATION)
-  {
-    return(SD_WRITE_PROT_VIOLATION);
-  }
-  
-  if((responseR1 & SD_OCR_LOCK_UNLOCK_FAILED) == SD_OCR_LOCK_UNLOCK_FAILED)
-  {
-    return(SD_LOCK_UNLOCK_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_COM_CRC_FAILED) == SD_OCR_COM_CRC_FAILED)
-  {
-    return(SD_COM_CRC_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_ILLEGAL_CMD) == SD_OCR_ILLEGAL_CMD)
-  {
-    return(SD_ILLEGAL_CMD);
-  }
-  
-  if((responseR1 & SD_OCR_CARD_ECC_FAILED) == SD_OCR_CARD_ECC_FAILED)
-  {
-    return(SD_CARD_ECC_FAILED);
-  }
-  
-  if((responseR1 & SD_OCR_CC_ERROR) == SD_OCR_CC_ERROR)
-  {
-    return(SD_CC_ERROR);
-  }
-  
-  if((responseR1 & SD_OCR_GENERAL_UNKNOWN_ERROR) == SD_OCR_GENERAL_UNKNOWN_ERROR)
-  {
-    return(SD_GENERAL_UNKNOWN_ERROR);
-  }
-  
-  if((responseR1 & SD_OCR_STREAM_READ_UNDERRUN) == SD_OCR_STREAM_READ_UNDERRUN)
-  {
-    return(SD_STREAM_READ_UNDERRUN);
-  }
-  
-  if((responseR1 & SD_OCR_STREAM_WRITE_OVERRUN) == SD_OCR_STREAM_WRITE_OVERRUN)
-  {
-    return(SD_STREAM_WRITE_OVERRUN);
-  }
-  
-  if((responseR1 & SD_OCR_CID_CSD_OVERWRIETE) == SD_OCR_CID_CSD_OVERWRIETE)
-  {
-    return(SD_CID_CSD_OVERWRITE);
-  }
-  
-  if((responseR1 & SD_OCR_WP_ERASE_SKIP) == SD_OCR_WP_ERASE_SKIP)
-  {
-    return(SD_WP_ERASE_SKIP);
-  }
-  
-  if((responseR1 & SD_OCR_CARD_ECC_DISABLED) == SD_OCR_CARD_ECC_DISABLED)
-  {
-    return(SD_CARD_ECC_DISABLED);
-  }
-  
-  if((responseR1 & SD_OCR_ERASE_RESET) == SD_OCR_ERASE_RESET)
-  {
-    return(SD_ERASE_RESET);
-  }
-  
-  if((responseR1 & SD_OCR_AKE_SEQ_ERROR) == SD_OCR_AKE_SEQ_ERROR)
-  {
-    return(SD_AKE_SEQ_ERROR);
-  }
-  
-  return errorstate;
-}   
-
-/**
-  * @}
-  */
-  
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-#endif /* HAL_SD_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sd.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,705 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_sd.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of SD HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_SD_H
-#define __STM32L1xx_HAL_SD_H
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_sdmmc.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SD
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SD_Exported_Types SD Exported Types
-  * @{
-  */
-
-#define SD_InitTypeDef      SDIO_InitTypeDef 
-#define SD_TypeDef          SDIO_TypeDef
-
-/** 
-  * @brief  SDIO Handle Structure definition  
-  */ 
-typedef struct
-{
-  SD_TypeDef                   *Instance;        /*!< SDIO register base address                     */
-  
-  SD_InitTypeDef               Init;             /*!< SD required parameters                         */
-  
-  HAL_LockTypeDef              Lock;             /*!< SD locking object                              */
-  
-  uint32_t                     CardType;         /*!< SD card type                                   */
-  
-  uint32_t                     RCA;              /*!< SD relative card address                       */
-  
-  uint32_t                     CSD[4];           /*!< SD card specific data table                    */
-  
-  uint32_t                     CID[4];           /*!< SD card identification number table            */
-  
-  __IO uint32_t                SdTransferCplt;   /*!< SD transfer complete flag in non blocking mode */
-  
-  __IO uint32_t                SdTransferErr;    /*!< SD transfer error flag in non blocking mode    */
-  
-  __IO uint32_t                DmaTransferCplt;  /*!< SD DMA transfer complete flag                  */
-  
-  __IO uint32_t                SdOperation;      /*!< SD transfer operation (read/write)             */
-  
-  DMA_HandleTypeDef            *hdmarx;          /*!< SD Rx DMA handle parameters                    */
-  
-  DMA_HandleTypeDef            *hdmatx;          /*!< SD Tx DMA handle parameters                    */
-  
-}SD_HandleTypeDef;
-
-/** 
-  * @brief  Card Specific Data: CSD Register   
-  */ 
-typedef struct
-{
-  __IO uint8_t  CSDStruct;            /*!< CSD structure                         */
-  __IO uint8_t  SysSpecVersion;       /*!< System specification version          */
-  __IO uint8_t  Reserved1;            /*!< Reserved                              */
-  __IO uint8_t  TAAC;                 /*!< Data read access time 1               */
-  __IO uint8_t  NSAC;                 /*!< Data read access time 2 in CLK cycles */
-  __IO uint8_t  MaxBusClkFrec;        /*!< Max. bus clock frequency              */
-  __IO uint16_t CardComdClasses;      /*!< Card command classes                  */
-  __IO uint8_t  RdBlockLen;           /*!< Max. read data block length           */
-  __IO uint8_t  PartBlockRead;        /*!< Partial blocks for read allowed       */
-  __IO uint8_t  WrBlockMisalign;      /*!< Write block misalignment              */
-  __IO uint8_t  RdBlockMisalign;      /*!< Read block misalignment               */
-  __IO uint8_t  DSRImpl;              /*!< DSR implemented                       */
-  __IO uint8_t  Reserved2;            /*!< Reserved                              */
-  __IO uint32_t DeviceSize;           /*!< Device Size                           */
-  __IO uint8_t  MaxRdCurrentVDDMin;   /*!< Max. read current @ VDD min           */
-  __IO uint8_t  MaxRdCurrentVDDMax;   /*!< Max. read current @ VDD max           */
-  __IO uint8_t  MaxWrCurrentVDDMin;   /*!< Max. write current @ VDD min          */
-  __IO uint8_t  MaxWrCurrentVDDMax;   /*!< Max. write current @ VDD max          */
-  __IO uint8_t  DeviceSizeMul;        /*!< Device size multiplier                */
-  __IO uint8_t  EraseGrSize;          /*!< Erase group size                      */
-  __IO uint8_t  EraseGrMul;           /*!< Erase group size multiplier           */
-  __IO uint8_t  WrProtectGrSize;      /*!< Write protect group size              */
-  __IO uint8_t  WrProtectGrEnable;    /*!< Write protect group enable            */
-  __IO uint8_t  ManDeflECC;           /*!< Manufacturer default ECC              */
-  __IO uint8_t  WrSpeedFact;          /*!< Write speed factor                    */
-  __IO uint8_t  MaxWrBlockLen;        /*!< Max. write data block length          */
-  __IO uint8_t  WriteBlockPaPartial;  /*!< Partial blocks for write allowed      */
-  __IO uint8_t  Reserved3;            /*!< Reserved                              */
-  __IO uint8_t  ContentProtectAppli;  /*!< Content protection application        */
-  __IO uint8_t  FileFormatGrouop;     /*!< File format group                     */
-  __IO uint8_t  CopyFlag;             /*!< Copy flag (OTP)                       */
-  __IO uint8_t  PermWrProtect;        /*!< Permanent write protection            */
-  __IO uint8_t  TempWrProtect;        /*!< Temporary write protection            */
-  __IO uint8_t  FileFormat;           /*!< File format                           */
-  __IO uint8_t  ECC;                  /*!< ECC code                              */
-  __IO uint8_t  CSD_CRC;              /*!< CSD CRC                               */
-  __IO uint8_t  Reserved4;            /*!< Always 1                              */
-
-}HAL_SD_CSDTypedef;
-
-/** 
-  * @brief  Card Identification Data: CID Register   
-  */
-typedef struct
-{
-  __IO uint8_t  ManufacturerID;  /*!< Manufacturer ID       */
-  __IO uint16_t OEM_AppliID;     /*!< OEM/Application ID    */
-  __IO uint32_t ProdName1;       /*!< Product Name part1    */
-  __IO uint8_t  ProdName2;       /*!< Product Name part2    */
-  __IO uint8_t  ProdRev;         /*!< Product Revision      */
-  __IO uint32_t ProdSN;          /*!< Product Serial Number */
-  __IO uint8_t  Reserved1;       /*!< Reserved1             */
-  __IO uint16_t ManufactDate;    /*!< Manufacturing Date    */
-  __IO uint8_t  CID_CRC;         /*!< CID CRC               */
-  __IO uint8_t  Reserved2;       /*!< Always 1              */
-
-}HAL_SD_CIDTypedef;
-
-/** 
-  * @brief SD Card Status returned by ACMD13  
-  */
-typedef struct
-{
-  __IO uint8_t  DAT_BUS_WIDTH;           /*!< Shows the currently defined data bus width                 */
-  __IO uint8_t  SECURED_MODE;            /*!< Card is in secured mode of operation                       */
-  __IO uint16_t SD_CARD_TYPE;            /*!< Carries information about card type                        */
-  __IO uint32_t SIZE_OF_PROTECTED_AREA;  /*!< Carries information about the capacity of protected area   */
-  __IO uint8_t  SPEED_CLASS;             /*!< Carries information about the speed class of the card      */
-  __IO uint8_t  PERFORMANCE_MOVE;        /*!< Carries information about the card's performance move      */
-  __IO uint8_t  AU_SIZE;                 /*!< Carries information about the card's allocation unit size  */
-  __IO uint16_t ERASE_SIZE;              /*!< Determines the number of AUs to be erased in one operation */
-  __IO uint8_t  ERASE_TIMEOUT;           /*!< Determines the timeout for any number of AU erase          */
-  __IO uint8_t  ERASE_OFFSET;            /*!< Carries information about the erase offset                 */
-
-}HAL_SD_CardStatusTypedef;
-
-/** 
-  * @brief SD Card information structure 
-  */
-typedef struct
-{
-  HAL_SD_CSDTypedef   SD_csd;         /*!< SD card specific data register         */
-  HAL_SD_CIDTypedef   SD_cid;         /*!< SD card identification number register */
-  uint64_t            CardCapacity;   /*!< Card capacity                          */
-  uint32_t            CardBlockSize;  /*!< Card block size                        */
-  uint16_t            RCA;            /*!< SD relative card address               */
-  uint8_t             CardType;       /*!< SD card type                           */
-
-}HAL_SD_CardInfoTypedef;
-
-/** 
-  * @brief  SD Error status enumeration Structure definition  
-  */
-typedef enum
-{
-/** 
-  * @brief  SD specific error defines  
-  */   
-  SD_CMD_CRC_FAIL                    = (1),   /*!< Command response received (but CRC check failed)              */
-  SD_DATA_CRC_FAIL                   = (2),   /*!< Data block sent/received (CRC check failed)                   */
-  SD_CMD_RSP_TIMEOUT                 = (3),   /*!< Command response timeout                                      */
-  SD_DATA_TIMEOUT                    = (4),   /*!< Data timeout                                                  */
-  SD_TX_UNDERRUN                     = (5),   /*!< Transmit FIFO underrun                                        */
-  SD_RX_OVERRUN                      = (6),   /*!< Receive FIFO overrun                                          */
-  SD_START_BIT_ERR                   = (7),   /*!< Start bit not detected on all data signals in wide bus mode   */
-  SD_CMD_OUT_OF_RANGE                = (8),   /*!< Command's argument was out of range.                          */
-  SD_ADDR_MISALIGNED                 = (9),   /*!< Misaligned address                                            */
-  SD_BLOCK_LEN_ERR                   = (10),  /*!< Transferred block length is not allowed for the card or the number of transferred bytes does not match the block length */
-  SD_ERASE_SEQ_ERR                   = (11),  /*!< An error in the sequence of erase command occurs.            */
-  SD_BAD_ERASE_PARAM                 = (12),  /*!< An invalid selection for erase groups                        */
-  SD_WRITE_PROT_VIOLATION            = (13),  /*!< Attempt to program a write protect block                     */
-  SD_LOCK_UNLOCK_FAILED              = (14),  /*!< Sequence or password error has been detected in unlock command or if there was an attempt to access a locked card */
-  SD_COM_CRC_FAILED                  = (15),  /*!< CRC check of the previous command failed                     */
-  SD_ILLEGAL_CMD                     = (16),  /*!< Command is not legal for the card state                      */
-  SD_CARD_ECC_FAILED                 = (17),  /*!< Card internal ECC was applied but failed to correct the data */
-  SD_CC_ERROR                        = (18),  /*!< Internal card controller error                               */
-  SD_GENERAL_UNKNOWN_ERROR           = (19),  /*!< General or unknown error                                     */
-  SD_STREAM_READ_UNDERRUN            = (20),  /*!< The card could not sustain data transfer in stream read operation. */
-  SD_STREAM_WRITE_OVERRUN            = (21),  /*!< The card could not sustain data programming in stream mode   */
-  SD_CID_CSD_OVERWRITE               = (22),  /*!< CID/CSD overwrite error                                      */
-  SD_WP_ERASE_SKIP                   = (23),  /*!< Only partial address space was erased                        */
-  SD_CARD_ECC_DISABLED               = (24),  /*!< Command has been executed without using internal ECC         */
-  SD_ERASE_RESET                     = (25),  /*!< Erase sequence was cleared before executing because an out of erase sequence command was received */
-  SD_AKE_SEQ_ERROR                   = (26),  /*!< Error in sequence of authentication.                         */
-  SD_INVALID_VOLTRANGE               = (27),
-  SD_ADDR_OUT_OF_RANGE               = (28),
-  SD_SWITCH_ERROR                    = (29),
-  SD_SDIO_DISABLED                   = (30),
-  SD_SDIO_FUNCTION_BUSY              = (31),
-  SD_SDIO_FUNCTION_FAILED            = (32),
-  SD_SDIO_UNKNOWN_FUNCTION           = (33),
-
-/** 
-  * @brief  Standard error defines   
-  */ 
-  SD_INTERNAL_ERROR                  = (34),
-  SD_NOT_CONFIGURED                  = (35),
-  SD_REQUEST_PENDING                 = (36),
-  SD_REQUEST_NOT_APPLICABLE          = (37),
-  SD_INVALID_PARAMETER               = (38),
-  SD_UNSUPPORTED_FEATURE             = (39),
-  SD_UNSUPPORTED_HW                  = (40),
-  SD_ERROR                           = (41),
-  SD_OK                              = (0) 
-
-}HAL_SD_ErrorTypedef;
-
-/** 
-  * @brief  SD Transfer state enumeration structure
-  */   
-typedef enum
-{
-  SD_TRANSFER_OK    = 0,  /*!< Transfer success      */
-  SD_TRANSFER_BUSY  = 1,  /*!< Transfer is occurring */
-  SD_TRANSFER_ERROR = 2   /*!< Transfer failed       */
-
-}HAL_SD_TransferStateTypedef;
-
-/** 
-  * @brief  SD Card State enumeration structure 
-  */   
-typedef enum
-{
-  SD_CARD_READY                  = ((uint32_t)0x00000001),  /*!< Card state is ready                     */
-  SD_CARD_IDENTIFICATION         = ((uint32_t)0x00000002),  /*!< Card is in identification state         */
-  SD_CARD_STANDBY                = ((uint32_t)0x00000003),  /*!< Card is in standby state                */
-  SD_CARD_TRANSFER               = ((uint32_t)0x00000004),  /*!< Card is in transfer state               */  
-  SD_CARD_SENDING                = ((uint32_t)0x00000005),  /*!< Card is sending an operation            */
-  SD_CARD_RECEIVING              = ((uint32_t)0x00000006),  /*!< Card is receiving operation information */
-  SD_CARD_PROGRAMMING            = ((uint32_t)0x00000007),  /*!< Card is in programming state            */
-  SD_CARD_DISCONNECTED           = ((uint32_t)0x00000008),  /*!< Card is disconnected                    */
-  SD_CARD_ERROR                  = ((uint32_t)0x000000FF)   /*!< Card is in error state                  */
-
-}HAL_SD_CardStateTypedef;
-
-/** 
-  * @brief  SD Operation enumeration structure   
-  */   
-typedef enum
-{
-  SD_READ_SINGLE_BLOCK    = 0,  /*!< Read single block operation      */
-  SD_READ_MULTIPLE_BLOCK  = 1,  /*!< Read multiple blocks operation   */
-  SD_WRITE_SINGLE_BLOCK   = 2,  /*!< Write single block operation     */
-  SD_WRITE_MULTIPLE_BLOCK = 3   /*!< Write multiple blocks operation  */
-
-}HAL_SD_OperationTypedef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SD_Exported_Constants SD Exported Constants
-  * @{
-  */
-
-/** 
-  * @brief SD Commands Index 
-  */
-#define SD_CMD_GO_IDLE_STATE                       ((uint8_t)0)   /*!< Resets the SD memory card.                                                               */
-#define SD_CMD_SEND_OP_COND                        ((uint8_t)1)   /*!< Sends host capacity support information and activates the card's initialization process. */
-#define SD_CMD_ALL_SEND_CID                        ((uint8_t)2)   /*!< Asks any card connected to the host to send the CID numbers on the CMD line.             */
-#define SD_CMD_SET_REL_ADDR                        ((uint8_t)3)   /*!< Asks the card to publish a new relative address (RCA).                                   */
-#define SD_CMD_SET_DSR                             ((uint8_t)4)   /*!< Programs the DSR of all cards.                                                           */
-#define SD_CMD_SDIO_SEN_OP_COND                    ((uint8_t)5)   /*!< Sends host capacity support information (HCS) and asks the accessed card to send its 
-                                                                       operating condition register (OCR) content in the response on the CMD line.              */
-#define SD_CMD_HS_SWITCH                           ((uint8_t)6)   /*!< Checks switchable function (mode 0) and switch card function (mode 1).                   */
-#define SD_CMD_SEL_DESEL_CARD                      ((uint8_t)7)   /*!< Selects the card by its own relative address and gets deselected by any other address    */
-#define SD_CMD_HS_SEND_EXT_CSD                     ((uint8_t)8)   /*!< Sends SD Memory Card interface condition, which includes host supply voltage information 
-                                                                       and asks the card whether card supports voltage.                                         */
-#define SD_CMD_SEND_CSD                            ((uint8_t)9)   /*!< Addressed card sends its card specific data (CSD) on the CMD line.                       */
-#define SD_CMD_SEND_CID                            ((uint8_t)10)  /*!< Addressed card sends its card identification (CID) on the CMD line.                      */
-#define SD_CMD_READ_DAT_UNTIL_STOP                 ((uint8_t)11)  /*!< SD card doesn't support it.                                                              */
-#define SD_CMD_STOP_TRANSMISSION                   ((uint8_t)12)  /*!< Forces the card to stop transmission.                                                    */
-#define SD_CMD_SEND_STATUS                         ((uint8_t)13)  /*!< Addressed card sends its status register.                                                */
-#define SD_CMD_HS_BUSTEST_READ                     ((uint8_t)14) 
-#define SD_CMD_GO_INACTIVE_STATE                   ((uint8_t)15)  /*!< Sends an addressed card into the inactive state.                                         */
-#define SD_CMD_SET_BLOCKLEN                        ((uint8_t)16)  /*!< Sets the block length (in bytes for SDSC) for all following block commands 
-                                                                       (read, write, lock). Default block length is fixed to 512 Bytes. Not effective 
-                                                                       for SDHS and SDXC.                                                                       */
-#define SD_CMD_READ_SINGLE_BLOCK                   ((uint8_t)17)  /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_READ_MULT_BLOCK                     ((uint8_t)18)  /*!< Continuously transfers data blocks from card to host until interrupted by 
-                                                                       STOP_TRANSMISSION command.                                                               */
-#define SD_CMD_HS_BUSTEST_WRITE                    ((uint8_t)19)  /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104.                                    */
-#define SD_CMD_WRITE_DAT_UNTIL_STOP                ((uint8_t)20)  /*!< Speed class control command.                                                             */
-#define SD_CMD_SET_BLOCK_COUNT                     ((uint8_t)23)  /*!< Specify block count for CMD18 and CMD25.                                                 */
-#define SD_CMD_WRITE_SINGLE_BLOCK                  ((uint8_t)24)  /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of 
-                                                                       fixed 512 bytes in case of SDHC and SDXC.                                                */
-#define SD_CMD_WRITE_MULT_BLOCK                    ((uint8_t)25)  /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows.                    */
-#define SD_CMD_PROG_CID                            ((uint8_t)26)  /*!< Reserved for manufacturers.                                                              */
-#define SD_CMD_PROG_CSD                            ((uint8_t)27)  /*!< Programming of the programmable bits of the CSD.                                         */
-#define SD_CMD_SET_WRITE_PROT                      ((uint8_t)28)  /*!< Sets the write protection bit of the addressed group.                                    */
-#define SD_CMD_CLR_WRITE_PROT                      ((uint8_t)29)  /*!< Clears the write protection bit of the addressed group.                                  */
-#define SD_CMD_SEND_WRITE_PROT                     ((uint8_t)30)  /*!< Asks the card to send the status of the write protection bits.                           */
-#define SD_CMD_SD_ERASE_GRP_START                  ((uint8_t)32)  /*!< Sets the address of the first write block to be erased. (For SD card only).              */
-#define SD_CMD_SD_ERASE_GRP_END                    ((uint8_t)33)  /*!< Sets the address of the last write block of the continuous range to be erased.           */
-#define SD_CMD_ERASE_GRP_START                     ((uint8_t)35)  /*!< Sets the address of the first write block to be erased. Reserved for each command 
-                                                                       system set by switch function command (CMD6).                                            */
-#define SD_CMD_ERASE_GRP_END                       ((uint8_t)36)  /*!< Sets the address of the last write block of the continuous range to be erased. 
-                                                                       Reserved for each command system set by switch function command (CMD6).                  */
-#define SD_CMD_ERASE                               ((uint8_t)38)  /*!< Reserved for SD security applications.                                                   */
-#define SD_CMD_FAST_IO                             ((uint8_t)39)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_GO_IRQ_STATE                        ((uint8_t)40)  /*!< SD card doesn't support it (Reserved).                                                   */
-#define SD_CMD_LOCK_UNLOCK                         ((uint8_t)42)  /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by 
-                                                                       the SET_BLOCK_LEN command.                                                               */
-#define SD_CMD_APP_CMD                             ((uint8_t)55)  /*!< Indicates to the card that the next command is an application specific command rather 
-                                                                       than a standard command.                                                                 */
-#define SD_CMD_GEN_CMD                             ((uint8_t)56)  /*!< Used either to transfer a data block to the card or to get a data block from the card 
-                                                                       for general purpose/application specific commands.                                       */
-#define SD_CMD_NO_CMD                              ((uint8_t)64) 
-
-/** 
-  * @brief Following commands are SD Card Specific commands.
-  *        SDIO_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_APP_SD_SET_BUSWIDTH                 ((uint8_t)6)   /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus 
-                                                                       widths are given in SCR register.                                                          */
-#define SD_CMD_SD_APP_STAUS                        ((uint8_t)13)  /*!< (ACMD13) Sends the SD status.                                                              */
-#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS        ((uint8_t)22)  /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with 
-                                                                       32bit+CRC data block.                                                                      */
-#define SD_CMD_SD_APP_OP_COND                      ((uint8_t)41)  /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to 
-                                                                       send its operating condition register (OCR) content in the response on the CMD line.       */
-#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT          ((uint8_t)42)  /*!< (ACMD42) Connects/Disconnects the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card. */
-#define SD_CMD_SD_APP_SEND_SCR                     ((uint8_t)51)  /*!< Reads the SD Configuration Register (SCR).                                                 */
-#define SD_CMD_SDIO_RW_DIRECT                      ((uint8_t)52)  /*!< For SD I/O card only, reserved for security specification.                                 */
-#define SD_CMD_SDIO_RW_EXTENDED                    ((uint8_t)53)  /*!< For SD I/O card only, reserved for security specification.                                 */
-
-/** 
-  * @brief Following commands are SD Card Specific security commands.
-  *        SD_CMD_APP_CMD should be sent before sending these commands. 
-  */
-#define SD_CMD_SD_APP_GET_MKB                      ((uint8_t)43)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_MID                      ((uint8_t)44)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RN1                  ((uint8_t)45)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RN2                  ((uint8_t)46)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SET_CER_RES2                 ((uint8_t)47)  /*!< For SD card only */
-#define SD_CMD_SD_APP_GET_CER_RES1                 ((uint8_t)48)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK   ((uint8_t)18)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK  ((uint8_t)25)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_ERASE                 ((uint8_t)38)  /*!< For SD card only */
-#define SD_CMD_SD_APP_CHANGE_SECURE_AREA           ((uint8_t)49)  /*!< For SD card only */
-#define SD_CMD_SD_APP_SECURE_WRITE_MKB             ((uint8_t)48)  /*!< For SD card only */
-
-/** 
-  * @brief Supported SD Memory Cards 
-  */
-#define STD_CAPACITY_SD_CARD_V1_1             ((uint32_t)0x00000000)
-#define STD_CAPACITY_SD_CARD_V2_0             ((uint32_t)0x00000001)
-#define HIGH_CAPACITY_SD_CARD                 ((uint32_t)0x00000002)
-#define MULTIMEDIA_CARD                       ((uint32_t)0x00000003)
-#define SECURE_DIGITAL_IO_CARD                ((uint32_t)0x00000004)
-#define HIGH_SPEED_MULTIMEDIA_CARD            ((uint32_t)0x00000005)
-#define SECURE_DIGITAL_IO_COMBO_CARD          ((uint32_t)0x00000006)
-#define HIGH_CAPACITY_MMC_CARD                ((uint32_t)0x00000007)
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SD_Exported_macros SD Exported Macros
-  * @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
- 
-/**
-  * @brief  Enable the SD device.
-  * @retval None
-  */ 
-#define __HAL_SD_SDIO_ENABLE() __SDIO_ENABLE()
-
-/**
-  * @brief  Disable the SD device.
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DISABLE() __SDIO_DISABLE()
-
-/**
-  * @brief  Enable the SDIO DMA transfer.
-  * @retval None
-  */ 
-#define __HAL_SD_SDIO_DMA_ENABLE() __SDIO_DMA_ENABLE()
-
-/**
-  * @brief  Disable the SDIO DMA transfer.
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DMA_DISABLE()  __SDIO_DMA_DISABLE()
- 
-/**
-  * @brief  Enable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __HAL_SD_SDIO_ENABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_ENABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SD device interrupt.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __HAL_SD_SDIO_DISABLE_IT(__HANDLE__, __INTERRUPT__) __SDIO_DISABLE_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-
-/**
-  * @brief  Check whether the specified SD flag is set or not. 
-  * @param  __HANDLE__: SD Handle   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
-  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval The new state of SD FLAG (SET or RESET).
-  */
-#define __HAL_SD_SDIO_GET_FLAG(__HANDLE__, __FLAG__) __SDIO_GET_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Clear the SD's pending flags.
-  * @param  __HANDLE__: SD Handle  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __HAL_SD_SDIO_CLEAR_FLAG(__HANDLE__, __FLAG__) __SDIO_CLEAR_FLAG((__HANDLE__)->Instance, (__FLAG__))
-
-/**
-  * @brief  Check whether the specified SD interrupt has occurred or not.
-  * @param  __HANDLE__: SD Handle   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
-  * @retval The new state of SD IT (SET or RESET).
-  */
-#define __HAL_SD_SDIO_GET_IT  (__HANDLE__, __INTERRUPT__) __SDIO_GET_IT  ((__HANDLE__)->Instance, __INTERRUPT__)
-
-/**
-  * @brief  Clear the SD's interrupt pending bits.
-  * @param  __HANDLE__ : SD Handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __HAL_SD_SDIO_CLEAR_IT(__HANDLE__, __INTERRUPT__) __SDIO_CLEAR_IT((__HANDLE__)->Instance, (__INTERRUPT__))
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SD_Exported_Functions
-  * @{
-  */
-
-/* Initialization and de-initialization functions  **********************************/
-/** @addtogroup SD_Exported_Functions_Group1
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Init(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *SDCardInfo);
-HAL_StatusTypeDef   HAL_SD_DeInit (SD_HandleTypeDef *hsd);
-void HAL_SD_MspInit(SD_HandleTypeDef *hsd);
-void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup SD_Exported_Functions_Group2
-  * @{
-  */
-/* Blocking mode: Polling */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint64_t startaddr, uint64_t endaddr);
-
-/* Non-Blocking mode: Interrupt */
-void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd);
-
-/* Callback in non blocking modes (DMA) */
-void HAL_SD_DMA_RxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_RxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxCpltCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_DMA_TxErrorCallback(DMA_HandleTypeDef *hdma);
-void HAL_SD_XferCpltCallback(SD_HandleTypeDef *hsd);
-void HAL_SD_XferErrorCallback(SD_HandleTypeDef *hsd);
-
-/* Non-Blocking mode: DMA */
-HAL_SD_ErrorTypedef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pReadBuffer, uint64_t ReadAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint32_t *pWriteBuffer, uint64_t WriteAddr, uint32_t BlockSize, uint32_t NumberOfBlocks);
-HAL_SD_ErrorTypedef HAL_SD_CheckWriteOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-HAL_SD_ErrorTypedef HAL_SD_CheckReadOperation(SD_HandleTypeDef *hsd, uint32_t Timeout);
-/**
-  * @}
-  */
-  
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup SD_Exported_Functions_Group3
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_Get_CardInfo(SD_HandleTypeDef *hsd, HAL_SD_CardInfoTypedef *pCardInfo);
-HAL_SD_ErrorTypedef HAL_SD_WideBusOperation_Config(SD_HandleTypeDef *hsd, uint32_t WideMode);
-HAL_SD_ErrorTypedef HAL_SD_StopTransfer(SD_HandleTypeDef *hsd);
-HAL_SD_ErrorTypedef HAL_SD_HighSpeed (SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-  
-/* Peripheral State functions  **************************************************/
-/** @addtogroup SD_Exported_Functions_Group4
-  * @{
-  */
-HAL_SD_ErrorTypedef HAL_SD_SendSDStatus(SD_HandleTypeDef *hsd, uint32_t *pSDstatus);
-HAL_SD_ErrorTypedef HAL_SD_GetCardStatus(SD_HandleTypeDef *hsd, HAL_SD_CardStatusTypedef *pCardStatus);
-HAL_SD_TransferStateTypedef HAL_SD_GetStatus(SD_HandleTypeDef *hsd);
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#endif /* __STM32L1xx_HAL_SD_H */ 
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1411 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_smartcard.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   SMARTCARD HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the SMARTCARD peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State and Errors functions
-  *           + Peripheral Control functions
-  *
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The SMARTCARD HAL driver can be used as follows:
-
-    (#) Declare a SMARTCARD_HandleTypeDef handle structure.
-    (#) Initialize the SMARTCARD low level resources by implementing the HAL_SMARTCARD_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) SMARTCARD pins configuration:
-            (+++) Enable the clock for the SMARTCARD GPIOs.
-            (+++) Configure these SMARTCARD pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_SMARTCARD_Transmit_IT()
-             and HAL_SMARTCARD_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_SMARTCARD_Transmit_DMA()
-             and HAL_SMARTCARD_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initilalized DMA handle to the SMARTCARD DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
-    (#) Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
-        flow control and Mode(Receiver/Transmitter) in the SMARTCARD Init structure.
-
-    (#) Initialize the SMARTCARD registers by calling the HAL_SMARTCARD_Init() API:
-        (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customed HAL_SMARTCARD_MspInit(&hsc) API.
-
-        -@@- The specific SMARTCARD interrupts (Transmission complete interrupt, 
-             RXNE interrupt and Error Interrupts) will be managed using the macros
-             __HAL_SMARTCARD_ENABLE_IT() and __HAL_SMARTCARD_DISABLE_IT() inside the transmit and receive process.
-          
-    (#) Three operation modes are available within this driver :
- 
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Send an amount of data in blocking mode using HAL_SMARTCARD_Transmit() 
-       (+) Receive an amount of data in blocking mode using HAL_SMARTCARD_Receive()
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Send an amount of data in non blocking mode using HAL_SMARTCARD_Transmit_IT() 
-       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_SMARTCARD_Receive_IT() 
-       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
-
-     *** DMA mode IO operation ***    
-     ==============================
-     [..] 
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Transmit_DMA() 
-       (+) At transmission end of transfer HAL_SMARTCARD_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_SMARTCARD_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_SMARTCARD_Receive_DMA() 
-       (+) At reception end of transfer HAL_SMARTCARD_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_SMARTCARD_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_SMARTCARD_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_SMARTCARD_ErrorCallback
-
-     *** SMARTCARD HAL driver macros list ***
-     ========================================
-     [..]
-       Below the list of most used macros in SMARTCARD HAL driver.
-       
-       (+) __HAL_SMARTCARD_ENABLE: Enable the SMARTCARD peripheral 
-       (+) __HAL_SMARTCARD_DISABLE: Disable the SMARTCARD peripheral     
-       (+) __HAL_SMARTCARD_GET_FLAG : Check whether the specified SMARTCARD flag is set or not
-       (+) __HAL_SMARTCARD_CLEAR_FLAG : Clear the specified SMARTCARD pending flag
-       (+) __HAL_SMARTCARD_ENABLE_IT: Enable the specified SMARTCARD interrupt
-       (+) __HAL_SMARTCARD_DISABLE_IT: Disable the specified SMARTCARD interrupt
-      
-     [..] 
-       (@) You can refer to the SMARTCARD HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SMARTCARD SMARTCARD
-  * @brief HAL SMARTCARD module driver
-  * @{
-  */
-
-#ifdef HAL_SMARTCARD_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Constants   SMARTCARD Private Constants
-  * @{
-  */
-#define SMARTCARD_TIMEOUT_VALUE  22000
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup SMARTCARD_Private_Functions   SMARTCARD Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc);
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard);
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_SetConfig (SMARTCARD_HandleTypeDef *hsc);
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
-  * @{
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim
-
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-  This subsection provides a set of functions allowing to initialize the USART 
-  in Smartcard mode.
-  [..]
-  The Smartcard interface is designed to support asynchronous protocol Smartcards as
-  defined in the ISO 7816-3 standard.
-  [..]
-  The USART can provide a clock to the smartcard through the SCLK output.
-  In smartcard mode, SCLK is not associated to the communication but is simply derived 
-  from the internal peripheral input clock through a 5-bit prescaler.
-  [..]
-  (+) For the Smartcard mode only these parameters can be configured:
-      (++) Baud Rate
-      (++) Word Length => Should be 9 bits (8 bits + parity)
-      (++) Stop Bit
-      (++) Parity: => Should be enabled 
-   +-------------------------------------------------------------+
-   |   M bit |  PCE bit  |        SMARTCARD frame                |
-   |---------------------|---------------------------------------|
-   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-   +-------------------------------------------------------------+
-      (++) USART polarity
-      (++) USART phase
-      (++) USART LastBit
-      (++) Receiver/transmitter modes
-      (++) Prescaler
-      (++) GuardTime
-      (++) NACKState: The Smartcard NACK state
-
-     (+) Recommended SmartCard interface configuration to get the Answer to Reset from the Card:
-        (++) Word Length = 9 Bits
-        (++) 1.5 Stop Bit
-        (++) Even parity
-        (++) BaudRate = 12096 baud
-        (++) Tx and Rx enabled
-  [..]
-  Please refer to the ISO 7816-3 specification for more details.
-
-    -@- It is also possible to choose 0.5 stop bit for receiving but it is recommended 
-        to use 1.5 stop bits for both transmitting and receiving to avoid switching 
-        between the two configurations.
-  [..]
-  The HAL_SMARTCARD_Init() function follows the USART  SmartCard configuration 
-  procedure (details for the procedure are available in reference manual (RM0038)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SmartCard mode according to the specified
-  *         parameters in the SMARTCARD_HandleTypeDef and create the associated handle.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *              the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Check the SMARTCARD handle allocation */
-  if(hsc == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-  assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
-
-  if(hsc->State == HAL_SMARTCARD_STATE_RESET)
-  {  
-    /* Init the low level hardware */
-    HAL_SMARTCARD_MspInit(hsc);
-  }
-  
-  hsc->State = HAL_SMARTCARD_STATE_BUSY;
-
-  /* Set the Prescaler */
-  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_PSC, hsc->Init.Prescaler);
-
-  /* Set the Guard Time */
-  MODIFY_REG(hsc->Instance->GTPR, USART_GTPR_GT, ((hsc->Init.GuardTime)<<8));
-
-  /* Set the Smartcard Communication parameters */
-  SMARTCARD_SetConfig(hsc);
-
-  /* In SmartCard mode, the following bits must be kept cleared: 
-  - LINEN bit in the USART_CR2 register
-  - HDSEL and IREN bits in the USART_CR3 register.*/
-  CLEAR_BIT(hsc->Instance->CR2, USART_CR2_LINEN);
-  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_IREN | USART_CR3_HDSEL));
-
-  /* Enable the SMARTCARD Parity Error Interrupt */
-  __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
-
-  /* Enable the SMARTCARD Framing Error Interrupt */
-  __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
-
-  /* Enable the Peripharal */
-  __HAL_SMARTCARD_ENABLE(hsc);
-
-  /* Configure the Smartcard NACK state */
-  MODIFY_REG(hsc->Instance->CR3, USART_CR3_NACK, hsc->Init.NACKState);
-
-  /* Enable the SC mode by setting the SCEN bit in the CR3 register */
-  SET_BIT(hsc->Instance->CR3, USART_CR3_SCEN);
-
-  /* Initialize the SMARTCARD state*/
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-  hsc->State= HAL_SMARTCARD_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the SMARTCARD peripheral
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *              the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Check the SMARTCARD handle allocation */
-  if(hsc == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-
-  hsc->State = HAL_SMARTCARD_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_SMARTCARD_DISABLE(hsc);
-
-  /* DeInit the low level hardware */
-  HAL_SMARTCARD_MspDeInit(hsc);
-
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-  hsc->State = HAL_SMARTCARD_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hsc);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  SMARTCARD MSP Init.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
- __weak void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_SMARTCARD_MspInit can be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SMARTCARD MSP DeInit.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
- __weak void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_SMARTCARD_MspDeInit can be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group2 IO operation functions 
-  *  @brief   SMARTCARD Transmit and Receive functions 
-  *
-@verbatim
-  ==============================================================================
-                         ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the SMARTCARD data transfers.
-
-  [..]
-    Smartcard is a single wire half duplex communication protocol. 
-    The Smartcard interface is designed to support asynchronous protocol Smartcards as
-    defined in the ISO 7816-3 standard. The USART should be configured as:
-    - 8 bits plus parity: where M=1 and PCE=1 in the USART_CR1 register
-    - 1.5 stop bits when transmitting and receiving: where STOP=11 in the USART_CR2 register.
-
-    (#) There are two modes of transfer:
-        (++) Blocking mode: The communication is performed in polling mode. 
-             The HAL status of all data processing is returned by the same function 
-             after finishing transfer.  
-        (++) No-Blocking mode: The communication is performed using Interrupts 
-             or DMA, These API's return the HAL status.
-             The end of the data processing will be indicated through the 
-             dedicated SMARTCARD IRQ when using Interrupt mode or the DMA IRQ when 
-             using DMA mode.
-             The HAL_SMARTCARD_TxCpltCallback(), HAL_SMARTCARD_RxCpltCallback() user callbacks 
-             will be executed respectivelly at the end of the Transmit or Receive process
-             The HAL_SMARTCARD_ErrorCallback() user callback will be executed when a communication 
-             error is detected
-
-    (#) Blocking mode APIs are :
-        (++) HAL_SMARTCARD_Transmit()
-        (++) HAL_SMARTCARD_Receive()
-
-    (#) Non Blocking mode APIs with Interrupt are :
-        (++) HAL_SMARTCARD_Transmit_IT()
-        (++) HAL_SMARTCARD_Receive_IT()
-        (++) HAL_SMARTCARD_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) HAL_SMARTCARD_Transmit_DMA()
-        (++) HAL_SMARTCARD_Receive_DMA()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_SMARTCARD_TxCpltCallback()
-        (++) HAL_SMARTCARD_RxCpltCallback()
-        (++) HAL_SMARTCARD_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Specify timeout value  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp = 0;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-    }
-    
-    hsc->TxXferSize = Size;
-    hsc->TxXferCount = Size;
-    while(hsc->TxXferCount > 0)
-    {
-      if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
-      {
-        if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pData;
-        WRITE_REG(hsc->Instance->DR, (*tmp & (uint16_t)0x01FF));
-        if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
-        {
-          pData +=2;
-        }
-        else
-        {
-          pData +=1;
-        }
-      }
-      else
-      {
-        if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        WRITE_REG(hsc->Instance->DR, (*pData++ & (uint8_t)0xFF));
-      }
-      hsc->TxXferCount--;
-    }
-
-    if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, Timeout) != HAL_OK)
-    {
-      return HAL_TIMEOUT;
-    }
-
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_READY;
-    }
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode. 
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @param  Timeout: Specify timeout value    
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp = 0;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-    
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
-
-    hsc->RxXferSize = Size;
-    hsc->RxXferCount = Size;
-    /* Check the remain data to be received */
-    while(hsc->RxXferCount > 0)
-    {
-      if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
-      {
-        if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pData;
-        if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
-        {
-          *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
-          pData +=2;
-        }
-        else
-        {
-          *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
-          pData +=1;
-        }
-      }
-      else
-      {
-        if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
-        {
-          *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
-        }
-        else
-        {
-          *pData++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
-        }
-      }
-      hsc->RxXferCount--;
-    }
-
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_READY;
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non-blocking mode. 
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->pTxBuffPtr = pData;
-    hsc->TxXferSize = Size;
-    hsc->TxXferCount = Size;
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-    }
-
-    /* Enable the SMARTCARD Parity Error Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
-
-    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    /* Enable the SMARTCARD Transmit data register empty Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TXE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in non-blocking mode. 
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->pRxBuffPtr = pData;
-    hsc->RxXferSize = Size;
-    hsc->RxXferCount = Size;
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
-
-    /* Enable the SMARTCARD Data Register not empty Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_RXNE); 
-
-    /* Enable the SMARTCARD Parity Error Interrupt */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_PE);
-
-    /* Enable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non-blocking mode. 
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp = 0;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->pTxBuffPtr = pData;
-    hsc->TxXferSize = Size;
-    hsc->TxXferCount = Size;
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-    }
-
-    /* Set the SMARTCARD DMA transfer complete callback */
-    hsc->hdmatx->XferCpltCallback = SMARTCARD_DMATransmitCplt;
-
-    /* Set the DMA error callback */
-    hsc->hdmatx->XferErrorCallback = SMARTCARD_DMAError;
-
-    /* Enable the SMARTCARD transmit DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hsc->hdmatx, *(uint32_t*)tmp, (uint32_t)&hsc->Instance->DR, Size);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-    in the SMARTCARD CR3 register */
-    SET_BIT(hsc->Instance->CR3,USART_CR3_DMAT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode. 
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @note   When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp = 0;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_READY) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hsc);
-
-    hsc->pRxBuffPtr = pData;
-    hsc->RxXferSize = Size;
-
-    hsc->ErrorCode = HAL_SMARTCARD_ERROR_NONE;
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
-
-    /* Set the SMARTCARD DMA transfer complete callback */
-    hsc->hdmarx->XferCpltCallback = SMARTCARD_DMAReceiveCplt;
-
-    /* Set the DMA error callback */
-    hsc->hdmarx->XferErrorCallback = SMARTCARD_DMAError;
-
-    /* Enable the DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(hsc->hdmarx, (uint32_t)&hsc->Instance->DR, *(uint32_t*)tmp, Size);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-    in the SMARTCARD CR3 register */
-    SET_BIT(hsc->Instance->CR3,USART_CR3_DMAR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hsc);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  This function handles SMARTCARD interrupt request.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc)
-{
-  uint32_t  tmp1 = 0, tmp2 = 0;
-  
-  tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_PE);
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_PE);
-  /* SMARTCARD parity error interrupt occurred -----------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_SMARTCARD_CLEAR_PEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_PE;
-  }
-
-  tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_FE);
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD frame error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_SMARTCARD_CLEAR_FEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_FE;
-  }
-
-  tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_NE);
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD noise error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_SMARTCARD_CLEAR_NEFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_NE;
-  }
-
-  tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_ORE);
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_ERR);
-  /* SMARTCARD Over-Run interrupt occurred ---------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_SMARTCARD_CLEAR_OREFLAG(hsc);
-    hsc->ErrorCode |= HAL_SMARTCARD_ERROR_ORE;
-  }
-  
-  tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_RXNE);
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_RXNE);
-  /* SMARTCARD in mode Receiver --------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    SMARTCARD_Receive_IT(hsc);
-  }
-
-  tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TXE);
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TXE);
-  /* SMARTCARD in mode Transmitter -----------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    SMARTCARD_Transmit_IT(hsc);
-  }
-  
-  tmp1 = __HAL_SMARTCARD_GET_FLAG(hsc, SMARTCARD_FLAG_TC);
-  tmp2 = __HAL_SMARTCARD_GET_IT_SOURCE(hsc, SMARTCARD_IT_TC);
-  /* SMARTCARD in mode Transmitter (transmission end) ------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    SMARTCARD_EndTransmit_IT(hsc);
-  } 
-
-  /* Call the Error call Back in case of Errors */
-  if(hsc->ErrorCode != HAL_SMARTCARD_ERROR_NONE)
-  {
-    /* Set the SMARTCARD state ready to be able to start again the process */
-    hsc->State= HAL_SMARTCARD_STATE_READY;
-    HAL_SMARTCARD_ErrorCallback(hsc);
-  }
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
- __weak void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_SMARTCARD_TxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-__weak void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_SMARTCARD_RxCpltCallback can be implemented in the user file
-   */
-}
-
-/**
-  * @brief  SMARTCARD error callbacks.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
- __weak void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* NOTE: This function should not be modified, when the callback is needed,
-           the HAL_SMARTCARD_ErrorCallback can be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   SMARTCARD State and Errors functions 
-  *
-@verbatim   
-  ==============================================================================
-                  ##### Peripheral State and Errors functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to return the State of SmartCard 
-    communication process and also return Peripheral Errors occurred during communication process
-     (+) HAL_SMARTCARD_GetState() API can be helpful to check in run-time the state 
-         of the SMARTCARD peripheral.
-     (+) HAL_SMARTCARD_GetError() check in run-time errors that could be occurred during 
-         communication.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the SMARTCARD state.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval HAL state
-  */
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc)
-{
-  return hsc->State;
-}
-
-/**
-  * @brief  Return the SMARTCARD error code
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval SMARTCARD Error Code
-  */
-uint32_t HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc)
-{
-  return hsc->ErrorCode;
-}
-
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Private_Functions   SMARTCARD Private Functions
-  *  @brief   SMARTCARD Private functions 
-  * @{
-  */
-/**
-  * @brief  DMA SMARTCARD transmit process complete callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->TxXferCount = 0;
-
-  /* Disable the DMA transfer for transmit request by setting the DMAT bit
-     in the SMARTCARD CR3 register */
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAT);
-
-  /* Wait for SMARTCARD TC Flag */
-  if(SMARTCARD_WaitOnFlagUntilTimeout(hsc, SMARTCARD_FLAG_TC, RESET, SMARTCARD_TIMEOUT_VALUE) != HAL_OK)
-  {
-    /* Timeout occurred */ 
-    hsc->State = HAL_SMARTCARD_STATE_TIMEOUT;
-    HAL_SMARTCARD_ErrorCallback(hsc);
-  }
-  else
-  {
-    /* No Timeout */
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-    {
-      hsc->State = HAL_SMARTCARD_STATE_BUSY_RX;
-    }
-    else
-    {
-      hsc->State = HAL_SMARTCARD_STATE_READY;
-    }
-    HAL_SMARTCARD_TxCpltCallback(hsc);
-  }
-}
-
-/**
-  * @brief  DMA SMARTCARD receive process complete callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)   
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  hsc->RxXferCount = 0;
-
-  /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
-     in the USART CR3 register */
-  CLEAR_BIT(hsc->Instance->CR3, USART_CR3_DMAR);
-
-  /* Check if a non-blocking transmit process is ongoing or not */
-  if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-  {
-    hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-  }
-  else
-  {
-    hsc->State = HAL_SMARTCARD_STATE_READY;
-  }
-
-  HAL_SMARTCARD_RxCpltCallback(hsc);
-}
-
-/**
-  * @brief  DMA SMARTCARD communication error callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SMARTCARD_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  SMARTCARD_HandleTypeDef* hsc = ( SMARTCARD_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  
-  hsc->RxXferCount = 0;
-  hsc->TxXferCount = 0;
-  hsc->ErrorCode = HAL_SMARTCARD_ERROR_DMA; 
-  hsc->State= HAL_SMARTCARD_STATE_READY;
-  
-  HAL_SMARTCARD_ErrorCallback(hsc);
-}
-
-/**
-  * @brief  This function handles SMARTCARD Communication Timeout.
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @param  Flag: specifies the SMARTCARD flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE and RXNE interrupts for the interrupt process */
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-
-          hsc->State= HAL_SMARTCARD_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsc);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_SMARTCARD_GET_FLAG(hsc, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE and RXNE interrupts for the interrupt process */
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-          __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-
-          hsc->State= HAL_SMARTCARD_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hsc);
-        
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Send an amount of data in non-blocking mode. 
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  *         Function called under interruption only, once
-  *         interruptions have been enabled by HAL_SMARTCARD_Transmit_IT()      
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc)
-{
-  uint16_t* tmp = 0;
-  uint32_t tmp1 = 0;
-
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_BUSY_TX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
-  {
-    if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) hsc->pTxBuffPtr;
-      WRITE_REG(hsc->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
-      if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
-      {
-        hsc->pTxBuffPtr += 2;
-      }
-      else
-      {
-        hsc->pTxBuffPtr += 1;
-      }
-    } 
-    else
-    {
-      WRITE_REG(hsc->Instance->DR, (uint8_t)(*hsc->pTxBuffPtr++ & (uint8_t)0x00FF));
-    }
-    
-    if(--hsc->TxXferCount == 0)
-    {
-      /* Disable the SMARTCARD Transmit Data Register Empty Interrupt */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_TXE);
-
-      /* Enable the SMARTCARD Transmit Complete Interrupt */    
-      __HAL_SMARTCARD_ENABLE_IT(hsc, SMARTCARD_IT_TC);
-    }
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_EndTransmit_IT(SMARTCARD_HandleTypeDef *hsmartcard)
-{
-  /* Disable the SMARTCARD Transmit Complete Interrupt */    
-  __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_TC);
-  
-  /* Check if a receive process is ongoing or not */
-  if(hsmartcard->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-  {
-    hsmartcard->State = HAL_SMARTCARD_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_ERR);
-    
-    /* Disable the SMARTCARD Parity Error Interrupt */
-    __HAL_SMARTCARD_DISABLE_IT(hsmartcard, SMARTCARD_IT_PE);
-        
-    hsmartcard->State = HAL_SMARTCARD_STATE_READY;
-  }
-  
-  HAL_SMARTCARD_TxCpltCallback(hsmartcard);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Receive an amount of data in non-blocking mode. 
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc)
-{
-  uint16_t* tmp = 0;
-  uint32_t tmp1 = 0;
-
-  tmp1 = hsc->State;
-  if((tmp1 == HAL_SMARTCARD_STATE_BUSY_RX) || (tmp1 == HAL_SMARTCARD_STATE_BUSY_TX_RX))
-  {
-    if(hsc->Init.WordLength == SMARTCARD_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) hsc->pRxBuffPtr;
-      if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
-      {
-        *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x01FF);
-        hsc->pRxBuffPtr += 2;
-      }
-      else
-      {
-        *tmp = (uint16_t)(hsc->Instance->DR & (uint16_t)0x00FF);
-        hsc->pRxBuffPtr += 1;
-      }
-    } 
-    else
-    {
-      if(hsc->Init.Parity == SMARTCARD_PARITY_NONE)
-      {
-        *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x00FF);
-      }
-      else
-      {
-        *hsc->pRxBuffPtr++ = (uint8_t)(hsc->Instance->DR & (uint8_t)0x007F);
-      }
-    }
-    
-    if(--hsc->RxXferCount == 0)
-    {
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_RXNE);
-      
-      /* Disable the SMARTCARD Parity Error Interrupt */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_PE);
-
-      /* Disable the SMARTCARD Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_SMARTCARD_DISABLE_IT(hsc, SMARTCARD_IT_ERR);
-
-      /* Check if a non-blocking transmit process is ongoing or not */
-      if(hsc->State == HAL_SMARTCARD_STATE_BUSY_TX_RX) 
-      {
-        hsc->State = HAL_SMARTCARD_STATE_BUSY_TX;
-      }
-      else
-      {
-        hsc->State = HAL_SMARTCARD_STATE_READY;
-      }
-
-      HAL_SMARTCARD_RxCpltCallback(hsc);
-
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Configures the SMARTCARD peripheral. 
-  * @param  hsc: Pointer to a SMARTCARD_HandleTypeDef structure that contains
-  *                the configuration information for the specified SMARTCARD module.
-  * @retval None
-  */
-static void SMARTCARD_SetConfig(SMARTCARD_HandleTypeDef *hsc)
-{
-  /* Check the parameters */
-  assert_param(IS_SMARTCARD_INSTANCE(hsc->Instance));
-  assert_param(IS_SMARTCARD_POLARITY(hsc->Init.CLKPolarity));
-  assert_param(IS_SMARTCARD_PHASE(hsc->Init.CLKPhase));
-  assert_param(IS_SMARTCARD_LASTBIT(hsc->Init.CLKLastBit));
-  assert_param(IS_SMARTCARD_BAUDRATE(hsc->Init.BaudRate));  
-  assert_param(IS_SMARTCARD_WORD_LENGTH(hsc->Init.WordLength));
-  assert_param(IS_SMARTCARD_STOPBITS(hsc->Init.StopBits));
-  assert_param(IS_SMARTCARD_PARITY(hsc->Init.Parity));
-  assert_param(IS_SMARTCARD_MODE(hsc->Init.Mode));
-  assert_param(IS_SMARTCARD_NACK_STATE(hsc->Init.NACKState));
-
-  /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
-     receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
-  CLEAR_BIT(hsc->Instance->CR1, (uint32_t)(USART_CR1_TE | USART_CR1_RE));
-  
-  /*-------------------------- SMARTCARD CR2 Configuration ------------------------*/
-  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
-  /* Configure the SMARTCARD Clock, CPOL, CPHA and LastBit -----------------------*/
-  /* Set CPOL bit according to hsc->Init.CLKPolarity value */
-  /* Set CPHA bit according to hsc->Init.CLKPhase value */
-  /* Set LBCL bit according to hsc->Init.CLKLastBit value */
-  MODIFY_REG(hsc->Instance->CR2, 
-             ((uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL)),
-             ((uint32_t)(USART_CR2_CLKEN | hsc->Init.CLKPolarity | hsc->Init.CLKPhase| hsc->Init.CLKLastBit)) );
-  
-  /* Set Stop Bits: Set STOP[13:12] bits according to hsc->Init.StopBits value */
-  MODIFY_REG(hsc->Instance->CR2, USART_CR2_STOP,(uint32_t)(hsc->Init.StopBits));
-
-  /*-------------------------- SMARTCARD CR1 Configuration -----------------------*/
-  /* Clear M, PCE, PS, TE and RE bits */
-  /* Configure the SMARTCARD Word Length, Parity and mode: 
-     Set the M bits according to hsc->Init.WordLength value 
-     Set PCE and PS bits according to hsc->Init.Parity value
-     Set TE and RE bits according to hsc->Init.Mode value */
-  MODIFY_REG(hsc->Instance->CR1, 
-             ((uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE)),
-             ((uint32_t)(hsc->Init.WordLength | hsc->Init.Parity | hsc->Init.Mode)) );
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
-  /* Clear CTSE and RTSE bits */
-  CLEAR_BIT(hsc->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE));
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  if(hsc->Instance == USART1)
-  {
-    hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK2Freq(), hsc->Init.BaudRate);
-  }
-  else
-  {
-    hsc->Instance->BRR = SMARTCARD_BRR(HAL_RCC_GetPCLK1Freq(), hsc->Init.BaudRate);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SMARTCARD_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_smartcard.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,587 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_smartcard.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   This file contains all the functions prototypes for the SMARTCARD 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_SMARTCARD_H
-#define __STM32L1xx_HAL_SMARTCARD_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SMARTCARD
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SMARTCARD_Exported_Types SMARTCARD Exported Types
-  * @{
-  */ 
-
-
-/** 
-  * @brief SMARTCARD Init Structure definition
-  */
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the SmartCard communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (hsc->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref SMARTCARD_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref SMARTCARD_Stop_Bits */
-
-  uint32_t Parity;                   /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref SMARTCARD_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits).*/
-
-  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref SMARTCARD_Mode */
-
-  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Polarity */
-
-  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref SMARTCARD_Clock_Phase */
-
-  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref SMARTCARD_Last_Bit */
-
-  uint32_t  Prescaler;                 /*!< Specifies the SmartCard Prescaler 
-                                           This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
-
-  uint32_t  GuardTime;                 /*!< Specifies the SmartCard Guard Time 
-                                            This parameter must be a number between Min_Data = 0 and Max_Data = 255 */
-
-  uint32_t NACKState;                 /*!< Specifies the SmartCard NACK Transmission state
-                                           This parameter can be a value of @ref SMARTCARD_NACK_State */
-}SMARTCARD_InitTypeDef;
-
-/** 
-  * @brief HAL State structures definition
-  */
-typedef enum
-{
-  HAL_SMARTCARD_STATE_RESET             = 0x00,    /*!< Peripheral is not yet Initialized */
-  HAL_SMARTCARD_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_SMARTCARD_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */
-  HAL_SMARTCARD_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */
-  HAL_SMARTCARD_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
-  HAL_SMARTCARD_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */ 
-  HAL_SMARTCARD_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_SMARTCARD_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_SMARTCARD_StateTypeDef;
-
-/** 
-  * @brief  HAL SMARTCARD Error Code structure definition
-  */
-typedef enum
-{
-  HAL_SMARTCARD_ERROR_NONE      = 0x00,    /*!< No error            */
-  HAL_SMARTCARD_ERROR_PE        = 0x01,    /*!< Parity error        */
-  HAL_SMARTCARD_ERROR_NE        = 0x02,    /*!< Noise error         */
-  HAL_SMARTCARD_ERROR_FE        = 0x04,    /*!< frame error         */
-  HAL_SMARTCARD_ERROR_ORE       = 0x08,    /*!< Overrun error       */
-  HAL_SMARTCARD_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
-}HAL_SMARTCARD_ErrorTypeDef;
-
-/** 
-  * @brief  SMARTCARD handle Structure definition
-  */
-typedef struct
-{
-  USART_TypeDef                    *Instance;        /* USART registers base address */
-
-  SMARTCARD_InitTypeDef            Init;             /* SmartCard communication parameters */
-
-  uint8_t                          *pTxBuffPtr;      /* Pointer to SmartCard Tx transfer Buffer */
-
-  uint16_t                         TxXferSize;       /* SmartCard Tx Transfer size */
-
-  uint16_t                         TxXferCount;      /* SmartCard Tx Transfer Counter */
-
-  uint8_t                          *pRxBuffPtr;      /* Pointer to SmartCard Rx transfer Buffer */
-
-  uint16_t                         RxXferSize;       /* SmartCard Rx Transfer size */
-
-  uint16_t                         RxXferCount;      /* SmartCard Rx Transfer Counter */
-
-  DMA_HandleTypeDef                *hdmatx;          /* SmartCard Tx DMA Handle parameters */
-
-  DMA_HandleTypeDef                *hdmarx;          /* SmartCard Rx DMA Handle parameters */
-
-  HAL_LockTypeDef                  Lock;            /* Locking object */
-
-  __IO HAL_SMARTCARD_StateTypeDef  State;           /* SmartCard communication state */
-
-  __IO HAL_SMARTCARD_ErrorTypeDef  ErrorCode;       /* SmartCard Error code */
-}SMARTCARD_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Constants  SMARTCARD Exported constants
-  * @{
-  */
-
-/** @defgroup SMARTCARD_Word_Length SMARTCARD Word Length
-  * @{
-  */
-#define SMARTCARD_WORDLENGTH_8B                  ((uint32_t)0x00000000)
-#define SMARTCARD_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-#define IS_SMARTCARD_WORD_LENGTH(LENGTH) ((LENGTH) == SMARTCARD_WORDLENGTH_9B)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Stop_Bits SMARTCARD Number of Stop Bits
-  * @{
-  */
-#define SMARTCARD_STOPBITS_1                     ((uint32_t)0x00000000)
-#define SMARTCARD_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
-#define SMARTCARD_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-#define SMARTCARD_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-#define IS_SMARTCARD_STOPBITS(STOPBITS) (((STOPBITS) == SMARTCARD_STOPBITS_0_5) || \
-                                         ((STOPBITS) == SMARTCARD_STOPBITS_1_5))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Parity SMARTCARD Parity
-  * @{
-  */
-#define SMARTCARD_PARITY_NONE                    ((uint32_t)0x00000000)
-#define SMARTCARD_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define SMARTCARD_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-#define IS_SMARTCARD_PARITY(PARITY) (((PARITY) == SMARTCARD_PARITY_EVEN) || \
-                                     ((PARITY) == SMARTCARD_PARITY_ODD))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Mode SMARTCARD Mode
-  * @{
-  */
-#define SMARTCARD_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define SMARTCARD_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define SMARTCARD_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_SMARTCARD_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Clock_Polarity  SMARTCARD Clock Polarity
-  * @{
-  */
-#define SMARTCARD_POLARITY_LOW                   ((uint32_t)0x00000000)
-#define SMARTCARD_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
-#define IS_SMARTCARD_POLARITY(CPOL) (((CPOL) == SMARTCARD_POLARITY_LOW) || ((CPOL) == SMARTCARD_POLARITY_HIGH))
-/**
-  * @}
-  */ 
-
-/** @defgroup SMARTCARD_Clock_Phase SMARTCARD Clock Phase
-  * @{
-  */
-#define SMARTCARD_PHASE_1EDGE                    ((uint32_t)0x00000000)
-#define SMARTCARD_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
-#define IS_SMARTCARD_PHASE(CPHA) (((CPHA) == SMARTCARD_PHASE_1EDGE) || ((CPHA) == SMARTCARD_PHASE_2EDGE))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Last_Bit  SMARTCARD Last Bit
-  * @{
-  */
-#define SMARTCARD_LASTBIT_DISABLE                ((uint32_t)0x00000000)
-#define SMARTCARD_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
-#define IS_SMARTCARD_LASTBIT(LASTBIT) (((LASTBIT) == SMARTCARD_LASTBIT_DISABLE) || \
-                                       ((LASTBIT) == SMARTCARD_LASTBIT_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_NACK_State   SMARTCARD NACK State
-  * @{
-  */
-#define SMARTCARD_NACK_ENABLED                  ((uint32_t)USART_CR3_NACK)
-#define SMARTCARD_NACK_DISABLED                 ((uint32_t)0x00000000)
-#define IS_SMARTCARD_NACK_STATE(NACK) (((NACK) == SMARTCARD_NACK_ENABLED) || \
-                                       ((NACK) == SMARTCARD_NACK_DISABLED))
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_DMA_Requests SMARTCARD DMA requests
-  * @{
-  */
-
-#define SMARTCARD_DMAREQ_TX                    ((uint32_t)USART_CR3_DMAT)
-#define SMARTCARD_DMAREQ_RX                    ((uint32_t)USART_CR3_DMAR)
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Flags    SMARTCARD Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-
-#define SMARTCARD_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define SMARTCARD_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define SMARTCARD_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define SMARTCARD_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define SMARTCARD_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define SMARTCARD_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define SMARTCARD_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define SMARTCARD_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Interrupt_definition     SMARTCARD Interrupts Definition
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the XX register
-  *           - Y  : Interrupt source register (4 bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR3 register
-
-  *
-  * @{
-  */
-#define SMARTCARD_IT_PE                          ((uint32_t)0x10000100)
-#define SMARTCARD_IT_TXE                         ((uint32_t)0x10000080)
-#define SMARTCARD_IT_TC                          ((uint32_t)0x10000040)
-#define SMARTCARD_IT_RXNE                        ((uint32_t)0x10000020)
-#define SMARTCARD_IT_IDLE                        ((uint32_t)0x10000010)
-#define SMARTCARD_IT_ERR                         ((uint32_t)0x20000001)
-
-/**
-  * @}
-  */
-
-/** @defgroup SMARTCARD_Interruption_Mask    SMARTCARD interruptions flag mask
-  * @{
-  */ 
-#define SMARTCARD_IT_MASK  ((uint32_t)0x0000FFFF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SMARTCARD_Exported_Macros SMARTCARD Exported Macros
-  * @{
-  */
-
-
-/** @brief Reset SMARTCARD handle state
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
-
-/** @brief  Flushs the Smartcard DR register 
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  */
-#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-    
-/** @brief  Checks whether the specified Smartcard flag is set or not.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg SMARTCARD_FLAG_TXE:  Transmit data register empty flag
-  *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag
-  *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag
-  *            @arg SMARTCARD_FLAG_IDLE: Idle Line detection flag
-  *            @arg SMARTCARD_FLAG_ORE:  OverRun Error flag
-  *            @arg SMARTCARD_FLAG_NE:   Noise Error flag
-  *            @arg SMARTCARD_FLAG_FE:   Framing Error flag
-  *            @arg SMARTCARD_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clears the specified Smartcard pending flags.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg SMARTCARD_FLAG_TC:   Transmission Complete flag.
-  *            @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error) and ORE (OverRun 
-  *          error) flags are cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a read operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the SMARTCARD PE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
-                                               (__HANDLE__)->Instance->DR;}while(0)
-/** @brief  Clear the SMARTCARD FE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD NE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD ORE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the SMARTCARD IDLE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @retval None
-  */
-#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enables the specified SmartCard interrupt.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
-  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  */
-#define __HAL_SMARTCARD_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
-                                                               ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief  Disables the specified SmartCard interrupts.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @param  __INTERRUPT__: specifies the SMARTCARD interrupt to disable.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:   Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_PE:   Parity Error interrupt
-  *            @arg SMARTCARD_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  */
-#define __HAL_SMARTCARD_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & SMARTCARD_IT_MASK)): \
-                                                               ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
-
-/** @brief  Checks whether the specified SmartCard interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @param  __IT__: specifies the SMARTCARD interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg SMARTCARD_IT_TC:  Transmission complete interrupt
-  *            @arg SMARTCARD_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg SMARTCARD_IT_IDLE: Idle line detection interrupt
-  *            @arg SMARTCARD_IT_ERR: Error interrupt
-  *            @arg SMARTCARD_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
-
-/** @brief  Enable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @retval None
-  */ 
-#define __HAL_SMARTCARD_ENABLE(__HANDLE__)               (SET_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-/** @brief  Disable the USART associated to the SMARTCARD Handle
-  * @param  __HANDLE__: specifies the SMARTCARD Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3.
-  * @retval None
-  */ 
-#define __HAL_SMARTCARD_DISABLE(__HANDLE__)              (CLEAR_BIT((__HANDLE__)->Instance->CR1, USART_CR1_UE))
-
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup SMARTCARD_Private_Macros   SMARTCARD Private Macros
-  * @{
-  */
-
-/** @brief  Macros to enable or disable the SmartCard DMA request.
-  * @param  __HANDLE__: specifies the SmartCard Handle.
-  * @param  __REQUEST__: specifies the SmartCard DMA request.
-  *          This parameter can be one of the following values:
-  *            @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
-  *            @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
-  */
-#define SMARTCARD_DMA_REQUEST_ENABLE(__HANDLE__, __REQUEST__)    (SET_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__)))
-#define SMARTCARD_DMA_REQUEST_DISABLE(__HANDLE__, __REQUEST__)   (CLEAR_BIT((__HANDLE__)->Instance->CR3, (__REQUEST__)))
-
-#define SMARTCARD_DIV(__PCLK__, __BAUD__)                (((__PCLK__)*25)/(4*(__BAUD__)))
-#define SMARTCARD_DIVMANT(__PCLK__, __BAUD__)            (SMARTCARD_DIV((__PCLK__), (__BAUD__))/100)
-#define SMARTCARD_DIVFRAQ(__PCLK__, __BAUD__)            (((SMARTCARD_DIV((__PCLK__), (__BAUD__)) - (SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-#define SMARTCARD_BRR(__PCLK__, __BAUD__)                ((SMARTCARD_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(SMARTCARD_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
-
-/** @brief  Check the Baud rate range. The maximum Baud Rate is derived from the 
-  *         maximum clock on L1 (i.e. 32 MHz) divided by the oversampling used 
-  *         on the SMARTCARD (i.e. 16). No overSampling by 16 on Smartcard.
-  * @param  __BAUDRATE__: Baud rate set by the configuration function.
-  * @retval Test result (TRUE or FALSE) 
-  */ 
-#define IS_SMARTCARD_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 2000001)
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SMARTCARD_Exported_Functions SMARTCARD Exported Functions
-  * @{
-  */
-  
-/** @addtogroup SMARTCARD_Exported_Functions_Group1 SmartCard Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Init(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_ReInit(SMARTCARD_HandleTypeDef *hsc);
-HAL_StatusTypeDef HAL_SMARTCARD_DeInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspInit(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_MspDeInit(SMARTCARD_HandleTypeDef *hsc);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group2 IO operation functions 
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SMARTCARD_Receive_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size);
-void HAL_SMARTCARD_IRQHandler(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_TxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_RxCpltCallback(SMARTCARD_HandleTypeDef *hsc);
-void HAL_SMARTCARD_ErrorCallback(SMARTCARD_HandleTypeDef *hsc);
-
-/**
-  * @}
-  */
-
-/** @addtogroup SMARTCARD_Exported_Functions_Group3 Peripheral State and Errors functions 
-  * @{
-  */
-
-/* Peripheral State and Errors functions functions  *****************************/
-HAL_SMARTCARD_StateTypeDef HAL_SMARTCARD_GetState(SMARTCARD_HandleTypeDef *hsc);
-uint32_t                   HAL_SMARTCARD_GetError(SMARTCARD_HandleTypeDef *hsc);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_SMARTCARD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,2256 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_spi.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   SPI HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Serial Peripheral Interface (SPI) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      The SPI HAL driver can be used as follows:
-
-      (#) Declare a SPI_HandleTypeDef handle structure, for example:
-          SPI_HandleTypeDef  hspi; 
-
-      (#)Initialize the SPI low level resources by implementing the HAL_SPI_MspInit ()API:
-          (##) Enable the SPIx interface clock 
-          (##) SPI pins configuration
-              (+++) Enable the clock for the SPI GPIOs 
-              (+++) Configure these SPI pins as alternate function push-pull
-          (##) NVIC configuration if you need to use interrupt process
-              (+++) Configure the SPIx interrupt priority
-              (+++) Enable the NVIC SPI IRQ handle
-          (##) DMA Configuration if you need to use DMA process
-              (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive Channel
-              (+++) Enable the DMAx clock
-              (+++) Configure the DMA handle parameters 
-              (+++) Configure the DMA Tx or Rx Channel
-              (+++) Associate the initilalized hdma_tx(or _rx) handle to the hspi DMA Tx (or Rx) handle
-              (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx or Rx Channel
-
-      (#) Program the Mode, Direction , Data size, Baudrate Prescaler, NSS 
-          management, Clock polarity and phase, FirstBit and CRC configuration in the hspi Init structure.
-
-      (#) Initialize the SPI registers by calling the HAL_SPI_Init() API:
-          (++) This API configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-              by calling the customed HAL_SPI_MspInit() API.
-     [..]
-       Circular mode restriction:
-      (#) The DMA circular mode cannot be used when the SPI is configured in these modes:
-          (##) Master 2Lines RxOnly
-          (##) Master 1Line Rx
-      (#) The CRC feature is not managed when the DMA circular mode is enabled
-      (#) When the SPI DMA Pause/Stop features are used, we must use the following APIs 
-          the HAL_SPI_DMAPause()/ HAL_SPI_DMAStop() only under the SPI callbacks
-
-
-            
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SPI SPI
-  * @brief SPI HAL module driver
-  * @{
-  */
-
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Constants SPI Private Constants
-  * @{
-  */
-#define SPI_TIMEOUT_VALUE  10
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup SPI_Private_Functions SPI Private Functions
-  * @{
-  */
-
-static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi);
-static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi);
-static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi);
-static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi);
-static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma);
-static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma);
-static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma);
-static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma);
-static void SPI_DMAError(struct __DMA_HandleTypeDef *hdma);
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Functions SPI Exported Functions
-  * @{
-  */
-
-/** @defgroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim
- ===============================================================================
-              ##### Initialization and de-initialization functions #####
- ===============================================================================
-    [..]  This subsection provides a set of functions allowing to initialize and 
-          de-initialiaze the SPIx peripheral:
-
-      (+) User must implement HAL_SPI_MspInit() function in which he configures 
-          all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
-
-      (+) Call the function HAL_SPI_Init() to configure the selected device with 
-          the selected configuration:
-        (++) Mode
-        (++) Direction 
-        (++) Data Size
-        (++) Clock Polarity and Phase
-        (++) NSS Management
-        (++) BaudRate Prescaler
-        (++) FirstBit
-        (++) TIMode
-        (++) CRC Calculation
-        (++) CRC Polynomial if CRC enabled
-
-      (+) Call the function HAL_SPI_DeInit() to restore the default configuration 
-          of the selected SPIx periperal.       
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SPI according to the specified parameters 
-  *         in the SPI_InitTypeDef and create the associated handle.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval HAL status
-  */
-__weak HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
-  return HAL_ERROR;
-}
-
-/**
-  * @brief  DeInitializes the SPI peripheral 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if(hspi == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Disable the SPI Peripheral Clock */
-  __HAL_SPI_DISABLE(hspi);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
-  HAL_SPI_MspDeInit(hspi);
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State = HAL_SPI_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(hspi);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief SPI MSP Init
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
- __weak void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi)
- {
-   /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_MspInit could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief SPI MSP DeInit
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
- __weak void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_MspDeInit could be implenetd in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group2 IO operation functions
- *  @brief   Data transfers functions
- *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
- ===============================================================================
-    This subsection provides a set of functions allowing to manage the SPI
-    data transfers.
-
-    [..] The SPI supports master and slave mode :
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode.
-            The HAL status of all data processing is returned by the same function
-            after finishing transfer.
-       (++) No-Blocking mode: The communication is performed using Interrupts
-           or DMA, These APIs return the HAL status.
-           The end of the data processing will be indicated through the 
-           dedicated SPI IRQ when using Interrupt mode or the DMA IRQ when 
-           using DMA mode.
-           The HAL_SPI_TxCpltCallback(), HAL_SPI_RxCpltCallback() and HAL_SPI_TxRxCpltCallback() user callbacks 
-           will be executed respectivelly at the end of the transmit or Receive process
-           The HAL_SPI_ErrorCallback()user callback will be executed when a communication error is detected
-
-    (#) Blocking mode APIs are :
-        (++) HAL_SPI_Transmit()in 1Line (simplex) and 2Lines (full duplex) mode
-        (++) HAL_SPI_Receive() in 1Line (simplex) and 2Lines (full duplex) mode
-        (++) HAL_SPI_TransmitReceive() in full duplex mode
-
-    (#) Non Blocking mode API's with Interrupt are :
-        (++) HAL_SPI_Transmit_IT()in 1Line (simplex) and 2Lines (full duplex) mode
-        (++) HAL_SPI_Receive_IT() in 1Line (simplex) and 2Lines (full duplex) mode
-        (++) HAL_SPI_TransmitReceive_IT()in full duplex mode
-        (++) HAL_SPI_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) HAL_SPI_Transmit_DMA()in 1Line (simplex) and 2Lines (full duplex) mode
-        (++) HAL_SPI_Receive_DMA() in 1Line (simplex) and 2Lines (full duplex) mode
-        (++) HAL_SPI_TransmitReceive_DMA() in full duplex mode
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_SPI_TxCpltCallback()
-        (++) HAL_SPI_RxCpltCallback()
-        (++) HAL_SPI_TxRxCpltCallback()
-        (++) HAL_SPI_TxHalfCpltCallback()
-        (++) HAL_SPI_RxHalfCpltCallback()
-        (++) HAL_SPI_TxRxHalfCpltCallback()
-        (++) HAL_SPI_ErrorCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmit an amount of data in blocking mode
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == HAL_NULL ) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
-
-    /* Configure communication */
-    hspi->State = HAL_SPI_STATE_BUSY_TX;
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-
-    hspi->pTxBuffPtr  = pData;
-    hspi->TxXferSize  = Size;
-    hspi->TxXferCount = Size;
-
-    /*Init field not used in handle to zero */
-    hspi->TxISR = 0;
-    hspi->RxISR = 0;
-    hspi->pRxBuffPtr  = HAL_NULL;
-    hspi->RxXferSize  = 0;
-    hspi->RxXferCount = 0;
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-      /* Configure communication direction : 1Line */
-      SPI_1LINE_TX(hspi);
-    }
-
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    /* Transmit data in 8 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-    {
-      if((hspi->Init.Mode == SPI_MODE_SLAVE)|| (hspi->TxXferCount == 0x01))
-      {
-        hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-        hspi->TxXferCount--;
-      }
-      while(hspi->TxXferCount > 0)
-      {
-        /* Wait until TXE flag is set to send data */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-        hspi->TxXferCount--;
-      }
-      /* Enable CRC Transmission */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) 
-      {
-        SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      }
-    }
-    /* Transmit data in 16 Bit mode */
-    else
-    {
-      if((hspi->Init.Mode == SPI_MODE_SLAVE) || (hspi->TxXferCount == 0x01))
-      {
-        hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr+=2;
-        hspi->TxXferCount--;
-      }
-      while(hspi->TxXferCount > 0)
-      {
-        /* Wait until TXE flag is set to send data */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr+=2;
-        hspi->TxXferCount--;
-      }
-      /* Enable CRC Transmission */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) 
-      {
-        SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      }
-    }
-
-    /* Wait until TXE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      return HAL_TIMEOUT;
-    }
-
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
-    { 
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      return HAL_TIMEOUT;
-    }
- 
-    /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
-    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-
-    hspi->State = HAL_SPI_STATE_READY; 
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in blocking mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  __IO uint16_t tmpreg = 0;
-
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == HAL_NULL ) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
-
-    /* Configure communication */
-    hspi->State       = HAL_SPI_STATE_BUSY_RX;
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-
-    hspi->pRxBuffPtr  = pData;
-    hspi->RxXferSize  = Size;
-    hspi->RxXferCount = Size;
-
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->TxISR = 0;
-    hspi->pTxBuffPtr  = HAL_NULL;
-    hspi->TxXferSize  = 0;
-    hspi->TxXferCount = 0;
-
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-      SPI_1LINE_RX(hspi);
-    }
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-    
-    if((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES))
-    {
-      /* Process Unlocked */
-      __HAL_UNLOCK(hspi);
-
-      /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-      return HAL_SPI_TransmitReceive(hspi, pData, pData, Size, Timeout);
-    }
-
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    /* Receive data in 8 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-    {
-      while(hspi->RxXferCount > 1)
-      {
-        /* Wait until RXNE flag is set */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-
-        (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-        hspi->RxXferCount--;
-      }
-      /* Enable CRC Transmission */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) 
-      {
-        SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      }
-    }
-    /* Receive data in 16 Bit mode */
-    else
-    {
-      while(hspi->RxXferCount > 1)
-      {
-        /* Wait until RXNE flag is set to read data */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-
-        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->pRxBuffPtr+=2;
-        hspi->RxXferCount--;
-      }
-      /* Enable CRC Transmission */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) 
-      {
-        SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-      }
-    }
-
-    /* Wait until RXNE flag is set */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-    { 
-      return HAL_TIMEOUT;
-    }
-
-    /* Receive last data in 8 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-    {
-      (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-    }
-    /* Receive last data in 16 Bit mode */
-    else
-    {
-      *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-      hspi->pRxBuffPtr+=2;
-    }
-    hspi->RxXferCount--;
-
-    /* Wait until RXNE flag is set: CRC Received */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-        return HAL_TIMEOUT;
-      }
-
-      /* Read CRC to Flush RXNE flag */
-      tmpreg = hspi->Instance->DR;
-    }
-    
-    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-    {
-      /* Disable SPI peripheral */
-      __HAL_SPI_DISABLE(hspi);
-    }
-
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* Check if CRC error occurred */
-    if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
-    {  
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
-      /* Reset CRC Calculation */
-      SPI_RESET_CRC(hspi);
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hspi);
-
-      return HAL_ERROR; 
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in blocking mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer to be
-  * @param  Size: amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-  __IO uint16_t tmpreg = 0;
-
-  if((hspi->State == HAL_SPI_STATE_READY) || (hspi->State == HAL_SPI_STATE_BUSY_RX))
-  {
-    if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
- 
-    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-    if(hspi->State == HAL_SPI_STATE_READY)
-    {
-      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-    }
-
-     /* Configure communication */   
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-
-    hspi->pRxBuffPtr  = pRxData;
-    hspi->RxXferSize  = Size;
-    hspi->RxXferCount = Size;  
-    
-    hspi->pTxBuffPtr  = pTxData;
-    hspi->TxXferSize  = Size; 
-    hspi->TxXferCount = Size;
-
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->TxISR = 0;
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    /* Transmit and Receive data in 16 Bit mode */
-    if(hspi->Init.DataSize == SPI_DATASIZE_16BIT)
-    {
-      if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
-      {
-        hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-        hspi->pTxBuffPtr+=2;
-        hspi->TxXferCount--;
-      }
-      if(hspi->TxXferCount == 0)
-      {
-        /* Enable CRC Transmission */
-        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-        {
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-
-        /* Wait until RXNE flag is set */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-
-        *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->pRxBuffPtr+=2;
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        while(hspi->TxXferCount > 0)
-        {
-          /* Wait until TXE flag is set to send data */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-          { 
-            return HAL_TIMEOUT;
-          }
-
-          hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-          hspi->pTxBuffPtr+=2;
-          hspi->TxXferCount--;
-
-          /* Enable CRC Transmission */
-          if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
-          {
-            SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-          }
-
-          /* Wait until RXNE flag is set */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          { 
-            return HAL_TIMEOUT;
-          }
-
-          *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-          hspi->pRxBuffPtr+=2;
-          hspi->RxXferCount--;
-        }
-        /* Receive the last byte */
-        if(hspi->Init.Mode == SPI_MODE_SLAVE)
-        {
-          /* Wait until RXNE flag is set */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-          
-          *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-          hspi->pRxBuffPtr+=2;
-          hspi->RxXferCount--;
-        }
-      }
-    }
-    /* Transmit and Receive data in 8 Bit mode */
-    else
-    {
-      if((hspi->Init.Mode == SPI_MODE_SLAVE) || ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->TxXferCount == 0x01)))
-      {
-        hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-        hspi->TxXferCount--;
-      }
-      if(hspi->TxXferCount == 0)
-      {
-        /* Enable CRC Transmission */
-        if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-        {
-          SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-        }
-
-        /* Wait until RXNE flag is set */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-
-        (*hspi->pRxBuffPtr) = hspi->Instance->DR;
-        hspi->RxXferCount--;
-      }
-      else
-      {
-        while(hspi->TxXferCount > 0)
-        {
-          /* Wait until TXE flag is set to send data */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-          hspi->TxXferCount--;
-
-          /* Enable CRC Transmission */
-          if((hspi->TxXferCount == 0) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
-          {
-            SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-          }
-
-          /* Wait until RXNE flag is set */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-
-          (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-          hspi->RxXferCount--;
-        }
-        if(hspi->Init.Mode == SPI_MODE_SLAVE)
-        {
-          /* Wait until RXNE flag is set */
-          if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-          {
-            return HAL_TIMEOUT;
-          }
-          
-          (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-          hspi->RxXferCount--;
-        }
-      }
-    }
-
-    /* Read CRC from DR to close CRC calculation process */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      /* Wait until RXNE flag is set */
-      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-        return HAL_TIMEOUT;
-      }
-      /* Read CRC */
-      tmpreg = hspi->Instance->DR;
-    }
-
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, Timeout) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      return HAL_TIMEOUT;
-    }
-    
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* Check if CRC error occurred */
-    if((hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET))
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
-      /* Reset CRC Calculation */
-      if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-      {
-        SPI_RESET_CRC(hspi);
-      }
-
-      /* Process Unlocked */
-      __HAL_UNLOCK(hspi);
-      
-      return HAL_ERROR; 
-    }
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit an amount of data in no-blocking mode with Interrupt
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
-
-    /* Configure communication */
-    hspi->State        = HAL_SPI_STATE_BUSY_TX;
-    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
-
-    hspi->TxISR = &SPI_TxISR;
-    hspi->pTxBuffPtr   = pData;
-    hspi->TxXferSize   = Size;
-    hspi->TxXferCount  = Size;
-
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->pRxBuffPtr   = HAL_NULL;
-    hspi->RxXferSize   = 0;
-    hspi->RxXferCount  = 0;
-
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-      SPI_1LINE_TX(hspi);
-    }
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-
-    if (hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE));
-    }else
-    {
-      /* Enable TXE and ERR interrupt */
-      __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_ERR));
-    }
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in no-blocking mode with Interrupt
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
-
-    /* Configure communication */
-    hspi->State        = HAL_SPI_STATE_BUSY_RX;
-    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
-
-    hspi->RxISR = &SPI_RxISR;
-    hspi->pRxBuffPtr   = pData;
-    hspi->RxXferSize   = Size;
-    hspi->RxXferCount  = Size ; 
-
-   /*Init field not used in handle to zero */
-    hspi->TxISR = 0;
-    hspi->pTxBuffPtr   = HAL_NULL;
-    hspi->TxXferSize   = 0;
-    hspi->TxXferCount  = 0;
-
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-       SPI_1LINE_RX(hspi);
-    }
-    else if((hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->Init.Mode == SPI_MODE_MASTER))
-    {
-       /* Process Unlocked */
-       __HAL_UNLOCK(hspi);
-
-       /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-       return HAL_SPI_TransmitReceive_IT(hspi, pData, pData, Size);
-    }
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-
-    /* Enable TXE and ERR interrupt */
-    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_RXNE | SPI_IT_ERR));
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    /* Note : The SPI must be enabled after unlocking current process 
-              to avoid the risk of SPI interrupt handle execution before current
-              process unlock */
-
-        /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in no-blocking mode with Interrupt 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer to be
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-
-  if((hspi->State == HAL_SPI_STATE_READY) || \
-     ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
-  {
-    if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-
-    /* Process locked */
-    __HAL_LOCK(hspi);
-
-    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-    if(hspi->State != HAL_SPI_STATE_BUSY_RX)
-    {
-      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-    }
-
-    /* Configure communication */
-    hspi->ErrorCode    = HAL_SPI_ERROR_NONE;
-
-    hspi->TxISR = &SPI_TxISR;
-    hspi->pTxBuffPtr   = pTxData;
-    hspi->TxXferSize   = Size;
-    hspi->TxXferCount  = Size;
-
-    hspi->RxISR = &SPI_2LinesRxISR;
-    hspi->pRxBuffPtr   = pRxData;
-    hspi->RxXferSize   = Size;
-    hspi->RxXferCount  = Size;
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-
-    /* Enable TXE, RXNE and ERR interrupt */
-    __HAL_SPI_ENABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Transmit an amount of data in no-blocking mode with DMA
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES_OR_1LINE(hspi->Init.Direction));
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
-
-    /* Configure communication */
-    hspi->State       = HAL_SPI_STATE_BUSY_TX;
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-
-    hspi->pTxBuffPtr  = pData;
-    hspi->TxXferSize  = Size;
-    hspi->TxXferCount = Size;
-
-    /*Init field not used in handle to zero */
-    hspi->TxISR = 0;
-    hspi->RxISR = 0;
-    hspi->pRxBuffPtr  = HAL_NULL;
-    hspi->RxXferSize  = 0;
-    hspi->RxXferCount = 0;
-
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-      SPI_1LINE_TX(hspi);
-    }
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-
-    /* Set the SPI TxDMA Half transfer complete callback */
-    hspi->hdmatx->XferHalfCpltCallback = SPI_DMAHalfTransmitCplt;
-    
-    /* Set the SPI TxDMA transfer complete callback */
-    hspi->hdmatx->XferCpltCallback = SPI_DMATransmitCplt;
-
-    /* Set the DMA error callback */
-    hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-
-    /* Enable the Tx DMA Channel */
-    HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
-    /* Enable Tx DMA Request */
-    SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receive an amount of data in no-blocking mode with DMA 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pData: pointer to data buffer
-  * @note  When the CRC feature is enabled the pData Length must be Size + 1. 
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
-{
-  if(hspi->State == HAL_SPI_STATE_READY)
-  {
-    if((pData == HAL_NULL) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(hspi);
-
-    /* Configure communication */
-    hspi->State       = HAL_SPI_STATE_BUSY_RX;
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-
-    hspi->pRxBuffPtr  = pData;
-    hspi->RxXferSize  = Size;
-    hspi->RxXferCount = Size;
-
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->TxISR = 0;
-    hspi->pTxBuffPtr  = HAL_NULL;
-    hspi->TxXferSize  = 0;
-    hspi->TxXferCount = 0;
-
-    /* Configure communication direction : 1Line */
-    if(hspi->Init.Direction == SPI_DIRECTION_1LINE)
-    {
-       SPI_1LINE_RX(hspi);
-    }
-    else if((hspi->Init.Direction == SPI_DIRECTION_2LINES)&&(hspi->Init.Mode == SPI_MODE_MASTER))
-    {
-       /* Process Unlocked */
-       __HAL_UNLOCK(hspi);
-
-       /* Call transmit-receive function to send Dummy data on Tx line and generate clock on CLK line */
-       return HAL_SPI_TransmitReceive_DMA(hspi, pData, pData, Size);
-    }
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-
-    /* Set the SPI RxDMA Half transfer complete callback */
-    hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-    
-    /* Set the SPI Rx DMA transfer complete callback */
-    hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-
-    /* Set the DMA error callback */
-    hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-    /* Enable the Rx DMA Channel */
-    HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
-    /* Enable Rx DMA Request */  
-    SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Transmit and Receive an amount of data in no-blocking mode with DMA 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  pTxData: pointer to transmission data buffer
-  * @param  pRxData: pointer to reception data buffer
-  * @note  When the CRC feature is enabled the pRxData Length must be Size + 1 
-  * @param  Size: amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  if((hspi->State == HAL_SPI_STATE_READY) || \
-     ((hspi->Init.Mode == SPI_MODE_MASTER) && (hspi->Init.Direction == SPI_DIRECTION_2LINES) && (hspi->State == HAL_SPI_STATE_BUSY_RX)))
-  {
-    if((pTxData == HAL_NULL ) || (pRxData == HAL_NULL ) || (Size == 0))
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Check the parameters */
-    assert_param(IS_SPI_DIRECTION_2LINES(hspi->Init.Direction));
-    
-    /* Process locked */
-    __HAL_LOCK(hspi);
-
-    /* Don't overwrite in case of HAL_SPI_STATE_BUSY_RX */
-    if(hspi->State != HAL_SPI_STATE_BUSY_RX)
-    {
-      hspi->State = HAL_SPI_STATE_BUSY_TX_RX;
-    }
-
-    /* Configure communication */
-    hspi->ErrorCode   = HAL_SPI_ERROR_NONE;
-
-    hspi->pTxBuffPtr  = (uint8_t*)pTxData;
-    hspi->TxXferSize  = Size;
-    hspi->TxXferCount = Size;
-
-    hspi->pRxBuffPtr  = (uint8_t*)pRxData;
-    hspi->RxXferSize  = Size;
-    hspi->RxXferCount = Size;
-
-    /*Init field not used in handle to zero */
-    hspi->RxISR = 0;
-    hspi->TxISR = 0;
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      SPI_RESET_CRC(hspi);
-    }
-
-    /* Check if we are in Rx only or in Rx/Tx Mode and configure the DMA transfer complete callback */
-    if(hspi->State == HAL_SPI_STATE_BUSY_RX)
-    {
-      /* Set the SPI Rx DMA Half transfer complete callback */
-      hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfReceiveCplt;
-      
-      hspi->hdmarx->XferCpltCallback = SPI_DMAReceiveCplt;
-    }
-    else
-    {
-      /* Set the SPI Tx/Rx DMA Half transfer complete callback */
-      hspi->hdmarx->XferHalfCpltCallback = SPI_DMAHalfTransmitReceiveCplt;
-  
-      hspi->hdmarx->XferCpltCallback = SPI_DMATransmitReceiveCplt;
-    }
-
-    /* Set the DMA error callback */
-    hspi->hdmarx->XferErrorCallback = SPI_DMAError;
-
-    /* Enable the Rx DMA Channel */
-    HAL_DMA_Start_IT(hspi->hdmarx, (uint32_t)&hspi->Instance->DR, (uint32_t)hspi->pRxBuffPtr, hspi->RxXferCount);
-
-    /* Enable Rx DMA Request */  
-    SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-    /* Set the SPI Tx DMA transfer complete callback as HAL_NULL because the communication closing
-    is performed in DMA reception complete callback  */
-    if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
-    {
-      /* Set the DMA error callback */
-      hspi->hdmatx->XferErrorCallback = SPI_DMAError;
-    }
-    else
-    {
-      hspi->hdmatx->XferErrorCallback = HAL_NULL;
-    }
-    
-    /* Enable the Tx DMA Channel */
-    HAL_DMA_Start_IT(hspi->hdmatx, (uint32_t)hspi->pTxBuffPtr, (uint32_t)&hspi->Instance->DR, hspi->TxXferCount);
-
-    /* Check if the SPI is already enabled */ 
-    if((hspi->Instance->CR1 &SPI_CR1_SPE) != SPI_CR1_SPE)
-    {
-      /* Enable SPI peripheral */
-      __HAL_SPI_ENABLE(hspi);
-    }
-
-    /* Enable Tx DMA Request */  
-    SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(hspi);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief Pauses the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-  
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief Resumes the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi)
-{
-  /* Process Locked */
-  __HAL_LOCK(hspi);
-  
-  /* Enable the SPI DMA Tx & Rx requests */
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-  SET_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hspi);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the DMA Transfer.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL SPI API under callbacks HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_SPI_TxCpltCallback() or HAL_SPI_RxCpltCallback() or HAL_SPI_TxRxCpltCallback()
-     */
-  
-  /* Abort the SPI DMA tx Channel */
-  if(hspi->hdmatx != HAL_NULL)
-  {
-    HAL_DMA_Abort(hspi->hdmatx);
-  }
-  /* Abort the SPI DMA rx Channel */
-  if(hspi->hdmarx != HAL_NULL)
-  {
-    HAL_DMA_Abort(hspi->hdmarx);
-  }
-  
-  /* Disable the SPI DMA Tx & Rx requests */
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-  CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-  
-  hspi->State = HAL_SPI_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles SPI interrupt request.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval HAL status
-  */
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi)
-{
-  /* SPI in mode Receiver and Overrun not occurred ---------------------------*/
-  if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_RXNE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) == RESET))
-  {
-    hspi->RxISR(hspi);
-    return;
-  }
-
-  /* SPI in mode Tramitter ---------------------------------------------------*/
-  if((__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) != RESET) && (__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_TXE) != RESET))
-  {
-    hspi->TxISR(hspi);
-    return;
-  }
-
-  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_ERR) != RESET)
-  {
-    /* SPI CRC error interrupt occurred ---------------------------------------*/
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-      __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-    }
-    /* SPI Mode Fault error interrupt occurred --------------------------------*/
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_MODF) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_MODF);
-      __HAL_SPI_CLEAR_MODFFLAG(hspi);
-    }
-    
-    /* SPI Overrun error interrupt occurred -----------------------------------*/
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_OVR) != RESET)
-    {
-      if(hspi->State != HAL_SPI_STATE_BUSY_TX)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_OVR);
-        __HAL_SPI_CLEAR_OVRFLAG(hspi);      
-      }
-    }
-
-    /* SPI Frame error interrupt occurred -------------------------------------*/
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_FRE) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FRE);
-      __HAL_SPI_CLEAR_FREFLAG(hspi);
-    }
-
-    /* Call the Error call Back in case of Errors */
-    if(hspi->ErrorCode!=HAL_SPI_ERROR_NONE)
-    {
-      __HAL_SPI_DISABLE_IT(hspi, SPI_IT_RXNE | SPI_IT_TXE | SPI_IT_ERR);
-      hspi->State = HAL_SPI_STATE_READY;
-      HAL_SPI_ErrorCallback(hspi);
-    }
-  }
-}
-
-/**
-  * @brief Tx Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_TxCpltCallback could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief Rx Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_RxCpltCallback() could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief Tx and Rx Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxCpltCallback() could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief Tx Half Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_TxHalfCpltCallback could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief Rx Half Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_RxHalfCpltCallback() could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief Tx and Rx Transfer completed callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
-__weak void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SPI_TxRxHalfCpltCallback() could be implenetd in the user file
-   */
-}
-
-/**
-  * @brief SPI error callbacks
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval None
-  */
- __weak void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi)
-{
-  /* NOTE : - This function Should not be modified, when the callback is needed,
-            the HAL_SPI_ErrorCallback() could be implenetd in the user file.
-            - The ErrorCode parameter in the hspi handle is updated by the SPI processes
-            and user can use HAL_SPI_GetError() API to check the latest error occurred.
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   SPI control functions 
-  *
-@verbatim
- ===============================================================================
-                      ##### Peripheral State and Errors functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the SPI.
-     (+) HAL_SPI_GetState() API can be helpful to check in run-time the state of the SPI peripheral
-     (+) HAL_SPI_GetError() check in run-time Errors occurring during communication
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the SPI state
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval HAL state
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi)
-{
-  return hspi->State;
-}
-
-/**
-  * @brief  Return the SPI error code
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval SPI Error Code
-  */
-HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi)
-{
-  return hspi->ErrorCode;
-}
-
-/**
-  * @}
-  */
-  
-/**
-    * @}
-    */
-
-
-
-/** @addtogroup SPI_Private_Functions
-    * @{
-    */
-
-
-  /**
-  * @brief  Interrupt Handler to close Tx transfer 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
-  */
-static void SPI_TxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Wait until TXE flag is set to send data */
-  if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-  {
-    SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-  }
-
-  /* Disable TXE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE ));
-
-  /* Disable ERR interrupt if Receive process is finished */
-  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_RXNE) == RESET)
-  {
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
-
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
-    if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-    {
-      __HAL_SPI_CLEAR_OVRFLAG(hspi);
-    }
-    
-    /* Check if Errors has been detected during transfer */
-    if(hspi->ErrorCode ==  HAL_SPI_ERROR_NONE)
-    {
-      /* Check if we are in Tx or in Rx/Tx Mode */
-      if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
-      {
-        /* Set state to READY before run the Callback Complete */
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxRxCpltCallback(hspi);
-      }
-      else
-      {
-        /* Set state to READY before run the Callback Complete */
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxCpltCallback(hspi);
-      }
-    }
-    else
-    {
-      /* Set state to READY before run the Callback Complete */
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Call Error call back in case of Error */
-      HAL_SPI_ErrorCallback(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Interrupt Handler to transmit amount of data in no-blocking mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
-  */
-static void SPI_TxISR(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Transmit data in 8 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-  {
-    hspi->Instance->DR = (*hspi->pTxBuffPtr++);
-  }
-  /* Transmit data in 16 Bit mode */
-  else
-  {
-    hspi->Instance->DR = *((uint16_t*)hspi->pTxBuffPtr);
-    hspi->pTxBuffPtr+=2;
-  }
-  hspi->TxXferCount--;
-
-  if(hspi->TxXferCount == 0)
-  {
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      /* calculate and transfer CRC on Tx line */
-      SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-    }
-    SPI_TxCloseIRQHandler(hspi);
-  }
-}
-
-/**
-  * @brief  Interrupt Handler to close Rx transfer 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
-  */
-static void SPI_RxCloseIRQHandler(struct __SPI_HandleTypeDef *hspi)
-{
-  __IO uint16_t tmpreg = 0;
-
-  if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-  {
-    /* Wait until RXNE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Read CRC to reset RXNE flag */
-    tmpreg = hspi->Instance->DR;
-
-    /* Wait until RXNE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Check if CRC error occurred */
-    if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-
-      /* Reset CRC Calculation */
-      SPI_RESET_CRC(hspi);
-    }
-  }
-
-  /* Disable RXNE interrupt */
-  __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_RXNE));
-
-  /* if Transmit process is finished */
-  if(__HAL_SPI_GET_IT_SOURCE(hspi, SPI_IT_TXE) == RESET)
-  {
-    /* Disable ERR interrupt */
-    __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_ERR));
-
-    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-    {
-      /* Disable SPI peripheral */
-      __HAL_SPI_DISABLE(hspi);
-    }
-    
-    /* Check if Errors has been detected during transfer */
-    if(hspi->ErrorCode ==  HAL_SPI_ERROR_NONE)
-    {
-      /* Check if we are in Rx or in Rx/Tx Mode */
-      if(hspi->State == HAL_SPI_STATE_BUSY_TX_RX)
-      {
-        /* Set state to READY before run the Callback Complete */
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_TxRxCpltCallback(hspi);
-      }
-      else
-      {
-        /* Set state to READY before run the Callback Complete */
-        hspi->State = HAL_SPI_STATE_READY;
-        HAL_SPI_RxCpltCallback(hspi);
-      }
-    }
-    else
-    {
-      /* Set state to READY before run the Callback Complete */
-      hspi->State = HAL_SPI_STATE_READY;
-      /* Call Error call back in case of Error */
-      HAL_SPI_ErrorCallback(hspi);
-    }
-  }
-}
-
-/**
-  * @brief  Interrupt Handler to receive amount of data in 2Lines mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
-  */
-static void SPI_2LinesRxISR(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 8 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-  {
-    (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-  }
-  /* Receive data in 16 Bit mode */
-  else
-  {
-    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-    hspi->pRxBuffPtr+=2;
-  }
-  hspi->RxXferCount--;
-
-  if(hspi->RxXferCount==0)
-  {
-    SPI_RxCloseIRQHandler(hspi);
-  }
-}
-
-/**
-  * @brief  Interrupt Handler to receive amount of data in no-blocking mode 
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval void
-  */
-static void SPI_RxISR(struct __SPI_HandleTypeDef *hspi)
-{
-  /* Receive data in 8 Bit mode */
-  if(hspi->Init.DataSize == SPI_DATASIZE_8BIT)
-  {
-    (*hspi->pRxBuffPtr++) = hspi->Instance->DR;
-  }
-  /* Receive data in 16 Bit mode */
-  else
-  {
-    *((uint16_t*)hspi->pRxBuffPtr) = hspi->Instance->DR;
-    hspi->pRxBuffPtr+=2;
-  }
-    hspi->RxXferCount--;
-
-  /* Enable CRC Transmission */
-  if((hspi->RxXferCount == 1) && (hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED))
-  {
-    /* Set CRC Next to calculate CRC on Rx side */
-    SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
-  }
-
-  if(hspi->RxXferCount == 0)
-  {
-    SPI_RxCloseIRQHandler(hspi);
-  }
-}
-
-/**
-  * @brief DMA SPI transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitCplt(struct __DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* DMA Normal Mode */
-  if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
-  {
-    /* Wait until TXE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    hspi->TxXferCount = 0;
-    hspi->State = HAL_SPI_STATE_READY;
-  }
-
-  /* Clear OVERUN flag in 2 Lines communication mode because received is not read */
-  if(hspi->Init.Direction == SPI_DIRECTION_2LINES)
-  {
-    __HAL_SPI_CLEAR_OVRFLAG(hspi);
-  }
-
-  /* Check if Errors has been detected during transfer */
-  if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-  {
-    HAL_SPI_ErrorCallback(hspi);
-  }
-  else
-  {
-    HAL_SPI_TxCpltCallback(hspi);
-  }
-}
-
-/**
-  * @brief DMA SPI receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAReceiveCplt(struct __DMA_HandleTypeDef *hdma)
-{
-  __IO uint16_t tmpreg = 0;
-
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* DMA Normal mode */
-  if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
-  {
-    if((hspi->Init.Mode == SPI_MODE_MASTER)&&((hspi->Init.Direction == SPI_DIRECTION_1LINE)||(hspi->Init.Direction == SPI_DIRECTION_2LINES_RXONLY)))
-    {
-      /* Disable SPI peripheral */
-      __HAL_SPI_DISABLE(hspi);
-    }
-
-    /* Disable Rx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-    /* Disable Tx DMA Request (done by default to handle the case Master RX direction 2 lines) */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      /* Wait until RXNE flag is set to send data */
-      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      }
-
-      /* Read CRC */
-      tmpreg = hspi->Instance->DR;
-
-      /* Wait until RXNE flag is set */
-      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-      }
-
-      /* Check if CRC error occurred */
-      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-        __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-      }
-    }
-
-    hspi->RxXferCount = 0;
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* Check if Errors has been detected during transfer */
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-    }
-    else
-    {
-      HAL_SPI_RxCpltCallback(hspi);
-    }
-  }
-  else
-  {
-    HAL_SPI_RxCpltCallback(hspi);
-  }
-}
-
-/**
-  * @brief DMA SPI transmit receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMATransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)   
-{
-  __IO uint16_t tmpreg = 0;
-
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  if((hdma->Instance->CCR & DMA_CIRCULAR) == 0)
-  {
-    /* Reset CRC Calculation */
-    if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-    {
-      /* Check if CRC is done on going (RXNE flag set) */
-      if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, SET, SPI_TIMEOUT_VALUE) == HAL_OK)
-      {
-        /* Wait until RXNE flag is set to send data */
-        if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_RXNE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-        {
-          SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-        }
-      }
-      /* Read CRC */
-      tmpreg = hspi->Instance->DR;
-
-      /* Check if CRC error occurred */
-      if(__HAL_SPI_GET_FLAG(hspi, SPI_FLAG_CRCERR) != RESET)
-      {
-        SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_CRC);
-        __HAL_SPI_CLEAR_CRCERRFLAG(hspi);
-      }
-    }
-
-    /* Wait until TXE flag is set to send data */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_TXE, RESET, SPI_TIMEOUT_VALUE) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-  
-    /* Disable Tx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_TXDMAEN);
-
-    /* Wait until Busy flag is reset before disabling SPI */
-    if(SPI_WaitOnFlagUntilTimeout(hspi, SPI_FLAG_BSY, SET, SPI_TIMEOUT_VALUE) != HAL_OK)
-    {
-      SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_FLAG);
-    }
-
-    /* Disable Rx DMA Request */
-    CLEAR_BIT(hspi->Instance->CR2, SPI_CR2_RXDMAEN);
-
-    hspi->TxXferCount = 0;
-    hspi->RxXferCount = 0;
-
-    hspi->State = HAL_SPI_STATE_READY;
-
-    /* Check if Errors has been detected during transfer */
-    if(hspi->ErrorCode != HAL_SPI_ERROR_NONE)
-    {
-      HAL_SPI_ErrorCallback(hspi);
-    }
-    else
-    {
-      HAL_SPI_TxRxCpltCallback(hspi);
-    }
-  }
-  else
-  {
-    HAL_SPI_TxRxCpltCallback(hspi);
-  }
-}
-
-/**
-  * @brief DMA SPI half transmit process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitCplt(struct __DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_TxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI half receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfReceiveCplt(struct __DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_RxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI Half transmit receive process complete callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAHalfTransmitReceiveCplt(struct __DMA_HandleTypeDef *hdma)   
-{
-  SPI_HandleTypeDef* hspi = ( SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  HAL_SPI_TxRxHalfCpltCallback(hspi);
-}
-
-/**
-  * @brief DMA SPI communication error callback 
-  * @param  hdma: pointer to a DMA_HandleTypeDef structure that contains
-  *                the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void SPI_DMAError(DMA_HandleTypeDef *hdma)
-{
-  SPI_HandleTypeDef* hspi = (SPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  hspi->TxXferCount = 0;
-  hspi->RxXferCount = 0;
-  hspi->State= HAL_SPI_STATE_READY;
-  SET_BIT(hspi->ErrorCode, HAL_SPI_ERROR_DMA);
-  HAL_SPI_ErrorCallback(hspi);
-}
-
-/**
-  * @brief  This function handles SPI Communication Timeout.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @param  Flag: SPI flag to check
-  * @param  Status: Flag status to check: RESET or set
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef SPI_WaitOnFlagUntilTimeout(struct __SPI_HandleTypeDef *hspi, uint32_t Flag, FlagStatus Status, uint32_t Timeout)  
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_SPI_GET_FLAG(hspi, Flag) == RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable the SPI and reset the CRC: the CRC value should be cleared
-             on both master and slave sides in order to resynchronize the master
-             and slave for their respective CRC calculation */
-
-          /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-          __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-
-          /* Reset CRC Calculation */
-          if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-          {
-            SPI_RESET_CRC(hspi);
-          }
-
-          hspi->State= HAL_SPI_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_SPI_GET_FLAG(hspi, Flag) != RESET)
-    {
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0) || ((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable the SPI and reset the CRC: the CRC value should be cleared
-             on both master and slave sides in order to resynchronize the master
-             and slave for their respective CRC calculation */
-
-          /* Disable TXE, RXNE and ERR interrupts for the interrupt process */
-          __HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE | SPI_IT_RXNE | SPI_IT_ERR));
-
-          /* Disable SPI peripheral */
-          __HAL_SPI_DISABLE(hspi);
-
-          /* Reset CRC Calculation */
-          if(hspi->Init.CRCCalculation == SPI_CRCCALCULATION_ENABLED)
-          {
-            SPI_RESET_CRC(hspi);
-          }
-
-          hspi->State= HAL_SPI_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(hspi);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,556 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_spi.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_SPI_H
-#define __STM32L1xx_HAL_SPI_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"  
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Types SPI Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  SPI Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t Mode;               /*!< Specifies the SPI operating mode.
-                                    This parameter can be a value of @ref SPI_mode */
-
-  uint32_t Direction;          /*!< Specifies the SPI Directional mode state.
-                                    This parameter can be a value of @ref SPI_Direction_mode */
-
-  uint32_t DataSize;           /*!< Specifies the SPI data size.
-                                    This parameter can be a value of @ref SPI_data_size */
-
-  uint32_t CLKPolarity;        /*!< Specifies the serial clock steady state.
-                                    This parameter can be a value of @ref SPI_Clock_Polarity */
-
-  uint32_t CLKPhase;           /*!< Specifies the clock active edge for the bit capture.
-                                    This parameter can be a value of @ref SPI_Clock_Phase */
-
-  uint32_t NSS;                /*!< Specifies whether the NSS signal is managed by
-                                    hardware (NSS pin) or by software using the SSI bit.
-                                    This parameter can be a value of @ref SPI_Slave_Select_management */
-
-  uint32_t BaudRatePrescaler;  /*!< Specifies the Baud Rate prescaler value which will be
-                                    used to configure the transmit and receive SCK clock.
-                                    This parameter can be a value of @ref SPI_BaudRate_Prescaler
-                                    @note The communication clock is derived from the master
-                                    clock. The slave clock does not need to be set */
-
-  uint32_t FirstBit;           /*!< Specifies whether data transfers start from MSB or LSB bit.
-                                    This parameter can be a value of @ref SPI_MSB_LSB_transmission */
-
-  uint32_t TIMode;             /*!< Specifies if the TI mode is enabled or not.
-                                    This parameter can be a value of @ref SPI_TI_mode */
-
-  uint32_t CRCCalculation;     /*!< Specifies if the CRC calculation is enabled or not.
-                                    This parameter can be a value of @ref SPI_CRC_Calculation */
-
-  uint32_t CRCPolynomial;      /*!< Specifies the polynomial used for the CRC calculation.
-                                    This parameter must be a number between Min_Data = 0 and Max_Data = 65535 */
-
-}SPI_InitTypeDef;
-
-/**
-  * @brief  HAL SPI State structure definition
-  */
-typedef enum
-{
-  HAL_SPI_STATE_RESET      = 0x00,  /*!< SPI not yet initialized or disabled                */
-  HAL_SPI_STATE_READY      = 0x01,  /*!< SPI initialized and ready for use                  */
-  HAL_SPI_STATE_BUSY       = 0x02,  /*!< SPI process is ongoing                             */
-  HAL_SPI_STATE_BUSY_TX    = 0x12,  /*!< Data Transmission process is ongoing               */
-  HAL_SPI_STATE_BUSY_RX    = 0x22,  /*!< Data Reception process is ongoing                  */
-  HAL_SPI_STATE_BUSY_TX_RX = 0x32,  /*!< Data Transmission and Reception process is ongoing */
-  HAL_SPI_STATE_ERROR      = 0x03   /*!< SPI error state                                    */
-    
-}HAL_SPI_StateTypeDef;
-
-/** 
-  * @brief  HAL SPI Error Code structure definition  
-  */ 
-typedef enum
-{
-  HAL_SPI_ERROR_NONE      = 0x00,    /*!< No error             */
-  HAL_SPI_ERROR_MODF      = 0x01,    /*!< MODF error           */
-  HAL_SPI_ERROR_CRC       = 0x02,    /*!< CRC error            */
-  HAL_SPI_ERROR_OVR       = 0x04,    /*!< OVR error            */
-  HAL_SPI_ERROR_FRE       = 0x08,    /*!< FRE error            */
-  HAL_SPI_ERROR_DMA       = 0x10,    /*!< DMA transfer error   */
-  HAL_SPI_ERROR_FLAG      = 0x20     /*!< Flag: RXNE,TXE, BSY  */
-
-}HAL_SPI_ErrorTypeDef;
-
-/** 
-  * @brief  SPI handle Structure definition
-  */
-typedef struct __SPI_HandleTypeDef
-{
-  SPI_TypeDef                *Instance;    /* SPI registers base address */
-
-  SPI_InitTypeDef            Init;         /* SPI communication parameters */
-
-  uint8_t                    *pTxBuffPtr;  /* Pointer to SPI Tx transfer Buffer */
-
-  uint16_t                   TxXferSize;   /* SPI Tx transfer size */
-  
-  uint16_t                   TxXferCount;  /* SPI Tx Transfer Counter */
-
-  uint8_t                    *pRxBuffPtr;  /* Pointer to SPI Rx transfer Buffer */
-
-  uint16_t                   RxXferSize;   /* SPI Rx transfer size */
-
-  uint16_t                   RxXferCount;  /* SPI Rx Transfer Counter */
-
-  DMA_HandleTypeDef          *hdmatx;      /* SPI Tx DMA handle parameters */
-
-  DMA_HandleTypeDef          *hdmarx;      /* SPI Rx DMA handle parameters */
-
-  void                       (*RxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Rx ISR */
-
-  void                       (*TxISR)(struct __SPI_HandleTypeDef * hspi); /* function pointer on Tx ISR */
-
-  HAL_LockTypeDef            Lock;         /* SPI locking object */
-
-  __IO HAL_SPI_StateTypeDef  State;        /* SPI communication state */
-
-  __IO HAL_SPI_ErrorTypeDef  ErrorCode;         /* SPI Error code */
-
-}SPI_HandleTypeDef;
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */
-
-/** @defgroup SPI_mode SPI mode
-  * @{
-  */
-#define SPI_MODE_SLAVE                  ((uint32_t)0x00000000)
-#define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
-
-#define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
-                           ((MODE) == SPI_MODE_MASTER))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Direction_mode SPI Direction mode
-  * @{
-  */
-#define SPI_DIRECTION_2LINES             ((uint32_t)0x00000000)
-#define SPI_DIRECTION_2LINES_RXONLY      SPI_CR1_RXONLY
-#define SPI_DIRECTION_1LINE              SPI_CR1_BIDIMODE
-
-#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_DIRECTION_2LINES)        || \
-                                     ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
-                                     ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES)  || \
-                                                ((MODE) == SPI_DIRECTION_1LINE))
-
-#define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
-
-/**
-  * @}
-  */
-
-/** @defgroup SPI_data_size SPI data size
-  * @{
-  */
-#define SPI_DATASIZE_8BIT               ((uint32_t)0x00000000)
-#define SPI_DATASIZE_16BIT              SPI_CR1_DFF
-
-#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
-                                   ((DATASIZE) == SPI_DATASIZE_8BIT))
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_Clock_Polarity SPI Clock Polarity
-  * @{
-  */
-#define SPI_POLARITY_LOW                ((uint32_t)0x00000000)
-#define SPI_POLARITY_HIGH               SPI_CR1_CPOL
-
-#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
-                           ((CPOL) == SPI_POLARITY_HIGH))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Clock_Phase SPI Clock Phase
-  * @{
-  */
-#define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000)
-#define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
-
-#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
-                           ((CPHA) == SPI_PHASE_2EDGE))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Slave_Select_management SPI Slave Select management
-  * @{
-  */
-#define SPI_NSS_SOFT                    SPI_CR1_SSM
-#define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000)
-#define SPI_NSS_HARD_OUTPUT             ((uint32_t)(SPI_CR2_SSOE << 16))
-
-#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
-                         ((NSS) == SPI_NSS_HARD_INPUT) || \
-                         ((NSS) == SPI_NSS_HARD_OUTPUT))
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
-  * @{
-  */
-#define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000)
-#define SPI_BAUDRATEPRESCALER_4         ((uint32_t)SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_8         ((uint32_t)SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_16        ((uint32_t)SPI_CR1_BR_1 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_32        ((uint32_t)SPI_CR1_BR_2)
-#define SPI_BAUDRATEPRESCALER_64        ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_0)
-#define SPI_BAUDRATEPRESCALER_128       ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1)
-#define SPI_BAUDRATEPRESCALER_256       ((uint32_t)SPI_CR1_BR_2 | SPI_CR1_BR_1 | SPI_CR1_BR_0)
-
-#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
-                                              ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
-/**
-  * @}
-  */ 
-
-/** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB transmission
-  * @{
-  */
-#define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000)
-#define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
-
-#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
-                               ((BIT) == SPI_FIRSTBIT_LSB))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_CRC_Calculation SPI CRC Calculation
-  * @{
-  */
-#define SPI_CRCCALCULATION_DISABLED     ((uint32_t)0x00000000)
-#define SPI_CRCCALCULATION_ENABLED      SPI_CR1_CRCEN
-
-#define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLED) || \
-                                             ((CALCULATION) == SPI_CRCCALCULATION_ENABLED))
-
-#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFF))
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Interrupt_configuration_definition SPI Interrupt configuration definition
-  * @{
-  */
-#define SPI_IT_TXE                      SPI_CR2_TXEIE
-#define SPI_IT_RXNE                     SPI_CR2_RXNEIE
-#define SPI_IT_ERR                      SPI_CR2_ERRIE
-/**
-  * @}
-  */
-
-/** @defgroup SPI_Flag_definition SPI Flag definition
-  * @{
-  */
-#define SPI_FLAG_RXNE                   SPI_SR_RXNE
-#define SPI_FLAG_TXE                    SPI_SR_TXE
-#define SPI_FLAG_CRCERR                 SPI_SR_CRCERR
-#define SPI_FLAG_MODF                   SPI_SR_MODF
-#define SPI_FLAG_OVR                    SPI_SR_OVR
-#define SPI_FLAG_BSY                    SPI_SR_BSY
-#define SPI_FLAG_FRE                    SPI_SR_FRE
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SPI_Exported_Macros SPI Exported Macros
-  * @{
-  */
-
-/** @brief Reset SPI handle state
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
-
-/** @brief  Enable or disable the specified SPI interrupts.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *            @arg SPI_IT_ERR: Error interrupt enable
-  * @retval None
-  */
-#define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   SET_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-#define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  CLEAR_BIT((__HANDLE__)->Instance->CR2, (__INTERRUPT__))
-
-/** @brief  Check if the specified SPI interrupt source is enabled or disabled.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
-  *          This parameter can be one of the following values:
-  *             @arg SPI_IT_TXE: Tx buffer empty interrupt enable
-  *             @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
-  *             @arg SPI_IT_ERR: Error interrupt enable
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief  Check whether the specified SPI flag is set or not.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
-  *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
-  *            @arg SPI_FLAG_CRCERR: CRC error flag
-  *            @arg SPI_FLAG_MODF: Mode fault flag
-  *            @arg SPI_FLAG_OVR: Overrun flag
-  *            @arg SPI_FLAG_BSY: Busy flag
-  *            @arg SPI_FLAG_FRE: Frame format error flag  
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clear the SPI CRCERR pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = ~(SPI_FLAG_CRCERR))
-
-/** @brief  Clear the SPI MODF pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
-                                                CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE);}while(0) 
-
-/** @brief  Clear the SPI OVR pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. 
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__) do{(__HANDLE__)->Instance->DR;\
-                                               (__HANDLE__)->Instance->SR;}while(0) 
-
-/** @brief  Clear the SPI FRE pending flag.
-  * @param  __HANDLE__: specifies the SPI handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR)
-
-/** @brief  Enables the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */                                                 
-#define __HAL_SPI_ENABLE(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-                                                 
-/** @brief  Disables the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */                                           
-#define __HAL_SPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_SPE)
-/**
-  * @}
-  */
-
-
-/* Private macro ------------------------------------------------------------*/
-/** @defgroup SPI_Private_Macros SPI Private Macros
-  * @{
-  */
-
-/** @brief  Sets the SPI transmit-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_1LINE_TX(__HANDLE__)  SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE)
-
-/** @brief  Sets the SPI receive-only mode.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */               
-#define SPI_1LINE_RX(__HANDLE__)  CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_BIDIOE) 
-
-/** @brief  Resets the CRC calculation of the SPI.
-  * @param  __HANDLE__: specifies the SPI Handle.
-  *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
-  * @retval None
-  */
-#define SPI_RESET_CRC(__HANDLE__) do{CLEAR_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);\
-                                             SET_BIT((__HANDLE__)->Instance->CR1, SPI_CR1_CRCEN);}while(0)
-/**
-  * @}
-  */
-
-/* Include SPI HAL Extension module */
-#include "stm32l1xx_hal_spi_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup SPI_Exported_Functions_Group1
-  * @{
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DeInit (SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
-void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup SPI_Exported_Functions_Group2
-  * @{
-  */
-HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
-HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
-
-void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
-/**
-  * @}
-  */
-
-
-/* Peripheral State and Control functions  **************************************/
-/** @addtogroup SPI_Exported_Functions_Group3
-  * @{
-  */
-HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
-HAL_SPI_ErrorTypeDef HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,153 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_spi_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Extended SPI HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities SPI extension peripheral:
-  *           + Extended Peripheral Control functions
-  *  
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */
-#ifdef HAL_SPI_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @addtogroup SPI_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup SPI_Exported_Functions_Group1
- *
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SPI according to the specified parameters 
-  *         in the SPI_InitTypeDef and create the associated handle.
-  * @param  hspi: pointer to a SPI_HandleTypeDef structure that contains
-  *                the configuration information for SPI module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi)
-{
-  /* Check the SPI handle allocation */
-  if(hspi == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_SPI_ALL_INSTANCE(hspi->Instance));
-  assert_param(IS_SPI_MODE(hspi->Init.Mode));
-  assert_param(IS_SPI_DIRECTION_MODE(hspi->Init.Direction));
-  assert_param(IS_SPI_DATASIZE(hspi->Init.DataSize));
-  assert_param(IS_SPI_CPOL(hspi->Init.CLKPolarity));
-  assert_param(IS_SPI_CPHA(hspi->Init.CLKPhase));
-  assert_param(IS_SPI_NSS(hspi->Init.NSS));
-  assert_param(IS_SPI_BAUDRATE_PRESCALER(hspi->Init.BaudRatePrescaler));
-  assert_param(IS_SPI_FIRST_BIT(hspi->Init.FirstBit));
-  assert_param(IS_SPI_TIMODE(hspi->Init.TIMode));
-  assert_param(IS_SPI_CRC_CALCULATION(hspi->Init.CRCCalculation));
-  assert_param(IS_SPI_CRC_POLYNOMIAL(hspi->Init.CRCPolynomial));
-
-  if(hspi->State == HAL_SPI_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC... */
-    HAL_SPI_MspInit(hspi);
-  }
-  
-  hspi->State = HAL_SPI_STATE_BUSY;
-
-  /* Disble the selected SPI peripheral */
-  __HAL_SPI_DISABLE(hspi);
-
-  /*----------------------- SPIx CR1 & CR2 Configuration ---------------------*/
-  /* Configure : SPI Mode, Communication Mode, Data size, Clock polarity and phase, NSS management,
-  Communication speed, First bit and CRC calculation state */
-  hspi->Instance->CR1 = (hspi->Init.Mode | hspi->Init.Direction | hspi->Init.DataSize |
-                         hspi->Init.CLKPolarity | hspi->Init.CLKPhase | (hspi->Init.NSS & SPI_CR1_SSM) |
-                         hspi->Init.BaudRatePrescaler | hspi->Init.FirstBit  | hspi->Init.CRCCalculation);
-
-  /* Configure : NSS management */
-  hspi->Instance->CR2 = (((hspi->Init.NSS >> 16) & SPI_CR2_SSOE) | hspi->Init.TIMode);
-
-  /*---------------------------- SPIx CRCPOLY Configuration ------------------*/
-  /* Configure : CRC Polynomial */
-  hspi->Instance->CRCPR = hspi->Init.CRCPolynomial;
-
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-  /* Activate the SPI mode (Make sure that I2SMOD bit in I2SCFGR register is reset) */
-  CLEAR_BIT(hspi->Instance->I2SCFGR, SPI_I2SCFGR_I2SMOD);
-#endif
-
-  hspi->ErrorCode = HAL_SPI_ERROR_NONE;
-  hspi->State = HAL_SPI_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_SPI_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_spi_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,106 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_spi_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of SPI HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_SPI_EX_H
-#define __STM32L1xx_HAL_SPI_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"  
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SPI
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup SPI_Exported_Constants SPI Exported Constants
-  * @{
-  */ 
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-/** @defgroup SPI_TI_mode SPI TI mode
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             ((uint32_t)0x00000000)
-#define SPI_TIMODE_ENABLED              SPI_CR2_FRF
-
-#define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLED) || \
-                             ((MODE) == SPI_TIMODE_ENABLED))
-#else
-/** @defgroup SPI_TI_mode SPI TI mode disable
-  * @brief  SPI TI Mode not supported for Category 1 and 2 
-  * @{
-  */
-#define SPI_TIMODE_DISABLED             ((uint32_t)0x00000000)
-
-#define IS_SPI_TIMODE(MODE) ((MODE) == SPI_TIMODE_DISABLED)
-
-#endif
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_SPI_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,681 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_sram.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   SRAM HAL module driver.
-  *          This file provides a generic firmware to drive SRAM memories  
-  *          mounted as external device.
-  *         
-  @verbatim
-  ==============================================================================
-                          ##### How to use this driver #####
-  ==============================================================================  
-  [..]
-    This driver is a generic layered driver which contains a set of APIs used to 
-    control SRAM memories. It uses the FSMC layer functions to interface 
-    with SRAM devices.  
-    The following sequence should be followed to configure the FSMC to interface
-    with SRAM/PSRAM memories: 
-      
-   (#) Declare a SRAM_HandleTypeDef handle structure, for example:
-          SRAM_HandleTypeDef  hsram; and: 
-          
-       (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed 
-            values of the structure member.
-            
-       (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined 
-            base register instance for NOR or SRAM device 
-                         
-       (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
-            base register instance for NOR or SRAM extended mode 
-             
-   (#) Declare two FSMC_NORSRAM_TimingTypeDef structures, for both normal and extended 
-       mode timings; for example:
-          FSMC_NORSRAM_TimingTypeDef  Timing and FSMC_NORSRAM_TimingTypeDef  ExTiming;
-      and fill its fields with the allowed values of the structure member.
-      
-   (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
-       performs the following sequence:
-          
-       (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
-       (##) Control register configuration using the FSMC NORSRAM interface function 
-            FSMC_NORSRAM_Init()
-       (##) Timing register configuration using the FSMC NORSRAM interface function 
-            FSMC_NORSRAM_Timing_Init()
-       (##) Extended mode Timing register configuration using the FSMC NORSRAM interface function 
-            FSMC_NORSRAM_Extended_Timing_Init()
-       (##) Enable the SRAM device using the macro __FSMC_NORSRAM_ENABLE()    
-
-   (#) At this stage you can perform read/write accesses from/to the memory connected 
-       to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
-       following APIs:
-       (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
-       (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
-       
-   (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
-       HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation  
-       
-   (#) You can continuously monitor the SRAM device HAL state by calling the function
-       HAL_SRAM_GetState()              
-                             
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SRAM SRAM
-  * @brief SRAM driver modules
-  * @{
-  */
-#ifdef HAL_SRAM_MODULE_ENABLED
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/    
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_Functions SRAM Exported Functions
-  * @{
-  */
-
-/** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @brief    Initialization and Configuration functions 
-  *
-  @verbatim    
-  ==============================================================================
-           ##### SRAM Initialization and de_initialization functions #####
-  ==============================================================================
-    [..]  This section provides functions allowing to initialize/de-initialize
-          the SRAM memory
-  
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Performs the SRAM device initialization sequence
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  Timing: Pointer to SRAM control timing structure 
-  * @param  ExtTiming: Pointer to SRAM extended mode timing structure  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming)
-{ 
-  /* Check the SRAM handle parameter */
-  if(hsram == HAL_NULL)
-  {
-     return HAL_ERROR;
-  }
-  
-  if(hsram->State == HAL_SRAM_STATE_RESET)
-  {  
-    /* Initialize the low level hardware (MSP) */
-    HAL_SRAM_MspInit(hsram);
-  }
-  
-  /* Initialize SRAM control Interface */
-  FSMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
-
-  /* Initialize SRAM timing Interface */
-  FSMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank); 
-
-  /* Initialize SRAM extended mode timing Interface */
-  FSMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);  
-  
-  /* Enable the NORSRAM device */
-  __FSMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank); 
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Performs the SRAM device De-initialization sequence.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
-{ 
-  /* De-Initialize the low level hardware (MSP) */
-  HAL_SRAM_MspDeInit(hsram);
-   
-  /* Configure the SRAM registers with their reset values */
-  FSMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
-
-  hsram->State = HAL_SRAM_STATE_RESET;
-  
-  /* Release Lock */
-  __HAL_UNLOCK(hsram);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  SRAM MSP Init.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval None
-  */
-__weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SRAM_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  SRAM MSP DeInit.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval None
-  */
-__weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SRAM_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DMA transfer complete callback.
-  * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval None
-  */
-__weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  DMA transfer complete error callback.
-  * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval None
-  */
-__weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SRAM_Exported_Functions_Group2 Input and Output functions 
-  * @brief    Input Output and memory control functions 
-  *
-  @verbatim    
-  ==============================================================================
-                  ##### SRAM Input and Output functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to use and control the SRAM memory
-  
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Reads 8-bit buffer from SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to read start address
-  * @param  pDstBuffer: Pointer to destination buffer  
-  * @param  BufferSize: Size of the buffer to read from memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
-{
-  __IO uint8_t * psramaddress = (uint8_t *)pAddress;
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;  
-  
-  /* Read data from memory */
-  for(; BufferSize != 0; BufferSize--)
-  {
-    *pDstBuffer = *(__IO uint8_t *)psramaddress;
-    pDstBuffer++;
-    psramaddress++;
-  }
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;    
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-    
-  return HAL_OK;   
-}
-
-/**
-  * @brief  Writes 8-bit buffer to SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to write start address
-  * @param  pSrcBuffer: Pointer to source buffer to write  
-  * @param  BufferSize: Size of the buffer to write to memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
-{
-  __IO uint8_t * psramaddress = (uint8_t *)pAddress;
-  
-  /* Check the SRAM controller state */
-  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
-  {
-    return  HAL_ERROR; 
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY; 
-
-  /* Write data to memory */
-  for(; BufferSize != 0; BufferSize--)
-  {
-    *(__IO uint8_t *)psramaddress = *pSrcBuffer; 
-    pSrcBuffer++;
-    psramaddress++;    
-  }    
-
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);
-    
-  return HAL_OK;   
-}
-
-/**
-  * @brief  Reads 16-bit buffer from SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to read start address
-  * @param  pDstBuffer: Pointer to destination buffer  
-  * @param  BufferSize: Size of the buffer to read from memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
-{
-  __IO uint16_t * psramaddress = (uint16_t *)pAddress;
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;  
-  
-  /* Read data from memory */
-  for(; BufferSize != 0; BufferSize--)
-  {
-    *pDstBuffer = *(__IO uint16_t *)psramaddress;
-    pDstBuffer++;
-    psramaddress++;
-  }
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;    
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-    
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Writes 16-bit buffer to SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to write start address
-  * @param  pSrcBuffer: Pointer to source buffer to write  
-  * @param  BufferSize: Size of the buffer to write to memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
-{
-  __IO uint16_t * psramaddress = (uint16_t *)pAddress; 
-  
-  /* Check the SRAM controller state */
-  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
-  {
-    return  HAL_ERROR; 
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY; 
-
-  /* Write data to memory */
-  for(; BufferSize != 0; BufferSize--)
-  {
-    *(__IO uint16_t *)psramaddress = *pSrcBuffer; 
-    pSrcBuffer++;
-    psramaddress++;    
-  }    
-
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);
-    
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Reads 32-bit buffer from SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to read start address
-  * @param  pDstBuffer: Pointer to destination buffer  
-  * @param  BufferSize: Size of the buffer to read from memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;  
-  
-  /* Read data from memory */
-  for(; BufferSize != 0; BufferSize--)
-  {
-    *pDstBuffer = *(__IO uint32_t *)pAddress;
-    pDstBuffer++;
-    pAddress++;
-  }
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;    
-
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-    
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Writes 32-bit buffer to SRAM memory. 
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to write start address
-  * @param  pSrcBuffer: Pointer to source buffer to write  
-  * @param  BufferSize: Size of the buffer to write to memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
-  /* Check the SRAM controller state */
-  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
-  {
-    return  HAL_ERROR; 
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY; 
-
-  /* Write data to memory */
-  for(; BufferSize != 0; BufferSize--)
-  {
-    *(__IO uint32_t *)pAddress = *pSrcBuffer; 
-    pSrcBuffer++;
-    pAddress++;    
-  }    
-
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);
-    
-  return HAL_OK;   
-}
-
-/**
-  * @brief  Reads a Words data from the SRAM memory using DMA transfer.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to read start address
-  * @param  pDstBuffer: Pointer to destination buffer  
-  * @param  BufferSize: Size of the buffer to read from memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
-{
-  /* Process Locked */
-  __HAL_LOCK(hsram);  
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;   
-  
-  /* Configure DMA user callbacks */
-  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
-  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY; 
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);  
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @param  pAddress: Pointer to write start address
-  * @param  pSrcBuffer: Pointer to source buffer to write  
-  * @param  BufferSize: Size of the buffer to write to memory
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
-{
-  /* Check the SRAM controller state */
-  if(hsram->State == HAL_SRAM_STATE_PROTECTED)
-  {
-    return  HAL_ERROR; 
-  }
-  
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY; 
-  
-  /* Configure DMA user callbacks */
-  hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
-  hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
-
-  /* Enable the DMA Stream */
-  HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;  
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram);  
-  
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-  
-/** @defgroup SRAM_Exported_Functions_Group3 Control functions 
- *  @brief   management functions 
- *
-@verbatim   
-  ==============================================================================
-                        ##### SRAM Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the SRAM interface.
-
-@endverbatim
-  * @{
-  */
-    
-/**
-  * @brief  Enables dynamically SRAM write operation.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
-{
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-
-  /* Enable write operation */
-  FSMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank); 
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_READY;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Disables dynamically SRAM write operation.
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
-{
-  /* Process Locked */
-  __HAL_LOCK(hsram);
-
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_BUSY;
-    
-  /* Disable write operation */
-  FSMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank); 
-  
-  /* Update the SRAM controller state */
-  hsram->State = HAL_SRAM_STATE_PROTECTED;
-  
-  /* Process unlocked */
-  __HAL_UNLOCK(hsram); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup SRAM_Exported_Functions_Group4 State functions 
- *  @brief   Peripheral State functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### SRAM State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in run-time the status of the SRAM controller 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Returns the SRAM controller state
-  * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
-  *                the configuration information for SRAM module.
-  * @retval HAL state
-  */
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
-{
-  return hsram->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-#endif /* HAL_SRAM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_sram.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,202 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_sram.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of SRAM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_SRAM_H
-#define __STM32L1xx_HAL_SRAM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_ll_fsmc.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SRAM
-  * @{
-  */ 
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/* Exported typedef ----------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_typedef SRAM Exported typedef
-  * @{
-  */ 
-
-/** 
-  * @brief  HAL SRAM State structures definition  
-  */ 
-typedef enum
-{
-  HAL_SRAM_STATE_RESET     = 0x00,  /*!< SRAM not yet initialized or disabled           */
-  HAL_SRAM_STATE_READY     = 0x01,  /*!< SRAM initialized and ready for use             */
-  HAL_SRAM_STATE_BUSY      = 0x02,  /*!< SRAM internal process is ongoing               */
-  HAL_SRAM_STATE_ERROR     = 0x03,  /*!< SRAM error state                               */
-  HAL_SRAM_STATE_PROTECTED = 0x04   /*!< SRAM peripheral NORSRAM device write protected */
-  
-}HAL_SRAM_StateTypeDef;
-
-/** 
-  * @brief  SRAM handle Structure definition  
-  */ 
-typedef struct
-{
-  FSMC_NORSRAM_TYPEDEF           *Instance;  /*!< Register base address                        */ 
-  
-  FSMC_NORSRAM_EXTENDED_TYPEDEF  *Extended;  /*!< Extended mode register base address          */
-  
-  FSMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
-
-  HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */ 
-  
-  __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
-  
-  DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
-  
-}SRAM_HandleTypeDef; 
-
-/**
-  * @}
-  */ 
-
-/* Exported constants --------------------------------------------------------*/ 
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup SRAM_Exported_macro SRAM Exported macro
-  * @{
-  */ 
-
-/** @brief Reset SRAM handle state
-  * @param  __HANDLE__: SRAM handle
-  * @retval None
-  */
-#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup SRAM_Exported_Functions
- *  @{
- */
-
-/** @addtogroup SRAM_Exported_Functions_Group1
- *  @{
- */
- 
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FSMC_NORSRAM_TimingTypeDef *Timing, FSMC_NORSRAM_TimingTypeDef *ExtTiming);
-HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
-void              HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
-void              HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
-
-void              HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
-void              HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup SRAM_Exported_Functions_Group2
- *  @{
- */
- 
-/* I/O operation functions  *****************************************************/
-HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
-HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup SRAM_Exported_Functions_Group3
- *  @{
- */
- 
-/* SRAM Control functions  ******************************************************/
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
-HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup SRAM_Exported_Functions_Group4
- *  @{
- */
- 
-/* SRAM State functions *********************************************************/
-HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_SRAM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,5039 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_tim.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer (TIM) peripheral:
-  *           + Time Base Initialization
-  *           + Time Base Start
-  *           + Time Base Start Interruption
-  *           + Time Base Start DMA
-  *           + Time Output Compare/PWM Initialization
-  *           + Time Output Compare/PWM Channel Configuration
-  *           + Time Output Compare/PWM  Start
-  *           + Time Output Compare/PWM  Start Interruption
-  *           + Time Output Compare/PWM Start DMA
-  *           + Time Input Capture Initialization
-  *           + Time Input Capture Channel Configuration
-  *           + Time Input Capture Start
-  *           + Time Input Capture Start Interruption
-  *           + Time Input Capture Start DMA
-  *           + Time One Pulse Initialization
-  *           + Time One Pulse Channel Configuration
-  *           + Time One Pulse Start
-  *           + Time Encoder Interface Initialization
-  *           + Time Encoder Interface Start
-  *           + Time Encoder Interface Start Interruption
-  *           + Time Encoder Interface Start DMA
-  *           + Commutation Event configuration with Interruption and DMA
-  *           + Time OCRef clear configuration
-  *           + Time External Clock configuration
-  *           + Time Master and Slave synchronization configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Generic features #####
-  ==============================================================================
-  [..] The Timer features include:
-       (#) 16-bit up, down, up/down auto-reload counter.
-       (#) 16-bit programmable prescaler allowing dividing (also on the fly) the
-           counter clock frequency either by any factor between 1 and 65536.
-       (#) Up to 4 independent channels for:
-           (++) Input Capture
-           (++) Output Compare
-           (++) PWM generation (Edge and Center-aligned Mode)
-           (++) One-pulse mode output
-       (#) Synchronization circuit to control the timer with external signals and to interconnect
-           several timers together.
-       (#) Supports incremental (quadrature) encoder
-
-            ##### How to use this driver #####
-================================================================================
-    [..]
-     (#) Initialize the TIM low level resources by implementing the following functions
-         depending from feature used :
-           (++) Time Base : HAL_TIM_Base_MspInit()
-           (++) Input Capture : HAL_TIM_IC_MspInit()
-           (++) Output Compare : HAL_TIM_OC_MspInit()
-           (++) PWM generation : HAL_TIM_PWM_MspInit()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_MspInit()
-           (++) Encoder mode output : HAL_TIM_Encoder_MspInit()
-
-     (#) Initialize the TIM low level resources :
-        (##) Enable the TIM interface clock using __TIMx_CLK_ENABLE();
-        (##) TIM pins configuration
-            (+++) Enable the clock for the TIM GPIOs using the following function:
-             __GPIOx_CLK_ENABLE();
-            (+++) Configure these TIM pins in Alternate function mode using HAL_GPIO_Init();
-
-     (#) The external Clock can be configured, if needed (the default clock is the
-         internal clock from the APBx), using the following function:
-         HAL_TIM_ConfigClockSource, the clock configuration should be done before
-         any start function.
-
-     (#) Configure the TIM in the desired functioning mode using one of the
-       Initialization function of this driver:
-       (++) HAL_TIM_Base_Init: to use the Timer to generate a simple time base
-       (++) HAL_TIM_OC_Init and HAL_TIM_OC_ConfigChannel: to use the Timer to generate an
-            Output Compare signal.
-       (++) HAL_TIM_PWM_Init and HAL_TIM_PWM_ConfigChannel: to use the Timer to generate a
-            PWM signal.
-       (++) HAL_TIM_IC_Init and HAL_TIM_IC_ConfigChannel: to use the Timer to measure an
-            external signal.
-         (++) HAL_TIM_OnePulse_Init and HAL_TIM_OnePulse_ConfigChannel: to use the Timer
-              in One Pulse Mode.
-       (++) HAL_TIM_Encoder_Init: to use the Timer Encoder Interface.
-
-     (#) Activate the TIM peripheral using one of the start functions depending from the feature used:
-           (++) Time Base : HAL_TIM_Base_Start(), HAL_TIM_Base_Start_DMA(), HAL_TIM_Base_Start_IT()
-           (++) Input Capture :  HAL_TIM_IC_Start(), HAL_TIM_IC_Start_DMA(), HAL_TIM_IC_Start_IT()
-           (++) Output Compare : HAL_TIM_OC_Start(), HAL_TIM_OC_Start_DMA(), HAL_TIM_OC_Start_IT()
-           (++) PWM generation : HAL_TIM_PWM_Start(), HAL_TIM_PWM_Start_DMA(), HAL_TIM_PWM_Start_IT()
-           (++) One-pulse mode output : HAL_TIM_OnePulse_Start(), HAL_TIM_OnePulse_Start_IT()
-           (++) Encoder mode output : HAL_TIM_Encoder_Start(), HAL_TIM_Encoder_Start_DMA(), HAL_TIM_Encoder_Start_IT().
-
-     (#) The DMA Burst is managed with the two following functions:
-         HAL_TIM_DMABurst_WriteStart()
-         HAL_TIM_DMABurst_ReadStart()
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIM TIM
-  * @brief TIM HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @defgroup TIM_Private_Functions TIM Private Functions
-  * @{
-  */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter);
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter);
-
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
-
-static void TIM_ITRx_SetConfig(TIM_TypeDef* TIMx, uint16_t InputTriggerSource);
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
-static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
-static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
-static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
-static void TIM_DMAError(DMA_HandleTypeDef *hdma);
-static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
-static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
-
-/**
-    * @}
-  */
-
-/* External functions ---------------------------------------------------------*/
-
-/** @defgroup TIM_Exported_Functions TIM Exported Functions
-  * @{
-  */
-
-/** @defgroup TIM_Exported_Functions_Group1 Time Base functions
- *  @brief    Time Base functions
- *
-@verbatim
-  ==============================================================================
-              ##### Time Base functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM base.
-    (+) De-initialize the TIM base.
-    (+) Start the Time Base.
-    (+) Stop the Time Base.
-    (+) Start the Time Base and enable interrupt.
-    (+) Stop the Time Base and disable interrupt.
-    (+) Start the Time Base and enable DMA transfer.
-    (+) Stop the Time Base and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Time base Unit according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC */
-    HAL_TIM_Base_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Set the Time Base configuration */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM Base peripheral
-  * @param  htim: TIM Base handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Base_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Base MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Base MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Base_MspDeInit could be implemented in the user file
-   */
-}
-
-
-/**
-  * @brief  Starts the TIM Base generation.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-   /* Enable the TIM Update interrupt */
-   __HAL_TIM_ENABLE_IT(htim, TIM_IT_UPDATE);
-
-   /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  /* Disable the TIM Update interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_UPDATE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Base generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to peripheral.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  /* Set the DMA Period elapsed callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-  /* Set the DMA error callback */
-  htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-  /* Enable the DMA channel */
-  HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)pData, (uint32_t)&htim->Instance->ARR, Length);
-
-  /* Enable the TIM Update DMA request */
-  __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Base generation in DMA mode.
-  * @param  htim : TIM handle
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_INSTANCE(htim->Instance));
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_UPDATE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group2 Time Output Compare functions
- *  @brief    Time Output Compare functions
- *
-@verbatim
-  ==============================================================================
-                  ##### Time Output Compare functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Output Compare.
-    (+) De-initialize the TIM Output Compare.
-    (+) Start the Time Output Compare.
-    (+) Stop the Time Output Compare.
-    (+) Start the Time Output Compare and enable interrupt.
-    (+) Stop the Time Output Compare and disable interrupt.
-    (+) Start the Time Output Compare and enable DMA transfer.
-    (+) Stop the Time Output Compare and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Output Compare according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: TIM Output Compare handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef* htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OC_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the Output Compare */
-  TIM_Base_SetConfig(htim->Instance,  &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim: TIM Output Compare handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-   htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_OC_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Output Compare MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Output Compare MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim : TIM OC handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in interrupt mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Output Compare signal generation in DMA mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Output Compare signal generation in DMA mode.
-  * @param  htim : TIM Output Compare handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Output compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group3 Time PWM functions
- *  @brief    Time PWM functions
- *
-@verbatim
-  ==============================================================================
-                          ##### Time PWM functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM OPWM.
-    (+) De-initialize the TIM PWM.
-    (+) Start the Time PWM.
-    (+) Stop the Time PWM.
-    (+) Start the Time PWM and enable interrupt.
-    (+) Stop the Time PWM and disable interrupt.
-    (+) Start the Time PWM and enable DMA transfer.
-    (+) Stop the Time PWM and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM PWM Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: TIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_PWM_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the PWM */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim: TIM handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_PWM_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM PWM MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_PWM_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the PWM signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the PWM signal generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channel to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the PWM signal generation in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM PWM signal generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The source Buffer address.
-  * @param  Length: The length of data to be transferred from memory to TIM peripheral
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if(((uint32_t)pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)pData, (uint32_t)&htim->Instance->CCR1, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)pData, (uint32_t)&htim->Instance->CCR2, Length);
-
-      /* Enable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)pData, (uint32_t)&htim->Instance->CCR3,Length);
-
-      /* Enable the TIM Output Capture/Compare 3 request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-     /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)pData, (uint32_t)&htim->Instance->CCR4, Length);
-
-      /* Enable the TIM Capture/Compare 4 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM PWM signal generation in DMA mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Capture compare channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group4 Time Input Capture functions
- *  @brief    Time Input Capture functions
- *
-@verbatim
-  ==============================================================================
-              ##### Time Input Capture functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-   (+) Initialize and configure the TIM Input Capture.
-   (+) De-initialize the TIM Input Capture.
-   (+) Start the Time Input Capture.
-   (+) Stop the Time Input Capture.
-   (+) Start the Time Input Capture and enable interrupt.
-   (+) Stop the Time Input Capture and disable interrupt.
-   (+) Start the Time Input Capture and enable DMA transfer.
-   (+) Stop the Time Input Capture and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Input Capture Time base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: TIM Input Capture handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim)
-{
-  /* Check the TIM handle allocation */
-  if(htim == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_IC_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Init the base time for the input capture */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM peripheral
-  * @param  htim: TIM Input Capture handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
-  HAL_TIM_IC_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM INput Capture MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Input Capture MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_IC_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement in interrupt mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Enable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Enable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Enable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Enable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement in interrupt mode.
-  * @param  htim : TIM handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4 interrupt */
-      __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Input Capture measurement on in DMA mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  pData: The destination Buffer address.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((pData == 0 ) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 2  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->CCR3, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->CCR4, (uint32_t)pData, Length);
-
-      /* Enable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Enable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_ENABLE);
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Input Capture measurement on in DMA mode.
-  * @param  htim : TIM Input Capture handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CCX_INSTANCE(htim->Instance, Channel));
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Disable the TIM Capture/Compare 1 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Disable the TIM Capture/Compare 2 DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      /* Disable the TIM Capture/Compare 3  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC3);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      /* Disable the TIM Capture/Compare 4  DMA request */
-      __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC4);
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  /* Disable the Input Capture channel */
-  TIM_CCxChannelCmd(htim->Instance, Channel, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group5 Time One Pulse functions
- *  @brief    Time One Pulse functions
- *
-@verbatim
-  ==============================================================================
-                        ##### Time One Pulse functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM One Pulse.
-    (+) De-initialize the TIM One Pulse.
-    (+) Start the Time One Pulse.
-    (+) Stop the Time One Pulse.
-    (+) Start the Time One Pulse and enable interrupt.
-    (+) Stop the Time One Pulse and disable interrupt.
-    (+) Start the Time One Pulse and enable DMA transfer.
-    (+) Stop the Time One Pulse and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM One Pulse Time Base according to the specified
-  *         parameters in the TIM_HandleTypeDef and create the associated handle.
-  * @param  htim: TIM OnePulse handle
-  * @param  OnePulseMode: Select the One pulse mode.
-  *         This parameter can be one of the following values:
-  *            @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
-  *            @arg TIM_OPMODE_REPETITIVE: Repetitive pulses wil be generated.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode)
-{
-  /* Check the TIM handle allocation */
-  if(htim == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
-  assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
-  assert_param(IS_TIM_OPM_MODE(OnePulseMode));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_OnePulse_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Configure the Time base in the One Pulse Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Reset the OPM Bit */
-  htim->Instance->CR1 &= ~TIM_CR1_OPM;
-
-  /* Configure the OPM Mode */
-  htim->Instance->CR1 |= OnePulseMode;
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the TIM One Pulse
-  * @param  htim: TIM One Pulse handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_OnePulse_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM One Pulse MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_OnePulse_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be disable
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Enable the Capture compare and the Input Capture channels
-    (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-    if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-    if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-    in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be enabled together
-
-    No need to enable the counter, it's enabled automatically by hardware
-    (the counter starts in response to a stimulus and generate a pulse */
-
-  /* Enable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-
-  /* Enable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM One Pulse signal generation in interrupt mode.
-  * @param  htim : TIM One Pulse handle
-  * @param  OutputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
-{
-  /* Disable the TIM Capture/Compare 1 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-
-  /* Disable the TIM Capture/Compare 2 interrupt */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-
-  /* Disable the Capture compare and the Input Capture channels
-  (in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
-  if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
-  if TIM_CHANNEL_1 is used as input, the TIM_CHANNEL_2 will be used as output
-  in all combinations, the TIM_CHANNEL_1 and TIM_CHANNEL_2 should be disabled together */
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-  TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-  /* Disable the Peripheral */
-   __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group6 Time Encoder functions
- *  @brief    Time Encoder functions
- *
-@verbatim
-  ==============================================================================
-                          ##### Time Encoder functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Initialize and configure the TIM Encoder.
-    (+) De-initialize the TIM Encoder.
-    (+) Start the Time Encoder.
-    (+) Stop the Time Encoder.
-    (+) Start the Time Encoder and enable interrupt.
-    (+) Stop the Time Encoder and disable interrupt.
-    (+) Start the Time Encoder and enable DMA transfer.
-    (+) Stop the Time Encoder and disable DMA transfer.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  Initializes the TIM Encoder Interface and create the associated handle.
-  * @param  htim: TIM Encoder Interface handle
-  * @param  sConfig: TIM Encoder Interface configuration structure
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig)
-{
-  uint32_t tmpsmcr = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Check the TIM handle allocation */
-  if(htim == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_ENCODER_MODE(sConfig->EncoderMode));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC1Selection));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->IC2Selection));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC1Polarity));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->IC2Polarity));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->IC2Prescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
-  assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
-
-  if(htim->State == HAL_TIM_STATE_RESET)
-  {
-    /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
-    HAL_TIM_Encoder_MspInit(htim);
-  }
-
-  /* Set the TIM state */
-  htim->State= HAL_TIM_STATE_BUSY;
-
-  /* Reset the SMS bits */
-  htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-
-  /* Configure the Time base in the Encoder Mode */
-  TIM_Base_SetConfig(htim->Instance, &htim->Init);
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmr1 = htim->Instance->CCMR1;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = htim->Instance->CCER;
-
-  /* Set the encoder Mode */
-  tmpsmcr |= sConfig->EncoderMode;
-
-  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
-  tmpccmr1 &= ~(TIM_CCMR1_CC1S | TIM_CCMR1_CC2S);
-  tmpccmr1 |= (sConfig->IC1Selection | (sConfig->IC2Selection << 8));
-
-  /* Set the the Capture Compare 1 and the Capture Compare 2 prescalers and filters */
-  tmpccmr1 &= ~(TIM_CCMR1_IC1PSC | TIM_CCMR1_IC2PSC);
-  tmpccmr1 &= (~(TIM_CCMR1_IC1F | TIM_CCMR1_IC2F));
-  tmpccmr1 |= sConfig->IC1Prescaler | (sConfig->IC2Prescaler << 8);
-  tmpccmr1 |= (sConfig->IC1Filter << 4) | (sConfig->IC2Filter << 12);
-
-  /* Set the TI1 and the TI2 Polarities */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC2P);
-  tmpccer &= ~(TIM_CCER_CC1NP | TIM_CCER_CC2NP);
-  tmpccer |= sConfig->IC1Polarity | (sConfig->IC2Polarity << 4);
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Write to TIMx CCMR1 */
-  htim->Instance->CCMR1 = tmpccmr1;
-
-  /* Write to TIMx CCER */
-  htim->Instance->CCER = tmpccer;
-
-  /* Initialize the TIM state*/
-  htim->State= HAL_TIM_STATE_READY;
-
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  DeInitializes the TIM Encoder interface
-  * @param  htim: TIM Encoder handle
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Disable the TIM Peripheral Clock */
-  __HAL_TIM_DISABLE(htim);
-
-  /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
-  HAL_TIM_Encoder_MspDeInit(htim);
-
-  /* Change TIM state */
-  htim->State = HAL_TIM_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Encoder Interface MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes TIM Encoder Interface MSP.
-  * @param  htim: TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_Encoder_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Enable the encoder interface channels */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      break;
-  }
-    case TIM_CHANNEL_2:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-      break;
-  }
-    default :
-  {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     break;
-    }
-  }
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-   /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-  {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-      break;
-  }
-    case TIM_CHANNEL_2:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-      break;
-  }
-    default :
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-     break;
-    }
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in interrupt mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Enable the encoder interface channels */
-  /* Enable the capture compare Interrupts 1 and/or 2 */
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-      break;
-  }
-    case TIM_CHANNEL_2:
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-    __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-      break;
-  }
-    default :
-  {
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-     TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
-     __HAL_TIM_ENABLE_IT(htim, TIM_IT_CC2);
-     break;
-    }
-  }
-
-  /* Enable the Peripheral */
-  __HAL_TIM_ENABLE(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in interrupt mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be disabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if(Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-  }
-  else if(Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 2 */
-  __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare Interrupts 1 and 2 */
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
-    __HAL_TIM_DISABLE_IT(htim, TIM_IT_CC2);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the TIM Encoder Interface in DMA mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  pData1: The destination Buffer address for IC1.
-  * @param  pData2: The destination Buffer address for IC2.
-  * @param  Length: The length of data to be transferred from TIM peripheral to memory.
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((((pData1 == 0) || (pData2 == 0) )) && (Length > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t )pData1, Length);
-
-      /* Enable the TIM Input Capture DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError;
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-
-      /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-    }
-    break;
-
-    case TIM_CHANNEL_ALL:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->CCR1, (uint32_t)pData1, Length);
-
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback = TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->CCR2, (uint32_t)pData2, Length);
-
-     /* Enable the Peripheral */
-      __HAL_TIM_ENABLE(htim);
-
-      /* Enable the Capture compare channel */
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_ENABLE);
-      TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_ENABLE);
-
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC1);
-      /* Enable the TIM Input Capture  DMA request */
-      __HAL_TIM_ENABLE_DMA(htim, TIM_DMA_CC2);
-    }
-    break;
-
-    default:
-    break;
-  }
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM Encoder Interface in DMA mode.
-  * @param  htim : TIM Encoder Interface handle
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-*/
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_CC_INSTANCE(htim->Instance));
-
-  /* Disable the Input Capture channels 1 and 2
-    (in the EncoderInterface the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2) */
-  if(Channel == TIM_CHANNEL_1)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-  }
-  else if(Channel == TIM_CHANNEL_2)
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }
-  else
-  {
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_1, TIM_CCx_DISABLE);
-    TIM_CCxChannelCmd(htim->Instance, TIM_CHANNEL_2, TIM_CCx_DISABLE);
-
-    /* Disable the capture compare DMA Request 1 and 2 */
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC1);
-    __HAL_TIM_DISABLE_DMA(htim, TIM_DMA_CC2);
-  }
-
-  /* Disable the Peripheral */
-  __HAL_TIM_DISABLE(htim);
-
-  /* Change the htim state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-/** @defgroup TIM_Exported_Functions_Group7 TIM IRQ handler management
- *  @brief    IRQ handler management
- *
-@verbatim
-  ==============================================================================
-                        ##### IRQ handler management #####
-  ==============================================================================
-  [..]
-    This section provides Timer IRQ handler function.
-
-@endverbatim
-  * @{
-  */
-/**
-  * @brief  This function handles TIM interrupts requests.
-  * @param  htim: TIM  handle
-  * @retval None
-  */
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim)
-{
-  /* Capture compare 1 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC1) != RESET)
-  {
-    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC1) !=RESET)
-    {
-      {
-        __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC1);
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-
-        /* Input capture event */
-        if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
-        {
-          HAL_TIM_IC_CaptureCallback(htim);
-        }
-        /* Output compare event */
-        else
-        {
-          HAL_TIM_OC_DelayElapsedCallback(htim);
-          HAL_TIM_PWM_PulseFinishedCallback(htim);
-        }
-        htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-      }
-    }
-  }
-  /* Capture compare 2 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC2) != RESET)
-  {
-    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC2) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC2);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-      /* Input capture event */
-      if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 3 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC3) != RESET)
-  {
-    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC3) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC3);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-      /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* Capture compare 4 event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_CC4) != RESET)
-  {
-    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_CC4) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_CC4);
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-      /* Input capture event */
-      if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
-      {
-        HAL_TIM_IC_CaptureCallback(htim);
-      }
-      /* Output compare event */
-      else
-      {
-        HAL_TIM_OC_DelayElapsedCallback(htim);
-        HAL_TIM_PWM_PulseFinishedCallback(htim);
-      }
-      htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-    }
-  }
-  /* TIM Update event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_UPDATE) != RESET)
-  {
-    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_UPDATE) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
-      HAL_TIM_PeriodElapsedCallback(htim);
-    }
-  }
-  /* TIM Trigger detection event */
-  if(__HAL_TIM_GET_FLAG(htim, TIM_FLAG_TRIGGER) != RESET)
-  {
-    if(__HAL_TIM_GET_ITSTATUS(htim, TIM_IT_TRIGGER) !=RESET)
-    {
-      __HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
-      HAL_TIM_TriggerCallback(htim);
-    }
-  }
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions
- *  @brief   	Peripheral Control functions
- *
-@verbatim
-  ==============================================================================
-                   ##### Peripheral Control functions #####
-  ==============================================================================
- [..]
-   This section provides functions allowing to:
-      (+) Configure The Input Output channels for OC, PWM, IC or One Pulse mode.
-      (+) Configure External Clock source.
-      (+) Configure Complementary channels, break features and dead time.
-      (+) Configure Master and the Slave synchronization.
-      (+) Configure the DMA Burst Mode.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the TIM Output Compare Channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: TIM Output Compare handle
-  * @param  sConfig: TIM Output Compare configuration structure
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_OC_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-  assert_param(IS_TIM_FAST_STATE(sConfig->OCFastMode));
-
-  /* Check input state */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 1 in Output Compare */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 2 in Output Compare */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-       assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      /* Configure the TIM Channel 3 in Output Compare */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-       /* Configure the TIM Channel 4 in Output Compare */
-       TIM_OC4_SetConfig(htim->Instance, sConfig);
-    }
-    break;
-
-    default:
-    break;
-  }
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM Input Capture Channels according to the specified
-  *         parameters in the TIM_IC_InitTypeDef.
-  * @param  htim: TIM IC handle
-  * @param  sConfig: TIM Input Capture configuration structure
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_IC_POLARITY(sConfig->ICPolarity));
-  assert_param(IS_TIM_IC_SELECTION(sConfig->ICSelection));
-  assert_param(IS_TIM_IC_PRESCALER(sConfig->ICPrescaler));
-  assert_param(IS_TIM_IC_FILTER(sConfig->ICFilter));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  if (Channel == TIM_CHANNEL_1)
-  {
-    /* TI1 Configuration */
-    TIM_TI1_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC1PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-    /* Set the IC1PSC value */
-    htim->Instance->CCMR1 |= sConfig->ICPrescaler;
-  }
-  else if (Channel == TIM_CHANNEL_2)
-  {
-    /* TI2 Configuration */
-    assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-    TIM_TI2_SetConfig(htim->Instance,
-                      sConfig->ICPolarity,
-                      sConfig->ICSelection,
-                      sConfig->ICFilter);
-
-    /* Reset the IC2PSC Bits */
-    htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-    /* Set the IC2PSC value */
-    htim->Instance->CCMR1 |= (sConfig->ICPrescaler << 8);
-  }
-  else if (Channel == TIM_CHANNEL_3)
-  {
-    /* TI3 Configuration */
-    assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-    TIM_TI3_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC3PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC3PSC;
-
-    /* Set the IC3PSC value */
-    htim->Instance->CCMR2 |= sConfig->ICPrescaler;
-  }
-  else
-  {
-    /* TI4 Configuration */
-    assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-    TIM_TI4_SetConfig(htim->Instance,
-               sConfig->ICPolarity,
-               sConfig->ICSelection,
-               sConfig->ICFilter);
-
-    /* Reset the IC4PSC Bits */
-    htim->Instance->CCMR2 &= ~TIM_CCMR2_IC4PSC;
-
-    /* Set the IC4PSC value */
-    htim->Instance->CCMR2 |= (sConfig->ICPrescaler << 8);
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM PWM  channels according to the specified
-  *         parameters in the TIM_OC_InitTypeDef.
-  * @param  htim: TIM handle
-  * @param  sConfig: TIM PWM configuration structure
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_CHANNELS(Channel));
-  assert_param(IS_TIM_PWM_MODE(sConfig->OCMode));
-  assert_param(IS_TIM_OC_POLARITY(sConfig->OCPolarity));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      /* Configure the Channel 1 in PWM mode */
-      TIM_OC1_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel1 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC1PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      /* Configure the Channel 2 in PWM mode */
-      TIM_OC2_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel2 */
-      htim->Instance->CCMR1 |= TIM_CCMR1_OC2PE;
-
-      /* Configure the Output Fast mode */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2FE;
-      htim->Instance->CCMR1 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    case TIM_CHANNEL_3:
-    {
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-      /* Configure the Channel 3 in PWM mode */
-      TIM_OC3_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel3 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC3PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode;
-    }
-    break;
-
-    case TIM_CHANNEL_4:
-    {
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-      /* Configure the Channel 4 in PWM mode */
-      TIM_OC4_SetConfig(htim->Instance, sConfig);
-
-      /* Set the Preload enable bit for channel4 */
-      htim->Instance->CCMR2 |= TIM_CCMR2_OC4PE;
-
-     /* Configure the Output Fast mode */
-      htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4FE;
-      htim->Instance->CCMR2 |= sConfig->OCFastMode << 8;
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the TIM One Pulse Channels according to the specified
-  *         parameters in the TIM_OnePulse_InitTypeDef.
-  * @param  htim: TIM One Pulse handle
-  * @param  sConfig: TIM One Pulse configuration structure
-  * @param  OutputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @param  InputChannel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim,  TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel)
-{
-  TIM_OC_InitTypeDef temp1;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OPM_CHANNELS(OutputChannel));
-  assert_param(IS_TIM_OPM_CHANNELS(InputChannel));
-
-  if(OutputChannel != InputChannel)
-  {
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Extract the Ouput compare configuration from sConfig structure */
-  temp1.OCMode = sConfig->OCMode;
-  temp1.Pulse = sConfig->Pulse;
-  temp1.OCPolarity = sConfig->OCPolarity;
-  temp1.OCIdleState = sConfig->OCIdleState;
-
-    switch (OutputChannel)
-  {
-    case TIM_CHANNEL_1:
-    {
-        assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      TIM_OC1_SetConfig(htim->Instance, &temp1);
-    }
-    break;
-    case TIM_CHANNEL_2:
-    {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      TIM_OC2_SetConfig(htim->Instance, &temp1);
-    }
-    break;
-    default:
-    break;
-  }
-  switch (InputChannel)
-  {
-    case TIM_CHANNEL_1:
-    {
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      TIM_TI1_SetConfig(htim->Instance, sConfig->ICPolarity,
-                        sConfig->ICSelection, sConfig->ICFilter);
-
-      /* Reset the IC1PSC Bits */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_IC1PSC;
-
-      /* Select the Trigger source */
-      htim->Instance->SMCR &= ~TIM_SMCR_TS;
-      htim->Instance->SMCR |= TIM_TS_TI1FP1;
-
-      /* Select the Slave Mode */
-      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-      htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-    }
-    break;
-    case TIM_CHANNEL_2:
-    {
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      TIM_TI2_SetConfig(htim->Instance, sConfig->ICPolarity,
-                 sConfig->ICSelection, sConfig->ICFilter);
-
-      /* Reset the IC2PSC Bits */
-      htim->Instance->CCMR1 &= ~TIM_CCMR1_IC2PSC;
-
-      /* Select the Trigger source */
-      htim->Instance->SMCR &= ~TIM_SMCR_TS;
-      htim->Instance->SMCR |= TIM_TS_TI2FP2;
-
-      /* Select the Slave Mode */
-      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-      htim->Instance->SMCR |= TIM_SLAVEMODE_TRIGGER;
-    }
-    break;
-
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-  else
-  {
-    return HAL_ERROR;
-  }
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
-  * @param  htim: TIM handle
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data write
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABase_CR1
-  *            @arg TIM_DMABase_CR2
-  *            @arg TIM_DMABase_SMCR
-  *            @arg TIM_DMABase_DIER
-  *            @arg TIM_DMABase_SR
-  *            @arg TIM_DMABase_EGR
-  *            @arg TIM_DMABase_CCMR1
-  *            @arg TIM_DMABase_CCMR2
-  *            @arg TIM_DMABase_CCER
-  *            @arg TIM_DMABase_CNT
-  *            @arg TIM_DMABase_PSC
-  *            @arg TIM_DMABase_ARR
-  *            @arg TIM_DMABase_CCR1
-  *            @arg TIM_DMABase_CCR2
-  *            @arg TIM_DMABase_CCR3
-  *            @arg TIM_DMABase_CCR4
-  *            @arg TIM_DMABase_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                              uint32_t* BurstBuffer, uint32_t  BurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((BurstBuffer == 0 ) && (BurstLength > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMADelayPulseCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)BurstBuffer, (uint32_t)&htim->Instance->DMAR, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    default:
-    break;
-  }
-   /* configure the DMA Burst Mode */
-   htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
-   /* Enable the TIM DMA Request */
-   __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
-   htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stops the TIM DMA Burst mode
-  * @param  htim: TIM handle
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
-  * @param  htim: TIM handle
-  * @param  BurstBaseAddress: TIM Base address from when the DMA will starts the Data read
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMABase_CR1
-  *            @arg TIM_DMABase_CR2
-  *            @arg TIM_DMABase_SMCR
-  *            @arg TIM_DMABase_DIER
-  *            @arg TIM_DMABase_SR
-  *            @arg TIM_DMABase_EGR
-  *            @arg TIM_DMABase_CCMR1
-  *            @arg TIM_DMABase_CCMR2
-  *            @arg TIM_DMABase_CCER
-  *            @arg TIM_DMABase_CNT
-  *            @arg TIM_DMABase_PSC
-  *            @arg TIM_DMABase_ARR
-  *            @arg TIM_DMABase_RCR
-  *            @arg TIM_DMABase_CCR1
-  *            @arg TIM_DMABase_CCR2
-  *            @arg TIM_DMABase_CCR3
-  *            @arg TIM_DMABase_CCR4
-  *            @arg TIM_DMABase_BDTR
-  *            @arg TIM_DMABase_DCR
-  * @param  BurstRequestSrc: TIM DMA Request sources
-  *         This parameters can be on of the following values:
-  *            @arg TIM_DMA_UPDATE: TIM update Interrupt source
-  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
-  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
-  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
-  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
-  *            @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
-  * @param  BurstBuffer: The Buffer address.
-  * @param  BurstLength: DMA Burst length. This parameter can be one value
-  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc,
-                                             uint32_t  *BurstBuffer, uint32_t  BurstLength)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMABURST_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_DMA_BASE(BurstBaseAddress));
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-  assert_param(IS_TIM_DMA_LENGTH(BurstLength));
-
-  if((htim->State == HAL_TIM_STATE_BUSY))
-  {
-     return HAL_BUSY;
-  }
-  else if((htim->State == HAL_TIM_STATE_READY))
-  {
-    if((BurstBuffer == 0 ) && (BurstLength > 0))
-    {
-      return HAL_ERROR;
-    }
-    else
-    {
-      htim->State = HAL_TIM_STATE_BUSY;
-    }
-  }
-  else
-  {
-    return HAL_ERROR;
-  }
-
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferCpltCallback = TIM_DMAPeriodElapsedCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_UPDATE]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-       HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_UPDATE], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferCpltCallback =  TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC1]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC1], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferCpltCallback =  TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC2]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC2], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferCpltCallback =  TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC3]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC3], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferCpltCallback =  TIM_DMACaptureCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_CC4]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_CC4], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      /* Set the DMA Period elapsed callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferCpltCallback = TIM_DMATriggerCplt;
-
-      /* Set the DMA error callback */
-      htim->hdma[TIM_DMA_ID_TRIGGER]->XferErrorCallback = TIM_DMAError ;
-
-      /* Enable the DMA channel */
-      HAL_DMA_Start_IT(htim->hdma[TIM_DMA_ID_TRIGGER], (uint32_t)&htim->Instance->DMAR, (uint32_t)BurstBuffer, ((BurstLength) >> 8) + 1);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* configure the DMA Burst Mode */
-  htim->Instance->DCR = BurstBaseAddress | BurstLength;
-
-  /* Enable the TIM DMA Request */
-  __HAL_TIM_ENABLE_DMA(htim, BurstRequestSrc);
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Stop the DMA burst reading
-  * @param  htim: TIM handle
-  * @param  BurstRequestSrc: TIM DMA Request sources to disable.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_DMA_SOURCE(BurstRequestSrc));
-
-  /* Abort the DMA transfer (at least disable the DMA channel) */
-  switch(BurstRequestSrc)
-  {
-    case TIM_DMA_UPDATE:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_UPDATE]);
-    }
-    break;
-    case TIM_DMA_CC1:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC1]);
-    }
-    break;
-    case TIM_DMA_CC2:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC2]);
-    }
-    break;
-    case TIM_DMA_CC3:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC3]);
-    }
-    break;
-    case TIM_DMA_CC4:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_CC4]);
-    }
-    break;
-    case TIM_DMA_TRIGGER:
-    {
-      HAL_DMA_Abort(htim->hdma[TIM_DMA_ID_TRIGGER]);
-    }
-    break;
-    default:
-    break;
-  }
-
-  /* Disable the TIM Update DMA request */
-  __HAL_TIM_DISABLE_DMA(htim, BurstRequestSrc);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Generate a software event
-  * @param  htim: TIM handle
-  * @param  EventSource: specifies the event source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_EventSource_Update: Timer update Event source
-  *            @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
-  *            @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
-  *            @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
-  *            @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
-  *            @arg TIM_EventSource_COM: Timer COM event source
-  *            @arg TIM_EventSource_Trigger: Timer Trigger Event source
-  *            @arg TIM_EventSource_Break: Timer Break event source
-  * @note   TBC can only generate an update event.
-  * @note   TIM_EventSource_COM and TIM_EventSource_Break are used only with TBC.
-  * @retval HAL status
-  */
-
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_EVENT_SOURCE(EventSource));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Set the event sources */
-  htim->Instance->EGR = EventSource;
-
-  /* Change the TIM state */
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the OCRef clear feature
-  * @param  htim: TIM handle
-  * @param  sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
-  *         contains the OCREF clear feature and parameters for the TIM peripheral.
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel)
-{
-
-  /* Check the parameters */
-  assert_param(IS_TIM_OCXREF_CLEAR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_CLEARINPUT_SOURCE(sClearInputConfig->ClearInputSource));
-  assert_param(IS_TIM_CLEARINPUT_POLARITY(sClearInputConfig->ClearInputPolarity));
-  assert_param(IS_TIM_CLEARINPUT_PRESCALER(sClearInputConfig->ClearInputPrescaler));
-  assert_param(IS_TIM_CLEARINPUT_FILTER(sClearInputConfig->ClearInputFilter));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  switch (sClearInputConfig->ClearInputSource)
-  {
-    case TIM_CLEARINPUTSOURCE_NONE:
-    {
-      /* Clear the OCREF clear selection bit */
-      CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
-
-      /* Clear the ETR Bits */
-      CLEAR_BIT(htim->Instance->SMCR, (TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
-
-    }
-    break;
-
-    case TIM_CLEARINPUTSOURCE_OCREFCLR:
-    {
-      /* Clear the OCREF clear selection bit */
-      CLEAR_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
-    }
-    break;
-    
-    case TIM_CLEARINPUTSOURCE_ETR:
-    {
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClearInputConfig->ClearInputPrescaler,
-                        sClearInputConfig->ClearInputPolarity,
-                        sClearInputConfig->ClearInputFilter);
-
-      /* Set the OCREF clear selection bit */
-      SET_BIT(htim->Instance->SMCR, TIM_SMCR_OCCS);
-    }
-    break;
-
-  default:
-    break;
-
-  }
-
-  switch (Channel)
-  {
-    case TIM_CHANNEL_1:
-      {
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 1 */
-          htim->Instance->CCMR1 |= TIM_CCMR1_OC1CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 1 */
-          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC1CE;
-        }
-      }
-      break;
-    case TIM_CHANNEL_2:
-      {
-        assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 2 */
-          htim->Instance->CCMR1 |= TIM_CCMR1_OC2CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 2 */
-          htim->Instance->CCMR1 &= ~TIM_CCMR1_OC2CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_3:
-      {
-        assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 3 */
-          htim->Instance->CCMR2 |= TIM_CCMR2_OC3CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 3 */
-          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC3CE;
-        }
-      }
-    break;
-    case TIM_CHANNEL_4:
-      {
-        assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-        if(sClearInputConfig->ClearInputState != RESET)
-        {
-          /* Enable the Ocref clear feature for Channel 4 */
-          htim->Instance->CCMR2 |= TIM_CCMR2_OC4CE;
-        }
-        else
-        {
-          /* Disable the Ocref clear feature for Channel 4 */
-          htim->Instance->CCMR2 &= ~TIM_CCMR2_OC4CE;
-        }
-      }
-    break;
-    default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief   Configures the clock source to be used
-  * @param  htim: TIM handle
-  * @param  sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
-  *         contains the clock source information for the TIM peripheral.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig)
-{
-  uint32_t tmpsmcr = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CLOCKSOURCE(sClockSourceConfig->ClockSource));
-  assert_param(IS_TIM_CLOCKPOLARITY(sClockSourceConfig->ClockPolarity));
-  assert_param(IS_TIM_CLOCKPRESCALER(sClockSourceConfig->ClockPrescaler));
-  assert_param(IS_TIM_CLOCKFILTER(sClockSourceConfig->ClockFilter));
-
-  /* Process Locked */
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Reset the SMS, TS, ECE, ETPS and ETRF bits */
-  tmpsmcr = htim->Instance->SMCR;
-  tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-  tmpsmcr &= ~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP);
-  htim->Instance->SMCR = tmpsmcr;
-
-  switch (sClockSourceConfig->ClockSource)
-  {
-  case TIM_CLOCKSOURCE_INTERNAL:
-    {
-      assert_param(IS_TIM_INSTANCE(htim->Instance));
-      /* Disable slave mode to clock the prescaler directly with the internal clock */
-      htim->Instance->SMCR &= ~TIM_SMCR_SMS;
-    }
-    break;
-
-  case TIM_CLOCKSOURCE_ETRMODE1:
-    {
-      /* Check whether or not the timer instance supports external trigger input mode 1 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Get the TIMx SMCR register value */
-      tmpsmcr = htim->Instance->SMCR;
-      /* Reset the SMS and TS Bits */
-      tmpsmcr &= ~(TIM_SMCR_SMS | TIM_SMCR_TS);
-      /* Select the External clock mode1 and the ETRF trigger */
-      tmpsmcr |= (TIM_SLAVEMODE_EXTERNAL1 | TIM_CLOCKSOURCE_ETRMODE1);
-      /* Write to TIMx SMCR */
-      htim->Instance->SMCR = tmpsmcr;
-    }
-    break;
-
-  case TIM_CLOCKSOURCE_ETRMODE2:
-    {
-      /* Check whether or not the timer instance supports external trigger input mode 2 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(htim->Instance));
-
-      /* Configure the ETR Clock source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sClockSourceConfig->ClockPrescaler,
-                        sClockSourceConfig->ClockPolarity,
-                        sClockSourceConfig->ClockFilter);
-      /* Enable the External clock mode2 */
-      htim->Instance->SMCR |= TIM_SMCR_ECE;
-    }
-    break;
-
-  case TIM_CLOCKSOURCE_TI1:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1);
-    }
-    break;
-  case TIM_CLOCKSOURCE_TI2:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 (ETRF)*/
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI2);
-    }
-    break;
-  case TIM_CLOCKSOURCE_TI1ED:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_TIX_INSTANCE(htim->Instance));
-
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sClockSourceConfig->ClockPolarity,
-                               sClockSourceConfig->ClockFilter);
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_TI1ED);
-    }
-    break;
-  case TIM_CLOCKSOURCE_ITR0:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR0);
-    }
-    break;
-  case TIM_CLOCKSOURCE_ITR1:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR1);
-    }
-    break;
-  case TIM_CLOCKSOURCE_ITR2:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR2);
-    }
-    break;
-  case TIM_CLOCKSOURCE_ITR3:
-    {
-      /* Check whether or not the timer instance supports external clock mode 1 */
-      assert_param(IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(htim->Instance));
-
-      TIM_ITRx_SetConfig(htim->Instance, TIM_CLOCKSOURCE_ITR3);
-    }
-    break;
-
-  default:
-    break;
-  }
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Selects the signal connected to the TI1 input: direct from CH1_input
-  *         or a XOR combination between CH1_input, CH2_input & CH3_input
-  * @param  htim: TIM handle.
-  * @param  TI1_Selection: Indicate whether or not channel 1 is connected to the
-  *         output of a XOR gate.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
-  *            @arg TIM_TI1SELECTION_XORCOMBINATION: The TIMx_CH1, CH2 and CH3
-  *            pins are connected to the TI1 input (XOR combination)
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection)
-{
-  uint32_t tmpcr2 = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_XOR_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TI1SELECTION(TI1_Selection));
-
-  /* Get the TIMx CR2 register value */
-  tmpcr2 = htim->Instance->CR2;
-
-  /* Reset the TI1 selection */
-  tmpcr2 &= ~TIM_CR2_TI1S;
-
-  /* Set the the TI1 selection */
-  tmpcr2 |= TI1_Selection;
-
-  /* Write to TIMxCR2 */
-  htim->Instance->CR2 = tmpcr2;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM in Slave mode
-  * @param  htim: TIM handle.
-  * @param  sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
-  *         contains the selected trigger (internal trigger input, filtered
-  *         timer input or external trigger input) and the ) and the Slave
-  *         mode (Disable, Reset, Gated, Trigger, External clock mode 1).
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig)
-{
-  uint32_t tmpsmcr = 0;
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_SLAVE_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_SLAVE_MODE(sSlaveConfig->SlaveMode));
-  assert_param(IS_TIM_TRIGGER_SELECTION(sSlaveConfig->InputTrigger));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Get the TIMx SMCR register value */
-  tmpsmcr = htim->Instance->SMCR;
-
-  /* Reset the Trigger Selection Bits */
-  tmpsmcr &= ~TIM_SMCR_TS;
-  /* Set the Input Trigger source */
-  tmpsmcr |= sSlaveConfig->InputTrigger;
-
-  /* Reset the slave mode Bits */
-  tmpsmcr &= ~TIM_SMCR_SMS;
-  /* Set the slave mode */
-  tmpsmcr |= sSlaveConfig->SlaveMode;
-
-  /* Write to TIMx SMCR */
-  htim->Instance->SMCR = tmpsmcr;
-
-  /* Configure the trigger prescaler, filter, and polarity */
-  switch (sSlaveConfig->InputTrigger)
-  {
-  case TIM_TS_ETRF:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPRESCALER(sSlaveConfig->TriggerPrescaler));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-      /* Configure the ETR Trigger source */
-      TIM_ETR_SetConfig(htim->Instance,
-                        sSlaveConfig->TriggerPrescaler,
-                        sSlaveConfig->TriggerPolarity,
-                        sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_TI1F_ED:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Disable the Channel 1: Reset the CC1E Bit */
-      tmpccer = htim->Instance->CCER;
-      htim->Instance->CCER &= ~TIM_CCER_CC1E;
-      tmpccmr1 = htim->Instance->CCMR1;
-
-      /* Set the filter */
-      tmpccmr1 &= ~TIM_CCMR1_IC1F;
-      tmpccmr1 |= ((sSlaveConfig->TriggerFilter) << 4);
-
-      /* Write to TIMx CCMR1 and CCER registers */
-      htim->Instance->CCMR1 = tmpccmr1;
-      htim->Instance->CCER = tmpccer;
-
-    }
-    break;
-
-  case TIM_TS_TI1FP1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI1 Filter and Polarity */
-      TIM_TI1_ConfigInputStage(htim->Instance,
-                               sSlaveConfig->TriggerPolarity,
-                               sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_TI2FP2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-      assert_param(IS_TIM_TRIGGERPOLARITY(sSlaveConfig->TriggerPolarity));
-      assert_param(IS_TIM_TRIGGERFILTER(sSlaveConfig->TriggerFilter));
-
-      /* Configure TI2 Filter and Polarity */
-      TIM_TI2_ConfigInputStage(htim->Instance,
-                                sSlaveConfig->TriggerPolarity,
-                                sSlaveConfig->TriggerFilter);
-    }
-    break;
-
-  case TIM_TS_ITR0:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR1:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR2:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  case TIM_TS_ITR3:
-    {
-      /* Check the parameter */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-    }
-    break;
-
-  default:
-    break;
-  }
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Read the captured value from Capture Compare unit
-  * @param  htim: TIM handle.
-  * @param  Channel : TIM Channels to be enabled
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @retval Captured value
-  */
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel)
-{
-  uint32_t tmpreg = 0;
-
-  __HAL_LOCK(htim);
-
-  switch (Channel)
-  {
-  case TIM_CHANNEL_1:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC1_INSTANCE(htim->Instance));
-
-      /* Return the capture 1 value */
-      tmpreg =  htim->Instance->CCR1;
-
-      break;
-    }
-  case TIM_CHANNEL_2:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC2_INSTANCE(htim->Instance));
-
-      /* Return the capture 2 value */
-      tmpreg =   htim->Instance->CCR2;
-
-      break;
-    }
-
-  case TIM_CHANNEL_3:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC3_INSTANCE(htim->Instance));
-
-      /* Return the capture 3 value */
-      tmpreg =   htim->Instance->CCR3;
-
-      break;
-    }
-
-  case TIM_CHANNEL_4:
-    {
-      /* Check the parameters */
-      assert_param(IS_TIM_CC4_INSTANCE(htim->Instance));
-
-      /* Return the capture 4 value */
-      tmpreg =   htim->Instance->CCR4;
-
-      break;
-    }
-
-  default:
-    break;
-  }
-
-  __HAL_UNLOCK(htim);
-  return tmpreg;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group9 TIM Callbacks functions
- *  @brief    TIM Callbacks functions
- *
-@verbatim
-  ==============================================================================
-                        ##### TIM Callbacks functions #####
-  ==============================================================================
- [..]
-   This section provides TIM callback functions:
-   (+) Timer Period elapsed callback
-   (+) Timer Output Compare callback
-   (+) Timer Input capture callback
-   (+) Timer Trigger callback
-   (+) Timer Error callback
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Period elapsed callback in non blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_PeriodElapsedCallback could be implemented in the user file
-   */
-
-}
-/**
-  * @brief  Output Compare callback in non blocking mode
-  * @param  htim : TIM OC handle
-  * @retval None
-  */
-__weak void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_OC_DelayElapsedCallback could be implemented in the user file
-   */
-}
-/**
-  * @brief  Input Capture callback in non blocking mode
-  * @param  htim : TIM IC handle
-  * @retval None
-  */
-__weak void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_IC_CaptureCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  PWM Pulse finished callback in non blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the __HAL_TIM_PWM_PulseFinishedCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Hall Trigger detection callback in non blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_TriggerCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Timer error callback in non blocking mode
-  * @param  htim : TIM handle
-  * @retval None
-  */
-__weak void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim)
-{
-  /* NOTE : This function Should not be modified, when the callback is needed,
-            the HAL_TIM_ErrorCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions
- *  @brief   Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================
-    [..]
-    This subsection permit to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Return the TIM Base state
-  * @param  htim: TIM Base handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM OC state
-  * @param  htim: TIM Ouput Compare handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM PWM state
-  * @param  htim: TIM handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Input Capture state
-  * @param  htim: TIM IC handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM One Pulse Mode state
-  * @param  htim: TIM OPM handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @brief  Return the TIM Encoder Mode state
-  * @param  htim: TIM Encoder handle
-  * @retval HAL state
-  */
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim)
-{
-  return htim->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-
-/** @addtogroup TIM_Private_Functions
-  * @{
-  */
-
-
-/**
-  * @brief  TIM DMA error callback
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMAError(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_ErrorCallback(htim);
-}
-
-/**
-  * @brief  TIM DMA Delay Pulse complete callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-
-  HAL_TIM_PWM_PulseFinishedCallback(htim);
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Capture complete callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  if (hdma == htim->hdma[TIM_DMA_ID_CC1])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_1;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC2])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC3])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_3;
-  }
-  else if (hdma == htim->hdma[TIM_DMA_ID_CC4])
-  {
-    htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
-  }
-
-  HAL_TIM_IC_CaptureCallback(htim);
-
-  htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
-}
-
-/**
-  * @brief  TIM DMA Period Elapse complete callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_PeriodElapsedCallback(htim);
-}
-
-/**
-  * @brief  TIM DMA Trigger callback.
-  * @param  hdma : pointer to DMA handle.
-  * @retval None
-  */
-static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma)
-{
-  TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  htim->State= HAL_TIM_STATE_READY;
-
-  HAL_TIM_TriggerCallback(htim);
-}
-
-/**
-  * @brief  Time Base configuration
-  * @param  TIMx: TIM periheral
-  * @param  Structure: TIM Base configuration structure
-  * @retval None
-  */
-static void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
-{
-  uint32_t tmpcr1 = 0;
-  tmpcr1 = TIMx->CR1;
-
-  /* Set TIM Time Base Unit parameters ---------------------------------------*/
-  if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
-  {
-    /* Select the Counter Mode */
-    tmpcr1 &= ~(TIM_CR1_DIR | TIM_CR1_CMS);
-    tmpcr1 |= Structure->CounterMode;
-  }
-
-  if(IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
-  {
-    /* Set the clock division */
-    tmpcr1 &= ~TIM_CR1_CKD;
-    tmpcr1 |= (uint32_t)Structure->ClockDivision;
-  }
-
-  TIMx->CR1 = tmpcr1;
-
-  /* Set the Autoreload value */
-  TIMx->ARR = (uint32_t)Structure->Period ;
-
-  /* Set the Prescaler value */
-  TIMx->PSC = (uint32_t)Structure->Prescaler;
-
-  /* Generate an update event to reload the Prescaler
-     and the repetition counter(only for TIM1 and TIM8) value immediatly */
-  TIMx->EGR = TIM_EGR_UG;
-}
-
-/**
-  * @brief  Time Ouput Compare 1 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-   /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare Mode Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC1M;
-  tmpccmrx &= ~TIM_CCMR1_CC1S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC1P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= OC_Config->OCPolarity;
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR1 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Ouput Compare 2 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-static void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR1 register value */
-  tmpccmrx = TIMx->CCMR1;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR1_OC2M;
-  tmpccmrx &= ~TIM_CCMR1_CC2S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC2P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 4);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR1 */
-  TIMx->CCMR1 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR2 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Ouput Compare 3 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 3: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC3M;
-  tmpccmrx &= ~TIM_CCMR2_CC3S;
-  /* Select the Output Compare Mode */
-  tmpccmrx |= OC_Config->OCMode;
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC3P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 8);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR3 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Time Ouput Compare 4 configuration
-  * @param  TIMx to select the TIM peripheral
-  * @param  OC_Config: The ouput configuration structure
-  * @retval None
-  */
-static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
-{
-  uint32_t tmpccmrx = 0;
-  uint32_t tmpccer = 0;
-  uint32_t tmpcr2 = 0;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-
-  /* Get the TIMx CCER register value */
-  tmpccer = TIMx->CCER;
-  /* Get the TIMx CR2 register value */
-  tmpcr2 =  TIMx->CR2;
-
-  /* Get the TIMx CCMR2 register value */
-  tmpccmrx = TIMx->CCMR2;
-
-  /* Reset the Output Compare mode and Capture/Compare selection Bits */
-  tmpccmrx &= ~TIM_CCMR2_OC4M;
-  tmpccmrx &= ~TIM_CCMR2_CC4S;
-
-  /* Select the Output Compare Mode */
-  tmpccmrx |= (OC_Config->OCMode << 8);
-
-  /* Reset the Output Polarity level */
-  tmpccer &= ~TIM_CCER_CC4P;
-  /* Set the Output Compare Polarity */
-  tmpccer |= (OC_Config->OCPolarity << 12);
-
-  /* Write to TIMx CR2 */
-  TIMx->CR2 = tmpcr2;
-
-  /* Write to TIMx CCMR2 */
-  TIMx->CCMR2 = tmpccmrx;
-
-  /* Set the Capture Compare Register value */
-  TIMx->CCR4 = OC_Config->Pulse;
-
-  /* Write to TIMx CCER */
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI1 as Input.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING
-  *            @arg TIM_ICPOLARITY_FALLING
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI:    TIM Input 1 is selected to be connected to IC1.
-  *            @arg TIM_ICSELECTION_INDIRECTTI:  TIM Input 1 is selected to be connected to IC2.
-  *            @arg TIM_ICSELECTION_TRC:         TIM Input 1 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  if(IS_TIM_CC2_INSTANCE(TIMx) != RESET)
-  {
-    tmpccmr1 &= ~TIM_CCMR1_CC1S;
-    tmpccmr1 |= TIM_ICSelection;
-  }
-  else
-  {
-    tmpccmr1 |= TIM_CCMR1_CC1S_0;
-  }
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= (TIM_ICFilter << 4);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= TIM_ICPolarity;
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI1.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING   
-  *            @arg TIM_ICPOLARITY_FALLING  
-  *            @arg TIM_ICPOLARITY_BOTHEDGE 
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI1_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 1: Reset the CC1E Bit */
-  tmpccer = TIMx->CCER;
-  TIMx->CCER &= ~TIM_CCER_CC1E;
-  tmpccmr1 = TIMx->CCMR1;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC1F;
-  tmpccmr1 |= (TIM_ICFilter << 4);
-
-  /* Select the Polarity and set the CC1E Bit */
-  tmpccer &= ~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
-  tmpccer |= TIM_ICPolarity;
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI2 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING   
-  *            @arg TIM_ICPOLARITY_FALLING  
-  *            @arg TIM_ICPOLARITY_BOTHEDGE 
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 2 is selected to be connected to IC2.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 2 is selected to be connected to IC1.
-  *            @arg TIM_ICSELECTION_TRC:        TIM Input 2 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI2_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr1 &= ~TIM_CCMR1_CC2S;
-  tmpccmr1 |= (TIM_ICSelection << 8);
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= (TIM_ICFilter << 12);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (TIM_ICPolarity << 4);
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the Polarity and Filter for TI2.
-  * @param  TIMx to select the TIM peripheral.
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING  
-  *            @arg TIM_ICPOLARITY_FALLING 
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI2_ConfigInputStage(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr1 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 2: Reset the CC2E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC2E;
-  tmpccmr1 = TIMx->CCMR1;
-  tmpccer = TIMx->CCER;
-
-  /* Set the filter */
-  tmpccmr1 &= ~TIM_CCMR1_IC2F;
-  tmpccmr1 |= (TIM_ICFilter << 12);
-
-  /* Select the Polarity and set the CC2E Bit */
-  tmpccer &= ~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
-  tmpccer |= (TIM_ICPolarity << 4);
-
-  /* Write to TIMx CCMR1 and CCER registers */
-  TIMx->CCMR1 = tmpccmr1 ;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI3 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING  
-  *            @arg TIM_ICPOLARITY_FALLING 
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 3 is selected to be connected to IC3.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 3 is selected to be connected to IC4.
-  *            @arg TIM_ICSELECTION_TRC:        TIM Input 3 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI3_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 3: Reset the CC3E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC3E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC3S;
-  tmpccmr2 |= TIM_ICSelection;
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC3F;
-  tmpccmr2 |= (TIM_ICFilter << 4);
-
-  /* Select the Polarity and set the CC3E Bit */
-  tmpccer &= ~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
-  tmpccer |= (TIM_ICPolarity << 8);
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer;
-}
-
-/**
-  * @brief  Configure the TI4 as Input.
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ICPolarity : The Input Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPOLARITY_RISING  
-  *            @arg TIM_ICPOLARITY_FALLING 
-  *            @arg TIM_ICPOLARITY_BOTHEDGE
-  * @param  TIM_ICSelection: specifies the input to be used.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICSELECTION_DIRECTTI:   TIM Input 4 is selected to be connected to IC4.
-  *            @arg TIM_ICSELECTION_INDIRECTTI: TIM Input 4 is selected to be connected to IC3.
-  *            @arg TIM_ICSELECTION_TRC:        TIM Input 4 is selected to be connected to TRC.
-  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
-  *          This parameter must be a value between 0x00 and 0x0F.
-  * @retval None
-  */
-static void TIM_TI4_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection,
-                       uint32_t TIM_ICFilter)
-{
-  uint32_t tmpccmr2 = 0;
-  uint32_t tmpccer = 0;
-
-  /* Disable the Channel 4: Reset the CC4E Bit */
-  TIMx->CCER &= ~TIM_CCER_CC4E;
-  tmpccmr2 = TIMx->CCMR2;
-  tmpccer = TIMx->CCER;
-
-  /* Select the Input */
-  tmpccmr2 &= ~TIM_CCMR2_CC4S;
-  tmpccmr2 |= (TIM_ICSelection << 8);
-
-  /* Set the filter */
-  tmpccmr2 &= ~TIM_CCMR2_IC4F;
-  tmpccmr2 |= (TIM_ICFilter << 12);
-
-  /* Select the Polarity and set the CC4E Bit */
-  tmpccer &= ~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
-  tmpccer |= (TIM_ICPolarity << 12);
-
-  /* Write to TIMx CCMR2 and CCER registers */
-  TIMx->CCMR2 = tmpccmr2;
-  TIMx->CCER = tmpccer ;
-}
-
-/**
-  * @brief  Selects the Input Trigger source
-  * @param  TIMx to select the TIM peripheral
-  * @param  InputTriggerSource: The Input Trigger source.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_TS_ITR0: Internal Trigger 0
-  *            @arg TIM_TS_ITR1: Internal Trigger 1
-  *            @arg TIM_TS_ITR2: Internal Trigger 2
-  *            @arg TIM_TS_ITR3: Internal Trigger 3
-  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
-  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
-  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
-  *            @arg TIM_TS_ETRF: External Trigger input
-  * @retval None
-  */
-static void TIM_ITRx_SetConfig(TIM_TypeDef *TIMx, uint16_t InputTriggerSource)
-{
-  uint32_t tmpsmcr = 0;
-
-   /* Get the TIMx SMCR register value */
-   tmpsmcr = TIMx->SMCR;
-   /* Reset the TS Bits */
-   tmpsmcr &= ~TIM_SMCR_TS;
-   /* Set the Input Trigger source and the slave mode*/
-   tmpsmcr |= InputTriggerSource | TIM_SLAVEMODE_EXTERNAL1;
-   /* Write to TIMx SMCR */
-   TIMx->SMCR = tmpsmcr;
-}
-/**
-  * @brief  Configures the TIMx External Trigger (ETR).
-  * @param  TIMx to select the TIM peripheral
-  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPRESCALER_DIV1: ETRP Prescaler OFF.
-  *            @arg TIM_ETRPRESCALER_DIV2: ETRP frequency divided by 2.
-  *            @arg TIM_ETRPRESCALER_DIV4: ETRP frequency divided by 4.
-  *            @arg TIM_ETRPRESCALER_DIV8: ETRP frequency divided by 8.
-  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ETRPOLARITY_INVERTED: active low or falling edge active.
-  *            @arg TIM_ETRPOLARITY_NONINVERTED: active high or rising edge active.
-  * @param  ExtTRGFilter: External Trigger Filter.
-  *          This parameter must be a value between 0x00 and 0x0F
-  * @retval None
-  */
-static void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler,
-                       uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter)
-{
-  uint32_t tmpsmcr = 0;
-
-  tmpsmcr = TIMx->SMCR;
-
-  /* Reset the ETR Bits */
-  tmpsmcr &= (uint32_t)(~(TIM_SMCR_ETF | TIM_SMCR_ETPS | TIM_SMCR_ECE | TIM_SMCR_ETP));
-
-  /* Set the Prescaler, the Filter value and the Polarity */
-  tmpsmcr |= (uint32_t)(TIM_ExtTRGPrescaler | (TIM_ExtTRGPolarity | (ExtTRGFilter << 8)));
-
-  /* Write to TIMx SMCR */
-  TIMx->SMCR = tmpsmcr;
-}
-
-/**
-  * @brief  Enables or disables the TIM Capture Compare Channel x.
-  * @param  TIMx to select the TIM peripheral
-  * @param  Channel: specifies the TIM Channel
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1
-  *            @arg TIM_CHANNEL_2: TIM Channel 2
-  *            @arg TIM_CHANNEL_3: TIM Channel 3
-  *            @arg TIM_CHANNEL_4: TIM Channel 4
-  * @param  ChannelState: specifies the TIM Channel CCxE bit new state.
-  *          This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
-  * @retval None
-  */
-static void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState)
-{
-  uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_TIM_CC1_INSTANCE(TIMx));
-  assert_param(IS_TIM_CHANNELS(Channel));
-
-  tmp = (uint16_t)(TIM_CCER_CC1E << Channel);
-
-  /* Reset the CCxE Bit */
-  TIMx->CCER &= ~tmp;
-
-  /* Set or reset the CCxE Bit */
-  TIMx->CCER |=  (uint32_t)(ChannelState << Channel);
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1508 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_tim.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of TIM HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_TIM_H
-#define __STM32L1xx_HAL_TIM_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIM
-  * @{
-  */
-
-/* Exported types ------------------------------------------------------------*/
-/** @defgroup TIM_Exported_Types TIM Exported Types
-  * @{
-  */
-/**
-  * @brief  TIM Time base Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t CounterMode;       /*!< Specifies the counter mode.
-                                   This parameter can be a value of @ref TIM_Counter_Mode */
-
-  uint32_t Period;            /*!< Specifies the period value to be loaded into the active
-                                   Auto-Reload Register at the next update event.
-                                   This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.  */
-
-  uint32_t ClockDivision;     /*!< Specifies the clock division.
-                                   This parameter can be a value of @ref TIM_ClockDivision */
-
-} TIM_Base_InitTypeDef;
-
-/**
-  * @brief  TIM Output Compare Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCFastMode;   /*!< Specifies the Fast mode state.
-                               This parameter can be a value of @ref TIM_Output_Fast_State
-                               @note This parameter is valid only in PWM1 and PWM2 mode. */
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-} TIM_OC_InitTypeDef;
-
-/**
-  * @brief  TIM One Pulse Mode Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t OCMode;        /*!< Specifies the TIM mode.
-                               This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
-
-  uint32_t Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
-                               This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
-
-  uint32_t OCPolarity;    /*!< Specifies the output polarity.
-                               This parameter can be a value of @ref TIM_Output_Compare_Polarity */
-
-  uint32_t OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
-                               This parameter can be a value of @ref TIM_Output_Compare_Idle_State
-                               @note This parameter is valid only for TIM1 and TIM8. */
-
-  uint32_t ICPolarity;    /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;   /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICFilter;      /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_OnePulse_InitTypeDef;
-
-
-/**
-  * @brief  TIM Input Capture Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t  ICPolarity;  /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t ICSelection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
-                              This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t ICFilter;     /*!< Specifies the input capture filter.
-                              This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_IC_InitTypeDef;
-
-/**
-  * @brief  TIM Encoder Configuration Structure definition
-  */
-typedef struct
-{
-  uint32_t EncoderMode;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Encoder_Mode */
-
-  uint32_t IC1Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC1Selection;  /*!< Specifies the input.
-                               This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC1Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC1Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-  uint32_t IC2Polarity;   /*!< Specifies the active edge of the input signal.
-                               This parameter can be a value of @ref TIM_Input_Capture_Polarity */
-
-  uint32_t IC2Selection;  /*!< Specifies the input.
-                              This parameter can be a value of @ref TIM_Input_Capture_Selection */
-
-  uint32_t IC2Prescaler;  /*!< Specifies the Input Capture Prescaler.
-                               This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
-
-  uint32_t IC2Filter;     /*!< Specifies the input capture filter.
-                               This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-} TIM_Encoder_InitTypeDef;
-
-
-/**
-  * @brief  Clock Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClockSource;     /*!< TIM clock sources
-                                 This parameter can be a value of @ref TIM_Clock_Source */
-  uint32_t ClockPolarity;   /*!< TIM clock polarity
-                                 This parameter can be a value of @ref TIM_Clock_Polarity */
-  uint32_t ClockPrescaler;  /*!< TIM clock prescaler
-                                 This parameter can be a value of @ref TIM_Clock_Prescaler */
-  uint32_t ClockFilter;     /*!< TIM clock filter
-                                This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClockConfigTypeDef;
-
-/**
-  * @brief  Clear Input Configuration Handle Structure definition
-  */
-typedef struct
-{
-  uint32_t ClearInputState;      /*!< TIM clear Input state
-                                      This parameter can be ENABLE or DISABLE */
-  uint32_t ClearInputSource;     /*!< TIM clear Input sources
-                                      This parameter can be a value of @ref TIM_ClearInput_Source */
-  uint32_t ClearInputPolarity;   /*!< TIM Clear Input polarity
-                                      This parameter can be a value of @ref TIM_ClearInput_Polarity */
-  uint32_t ClearInputPrescaler;  /*!< TIM Clear Input prescaler
-                                      This parameter can be a value of @ref TIM_ClearInput_Prescaler */
-  uint32_t ClearInputFilter;     /*!< TIM Clear Input filter
-                                     This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-}TIM_ClearInputConfigTypeDef;
-
-/**
-  * @brief  TIM Slave configuration Structure definition
-  */
-typedef struct {
-  uint32_t  SlaveMode;         /*!< Slave mode selection
-                                  This parameter can be a value of @ref TIM_Slave_Mode */
-  uint32_t  InputTrigger;      /*!< Input Trigger source
-                                  This parameter can be a value of @ref TIM_Trigger_Selection */
-  uint32_t  TriggerPolarity;   /*!< Input Trigger polarity
-                                  This parameter can be a value of @ref TIM_Trigger_Polarity */
-  uint32_t  TriggerPrescaler;  /*!< Input trigger prescaler
-                                  This parameter can be a value of @ref TIM_Trigger_Prescaler */
-  uint32_t  TriggerFilter;     /*!< Input trigger filter
-                                  This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
-
-}TIM_SlaveConfigTypeDef;
-
-/**
-  * @brief  HAL State structures definition
-  */
-typedef enum
-{
-  HAL_TIM_STATE_RESET             = 0x00,    /*!< Peripheral not yet initialized or disabled  */
-  HAL_TIM_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use    */
-  HAL_TIM_STATE_BUSY              = 0x02,    /*!< An internal process is ongoing              */
-  HAL_TIM_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                               */
-  HAL_TIM_STATE_ERROR             = 0x04     /*!< Reception process is ongoing                */
-}HAL_TIM_StateTypeDef;
-
-/**
-  * @brief  HAL Active channel structures definition
-  */
-typedef enum
-{
-  HAL_TIM_ACTIVE_CHANNEL_1        = 0x01,    /*!< The active channel is 1     */
-  HAL_TIM_ACTIVE_CHANNEL_2        = 0x02,    /*!< The active channel is 2     */
-  HAL_TIM_ACTIVE_CHANNEL_3        = 0x04,    /*!< The active channel is 3     */
-  HAL_TIM_ACTIVE_CHANNEL_4        = 0x08,    /*!< The active channel is 4     */
-  HAL_TIM_ACTIVE_CHANNEL_CLEARED  = 0x00     /*!< All active channels cleared */
-}HAL_TIM_ActiveChannel;
-
-/**
-  * @brief  TIM Time Base Handle Structure definition
-  */
-typedef struct
-{
-  TIM_TypeDef              *Instance;     /*!< Register base address             */
-  TIM_Base_InitTypeDef     Init;          /*!< TIM Time Base required parameters */
-  HAL_TIM_ActiveChannel    Channel;       /*!< Active channel                    */
-  DMA_HandleTypeDef        *hdma[7];      /*!< DMA Handlers array
-                                             This array is accessed by a @ref DMA_Handle_index */
-  HAL_LockTypeDef          Lock;          /*!< Locking object                    */
-  __IO HAL_TIM_StateTypeDef   State;      /*!< TIM operation state               */
-}TIM_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIM_Exported_Constants TIM Exported Constants
-  * @{
-  */
-
-/** @defgroup TIM_Input_Channel_Polarity TIM_Input_Channel_Polarity
-  * @{
-  */
-#define  TIM_INPUTCHANNELPOLARITY_RISING      ((uint32_t)0x00000000)            /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_FALLING     (TIM_CCER_CC1P)                   /*!< Polarity for TIx source */
-#define  TIM_INPUTCHANNELPOLARITY_BOTHEDGE    (TIM_CCER_CC1P | TIM_CCER_CC1NP)  /*!< Polarity for TIx source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Polarity TIM_ETR_Polarity
-  * @{
-  */
-#define TIM_ETRPOLARITY_INVERTED              (TIM_SMCR_ETP)                    /*!< Polarity for ETR source */
-#define TIM_ETRPOLARITY_NONINVERTED           ((uint32_t)0x0000)                /*!< Polarity for ETR source */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ETR_Prescaler TIM_ETR_Prescaler
-  * @{
-  */
-#define TIM_ETRPRESCALER_DIV1                 ((uint32_t)0x0000)                /*!< No prescaler is used */
-#define TIM_ETRPRESCALER_DIV2                 (TIM_SMCR_ETPS_0)                 /*!< ETR input source is divided by 2 */
-#define TIM_ETRPRESCALER_DIV4                 (TIM_SMCR_ETPS_1)                 /*!< ETR input source is divided by 4 */
-#define TIM_ETRPRESCALER_DIV8                 (TIM_SMCR_ETPS)                   /*!< ETR input source is divided by 8 */
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Counter_Mode TIM_Counter_Mode
-  * @{
-  */
-#define TIM_COUNTERMODE_UP                 ((uint32_t)0x0000)
-#define TIM_COUNTERMODE_DOWN               TIM_CR1_DIR
-#define TIM_COUNTERMODE_CENTERALIGNED1     TIM_CR1_CMS_0
-#define TIM_COUNTERMODE_CENTERALIGNED2     TIM_CR1_CMS_1
-#define TIM_COUNTERMODE_CENTERALIGNED3     TIM_CR1_CMS
-
-#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP)              || \
-                                   ((MODE) == TIM_COUNTERMODE_DOWN)            || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED1)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED2)  || \
-                                   ((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClockDivision TIM_ClockDivision
-  * @{
-  */
-#define TIM_CLOCKDIVISION_DIV1                       ((uint32_t)0x0000)
-#define TIM_CLOCKDIVISION_DIV2                       (TIM_CR1_CKD_0)
-#define TIM_CLOCKDIVISION_DIV4                       (TIM_CR1_CKD_1)
-
-#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV2) || \
-                                       ((DIV) == TIM_CLOCKDIVISION_DIV4))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_and_PWM_modes TIM_Output_Compare_and_PWM_modes
-  * @{
-  */
-#define TIM_OCMODE_TIMING                   ((uint32_t)0x0000)
-#define TIM_OCMODE_ACTIVE                   (TIM_CCMR1_OC1M_0)
-#define TIM_OCMODE_INACTIVE                 (TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_TOGGLE                   (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1)
-#define TIM_OCMODE_PWM1                     (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_PWM2                     (TIM_CCMR1_OC1M)
-#define TIM_OCMODE_FORCED_ACTIVE            (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2)
-#define TIM_OCMODE_FORCED_INACTIVE          (TIM_CCMR1_OC1M_2)
-
-#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) || \
-                               ((MODE) == TIM_OCMODE_PWM2))
-
-#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING)       || \
-                          ((MODE) == TIM_OCMODE_ACTIVE)           || \
-                          ((MODE) == TIM_OCMODE_INACTIVE)         || \
-                          ((MODE) == TIM_OCMODE_TOGGLE)           || \
-                          ((MODE) == TIM_OCMODE_FORCED_ACTIVE)    || \
-                          ((MODE) == TIM_OCMODE_FORCED_INACTIVE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_State TIM_Output_Compare_State
-  * @{
-  */
-#define TIM_OUTPUTSTATE_DISABLE            ((uint32_t)0x0000)
-#define TIM_OUTPUTSTATE_ENABLE             (TIM_CCER_CC1E)
-
-#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
-                                    ((STATE) == TIM_OUTPUTSTATE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Fast_State TIM_Output_Fast_State
-  * @{
-  */
-#define TIM_OCFAST_DISABLE                ((uint32_t)0x0000)
-#define TIM_OCFAST_ENABLE                 (TIM_CCMR1_OC1FE)
-
-#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) || \
-                                  ((STATE) == TIM_OCFAST_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Polarity TIM_Output_Compare_Polarity
-  * @{
-  */
-#define TIM_OCPOLARITY_HIGH                ((uint32_t)0x0000)
-#define TIM_OCPOLARITY_LOW                 (TIM_CCER_CC1P)
-
-#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) || \
-                                      ((POLARITY) == TIM_OCPOLARITY_LOW))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Output_Compare_Idle_State TIM_Output_Compare_Idle_State
-  * @{
-  */
-#define TIM_OCIDLESTATE_SET                (TIM_CR2_OIS1)
-#define TIM_OCIDLESTATE_RESET              ((uint32_t)0x0000)
-#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIDLESTATE_SET) || \
-                                    ((STATE) == TIM_OCIDLESTATE_RESET))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Channel TIM_Channel
-  * @{
-  */
-#define TIM_CHANNEL_1                      ((uint32_t)0x0000)
-#define TIM_CHANNEL_2                      ((uint32_t)0x0004)
-#define TIM_CHANNEL_3                      ((uint32_t)0x0008)
-#define TIM_CHANNEL_4                      ((uint32_t)0x000C)
-#define TIM_CHANNEL_ALL                    ((uint32_t)0x0018)
-
-#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                  ((CHANNEL) == TIM_CHANNEL_2) || \
-                                  ((CHANNEL) == TIM_CHANNEL_3) || \
-                                  ((CHANNEL) == TIM_CHANNEL_4) || \
-                                  ((CHANNEL) == TIM_CHANNEL_ALL))
-
-#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                       ((CHANNEL) == TIM_CHANNEL_2))
-
-#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) || \
-                                      ((CHANNEL) == TIM_CHANNEL_2))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Polarity TIM_Input_Capture_Polarity
-  * @{
-  */
-#define  TIM_ICPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING
-#define  TIM_ICPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING
-#define  TIM_ICPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE
-
-#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING)   || \
-                                      ((POLARITY) == TIM_ICPOLARITY_FALLING)  || \
-                                      ((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Selection TIM_Input_Capture_Selection
-  * @{
-  */
-#define TIM_ICSELECTION_DIRECTTI           (TIM_CCMR1_CC1S_0)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                               connected to IC1, IC2, IC3 or IC4, respectively */
-#define TIM_ICSELECTION_INDIRECTTI         (TIM_CCMR1_CC1S_1)   /*!< TIM Input 1, 2, 3 or 4 is selected to be
-                                                                               connected to IC2, IC1, IC4 or IC3, respectively */
-#define TIM_ICSELECTION_TRC                (TIM_CCMR1_CC1S)     /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
-
-#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) || \
-                                        ((SELECTION) == TIM_ICSELECTION_INDIRECTTI) || \
-                                        ((SELECTION) == TIM_ICSELECTION_TRC))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Prescaler TIM_Input_Capture_Prescaler
-  * @{
-  */
-#define TIM_ICPSC_DIV1                     ((uint32_t)0x0000)       /*!< Capture performed each time an edge is detected on the capture input */
-#define TIM_ICPSC_DIV2                     (TIM_CCMR1_IC1PSC_0)     /*!< Capture performed once every 2 events */
-#define TIM_ICPSC_DIV4                     (TIM_CCMR1_IC1PSC_1)     /*!< Capture performed once every 4 events */
-#define TIM_ICPSC_DIV8                     (TIM_CCMR1_IC1PSC)       /*!< Capture performed once every 8 events */
-
-#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
-                                        ((PRESCALER) == TIM_ICPSC_DIV8))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_One_Pulse_Mode TIM_One_Pulse_Mode
-  * @{
-  */
-#define TIM_OPMODE_SINGLE                  (TIM_CR1_OPM)
-#define TIM_OPMODE_REPETITIVE              ((uint32_t)0x0000)
-
-#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) || \
-                               ((MODE) == TIM_OPMODE_REPETITIVE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Encoder_Mode TIM_Encoder_Mode
-  * @{
-  */
-#define TIM_ENCODERMODE_TI1                (TIM_SMCR_SMS_0)
-#define TIM_ENCODERMODE_TI2                (TIM_SMCR_SMS_1)
-#define TIM_ENCODERMODE_TI12               (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
-
-#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI2) || \
-                                   ((MODE) == TIM_ENCODERMODE_TI12))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Interrupt_definition TIM_Interrupt_definition
-  * @{
-  */
-#define TIM_IT_UPDATE           (TIM_DIER_UIE)
-#define TIM_IT_CC1              (TIM_DIER_CC1IE)
-#define TIM_IT_CC2              (TIM_DIER_CC2IE)
-#define TIM_IT_CC3              (TIM_DIER_CC3IE)
-#define TIM_IT_CC4              (TIM_DIER_CC4IE)
-#define TIM_IT_TRIGGER          (TIM_DIER_TIE)
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_sources TIM_DMA_sources
-  * @{
-  */
-#define TIM_DMA_UPDATE                     (TIM_DIER_UDE)
-#define TIM_DMA_CC1                        (TIM_DIER_CC1DE)
-#define TIM_DMA_CC2                        (TIM_DIER_CC2DE)
-#define TIM_DMA_CC3                        (TIM_DIER_CC3DE)
-#define TIM_DMA_CC4                        (TIM_DIER_CC4DE)
-#define TIM_DMA_TRIGGER                    (TIM_DIER_TDE)
-
-#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFF80FF) == 0x00000000) && ((SOURCE) != 0x00000000))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Event_Source TIM_Event_Source
-  * @{
-  */
-#define TIM_EventSource_Update              TIM_EGR_UG
-#define TIM_EventSource_CC1                 TIM_EGR_CC1G
-#define TIM_EventSource_CC2                 TIM_EGR_CC2G
-#define TIM_EventSource_CC3                 TIM_EGR_CC3G
-#define TIM_EventSource_CC4                 TIM_EGR_CC4G
-#define TIM_EventSource_Trigger             TIM_EGR_TG
-
-#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFF00) == 0x00000000) && ((SOURCE) != 0x00000000))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Flag_definition TIM_Flag_definition
-  * @{
-  */
-#define TIM_FLAG_UPDATE                    (TIM_SR_UIF)
-#define TIM_FLAG_CC1                       (TIM_SR_CC1IF)
-#define TIM_FLAG_CC2                       (TIM_SR_CC2IF)
-#define TIM_FLAG_CC3                       (TIM_SR_CC3IF)
-#define TIM_FLAG_CC4                       (TIM_SR_CC4IF)
-#define TIM_FLAG_TRIGGER                   (TIM_SR_TIF)
-#define TIM_FLAG_CC1OF                     (TIM_SR_CC1OF)
-#define TIM_FLAG_CC2OF                     (TIM_SR_CC2OF)
-#define TIM_FLAG_CC3OF                     (TIM_SR_CC3OF)
-#define TIM_FLAG_CC4OF                     (TIM_SR_CC4OF)
-
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Source TIM_Clock_Source
-  * @{
-  */
-#define  TIM_CLOCKSOURCE_ETRMODE2    (TIM_SMCR_ETPS_1)
-#define  TIM_CLOCKSOURCE_INTERNAL    (TIM_SMCR_ETPS_0)
-#define  TIM_CLOCKSOURCE_ITR0        ((uint32_t)0x0000)
-#define  TIM_CLOCKSOURCE_ITR1        (TIM_SMCR_TS_0)
-#define  TIM_CLOCKSOURCE_ITR2        (TIM_SMCR_TS_1)
-#define  TIM_CLOCKSOURCE_ITR3        (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
-#define  TIM_CLOCKSOURCE_TI1ED       (TIM_SMCR_TS_2)
-#define  TIM_CLOCKSOURCE_TI1         (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
-#define  TIM_CLOCKSOURCE_TI2         (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
-#define  TIM_CLOCKSOURCE_ETRMODE1    (TIM_SMCR_TS)
-
-#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR0)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR1)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR2)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ITR3)     || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1ED)    || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI1)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_TI2)      || \
-                                   ((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Polarity TIM_Clock_Polarity
-  * @{
-  */
-#define TIM_CLOCKPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED           /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED        /*!< Polarity for ETRx clock sources */
-#define TIM_CLOCKPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING    /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING   /*!< Polarity for TIx clock sources */
-#define TIM_CLOCKPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE  /*!< Polarity for TIx clock sources */
-
-#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED)    || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_RISING)      || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_FALLING)     || \
-                                        ((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Prescaler TIM_Clock_Prescaler
-  * @{
-  */
-#define TIM_CLOCKPRESCALER_DIV1                 TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_CLOCKPRESCALER_DIV2                 TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
-#define TIM_CLOCKPRESCALER_DIV4                 TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
-#define TIM_CLOCKPRESCALER_DIV8                 TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
-
-#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) || \
-                                          ((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Clock_Filter TIM_Clock_Filter
-  * @{
-  */
-#define IS_TIM_CLOCKFILTER(ICFILTER)      ((ICFILTER) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Source TIM_ClearInput_Source
-  * @{
-  */
-#define TIM_CLEARINPUTSOURCE_ETR            ((uint32_t)0x0001) 
-#define TIM_CLEARINPUTSOURCE_OCREFCLR       ((uint32_t)0x0002) 
-#define TIM_CLEARINPUTSOURCE_NONE           ((uint32_t)0x0000)
-
-#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_ETR)      || \
-                                          ((SOURCE) == TIM_CLEARINPUTSOURCE_OCREFCLR) || \
-                                          ((SOURCE) == TIM_CLEARINPUTSOURCE_NONE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Polarity TIM_ClearInput_Polarity
-  * @{
-  */
-#define TIM_CLEARINPUTPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED               /*!< Polarity for ETRx pin */
-#define TIM_CLEARINPUTPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED            /*!< Polarity for ETRx pin */
-
-
-#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
-                                              ((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Prescaler TIM_ClearInput_Prescaler
-  * @{
-  */
-#define TIM_CLEARINPUTPRESCALER_DIV1                    TIM_ETRPRESCALER_DIV1      /*!< No prescaler is used */
-#define TIM_CLEARINPUTPRESCALER_DIV2                    TIM_ETRPRESCALER_DIV2      /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV4                    TIM_ETRPRESCALER_DIV4      /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
-#define TIM_CLEARINPUTPRESCALER_DIV8                    TIM_ETRPRESCALER_DIV8      /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
-
-#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER)   (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) || \
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) || \
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) || \
-                                                  ((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_ClearInput_Filter TIM_ClearInput_Filter
-  * @{
-  */
-#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM_OSSR_Off_State_Selection_for_Run_mode_state
-  * @{
-  */
-#define TIM_OSSR_ENABLE         (TIM_BDTR_OSSR)
-#define TIM_OSSR_DISABLE              ((uint32_t)0x0000)
-
-#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSR_ENABLE) || \
-                                  ((STATE) == TIM_OSSR_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM_OSSI_Off_State_Selection_for_Idle_mode_state
-  * @{
-  */
-#define TIM_OSSI_ENABLE         (TIM_BDTR_OSSI)
-#define TIM_OSSI_DISABLE            ((uint32_t)0x0000)
-
-#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSI_ENABLE) || \
-                                  ((STATE) == TIM_OSSI_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Lock_level TIM_Lock_level
-  * @{
-  */
-#define TIM_LOCKLEVEL_OFF     ((uint32_t)0x0000)
-#define TIM_LOCKLEVEL_1            (TIM_BDTR_LOCK_0)
-#define TIM_LOCKLEVEL_2            (TIM_BDTR_LOCK_1)
-#define TIM_LOCKLEVEL_3            (TIM_BDTR_LOCK)
-
-#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLEVEL_OFF) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_1) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_2) || \
-                                  ((LEVEL) == TIM_LOCKLEVEL_3))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_AOE_Bit_Set_Reset TIM_AOE_Bit_Set_Reset
-  * @{
-  */
-#define TIM_AUTOMATICOUTPUT_ENABLE           (TIM_BDTR_AOE)
-#define  TIM_AUTOMATICOUTPUT_DISABLE          ((uint32_t)0x0000)
-
-#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AUTOMATICOUTPUT_ENABLE) || \
-                                              ((STATE) == TIM_AUTOMATICOUTPUT_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Mode_Selection TIM_Master_Mode_Selection
-  * @{
-  */
-#define  TIM_TRGO_RESET            ((uint32_t)0x0000)
-#define  TIM_TRGO_ENABLE           (TIM_CR2_MMS_0)
-#define  TIM_TRGO_UPDATE           (TIM_CR2_MMS_1)
-#define  TIM_TRGO_OC1              ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-#define  TIM_TRGO_OC1REF           (TIM_CR2_MMS_2)
-#define  TIM_TRGO_OC2REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
-#define  TIM_TRGO_OC3REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
-#define  TIM_TRGO_OC4REF           ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
-
-#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) || \
-                                    ((SOURCE) == TIM_TRGO_ENABLE) || \
-                                    ((SOURCE) == TIM_TRGO_UPDATE) || \
-                                    ((SOURCE) == TIM_TRGO_OC1) || \
-                                    ((SOURCE) == TIM_TRGO_OC1REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC2REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC3REF) || \
-                                    ((SOURCE) == TIM_TRGO_OC4REF))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Slave_Mode TIM_Slave_Mode
-  * @{
-  */
-#define TIM_SLAVEMODE_DISABLE              ((uint32_t)0x0000)
-#define TIM_SLAVEMODE_RESET                ((uint32_t)0x0004)
-#define TIM_SLAVEMODE_GATED                ((uint32_t)0x0005)
-#define TIM_SLAVEMODE_TRIGGER              ((uint32_t)0x0006)
-#define TIM_SLAVEMODE_EXTERNAL1            ((uint32_t)0x0007)
-
-#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) || \
-                                 ((MODE) == TIM_SLAVEMODE_GATED) || \
-                                 ((MODE) == TIM_SLAVEMODE_RESET) || \
-                                 ((MODE) == TIM_SLAVEMODE_TRIGGER) || \
-                                 ((MODE) == TIM_SLAVEMODE_EXTERNAL1))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Master_Slave_Mode TIM_Master_Slave_Mode
-  * @{
-  */
-#define TIM_MASTERSLAVEMODE_ENABLE          ((uint32_t)0x0080)
-#define TIM_MASTERSLAVEMODE_DISABLE         ((uint32_t)0x0000)
-
-#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) || \
-                                 ((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Selection TIM_Trigger_Selection
-  * @{
-  */
-#define TIM_TS_ITR0                        ((uint32_t)0x0000)
-#define TIM_TS_ITR1                        ((uint32_t)0x0010)
-#define TIM_TS_ITR2                        ((uint32_t)0x0020)
-#define TIM_TS_ITR3                        ((uint32_t)0x0030)
-#define TIM_TS_TI1F_ED                     ((uint32_t)0x0040)
-#define TIM_TS_TI1FP1                      ((uint32_t)0x0050)
-#define TIM_TS_TI2FP2                      ((uint32_t)0x0060)
-#define TIM_TS_ETRF                        ((uint32_t)0x0070)
-#define TIM_TS_NONE                        ((uint32_t)0xFFFF)
-
-#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                             ((SELECTION) == TIM_TS_ITR1) || \
-                                             ((SELECTION) == TIM_TS_ITR2) || \
-                                             ((SELECTION) == TIM_TS_ITR3) || \
-                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
-                                             ((SELECTION) == TIM_TS_TI1FP1) || \
-                                             ((SELECTION) == TIM_TS_TI2FP2) || \
-                                             ((SELECTION) == TIM_TS_ETRF))
-
-#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                      ((SELECTION) == TIM_TS_ITR1) || \
-                                                      ((SELECTION) == TIM_TS_ITR2) || \
-                                                      ((SELECTION) == TIM_TS_ITR3))
-
-#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
-                                                           ((SELECTION) == TIM_TS_ITR1) || \
-                                                           ((SELECTION) == TIM_TS_ITR2) || \
-                                                           ((SELECTION) == TIM_TS_ITR3) || \
-                                                           ((SELECTION) == TIM_TS_NONE))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Polarity TIM_Trigger_Polarity
-  * @{
-  */
-#define TIM_TRIGGERPOLARITY_INVERTED           TIM_ETRPOLARITY_INVERTED            /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_NONINVERTED        TIM_ETRPOLARITY_NONINVERTED         /*!< Polarity for ETRx trigger sources */
-#define TIM_TRIGGERPOLARITY_RISING             TIM_INPUTCHANNELPOLARITY_RISING     /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_FALLING            TIM_INPUTCHANNELPOLARITY_FALLING    /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-#define TIM_TRIGGERPOLARITY_BOTHEDGE           TIM_INPUTCHANNELPOLARITY_BOTHEDGE   /*!< Polarity for TIxFPx or TI1_ED trigger sources */
-
-#define IS_TIM_TRIGGERPOLARITY(POLARITY)     (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED   ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_RISING     ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_FALLING    ) || \
-                                              ((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE   ))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Prescaler TIM_Trigger_Prescaler
-  * @{
-  */
-#define TIM_TRIGGERPRESCALER_DIV1             TIM_ETRPRESCALER_DIV1     /*!< No prescaler is used */
-#define TIM_TRIGGERPRESCALER_DIV2             TIM_ETRPRESCALER_DIV2     /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
-#define TIM_TRIGGERPRESCALER_DIV4             TIM_ETRPRESCALER_DIV4     /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
-#define TIM_TRIGGERPRESCALER_DIV8             TIM_ETRPRESCALER_DIV8     /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
-
-#define IS_TIM_TRIGGERPRESCALER(PRESCALER)  (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) || \
-                                             ((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Trigger_Filter TIM_Trigger_Filter
-  * @{
-  */
-#define IS_TIM_TRIGGERFILTER(ICFILTER)     ((ICFILTER) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup TIM_TI1_Selection TIM_TI1_Selection
-  * @{
-  */
-#define TIM_TI1SELECTION_CH1                ((uint32_t)0x0000)
-#define TIM_TI1SELECTION_XORCOMBINATION     (TIM_CR2_TI1S)
-
-#define IS_TIM_TI1SELECTION(TI1SELECTION)   (((TI1SELECTION) == TIM_TI1SELECTION_CH1) || \
-                                             ((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Base_address TIM_DMA_Base_address
-  * @{
-  */
-#define TIM_DMABase_CR1                    (0x00000000)
-#define TIM_DMABase_CR2                    (0x00000001)
-#define TIM_DMABase_SMCR                   (0x00000002)
-#define TIM_DMABase_DIER                   (0x00000003)
-#define TIM_DMABase_SR                     (0x00000004)
-#define TIM_DMABase_EGR                    (0x00000005)
-#define TIM_DMABase_CCMR1                  (0x00000006)
-#define TIM_DMABase_CCMR2                  (0x00000007)
-#define TIM_DMABase_CCER                   (0x00000008)
-#define TIM_DMABase_CNT                    (0x00000009)
-#define TIM_DMABase_PSC                    (0x0000000A)
-#define TIM_DMABase_ARR                    (0x0000000B)
-#define TIM_DMABase_CCR1                   (0x0000000D)
-#define TIM_DMABase_CCR2                   (0x0000000E)
-#define TIM_DMABase_CCR3                   (0x0000000F)
-#define TIM_DMABase_CCR4                   (0x00000010)
-#define TIM_DMABase_DCR                    (0x00000012)
-#define TIM_DMABase_OR                     (0x00000013)
-
-#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1)   || \
-                               ((BASE) == TIM_DMABase_CR2)   || \
-                               ((BASE) == TIM_DMABase_SMCR)  || \
-                               ((BASE) == TIM_DMABase_DIER)  || \
-                               ((BASE) == TIM_DMABase_SR)    || \
-                               ((BASE) == TIM_DMABase_EGR)   || \
-                               ((BASE) == TIM_DMABase_CCMR1) || \
-                               ((BASE) == TIM_DMABase_CCMR2) || \
-                               ((BASE) == TIM_DMABase_CCER)  || \
-                               ((BASE) == TIM_DMABase_CNT)   || \
-                               ((BASE) == TIM_DMABase_PSC)   || \
-                               ((BASE) == TIM_DMABase_ARR)   || \
-                               ((BASE) == TIM_DMABase_CCR1)  || \
-                               ((BASE) == TIM_DMABase_CCR2)  || \
-                               ((BASE) == TIM_DMABase_CCR3)  || \
-                               ((BASE) == TIM_DMABase_CCR4)  || \
-                               ((BASE) == TIM_DMABase_DCR)   || \
-                               ((BASE) == TIM_DMABase_OR))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_DMA_Burst_Length TIM_DMA_Burst_Length
-  * @{
-  */
-#define TIM_DMABurstLength_1Transfer           (0x00000000)
-#define TIM_DMABurstLength_2Transfers          (0x00000100)
-#define TIM_DMABurstLength_3Transfers          (0x00000200)
-#define TIM_DMABurstLength_4Transfers          (0x00000300)
-#define TIM_DMABurstLength_5Transfers          (0x00000400)
-#define TIM_DMABurstLength_6Transfers          (0x00000500)
-#define TIM_DMABurstLength_7Transfers          (0x00000600)
-#define TIM_DMABurstLength_8Transfers          (0x00000700)
-#define TIM_DMABurstLength_9Transfers          (0x00000800)
-#define TIM_DMABurstLength_10Transfers         (0x00000900)
-#define TIM_DMABurstLength_11Transfers         (0x00000A00)
-#define TIM_DMABurstLength_12Transfers         (0x00000B00)
-#define TIM_DMABurstLength_13Transfers         (0x00000C00)
-#define TIM_DMABurstLength_14Transfers         (0x00000D00)
-#define TIM_DMABurstLength_15Transfers         (0x00000E00)
-#define TIM_DMABurstLength_16Transfers         (0x00000F00)
-#define TIM_DMABurstLength_17Transfers         (0x00001000)
-#define TIM_DMABurstLength_18Transfers         (0x00001100)
-
-#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
-                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
-                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
-/**
-  * @}
-  */
-
-/** @defgroup TIM_Input_Capture_Filer_Value TIM_Input_Capture_Filer_Value
-  * @{
-  */
-#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
-/**
-  * @}
-  */
-
-/** @defgroup DMA_Handle_index DMA_Handle_index
-  * @{
-  */
-#define TIM_DMA_ID_UPDATE                ((uint16_t) 0x0)       /*!< Index of the DMA handle used for Update DMA requests */
-#define TIM_DMA_ID_CC1                   ((uint16_t) 0x1)       /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
-#define TIM_DMA_ID_CC2                   ((uint16_t) 0x2)       /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
-#define TIM_DMA_ID_CC3                   ((uint16_t) 0x3)       /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
-#define TIM_DMA_ID_CC4                   ((uint16_t) 0x4)       /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
-#define TIM_DMA_ID_TRIGGER               ((uint16_t) 0x6)       /*!< Index of the DMA handle used for Trigger DMA requests */
-/**
-  * @}
-  */
-
-/** @defgroup Channel_CC_State Channel_CC_State
-  * @{
-  */
-#define TIM_CCx_ENABLE                   ((uint32_t)0x0001)
-#define TIM_CCx_DISABLE                  ((uint32_t)0x0000)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Private Constants -----------------------------------------------------------*/
-/** @defgroup TIM_Private_Constants TIM_Private_Constants
-  * @{
-  */
-
-/* The counter of a timer instance is disabled only if all the CCx
-   channels have been disabled */
-#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-/**
-  * @}
-  */
-
-
-
-/* Exported macros -----------------------------------------------------------*/
-/** @defgroup TIM_Exported_Macros TIM Exported Macros
-  * @{
-  */
-
-/** @brief  Reset TIM handle state
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
- */
-#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
-
-/**
-  * @brief  Enable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
- */
-#define __HAL_TIM_ENABLE(__HANDLE__)                 ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
-
-/**
-  * @brief  Disable the TIM peripheral.
-  * @param  __HANDLE__: TIM handle
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE(__HANDLE__) \
-                        do { \
-                          if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
-                          { \
-                              (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
-                          } \
-                        } while(0)
-
-/**
-  * @brief  Enable the specified TIM interrupt.
-  * @param  __HANDLE__: TIM handle
-  * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. 
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__)    ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-
-/**
-  * @brief  Enable the specified DMA Channel.
-  * @param  __HANDLE__: TIM handle
-  * @param __DMA__: specifies the DMA Channel to be enabled or disabled. 
-  * @retval None
-  */
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__)         ((__HANDLE__)->Instance->DIER |= (__DMA__))
-
-/**
-  * @brief  Disable the specified TIM interrupt.
-  * @param  __HANDLE__: TIM handle
-  * @param __INTERRUPT__: specifies the TIM interrupt sources to be enabled or disabled. 
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Disable the specified DMA Channel.
-  * @param  __HANDLE__: TIM handle
-  * @param __DMA__: specifies the DMA Channel to be enabled or disabled. 
-  * @retval None
-  */
-#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__)        ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
-
-/**
-  * @brief  Get the TIM Channel pending flags.
-  * @param  __HANDLE__: TIM handle
-  * @param  __FLAG__: Get the specified flag.
-  * @retval The state of FLAG (SET or RESET).
-  */
-#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__)          (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clear the TIM Channel pending flags.
-  * @param  __HANDLE__: TIM handle
-  * @param  __FLAG__: specifies the flag to clear.
-  * @retval None
-  */
-#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__)        ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/**
-  * @brief  Checks whether the specified TIM interrupt has occurred or not.
-  * @param  __HANDLE__: TIM handle
-  * @param  __INTERRUPT__: specifies the TIM interrupt source to check.
-  * @retval The state of TIM_IT (SET or RESET).
-  */
-#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
-
-/** @brief Clear the TIM interrupt pending bits
-  * @param  __HANDLE__: TIM handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  * @retval None
-  */
-#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__)     ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
-
-/** @brief TIM counter direction
-  * @param  __HANDLE__: TIM handle
-  */
-#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__)            (((__HANDLE__)->Instance->CR1 & (TIM_CR1_DIR)) == (TIM_CR1_DIR))
-
-/** @brief Set TIM prescaler
-  * @param  __HANDLE__: TIM handle
-  * @param  __PRESC__: specifies the prescaler value.
-  * @retval None
-  */
-#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__)        ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-/** @brief Set TIM IC prescaler
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
-  * @param  __ICPSC__: specifies the prescaler value.
-  * @retval None
-  */
-#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-
-/** @brief Reset TIM IC prescaler
-  * @param  __HANDLE__: TIM handle
-  * @param  __CHANNEL__: specifies TIM Channel
-  * @retval None
-  */
-#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-
-/**
-  * @brief  Sets the TIM Capture Compare Register value on runtime without
-  *         calling another time ConfigChannel function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __COMPARE__: specifies the Capture Compare register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
-(*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
-
-/**
-  * @brief  Gets the TIM Capture Compare Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channel associated with the capture compare register
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get capture/compare 1 register value
-  *            @arg TIM_CHANNEL_2: get capture/compare 2 register value
-  *            @arg TIM_CHANNEL_3: get capture/compare 3 register value
-  *            @arg TIM_CHANNEL_4: get capture/compare 4 register value
-  * @retval None
-  */
-#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
-  (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
-
-/**
-  * @brief  Sets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __COUNTER__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__)  ((__HANDLE__)->Instance->CNT = (__COUNTER__))
-
-/**
-  * @brief  Gets the TIM Counter Register value on runtime.
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GetCounter(__HANDLE__) \
-   ((__HANDLE__)->Instance->CNT)
-
-/**
-  * @brief  Sets the TIM Autoreload Register value on runtime without calling
-  *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __AUTORELOAD__: specifies the Counter register new value.
-  * @retval None
-  */
-#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
-                        do{                                                    \
-                              (__HANDLE__)->Instance->ARR = (__AUTORELOAD__);  \
-                              (__HANDLE__)->Init.Period = (__AUTORELOAD__);    \
-                          } while(0)
-
-/**
-  * @brief  Gets the TIM Autoreload Register value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GetAutoreload(__HANDLE__) \
-   ((__HANDLE__)->Instance->ARR)
-
-/**
-  * @brief  Sets the TIM Clock Division value on runtime without calling
-  *         another time any Init function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CKD__: specifies the clock division value.
-  *          This parameter can be one of the following value:
-  *            @arg TIM_CLOCKDIVISION_DIV1
-  *            @arg TIM_CLOCKDIVISION_DIV2
-  *            @arg TIM_CLOCKDIVISION_DIV4
-  * @retval None
-  */
-#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
-                        do{                                                    \
-                              (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD);  \
-                              (__HANDLE__)->Instance->CR1 |= (__CKD__);                   \
-                              (__HANDLE__)->Init.ClockDivision = (__CKD__);             \
-                          } while(0)
-
-/**
-  * @brief  Gets the TIM Clock Division value on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @retval None
-  */
-#define __HAL_TIM_GetClockDivision(__HANDLE__)  \
-   ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
-
-/**
-  * @brief  Sets the TIM Input Capture prescaler on runtime without calling
-  *         another time HAL_TIM_IC_ConfigChannel() function.
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: TIM Channel 1 selected
-  *            @arg TIM_CHANNEL_2: TIM Channel 2 selected
-  *            @arg TIM_CHANNEL_3: TIM Channel 3 selected
-  *            @arg TIM_CHANNEL_4: TIM Channel 4 selected
-  * @param  __ICPSC__: specifies the Input Capture4 prescaler new value.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_ICPSC_DIV1: no prescaler
-  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
-  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
-  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
-  * @retval None
-  */
-#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
-                        do{                                                    \
-                              __HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__));  \
-                              __HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
-                          } while(0)
-
-/**
-  * @brief  Gets the TIM Input Capture prescaler on runtime
-  * @param  __HANDLE__: TIM handle.
-  * @param  __CHANNEL__ : TIM Channels to be configured.
-  *          This parameter can be one of the following values:
-  *            @arg TIM_CHANNEL_1: get input capture 1 prescaler value
-  *            @arg TIM_CHANNEL_2: get input capture 2 prescaler value
-  *            @arg TIM_CHANNEL_3: get input capture 3 prescaler value
-  *            @arg TIM_CHANNEL_4: get input capture 4 prescaler value
-  * @retval None
-  */
-#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__)  \
-  (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
-   ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
-   ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
-   (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
-
-/**
-  * @}
-  */
-
-/* Include TIM HAL Extension module */
-#include "stm32l1xx_hal_tim_ex.h"
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIM_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group1
-  * @{
-  */
-/* Time Base functions ********************************************************/
-HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group2
-  * @{
-  */
-/* Timer Output Compare functions **********************************************/
-HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group3
-  * @{
-  */
-/* Timer PWM functions *********************************************************/
-HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group4
-  * @{
-  */
-/* Timer Input Capture functions ***********************************************/
-HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
-HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group5
-  * @{
-  */
-/* Timer One Pulse functions ***************************************************/
-HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
-HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
-/* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group6
-  * @{
-  */
-/* Timer Encoder functions *****************************************************/
-HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim,  TIM_Encoder_InitTypeDef* sConfig);
-HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
-void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
- /* Blocking mode: Polling */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: Interrupt */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
-/* Non-Blocking mode: DMA */
-HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
-HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group7
-  * @{
-  */
-/* Interrupt Handler functions  **********************************************/
-void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group8
-  * @{
-  */
-/* Control functions  *********************************************************/
-HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel,  uint32_t InputChannel);
-HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
-HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
-HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
-HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
-                                              uint32_t  *BurstBuffer, uint32_t  BurstLength);
-HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
-HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
-uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
-
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group9
-  * @{
-  */
-/* Callback in non blocking modes (Interrupt and DMA) *************************/
-void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
-void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
-/**
-  * @}
-  */
-
-/** @addtogroup TIM_Exported_Functions_Group10
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
-HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_TIM_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,260 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_tim_ex.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   TIM HAL module driver.
-  *          This file provides firmware functions to manage the following
-  *          functionalities of the Timer extension peripheral:
-  *           + Time Master and Slave synchronization configuration
-  *           + Timer remapping capabilities configuration
-  @verbatim
-  ==============================================================================
-                      ##### TIMER Extended features #####
-  ==============================================================================
-  [..]
-    The Timer Extension features include:
-    (#) Synchronization circuit to control the timer with external signals and to
-        interconnect several timers together.
-    (#) Timer remapping capabilities configuration
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-*/
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup TIMEx TIMEx
-  * @brief TIM HAL module driver
-  * @{
-  */
-
-#ifdef HAL_TIM_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup TIMEx_Exported_Functions TIMEx Exported Functions
-  * @{
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group1 Peripheral Control functions
- *  @brief   	Peripheral Control functions
- *
-@verbatim
-  ==============================================================================
-                    ##### Peripheral Control functions #####
-  ==============================================================================
-  [..]
-    This section provides functions allowing to:
-    (+) Configure the commutation event in case of use of the Hall sensor interface.
-      (+) Configure Complementary channels, break features and dead time.
-      (+) Configure Master synchronization.
-      (+) Configure timer remapping capabilities.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Configures the TIM in master mode.
-  * @param  htim: TIM handle.
-  * @param  sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
-  *         contains the selected trigger output (TRGO) and the Master/Slave
-  *         mode.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig)
-{
-  /* Check the parameters */
-  assert_param(IS_TIM_MASTER_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_TRGO_SOURCE(sMasterConfig->MasterOutputTrigger));
-  assert_param(IS_TIM_MSM_STATE(sMasterConfig->MasterSlaveMode));
-
-  __HAL_LOCK(htim);
-
-  htim->State = HAL_TIM_STATE_BUSY;
-
-  /* Reset the MMS Bits */
-  htim->Instance->CR2 &= ~TIM_CR2_MMS;
-  /* Select the TRGO source */
-  htim->Instance->CR2 |=  sMasterConfig->MasterOutputTrigger;
-
-  /* Reset the MSM Bit */
-  htim->Instance->SMCR &= ~TIM_SMCR_MSM;
-  /* Set or Reset the MSM Bit */
-  htim->Instance->SMCR |= sMasterConfig->MasterSlaveMode;
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  Configures the TIM2/TIM3/TIM9/TIM10/TIM11 Remapping input capabilities.
-  * @param  htim: TIM handle.
-  * @param  Remap: specifies the TIM remapping source.
-  *         This parameter is a combination of the following values depending on TIM instance.
-  *
-  *         For TIM2, the parameter can have the following values:
-  *            @arg TIM_TIM2_ITR1_TIM10_OC:      TIM2 ITR1 input is connected to TIM10 OC
-  *            @arg TIM_TIM2_ITR1_TIM5_TGO:      TIM2 ITR1 input is connected to TIM5 TGO
-  *
-  *         For TIM3, the parameter can have the following values:
-  *            @arg TIM_TIM3_ITR2_TIM11_OC:      TIM3 ITR2 input is connected to TIM11 OC
-  *            @arg TIM_TIM3_ITR2_TIM5_TGO:      TIM3 ITR2 input is connected to TIM5 TGO
-  *
-  *         For TIM9, the parameter is a combination of 2 fields (field1 | field2):
-  *                   field1 can have the following values:
-  *            @arg TIM_TIM9_ITR1_TIM3_TGO:      TIM9 ITR1 input is connected to TIM3 TGO
-  *            @arg TIM_TIM9_ITR1_TS:            TIM9 ITR1 input is connected to touch sensing I/O
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM9_GPIO:               TIM9 Channel1 is connected to GPIO
-  *            @arg TIM_TIM9_LSE:                TIM9 Channel1 is connected to LSE internal clock
-  *            @arg TIM_TIM9_GPIO1:              TIM9 Channel1 is connected to GPIO
-  *            @arg TIM_TIM9_GPIO2:              TIM9 Channel1 is connected to GPIO
-  *
-  *         For TIM10, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *                   field1 can have the following values:
-  *            @arg TIM_TIM10_TI1RMP:            TIM10 Channel 1 depends on TI1_RMP
-  *            @arg TIM_TIM10_RI:                TIM10 Channel 1 is connected to RI
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM10_ETR_LSE:           TIM10 ETR input is connected to LSE clock
-  *            @arg TIM_TIM10_ETR_TIM9_TGO:      TIM10 ETR input is connected to TIM9 TGO
-  *                   field3 can have the following values:
-  *            @arg TIM_TIM10_GPIO:              TIM10 Channel1 is connected to GPIO
-  *            @arg TIM_TIM10_LSI:               TIM10 Channel1 is connected to LSI internal clock
-  *            @arg TIM_TIM10_LSE:               TIM10 Channel1 is connected to LSE internal clock
-  *            @arg TIM_TIM10_RTC:               TIM10 Channel1 is connected to RTC wakeup interrupt
-  *
-  *         For TIM11, the parameter is a combination of 3 fields (field1 | field2 | field3):
-  *                   field1 can have the following values:
-  *            @arg TIM_TIM11_TI1RMP:            TIM11 Channel 1 depends on TI1_RMP
-  *            @arg TIM_TIM11_RI:                TIM11 Channel 1 is connected to RI
-  *                   field2 can have the following values:
-  *            @arg TIM_TIM11_ETR_LSE:           TIM11 ETR input is connected to LSE clock
-  *            @arg TIM_TIM11_ETR_TIM9_TGO:      TIM11 ETR input is connected to TIM9 TGO 
-  *                   field3 can have the following values:
-  *            @arg TIM_TIM11_GPIO:     TIM11 Channel1 is connected to GPIO           
-  *            @arg TIM_TIM11_MSI:      TIM11 Channel1 is connected to MSI internal clock
-  *            @arg TIM_TIM11_HSE_RTC:  TIM11 Channel1 is connected to HSE_RTC clock
-  *            @arg TIM_TIM11_GPIO1:    TIM11 Channel1 is connected to GPIO
-  *
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap)
-{
-  __HAL_LOCK(htim);
-
-  /* Check parameters */
-  assert_param(IS_TIM_REMAP_INSTANCE(htim->Instance));
-  assert_param(IS_TIM_REMAP(htim->Instance,Remap));
-
-  /* Set the Timer remapping configuration */
-  htim->Instance->OR = Remap;
-
-  htim->State = HAL_TIM_STATE_READY;
-
-  __HAL_UNLOCK(htim);
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group2 Extension Callbacks functions
- *  @brief   Extension Callbacks functions
- *
-@verbatim
-  ==============================================================================
-                    ##### Extension Callbacks functions #####
-  ==============================================================================
-  [..]
-    This section provides Extension TIM callback functions:
-    (+) Timer Commutation callback
-    (+) Timer Break callback
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @}
-  */
-
-/** @defgroup TIMEx_Exported_Functions_Group3 Extension Peripheral State functions
- *  @brief   Extension Peripheral State functions
- *
-@verbatim
-  ==============================================================================
-                ##### Extension Peripheral State functions #####
-  ==============================================================================
-  [..]
-    This subsection permit to get in run-time the status of the peripheral
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-
-/**
-  * @}
-  */
-
-#endif /* HAL_TIM_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_tim_ex.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,212 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_tim_ex.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of TIM HAL Extension module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_TIM_EX_H
-#define __STM32L1xx_HAL_TIM_EX_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup TIMEx
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup TIMEx_Exported_Types TIMEx Exported Types
-  * @{
-  */
-
-/** 
-  * @brief  TIM Master configuration Structure definition  
-  */ 
-typedef struct {
-  uint32_t  MasterOutputTrigger;   /*!< Trigger output (TRGO) selection 
-                                      This parameter can be a value of @ref TIM_Master_Mode_Selection */ 
-  uint32_t  MasterSlaveMode;       /*!< Master/slave mode selection 
-                                      This parameter can be a value of @ref TIM_Master_Slave_Mode */
-}TIM_MasterConfigTypeDef;
-
-/**
-  * @}
-  */
-
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup TIMEx_Exported_Constants TIMEx_Exported_Constants
-  * @{
-  */
-    
-/** @defgroup TIMEx_Remap TIMEx_Remap
-  * @{
-  */
-
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define TIM_TIM2_ITR1_TIM10_OC        (0x00000000)       /* !< TIM2 ITR1 input is connected to TIM10 OC */
-#define TIM_TIM2_ITR1_TIM5_TGO        TIM2_OR_ITR1_RMP   /* !< TIM2 ITR1 input is connected to TIM5 TGO */
-#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */
-
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define TIM_TIM3_ITR2_TIM11_OC        (0x00000000)       /* !< TIM3 ITR2 input is connected to TIM11 OC */
-#define TIM_TIM3_ITR2_TIM5_TGO        TIM2_OR_ITR1_RMP   /* !< TIM3 ITR2 input is connected to TIM5 TGO */
-#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */
-
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define TIM_TIM9_ITR1_TIM3_TGO        (0x00000000)       /* !< TIM9 ITR1 input is connected to TIM3 TGO */
-#define TIM_TIM9_ITR1_TS              TIM9_OR_ITR1_RMP   /* !< TIM9 ITR1 input is connected to touch sensing I/O */
-#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */
-#define TIM_TIM9_GPIO                 (0x00000000)       /* !< TIM9 Channel1 is connected to GPIO */
-#define TIM_TIM9_LSE                  TIM_OR_TI1RMP_0    /* !< TIM9 Channel1 is connected to LSE internal clock */
-#define TIM_TIM9_GPIO1                TIM_OR_TI1RMP_1    /* !< TIM9 Channel1 is connected to GPIO */
-#define TIM_TIM9_GPIO2                TIM_OR_TI1RMP      /* !< TIM9 Channel1 is connected to GPIO */
-
-
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define TIM_TIM10_TI1RMP              (0x00000000)       /* !< TIM10 Channel 1 depends on TI1_RMP */
-#define TIM_TIM10_RI                  TIM_OR_TI1_RMP_RI  /* !< TIM10 Channel 1 is connected to RI */
-#define TIM_TIM10_ETR_LSE             (0x00000000)       /* !< TIM10 ETR input is connected to LSE clock */
-#define TIM_TIM10_ETR_TIM9_TGO        TIM_OR_ETR_RMP     /* !< TIM10 ETR input is connected to TIM9 TGO */
-#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */
-#define TIM_TIM10_GPIO                (0x00000000) /* !< TIM10 Channel1 is connected to GPIO */
-#define TIM_TIM10_LSI                 TIM_OR_TI1RMP_0    /* !< TIM10 Channel1 is connected to LSI internal clock */
-#define TIM_TIM10_LSE                 TIM_OR_TI1RMP_1    /* !< TIM10 Channel1 is connected to LSE internal clock */
-#define TIM_TIM10_RTC                 TIM_OR_TI1RMP      /* !< TIM10 Channel1 is connected to RTC wakeup interrupt */
-
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define TIM_TIM11_TI1RMP              (0x00000000)       /* !< TIM11 Channel 1 depends on TI1_RMP */
-#define TIM_TIM11_RI                  TIM_OR_TI1_RMP_RI  /* !< TIM11 Channel 1 is connected to RI */
-#define TIM_TIM11_ETR_LSE             (0x00000000)       /* !< TIM11 ETR input is connected to LSE clock */
-#define TIM_TIM11_ETR_TIM9_TGO        TIM_OR_ETR_RMP     /* !< TIM11 ETR input is connected to TIM9 TGO */
-#endif /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */
-#define TIM_TIM11_GPIO                (0x00000000)       /* !< TIM11 Channel1 is connected to GPIO */
-#define TIM_TIM11_MSI                 TIM_OR_TI1RMP_0    /* !< TIM11 Channel1 is connected to MSI internal clock */
-#define TIM_TIM11_HSE_RTC             TIM_OR_TI1RMP_1    /* !< TIM11 Channel1 is connected to HSE_RTC clock */
-#define TIM_TIM11_GPIO1               TIM_OR_TI1RMP      /* !< TIM11 Channel1 is connected to GPIO */
-
-
-#if defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE)
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)               \
-        ( (((INSTANCE) == TIM2)  && (((TIM_REMAP) == TIM_TIM2_ITR1_TIM10_OC) || ((TIM_REMAP) == TIM_TIM2_ITR1_TIM5_TGO)))  || \
-          (((INSTANCE) == TIM3)  && (((TIM_REMAP) == TIM_TIM3_ITR2_TIM11_OC) || ((TIM_REMAP) == TIM_TIM3_ITR2_TIM5_TGO)))  || \
-          (((INSTANCE) == TIM9)  && ((TIM_REMAP) <= (TIM_TIM9_ITR1_TS | TIM_TIM9_GPIO2)))                                  || \
-          (((INSTANCE) == TIM10) && ((TIM_REMAP) <= (TIM_TIM10_RI | TIM_TIM10_ETR_TIM9_TGO | TIM_TIM10_RTC)))              || \
-          (((INSTANCE) == TIM11) && ((TIM_REMAP) <= (TIM_TIM11_RI | TIM_TIM11_ETR_TIM9_TGO | TIM_TIM11_GPIO1)))               \
-        )
-#else /* defined (STM32L100xC) || defined (STM32L151xC) || defined (STM32L152xC) || defined (STM32L162xC) || defined (STM32L151xCA) || defined (STM32L151xD) || defined (STM32L152xCA) || defined (STM32L152xD) || defined (STM32L162xCA) || defined (STM32L162xD) || defined (STM32L151xE) || defined (STM32L152xE) || defined (STM32L162xE) */
-#define IS_TIM_REMAP(INSTANCE, TIM_REMAP)               \
-        ( (((INSTANCE) == TIM9)  && (((TIM_REMAP) == TIM_TIM9_GPIO) || ((TIM_REMAP) == TIM_TIM9_LSE) || ((TIM_REMAP) == TIM_TIM9_GPIO1) || ((TIM_REMAP) == TIM_TIM9_GPIO2)))       || \
-          (((INSTANCE) == TIM10) && (((TIM_REMAP) == TIM_TIM10_GPIO) || ((TIM_REMAP) == TIM_TIM10_LSI) || ((TIM_REMAP) == TIM_TIM10_LSE) || ((TIM_REMAP) == TIM_TIM10_RTC)))       || \
-          (((INSTANCE) == TIM11) && (((TIM_REMAP) == TIM_TIM11_GPIO) || ((TIM_REMAP) == TIM_TIM11_MSI) || ((TIM_REMAP) == TIM_TIM11_HSE_RTC) || ((TIM_REMAP) == TIM_TIM11_GPIO1)))    \
-        )
-#endif 
-
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/* Exported macro ------------------------------------------------------------*/
-
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup TIMEx_Exported_Functions
-  * @{
-  */ 
-
-/** @addtogroup TIMEx_Exported_Functions_Group1
-  * @{
-  */
-/* Extension Control functions  ************************************************/
-HAL_StatusTypeDef HAL_TIMEx_MasterConfigSynchronization(TIM_HandleTypeDef *htim, TIM_MasterConfigTypeDef * sMasterConfig);
-HAL_StatusTypeDef HAL_TIMEx_RemapConfig(TIM_HandleTypeDef *htim, uint32_t Remap);
-/**
-  * @}
-  */
-  
-/** @addtogroup TIMEx_Exported_Functions_Group2
-  * @{
-  */
-
-/**
-  * @}
-  */
-
-/* Extension Callback *********************************************************/
-
-/** @addtogroup TIMEx_Exported_Functions_Group3
-  * @{
-  */
-
-/**
-  * @}
-  */
-/* Extension Peripheral State functions  **************************************/
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-
-#endif /* __STM32L1xx_HAL_TIM_EX_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1974 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_uart.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   UART HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State and Errors functions  
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The UART HAL driver can be used as follows:
-    
-    (#) Declare a UART_HandleTypeDef handle structure.
-
-    (#) Initialize the UART low level resources by implementing the HAL_UART_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) UART pins configuration:
-            (+++) Enable the clock for the UART GPIOs.
-            (+++) Configure these UART pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_UART_Transmit_IT()
-             and HAL_UART_Receive_IT() APIs):
-            (+++) Configure the USARTx interrupt priority.
-            (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_UART_Transmit_DMA()
-             and HAL_UART_Receive_DMA() APIs):
-            (+++) Declare a DMA handle structure for the Tx/Rx channel.
-            (+++) Enable the DMAx interface clock.
-            (+++) Configure the declared DMA handle structure with the required 
-                  Tx/Rx parameters.                
-            (+++) Configure the DMA Tx/Rx channel.
-            (+++) Associate the initialized DMA handle to the UART DMA Tx/Rx handle.
-            (+++) Configure the priority and enable the NVIC for the transfer complete 
-                  interrupt on the DMA Tx/Rx channel.
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware 
-        flow control and Mode(Receiver/Transmitter) in the huart Init structure.
-
-    (#) For the UART asynchronous mode, initialize the UART registers by calling
-        the HAL_UART_Init() API.
-    
-    (#) For the UART Half duplex mode, initialize the UART registers by calling 
-        the HAL_HalfDuplex_Init() API.
-    
-    (#) For the LIN mode, initialize the UART registers by calling the HAL_LIN_Init() API.
-    
-    (#) For the Multi-Processor mode, initialize the UART registers by calling 
-        the HAL_MultiProcessor_Init() API.
-        
-     [..] 
-       (@) The specific UART interrupts (Transmission complete interrupt, 
-            RXNE interrupt and Error Interrupts) will be managed using the macros
-            __HAL_UART_ENABLE_IT() and __HAL_UART_DISABLE_IT() inside the transmit 
-            and receive process.
-          
-     [..] 
-       (@) These APIs (HAL_UART_Init() and HAL_HalfDuplex_Init()) configure also the 
-            low level Hardware GPIO, CLOCK, CORTEX...etc) by calling the customed 
-            HAL_UART_MspInit() API.
-          
-     [..] 
-        Three operation modes are available within this driver :     
-  
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Send an amount of data in blocking mode using HAL_UART_Transmit() 
-       (+) Receive an amount of data in blocking mode using HAL_UART_Receive()
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Send an amount of data in non blocking mode using HAL_UART_Transmit_IT() 
-       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback 
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_UART_Receive_IT() 
-       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback 
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-
-     *** DMA mode IO operation ***    
-     ==============================
-     [..] 
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_UART_Transmit_DMA() 
-       (+) At transmission end of half transfer HAL_UART_TxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_TxHalfCpltCallback 
-       (+) At transmission end of transfer HAL_UART_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_UART_Receive_DMA() 
-       (+) At reception end of half transfer HAL_UART_RxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxHalfCpltCallback 
-       (+) At reception end of transfer HAL_UART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_UART_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_UART_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_UART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_UART_DMAPause()      
-       (+) Resume the DMA Transfer using HAL_UART_DMAResume()  
-       (+) Stop the DMA Transfer using HAL_UART_DMAStop()      
-    
-     *** UART HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in UART HAL driver.
-       
-      (+) __HAL_UART_ENABLE: Enable the UART peripheral 
-      (+) __HAL_UART_DISABLE: Disable the UART peripheral     
-      (+) __HAL_UART_GET_FLAG : Check whether the specified UART flag is set or not
-      (+) __HAL_UART_CLEAR_FLAG : Clear the specified UART pending flag
-      (+) __HAL_UART_ENABLE_IT: Enable the specified UART interrupt
-      (+) __HAL_UART_DISABLE_IT: Disable the specified UART interrupt
-      
-     [..] 
-       (@) You can refer to the UART HAL driver header file for more useful macros 
-      
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup UART UART HAL module driver
-  * @brief HAL UART module driver
-  * @{
-  */
-#ifdef HAL_UART_MODULE_ENABLED
-    
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup UART_Private_Constants   UART Private Constants
-  * @{
-  */
-#define UART_TIMEOUT_VALUE  22000
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup UART_Private_Functions   UART Private Functions
-  * @{
-  */
-static void UART_SetConfig (UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart);
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart);
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void UART_DMAError(DMA_HandleTypeDef *hdma); 
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-/** @defgroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-
-/** @defgroup UART_Exported_Functions_Group1 Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim
-===============================================================================
-            ##### Initialization and Configuration functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to initialize the USARTx or the UARTy 
-    in asynchronous mode.
-      (+) For the asynchronous mode only these parameters can be configured: 
-        (++) Baud Rate
-        (++) Word Length 
-        (++) Stop Bit
-        (++) Parity: If the parity is enabled, then the MSB bit of the data written
-             in the data register is transmitted but is changed by the parity bit.
-             Depending on the frame length defined by the M bit (8-bits or 9-bits),
-             the possible UART frame formats are as listed in the following table:
-   +-------------------------------------------------------------+     
-   |   M bit |  PCE bit  |            UART frame                 |
-   |---------------------|---------------------------------------|             
-   |    0    |    0      |    | SB | 8 bit data | STB |          |
-   |---------|-----------|---------------------------------------|  
-   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-   |---------|-----------|---------------------------------------|  
-   |    1    |    0      |    | SB | 9 bit data | STB |          |
-   |---------|-----------|---------------------------------------|  
-   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-   +-------------------------------------------------------------+            
-        (++) Hardware flow control
-        (++) Receiver/transmitter modes
-        (++) Over Sampling Methode
-    [..]
-    The HAL_UART_Init(), HAL_HalfDuplex_Init(), HAL_LIN_Init() and HAL_MultiProcessor_Init() APIs 
-    follow respectively the UART asynchronous, UART Half duplex, LIN and Multi-Processor
-    configuration procedures (details for the procedures are available in reference manual (RM0038)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the UART mode according to the specified parameters in
-  *         the UART_InitTypeDef and create the associated handle.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  {
-    /* Check the parameters */
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
-  }
-  else
-  {
-    /* Check the parameters */
-    assert_param(IS_UART_INSTANCE(huart->Instance));
-  }
-  
-  if(huart->State == HAL_UART_STATE_RESET)
-  {  
-    /* Init the low level hardware */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-  
-  /* In asynchronous mode, the following bits must be kept cleared: 
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-  
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-  
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State= HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the half-duplex mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check UART instance */
-  assert_param(IS_UART_HALFDUPLEX_INSTANCE(huart->Instance));
-  
-  if(huart->State == HAL_UART_STATE_RESET)
-  {   
-    /* Init the low level hardware */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-  
-  /* In half-duplex mode, the following bits must be kept cleared: 
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN and IREN bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_IREN | USART_CR3_SCEN);
-  
-  /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
-  huart->Instance->CR3 |= USART_CR3_HDSEL;
- 
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-  
-  /* Initialize the UART state*/
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State= HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the LIN mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  BreakDetectLength: Specifies the LIN break detection length.
-  *         This parameter can be one of the following values:
-  *            @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
-  *            @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength)
-{
-  /* Check the UART handle allocation */
-  if(huart == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the LIN UART instance */  
-  assert_param(IS_UART_LIN_INSTANCE(huart->Instance));
-  /* Check the Break detection length parameter */
-  assert_param(IS_UART_LIN_BREAK_DETECT_LENGTH(BreakDetectLength));
-
-  /* LIN mode limited to 16-bit oversampling only */
-  if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    return HAL_ERROR;
-  }
-
-  if(huart->State == HAL_UART_STATE_RESET)
-  {   
-    /* Init the low level hardware */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-  
-  /* In LIN mode, the following bits must be kept cleared: 
-     - CLKEN bits in the USART_CR2 register,
-     - SCEN and IREN bits in the USART_CR3 register.*/
-  huart->Instance->CR2 &= ~(USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_HDSEL | USART_CR3_IREN | USART_CR3_SCEN);
-  
-  /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
-  huart->Instance->CR2 |= USART_CR2_LINEN;
-  
-  /* Set the USART LIN Break detection length. */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_LBDL, BreakDetectLength);
-  
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-  
-  /* Initialize the UART state*/
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State= HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the Multi-Processor mode according to the specified
-  *         parameters in the UART_InitTypeDef and create the associated handle.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  Address: UART node address 
-  * @param  WakeUpMethod: specifies the UART wakeup method.
-  *         This parameter can be one of the following values:
-  *            @arg UART_WAKEUPMETHOD_IDLELINE: Wakeup by an idle line detection
-  *            @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wakeup by an address mark
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod)
-{
-  /* Check the UART handle allocation */
-  if(huart == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check UART instance capabilities */  
-  assert_param(IS_UART_MULTIPROCESSOR_INSTANCE(huart->Instance));
-
-  /* Check the Address & wake up method parameters */
-  assert_param(IS_UART_WAKEUPMETHOD(WakeUpMethod));
-  assert_param(IS_UART_ADDRESS(Address));
-  
-  if(huart->State == HAL_UART_STATE_RESET)
-  {   
-    /* Init the low level hardware */
-    HAL_UART_MspInit(huart);
-  }
-
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /* Disable the peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* Set the UART Communication parameters */
-  UART_SetConfig(huart);
-  
-  /* In Multi-Processor mode, the following bits must be kept cleared: 
-     - LINEN and CLKEN bits in the USART_CR2 register,
-     - SCEN, HDSEL and IREN  bits in the USART_CR3 register */
-  huart->Instance->CR2 &= ~(USART_CR2_LINEN | USART_CR2_CLKEN);
-  huart->Instance->CR3 &= ~(USART_CR3_SCEN | USART_CR3_HDSEL | USART_CR3_IREN);
-  
-  /* Set the USART address node */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_ADD, Address);
-  
-  /* Set the wake up method by setting the WAKE bit in the CR1 register */
-  MODIFY_REG(huart->Instance->CR1, USART_CR1_WAKE, WakeUpMethod);
-  
-  /* Enable the peripheral */
-  __HAL_UART_ENABLE(huart);
-  
-  /* Initialize the UART state */
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State= HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the UART peripheral. 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart)
-{
-  /* Check the UART handle allocation */
-  if(huart == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-
-  huart->State = HAL_UART_STATE_BUSY;
-  
-  /* Disable the Peripheral */
-  __HAL_UART_DISABLE(huart);
-  
-  /* DeInit the low level hardware */
-  HAL_UART_MspDeInit(huart);
-
-  huart->ErrorCode = HAL_UART_ERROR_NONE;
-  huart->State = HAL_UART_STATE_RESET;
-
-  /* Process Unlock */
-  __HAL_UNLOCK(huart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  UART MSP Init.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  UART MSP DeInit.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group2 IO operation functions 
-  *  @brief UART Transmit and Receive functions 
-  *
-@verbatim
-  ==============================================================================
-                      ##### IO operation functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to manage the UART asynchronous
-    and Half duplex data transfers.
-
-    (#) There are two modes of transfer:
-       (++) Blocking mode: The communication is performed in polling mode. 
-            The HAL status of all data processing is returned by the same function 
-            after finishing transfer.  
-       (++) Non blocking mode: The communication is performed using Interrupts 
-            or DMA, these APIs return the HAL status.
-            The end of the data processing will be indicated through the 
-            dedicated UART IRQ when using Interrupt mode or the DMA IRQ when 
-            using DMA mode.
-            The HAL_UART_TxCpltCallback(), HAL_UART_RxCpltCallback() user callbacks 
-            will be executed respectivelly at the end of the transmit or receive process.
-            The HAL_UART_ErrorCallback() user callback will be executed when 
-            a communication error is detected.
-
-    (#) Blocking mode APIs are:
-        (++) HAL_UART_Transmit()
-        (++) HAL_UART_Receive() 
-
-    (#) Non Blocking mode APIs with Interrupt are:
-        (++) HAL_UART_Transmit_IT()
-        (++) HAL_UART_Receive_IT()
-        (++) HAL_UART_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are:
-        (++) HAL_UART_Transmit_DMA()
-        (++) HAL_UART_Receive_DMA()
-        (++) HAL_UART_DMAPause()
-        (++) HAL_UART_DMAResume()
-        (++) HAL_UART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in non blocking mode:
-        (++) HAL_UART_TxHalfCpltCallback()
-        (++) HAL_UART_TxCpltCallback()
-        (++) HAL_UART_RxHalfCpltCallback()
-        (++) HAL_UART_RxCpltCallback()
-        (++) HAL_UART_ErrorCallback()
-
-    [..] 
-      (@) In the Half duplex communication, it is forbidden to run the transmit 
-          and receive process in parallel, the UART state HAL_UART_STATE_BUSY_TX_RX 
-          can't be useful.
-      
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Sends an amount of data in blocking mode. 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State;
-  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(huart);
-    
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-    while(huart->TxXferCount > 0)
-    {
-      huart->TxXferCount--;
-      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
-      {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pData;
-        huart->Instance->DR = (*tmp & (uint16_t)0x01FF);
-        if(huart->Init.Parity == UART_PARITY_NONE)
-        {
-          pData +=2;
-        }
-        else
-        { 
-          pData +=1;
-        }
-      } 
-      else
-      {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        huart->Instance->DR = (*pData++ & (uint8_t)0xFF);
-      }
-    }
-    
-    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, Timeout) != HAL_OK)
-    { 
-      return HAL_TIMEOUT;
-    }
-    
-    /* Check if a non-blocking receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_READY;
-    }
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in blocking mode. 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp;
-  uint32_t  tmp1 = 0;
-  
-  tmp1 = huart->State;
-  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL ) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(huart);
-    
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-    
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-    
-    /* Check the remain data to be received */
-    while(huart->RxXferCount > 0)
-    {
-      huart->RxXferCount--;
-      if(huart->Init.WordLength == UART_WORDLENGTH_9B)
-      {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pData ;
-        if(huart->Init.Parity == UART_PARITY_NONE)
-        {
-          *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
-          pData +=2;
-        }
-        else
-        {
-          *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
-          pData +=1;
-        }
-
-      } 
-      else
-      {
-        if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        if(huart->Init.Parity == UART_PARITY_NONE)
-        {
-          *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
-        }
-        else
-        {
-          *pData++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
-        }
-        
-      }
-    }
-    
-    /* Check if a non-blocking transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_READY;
-    }
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;   
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tmp = 0;
-  
-  tmp = huart->State;
-  if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL ) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(huart);
-    
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-
-    /* Enable the UART Parity Error Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Transmit data register empty Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_TXE);
-    
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t tmp = 0;
-  
-  tmp = huart->State;
-  if((tmp == HAL_UART_STATE_READY) || (tmp == HAL_UART_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL ) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pRxBuffPtr = pData;
-    huart->RxXferSize = Size;
-    huart->RxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-
-    /* Enable the UART Parity Error Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_PE);
-
-    /* Enable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    /* Enable the UART Data Register not empty Interrupt */
-    __HAL_UART_ENABLE_IT(huart, UART_IT_RXNE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode. 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-  uint32_t tmp1 = 0;
-
-  tmp1 = huart->State;
-  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_RX))
-  {
-    if((pData == HAL_NULL ) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pTxBuffPtr = pData;
-    huart->TxXferSize = Size;
-    huart->TxXferCount = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a receive process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_RX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmatx->XferCpltCallback = UART_DMATransmitCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmatx->XferHalfCpltCallback = UART_DMATxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmatx->XferErrorCallback = UART_DMAError;
-
-    /* Enable the UART transmit DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmatx, *(uint32_t*)tmp, (uint32_t)&huart->Instance->DR, Size);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode. 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  pData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @note   When the UART parity is enabled (PCE = 1), the received data contain 
-  *         the parity bit (MSB position)     
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
-{
-  uint32_t *tmp;
-  uint32_t tmp1 = 0;
-
-  tmp1 = huart->State;
-  if((tmp1 == HAL_UART_STATE_READY) || (tmp1 == HAL_UART_STATE_BUSY_TX))
-  {
-    if((pData == HAL_NULL ) || (Size == 0))
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(huart);
-
-    huart->pRxBuffPtr = pData;
-    huart->RxXferSize = Size;
-
-    huart->ErrorCode = HAL_UART_ERROR_NONE;
-    /* Check if a transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX)
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX_RX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_BUSY_RX;
-    }
-
-    /* Set the UART DMA transfer complete callback */
-    huart->hdmarx->XferCpltCallback = UART_DMAReceiveCplt;
-
-    /* Set the UART DMA Half transfer complete callback */
-    huart->hdmarx->XferHalfCpltCallback = UART_DMARxHalfCplt;
-
-    /* Set the DMA error callback */
-    huart->hdmarx->XferErrorCallback = UART_DMAError;
-
-    /* Enable the DMA channel */
-    tmp = (uint32_t*)&pData;
-    HAL_DMA_Start_IT(huart->hdmarx, (uint32_t)&huart->Instance->DR, *(uint32_t*)tmp, Size);
-
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the UART CR3 register */
-    huart->Instance->CR3 |= USART_CR3_DMAR;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-    
-/**
-  * @brief Pauses the DMA Transfer.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  if(huart->State == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Disable the UART DMA Tx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-  }
-  else if(huart->State == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Disable the UART DMA Rx request */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
-  }
-  else if (huart->State == HAL_UART_STATE_BUSY_TX_RX)
-  {
-    /* Disable the UART DMA Tx & Rx requests */
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAT);
-    huart->Instance->CR3 &= (uint32_t)(~USART_CR3_DMAR);
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-  
-    return HAL_ERROR; 
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief Resumes the DMA Transfer.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart)
-{
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  if(huart->State == HAL_UART_STATE_BUSY_TX)
-  {
-    /* Enable the UART DMA Tx request */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-  }
-  else if(huart->State == HAL_UART_STATE_BUSY_RX)
-  {
-    /* Clear the Overrun flag before resumming the Rx transfer*/
-    __HAL_UART_CLEAR_OREFLAG(huart);
-    /* Enable the UART DMA Rx request */
-    huart->Instance->CR3 |= USART_CR3_DMAR;
-  }
-  else if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-  {
-    /* Clear the Overrun flag before resumming the Rx transfer*/
-    __HAL_UART_CLEAR_OREFLAG(huart);
-    /* Enable the UART DMA Tx & Rx request */
-    huart->Instance->CR3 |= USART_CR3_DMAT;
-    huart->Instance->CR3 |= USART_CR3_DMAR;
-  }
-  else
-  {
-    /* Process Unlocked */
-    __HAL_UNLOCK(huart);
-  
-    return HAL_ERROR; 
-  }
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the DMA Transfer.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL UART API under callbacks HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_UART_TxCpltCallback() / HAL_UART_RxCpltCallback()
-     */
-  
-  /* Disable the UART Tx/Rx DMA requests */
-  huart->Instance->CR3 &= ~USART_CR3_DMAT;
-  huart->Instance->CR3 &= ~USART_CR3_DMAR;
-  
-  /* Abort the UART DMA tx channel */
-  if(huart->hdmatx != HAL_NULL)
-  {
-    HAL_DMA_Abort(huart->hdmatx);
-  }
-  /* Abort the UART DMA rx channel */
-  if(huart->hdmarx != HAL_NULL)
-  {
-    HAL_DMA_Abort(huart->hdmarx);
-  }
-  
-  huart->State = HAL_UART_STATE_READY;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles UART interrupt request.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart)
-{
-  uint32_t tmp1 = 0, tmp2 = 0;
-
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_PE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_PE);  
-  /* UART parity error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_PEFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_PE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_FE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART frame error interrupt occurred -------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_FEFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_FE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_NE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART noise error interrupt occurred -------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_NEFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_NE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_ORE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_ERR);
-  /* UART Over-Run interrupt occurred ----------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    __HAL_UART_CLEAR_OREFLAG(huart);
-    
-    huart->ErrorCode |= HAL_UART_ERROR_ORE;
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_RXNE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_RXNE);
-  /* UART in mode Receiver ---------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  { 
-    UART_Receive_IT(huart);
-  }
-  
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TXE);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TXE);
-  /* UART in mode Transmitter ------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    UART_Transmit_IT(huart);
-  }
-
-  tmp1 = __HAL_UART_GET_FLAG(huart, UART_FLAG_TC);
-  tmp2 = __HAL_UART_GET_IT_SOURCE(huart, UART_IT_TC);
-  /* UART in mode Transmitter end --------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    UART_EndTransmit_IT(huart);
-  }  
-
-  if(huart->ErrorCode != HAL_UART_ERROR_NONE)
-  {
-    /* Set the UART state ready to be able to start again the process */
-    huart->State = HAL_UART_STATE_READY;
-    
-    HAL_UART_ErrorCallback(huart);
-  }  
-}
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_TxHalfCpltCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callbacks.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-__weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  UART error callbacks.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
- __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_UART_ErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group3 Peripheral Control functions 
-  *  @brief   UART control functions 
-  *
-@verbatim   
-  ==============================================================================
-                      ##### Peripheral Control functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to control the UART:
-    (+) HAL_LIN_SendBreak() API can be helpful to transmit the break character.
-    (+) HAL_MultiProcessor_EnterMuteMode() API can be helpful to enter the UART in mute mode. 
-    (+) HAL_MultiProcessor_ExitMuteMode() API can be helpful to exit the UART mute mode by software.
-    (+) HAL_HalfDuplex_EnableTransmitter() API to enable the UART transmitter and disables the UART receiver in Half Duplex mode
-    (+) HAL_HalfDuplex_EnableReceiver() API to enable the UART receiver and disables the UART transmitter in Half Duplex mode
-    
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Transmits break characters.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
-  
-  /* Send break characters */
-  huart->Instance->CR1 |= USART_CR1_SBK;
- 
-  huart->State = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Enters the UART in mute mode. 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
-  
-  /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
-  huart->Instance->CR1 |= USART_CR1_RWU;
-  
-  huart->State = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Exits the UART mute mode: wake up software. 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart)
-{
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
-  
-  /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
-  huart->Instance->CR1 &= (uint32_t)~((uint32_t)USART_CR1_RWU);
-  
-  huart->State = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Enables the UART transmitter and disables the UART receiver.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-  
-  /* Clear TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-  
-  /* Enable the USART's transmit interface by setting the TE bit in the USART CR1 register */
-  tmpreg |= (uint32_t)USART_CR1_TE;
-  
-  /* Write to USART CR1 */
-  huart->Instance->CR1 = (uint32_t)tmpreg;
- 
-  huart->State = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Enables the UART receiver and disables the UART transmitter.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00;
-
-  /* Process Locked */
-  __HAL_LOCK(huart);
-  
-  huart->State = HAL_UART_STATE_BUSY;
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  tmpreg = huart->Instance->CR1;
-  
-  /* Clear TE and RE bits */
-  tmpreg &= (uint32_t)~((uint32_t)(USART_CR1_TE | USART_CR1_RE));
-  
-  /* Enable the USART's receive interface by setting the RE bit in the USART CR1 register */
-  tmpreg |= (uint32_t)USART_CR1_RE;
-  
-  /* Write to USART CR1 */
-  huart->Instance->CR1 = (uint32_t)tmpreg;
-  
-  huart->State = HAL_UART_STATE_READY;
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(huart);
-  
-  return HAL_OK; 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Exported_Functions_Group4 Peripheral State and Errors functions 
-  *  @brief   UART State and Errors functions 
-  *
-@verbatim   
-  ==============================================================================
-                 ##### Peripheral State and Errors functions #####
-  ==============================================================================  
- [..]
-   This subsection provides a set of functions allowing to return the State of 
-   UART communication process, return Peripheral Errors occurred during communication 
-   process
-   (+) HAL_UART_GetState() API can be helpful to check in run-time the state of the UART peripheral.
-   (+) HAL_UART_GetError() check in run-time errors that could be occurred during communication. 
-
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Returns the UART state.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL state
-  */
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart)
-{
-  return huart->State;
-}
-
-/**
-* @brief  Return the UART error code
-* @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *              the configuration information for the specified UART.
-* @retval UART Error Code
-*/
-uint32_t HAL_UART_GetError(UART_HandleTypeDef *huart)
-{
-  return huart->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Private_Functions   UART Private Functions
-  *  @brief   UART Private functions 
-  * @{
-  */
-/**
-  * @brief  DMA UART transmit process complete callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)     
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* DMA Normal mode*/
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  {
-    huart->TxXferCount = 0;
-
-    /* Disable the DMA transfer for transmit request by setting the DMAT bit
-       in the UART CR3 register */
-    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAT);
-
-    /* Wait for UART TC Flag */
-    if(UART_WaitOnFlagUntilTimeout(huart, UART_FLAG_TC, RESET, UART_TIMEOUT_VALUE) != HAL_OK)
-    {
-      /* Timeout occurred */ 
-      huart->State = HAL_UART_STATE_TIMEOUT;
-      HAL_UART_ErrorCallback(huart);
-    }
-    else
-    {
-      /* No Timeout */
-      /* Check if a receive process is ongoing or not */
-      if(huart->State == HAL_UART_STATE_BUSY_TX_RX)
-      {
-        huart->State = HAL_UART_STATE_BUSY_RX;
-      }
-      else
-      {
-        huart->State = HAL_UART_STATE_READY;
-      }
-      HAL_UART_TxCpltCallback(huart);
-    }
-  }
-  /* DMA Circular mode */
-  else
-  {
-    HAL_UART_TxCpltCallback(huart);
-  }
-}
-
-/**
-  * @brief DMA UART transmit process half complete callback 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_TxHalfCpltCallback(huart);
-}
-
-/**
-  * @brief  DMA UART receive process complete callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)  
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  /* DMA Normal mode*/
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  {
-    huart->RxXferCount = 0;
-  
-    /* Disable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the UART CR3 register */
-    huart->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_DMAR);
-
-    /* Check if a transmit process is ongoing or not */
-    if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-    {
-      huart->State = HAL_UART_STATE_BUSY_TX;
-    }
-    else
-    {
-      huart->State = HAL_UART_STATE_READY;
-    }
-  }
-  HAL_UART_RxCpltCallback(huart);
-}
-
-/**
-  * @brief DMA UART receive process half complete callback 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  UART_HandleTypeDef* huart = (UART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_UART_RxHalfCpltCallback(huart); 
-}
-
-/**
-  * @brief  DMA UART communication error callback.
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void UART_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  UART_HandleTypeDef* huart = ( UART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-  huart->RxXferCount = 0;
-  huart->TxXferCount = 0;
-  huart->State= HAL_UART_STATE_READY;
-  huart->ErrorCode |= HAL_UART_ERROR_DMA;
-  HAL_UART_ErrorCallback(huart);
-}
-
-/**
-  * @brief  This function handles UART Communication Timeout.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @param  Flag: specifies the UART flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_UART_GET_FLAG(huart, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-          huart->State= HAL_UART_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_UART_GET_FLAG(huart, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-          __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-          huart->State= HAL_UART_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(huart);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Sends an amount of data in non blocking mode.
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State;
-  if((tmp1 == HAL_UART_STATE_BUSY_TX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
-  {
-    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) huart->pTxBuffPtr;
-      huart->Instance->DR = (uint16_t)(*tmp & (uint16_t)0x01FF);
-      if(huart->Init.Parity == UART_PARITY_NONE)
-      {
-        huart->pTxBuffPtr += 2;
-      }
-      else
-      {
-        huart->pTxBuffPtr += 1;
-      }
-    } 
-    else
-    {
-      huart->Instance->DR = (uint8_t)(*huart->pTxBuffPtr++ & (uint8_t)0x00FF);
-    }
-
-    if(--huart->TxXferCount == 0)
-    {
-      /* Disable the UART Transmit Complete Interrupt */
-      __HAL_UART_DISABLE_IT(huart, UART_IT_TXE);
-
-      /* Enable the UART Transmit Complete Interrupt */    
-      __HAL_UART_ENABLE_IT(huart, UART_IT_TC);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  huart: pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_EndTransmit_IT(UART_HandleTypeDef *huart)
-{
-  /* Disable the UART Transmit Complete Interrupt */    
-  __HAL_UART_DISABLE_IT(huart, UART_IT_TC);
-  
-  /* Check if a receive process is ongoing or not */
-  if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-  {
-    huart->State = HAL_UART_STATE_BUSY_RX;
-  }
-  else
-  {
-    /* Disable the UART Parity Error Interrupt */
-    __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
-    /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-    huart->State = HAL_UART_STATE_READY;
-  }
-  
-  HAL_UART_TxCpltCallback(huart);
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Receives an amount of data in non blocking mode 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart)
-{
-  uint16_t* tmp;
-  uint32_t tmp1 = 0;
-  
-  tmp1 = huart->State; 
-  if((tmp1 == HAL_UART_STATE_BUSY_RX) || (tmp1 == HAL_UART_STATE_BUSY_TX_RX))
-  {
-    if(huart->Init.WordLength == UART_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) huart->pRxBuffPtr;
-      if(huart->Init.Parity == UART_PARITY_NONE)
-      {
-        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x01FF);
-        huart->pRxBuffPtr += 2;
-      }
-      else
-      {
-        *tmp = (uint16_t)(huart->Instance->DR & (uint16_t)0x00FF);
-        huart->pRxBuffPtr += 1;
-      }
-    }
-    else
-    {
-      if(huart->Init.Parity == UART_PARITY_NONE)
-      {
-        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x00FF);
-      }
-      else
-      {
-        *huart->pRxBuffPtr++ = (uint8_t)(huart->Instance->DR & (uint8_t)0x007F);
-      }
-    }
-
-    if(--huart->RxXferCount == 0)
-    {
-      __HAL_UART_DISABLE_IT(huart, UART_IT_RXNE);
-
-      /* Check if a transmit process is ongoing or not */
-      if(huart->State == HAL_UART_STATE_BUSY_TX_RX) 
-      {
-        huart->State = HAL_UART_STATE_BUSY_TX;
-      }
-      else
-      {
-        /* Disable the UART Parity Error Interrupt */
-        __HAL_UART_DISABLE_IT(huart, UART_IT_PE);
-
-        /* Disable the UART Error Interrupt: (Frame error, noise error, overrun error) */
-        __HAL_UART_DISABLE_IT(huart, UART_IT_ERR);
-
-        huart->State = HAL_UART_STATE_READY;
-      }
-      HAL_UART_RxCpltCallback(huart);
-
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Configures the UART peripheral. 
-  * @param  huart: Pointer to a UART_HandleTypeDef structure that contains
-  *                the configuration information for the specified UART module.
-  * @retval None
-  */
-static void UART_SetConfig(UART_HandleTypeDef *huart)
-{
-  uint32_t tmpreg = 0x00;
-  
-  /* Check the parameters */
-  assert_param(IS_UART_INSTANCE(huart->Instance));
-  assert_param(IS_UART_BAUDRATE(huart->Init.BaudRate));  
-  assert_param(IS_UART_WORD_LENGTH(huart->Init.WordLength));
-  assert_param(IS_UART_STOPBITS(huart->Init.StopBits));
-  assert_param(IS_UART_PARITY(huart->Init.Parity));
-  assert_param(IS_UART_MODE(huart->Init.Mode));
-  assert_param(IS_UART_HARDWARE_FLOW_CONTROL(huart->Init.HwFlowCtl));
-
-  /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
-  if(huart->Init.HwFlowCtl != UART_HWCONTROL_NONE)
-  {
-    assert_param(IS_UART_HWFLOW_INSTANCE(huart->Instance));
-  }
-
-  /*-------------------------- USART CR2 Configuration -----------------------*/
-  /* Configure the UART Stop Bits: Set STOP[13:12] bits according 
-   * to huart->Init.StopBits value */
-  MODIFY_REG(huart->Instance->CR2, USART_CR2_STOP, huart->Init.StopBits);
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Configure the UART Word Length, Parity and mode: 
-     Set the M bits according to huart->Init.WordLength value 
-     Set PCE and PS bits according to huart->Init.Parity value
-     Set TE and RE bits according to huart->Init.Mode value
-     Set OVER8 bit according to huart->Init.OverSampling value */
-  tmpreg = (uint32_t)huart->Init.WordLength | huart->Init.Parity | huart->Init.Mode | huart->Init.OverSampling;
-  MODIFY_REG(huart->Instance->CR1, 
-             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE | USART_CR1_OVER8), 
-             tmpreg);
-  
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
-  /* Configure the UART HFC: Set CTSE and RTSE bits according to huart->Init.HwFlowCtl value */
-  MODIFY_REG(huart->Instance->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), huart->Init.HwFlowCtl);
-  
-  /* Check the Over Sampling */
-  if(huart->Init.OverSampling == UART_OVERSAMPLING_8)
-  {
-    /*-------------------------- USART BRR Configuration ---------------------*/
-    if((huart->Instance == USART1))
-    {
-      huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
-    }
-    else
-    {
-      huart->Instance->BRR = UART_BRR_SAMPLING8(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
-    }
-  }
-  else
-  {
-    /*-------------------------- USART BRR Configuration ---------------------*/
-    if((huart->Instance == USART1))
-    {
-      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK2Freq(), huart->Init.BaudRate);
-    }
-    else
-    {
-      huart->Instance->BRR = UART_BRR_SAMPLING16(HAL_RCC_GetPCLK1Freq(), huart->Init.BaudRate);
-    }
-  }
-}
-/**
-  * @}
-  */
-
-#endif /* HAL_UART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_uart.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,624 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_uart.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   This file contains all the functions prototypes for the UART 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_UART_H
-#define __STM32L1xx_HAL_UART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup UART
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup UART_Exported_Types UART Exported Types
-  * @{
-  */ 
-
-
-/** 
-  * @brief UART Init Structure definition
-  */ 
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the UART communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (huart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
-                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref UART_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref UART_Stop_Bits */
-
-  uint32_t Parity;                    /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref UART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref UART_Mode */
-
-  uint32_t HwFlowCtl;                 /*!< Specifies wether the hardware flow control mode is enabled
-                                           or disabled.
-                                           This parameter can be a value of @ref UART_Hardware_Flow_Control */
-  
-  uint32_t OverSampling;              /*!< Specifies wether the Over sampling 8 is enabled or disabled, to achieve higher speed (up to fPCLK/8).
-                                           This parameter can be a value of @ref UART_Over_Sampling */ 
-}UART_InitTypeDef;
-
-/** 
-  * @brief HAL UART State structures definition  
-  */ 
-typedef enum
-{
-  HAL_UART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized                      */
-  HAL_UART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use           */
-  HAL_UART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing                     */
-  HAL_UART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing               */
-  HAL_UART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing                  */
-  HAL_UART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission and Reception process is ongoing */
-  HAL_UART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state                                      */
-  HAL_UART_STATE_ERROR             = 0x04     /*!< Error                                              */
-}HAL_UART_StateTypeDef;
-
-/** 
-  * @brief  HAL UART Error Code structure definition  
-  */ 
-typedef enum
-{
-  HAL_UART_ERROR_NONE      = 0x00,    /*!< No error            */
-  HAL_UART_ERROR_PE        = 0x01,    /*!< Parity error        */
-  HAL_UART_ERROR_NE        = 0x02,    /*!< Noise error         */
-  HAL_UART_ERROR_FE        = 0x04,    /*!< frame error         */
-  HAL_UART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
-  HAL_UART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
-}HAL_UART_ErrorTypeDef;
-
-/** 
-  * @brief  UART handle Structure definition  
-  */  
-typedef struct
-{
-  USART_TypeDef                 *Instance;        /* UART registers base address        */
-
-  UART_InitTypeDef              Init;             /* UART communication parameters      */
-
-  uint8_t                       *pTxBuffPtr;      /* Pointer to UART Tx transfer Buffer */
-
-  uint16_t                      TxXferSize;       /* UART Tx Transfer size              */
-
-  uint16_t                      TxXferCount;      /* UART Tx Transfer Counter           */
-
-  uint8_t                       *pRxBuffPtr;      /* Pointer to UART Rx transfer Buffer */
-
-  uint16_t                      RxXferSize;       /* UART Rx Transfer size              */
-
-  uint16_t                      RxXferCount;      /* UART Rx Transfer Counter           */  
-
-  DMA_HandleTypeDef             *hdmatx;          /* UART Tx DMA Handle parameters      */
-
-  DMA_HandleTypeDef             *hdmarx;          /* UART Rx DMA Handle parameters      */
-
-  HAL_LockTypeDef               Lock;            /* Locking object                     */
-
-  __IO HAL_UART_StateTypeDef    State;            /* UART communication state           */
-  
-  __IO HAL_UART_ErrorTypeDef    ErrorCode;        /* UART Error code                    */
-
-}UART_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup UART_Exported_Constants UART Exported constants
-  * @{
-  */
-  
-/** @defgroup UART_Word_Length   UART Word Length
-  * @{
-  */
-#define UART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
-#define UART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-#define IS_UART_WORD_LENGTH(LENGTH) (((LENGTH) == UART_WORDLENGTH_8B) || \
-                                     ((LENGTH) == UART_WORDLENGTH_9B))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Stop_Bits   UART Number of Stop Bits
-  * @{
-  */
-#define UART_STOPBITS_1                     ((uint32_t)0x00000000)
-#define UART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-#define IS_UART_STOPBITS(STOPBITS) (((STOPBITS) == UART_STOPBITS_1) || \
-                                    ((STOPBITS) == UART_STOPBITS_2))
-/**
-  * @}
-  */ 
-
-/** @defgroup UART_Parity  UART Parity
-  * @{
-  */ 
-#define UART_PARITY_NONE                    ((uint32_t)0x00000000)
-#define UART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define UART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-#define IS_UART_PARITY(PARITY) (((PARITY) == UART_PARITY_NONE) || \
-                                ((PARITY) == UART_PARITY_EVEN) || \
-                                ((PARITY) == UART_PARITY_ODD))
-/**
-  * @}
-  */ 
-
-/** @defgroup UART_Hardware_Flow_Control UART Hardware Flow Control
-  * @{
-  */ 
-#define UART_HWCONTROL_NONE                  ((uint32_t)0x00000000)
-#define UART_HWCONTROL_RTS                   ((uint32_t)USART_CR3_RTSE)
-#define UART_HWCONTROL_CTS                   ((uint32_t)USART_CR3_CTSE)
-#define UART_HWCONTROL_RTS_CTS               ((uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE))
-#define IS_UART_HARDWARE_FLOW_CONTROL(CONTROL)\
-                              (((CONTROL) == UART_HWCONTROL_NONE) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS) || \
-                               ((CONTROL) == UART_HWCONTROL_CTS) || \
-                               ((CONTROL) == UART_HWCONTROL_RTS_CTS))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Mode UART Transfer Mode
-  * @{
-  */ 
-#define UART_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define UART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define UART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_UART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000))
-/**
-  * @}
-  */
-    
- /** @defgroup UART_State  UART State
-  * @{
-  */ 
-#define UART_STATE_DISABLE                  ((uint32_t)0x00000000)
-#define UART_STATE_ENABLE                   ((uint32_t)USART_CR1_UE)
-#define IS_UART_STATE(STATE) (((STATE) == UART_STATE_DISABLE) || \
-                              ((STATE) == UART_STATE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Over_Sampling UART Over Sampling
-  * @{
-  */
-#define UART_OVERSAMPLING_16                    ((uint32_t)0x00000000)
-#define UART_OVERSAMPLING_8                     ((uint32_t)USART_CR1_OVER8)
-#define IS_UART_OVERSAMPLING(SAMPLING) (((SAMPLING) == UART_OVERSAMPLING_16) || \
-                                        ((SAMPLING) == UART_OVERSAMPLING_8))
-/**
-  * @}
-  */
-
-/** @defgroup UART_LIN_Break_Detection_Length  UART LIN Break Detection Length
-  * @{
-  */  
-#define UART_LINBREAKDETECTLENGTH_10B      ((uint32_t)0x00000000)
-#define UART_LINBREAKDETECTLENGTH_11B      ((uint32_t)USART_CR2_LBDL)
-#define IS_UART_LIN_BREAK_DETECT_LENGTH(LENGTH) (((LENGTH) == UART_LINBREAKDETECTLENGTH_10B) || \
-                                                 ((LENGTH) == UART_LINBREAKDETECTLENGTH_11B))
-/**
-  * @}
-  */
-                                         
-/** @defgroup UART_WakeUp_functions UART Wakeup Functions
-  * @{
-  */
-#define UART_WAKEUPMETHOD_IDLELINE                ((uint32_t)0x00000000)
-#define UART_WAKEUPMETHOD_ADDRESSMARK             ((uint32_t)0x00000800)
-#define IS_UART_WAKEUPMETHOD(WAKEUP) (((WAKEUP) == UART_WAKEUPMETHOD_IDLELINE) || \
-                                      ((WAKEUP) == UART_WAKEUPMETHOD_ADDRESSMARK))
-/**
-  * @}
-  */
-
-/** @defgroup UART_Flags   UART FLags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-#define UART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
-#define UART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
-#define UART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define UART_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define UART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define UART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define UART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define UART_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define UART_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define UART_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interrupt_definition  UART Interrupt Definitions
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the XX register
-  *           - Y  : Interrupt source register (2bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *
-  * @{
-  */  
-#define UART_IT_PE                          ((uint32_t)0x10000100)
-#define UART_IT_TXE                         ((uint32_t)0x10000080)
-#define UART_IT_TC                          ((uint32_t)0x10000040)
-#define UART_IT_RXNE                        ((uint32_t)0x10000020)
-#define UART_IT_IDLE                        ((uint32_t)0x10000010)
-
-#define UART_IT_LBD                         ((uint32_t)0x20000040)
-#define UART_IT_CTS                         ((uint32_t)0x30000400)
-
-#define UART_IT_ERR                         ((uint32_t)0x30000001)
-
-/**
-  * @}
-  */
-
-/** @defgroup UART_Interruption_Mask    UART interruptions flag mask
-  * @{
-  */ 
-#define UART_IT_MASK  ((uint32_t)0x0000FFFF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup UART_Exported_Macros UART Exported Macros
-  * @{
-  */
-
-
-/** @brief Reset UART handle state
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_UART_STATE_RESET)
-
-/** @brief  Flushs the UART DR register 
-  * @param  __HANDLE__: specifies the UART Handle.
-  */
-#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
-
-/** @brief  Checks whether the specified UART flag is set or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag
-  *            @arg UART_FLAG_TXE:  Transmit data register empty flag
-  *            @arg UART_FLAG_TC:   Transmission Complete flag
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag
-  *            @arg UART_FLAG_IDLE: Idle Line detection flag
-  *            @arg UART_FLAG_ORE:  OverRun Error flag
-  *            @arg UART_FLAG_NE:   Noise Error flag
-  *            @arg UART_FLAG_FE:   Framing Error flag
-  *            @arg UART_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))   
-
-/** @brief  Clears the specified UART pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg UART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
-  *            @arg UART_FLAG_LBD:  LIN Break detection flag.
-  *            @arg UART_FLAG_TC:   Transmission Complete flag.
-  *            @arg UART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the UART PE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
-                                               (__HANDLE__)->Instance->DR;}while(0)
-/** @brief  Clear the UART FE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART NE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART ORE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the UART IDLE pending flag.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
-                                                 
-/** @brief  Enables or disables the specified UART interrupt.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __INTERRUPT__: specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS:  CTS change interrupt
-  *            @arg UART_IT_LBD:  LIN Break detection interrupt
-  *            @arg UART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:   Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg UART_IT_PE:   Parity Error interrupt
-  *            @arg UART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_UART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & UART_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
-#define __HAL_UART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & UART_IT_MASK)): \
-                                                        ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
-    
-/** @brief  Checks whether the specified UART interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @param  __IT__: specifies the UART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
-  *            @arg UART_IT_LBD: LIN Break detection interrupt
-  *            @arg UART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg UART_IT_TC:  Transmission complete interrupt
-  *            @arg UART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg UART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_ERR: Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_UART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & UART_IT_MASK))
-
-/** @brief  macros to enables or disables the UART's one bit sampling method
-  * @param  __HANDLE__: specifies the UART Handle.  
-  *         This parameter can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */     
-#define __HAL_UART_ONEBIT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
-#define __HAL_UART_ONEBIT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
-
-/** @brief  Enable UART
-  * @param  __HANDLE__: specifies the UART Handle.
-  *         The Handle Instance can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */ 
-#define __HAL_UART_ENABLE(__HANDLE__)               ((__HANDLE__)->Instance->CR1 |=  USART_CR1_UE)
-
-/** @brief  Disable UART
-  *         The Handle Instance can be USARTx with x: 1, 2 or 3, or UARTy with y:4 or 5 to select the USART or 
-  *         UART peripheral (availability depending on device for UARTy).
-  * @retval None
-  */
-#define __HAL_UART_DISABLE(__HANDLE__)              ((__HANDLE__)->Instance->CR1 &=  ~USART_CR1_UE)
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup UART_Private_Macros   UART Private Macros
-  * @{
-  */
-
-#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_)         (((_PCLK_)*25)/(4*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING16(_PCLK_, _BAUD_)     (UART_DIV_SAMPLING16((_PCLK_), (_BAUD_))/100)
-#define UART_DIVFRAQ_SAMPLING16(_PCLK_, _BAUD_)     (((UART_DIV_SAMPLING16((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define UART_BRR_SAMPLING16(_PCLK_, _BAUD_)         ((UART_DIVMANT_SAMPLING16((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING16((_PCLK_), (_BAUD_)) & 0x0F))
-
-#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_)          (((_PCLK_)*25)/(2*(_BAUD_)))
-#define UART_DIVMANT_SAMPLING8(_PCLK_, _BAUD_)      (UART_DIV_SAMPLING8((_PCLK_), (_BAUD_))/100)
-#define UART_DIVFRAQ_SAMPLING8(_PCLK_, _BAUD_)      (((UART_DIV_SAMPLING8((_PCLK_), (_BAUD_)) - (UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) * 100)) * 16 + 50) / 100)
-#define UART_BRR_SAMPLING8(_PCLK_, _BAUD_)          ((UART_DIVMANT_SAMPLING8((_PCLK_), (_BAUD_)) << 4)|(UART_DIVFRAQ_SAMPLING8((_PCLK_), (_BAUD_)) & 0x0F))
-
-/** @brief  Check UART Baud rate
-  * @param  __BAUDRATE__: Baudrate specified by the user
-  *         The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) 
-  *         divided by the smallest oversampling used on the USART (i.e. 8) 
-  * @retval Test result (TRUE or FALSE).
-  */
-#define IS_UART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001)
-#define IS_UART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup UART_Exported_Functions UART Exported Functions
-  * @{
-  */
-  
-/** @addtogroup UART_Exported_Functions_Group1 Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ****************************/
-HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_LIN_Init(UART_HandleTypeDef *huart, uint32_t BreakDetectLength);
-HAL_StatusTypeDef HAL_MultiProcessor_Init(UART_HandleTypeDef *huart, uint8_t Address, uint32_t WakeUpMethod);
-HAL_StatusTypeDef HAL_UART_DeInit (UART_HandleTypeDef *huart);
-void HAL_UART_MspInit(UART_HandleTypeDef *huart);
-void HAL_UART_MspDeInit(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group2 IO operation functions 
-  * @{
-  */
-
-/* IO operation functions *****************************************************/
-HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_Receive_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size);
-HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart);
-void HAL_UART_IRQHandler(UART_HandleTypeDef *huart);
-void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart);
-void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group3 Peripheral Control functions
-  * @{
-  */
-
-/* Peripheral Control functions  ************************************************/
-HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_MultiProcessor_ExitMuteMode(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableTransmitter(UART_HandleTypeDef *huart);
-HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup UART_Exported_Functions_Group4 Peripheral State and Errors functions 
-  * @{
-  */
-
-/* Peripheral State and Errors functions  **************************************************/
-HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart);
-uint32_t              HAL_UART_GetError(UART_HandleTypeDef *huart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_UART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,1879 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_usart.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   USART HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State and Errors functions  
-  @verbatim
-  ==============================================================================
-                        ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    The USART HAL driver can be used as follows:
-
-    (#) Declare a USART_HandleTypeDef handle structure.
-    (#) Initialize the USART low level resources by implementing the HAL_USART_MspInit() API:
-        (##) Enable the USARTx interface clock.
-        (##) USART pins configuration:
-             (+++) Enable the clock for the USART GPIOs.
-             (+++) Configure these USART pins as alternate function pull-up.
-        (##) NVIC configuration if you need to use interrupt process (HAL_USART_Transmit_IT(),
-             HAL_USART_Receive_IT() and HAL_USART_TransmitReceive_IT() APIs):
-             (+++) Configure the USARTx interrupt priority.
-             (+++) Enable the NVIC USART IRQ handle.
-        (##) DMA Configuration if you need to use DMA process (HAL_USART_Transmit_DMA()
-             HAL_USART_Receive_DMA() and HAL_USART_TransmitReceive_DMA() APIs):
-             (+++) Declare a DMA handle structure for the Tx/Rx channel.
-             (+++) Enable the DMAx interface clock.
-             (+++) Configure the declared DMA handle structure with the required Tx/Rx parameters.
-             (+++) Configure the DMA Tx/Rx channel.
-             (+++) Associate the initilalized DMA handle to the USART DMA Tx/Rx handle.
-             (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on the DMA Tx/Rx channel.
-
-    (#) Program the Baud Rate, Word Length, Stop Bit, Parity, Hardware 
-        flow control and Mode(Receiver/Transmitter) in the husart Init structure.
-
-    (#) Initialize the USART registers by calling the HAL_USART_Init() API:
-        (++) These APIs configures also the low level Hardware GPIO, CLOCK, CORTEX...etc)
-             by calling the customed HAL_USART_MspInit(&husart) API.
-                    
-        -@@- The specific USART interrupts (Transmission complete interrupt, 
-             RXNE interrupt and Error Interrupts) will be managed using the macros
-             __HAL_USART_ENABLE_IT() and __HAL_USART_DISABLE_IT() inside the transmit and receive process.
-          
-    (#) Three operation modes are available within this driver :     
-  
-     *** Polling mode IO operation ***
-     =================================
-     [..]    
-       (+) Send an amount of data in blocking mode using HAL_USART_Transmit() 
-       (+) Receive an amount of data in blocking mode using HAL_USART_Receive()
-       
-     *** Interrupt mode IO operation ***    
-     ===================================
-     [..]    
-       (+) Send an amount of data in non blocking mode using HAL_USART_Transmit_IT() 
-       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback 
-       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode using HAL_USART_Receive_IT() 
-       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback 
-       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_USART_ErrorCallback
-    
-     *** DMA mode IO operation ***    
-     ==============================
-     [..] 
-       (+) Send an amount of data in non blocking mode (DMA) using HAL_USART_Transmit_DMA() 
-       (+) At transmission end of half transfer HAL_USART_TxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_TxHalfCpltCallback 
-       (+) At transmission end of transfer HAL_USART_TxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_TxCpltCallback
-       (+) Receive an amount of data in non blocking mode (DMA) using HAL_USART_Receive_DMA() 
-       (+) At reception end of half transfer HAL_USART_RxHalfCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_RxHalfCpltCallback 
-       (+) At reception end of transfer HAL_USART_RxCpltCallback is executed and user can 
-            add his own code by customization of function pointer HAL_USART_RxCpltCallback                                      
-       (+) In case of transfer Error, HAL_USART_ErrorCallback() function is executed and user can 
-            add his own code by customization of function pointer HAL_USART_ErrorCallback
-       (+) Pause the DMA Transfer using HAL_USART_DMAPause()      
-       (+) Resume the DMA Transfer using HAL_USART_DMAResume()  
-       (+) Stop the DMA Transfer using HAL_USART_DMAStop()      
-     
-     *** USART HAL driver macros list ***
-     ============================================= 
-     [..]
-       Below the list of most used macros in USART HAL driver.
-       
-       (+) __HAL_USART_ENABLE: Enable the USART peripheral 
-       (+) __HAL_USART_DISABLE: Disable the USART peripheral     
-       (+) __HAL_USART_GET_FLAG : Check whether the specified USART flag is set or not
-       (+) __HAL_USART_CLEAR_FLAG : Clear the specified USART pending flag
-       (+) __HAL_USART_ENABLE_IT: Enable the specified USART interrupt
-       (+) __HAL_USART_DISABLE_IT: Disable the specified USART interrupt
-      
-     [..] 
-       (@) You can refer to the USART HAL driver header file for more useful macros
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup USART USART
-  * @brief HAL USART Synchronous module driver
-  * @{
-  */
-#ifdef HAL_USART_MODULE_ENABLED
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/** @defgroup USART_Private_Constants   USART Private Constants
-  * @{
-  */
-#define DUMMY_DATA      0xFFFF
-#define USART_TIMEOUT_VALUE  22000
-/**
-  * @}
-  */
-
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup USART_Private_Functions   USART Private Functions
-  * @{
-  */
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart);
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart);
-static void USART_SetConfig (USART_HandleTypeDef *husart);
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
-static void USART_DMAError(DMA_HandleTypeDef *hdma); 
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout);
-/**
-  * @}
-  */
-
-/* Exported functions ---------------------------------------------------------*/
-
-
-/** @defgroup USART_Exported_Functions USART Exported Functions
-  * @{
-  */
-
-/** @defgroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions 
-  *  @brief    Initialization and Configuration functions 
-  *
-@verbatim
-  ==============================================================================
-              ##### Initialization and Configuration functions #####
-  ==============================================================================
-  [..]
-  This subsection provides a set of functions allowing to initialize the USART 
-  in asynchronous and in synchronous modes.
-  (+) For the asynchronous mode only these parameters can be configured: 
-      (++) Baud Rate
-      (++) Word Length 
-      (++) Stop Bit
-      (++) Parity: If the parity is enabled, then the MSB bit of the data written
-           in the data register is transmitted but is changed by the parity bit.
-           Depending on the frame length defined by the M bit (8-bits or 9-bits),
-           the possible USART frame formats are as listed in the following table:
-   +-------------------------------------------------------------+
-   |   M bit |  PCE bit  |            USART frame                |
-   |---------------------|---------------------------------------|
-   |    0    |    0      |    | SB | 8 bit data | STB |          |
-   |---------|-----------|---------------------------------------|
-   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
-   |---------|-----------|---------------------------------------|
-   |    1    |    0      |    | SB | 9 bit data | STB |          |
-   |---------|-----------|---------------------------------------|
-   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
-   +-------------------------------------------------------------+
-      (++) USART polarity
-      (++) USART phase
-      (++) USART LastBit
-      (++) Receiver/transmitter modes
-
-  [..]
-    The HAL_USART_Init() function follows the USART  synchronous configuration 
-    procedure (details for the procedure are available in reference manual (RM0038)).
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the USART mode according to the specified
-  *         parameters in the USART_InitTypeDef and create the associated handle.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
-{
-  /* Check the USART handle allocation */
-  if(husart == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_USART_INSTANCE(husart->Instance));
-
-  if(husart->State == HAL_USART_STATE_RESET)
-  {
-    /* Init the low level hardware */
-    HAL_USART_MspInit(husart);
-  }
-  
-  husart->State = HAL_USART_STATE_BUSY;
-
-  /* Set the USART Communication parameters */
-  USART_SetConfig(husart);
-
-  /* In USART mode, the following bits must be kept cleared: 
-     - LINEN bit in the USART_CR2 register
-     - HDSEL, SCEN and IREN bits in the USART_CR3 register */
-  CLEAR_BIT(husart->Instance->CR2, USART_CR2_LINEN);
-  CLEAR_BIT(husart->Instance->CR3, (USART_CR3_IREN | USART_CR3_SCEN | USART_CR3_HDSEL));
-
-  /* Enable the Peripheral */
-  __HAL_USART_ENABLE(husart);
-
-  /* Initialize the USART state */
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-  husart->State= HAL_USART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the USART peripheral.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
-{
-   /* Check the USART handle allocation */
-  if(husart == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-
-  /* Check the parameters */
-  assert_param(IS_USART_INSTANCE(husart->Instance));
-
-  husart->State = HAL_USART_STATE_BUSY;
-
-  /* Disable the Peripheral */
-  __HAL_USART_DISABLE(husart);
-
-  /* DeInit the low level hardware */
-  HAL_USART_MspDeInit(husart);
-
-  husart->ErrorCode = HAL_USART_ERROR_NONE;
-  husart->State = HAL_USART_STATE_RESET;
-
-  /* Release Lock */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  USART MSP Init.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
- __weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_MspInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @brief  USART MSP DeInit.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
- __weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_MspDeInit could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Exported_Functions_Group2 IO operation functions 
-  *  @brief   USART Transmit and Receive functions 
-  *
-@verbatim
-  ==============================================================================
-                         ##### IO operation functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to manage the USART synchronous
-    data transfers.
-      
-  [..] 
-    The USART supports master mode only: it cannot receive or send data related to an input
-    clock (SCLK is always an output).
-
-    (#) There are two modes of transfer:
-        (++) Blocking mode: The communication is performed in polling mode. 
-             The HAL status of all data processing is returned by the same function 
-             after finishing transfer.  
-        (++) No-Blocking mode: The communication is performed using Interrupts 
-             or DMA, These API's return the HAL status.
-             The end of the data processing will be indicated through the 
-             dedicated USART IRQ when using Interrupt mode or the DMA IRQ when 
-             using DMA mode.
-             The HAL_USART_TxCpltCallback(), HAL_USART_RxCpltCallback() and HAL_USART_TxRxCpltCallback() 
-             user callbacks 
-             will be executed respectivelly at the end of the transmit or Receive process
-             The HAL_USART_ErrorCallback() user callback will be executed when a communication 
-             error is detected
-
-    (#) Blocking mode APIs are :
-        (++) HAL_USART_Transmit() in simplex mode
-        (++) HAL_USART_Receive() in full duplex receive only
-        (++) HAL_USART_TransmitReceive() in full duplex mode
-
-    (#) Non Blocking mode APIs with Interrupt are :
-        (++) HAL_USART_Transmit_IT()in simplex mode
-        (++) HAL_USART_Receive_IT() in full duplex receive only
-        (++) HAL_USART_TransmitReceive_IT() in full duplex mode
-        (++) HAL_USART_IRQHandler()
-
-    (#) Non Blocking mode functions with DMA are :
-        (++) HAL_USART_Transmit_DMA()in simplex mode
-        (++) HAL_USART_Receive_DMA() in full duplex receive only
-        (++) HAL_USART_TransmitReceive_DMA() in full duplex mode
-        (++) HAL_USART_DMAPause()
-        (++) HAL_USART_DMAResume()
-        (++) HAL_USART_DMAStop()
-
-    (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
-        (++) HAL_USART_TxHalfCpltCallback()
-        (++) HAL_USART_TxCpltCallback()
-        (++) HAL_USART_RxHalfCpltCallback()
-        (++) HAL_USART_RxCpltCallback()
-        (++) HAL_USART_ErrorCallback()
-        (++) HAL_USART_TxRxCpltCallback()
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Simplex Send an amount of data in blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp=0;
-
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pTxData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX;
-
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-    while(husart->TxXferCount > 0)
-    {
-      husart->TxXferCount--;
-      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
-      {
-        /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pTxData;
-        WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
-        if(husart->Init.Parity == USART_PARITY_NONE)
-        {
-          pTxData += 2;
-        }
-        else
-        {
-          pTxData += 1;
-        }
-      }
-      else
-      {
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0xFF));
-      }
-    }
-
-    if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, Timeout) != HAL_OK)
-    { 
-      return HAL_TIMEOUT;
-    }
-
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Receive an amount of data in blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pRxData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp=0;
-
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pRxData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-    
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    husart->RxXferSize = Size;
-    husart->RxXferCount = Size;
-    /* Check the remain data to be received */
-    while(husart->RxXferCount > 0)
-    {
-      husart->RxXferCount--;
-      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
-      {
-        /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        /* Send dummy byte in order to generate clock */
-        WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));
-        
-        /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pRxData ;
-        if(husart->Init.Parity == USART_PARITY_NONE)
-        {
-          *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-          pRxData +=2;
-        }
-        else
-        {
-          *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
-          pRxData +=1;
-        }
-      }
-      else
-      {
-        /* Wait until TXE flag is set to send dummy byte in order to generate the clock for the slave to send data */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        { 
-          return HAL_TIMEOUT;
-        }
-
-        /* Send Dummy Byte in order to generate clock */
-        WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));
-
-        /* Wait until RXNE flag is set to receive the byte */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        if(husart->Init.Parity == USART_PARITY_NONE)
-        {
-          /* Receive data */
-          *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
-        }
-        else
-        {
-          /* Receive data */
-          *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
-        }
-        
-      }
-    }
-
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode). 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer  
-  * @param  Size: Amount of data to be sent
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
-{
-  uint16_t* tmp=0;
-
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) 
-    {
-      return  HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    husart->RxXferSize = Size;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-    husart->RxXferCount = Size;
-
-    /* Check the remain data to be received */
-    while(husart->TxXferCount > 0)
-    {
-      husart->TxXferCount--;
-      husart->RxXferCount--;
-      if(husart->Init.WordLength == USART_WORDLENGTH_9B)
-      {
-        /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pTxData;
-        WRITE_REG(husart->Instance->DR, (*tmp & (uint16_t)0x01FF));
-        if(husart->Init.Parity == USART_PARITY_NONE)
-        {
-          pTxData += 2;
-        }
-        else
-        {
-          pTxData += 1;
-        }
-        
-        /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        tmp = (uint16_t*) pRxData ;
-        if(husart->Init.Parity == USART_PARITY_NONE)
-        {
-          *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-          pRxData += 2;
-        }
-        else
-        {
-          *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
-          pRxData += 1;
-        }
-      } 
-      else
-      {
-        /* Wait for TC flag in order to write data in DR */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TXE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        WRITE_REG(husart->Instance->DR, (*pTxData++ & (uint8_t)0x00FF));
-
-        /* Wait for RXNE Flag */
-        if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_RXNE, RESET, Timeout) != HAL_OK)
-        {
-          return HAL_TIMEOUT;
-        }
-        if(husart->Init.Parity == USART_PARITY_NONE)
-        {
-          /* Receive data */
-          *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
-        }
-        else
-        {
-          /* Receive data */
-          *pRxData++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
-        }
-      }
-    }
-
-    husart->State = HAL_USART_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  * @note   The USART errors are not managed to avoid the overrun error.
-  */
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pTxData == HAL_NULL) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX;
-
-    /* The USART Error Interrupts: (Frame error, Noise error, Overrun error) 
-       are not managed by the USART transmit process to avoid the overrun interrupt
-       when the USART mode is configured for transmit and receive "USART_MODE_TX_RX"
-       to benefit for the frame error and noise interrupts the USART mode should be
-       configured only for transmit "USART_MODE_TX"
-       The __HAL_USART_ENABLE_IT(husart, USART_IT_ERR) can be used to enable the Frame error,
-       Noise error interrupt */
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Enable the USART Transmit Data Register Empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Simplex Receive an amount of data in non-blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pRxData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pRxData == HAL_NULL) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->RxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Enable the USART Data Register not empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); 
-
-    /* Enable the USART Parity Error Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
-
-    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Send dummy byte in order to generate the clock for the slave to send data */
-    WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF));    
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer 
-  * @param  Size: Amount of data to be received
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size)
-{
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->RxXferCount = Size;
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
-    /* Enable the USART Data Register not empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_RXNE); 
-
-    /* Enable the USART Parity Error Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_PE);
-
-    /* Enable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_ERR);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    /* Enable the USART Transmit Data Register Empty Interrupt */
-    __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data buffer
-  * @param  Size: Amount of data to be sent
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
-{
-  uint32_t *tmp=0;
-  
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pTxData == HAL_NULL) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);  
-
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-    husart->TxXferCount = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX;
-
-    /* Set the USART DMA transfer complete callback */
-    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
-    /* Set the USART DMA Half transfer complete callback */
-    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
-    /* Set the DMA error callback */
-    husart->hdmatx->XferErrorCallback = USART_DMAError;
-
-    /* Enable the USART transmit DMA channel */
-    tmp = (uint32_t*)&pTxData;
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Receive an amount of data in non-blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pRxData: Pointer to data buffer
-  * @param  Size: Amount of data to be received
-  * @retval HAL status
-  * @note   The USART DMA transmit channel must be configured in order to generate the clock for the slave.
-  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
-  */
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t *tmp=0;
-  
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pRxData == HAL_NULL) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->pTxBuffPtr = pRxData;
-    husart->TxXferSize = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_RX;
-
-    /* Set the USART DMA Rx transfer complete callback */
-    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
-    /* Set the USART DMA Half transfer complete callback */
-    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
-    /* Set the USART DMA Rx transfer error callback */
-    husart->hdmarx->XferErrorCallback = USART_DMAError;
-
-    /* Enable the USART receive DMA channel */
-    tmp = (uint32_t*)&pRxData;
-    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
-
-    /* Enable the USART transmit DMA channel: the transmit channel is used in order
-       to generate in the non-blocking mode the clock to the slave device, 
-       this mode isn't a simplex receive mode but a full-duplex receive one */
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-
-    /* Clear the Overrun flag just before enabling the DMA Rx request: mandatory for the second transfer
-       when using the USART in circular mode */
-    __HAL_USART_CLEAR_OREFLAG(husart);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief  Full-Duplex Transmit Receive an amount of data in non-blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  pTxData: Pointer to data transmitted buffer
-  * @param  pRxData: Pointer to data received buffer 
-  * @param  Size: Amount of data to be received
-  * @note   When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
-{
-  uint32_t *tmp=0;
-  
-  if(husart->State == HAL_USART_STATE_READY)
-  {
-    if((pTxData == HAL_NULL) || (pRxData == HAL_NULL) || (Size == 0)) 
-    {
-      return HAL_ERROR;
-    }
-    /* Process Locked */
-    __HAL_LOCK(husart);
-
-    husart->pRxBuffPtr = pRxData;
-    husart->RxXferSize = Size;
-    husart->pTxBuffPtr = pTxData;
-    husart->TxXferSize = Size;
-
-    husart->ErrorCode = HAL_USART_ERROR_NONE;
-    husart->State = HAL_USART_STATE_BUSY_TX_RX;
-
-    /* Set the USART DMA Rx transfer complete callback */
-    husart->hdmarx->XferCpltCallback = USART_DMAReceiveCplt;
-
-    /* Set the USART DMA Half transfer complete callback */
-    husart->hdmarx->XferHalfCpltCallback = USART_DMARxHalfCplt;
-
-    /* Set the USART DMA Tx transfer complete callback */
-    husart->hdmatx->XferCpltCallback = USART_DMATransmitCplt;
-
-    /* Set the USART DMA Half transfer complete callback */
-    husart->hdmatx->XferHalfCpltCallback = USART_DMATxHalfCplt;
-
-    /* Set the USART DMA Tx transfer error callback */
-    husart->hdmatx->XferErrorCallback = USART_DMAError;
-
-    /* Set the USART DMA Rx transfer error callback */
-    husart->hdmarx->XferErrorCallback = USART_DMAError;
-
-    /* Enable the USART receive DMA channel */
-    tmp = (uint32_t*)&pRxData;
-    HAL_DMA_Start_IT(husart->hdmarx, (uint32_t)&husart->Instance->DR, *(uint32_t*)tmp, Size);
-
-    /* Enable the USART transmit DMA channel */
-    tmp = (uint32_t*)&pTxData;
-    HAL_DMA_Start_IT(husart->hdmatx, *(uint32_t*)tmp, (uint32_t)&husart->Instance->DR, Size);
-    
-    /* Clear the Overrun flag: mandatory for the second transfer in circular mode */
-    __HAL_USART_CLEAR_OREFLAG(husart);
-    
-    /* Enable the DMA transfer for the receiver request by setting the DMAR bit 
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-    /* Enable the DMA transfer for transmit request by setting the DMAT bit
-       in the USART CR3 register */
-    SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(husart);
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-/**
-  * @brief Pauses the DMA Transfer.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
-{
-  /* Process Locked */
-  __HAL_LOCK(husart);
-  
-  /* Disable the USART DMA Tx request */
-  CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_DMAT));
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK; 
-}
-
-/**
-  * @brief Resumes the DMA Transfer.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
-{
-  /* Process Locked */
-  __HAL_LOCK(husart);
-  
-  /* Enable the USART DMA Tx request */
-  SET_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(husart);
-
-  return HAL_OK;
-}
-
-/**
-  * @brief Stops the DMA Transfer.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
-{
-  /* The Lock is not implemented on this API to allow the user application
-     to call the HAL USART API under callbacks HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback():
-     when calling HAL_DMA_Abort() API the DMA TX/RX Transfer complete interrupt is generated
-     and the correspond call back is executed HAL_USART_TxCpltCallback() / HAL_USART_RxCpltCallback()
-     */
-
-  /* Abort the USART DMA Tx channel */
-  if(husart->hdmatx != HAL_NULL)
-  {
-    HAL_DMA_Abort(husart->hdmatx);
-  }
-  /* Abort the USART DMA Rx channel */
-  if(husart->hdmarx != HAL_NULL)
-  {  
-    HAL_DMA_Abort(husart->hdmarx);
-  }
-  
-  /* Disable the USART Tx/Rx DMA requests */
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-  CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-  husart->State = HAL_USART_STATE_READY;
-
-  return HAL_OK;
-}
-
-/**
-  * @brief  This function handles USART interrupt request.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
-{
-  uint32_t tmp1 = 0, tmp2 = 0;
-  
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_PE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_PE);
-  /* USART parity error interrupt occurred -----------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_USART_CLEAR_PEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_PE;
-  }
-
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_FE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART frame error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_USART_CLEAR_FEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_FE;
-  }
-
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_NE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART noise error interrupt occurred ------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_USART_CLEAR_NEFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_NE;
-  }
-
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_ORE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_ERR);
-  /* USART Over-Run interrupt occurred ---------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    __HAL_USART_CLEAR_OREFLAG(husart);
-    husart->ErrorCode |= HAL_USART_ERROR_ORE;
-  }
-
-  if(husart->ErrorCode != HAL_USART_ERROR_NONE)
-  {
-    /* Set the USART state ready to be able to start again the process */
-    husart->State = HAL_USART_STATE_READY;
-    
-    HAL_USART_ErrorCallback(husart);
-  }
-
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_RXNE);
-  /* USART in mode Receiver --------------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    if(husart->State == HAL_USART_STATE_BUSY_RX)
-    {
-      USART_Receive_IT(husart);
-    }
-    else
-    {
-      USART_TransmitReceive_IT(husart);
-    }
-  }
-
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TXE);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TXE);
-  /* USART in mode Transmitter -----------------------------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    if(husart->State == HAL_USART_STATE_BUSY_TX)
-    {
-      USART_Transmit_IT(husart);
-    }
-    else
-    {
-      USART_TransmitReceive_IT(husart);
-    }
-  }
-  
-  tmp1 = __HAL_USART_GET_FLAG(husart, USART_FLAG_TC);
-  tmp2 = __HAL_USART_GET_IT_SOURCE(husart, USART_IT_TC);
-  /* USART in mode Transmitter (transmission end) -----------------------------*/
-  if((tmp1 != RESET) && (tmp2 != RESET))
-  {
-    USART_EndTransmit_IT(husart);
-  } 
-
-}
-
-
-/**
-  * @brief  Tx Transfer completed callbacks.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
- __weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_TxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx Half Transfer completed callbacks.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
- __weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_TxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Transfer completed callbacks.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_RxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Rx Half Transfer completed callbacks.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_RxHalfCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  Tx/Rx Transfers completed callback for the non-blocking process.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
-__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_TxRxCpltCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  USART error callbacks.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
- __weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_USART_ErrorCallback could be implemented in the user file
-   */ 
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Exported_Functions_Group3 Peripheral State and Errors functions 
-  *  @brief   USART State and Errors functions 
-  *
-@verbatim   
-  ==============================================================================
-                  ##### Peripheral State and Errors functions #####
-  ==============================================================================  
-  [..]
-    This subsection provides a set of functions allowing to return the State of 
-    USART communication
-    process, return Peripheral Errors occurred during communication process
-     (+) HAL_USART_GetState() API can be helpful to check in run-time the state 
-         of the USART peripheral.
-     (+) HAL_USART_GetError() check in run-time errors that could be occurred during 
-         communication. 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the USART state.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL state
-  */
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
-{
-  return husart->State;
-}
-
-/**
-  * @brief  Return the USART error code
-  * @param  husart : pointer to a USART_HandleTypeDef structure that contains
-  *              the configuration information for the specified USART.
-  * @retval USART Error Code
-  */
-uint32_t HAL_USART_GetError(USART_HandleTypeDef *husart)
-{
-  return husart->ErrorCode;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Private_Functions   USART Private Functions
-  *  @brief   USART Private functions 
-  * @{
-  */
-/**
-  * @brief  DMA USART transmit process complete callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* DMA Normal mode */
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  {
-    husart->TxXferCount = 0;
-    if(husart->State == HAL_USART_STATE_BUSY_TX)
-    {
-      /* Wait for USART TC Flag */
-      if(USART_WaitOnFlagUntilTimeout(husart, USART_FLAG_TC, RESET, USART_TIMEOUT_VALUE) != HAL_OK)
-      {
-        /* Timeout occurred */ 
-        husart->State = HAL_USART_STATE_TIMEOUT;
-        HAL_USART_ErrorCallback(husart);
-      }
-      else
-      {
-        /* No Timeout */
-        /* Disable the DMA transfer for transmit request by setting the DMAT bit
-           in the USART CR3 register */
-        CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-        husart->State= HAL_USART_STATE_READY;
-        HAL_USART_TxCpltCallback(husart);
-      }
-    }
-  }
-  /* DMA Circular mode */
-  else
-  {
-    if(husart->State == HAL_USART_STATE_BUSY_TX)
-    {
-      HAL_USART_TxCpltCallback(husart);
-    }
-  }
-}
-
-/**
-  * @brief DMA USART transmit process half complete callback 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_USART_TxHalfCpltCallback(husart);
-}
-
-/**
-  * @brief  DMA USART receive process complete callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  /* DMA Normal mode */
-  if((hdma->Instance->CCR & DMA_CCR_CIRC) == 0)
-  {
-    husart->RxXferCount = 0;
-    if(husart->State == HAL_USART_STATE_BUSY_RX)
-    {
-      /* Disable the DMA transfer for the receiver requests by setting the DMAR bit 
-         in the USART CR3 register */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
-      HAL_USART_RxCpltCallback(husart);
-    }
-    /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
-    else
-    {
-      /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit 
-         in the USART CR3 register */
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-      CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
-      HAL_USART_TxRxCpltCallback(husart);
-    }
-    husart->State= HAL_USART_STATE_READY;
-  }
-  /* DMA circular mode */
-  else
-  {
-    if(husart->State == HAL_USART_STATE_BUSY_RX)
-    {
-      HAL_USART_RxCpltCallback(husart);
-    }
-    /* the usart state is HAL_USART_STATE_BUSY_TX_RX*/
-    else
-    {
-      HAL_USART_TxRxCpltCallback(husart);
-    }
-  }
-}
-
-/**
-  * @brief DMA USART receive process half complete callback 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
-{
-  USART_HandleTypeDef* husart = (USART_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
-
-  HAL_USART_RxHalfCpltCallback(husart); 
-}
-
-/**
-  * @brief  DMA USART communication error callback. 
-  * @param  hdma: Pointer to a DMA_HandleTypeDef structure that contains
-  *               the configuration information for the specified DMA module.
-  * @retval None
-  */
-static void USART_DMAError(DMA_HandleTypeDef *hdma)   
-{
-  USART_HandleTypeDef* husart = ( USART_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
-  husart->RxXferCount = 0;
-  husart->TxXferCount = 0;
-  husart->ErrorCode |= HAL_USART_ERROR_DMA;
-  husart->State= HAL_USART_STATE_READY;
-  
-  HAL_USART_ErrorCallback(husart);
-}
-
-/**
-  * @brief  This function handles USART Communication Timeout.
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @param  Flag: specifies the USART flag to check.
-  * @param  Status: The new Flag status (SET or RESET).
-  * @param  Timeout: Timeout duration
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
-{
-  uint32_t tickstart = 0;
-
-  /* Get tick */ 
-  tickstart = HAL_GetTick();
-
-  /* Wait until flag is set */
-  if(Status == RESET)
-  {
-    while(__HAL_USART_GET_FLAG(husart, Flag) == RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
-          husart->State= HAL_USART_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(husart);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  else
-  {
-    while(__HAL_USART_GET_FLAG(husart, Flag) != RESET)
-    {
-      /* Check for the Timeout */
-      if(Timeout != HAL_MAX_DELAY)
-      {
-        if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
-        {
-          /* Disable TXE, RXNE, PE and ERR (Frame error, noise error, overrun error) interrupts for the interrupt process */
-          __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-          __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
-          husart->State= HAL_USART_STATE_READY;
-
-          /* Process Unlocked */
-          __HAL_UNLOCK(husart);
-
-          return HAL_TIMEOUT;
-        }
-      }
-    }
-  }
-  return HAL_OK;
-}
-
-/**
-  * @brief  Simplex Send an amount of data in non-blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL status
-  * @note   The USART errors are not managed to avoid the overrun error.
-  */
-static HAL_StatusTypeDef USART_Transmit_IT(USART_HandleTypeDef *husart)
-{
-  uint16_t* tmp=0;
- 
-  if(husart->State == HAL_USART_STATE_BUSY_TX)
-  {
-    if(husart->Init.WordLength == USART_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) husart->pTxBuffPtr;
-      WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
-      if(husart->Init.Parity == USART_PARITY_NONE)
-      {
-        husart->pTxBuffPtr += 2;
-      }
-      else
-      {
-        husart->pTxBuffPtr += 1;
-      }
-    } 
-    else
-    { 
-      WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
-    }
-    
-    if(--husart->TxXferCount == 0)
-    {
-      /* Disable the USART Transmit data register empty Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-
-      /* Enable the USART Transmit Complete Interrupt */    
-      __HAL_USART_ENABLE_IT(husart, USART_IT_TC);
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY;
-  }
-}
-
-
-/**
-  * @brief  Wraps up transmission in non blocking mode.
-  * @param  husart: pointer to a USART_HandleTypeDef structure that contains
-  *                the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_EndTransmit_IT(USART_HandleTypeDef *husart)
-{
-  /* Disable the USART Transmit Complete Interrupt */    
-  __HAL_USART_DISABLE_IT(husart, USART_IT_TC);
-  
-  /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-  __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-    
-  husart->State = HAL_USART_STATE_READY;
-   
-  HAL_USART_TxCpltCallback(husart);
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Simplex Receive an amount of data in non-blocking mode. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
-{
-  uint16_t* tmp=0;
-  if(husart->State == HAL_USART_STATE_BUSY_RX)
-  {
-    if(husart->Init.WordLength == USART_WORDLENGTH_9B)
-    {
-      tmp = (uint16_t*) husart->pRxBuffPtr;
-      if(husart->Init.Parity == USART_PARITY_NONE)
-      {
-        *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-        husart->pRxBuffPtr += 2;
-      }
-      else
-      {
-        *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
-        husart->pRxBuffPtr += 1;
-      }
-      if(--husart->RxXferCount != 0x00) 
-      {
-        /* Send dummy byte in order to generate the clock for the slave to send the next data */
-        WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x01FF)); 
-      }
-    } 
-    else
-    {
-      if(husart->Init.Parity == USART_PARITY_NONE)
-      {
-        *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
-      }
-      else
-      {
-        *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
-      }
-
-      if(--husart->RxXferCount != 0x00) 
-      {
-        /* Send dummy byte in order to generate the clock for the slave to send the next data */
-        WRITE_REG(husart->Instance->DR, (DUMMY_DATA & (uint16_t)0x00FF));  
-      }
-    }
-
-    if(husart->RxXferCount == 0)
-    {
-      /* Disable the USART RXNE Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-
-      /* Disable the USART Parity Error Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-
-      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
-      husart->State = HAL_USART_STATE_READY;
-      HAL_USART_RxCpltCallback(husart);
-      
-      return HAL_OK;
-    }
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking). 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval HAL status
-  */
-static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
-{
-  uint16_t* tmp=0;
-
-  if(husart->State == HAL_USART_STATE_BUSY_TX_RX)
-  {
-    if(husart->TxXferCount != 0x00)
-    {
-      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_TXE) != RESET)
-      {
-        if(husart->Init.WordLength == USART_WORDLENGTH_9B)
-        {
-          tmp = (uint16_t*) husart->pTxBuffPtr;
-          WRITE_REG(husart->Instance->DR, (uint16_t)(*tmp & (uint16_t)0x01FF));
-          if(husart->Init.Parity == USART_PARITY_NONE)
-          {
-            husart->pTxBuffPtr += 2;
-          }
-          else
-          {
-            husart->pTxBuffPtr += 1;
-          }
-        } 
-        else
-        {
-          WRITE_REG(husart->Instance->DR, (uint8_t)(*husart->pTxBuffPtr++ & (uint8_t)0x00FF));
-        }
-        husart->TxXferCount--;
-
-        /* Check the latest data transmitted */
-        if(husart->TxXferCount == 0)
-        {
-           __HAL_USART_DISABLE_IT(husart, USART_IT_TXE);
-        }
-      }
-    }
-
-    if(husart->RxXferCount != 0x00)
-    {
-      if(__HAL_USART_GET_FLAG(husart, USART_FLAG_RXNE) != RESET)
-      {
-        if(husart->Init.WordLength == USART_WORDLENGTH_9B)
-        {
-          tmp = (uint16_t*) husart->pRxBuffPtr;
-          if(husart->Init.Parity == USART_PARITY_NONE)
-          {
-            *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x01FF);
-            husart->pRxBuffPtr += 2;
-          }
-          else
-          {
-            *tmp = (uint16_t)(husart->Instance->DR & (uint16_t)0x00FF);
-            husart->pRxBuffPtr += 1;
-          }
-        } 
-        else
-        {
-          if(husart->Init.Parity == USART_PARITY_NONE)
-          {
-            *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x00FF);
-          }
-          else
-          {
-            *husart->pRxBuffPtr++ = (uint8_t)(husart->Instance->DR & (uint8_t)0x007F);
-          }
-        }
-        husart->RxXferCount--;
-      }
-    }
-
-    /* Check the latest data received */
-    if(husart->RxXferCount == 0)
-    {
-      __HAL_USART_DISABLE_IT(husart, USART_IT_RXNE);
-
-      /* Disable the USART Parity Error Interrupt */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_PE);
-
-      /* Disable the USART Error Interrupt: (Frame error, noise error, overrun error) */
-      __HAL_USART_DISABLE_IT(husart, USART_IT_ERR);
-
-      husart->State = HAL_USART_STATE_READY;
-
-      HAL_USART_TxRxCpltCallback(husart);
-
-      return HAL_OK;
-    }
-
-    return HAL_OK;
-  }
-  else
-  {
-    return HAL_BUSY; 
-  }
-}
-
-/**
-  * @brief  Configures the USART peripheral. 
-  * @param  husart: Pointer to a USART_HandleTypeDef structure that contains
-  *                 the configuration information for the specified USART module.
-  * @retval None
-  */
-static void USART_SetConfig(USART_HandleTypeDef *husart)
-{
-  /* Check the parameters */
-  assert_param(IS_USART_INSTANCE(husart->Instance));
-  assert_param(IS_USART_POLARITY(husart->Init.CLKPolarity));
-  assert_param(IS_USART_PHASE(husart->Init.CLKPhase));
-  assert_param(IS_USART_LASTBIT(husart->Init.CLKLastBit));
-  assert_param(IS_USART_BAUDRATE(husart->Init.BaudRate));  
-  assert_param(IS_USART_WORD_LENGTH(husart->Init.WordLength));
-  assert_param(IS_USART_STOPBITS(husart->Init.StopBits));
-  assert_param(IS_USART_PARITY(husart->Init.Parity));
-  assert_param(IS_USART_MODE(husart->Init.Mode));
-
-  /* The LBCL, CPOL and CPHA bits have to be selected when both the transmitter and the
-     receiver are disabled (TE=RE=0) to ensure that the clock pulses function correctly. */
-  CLEAR_BIT(husart->Instance->CR1, ((uint32_t)(USART_CR1_TE | USART_CR1_RE)));
-
-  /*---------------------------- USART CR2 Configuration ---------------------*/
-  /* Configure the USART Clock, CPOL, CPHA and LastBit -----------------------*/
-  /* Set CPOL bit according to husart->Init.CLKPolarity value */
-  /* Set CPHA bit according to husart->Init.CLKPhase value */
-  /* Set LBCL bit according to husart->Init.CLKLastBit value */
-  /* Set Stop Bits: Set STOP[13:12] bits according to husart->Init.StopBits value */
-  /* Write to USART CR2 */
-  MODIFY_REG(husart->Instance->CR2, 
-             (uint32_t)(USART_CR2_CPHA | USART_CR2_CPOL | USART_CR2_CLKEN | USART_CR2_LBCL | USART_CR2_STOP),
-             ((uint32_t)(USART_CLOCK_ENABLED| husart->Init.CLKPolarity | husart->Init.CLKPhase| husart->Init.CLKLastBit | husart->Init.StopBits)));
-
-  /*-------------------------- USART CR1 Configuration -----------------------*/
-  /* Configure the USART Word Length, Parity and mode: 
-     Set the M bits according to husart->Init.WordLength value 
-     Set PCE and PS bits according to husart->Init.Parity value
-     Set TE and RE bits according to husart->Init.Mode value */
-  MODIFY_REG(husart->Instance->CR1, 
-             (uint32_t)(USART_CR1_M | USART_CR1_PCE | USART_CR1_PS | USART_CR1_TE | USART_CR1_RE),
-             (uint32_t)husart->Init.WordLength | husart->Init.Parity | husart->Init.Mode);
-
-  /*-------------------------- USART CR3 Configuration -----------------------*/  
-  /* Clear CTSE and RTSE bits */
-  CLEAR_BIT(husart->Instance->CR3, (uint32_t)(USART_CR3_RTSE | USART_CR3_CTSE));
-
-  /*-------------------------- USART BRR Configuration -----------------------*/
-  if((husart->Instance == USART1))
-  {
-    husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK2Freq(), husart->Init.BaudRate);
-  }
-  else
-  {
-    husart->Instance->BRR = USART_BRR(HAL_RCC_GetPCLK1Freq(), husart->Init.BaudRate);
-  }
-}
-
-/**
-  * @}
-  */
-
-#endif /* HAL_USART_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_usart.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,579 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_usart.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   This file contains all the functions prototypes for the USART 
-  *          firmware library.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_USART_H
-#define __STM32L1xx_HAL_USART_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup USART
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup USART_Exported_Types USART Exported Types
-  * @{
-  */ 
-
-
-/** 
-  * @brief USART Init Structure definition
-  */ 
-typedef struct
-{
-  uint32_t BaudRate;                  /*!< This member configures the Usart communication baud rate.
-                                           The baud rate is computed using the following formula:
-                                           - IntegerDivider = ((PCLKx) / (8 * (husart->Init.BaudRate)))
-                                           - FractionalDivider = ((IntegerDivider - ((uint32_t) IntegerDivider)) * 8) + 0.5 */
-
-  uint32_t WordLength;                /*!< Specifies the number of data bits transmitted or received in a frame.
-                                           This parameter can be a value of @ref USART_Word_Length */
-
-  uint32_t StopBits;                  /*!< Specifies the number of stop bits transmitted.
-                                           This parameter can be a value of @ref USART_Stop_Bits */
-
-  uint32_t Parity;                   /*!< Specifies the parity mode.
-                                           This parameter can be a value of @ref USART_Parity
-                                           @note When parity is enabled, the computed parity is inserted
-                                                 at the MSB position of the transmitted data (9th bit when
-                                                 the word length is set to 9 data bits; 8th bit when the
-                                                 word length is set to 8 data bits). */
- 
-  uint32_t Mode;                      /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
-                                           This parameter can be a value of @ref USART_Mode */
-
-  uint32_t CLKPolarity;               /*!< Specifies the steady state of the serial clock.
-                                           This parameter can be a value of @ref USART_Clock_Polarity */
-
-  uint32_t CLKPhase;                  /*!< Specifies the clock transition on which the bit capture is made.
-                                           This parameter can be a value of @ref USART_Clock_Phase */
-
-  uint32_t CLKLastBit;                /*!< Specifies whether the clock pulse corresponding to the last transmitted
-                                           data bit (MSB) has to be output on the SCLK pin in synchronous mode.
-                                           This parameter can be a value of @ref USART_Last_Bit */
-}USART_InitTypeDef;
-
-/** 
-  * @brief HAL State structures definition
-  */ 
-typedef enum
-{
-  HAL_USART_STATE_RESET             = 0x00,    /*!< Peripheral is not initialized   */
-  HAL_USART_STATE_READY             = 0x01,    /*!< Peripheral Initialized and ready for use */
-  HAL_USART_STATE_BUSY              = 0x02,    /*!< an internal process is ongoing */   
-  HAL_USART_STATE_BUSY_TX           = 0x12,    /*!< Data Transmission process is ongoing */ 
-  HAL_USART_STATE_BUSY_RX           = 0x22,    /*!< Data Reception process is ongoing */
-  HAL_USART_STATE_BUSY_TX_RX        = 0x32,    /*!< Data Transmission Reception process is ongoing */
-  HAL_USART_STATE_TIMEOUT           = 0x03,    /*!< Timeout state */
-  HAL_USART_STATE_ERROR             = 0x04     /*!< Error */
-}HAL_USART_StateTypeDef;
-
-/** 
-  * @brief  HAL USART Error Code structure definition  
-  */ 
-typedef enum
-{
-  HAL_USART_ERROR_NONE      = 0x00,    /*!< No error            */
-  HAL_USART_ERROR_PE        = 0x01,    /*!< Parity error        */
-  HAL_USART_ERROR_NE        = 0x02,    /*!< Noise error         */
-  HAL_USART_ERROR_FE        = 0x04,    /*!< frame error         */
-  HAL_USART_ERROR_ORE       = 0x08,    /*!< Overrun error       */
-  HAL_USART_ERROR_DMA       = 0x10     /*!< DMA transfer error  */
-}HAL_USART_ErrorTypeDef;
-
-/** 
-  * @brief  USART handle Structure definition  
-  */  
-typedef struct
-{
-  USART_TypeDef                 *Instance;        /* USART registers base address        */
-  
-  USART_InitTypeDef             Init;             /* Usart communication parameters      */
-  
-  uint8_t                       *pTxBuffPtr;      /* Pointer to Usart Tx transfer Buffer */
-  
-  uint16_t                      TxXferSize;       /* Usart Tx Transfer size              */
-  
-  __IO uint16_t                 TxXferCount;      /* Usart Tx Transfer Counter           */
-  
-  uint8_t                       *pRxBuffPtr;      /* Pointer to Usart Rx transfer Buffer */
-  
-  uint16_t                      RxXferSize;       /* Usart Rx Transfer size              */
-  
-  __IO uint16_t                 RxXferCount;      /* Usart Rx Transfer Counter           */  
-  
-  DMA_HandleTypeDef             *hdmatx;          /* Usart Tx DMA Handle parameters      */
-    
-  DMA_HandleTypeDef             *hdmarx;          /* Usart Rx DMA Handle parameters      */
-  
-  HAL_LockTypeDef                Lock;            /* Locking object                      */
-  
-  __IO HAL_USART_StateTypeDef    State;           /* Usart communication state           */
-  
-  __IO HAL_USART_ErrorTypeDef    ErrorCode;        /* USART Error code                    */
-  
-}USART_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup USART_Exported_Constants USART Exported constants
-  * @{
-  */
-
-/** @defgroup USART_Word_Length USART Word Length
-  * @{
-  */
-#define USART_WORDLENGTH_8B                  ((uint32_t)0x00000000)
-#define USART_WORDLENGTH_9B                  ((uint32_t)USART_CR1_M)
-#define IS_USART_WORD_LENGTH(LENGTH)     (((LENGTH) == USART_WORDLENGTH_8B) || \
-                                          ((LENGTH) == USART_WORDLENGTH_9B))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Stop_Bits USART Number of Stop Bits
-  * @{
-  */
-#define USART_STOPBITS_1                     ((uint32_t)0x00000000)
-#define USART_STOPBITS_0_5                   ((uint32_t)USART_CR2_STOP_0)
-#define USART_STOPBITS_2                     ((uint32_t)USART_CR2_STOP_1)
-#define USART_STOPBITS_1_5                   ((uint32_t)(USART_CR2_STOP_0 | USART_CR2_STOP_1))
-#define IS_USART_STOPBITS(STOPBITS)     (((STOPBITS) == USART_STOPBITS_1) || \
-                                         ((STOPBITS) == USART_STOPBITS_0_5) || \
-                                         ((STOPBITS) == USART_STOPBITS_1_5) || \
-                                         ((STOPBITS) == USART_STOPBITS_2))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Parity USART Parity
-  * @{
-  */ 
-#define USART_PARITY_NONE                    ((uint32_t)0x00000000)
-#define USART_PARITY_EVEN                    ((uint32_t)USART_CR1_PCE)
-#define USART_PARITY_ODD                     ((uint32_t)(USART_CR1_PCE | USART_CR1_PS)) 
-#define IS_USART_PARITY(PARITY)     (((PARITY) == USART_PARITY_NONE) || \
-                                     ((PARITY) == USART_PARITY_EVEN) || \
-                                     ((PARITY) == USART_PARITY_ODD))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Mode USART Mode
-  * @{
-  */ 
-#define USART_MODE_RX                        ((uint32_t)USART_CR1_RE)
-#define USART_MODE_TX                        ((uint32_t)USART_CR1_TE)
-#define USART_MODE_TX_RX                     ((uint32_t)(USART_CR1_TE |USART_CR1_RE))
-#define IS_USART_MODE(MODE) ((((MODE) & (uint32_t)0x0000FFF3) == 0x00) && ((MODE) != (uint32_t)0x00000000))
-/**
-  * @}
-  */
-    
-/** @defgroup USART_Clock USART Clock
-  * @{
-  */ 
-#define USART_CLOCK_DISABLED                 ((uint32_t)0x00000000)
-#define USART_CLOCK_ENABLED                  ((uint32_t)USART_CR2_CLKEN)
-#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_CLOCK_DISABLED) || \
-                               ((CLOCK) == USART_CLOCK_ENABLED))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Polarity USART Clock Polarity
-  * @{
-  */
-#define USART_POLARITY_LOW                   ((uint32_t)0x00000000)
-#define USART_POLARITY_HIGH                  ((uint32_t)USART_CR2_CPOL)
-#define IS_USART_POLARITY(CPOL) (((CPOL) == USART_POLARITY_LOW) || ((CPOL) == USART_POLARITY_HIGH))
-/**
-  * @}
-  */ 
-
-/** @defgroup USART_Clock_Phase USART Clock Phase
-  * @{
-  */
-#define USART_PHASE_1EDGE                    ((uint32_t)0x00000000)
-#define USART_PHASE_2EDGE                    ((uint32_t)USART_CR2_CPHA)
-#define IS_USART_PHASE(CPHA) (((CPHA) == USART_PHASE_1EDGE) || ((CPHA) == USART_PHASE_2EDGE))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Last_Bit USART Last Bit
-  * @{
-  */
-#define USART_LASTBIT_DISABLE                ((uint32_t)0x00000000)
-#define USART_LASTBIT_ENABLE                 ((uint32_t)USART_CR2_LBCL)
-#define IS_USART_LASTBIT(LASTBIT)   (((LASTBIT) == USART_LASTBIT_DISABLE) || \
-                                     ((LASTBIT) == USART_LASTBIT_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup USART_NACK_State USART NACK State
-  * @{
-  */
-#define USARTNACK_ENABLED           ((uint32_t)USART_CR3_NACK)
-#define USARTNACK_DISABLED          ((uint32_t)0x00000000)
-#define IS_USART_NACK_STATE(NACK)   (((NACK) == USARTNACK_ENABLED) || \
-                                     ((NACK) == USARTNACK_DISABLED))
-/**
-  * @}
-  */
-
-/** @defgroup USART_Flags USART Flags
-  *        Elements values convention: 0xXXXX
-  *           - 0xXXXX  : Flag mask in the SR register
-  * @{
-  */
-
-#define USART_FLAG_CTS                       ((uint32_t)USART_SR_CTS)
-#define USART_FLAG_LBD                       ((uint32_t)USART_SR_LBD)
-#define USART_FLAG_TXE                       ((uint32_t)USART_SR_TXE)
-#define USART_FLAG_TC                        ((uint32_t)USART_SR_TC)
-#define USART_FLAG_RXNE                      ((uint32_t)USART_SR_RXNE)
-#define USART_FLAG_IDLE                      ((uint32_t)USART_SR_IDLE)
-#define USART_FLAG_ORE                       ((uint32_t)USART_SR_ORE)
-#define USART_FLAG_NE                        ((uint32_t)USART_SR_NE)
-#define USART_FLAG_FE                        ((uint32_t)USART_SR_FE)
-#define USART_FLAG_PE                        ((uint32_t)USART_SR_PE)
-/**
-  * @}
-  */
-
-/** @defgroup USART_Interrupt_definition USART Interrupts Definition
-  *        Elements values convention: 0xY000XXXX
-  *           - XXXX  : Interrupt mask in the XX register
-  *           - Y  : Interrupt source register (4bits)
-  *                 - 01: CR1 register
-  *                 - 10: CR2 register
-  *                 - 11: CR3 register
-  *
-  * @{
-  */
-#define USART_IT_PE                          ((uint32_t)0x10000100)
-#define USART_IT_TXE                         ((uint32_t)0x10000080)
-#define USART_IT_TC                          ((uint32_t)0x10000040)
-#define USART_IT_RXNE                        ((uint32_t)0x10000020)
-#define USART_IT_IDLE                        ((uint32_t)0x10000010)
-
-#define USART_IT_LBD                         ((uint32_t)0x20000040)
-#define USART_IT_CTS                         ((uint32_t)0x30000400)
-
-#define USART_IT_ERR                         ((uint32_t)0x30000001)
-
-
-/**
-  * @}
-  */
-
-/** @defgroup USART_Interruption_Mask    USART interruptions flag mask
-  * @{
-  */ 
-#define USART_IT_MASK  ((uint32_t)0x0000FFFF)
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup USART_Exported_Macros USART Exported Macros
-  * @{
-  */
-
-
-/** @brief Reset USART handle state
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @retval None
-  */
-#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
-
-/** @brief  Checks whether the specified USART flag is set or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *        This parameter can be one of the following values:
-  *            @arg USART_FLAG_TXE:  Transmit data register empty flag
-  *            @arg USART_FLAG_TC:   Transmission Complete flag
-  *            @arg USART_FLAG_RXNE: Receive data register not empty flag
-  *            @arg USART_FLAG_IDLE: Idle Line detection flag
-  *            @arg USART_FLAG_ORE:  OverRun Error flag
-  *            @arg USART_FLAG_NE:   Noise Error flag
-  *            @arg USART_FLAG_FE:   Framing Error flag
-  *            @arg USART_FLAG_PE:   Parity Error flag
-  * @retval The new state of __FLAG__ (TRUE or FALSE).
-  */
-
-#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/** @brief  Clears the specified USART pending flags.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @param  __FLAG__: specifies the flag to check.
-  *          This parameter can be any combination of the following values:
-  *            @arg USART_FLAG_TC:   Transmission Complete flag.
-  *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
-  *   
-  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
-  *          error) and IDLE (Idle line detected) flags are cleared by software 
-  *          sequence: a read operation to USART_SR register followed by a read
-  *          operation to USART_DR register.
-  * @note   RXNE flag can be also cleared by a read to the USART_DR register.
-  * @note   TC flag can be also cleared by software sequence: a read operation to 
-  *          USART_SR register followed by a write operation to USART_DR register.
-  * @note   TXE flag is cleared only by a write to the USART_DR register.
-  *   
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__)  ((__HANDLE__)->Instance->SR = ~(__FLAG__))
-
-/** @brief  Clear the USART PE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_PEFLAG(__HANDLE__) do{(__HANDLE__)->Instance->SR;\
-                                                (__HANDLE__)->Instance->DR;}while(0)
-/** @brief  Clear the USART FE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART NE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART ORE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Clear the USART IDLE pending flag.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @retval None
-  */
-#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
-
-/** @brief  Enables or disables the specified Usart interrupts.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @param  __INTERRUPT__: specifies the USART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
-  *            @arg USART_IT_TC:   Transmission complete interrupt
-  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg USART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_PE:   Parity Error interrupt
-  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
-  * @retval None
-  */
-#define __HAL_USART_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 |= ((__INTERRUPT__) & USART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 |=  ((__INTERRUPT__) & USART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & USART_IT_MASK)))
-#define __HAL_USART_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((((__INTERRUPT__) >> 28) == 1)? ((__HANDLE__)->Instance->CR1 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
-                                                           (((__INTERRUPT__) >> 28) == 2)? ((__HANDLE__)->Instance->CR2 &= ~((__INTERRUPT__) & USART_IT_MASK)): \
-                                                           ((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
-
-
-    
-/** @brief  Checks whether the specified Usart interrupt has occurred or not.
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         This parameter can be USARTx where x: 1, 2 or 3 to select the USART peripheral.
-  * @param  __IT__: specifies the USART interrupt source to check.
-  *          This parameter can be one of the following values:
-  *            @arg USART_IT_TXE: Transmit Data Register empty interrupt
-  *            @arg USART_IT_TC:  Transmission complete interrupt
-  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
-  *            @arg USART_IT_IDLE: Idle line detection interrupt
-  *            @arg USART_IT_ERR: Error interrupt
-  *            @arg USART_IT_PE: Parity Error interrupt
-  * @retval The new state of __IT__ (TRUE or FALSE).
-  */
-#define __HAL_USART_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28) == 1)? (__HANDLE__)->Instance->CR1:(((((uint32_t)(__IT__)) >> 28) == 2)? \
-                                                      (__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
-
-/** @brief  Enable USART
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         The Handle Instance can be USARTx where x: 1, 2, 3 to select the USART peripheral
-  * @retval None
-  */ 
-#define __HAL_USART_ENABLE(__HANDLE__)               SET_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) 
-
-/** @brief  Disable USART
-  * @param  __HANDLE__: specifies the USART Handle.
-  *         The Handle Instance can be USARTx where x: 1, 2, 3 to select the USART peripheral
-  * @retval None
-  */ 
-#define __HAL_USART_DISABLE(__HANDLE__)              CLEAR_BIT((__HANDLE__)->Instance->CR1,(USART_CR1_UE)) 
- 
-
-/**
-  * @}
-  */
-
-/* Private macros --------------------------------------------------------*/
-/** @defgroup USART_Private_Macros   USART Private Macros
-  * @{
-  */
-
-#define USART_DIV(__PCLK__, __BAUD__)                (((__PCLK__)*25)/(4*(__BAUD__)))
-#define USART_DIVMANT(__PCLK__, __BAUD__)            (USART_DIV((__PCLK__), (__BAUD__))/100)
-#define USART_DIVFRAQ(__PCLK__, __BAUD__)            (((USART_DIV((__PCLK__), (__BAUD__)) - (USART_DIVMANT((__PCLK__), (__BAUD__)) * 100)) * 16 + 50) / 100)
-#define USART_BRR(__PCLK__, __BAUD__)                ((USART_DIVMANT((__PCLK__), (__BAUD__)) << 4)|(USART_DIVFRAQ((__PCLK__), (__BAUD__)) & 0x0F))
-
-/** @brief  Check USART Baud rate
-  * @param  __BAUDRATE__: Baudrate specified by the user
-  *         The maximum Baud Rate is derived from the maximum clock on APB (i.e. 32 MHz) 
-  *         divided by the smallest oversampling used on the USART (i.e. 8)  
-  * @retval Test result (TRUE or FALSE) 
-  */ 
-#define IS_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 4000001)
-/**
-  * @}
-  */
-
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup USART_Exported_Functions USART Exported Functions
-  * @{
-  */
-  
-/** @addtogroup USART_Exported_Functions_Group1 USART Initialization and de-initialization functions 
-  * @{
-  */
-
-/* Initialization and de-initialization functions  ******************************/
-HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspInit(USART_HandleTypeDef *husart);
-void HAL_USART_MspDeInit(USART_HandleTypeDef *husart);
-
-/**
-  * @}
-  */
-
-/** @addtogroup USART_Exported_Functions_Group2 IO operation functions 
-  * @{
-  */
-
-/* IO operation functions *******************************************************/
-HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout);
-HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData,  uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_Receive_DMA(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_TransmitReceive_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size);
-HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart);
-HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart);
-void HAL_USART_IRQHandler(USART_HandleTypeDef *husart);
-void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart);
-void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart);
-
-/**
-  * @}
-  */
-
-/* Peripheral Control functions ***********************************************/
-
-/** @addtogroup USART_Exported_Functions_Group3 Peripheral State and Errors functions 
-  * @{
-  */
-
-/* Peripheral State and Error functions ***************************************/
-HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart);
-uint32_t               HAL_USART_GetError(USART_HandleTypeDef *husart);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_USART_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,444 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_wwdg.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   WWDG HAL module driver.
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Window Watchdog (WWDG) peripheral:
-  *           + Initialization and de-initialization functions
-  *           + IO operation functions
-  *           + Peripheral State functions       
-  @verbatim
-  ==============================================================================
-                      ##### WWDG specific features #####
-  ==============================================================================
-  [..] 
-    Once enabled the WWDG generates a system reset on expiry of a programmed
-    time period, unless the program refreshes the counter (downcounter) 
-    before reaching 0x3F value (i.e. a reset is generated when the counter
-    value rolls over from 0x40 to 0x3F). 
-       
-    (+) An MCU reset is also generated if the counter value is refreshed
-        before the counter has reached the refresh window value. This 
-        implies that the counter must be refreshed in a limited window.
-    (+) Once enabled the WWDG cannot be disabled except by a system reset.
-    (+) WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
-        reset occurs.               
-    (+) The WWDG counter input clock is derived from the APB clock divided 
-        by a programmable prescaler.
-    (+) WWDG clock (Hz) = PCLK1 / (4096 * Prescaler)
-    (+) WWDG timeout (mS) = 1000 * Counter / WWDG clock
-    (+) WWDG Counter refresh is allowed between the following limits :
-        (++) min time (mS) = 1000 * (Counter – Window) / WWDG clock
-        (++) max time (mS) = 1000 * (Counter – 0x40) / WWDG clock
-    
-    (+) Min-max timeout value at @32MHz (PCLK1): ~128us / ~65.6ms.
-
-
-                     ##### How to use this driver #####
-  ==============================================================================
-  [..]
-    (+) Enable WWDG APB1 clock using __WWDG_CLK_ENABLE().
-    (+) Set the WWDG prescaler, refresh window and counter value 
-        using HAL_WWDG_Init() function.
-    (+) Start the WWDG using HAL_WWDG_Start() function.
-        When the WWDG is enabled the counter value should be configured to 
-        a value greater than 0x40 to prevent generating an immediate reset.
-    (+) Optionally you can enable the Early Wakeup Interrupt (EWI) which is 
-        generated when the counter reaches 0x40, and then start the WWDG using
-        HAL_WWDG_Start_IT(). At EWI HAL_WWDG_WakeupCallback is executed and user can 
-        add his own code by customization of function pointer HAL_WWDG_WakeupCallback
-        Once enabled, EWI interrupt cannot be disabled except by a system reset.          
-    (+) Then the application program must refresh the WWDG counter at regular
-        intervals during normal operation to prevent an MCU reset, using
-        HAL_WWDG_Refresh() function. This operation must occur only when
-        the counter is lower than the refresh window value already programmed.
-        
-     *** WWDG HAL driver macros list ***
-     ==================================
-     [..]
-       Below the list of most used macros in WWDG HAL driver.
-       
-      (+) __HAL_WWDG_ENABLE: Enable the WWDG peripheral 
-      (+) __HAL_WWDG_GET_FLAG: Get the selected WWDG's flag status
-      (+) __HAL_WWDG_CLEAR_FLAG: Clear the WWDG's pending flags 
-      (+) __HAL_WWDG_ENABLE_IT:  Enables the WWDG early wakeup interrupt 
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup WWDG WWDG
-  * @brief WWDG HAL module driver.
-  * @{
-  */
-
-#ifdef HAL_WWDG_MODULE_ENABLED
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Functions WWDG Exported Functions
-  * @{
-  */
-
-/** @defgroup WWDG_Exported_Functions_Group1 Initialization and de-initialization functions 
- *  @brief    Initialization and Configuration functions. 
- *
-@verbatim    
-  ==============================================================================
-          ##### Initialization and de-initialization functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize the WWDG according to the specified parameters 
-        in the WWDG_InitTypeDef and create the associated handle
-    (+) DeInitialize the WWDG peripheral
-    (+) Initialize the WWDG MSP
-    (+) DeInitialize the WWDG MSP 
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the WWDG according to the specified
-  *         parameters in the WWDG_InitTypeDef and creates the associated handle.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Check the WWDG handle allocation */
-  if(hwwdg == HAL_NULL)
-  {
-    return HAL_ERROR;
-  }
-  
-  /* Check the parameters */
-  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
-  assert_param(IS_WWDG_PRESCALER(hwwdg->Init.Prescaler));
-  assert_param(IS_WWDG_WINDOW(hwwdg->Init.Window)); 
-  assert_param(IS_WWDG_COUNTER(hwwdg->Init.Counter)); 
-  
-  if(hwwdg->State == HAL_WWDG_STATE_RESET)
-  {
-    /* Init the low level hardware */
-    HAL_WWDG_MspInit(hwwdg);
-  }
-  
-  /* Change WWDG peripheral state */
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-
-  /* Set WWDG Prescaler and Window */
-  MODIFY_REG(hwwdg->Instance->CFR, (WWDG_CFR_WDGTB | WWDG_CFR_W), (hwwdg->Init.Prescaler | hwwdg->Init.Window));
-
-  /* Set WWDG Counter */
-  MODIFY_REG(hwwdg->Instance->CR, WWDG_CR_T, hwwdg->Init.Counter);
-   
-  /* Change WWDG peripheral state */
-  hwwdg->State = HAL_WWDG_STATE_READY;
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  DeInitializes the WWDG peripheral. 
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg)
-{   
-  /* Check the parameters */
-  assert_param(IS_WWDG_ALL_INSTANCE(hwwdg->Instance));
-
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-  
-  /* DeInit the low level hardware */
-  HAL_WWDG_MspDeInit(hwwdg);
-  
-  /* Reset WWDG Control register */
-  hwwdg->Instance->CR  = (uint32_t)0x0000007F;
-  
-  /* Reset WWDG Configuration register */
-  hwwdg->Instance->CFR = (uint32_t)0x0000007F;
-  
-  /* Reset WWDG Status register */
-  hwwdg->Instance->SR  = 0; 
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_RESET; 
-
-  /* Release Lock */
-  __HAL_UNLOCK(hwwdg);
-
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Initializes the WWDG MSP.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval None
-  */
-__weak void HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_WWDG_MspInit could be implemented in the user file
-   */
-}
-
-/**
-  * @brief  DeInitializes the WWDG MSP.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval None
-  */
-__weak void HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_WWDG_MspDeInit could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Exported_Functions_Group2 IO operation functions 
- *  @brief    IO operation functions 
- *
-@verbatim   
-  ==============================================================================
-                       ##### IO operation functions #####
-  ==============================================================================  
-  [..]  
-    This section provides functions allowing to:
-    (+) Start the WWDG.
-    (+) Refresh the WWDG.
-    (+) Handle WWDG interrupt request. 
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Starts the WWDG.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg)
-{
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
-  
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-
-  /* Enable the peripheral */
-  __HAL_WWDG_ENABLE(hwwdg);  
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hwwdg);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Starts the WWDG with interrupt enabled.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg)
-{   
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
-  
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-  
-  /* Enable the Early Wakeup Interrupt */ 
-  __HAL_WWDG_ENABLE_IT(WWDG_IT_EWI);
-
-  /* Enable the peripheral */
-  __HAL_WWDG_ENABLE(hwwdg);  
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Refreshes the WWDG.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @param  Counter: value of counter to put in WWDG counter
-  * @retval HAL status
-  */
-HAL_StatusTypeDef HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter)
-{
-  /* Process Locked */
-  __HAL_LOCK(hwwdg); 
-  
-  /* Change WWDG peripheral state */  
-  hwwdg->State = HAL_WWDG_STATE_BUSY;
-  
-  /* Check the parameters */
-  assert_param(IS_WWDG_COUNTER(Counter));
-  
-  /* Write to WWDG CR the WWDG Counter value to refresh with */
-  MODIFY_REG(hwwdg->Instance->CR, (uint32_t)WWDG_CR_T, Counter);
-  
-  /* Change WWDG peripheral state */    
-  hwwdg->State = HAL_WWDG_STATE_READY; 
-  
-  /* Process Unlocked */
-  __HAL_UNLOCK(hwwdg);
-  
-  /* Return function status */
-  return HAL_OK;
-}
-
-/**
-  * @brief  Handles WWDG interrupt request.
-  * @note   The Early Wakeup Interrupt (EWI) can be used if specific safety operations 
-  *         or data logging must be performed before the actual reset is generated. 
-  *         The EWI interrupt is enabled using __HAL_WWDG_ENABLE_IT() macro.
-  *         When the downcounter reaches the value 0x40, and EWI interrupt is 
-  *         generated and the corresponding Interrupt Service Routine (ISR) can 
-  *         be used to trigger specific actions (such as communications or data 
-  *         logging), before resetting the device. 
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval None
-  */
-void HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg)
-{ 
-  /* WWDG Early Wakeup Interrupt occurred */   
-  if(__HAL_WWDG_GET_FLAG(hwwdg, WWDG_FLAG_EWIF) != RESET)
-  {
-    /* Early Wakeup callback */ 
-    HAL_WWDG_WakeupCallback(hwwdg);
-    
-    /* Change WWDG peripheral state */
-    hwwdg->State = HAL_WWDG_STATE_READY; 
-    
-    /* Clear the WWDG Data Ready flag */
-    __HAL_WWDG_CLEAR_IT(hwwdg, WWDG_FLAG_EWIF);
-    
-    /* Process Unlocked */
-    __HAL_UNLOCK(hwwdg);
-  }
-} 
-
-/**
-  * @brief  Early Wakeup WWDG callback.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval None
-  */
-__weak void HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg)
-{
-  /* NOTE: This function Should not be modified, when the callback is needed,
-           the HAL_WWDG_WakeupCallback could be implemented in the user file
-   */
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Exported_Functions_Group3 Peripheral State functions 
- *  @brief    Peripheral State functions. 
- *
-@verbatim   
-  ==============================================================================
-                        ##### Peripheral State functions #####
-  ==============================================================================  
-  [..]
-    This subsection permits to get in run-time the status of the peripheral 
-    and the data flow.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Returns the WWDG state.
-  * @param  hwwdg: pointer to a WWDG_HandleTypeDef structure that contains
-  *              the configuration information for the specified WWDG module.
-  * @retval HAL state
-  */
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg)
-{
-  return hwwdg->State;
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* HAL_WWDG_MODULE_ENABLED */
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_hal_wwdg.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,310 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_hal_wwdg.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of WWDG HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_HAL_WWDG_H
-#define __STM32L1xx_HAL_WWDG_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup WWDG
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Types WWDG Exported Types
-  * @{
-  */
-   
-/**
-  * @brief  WWDG HAL State Structure definition
-  */
-typedef enum
-{
-  HAL_WWDG_STATE_RESET     = 0x00,  /*!< WWDG not yet initialized or disabled */
-  HAL_WWDG_STATE_READY     = 0x01,  /*!< WWDG initialized and ready for use   */
-  HAL_WWDG_STATE_BUSY      = 0x02,  /*!< WWDG internal process is ongoing     */
-  HAL_WWDG_STATE_TIMEOUT   = 0x03,  /*!< WWDG timeout state                   */
-  HAL_WWDG_STATE_ERROR     = 0x04   /*!< WWDG error state                     */
-}HAL_WWDG_StateTypeDef;
-
-/** 
-  * @brief  WWDG Init structure definition  
-  */ 
-typedef struct
-{
-  uint32_t Prescaler;  /*!< Specifies the prescaler value of the WWDG.
-                            This parameter can be a value of @ref WWDG_Prescaler */
-  
-  uint32_t Window;     /*!< Specifies the WWDG window value to be compared to the downcounter.
-                            This parameter must be a number lower than Max_Data = 0x80 */ 
-  
-  uint32_t Counter;    /*!< Specifies the WWDG free-running downcounter value.
-                            This parameter must be a number between Min_Data = 0x40 and Max_Data = 0x7F */
-
-}WWDG_InitTypeDef;
-
-/** 
-  * @brief  WWDG handle Structure definition  
-  */ 
-typedef struct
-{
-  WWDG_TypeDef                 *Instance;  /*!< Register base address    */
-  
-  WWDG_InitTypeDef             Init;       /*!< WWDG required parameters */
-  
-  HAL_LockTypeDef              Lock;       /*!< WWDG locking object      */
-  
-  __IO HAL_WWDG_StateTypeDef   State;      /*!< WWDG communication state */
-  
-}WWDG_HandleTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Constants WWDG Exported Constants
-  * @{
-  */
-
-/** @defgroup WWDG_BitAddress_AliasRegion WWDG BitAddress AliasRegion
-  * @brief WWDG registers bit address in the alias region
-  * @{
-  */
-
-/* --- CFR Register ---*/
-/* Alias word address of EWI bit */
-#define CFR_BASE   (uint32_t)(WWDG_BASE + 0x04)
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Interrupt_definition WWDG Interrupt definition
-  * @{
-  */ 
-#define WWDG_IT_EWI   ((uint32_t)WWDG_CFR_EWI)  
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Flag_definition WWDG Flag definition
-  * @brief WWDG Flag definition
-  * @{
-  */ 
-#define WWDG_FLAG_EWIF   ((uint32_t)WWDG_SR_EWIF)  /*!< Early wakeup interrupt flag */
-
-/**
-  * @}
-  */
-
-/** @defgroup WWDG_Prescaler WWDG Prescaler
-  * @{
-  */ 
-#define WWDG_PRESCALER_1   ((uint32_t)0x00000000)  /*!< WWDG counter clock = (PCLK1/4096)/1 */
-#define WWDG_PRESCALER_2   ((uint32_t)WWDG_CFR_WDGTB0)  /*!< WWDG counter clock = (PCLK1/4096)/2 */
-#define WWDG_PRESCALER_4   ((uint32_t)WWDG_CFR_WDGTB1)  /*!< WWDG counter clock = (PCLK1/4096)/4 */
-#define WWDG_PRESCALER_8   ((uint32_t)WWDG_CFR_WDGTB)  /*!< WWDG counter clock = (PCLK1/4096)/8 */
-
-#define IS_WWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == WWDG_PRESCALER_1) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_2) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_4) || \
-                                          ((__PRESCALER__) == WWDG_PRESCALER_8))
-
-/**
-  * @}
-  */ 
-
-/** @defgroup WWDG_Window WWDG Window
-  * @{
-  */ 
-#define IS_WWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= 0x7F)
-
-/**
-  * @}
-  */ 
-
-/** @defgroup WWDG_Counter WWDG Counter
-  * @{
-  */ 
-#define IS_WWDG_COUNTER(__COUNTER__) (((__COUNTER__) >= 0x40) && ((__COUNTER__) <= 0x7F))
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup WWDG_Exported_Macros WWDG Exported Macros
-  * @{
-  */
-
-/** @brief Reset WWDG handle state
-  * @param  __HANDLE__: WWDG handle
-  * @retval None
-  */
-#define __HAL_WWDG_RESET_HANDLE_STATE(__HANDLE__)   ((__HANDLE__)->State = HAL_WWDG_STATE_RESET)
-
-/**
-  * @brief  Enables the WWDG peripheral.
-  * @param  __HANDLE__: WWDG handle
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE(__HANDLE__)               SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA)
-
-/**
-  * @brief  Gets the selected WWDG's flag status.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __FLAG__: specifies the flag to check.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  * @retval The new state of WWDG_FLAG (SET or RESET).
-  */
-#define __HAL_WWDG_GET_FLAG(__HANDLE__, __FLAG__)   (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
-
-/**
-  * @brief  Clears the WWDG's pending flags.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __FLAG__: specifies the flag to clear.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  * @retval None
-  */
-#define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
-
-/**
-  * @brief  Enables the WWDG early wakeup interrupt.
-  * @param  __INTERRUPT__: specifies the interrupt to enable.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_IT_EWI: Early wakeup interrupt
-  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
-  * @retval None
-  */
-#define __HAL_WWDG_ENABLE_IT(__INTERRUPT__)         (*(__IO uint32_t *) CFR_BASE |= (__INTERRUPT__))
-
-/** @brief  Clear the WWDG's interrupt pending bits
-  *         bits to clear the selected interrupt pending bits.
-  * @param  __HANDLE__: WWDG handle
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear.
-  *         This parameter can be one of the following values:
-  *            @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag
-  */
-#define __HAL_WWDG_CLEAR_IT(__HANDLE__, __INTERRUPT__) __HAL_WWDG_CLEAR_FLAG((__HANDLE__), (__INTERRUPT__))
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup WWDG_Exported_Functions
-  * @{
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group1
-  * @{
-  */
-/* Initialization/de-initialization functions  **********************************/
-HAL_StatusTypeDef     HAL_WWDG_Init(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef     HAL_WWDG_DeInit(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_MspInit(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_MspDeInit(WWDG_HandleTypeDef *hwwdg);
-void                  HAL_WWDG_WakeupCallback(WWDG_HandleTypeDef* hwwdg);
-
-/**
-  * @}
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group2
-  * @{
-  */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef     HAL_WWDG_Start(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef     HAL_WWDG_Start_IT(WWDG_HandleTypeDef *hwwdg);
-HAL_StatusTypeDef     HAL_WWDG_Refresh(WWDG_HandleTypeDef *hwwdg, uint32_t Counter);
-void                  HAL_WWDG_IRQHandler(WWDG_HandleTypeDef *hwwdg);
-
-/**
-  * @}
-  */
-
-/** @addtogroup WWDG_Exported_Functions_Group3
-  * @{
-  */
-/* Peripheral State functions  **************************************************/
-HAL_WWDG_StateTypeDef HAL_WWDG_GetState(WWDG_HandleTypeDef *hwwdg);
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_HAL_WWDG_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,359 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_fsmc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   FSMC Low Layer HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the Flexible Static Memory Controller (FSMC) peripheral memories:
-  *           + Initialization/de-initialization functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  =============================================================================
-                        ##### FSMC peripheral features #####
-  =============================================================================
-    [..] The Flexible static memory controller (FSMC) includes following memory controllers:
-         (+) The NOR/PSRAM memory controller
-       
-    [..] The FSMC functional block makes the interface with synchronous and asynchronous static
-         memories and SDRAM memories. Its main purposes are:
-         (+) to translate AHB transactions into the appropriate external device protocol.
-         (+) to meet the access time requirements of the external memory devices.
-   
-    [..] All external memories share the addresses, data and control signals with the controller.
-         Each external device is accessed by means of a unique Chip Select. The FSMC performs
-         only one access at a time to an external device.
-         The main features of the FSMC controller are the following:
-          (+) Interface with static-memory mapped devices including:
-             (++) Static random access memory (SRAM).
-             (++) NOR Flash memory.
-             (++) PSRAM (4 memory banks).
-          (+) Independent Chip Select control for each memory bank.
-          (+) Independent configuration for each memory bank.          
-        
-  =============================================================================
-                   ##### How to use NORSRAM device driver #####
-  =============================================================================
- 
-  [..] 
-    This driver contains a set of APIs to interface with the FSMC NORSRAM banks in order
-    to run the NORSRAM external devices.
-      
-    (+) FSMC NORSRAM bank reset using the function FSMC_NORSRAM_DeInit() 
-    (+) FSMC NORSRAM bank control configuration using the function FSMC_NORSRAM_Init()
-    (+) FSMC NORSRAM bank timing configuration using the function FSMC_NORSRAM_Timing_Init()
-    (+) FSMC NORSRAM bank extended timing configuration using the function 
-        FSMC_NORSRAM_Extended_Timing_Init()
-    (+) FSMC NORSRAM bank enable/disable write operation using the functions
-        FSMC_NORSRAM_WriteOperation_Enable()/FSMC_NORSRAM_WriteOperation_Disable()
-
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup FSMC_LL FSMC_LL
-  * @brief FSMC driver modules
-  * @{
-  */
-
-#if defined (HAL_SRAM_MODULE_ENABLED) || defined(HAL_NOR_MODULE_ENABLED)
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/    
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup FSMC_Exported_Functions FSMC Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_FSMC_NORSRAM_Group1 Initialization/de-initialization functions 
-  * @brief    Initialization and Configuration functions 
-  *
-  @verbatim    
-  ==============================================================================
-              ##### Initialization and de_initialization functions #####
-  ==============================================================================
-  [..]  
-    This section provides functions allowing to:
-    (+) Initialize and configure the FSMC NORSRAM interface
-    (+) De-initialize the FSMC NORSRAM interface 
-    (+) Configure the FSMC clock and associated GPIOs    
- 
-@endverbatim
-  * @{
-  */
-  
-/**
-  * @brief  Initialize the FSMC_NORSRAM device according to the specified
-  *         control parameters in the FSMC_NORSRAM_InitTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Init: Pointer to NORSRAM Initialization structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef* Init)
-{ 
-  uint32_t tmpr = 0;
-    
-  /* Check the parameters */
-  assert_param(IS_FSMC_NORSRAM_BANK(Init->NSBank));
-  assert_param(IS_FSMC_MUX(Init->DataAddressMux));
-  assert_param(IS_FSMC_MEMORY(Init->MemoryType));
-  assert_param(IS_FSMC_NORSRAM_MEMORY_WIDTH(Init->MemoryDataWidth));
-  assert_param(IS_FSMC_BURSTMODE(Init->BurstAccessMode));
-  assert_param(IS_FSMC_WAIT_POLARITY(Init->WaitSignalPolarity));
-  assert_param(IS_FSMC_WRAP_MODE(Init->WrapMode));
-  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(Init->WaitSignalActive));
-  assert_param(IS_FSMC_WRITE_OPERATION(Init->WriteOperation));
-  assert_param(IS_FSMC_WAITE_SIGNAL(Init->WaitSignal));
-  assert_param(IS_FSMC_EXTENDED_MODE(Init->ExtendedMode));
-  assert_param(IS_FSMC_ASYNWAIT(Init->AsynchronousWait));
-  assert_param(IS_FSMC_WRITE_BURST(Init->WriteBurst));
-  
-  /* Set NORSRAM device control parameters */
-  tmpr = (uint32_t)(Init->DataAddressMux       |\
-                    Init->MemoryType           |\
-                    Init->MemoryDataWidth      |\
-                    Init->BurstAccessMode      |\
-                    Init->WaitSignalPolarity   |\
-                    Init->WrapMode             |\
-                    Init->WaitSignalActive     |\
-                    Init->WriteOperation       |\
-                    Init->WaitSignal           |\
-                    Init->ExtendedMode         |\
-                    Init->AsynchronousWait     |\
-                    Init->WriteBurst
-                    );
-                    
-  if(Init->MemoryType == FSMC_MEMORY_TYPE_NOR)
-  {
-    tmpr |= (uint32_t)FSMC_NORSRAM_FLASH_ACCESS_ENABLE;
-  }
-  
-  Device->BTCR[Init->NSBank] = tmpr;                   
-  
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  DeInitialize the FSMC_NORSRAM peripheral 
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  ExDevice: Pointer to NORSRAM extended mode device instance  
-  * @param  Bank: NORSRAM bank number  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank)
-{
-  /* Check the parameters */
-  assert_param(IS_FSMC_NORSRAM_DEVICE(Device));
-  assert_param(IS_FSMC_NORSRAM_EXTENDED_DEVICE(ExDevice));
-
-  /* Disable the FSMC_NORSRAM device */
-  __FSMC_NORSRAM_DISABLE(Device, Bank);
-  
-  /* De-initialize the FSMC_NORSRAM device */
-  /* FSMC_NORSRAM_BANK1 */
-  if(Bank == FSMC_BANK1_NORSRAM1)
-  {
-    Device->BTCR[Bank] = 0x000030DB;    
-  }
-  /* FSMC_BANK1_NORSRAM2, FSMC_BANK1_NORSRAM3 or FSMC_BANK1_NORSRAM4 */
-  else
-  {   
-    Device->BTCR[Bank] = 0x000030D2; 
-  }
-  
-  Device->BTCR[Bank + 1] = 0x0FFFFFFF;
-  ExDevice->BWTR[Bank]   = 0x0FFFFFFF;
-   
-  return HAL_OK;
-}
-
-
-/**
-  * @brief  Initialize the FSMC_NORSRAM Timing according to the specified
-  *         parameters in the FSMC_NORSRAM_TimingTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Timing: Pointer to NORSRAM Timing structure
-  * @param  Bank: NORSRAM bank number  
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
-{
-  uint32_t tmpr = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
-  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
-  assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
-  assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-  assert_param(IS_FSMC_CLK_DIV(Timing->CLKDivision));
-  assert_param(IS_FSMC_DATA_LATENCY(Timing->DataLatency));
-  assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
-  
-  /* Set FSMC_NORSRAM device timing parameters */  
-  tmpr = (uint32_t)(Timing->AddressSetupTime                                                    |\
-                   ((Timing->AddressHoldTime)           << POSITION_VAL(FSMC_BTRx_ADDHLD))      |\
-                   ((Timing->DataSetupTime)             << POSITION_VAL(FSMC_BTRx_DATAST))      |\
-                   ((Timing->BusTurnAroundDuration)     << POSITION_VAL(FSMC_BTRx_BUSTURN))     |\
-                   (((Timing->CLKDivision)-1)           << POSITION_VAL(FSMC_BTRx_CLKDIV))      |\
-                   (((Timing->DataLatency)-2)           << POSITION_VAL(FSMC_BTRx_DATLAT))      |\
-                    (Timing->AccessMode)
-                    );
-  
-  Device->BTCR[Bank + 1] = tmpr; 
-  
-  return HAL_OK;   
-}
-
-/**
-  * @brief  Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
-  *         parameters in the FSMC_NORSRAM_TimingTypeDef
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Timing: Pointer to NORSRAM Timing structure
-  * @param  Bank: NORSRAM bank number  
-  * @param  ExtendedMode: FSMC Extended Mode
-  *          This parameter can be one of the following values:
-  *            @arg FSMC_EXTENDED_MODE_DISABLE
-  *            @arg FSMC_EXTENDED_MODE_ENABLE
-  * @retval HAL status
-  */
-HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
-{
-  /* Set NORSRAM device timing register for write configuration, if extended mode is used */
-  if(ExtendedMode == FSMC_EXTENDED_MODE_ENABLE)
-  {
-    /* Check the parameters */  
-    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(Timing->AddressSetupTime));
-    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(Timing->AddressHoldTime));
-    assert_param(IS_FSMC_DATASETUP_TIME(Timing->DataSetupTime));
-    assert_param(IS_FSMC_TURNAROUND_TIME(Timing->BusTurnAroundDuration));
-    assert_param(IS_FSMC_ACCESS_MODE(Timing->AccessMode));
-  
-    Device->BWTR[Bank] = (uint32_t)(Timing->AddressSetupTime                 |\
-                                   ((Timing->AddressHoldTime) << POSITION_VAL(FSMC_BWTRx_ADDHLD))          |\
-                                   ((Timing->DataSetupTime) << POSITION_VAL(FSMC_BWTRx_DATAST))            |\
-                                   ((Timing->BusTurnAroundDuration) << POSITION_VAL(FSMC_BWTRx_BUSTURN))   |\
-                                   (Timing->AccessMode));
-  }
-  else                                        
-  {
-    Device->BWTR[Bank] = 0x0FFFFFFF;
-  }   
-  
-  return HAL_OK;  
-}
-
-
-/**
-  * @}
-  */
-  
-  
-/** @defgroup HAL_FSMC_NORSRAM_Group2 Control functions 
- *  @brief   management functions 
- *
-@verbatim   
-  ==============================================================================
-                      ##### FSMC_NORSRAM Control functions #####
-  ==============================================================================
-  [..]
-    This subsection provides a set of functions allowing to control dynamically
-    the FSMC NORSRAM interface.
-
-@endverbatim
-  * @{
-  */
-    
-/**
-  * @brief  Enables dynamically FSMC_NORSRAM write operation.
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Bank: NORSRAM bank number   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank)
-{
-  /* Enable write operation */
-  Device->BTCR[Bank] |= FSMC_WRITE_OPERATION_ENABLE; 
-
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Disables dynamically FSMC_NORSRAM write operation.
-  * @param  Device: Pointer to NORSRAM device instance
-  * @param  Bank: NORSRAM bank number   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank)
-{ 
-  /* Disable write operation */
-  Device->BTCR[Bank] &= ~FSMC_WRITE_OPERATION_ENABLE; 
-
-  return HAL_OK;  
-}
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-  
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#endif /* HAL_FSMC_MODULE_ENABLED */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_fsmc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,567 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_fsmc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of FSMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_FSMC_H
-#define __STM32L1xx_LL_FSMC_H
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-#if defined (STM32L151xD) || defined (STM32L152xD) || defined (STM32L162xD)
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup FSMC_LL
-  * @{
-  */ 
-
-/* Exported typedef ----------------------------------------------------------*/ 
-
-/** @defgroup FSMC_NORSRAM_Exported_typedef FSMC NOR/SRAM Exported typedef
-  * @{
-  */ 
-  
-#define FSMC_NORSRAM_TYPEDEF            FSMC_Bank1_TypeDef
-#define FSMC_NORSRAM_EXTENDED_TYPEDEF   FSMC_Bank1E_TypeDef
-
-#define FSMC_NORSRAM_DEVICE             FSMC_Bank1
-#define FSMC_NORSRAM_EXTENDED_DEVICE    FSMC_Bank1E
-
-/** 
-  * @brief  FSMC_NORSRAM Configuration Structure definition  
-  */ 
-typedef struct
-{
-  uint32_t NSBank;                       /*!< Specifies the NORSRAM memory device that will be used.
-                                              This parameter can be a value of @ref FSMC_NORSRAM_Bank                     */  
-                                                    
-  uint32_t DataAddressMux;               /*!< Specifies whether the address and data values are
-                                              multiplexed on the data bus or not. 
-                                              This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing    */
-  
-  uint32_t MemoryType;                   /*!< Specifies the type of external memory attached to
-                                              the corresponding memory device.
-                                              This parameter can be a value of @ref FSMC_Memory_Type                      */
-                                              
-  uint32_t MemoryDataWidth;              /*!< Specifies the external memory device width.
-                                              This parameter can be a value of @ref FSMC_NORSRAM_Data_Width               */
-  
-  uint32_t BurstAccessMode;              /*!< Enables or disables the burst access mode for Flash memory,
-                                              valid only with synchronous burst Flash memories.
-                                              This parameter can be a value of @ref FSMC_Burst_Access_Mode                */
-                                               
-  uint32_t WaitSignalPolarity;           /*!< Specifies the wait signal polarity, valid only when accessing
-                                              the Flash memory in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wait_Signal_Polarity             */
-  
-  uint32_t WrapMode;                     /*!< Enables or disables the Wrapped burst access mode for Flash
-                                              memory, valid only when accessing Flash memories in burst mode.
-                                              This parameter can be a value of @ref FSMC_Wrap_Mode                        */
-  
-  uint32_t WaitSignalActive;             /*!< Specifies if the wait signal is asserted by the memory one
-                                              clock cycle before the wait state or during the wait state,
-                                              valid only when accessing memories in burst mode. 
-                                              This parameter can be a value of @ref FSMC_Wait_Timing                      */
-  
-  uint32_t WriteOperation;               /*!< Enables or disables the write operation in the selected device by the FSMC. 
-                                              This parameter can be a value of @ref FSMC_Write_Operation                  */
-  
-  uint32_t WaitSignal;                   /*!< Enables or disables the wait state insertion via wait
-                                              signal, valid for Flash memory access in burst mode. 
-                                              This parameter can be a value of @ref FSMC_Wait_Signal                      */
-  
-  uint32_t ExtendedMode;                 /*!< Enables or disables the extended mode.
-                                              This parameter can be a value of @ref FSMC_Extended_Mode                    */
-  
-  uint32_t AsynchronousWait;             /*!< Enables or disables wait signal during asynchronous transfers,
-                                              valid only with asynchronous Flash memories.
-                                              This parameter can be a value of @ref FSMC_AsynchronousWait                 */
-  
-  uint32_t WriteBurst;                   /*!< Enables or disables the write burst operation.
-                                              This parameter can be a value of @ref FSMC_Write_Burst                      */                                     
-
-}FSMC_NORSRAM_InitTypeDef;
-
-
-/** 
-  * @brief  FSMC_NORSRAM Timing parameters structure definition  
-  */
-typedef struct
-{
-  uint32_t AddressSetupTime;             /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address setup time. 
-                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
-                                              @note This parameter is not used with synchronous NOR Flash memories.      */
-  
-  uint32_t AddressHoldTime;              /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the address hold time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 15. 
-                                              @note This parameter is not used with synchronous NOR Flash memories.      */
-  
-  uint32_t DataSetupTime;                /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the data setup time.
-                                              This parameter can be a value between Min_Data = 1 and Max_Data = 255.
-                                              @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed 
-                                              NOR Flash memories.                                                        */
-  
-  uint32_t BusTurnAroundDuration;        /*!< Defines the number of HCLK cycles to configure
-                                              the duration of the bus turnaround.
-                                              This parameter can be a value between Min_Data = 0 and Max_Data = 15.
-                                              @note This parameter is only used for multiplexed NOR Flash memories.      */
-  
-  uint32_t CLKDivision;                  /*!< Defines the period of CLK clock output signal, expressed in number of 
-                                              HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
-                                              @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM 
-                                              accesses.                                                                  */
-  
-  uint32_t DataLatency;                  /*!< Defines the number of memory clock cycles to issue
-                                              to the memory before getting the first data.
-                                              The parameter value depends on the memory type as shown below:
-                                              - It must be set to 0 in case of a CRAM
-                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
-                                              - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
-                                                with synchronous burst mode enable                                       */
-  
-  uint32_t AccessMode;                   /*!< Specifies the asynchronous access mode. 
-                                              This parameter can be a value of @ref FSMC_Access_Mode                      */
-  
-}FSMC_NORSRAM_TimingTypeDef;
-
-/**
-  * @}
-  */
-
-/* Exported constants --------------------------------------------------------*/
-
-/** @defgroup FSMC_NORSRAM_Exported_constants FSMC NOR/SRAM Exported constants
-  * @{
-  */ 
-  
-/** @defgroup FSMC_NORSRAM_Bank FSMC NOR/SRAM Bank
-  * @{
-  */
-#define FSMC_BANK1_NORSRAM1                       ((uint32_t)0x00000000)
-#define FSMC_BANK1_NORSRAM2                       ((uint32_t)0x00000002)
-#define FSMC_BANK1_NORSRAM3                       ((uint32_t)0x00000004)
-#define FSMC_BANK1_NORSRAM4                       ((uint32_t)0x00000006)
-
-/* To keep compatibility with previous families */
-#define FSMC_NORSRAM_BANK1                        FSMC_BANK1_NORSRAM1
-#define FSMC_NORSRAM_BANK2                        FSMC_BANK1_NORSRAM2
-#define FSMC_NORSRAM_BANK3                        FSMC_BANK1_NORSRAM3
-#define FSMC_NORSRAM_BANK4                        FSMC_BANK1_NORSRAM4
-
-#define IS_FSMC_NORSRAM_BANK(__BANK__) (((__BANK__) == FSMC_BANK1_NORSRAM1) || \
-                                        ((__BANK__) == FSMC_BANK1_NORSRAM2) || \
-                                        ((__BANK__) == FSMC_BANK1_NORSRAM3) || \
-                                        ((__BANK__) == FSMC_BANK1_NORSRAM4))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Address_Bus_Multiplexing FSMC Data Address Bus Multiplexing
-  * @{
-  */
-
-#define FSMC_DATA_ADDRESS_MUX_DISABLE            ((uint32_t)0x00000000)
-#define FSMC_DATA_ADDRESS_MUX_ENABLE             ((uint32_t)FSMC_BCRx_MUXEN)
-
-#define IS_FSMC_MUX(__MUX__) (((__MUX__) == FSMC_DATA_ADDRESS_MUX_DISABLE) || \
-                              ((__MUX__) == FSMC_DATA_ADDRESS_MUX_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Memory_Type FSMC Memory Type
-  * @{
-  */
-
-#define FSMC_MEMORY_TYPE_SRAM                    ((uint32_t)0x00000000)
-#define FSMC_MEMORY_TYPE_PSRAM                   ((uint32_t)FSMC_BCRx_MTYP_0)
-#define FSMC_MEMORY_TYPE_NOR                     ((uint32_t)FSMC_BCRx_MTYP_1)
-
-
-#define IS_FSMC_MEMORY(__MEMORY__) (((__MEMORY__) == FSMC_MEMORY_TYPE_SRAM) || \
-                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_PSRAM)|| \
-                                    ((__MEMORY__) == FSMC_MEMORY_TYPE_NOR))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_Data_Width FSMC NOR/SRAM Data Width
-  * @{
-  */
-
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_8             ((uint32_t)0x00000000)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_16            ((uint32_t)FSMC_BCRx_MWID_0)
-#define FSMC_NORSRAM_MEM_BUS_WIDTH_32            ((uint32_t)FSMC_BCRx_MWID_1)
-
-#define IS_FSMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_8)  || \
-                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_16) || \
-                                                 ((__WIDTH__) == FSMC_NORSRAM_MEM_BUS_WIDTH_32))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_Flash_Access FSMC NOR/SRAM Flash Access
-  * @{
-  */
-  
-#define FSMC_NORSRAM_FLASH_ACCESS_ENABLE         ((uint32_t)FSMC_BCRx_FACCEN)
-#define FSMC_NORSRAM_FLASH_ACCESS_DISABLE        ((uint32_t)0x00000000)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Burst_Access_Mode FSMC Burst Access Mode
-  * @{
-  */
-
-#define FSMC_BURST_ACCESS_MODE_DISABLE           ((uint32_t)0x00000000) 
-#define FSMC_BURST_ACCESS_MODE_ENABLE            ((uint32_t)FSMC_BCRx_BURSTEN)
-
-#define IS_FSMC_BURSTMODE(__STATE__) (((__STATE__) == FSMC_BURST_ACCESS_MODE_DISABLE) || \
-                                      ((__STATE__) == FSMC_BURST_ACCESS_MODE_ENABLE))
-/**
-  * @}
-  */
-    
-
-/** @defgroup FSMC_Wait_Signal_Polarity FSMC Wait Signal Polarity
-  * @{
-  */
-  
-#define FSMC_WAIT_SIGNAL_POLARITY_LOW            ((uint32_t)0x00000000)
-#define FSMC_WAIT_SIGNAL_POLARITY_HIGH           ((uint32_t)FSMC_BCRx_WAITPOL)
-
-#define IS_FSMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_LOW) || \
-                                             ((__POLARITY__) == FSMC_WAIT_SIGNAL_POLARITY_HIGH))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wrap_Mode FSMC Wrap Mode
-  * @{
-  */
-  
-#define FSMC_WRAP_MODE_DISABLE                   ((uint32_t)0x00000000)
-#define FSMC_WRAP_MODE_ENABLE                    ((uint32_t)FSMC_BCRx_WRAPMOD)
-
-#define IS_FSMC_WRAP_MODE(__MODE__) (((__MODE__) == FSMC_WRAP_MODE_DISABLE) || \
-                                     ((__MODE__) == FSMC_WRAP_MODE_ENABLE)) 
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Timing FSMC Wait Timing
-  * @{
-  */
-  
-#define FSMC_WAIT_TIMING_BEFORE_WS               ((uint32_t)0x00000000)
-#define FSMC_WAIT_TIMING_DURING_WS               ((uint32_t)FSMC_BCRx_WAITCFG)
-
-#define IS_FSMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FSMC_WAIT_TIMING_BEFORE_WS) || \
-                                                ((__ACTIVE__) == FSMC_WAIT_TIMING_DURING_WS)) 
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Write_Operation FSMC Write Operation
-  * @{
-  */
-  
-#define FSMC_WRITE_OPERATION_DISABLE             ((uint32_t)0x00000000)
-#define FSMC_WRITE_OPERATION_ENABLE              ((uint32_t)FSMC_BCRx_WREN)
-
-#define IS_FSMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FSMC_WRITE_OPERATION_DISABLE) || \
-                                                ((__OPERATION__) == FSMC_WRITE_OPERATION_ENABLE))                        
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Wait_Signal FSMC Wait Signal
-  * @{
-  */
-  
-#define FSMC_WAIT_SIGNAL_DISABLE                 ((uint32_t)0x00000000)
-#define FSMC_WAIT_SIGNAL_ENABLE                  ((uint32_t)FSMC_BCRx_WAITEN)
-
-#define IS_FSMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FSMC_WAIT_SIGNAL_DISABLE) || \
-                                          ((__SIGNAL__) == FSMC_WAIT_SIGNAL_ENABLE)) 
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Extended_Mode FSMC Extended Mode
-  * @{
-  */
-  
-#define FSMC_EXTENDED_MODE_DISABLE               ((uint32_t)0x00000000)
-#define FSMC_EXTENDED_MODE_ENABLE                ((uint32_t)FSMC_BCRx_EXTMOD)
-
-#define IS_FSMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FSMC_EXTENDED_MODE_DISABLE) || \
-                                         ((__MODE__) == FSMC_EXTENDED_MODE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_AsynchronousWait FSMC Asynchronous Wait
-  * @{
-  */
-  
-#define FSMC_ASYNCHRONOUS_WAIT_DISABLE           ((uint32_t)0x00000000)
-#define FSMC_ASYNCHRONOUS_WAIT_ENABLE            ((uint32_t)FSMC_BCRx_ASYNCWAIT)
-
-#define IS_FSMC_ASYNWAIT(__STATE__) (((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_DISABLE) || \
-                                     ((__STATE__) == FSMC_ASYNCHRONOUS_WAIT_ENABLE))
-
-/**
-  * @}
-  */  
-
-/** @defgroup FSMC_Write_Burst FSMC Write Burst
-  * @{
-  */
-
-#define FSMC_WRITE_BURST_DISABLE                 ((uint32_t)0x00000000)
-#define FSMC_WRITE_BURST_ENABLE                  ((uint32_t)FSMC_BCRx_CBURSTRW)
-
-#define IS_FSMC_WRITE_BURST(__BURST__) (((__BURST__) == FSMC_WRITE_BURST_DISABLE) || \
-                                        ((__BURST__) == FSMC_WRITE_BURST_ENABLE)) 
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Setup_Time FSMC Address Setup Time
-  * @{
-  */
-  
-#define IS_FSMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Address_Hold_Time FSMC Address Hold Time
-  * @{
-  */
-  
-#define IS_FSMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Setup_Time FSMC Data Setup Time
-  * @{
-  */
-  
-#define IS_FSMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Bus_Turn_around_Duration FSMC Bus Turn around Duration
-  * @{
-  */
-  
-#define IS_FSMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_CLK_Division FSMC CLK Division
-  * @{
-  */
-  
-#define FSMC_CLK_DIV2                        ((uint32_t)0x00000002)
-#define FSMC_CLK_DIV3                        ((uint32_t)0x00000003)
-#define FSMC_CLK_DIV4                        ((uint32_t)0x00000004)
-#define FSMC_CLK_DIV5                        ((uint32_t)0x00000005)
-#define FSMC_CLK_DIV6                        ((uint32_t)0x00000006)
-#define FSMC_CLK_DIV7                        ((uint32_t)0x00000007)
-#define FSMC_CLK_DIV8                        ((uint32_t)0x00000008)
-#define FSMC_CLK_DIV9                        ((uint32_t)0x00000009)
-#define FSMC_CLK_DIV10                       ((uint32_t)0x0000000A)
-#define FSMC_CLK_DIV11                       ((uint32_t)0x0000000B)
-#define FSMC_CLK_DIV12                       ((uint32_t)0x0000000C)
-#define FSMC_CLK_DIV13                       ((uint32_t)0x0000000D)
-#define FSMC_CLK_DIV14                       ((uint32_t)0x0000000E)
-#define FSMC_CLK_DIV15                       ((uint32_t)0x0000000F)
-#define FSMC_CLK_DIV16                       ((uint32_t)0x00000010)
-#define IS_FSMC_CLK_DIV(__DIV__) (((__DIV__) > 1) && ((__DIV__) <= 16))
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_Data_Latency FSMC Data Latency
-  * @{
-  */
-  
-#define IS_FSMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
-/**
-  * @}
-  */  
-
-/** @defgroup FSMC_Access_Mode FSMC Access Mode
-  * @{
-  */
-  
-#define FSMC_ACCESS_MODE_A                        ((uint32_t)0x00000000)
-#define FSMC_ACCESS_MODE_B                        ((uint32_t)FSMC_BTRx_ACCMOD_0) 
-#define FSMC_ACCESS_MODE_C                        ((uint32_t)FSMC_BTRx_ACCMOD_1)
-#define FSMC_ACCESS_MODE_D                        ((uint32_t)(FSMC_BTRx_ACCMOD_0 | FSMC_BTRx_ACCMOD_1))
-
-#define IS_FSMC_ACCESS_MODE(__MODE__) (((__MODE__) == FSMC_ACCESS_MODE_A) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_B) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_C) || \
-                                       ((__MODE__) == FSMC_ACCESS_MODE_D))
-/**
-  * @}
-  */
-    
-/** @defgroup FSMC_NORSRAM_Device_Instance FSMC NOR/SRAM Device Instance
-  * @{
-  */
-  
-#define IS_FSMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_DEVICE)
-
-/**
-  * @}
-  */
-
-/** @defgroup FSMC_NORSRAM_EXTENDED_Device_Instance FSMC NOR/SRAM EXTENDED Device Instance
-  * @{
-  */
-  
-#define IS_FSMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FSMC_NORSRAM_EXTENDED_DEVICE)
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/* Exported macro ------------------------------------------------------------*/
-
-/** @defgroup FSMC_NOR_Macros FSMC NOR/SRAM Exported Macros
- *  @brief macros to handle NOR device enable/disable and read/write operations
- *  @{
- */
- 
-/**
-  * @brief  Enable the NORSRAM device access.
-  * @param  __INSTANCE__: FSMC_NORSRAM Instance
-  * @param  __BANK__: FSMC_NORSRAM Bank    
-  * @retval none
-  */ 
-#define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__)  ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCRx_MBKEN)
-
-/**
-  * @brief  Disable the NORSRAM device access.
-  * @param  __INSTANCE__: FSMC_NORSRAM Instance
-  * @param  __BANK__: FSMC_NORSRAM Bank   
-  * @retval none
-  */ 
-#define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCRx_MBKEN)  
-
-/**
-  * @}
-  */ 
-
-/* Exported functions --------------------------------------------------------*/
-
-/** @addtogroup FSMC_Exported_Functions
- *  @{
- */
-
-/** @addtogroup HAL_FSMC_NORSRAM_Group1
- *  @{
- */
-
-/* FSMC_NORSRAM Controller functions ******************************************/
-/* Initialization/de-initialization functions */
-HAL_StatusTypeDef  FSMC_NORSRAM_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_InitTypeDef *Init);
-HAL_StatusTypeDef  FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TYPEDEF *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
-HAL_StatusTypeDef  FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TYPEDEF *Device, FSMC_NORSRAM_EXTENDED_TYPEDEF *ExDevice, uint32_t Bank);
-
-/**
-  * @}
-  */ 
-
-/** @addtogroup HAL_FSMC_NORSRAM_Group2
- *  @{
- */
-
-/* FSMC_NORSRAM Control functions */
-HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank);
-HAL_StatusTypeDef  FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TYPEDEF *Device, uint32_t Bank);
-
-/**
-  * @}
-  */ 
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* __STM32L1xx_LL_FSMC_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,519 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_sdmmc.c
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   SDMMC Low Layer HAL module driver.
-  *    
-  *          This file provides firmware functions to manage the following 
-  *          functionalities of the SDMMC peripheral:
-  *           + Initialization/de-initialization functions
-  *           + I/O operation functions
-  *           + Peripheral Control functions 
-  *           + Peripheral State functions
-  *         
-  @verbatim
-  ==============================================================================
-                       ##### SDMMC peripheral features #####
-  ==============================================================================        
-    [..] The SD/SDIO MMC card host interface (SDIO) provides an interface between the APB2
-         peripheral bus and MultiMedia cards (MMCs), SD memory cards, SDIO cards and CE-ATA
-         devices.
-
-    [..] The MultiMedia Card system specifications are available through the MultiMedia Card
-         Association website at www.mmca.org, published by the MMCA technical committee.
-         SD memory card and SD I/O card system specifications are available through the SD card
-         Association website at www.sdcard.org.
-         CE-ATA system specifications are available through the CE-ATA work group web site at
-         www.ce-ata.org.
-    
-    [..] The SDIO features include the following:
-         (+) Full compliance with MultiMedia Card System Specification Version 4.2. Card support
-             for three different databus modes: 1-bit (default), 4-bit and 8-bit
-         (+) Full compatibility with previous versions of MultiMedia Cards (forward compatibility)
-         (+) Full compliance with SD Memory Card Specifications Version 2.0
-         (+) Full compliance with SD I/O Card Specification Version 2.0: card support for two
-             different data bus modes: 1-bit (default) and 4-bit
-         (+) Full support of the CE-ATA features (full compliance with CE-ATA digital protocol
-             Rev1.1)
-         (+) Data transfer up to 48 MHz for the 8 bit mode
-         (+) Data and command output enable signals to control external bidirectional drivers.
-                 
-   
-                           ##### How to use this driver #####
-  ==============================================================================
-    [..]
-      This driver is a considered as a driver of service for external devices drivers 
-      that interfaces with the SDIO peripheral.
-      According to the device used (SD card/ MMC card / SDIO card ...), a set of APIs 
-      is used in the device's driver to perform SDIO operations and functionalities.
-   
-      This driver is almost transparent for the final user, it is only used to implement other
-      functionalities of the external device.
-   
-    [..]
-      (+) The SDIO clock (SDIOCLK = 48 MHz) is coming from the PLL. Before start working with SDIO peripheral make sure that the
-          PLL is well configured.
-          The SDIO peripheral uses two clock signals:
-          (++) SDIO adapter clock (SDIOCLK = 48 MHz)
-          (++) APB2 bus clock (PCLK2)
-       
-          -@@- PCLK2 and SDIO_CK clock frequencies must respect the following condition:
-               Frequency(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
-  
-      (+) Enable/Disable peripheral clock using RCC peripheral macros related to SDIO
-          peripheral.
-
-      (+) Enable the Power ON State using the SDIO_PowerState_ON(hsdio) 
-          function and disable it using the function SDIO_PowerState_OFF(hsdio).
-                
-      (+) Enable/Disable the clock using the __SDIO_ENABLE()/__SDIO_DISABLE() macros.
-  
-      (+) Enable/Disable the peripheral interrupts using the macros __SDIO_ENABLE_IT(hsdio, IT) 
-          and __SDIO_DISABLE_IT(hsdio, IT) if you need to use interrupt mode. 
-  
-      (+) When using the DMA mode 
-          (++) Configure the DMA in the MSP layer of the external device
-          (++) Active the needed channel Request 
-          (++) Enable the DMA using __SDIO_DMA_ENABLE() macro or Disable it using the macro
-               __SDIO_DMA_DISABLE().
-  
-      (+) To control the CPSM (Command Path State Machine) and send 
-          commands to the card use the SDIO_SendCommand(), 
-          SDIO_GetCommandResponse() and SDIO_GetResponse() functions. First, user has
-          to fill the command structure (pointer to SDIO_CmdInitTypeDef) according 
-          to the selected command to be sent.
-          The parameters that should be filled are:
-           (++) Command Argument
-           (++) Command Index
-           (++) Command Response type
-           (++) Command Wait
-           (++) CPSM Status (Enable or Disable).
-  
-          -@@- To check if the command is well received, read the SDIO_CMDRESP
-              register using the SDIO_GetCommandResponse().
-              The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
-              SDIO_GetResponse() function.
-  
-      (+) To control the DPSM (Data Path State Machine) and send/receive 
-           data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), 
-          SDIO_ReadFIFO(), SDIO_WriteFIFO() and SDIO_GetFIFOCount() functions.
-  
-    *** Read Operations ***
-    =======================
-    [..]
-      (#) First, user has to fill the data structure (pointer to
-          SDIO_DataInitTypeDef) according to the selected data type to be received.
-          The parameters that should be filled are:
-           (++) Data TimeOut
-           (++) Data Length
-           (++) Data Block size
-           (++) Data Transfer direction: should be from card (To SDIO)
-           (++) Data Transfer mode
-           (++) DPSM Status (Enable or Disable)
-                                     
-      (#) Configure the SDIO resources to receive the data from the card
-          according to selected transfer mode.
-  
-      (#) Send the selected Read command.
-                    
-      (#) Use the SDIO flags/interrupts to check the transfer status.
-  
-    *** Write Operations ***
-    ========================
-    [..]
-     (#) First, user has to fill the data structure (pointer to
-         SDIO_DataInitTypeDef) according to the selected data type to be received.
-         The parameters that should be filled are:
-          (++) Data TimeOut
-          (++) Data Length
-          (++) Data Block size
-          (++) Data Transfer direction:  should be to card (To CARD)
-          (++) Data Transfer mode
-          (++) DPSM Status (Enable or Disable)
-  
-     (#) Configure the SDIO resources to send the data to the card according to 
-         selected transfer mode.
-                     
-     (#) Send the selected Write command.
-                    
-     (#) Use the SDIO flags/interrupts to check the transfer status.
-  
-  @endverbatim
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @defgroup SDMMC_LL SDMMC_LL
-  * @brief Low layer module for SD and MMC driver
-  * @{
-  */
-
-#if defined (HAL_SD_MODULE_ENABLED) || defined(HAL_MMC_MODULE_ENABLED)
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-/* Private typedef -----------------------------------------------------------*/
-/* Private define ------------------------------------------------------------*/
-/* Private macro -------------------------------------------------------------*/
-/* Private variables ---------------------------------------------------------*/
-/* Private function prototypes -----------------------------------------------*/
-/* Private functions ---------------------------------------------------------*/
-
-/** @defgroup SDMMC_LL_Exported_Functions SDMMC_LL Exported Functions
-  * @{
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group1 Initialization/de-initialization functions 
- *  @brief    Initialization and Configuration functions 
- *
-@verbatim    
- ===============================================================================
-              ##### Initialization/de-initialization functions #####
- ===============================================================================
-    [..]  This section provides functions allowing to:
- 
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Initializes the SDIO according to the specified
-  *         parameters in the SDIO_InitTypeDef and create the associated handle.
-  * @param  SDIOx: Pointer to SDIO register base
-  * @param  Init: SDIO initialization structure   
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
-{
-  uint32_t tmpreg = 0; 
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_ALL_INSTANCE(SDIOx));
-  assert_param(IS_SDIO_CLOCK_EDGE(Init.ClockEdge)); 
-  assert_param(IS_SDIO_CLOCK_BYPASS(Init.ClockBypass));
-  assert_param(IS_SDIO_CLOCK_POWER_SAVE(Init.ClockPowerSave));
-  assert_param(IS_SDIO_BUS_WIDE(Init.BusWide));
-  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(Init.HardwareFlowControl));
-  assert_param(IS_SDIO_CLKDIV(Init.ClockDiv));
-  
-  /* Set SDIO configuration parameters */
-  tmpreg |= (Init.ClockEdge           |\
-             Init.ClockBypass         |\
-             Init.ClockPowerSave      |\
-             Init.BusWide             |\
-             Init.HardwareFlowControl |\
-             Init.ClockDiv
-             ); 
-  
-  /* Write to SDIO CLKCR */
-  MODIFY_REG(SDIOx->CLKCR, CLKCR_CLEAR_MASK, tmpreg);  
-
-  return HAL_OK;
-}
-
-
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group2 I/O operation functions 
- *  @brief   Data transfers functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### I/O operation functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to manage the SDIO data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Read data (word) from Rx FIFO in blocking mode (polling) 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval HAL status
-  */
-uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
-{
-  /* Read data from Rx FIFO */ 
-  return (SDIOx->FIFO);
-}
-
-/**
-  * @brief  Write data (word) to Tx FIFO in blocking mode (polling) 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @param  pWriteData: pointer to data to write
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
-{ 
-  /* Write data to FIFO */ 
-  SDIOx->FIFO = *pWriteData;
-
-  return HAL_OK;
-}
-
-/**
-  * @}
-  */
-
-/** @defgroup HAL_SDMMC_LL_Group3 Peripheral Control functions 
- *  @brief   management functions 
- *
-@verbatim   
- ===============================================================================
-                      ##### Peripheral Control functions #####
- ===============================================================================  
-    [..]
-    This subsection provides a set of functions allowing to control the SDIO data 
-    transfers.
-
-@endverbatim
-  * @{
-  */
-
-/**
-  * @brief  Set SDIO Power state to ON. 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
-{  
-  /* Set power state to ON */ 
-  SDIOx->POWER = SDIO_POWER_PWRCTRL;
-  
-  return HAL_OK; 
-}
-
-/**
-  * @brief  Set SDIO Power state to OFF. 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
-{
-  /* Set power state to OFF */
-  SDIOx->POWER = (uint32_t)0x00000000;
-  
-  return HAL_OK;
-}
-
-/**
-  * @brief  Get SDIO Power state. 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval Power status of the controller. The returned value can be one of the 
-  *         following values:
-  *            - 0x00: Power OFF
-  *            - 0x02: Power UP
-  *            - 0x03: Power ON 
-  */
-uint32_t SDIO_GetPowerState(SDIO_TypeDef *SDIOx)  
-{
-  return (SDIOx->POWER & SDIO_POWER_PWRCTRL);
-}
-
-/**
-  * @brief  Configure the SDIO command path according to the specified parameters in
-  *         SDIO_CmdInitTypeDef structure and send the command 
-  * @param  SDIOx: Pointer to SDIO register base
-  * @param  SDIO_CmdInitStruct: pointer to a SDIO_CmdInitTypeDef structure that contains 
-  *         the configuration information for the SDIO command
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->CmdIndex));
-  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->Response));
-  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->WaitForInterrupt));
-  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->CPSM));
-
-  /* Set the SDIO Argument value */
-  SDIOx->ARG = SDIO_CmdInitStruct->Argument;
-
-  /* Set SDIO command parameters */
-  tmpreg |= (uint32_t)(SDIO_CmdInitStruct->CmdIndex         |\
-                       SDIO_CmdInitStruct->Response         |\
-                       SDIO_CmdInitStruct->WaitForInterrupt |\
-                       SDIO_CmdInitStruct->CPSM);
-  
-  /* Write to SDIO CMD register */
-  MODIFY_REG(SDIOx->CMD, CMD_CLEAR_MASK, tmpreg); 
-  
-  return HAL_OK;  
-}
-
-/**
-  * @brief  Return the command index of last command for which response received
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval Command index of the last command response received
-  */
-uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
-{
-  return (uint8_t)(SDIOx->RESPCMD);
-}
-
-
-/**
-  * @brief  Return the response received from the card for the last command
-  * @param  SDIO_RESP: Specifies the SDIO response register. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_RESP1: Response Register 1
-  *            @arg SDIO_RESP2: Response Register 2
-  *            @arg SDIO_RESP3: Response Register 3
-  *            @arg SDIO_RESP4: Response Register 4  
-  * @retval The Corresponding response register value
-  */
-uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
-{
-  __IO uint32_t tmp = 0;
-
-  /* Check the parameters */
-  assert_param(IS_SDIO_RESP(SDIO_RESP));
-
-  /* Get the response */
-  tmp = SDIO_RESP_ADDR + SDIO_RESP;
-  
-  return (*(__IO uint32_t *) tmp);
-}  
-
-/**
-  * @brief  Configure the SDIO data path according to the specified 
-  *         parameters in the SDIO_DataInitTypeDef.
-  * @param  SDIOx: Pointer to SDIO register base  
-  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure 
-  *         that contains the configuration information for the SDIO command.
-  * @retval HAL status
-  */
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct)
-{
-  uint32_t tmpreg = 0;
-  
-  /* Check the parameters */
-  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->DataLength));
-  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->DataBlockSize));
-  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->TransferDir));
-  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->TransferMode));
-  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->DPSM));
-
-  /* Set the SDIO Data TimeOut value */
-  SDIOx->DTIMER = SDIO_DataInitStruct->DataTimeOut;
-
-  /* Set the SDIO DataLength value */
-  SDIOx->DLEN = SDIO_DataInitStruct->DataLength;
-
-  /* Set the SDIO data configuration parameters */
-  tmpreg |= (uint32_t)(SDIO_DataInitStruct->DataBlockSize |\
-                       SDIO_DataInitStruct->TransferDir   |\
-                       SDIO_DataInitStruct->TransferMode  |\
-                       SDIO_DataInitStruct->DPSM);
-  
-  /* Write to SDIO DCTRL */
-  MODIFY_REG(SDIOx->DCTRL, DCTRL_CLEAR_MASK, tmpreg);
-
-  return HAL_OK;
-
-}
-
-/**
-  * @brief  Returns number of remaining data bytes to be transferred.
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval Number of remaining data bytes to be transferred
-  */
-uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
-{
-  return (SDIOx->DCOUNT);
-}
-
-/**
-  * @brief  Get the FIFO data
-  * @param  SDIOx: Pointer to SDIO register base
-  * @retval Data received
-  */
-uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
-{
-  return (SDIOx->FIFO);
-}
-
-
-/**
-  * @brief  Sets one of the two options of inserting read wait interval.
-  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
-  *          This parameter can be:
-  *            @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDIOCLK
-  *            @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDIO_DATA2
-  * @retval None
-  */
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
-{
-  /* Check the parameters */
-  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
-  
-  *(__IO uint32_t *)DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
-  
-  return HAL_OK;  
-}
-
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#endif /* (HAL_SD_MODULE_ENABLED) || (HAL_MMC_MODULE_ENABLED) */
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TARGET_STM/TARGET_STM32L1/stm32l1xx_ll_sdmmc.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,907 +0,0 @@
-/**
-  ******************************************************************************
-  * @file    stm32l1xx_ll_sdmmc.h
-  * @author  MCD Application Team
-  * @version V1.0.0
-  * @date    5-September-2014
-  * @brief   Header file of low layer SDMMC HAL module.
-  ******************************************************************************
-  * @attention
-  *
-  * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
-  *
-  * Redistribution and use in source and binary forms, with or without modification,
-  * are permitted provided that the following conditions are met:
-  *   1. Redistributions of source code must retain the above copyright notice,
-  *      this list of conditions and the following disclaimer.
-  *   2. Redistributions in binary form must reproduce the above copyright notice,
-  *      this list of conditions and the following disclaimer in the documentation
-  *      and/or other materials provided with the distribution.
-  *   3. Neither the name of STMicroelectronics nor the names of its contributors
-  *      may be used to endorse or promote products derived from this software
-  *      without specific prior written permission.
-  *
-  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-  *
-  ******************************************************************************
-  */ 
-
-/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32L1xx_LL_SD_H
-#define __STM32L1xx_LL_SD_H
-
-#if defined(STM32L151xD) || defined(STM32L152xD) || defined(STM32L162xD)
-
-#ifdef __cplusplus
- extern "C" {
-#endif
-
-/* Includes ------------------------------------------------------------------*/
-#include "stm32l1xx_hal_def.h"
-
-/** @addtogroup STM32L1xx_HAL_Driver
-  * @{
-  */
-
-/** @addtogroup SDMMC_LL
-  * @{
-  */ 
-
-/* Exported types ------------------------------------------------------------*/ 
-/** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
-  * @{
-  */
-  
-/** 
-  * @brief  SDMMC Configuration Structure definition  
-  */
-typedef struct
-{
-  uint32_t ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Edge                 */
-
-  uint32_t ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
-                                      enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Bypass               */
-
-  uint32_t ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
-                                      disabled when the bus is idle.
-                                      This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save           */
-
-  uint32_t BusWide;              /*!< Specifies the SDIO bus width.
-                                      This parameter can be a value of @ref SDMMC_LL_Bus_Wide                   */
-
-  uint32_t HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
-                                      This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control      */
-
-  uint32_t ClockDiv;             /*!< Specifies the clock frequency of the SDIO controller.
-                                      This parameter can be a value between Min_Data = 0 and Max_Data = 255 */  
-  
-}SDIO_InitTypeDef;
-  
-
-/** 
-  * @brief  SDIO Command Control structure 
-  */
-typedef struct                                                                                            
-{
-  uint32_t Argument;            /*!< Specifies the SDIO command argument which is sent
-                                     to a card as part of a command message. If a command
-                                     contains an argument, it must be loaded into this register
-                                     before writing the command to the command register.              */
-
-  uint32_t CmdIndex;            /*!< Specifies the SDIO command index. It must be Min_Data = 0 and 
-                                     Max_Data = 64                                                    */
-
-  uint32_t Response;            /*!< Specifies the SDIO response type.
-                                     This parameter can be a value of @ref SDMMC_LL_Response_Type         */
-
-  uint32_t WaitForInterrupt;    /*!< Specifies whether SDIO wait for interrupt request is 
-                                     enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State  */
-
-  uint32_t CPSM;                /*!< Specifies whether SDIO Command path state machine (CPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_CPSM_State            */
-}SDIO_CmdInitTypeDef;
-
-
-/** 
-  * @brief  SDIO Data Control structure 
-  */
-typedef struct
-{
-  uint32_t DataTimeOut;         /*!< Specifies the data timeout period in card bus clock periods.  */
-
-  uint32_t DataLength;          /*!< Specifies the number of data bytes to be transferred.         */
- 
-  uint32_t DataBlockSize;       /*!< Specifies the data block size for block transfer.
-                                     This parameter can be a value of @ref SDMMC_LL_Data_Block_Size    */
- 
-  uint32_t TransferDir;         /*!< Specifies the data transfer direction, whether the transfer
-                                     is a read or write.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
- 
-  uint32_t TransferMode;        /*!< Specifies whether data transfer is in stream or block mode.
-                                     This parameter can be a value of @ref SDMMC_LL_Transfer_Type      */
- 
-  uint32_t DPSM;                /*!< Specifies whether SDIO Data path state machine (DPSM)
-                                     is enabled or disabled.
-                                     This parameter can be a value of @ref SDMMC_LL_DPSM_State         */
-}SDIO_DataInitTypeDef;
-
-/**
-  * @}
-  */
-  
-/* Exported constants --------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
-  * @{
-  */
-
-/** @defgroup SDMMC_LL_Clock_Edge Clock Edge
-  * @{
-  */
-#define SDIO_CLOCK_EDGE_RISING               ((uint32_t)0x00000000)
-#define SDIO_CLOCK_EDGE_FALLING              SDIO_CLKCR_NEGEDGE
-
-#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_CLOCK_EDGE_RISING) || \
-                                  ((EDGE) == SDIO_CLOCK_EDGE_FALLING))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
-  * @{
-  */
-#define SDIO_CLOCK_BYPASS_DISABLE             ((uint32_t)0x00000000)
-#define SDIO_CLOCK_BYPASS_ENABLE              SDIO_CLKCR_BYPASS   
-
-#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_CLOCK_BYPASS_DISABLE) || \
-                                      ((BYPASS) == SDIO_CLOCK_BYPASS_ENABLE))
-/**
-  * @}
-  */ 
-
-/** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
-  * @{
-  */
-#define SDIO_CLOCK_POWER_SAVE_DISABLE         ((uint32_t)0x00000000)
-#define SDIO_CLOCK_POWER_SAVE_ENABLE          SDIO_CLKCR_PWRSAV
-
-#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_CLOCK_POWER_SAVE_DISABLE) || \
-                                        ((SAVE) == SDIO_CLOCK_POWER_SAVE_ENABLE))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Bus_Wide Bus Width
-  * @{
-  */
-#define SDIO_BUS_WIDE_1B                      ((uint32_t)0x00000000)
-#define SDIO_BUS_WIDE_4B                      SDIO_CLKCR_WIDBUS_0
-#define SDIO_BUS_WIDE_8B                      SDIO_CLKCR_WIDBUS_1
-
-#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BUS_WIDE_1B) || \
-                                ((WIDE) == SDIO_BUS_WIDE_4B) || \
-                                ((WIDE) == SDIO_BUS_WIDE_8B))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
-  * @{
-  */
-#define SDIO_HARDWARE_FLOW_CONTROL_DISABLE    ((uint32_t)0x00000000)
-#define SDIO_HARDWARE_FLOW_CONTROL_ENABLE     SDIO_CLKCR_HWFC_EN
-
-#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_DISABLE) || \
-                                                ((CONTROL) == SDIO_HARDWARE_FLOW_CONTROL_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDMMC_LL_Clock_Division Clock Division
-  * @{
-  */
-#define IS_SDIO_CLKDIV(DIV)   ((DIV) <= 0xFF)
-/**
-  * @}
-  */  
-    
-/** @defgroup SDMMC_LL_Command_Index Command Index
-  * @{
-  */
-#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Response_Type Response Type
-  * @{
-  */
-#define SDIO_RESPONSE_NO                    ((uint32_t)0x00000000)
-#define SDIO_RESPONSE_SHORT                 SDIO_CMD_WAITRESP_0
-#define SDIO_RESPONSE_LONG                  SDIO_CMD_WAITRESP
-
-#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_RESPONSE_NO)    || \
-                                    ((RESPONSE) == SDIO_RESPONSE_SHORT) || \
-                                    ((RESPONSE) == SDIO_RESPONSE_LONG))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
-  * @{
-  */
-#define SDIO_WAIT_NO                        ((uint32_t)0x00000000)
-#define SDIO_WAIT_IT                        SDIO_CMD_WAITINT 
-#define SDIO_WAIT_PEND                      SDIO_CMD_WAITPEND
-
-#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_WAIT_NO) || \
-                            ((WAIT) == SDIO_WAIT_IT) || \
-                            ((WAIT) == SDIO_WAIT_PEND))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_CPSM_State CPSM State
-  * @{
-  */
-#define SDIO_CPSM_DISABLE                   ((uint32_t)0x00000000)
-#define SDIO_CPSM_ENABLE                    SDIO_CMD_CPSMEN
-
-#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_DISABLE) || \
-                            ((CPSM) == SDIO_CPSM_ENABLE))
-/**
-  * @}
-  */  
-
-/** @defgroup SDMMC_LL_Response_Registers Response Register
-  * @{
-  */
-#define SDIO_RESP1                          ((uint32_t)0x00000000)
-#define SDIO_RESP2                          ((uint32_t)0x00000004)
-#define SDIO_RESP3                          ((uint32_t)0x00000008)
-#define SDIO_RESP4                          ((uint32_t)0x0000000C)
-
-#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || \
-                            ((RESP) == SDIO_RESP2) || \
-                            ((RESP) == SDIO_RESP3) || \
-                            ((RESP) == SDIO_RESP4))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Data_Length Data Lenght
-  * @{
-  */
-#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Data_Block_Size  Data Block Size
-  * @{
-  */
-#define SDIO_DATABLOCK_SIZE_1B               ((uint32_t)0x00000000)
-#define SDIO_DATABLOCK_SIZE_2B               SDIO_DCTRL_DBLOCKSIZE_0
-#define SDIO_DATABLOCK_SIZE_4B               SDIO_DCTRL_DBLOCKSIZE_1
-#define SDIO_DATABLOCK_SIZE_8B               ((uint32_t)0x00000030)
-#define SDIO_DATABLOCK_SIZE_16B              SDIO_DCTRL_DBLOCKSIZE_2
-#define SDIO_DATABLOCK_SIZE_32B              ((uint32_t)0x00000050)
-#define SDIO_DATABLOCK_SIZE_64B              ((uint32_t)0x00000060)
-#define SDIO_DATABLOCK_SIZE_128B             ((uint32_t)0x00000070)
-#define SDIO_DATABLOCK_SIZE_256B             SDIO_DCTRL_DBLOCKSIZE_3
-#define SDIO_DATABLOCK_SIZE_512B             ((uint32_t)0x00000090)
-#define SDIO_DATABLOCK_SIZE_1024B            ((uint32_t)0x000000A0)
-#define SDIO_DATABLOCK_SIZE_2048B            ((uint32_t)0x000000B0)
-#define SDIO_DATABLOCK_SIZE_4096B            ((uint32_t)0x000000C0)
-#define SDIO_DATABLOCK_SIZE_8192B            ((uint32_t)0x000000D0)
-#define SDIO_DATABLOCK_SIZE_16384B           ((uint32_t)0x000000E0)
-
-#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DATABLOCK_SIZE_1B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8B)    || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_32B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_64B)   || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_128B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_256B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_512B)  || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_1024B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_2048B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_4096B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_8192B) || \
-                                  ((SIZE) == SDIO_DATABLOCK_SIZE_16384B)) 
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
-  * @{
-  */
-#define SDIO_TRANSFER_DIR_TO_CARD            ((uint32_t)0x00000000)
-#define SDIO_TRANSFER_DIR_TO_SDIO            SDIO_DCTRL_DTDIR
-
-#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TRANSFER_DIR_TO_CARD) || \
-                                   ((DIR) == SDIO_TRANSFER_DIR_TO_SDIO))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_Transfer_Type Transfer Type
-  * @{
-  */
-#define SDIO_TRANSFER_MODE_BLOCK             ((uint32_t)0x00000000)
-#define SDIO_TRANSFER_MODE_STREAM            SDIO_DCTRL_DTMODE
-
-#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TRANSFER_MODE_BLOCK) || \
-                                     ((MODE) == SDIO_TRANSFER_MODE_STREAM))
-/**
-  * @}
-  */
-
-/** @defgroup SDMMC_LL_DPSM_State DPSM State
-  * @{
-  */
-#define SDIO_DPSM_DISABLE                    ((uint32_t)0x00000000)
-#define SDIO_DPSM_ENABLE                     SDIO_DCTRL_DTEN
-
-#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_DISABLE) ||\
-                            ((DPSM) == SDIO_DPSM_ENABLE))
-/**
-  * @}
-  */
-  
-/** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
-  * @{
-  */
-#define SDIO_READ_WAIT_MODE_CLK               ((uint32_t)0x00000000)
-#define SDIO_READ_WAIT_MODE_DATA2             ((uint32_t)0x00000001)
-
-#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_READ_WAIT_MODE_CLK) || \
-                                     ((MODE) == SDIO_READ_WAIT_MODE_DATA2))
-/**
-  * @}
-  */  
-
-/** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
-  * @{
-  */
-#define SDIO_IT_CCRCFAIL                    SDIO_STA_CCRCFAIL
-#define SDIO_IT_DCRCFAIL                    SDIO_STA_DCRCFAIL
-#define SDIO_IT_CTIMEOUT                    SDIO_STA_CTIMEOUT
-#define SDIO_IT_DTIMEOUT                    SDIO_STA_DTIMEOUT
-#define SDIO_IT_TXUNDERR                    SDIO_STA_TXUNDERR
-#define SDIO_IT_RXOVERR                     SDIO_STA_RXOVERR
-#define SDIO_IT_CMDREND                     SDIO_STA_CMDREND
-#define SDIO_IT_CMDSENT                     SDIO_STA_CMDSENT
-#define SDIO_IT_DATAEND                     SDIO_STA_DATAEND
-#define SDIO_IT_STBITERR                    SDIO_STA_STBITERR
-#define SDIO_IT_DBCKEND                     SDIO_STA_DBCKEND
-#define SDIO_IT_CMDACT                      SDIO_STA_CMDACT
-#define SDIO_IT_TXACT                       SDIO_STA_TXACT
-#define SDIO_IT_RXACT                       SDIO_STA_RXACT
-#define SDIO_IT_TXFIFOHE                    SDIO_STA_TXFIFOHE
-#define SDIO_IT_RXFIFOHF                    SDIO_STA_RXFIFOHF
-#define SDIO_IT_TXFIFOF                     SDIO_STA_TXFIFOF
-#define SDIO_IT_RXFIFOF                     SDIO_STA_RXFIFOF
-#define SDIO_IT_TXFIFOE                     SDIO_STA_TXFIFOE
-#define SDIO_IT_RXFIFOE                     SDIO_STA_RXFIFOE
-#define SDIO_IT_TXDAVL                      SDIO_STA_TXDAVL
-#define SDIO_IT_RXDAVL                      SDIO_STA_RXDAVL
-#define SDIO_IT_SDIOIT                      SDIO_STA_SDIOIT
-#define SDIO_IT_CEATAEND                    SDIO_STA_CEATAEND
-
-/**
-  * @}
-  */ 
-
-/** @defgroup SDMMC_LL_Flags Flags
-  * @{
-  */
-#define SDIO_FLAG_CCRCFAIL                  SDIO_STA_CCRCFAIL
-#define SDIO_FLAG_DCRCFAIL                  SDIO_STA_DCRCFAIL
-#define SDIO_FLAG_CTIMEOUT                  SDIO_STA_CTIMEOUT
-#define SDIO_FLAG_DTIMEOUT                  SDIO_STA_DTIMEOUT
-#define SDIO_FLAG_TXUNDERR                  SDIO_STA_TXUNDERR
-#define SDIO_FLAG_RXOVERR                   SDIO_STA_RXOVERR
-#define SDIO_FLAG_CMDREND                   SDIO_STA_CMDREND
-#define SDIO_FLAG_CMDSENT                   SDIO_STA_CMDSENT
-#define SDIO_FLAG_DATAEND                   SDIO_STA_DATAEND
-#define SDIO_FLAG_STBITERR                  SDIO_STA_STBITERR
-#define SDIO_FLAG_DBCKEND                   SDIO_STA_DBCKEND
-#define SDIO_FLAG_CMDACT                    SDIO_STA_CMDACT
-#define SDIO_FLAG_TXACT                     SDIO_STA_TXACT
-#define SDIO_FLAG_RXACT                     SDIO_STA_RXACT
-#define SDIO_FLAG_TXFIFOHE                  SDIO_STA_TXFIFOHE
-#define SDIO_FLAG_RXFIFOHF                  SDIO_STA_RXFIFOHF
-#define SDIO_FLAG_TXFIFOF                   SDIO_STA_TXFIFOF
-#define SDIO_FLAG_RXFIFOF                   SDIO_STA_RXFIFOF
-#define SDIO_FLAG_TXFIFOE                   SDIO_STA_TXFIFOE
-#define SDIO_FLAG_RXFIFOE                   SDIO_STA_RXFIFOE
-#define SDIO_FLAG_TXDAVL                    SDIO_STA_TXDAVL
-#define SDIO_FLAG_RXDAVL                    SDIO_STA_RXDAVL
-#define SDIO_FLAG_SDIOIT                    SDIO_STA_SDIOIT
-#define SDIO_FLAG_CEATAEND                  SDIO_STA_CEATAEND
-
-/**
-  * @}
-  */
-
-/**
-  * @}
-  */ 
-  
-/* Exported macro ------------------------------------------------------------*/
-/** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
-  * @{
-  */
-  
-/** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
-  * @brief SDMMC_LL registers bit address in the alias region
-  * @{
-  */
-  
-/* ------------ SDIO registers bit address in the alias region -------------- */
-#define SDIO_OFFSET               (SDIO_BASE - PERIPH_BASE)
-
-/* --- CLKCR Register ---*/
-/* Alias word address of CLKEN bit */
-#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
-#define CLKEN_BITNUMBER           0x08
-#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BITNUMBER * 4))
-
-/* --- CMD Register ---*/
-/* Alias word address of SDIOSUSPEND bit */
-#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
-#define SDIOSUSPEND_BITNUMBER     0x0B
-#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BITNUMBER * 4))
-
-/* Alias word address of ENCMDCOMPL bit */
-#define ENCMDCOMPL_BITNUMBER      0x0C
-#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BITNUMBER * 4))
-
-/* Alias word address of NIEN bit */
-#define NIEN_BITNUMBER            0x0D
-#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BITNUMBER * 4))
-
-/* Alias word address of ATACMD bit */
-#define ATACMD_BITNUMBER          0x0E
-#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BITNUMBER * 4))
-
-/* --- DCTRL Register ---*/
-/* Alias word address of DMAEN bit */
-#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
-#define DMAEN_BITNUMBER           0x03
-#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BITNUMBER * 4))
-
-/* Alias word address of RWSTART bit */
-#define RWSTART_BITNUMBER         0x08
-#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BITNUMBER * 4))
-
-/* Alias word address of RWSTOP bit */
-#define RWSTOP_BITNUMBER          0x09
-#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BITNUMBER * 4))
-
-/* Alias word address of RWMOD bit */
-#define RWMOD_BITNUMBER           0x0A
-#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BITNUMBER * 4))
-
-/* Alias word address of SDIOEN bit */
-#define SDIOEN_BITNUMBER          0x0B
-#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BITNUMBER * 4))
-
-/* ---------------------- SDIO registers bit mask --------------------------- */
-/* --- CLKCR Register ---*/
-/* CLKCR register clear mask */ 
-#define CLKCR_CLEAR_MASK         ((uint32_t)(SDIO_CLKCR_CLKDIV  | SDIO_CLKCR_PWRSAV |\
-                                             SDIO_CLKCR_BYPASS  | SDIO_CLKCR_WIDBUS |\
-                                             SDIO_CLKCR_NEGEDGE | SDIO_CLKCR_HWFC_EN))
-
-/* --- DCTRL Register ---*/
-/* SDIO DCTRL Clear Mask */
-#define DCTRL_CLEAR_MASK         ((uint32_t)(SDIO_DCTRL_DTEN    | SDIO_DCTRL_DTDIR |\
-                                             SDIO_DCTRL_DTMODE  | SDIO_DCTRL_DBLOCKSIZE))
-
-/* --- CMD Register ---*/
-/* CMD Register clear mask */
-#define CMD_CLEAR_MASK           ((uint32_t)(SDIO_CMD_CMDINDEX | SDIO_CMD_WAITRESP |\
-                                             SDIO_CMD_WAITINT  | SDIO_CMD_WAITPEND |\
-                                             SDIO_CMD_CPSMEN   | SDIO_CMD_SDIOSUSPEND))
-
-/* SDIO RESP Registers Address */
-#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
-
-/* SDIO Intialization Frequency (400KHz max) */
-#define SDIO_INIT_CLK_DIV ((uint8_t)0x76)
-
-/* SDIO Data Transfer Frequency */
-#define SDIO_TRANSFER_CLK_DIV ((uint8_t)0x4)
-
-/**
-  * @}
-  */
-  
-/** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
-  * @brief macros to handle interrupts and specific clock configurations
-  * @{
-  */
- 
-/**
-  * @brief  Enable the SDIO device.
-  * @retval None
-  */ 
-#define __SDIO_ENABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SDIO device.
-  * @retval None
-  */
-#define __SDIO_DISABLE()   (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE)
-
-/**
-  * @brief  Enable the SDIO DMA transfer.
-  * @retval None
-  */ 
-#define __SDIO_DMA_ENABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SDIO DMA transfer.
-  * @retval None
-  */
-#define __SDIO_DMA_DISABLE()   (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE)
- 
-/**
-  * @brief  Enable the SDIO device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled.
-  *         This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __SDIO_ENABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK |= (__INTERRUPT__))
-
-/**
-  * @brief  Disable the SDIO device interrupt.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled.
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt     
-  * @retval None
-  */
-#define __SDIO_DISABLE_IT(__INSTANCE__, __INTERRUPT__)  ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
-
-/**
-  * @brief  Checks whether the specified SDIO flag is set or not. 
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __FLAG__: specifies the flag to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
-  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
-  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
-  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
-  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
-  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
-  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
-  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
-  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
-  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
-  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval The new state of SDIO_FLAG (SET or RESET).
-  */
-#define __SDIO_GET_FLAG(__INSTANCE__, __FLAG__)   (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
-
-
-/**
-  * @brief  Clears the SDIO pending flags.
-  * @param  __INSTANCE__ : Pointer to SDIO register base  
-  * @param  __FLAG__: specifies the flag to clear.  
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
-  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
-  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
-  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
-  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
-  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
-  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
-  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
-  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
-  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
-  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
-  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
-  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __SDIO_CLEAR_FLAG(__INSTANCE__, __FLAG__)   ((__INSTANCE__)->ICR = (__FLAG__))
-
-/**
-  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
-  * @param  __INSTANCE__ : Pointer to SDIO register base   
-  * @param  __INTERRUPT__: specifies the SDIO interrupt source to check. 
-  *          This parameter can be one of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
-  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
-  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
-  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
-  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
-  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
-  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
-  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
-  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
-  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
-  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
-  * @retval The new state of SDIO_IT (SET or RESET).
-  */
-#define __SDIO_GET_IT  (__INSTANCE__, __INTERRUPT__)   (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
-
-/**
-  * @brief  Clears the SDIO's interrupt pending bits.
-  * @param  __INSTANCE__ : Pointer to SDIO register base 
-  * @param  __INTERRUPT__: specifies the interrupt pending bit to clear. 
-  *          This parameter can be one or a combination of the following values:
-  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
-  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
-  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
-  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
-  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
-  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
-  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
-  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
-  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
-  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
-  *                                   bus mode interrupt
-  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
-  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
-  * @retval None
-  */
-#define __SDIO_CLEAR_IT(__INSTANCE__, __INTERRUPT__)   ((__INSTANCE__)->ICR = (__INTERRUPT__))
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @retval None
-  */  
-#define __SDIO_START_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE)
-
-/**
-  * @brief  Disable Start the SD I/O Read Wait operations.
-  * @retval None
-  */  
-#define __SDIO_START_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE)
-
-/**
-  * @brief  Enable Start the SD I/O Read Wait operation.
-  * @retval None
-  */  
-#define __SDIO_STOP_READWAIT_ENABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE)
-
-/**
-  * @brief  Disable Stop the SD I/O Read Wait operations.
-  * @retval None
-  */  
-#define __SDIO_STOP_READWAIT_DISABLE()   (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE)
-
-/**
-  * @brief  Enable the SD I/O Mode Operation.
-  * @retval None
-  */  
-#define __SDIO_OPERATION_ENABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE)
-
-/**
-  * @brief  Disable the SD I/O Mode Operation.
-  * @retval None
-  */  
-#define __SDIO_OPERATION_DISABLE()   (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE)
-
-/**
-  * @brief  Enable the SD I/O Suspend command sending.
-  * @retval None
-  */  
-#define __SDIO_SUSPEND_CMD_ENABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE)
-
-/**
-  * @brief  Disable the SD I/O Suspend command sending.
-  * @retval None
-  */  
-#define __SDIO_SUSPEND_CMD_DISABLE()   (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
-    
-/**
-  * @brief  Enable the command completion signal.
-  * @retval None
-  */    
-#define __SDIO_CEATA_CMD_COMPLETION_ENABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = ENABLE)
-
-/**
-  * @brief  Disable the command completion signal.
-  * @retval None
-  */  
-#define __SDIO_CEATA_CMD_COMPLETION_DISABLE()   (*(__IO uint32_t *) CMD_ENCMDCOMPL_BB = DISABLE)
-
-/**
-  * @brief  Enable the CE-ATA interrupt.
-  * @retval None
-  */    
-#define __SDIO_CEATA_ENABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)0)
-
-/**
-  * @brief  Disable the CE-ATA interrupt.
-  * @retval None
-  */  
-#define __SDIO_CEATA_DISABLE_IT()   (*(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)1)
-
-/**
-  * @brief  Enable send CE-ATA command (CMD61).
-  * @retval None
-  */  
-#define __SDIO_CEATA_SENDCMD_ENABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = ENABLE)
-
-/**
-  * @brief  Disable send CE-ATA command (CMD61).
-  * @retval None
-  */  
-#define __SDIO_CEATA_SENDCMD_DISABLE()   (*(__IO uint32_t *) CMD_ATACMD_BB = DISABLE)
-  
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/* Exported functions --------------------------------------------------------*/
-/** @addtogroup SDMMC_LL_Exported_Functions
-  * @{
-  */
-  
-/* Initialization/de-initialization functions  **********************************/
-/** @addtogroup HAL_SDMMC_LL_Group1
-  * @{
-  */
-HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init);
-/**
-  * @}
-  */
-
-/* I/O operation functions  *****************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group2
-  * @{
-  */
-/* Blocking mode: Polling */
-uint32_t          SDIO_ReadFIFO(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData);
-/**
-  * @}
-  */
-  
-/* Peripheral Control functions  ************************************************/
-/** @addtogroup HAL_SDMMC_LL_Group3
-  * @{
-  */
-HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx);
-HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetPowerState(SDIO_TypeDef *SDIOx);
-
-/* Command path state machine (CPSM) management functions */
-HAL_StatusTypeDef SDIO_SendCommand(SDIO_TypeDef *SDIOx, SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
-uint8_t           SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetResponse(uint32_t SDIO_RESP);
-
-/* Data path state machine (DPSM) management functions */
-HAL_StatusTypeDef SDIO_DataConfig(SDIO_TypeDef *SDIOx, SDIO_DataInitTypeDef* SDIO_DataInitStruct);
-uint32_t          SDIO_GetDataCounter(SDIO_TypeDef *SDIOx);
-uint32_t          SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx);
-
-/* SDIO IO Cards mode management functions */
-HAL_StatusTypeDef SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */
-  
-/**
-  * @}
-  */ 
-
-/**
-  * @}
-  */
-  
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* STM32L151xD || STM32L152xD || STM32L162xD */
-
-#endif /* __STM32L1xx_LL_SD_H */
-
-/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/

--- a/targets/cmsis/TOOLCHAIN_IAR/cmain.S	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-/**************************************************
- *
- * Part two of the system initialization code, contains C-level
- * initialization, thumb-2 only variant.
- *
- * Copyright 2006 IAR Systems. All rights reserved.
- *
- * $Revision: 59783 $
- *
- **************************************************/
-
-
-; --------------------------------------------------
-; Module ?cmain, C-level initialization.
-;
-
-
-        SECTION SHT$$PREINIT_ARRAY:CONST:NOROOT(2)
-        SECTION SHT$$INIT_ARRAY:CONST:NOROOT(2)
-
-        SECTION .text:CODE:NOROOT(2)
-
-        PUBLIC  __cmain
-        ;; Keep ?main for legacy reasons, it is accessed in countless instances of cstartup.s around the world...
-        PUBLIC  ?main
-        EXTWEAK __iar_data_init3
-        EXTWEAK __iar_argc_argv
-        EXTERN  __low_level_init
-        EXTERN  __call_ctors
-        EXTERN  main
-        EXTERN  exit
-        EXTERN  __iar_dynamic_initialization
-        EXTERN mbed_sdk_init
-        EXTERN SystemInit
-        
-        THUMB
-__cmain:
-?main:
-
-; Initialize segments.
-; __segment_init and __low_level_init are assumed to use the same
-; instruction set and to be reachable by BL from the ICODE segment
-; (it is safest to link them in segment ICODE).
-
-          FUNCALL __cmain, __low_level_init
-        bl      __low_level_init
-        cmp     r0,#0
-        beq     ?l1
-          FUNCALL __cmain, __iar_data_init3
-        bl      __iar_data_init3
-        MOVS    r0,#0             ;  No parameters
-        FUNCALL __cmain, mbed_sdk_init
-        BL      mbed_sdk_init
-        MOVS    r0,#0             ;  No parameters        
-          FUNCALL __cmain, __iar_dynamic_initialization
-        BL      __iar_dynamic_initialization   ; C++ dynamic initialization  
-
-?l1:
-        REQUIRE ?l3
-
-        SECTION .text:CODE:NOROOT(2)
-
-        PUBLIC  _main
-        PUBLIC _call_main
-        THUMB
-
-__iar_init$$done:                 ; Copy initialization is done
-
-?l3:
-_call_main:
-        MOVS    r0,#0             ;  No parameters  
-          FUNCALL __cmain, __iar_argc_argv
-        BL      __iar_argc_argv   ; Maybe setup command line
-
-          FUNCALL __cmain, main
-        BL      main
-_main:
-          FUNCALL __cmain, exit
-        BL      exit
-
-        END

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/PeripheralPins.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_PERIPHERALPINS_H
-#define MBED_PERIPHERALPINS_H
-
-#include "pinmap.h"
-#include "PeripheralNames.h"
-
-//*** ADC ***
-
-extern const PinMap PinMap_ADC[];
-
-//*** DAC ***
-
-extern const PinMap PinMap_DAC[];
-
-//*** I2C ***
-
-extern const PinMap PinMap_I2C_SDA[];
-extern const PinMap PinMap_I2C_SCL[];
-
-//*** PWM ***
-
-extern const PinMap PinMap_PWM[];
-
-//*** SERIAL ***
-
-extern const PinMap PinMap_UART_TX[];
-extern const PinMap PinMap_UART_RX[];
-
-//*** SPI ***
-
-extern const PinMap PinMap_SPI_MOSI[];
-extern const PinMap PinMap_SPI_MISO[];
-extern const PinMap PinMap_SPI_SCLK[];
-extern const PinMap PinMap_SPI_SSEL[];
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PeripheralNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
-    UART_1   = (int)USART1_BASE,
-    UART_2   = (int)USART2_BASE,
-    LPUART_1 = (int)LPUART1_BASE
-} UARTName;
-
-#define STDIO_UART_TX  PA_9
-#define STDIO_UART_RX  PA_10
-#define STDIO_UART     UART_1
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_2  = (int)TIM2_BASE,
-    PWM_21 = (int)TIM21_BASE,
-    PWM_22 = (int)TIM22_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PeripheralPins.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,156 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
-    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
-    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
-    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
-    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
-    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
-    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
-    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
-    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
-    {NC,   NC,    0}
-};
-
-//*** DAC ***
-
-const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // DAC_OUT
-    {NC,   NC,    0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {NC,    NC,    0}
-};
-
-//*** PWM ***
-
-// TIM21 cannot be used because already used by the us_ticker
-const PinMap PinMap_PWM[] = {
-//  {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1 - Warning: user_button is on this pin
-    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
-//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
-//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4 - used by STDIO RX
-    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used also to drive the LED
-    {PA_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
-    {PA_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
-    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
-    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-    {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
-    {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
-    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
-    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
-//  {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1
-//  {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2
-    {NC,    NC,     0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
-    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {NC,    NC,       0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {NC,    NC,      0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PinNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,181 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
-                                                ((PUPD  & 0x07) << 4) |\
-                                                ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
-                                                                       ((PUPD     & 0x07) <<  4) |\
-                                                                       ((AFNUM    & 0x0F) <<  7) |\
-                                                                       ((CHANNEL  & 0x0F) << 11) |\
-                                                                       ((INVERTED & 0x01) << 15)))
-
-#define STM_PIN_MODE(X)     (((X) >>  0) & 0x0F)
-#define STM_PIN_PUPD(X)     (((X) >>  4) & 0x07)
-#define STM_PIN_AFNUM(X)    (((X) >>  7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
-
-#define STM_MODE_INPUT              (0)
-#define STM_MODE_OUTPUT_PP          (1)
-#define STM_MODE_OUTPUT_OD          (2)
-#define STM_MODE_AF_PP              (3)
-#define STM_MODE_AF_OD              (4)
-#define STM_MODE_ANALOG             (5)
-#define STM_MODE_IT_RISING          (6)
-#define STM_MODE_IT_FALLING         (7)
-#define STM_MODE_IT_RISING_FALLING  (8)
-#define STM_MODE_EVT_RISING         (9)
-#define STM_MODE_EVT_FALLING        (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET       (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble  = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PH_0  = 0x70,
-    PH_1  = 0x71,
-
-    // Arduino connector namings
-    // Note: The Arduino connector is not present on this board.
-    // We keep these definitions for compatibility with Nucleo code examples.
-    A0          = PA_1,
-    A1          = PA_2,
-    A2          = PA_3,
-    A3          = PA_4,
-    A4          = PB_0,
-    A5          = PB_1,
-    D0          = PA_10,
-    D1          = PA_9,
-    D2          = PA_8,
-    D3          = PA_6,
-    D4          = PA_13,
-    D5          = PA_7,
-    D6          = PB_11,
-    D7          = PC_13,
-    D8          = PC_14,
-    D9          = PA_15,
-    D10         = PA_5,
-    D11         = PB_15,
-    D12         = PB_14,
-    D13         = PB_13,
-    D14         = PB_9,
-    D15         = PB_8,
-
-    // Generic signals namings
-    LED1        = PB_4,
-    LED2        = PA_5,
-    LED3        = PB_4,
-    LED4        = PA_5,
-    USER_BUTTON = PA_0,
-    SERIAL_TX   = PA_9,
-    SERIAL_RX   = PA_10,
-    USBTX       = PA_9,
-    USBRX       = PA_10,
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PB_15,
-    SPI_MISO    = PB_14,
-    SPI_SCK     = PB_13,
-    SPI_CS      = PB_12,
-    PWM_OUT     = PB_11,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullNone  = 0,
-    PullUp    = 1,
-    PullDown  = 2,
-    OpenDrain = 3,
-    PullDefault = PullNone
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/PortNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PortA = 0,
-    PortB = 1,
-    PortC = 2,
-    PortD = 3,
-    PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/device.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SLEEP            1
-
-//=======================================
-
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       24
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        0
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/objects.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
-    ADCName adc;
-    PinName pin;
-    uint32_t channel;
-};
-
-struct dac_s {
-    DACName dac;
-    PinName pin;
-    uint32_t channel;
-};
-
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName  pin_tx;
-    PinName  pin_rx;
-};
-
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
-struct i2c_s {
-    I2CName  i2c;
-};
-
-struct pwmout_s {
-    PWMName pwm;
-    PinName pin;
-    uint32_t period;
-    uint32_t pulse;
-    uint32_t channel;
-    uint32_t inverted;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_DISCO_L053C8/rtc_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,215 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "rtc_api.h"
-
-/* The mcu STM32L053C8 seems to have a problem in the RCC - LSE hardware block. The Disco_L053 don't have a 32kHz crystal connected to LSE port pins.
- * During initialization the HAL tests if it can start the LSE oscillator. The Flag LSERDY in RCC_CSR should be set to 1 by RCC clock control when
- * the oscillator runs stable. Without a crystal the flag shouldn't be set and the HAL trys to start the internal LSI oscillator.
- * But the flag is also set to 1 without a crystal. That's why the RTC doesn't start.
- *
- */
-#define DONT_USE_LSE
-
-#if DEVICE_RTC
-
-#include "mbed_error.h"
-
-static int rtc_inited = 0;
-
-static RTC_HandleTypeDef RtcHandle;
-
-void rtc_init(void)
-{
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    uint32_t rtc_freq = 0;
-
-    if (rtc_inited) return;
-    rtc_inited = 1;
-
-    RtcHandle.Instance = RTC;
-
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
-    // Enable LSE Oscillator
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-#ifndef DONT_USE_LSE
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-        // Connect LSE to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
-        rtc_freq = LSE_VALUE;
-    } else {
-#endif
-        // Enable LSI clock
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
-        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-            error("RTC error: LSI clock initialization failed.");
-        }
-        // Connect LSI to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
-        // This value is LSI typical value. To be measured precisely using a timer input capture for example.
-        rtc_freq = 37000;
-#ifndef DONT_USE_LSE
-    }
-#endif
-
-    // Enable RTC
-    __HAL_RCC_RTC_ENABLE();
-
-    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
-    RtcHandle.Init.AsynchPrediv   = 127;
-    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
-    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
-    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
-    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
-
-    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
-        error("RTC error: RTC initialization failed.");
-    }
-}
-
-void rtc_free(void)
-{
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
-    // Disable access to Backup domain
-    HAL_PWR_DisableBkUpAccess();
-
-    // Disable LSI and LSE clocks
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
-    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
-    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-    HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-    rtc_inited = 0;
-}
-
-int rtc_isenabled(void)
-{
-    return rtc_inited;
-}
-
-/*
- RTC Registers
-   RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
-   RTC_Month   1=january, 2=february, ..., 12=december
-   RTC_Date    day of the month 1-31
-   RTC_Year    year 0-99
- struct tm
-   tm_sec      seconds after the minute 0-61
-   tm_min      minutes after the hour 0-59
-   tm_hour     hours since midnight 0-23
-   tm_mday     day of the month 1-31
-   tm_mon      months since January 0-11
-   tm_year     years since 1900
-   tm_wday     days since Sunday 0-6
-   tm_yday     days since January 1 0-365
-   tm_isdst    Daylight Saving Time flag
-*/
-time_t rtc_read(void)
-{
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
-    struct tm timeinfo;
-
-    RtcHandle.Instance = RTC;
-
-    // Read actual date and time
-    // Warning: the time must be read first!
-    HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
-    HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
-
-    // Setup a tm structure based on the RTC
-    timeinfo.tm_wday = dateStruct.WeekDay;
-    timeinfo.tm_mon  = dateStruct.Month - 1;
-    timeinfo.tm_mday = dateStruct.Date;
-    timeinfo.tm_year = dateStruct.Year + 100;
-    timeinfo.tm_hour = timeStruct.Hours;
-    timeinfo.tm_min  = timeStruct.Minutes;
-    timeinfo.tm_sec  = timeStruct.Seconds;
-
-    // Convert to timestamp
-    time_t t = mktime(&timeinfo);
-
-    return t;
-}
-
-void rtc_write(time_t t)
-{
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
-
-    RtcHandle.Instance = RTC;
-
-    // Convert the time into a tm
-    struct tm *timeinfo = localtime(&t);
-
-    // Fill RTC structures
-    dateStruct.WeekDay        = timeinfo->tm_wday;
-    dateStruct.Month          = timeinfo->tm_mon + 1;
-    dateStruct.Date           = timeinfo->tm_mday;
-    dateStruct.Year           = timeinfo->tm_year - 100;
-    timeStruct.Hours          = timeinfo->tm_hour;
-    timeStruct.Minutes        = timeinfo->tm_min;
-    timeStruct.Seconds        = timeinfo->tm_sec;
-    timeStruct.TimeFormat     = RTC_HOURFORMAT12_PM;
-    timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
-    timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
-
-    // Change the RTC current date/time
-    HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
-    HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
-    UART_1   = (int)USART1_BASE,
-    UART_2   = (int)USART2_BASE,
-    LPUART_1 = (int)LPUART1_BASE
-} UARTName;
-
-#define STDIO_UART_TX  PA_2
-#define STDIO_UART_RX  PA_3
-#define STDIO_UART     UART_2
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_2  = (int)TIM2_BASE,
-    PWM_21 = (int)TIM21_BASE,
-    PWM_22 = (int)TIM22_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PeripheralPins.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,170 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
-    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
-    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
-    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
-    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
-    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
-    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
-    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
-    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
-    {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
-    {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
-    {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
-    {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
-    {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
-    {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
-    {NC,   NC,    0}
-};
-
-//*** DAC ***
-
-const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // DAC_OUT
-    {NC,   NC,    0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {NC,    NC,    0}
-};
-
-//*** PWM ***
-
-// TIM21 cannot be used because already used by the us_ticker
-const PinMap PinMap_PWM[] = {
-    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1
-    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
-//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
-//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4 - used by STDIO RX
-    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used also to drive the LED
-    {PA_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
-    {PA_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
-    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
-    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-    {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
-    {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
-    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
-    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
-//  {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1
-//  {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2
-    {PC_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 1, 0)}, // TIM22_CH1
-    {PC_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 2, 0)}, // TIM22_CH2
-    {NC,    NC,     0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
-    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PC_4,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
-    {PC_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
-    {NC,    NC,       0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PC_5,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
-    {PC_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
-    {NC,    NC,      0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PinNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,194 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
-                                                ((PUPD  & 0x07) << 4) |\
-                                                ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
-                                                                       ((PUPD     & 0x07) <<  4) |\
-                                                                       ((AFNUM    & 0x0F) <<  7) |\
-                                                                       ((CHANNEL  & 0x0F) << 11) |\
-                                                                       ((INVERTED & 0x01) << 15)))
-
-#define STM_PIN_MODE(X)     (((X) >>  0) & 0x0F)
-#define STM_PIN_PUPD(X)     (((X) >>  4) & 0x07)
-#define STM_PIN_AFNUM(X)    (((X) >>  7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
-
-#define STM_MODE_INPUT              (0)
-#define STM_MODE_OUTPUT_PP          (1)
-#define STM_MODE_OUTPUT_OD          (2)
-#define STM_MODE_AF_PP              (3)
-#define STM_MODE_AF_OD              (4)
-#define STM_MODE_ANALOG             (5)
-#define STM_MODE_IT_RISING          (6)
-#define STM_MODE_IT_FALLING         (7)
-#define STM_MODE_IT_RISING_FALLING  (8)
-#define STM_MODE_EVT_RISING         (9)
-#define STM_MODE_EVT_FALLING        (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET       (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble  = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_0  = 0x20,
-    PC_1  = 0x21,
-    PC_2  = 0x22,
-    PC_3  = 0x23,
-    PC_4  = 0x24,
-    PC_5  = 0x25,
-    PC_6  = 0x26,
-    PC_7  = 0x27,
-    PC_8  = 0x28,
-    PC_9  = 0x29,
-    PC_10 = 0x2A,
-    PC_11 = 0x2B,
-    PC_12 = 0x2C,
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PD_2  = 0x32,
-
-    PH_0  = 0x70,
-    PH_1  = 0x71,
-
-    // Arduino connector namings
-    A0          = PA_0,
-    A1          = PA_1,
-    A2          = PA_4,
-    A3          = PB_0,
-    A4          = PC_1,
-    A5          = PC_0,
-    D0          = PA_3,
-    D1          = PA_2,
-    D2          = PA_10,
-    D3          = PB_3,
-    D4          = PB_5,
-    D5          = PB_4,
-    D6          = PB_10,
-    D7          = PA_8,
-    D8          = PA_9,
-    D9          = PC_7,
-    D10         = PB_6,
-    D11         = PA_7,
-    D12         = PA_6,
-    D13         = PA_5,
-    D14         = PB_9,
-    D15         = PB_8,
-
-    // Generic signals namings
-    LED1        = PA_5,
-    LED2        = PA_5,
-    LED3        = PA_5,
-    LED4        = PA_5,
-    USER_BUTTON = PC_13,
-    SERIAL_TX   = PA_2,
-    SERIAL_RX   = PA_3,
-    USBTX       = PA_2,
-    USBRX       = PA_3,
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PA_7,
-    SPI_MISO    = PA_6,
-    SPI_SCK     = PA_5,
-    SPI_CS      = PB_6,
-    PWM_OUT     = PB_3,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullNone  = 0,
-    PullUp    = 1,
-    PullDown  = 2,
-    OpenDrain = 3,
-    PullDefault = PullNone
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/PortNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PortA = 0,
-    PortB = 1,
-    PortC = 2,
-    PortD = 3,
-    PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/device.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SLEEP            1
-
-//=======================================
-
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       24
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        0
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/objects.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
-    ADCName adc;
-    PinName pin;
-    uint32_t channel;
-};
-
-struct dac_s {
-    DACName dac;
-    PinName pin;
-    uint32_t channel;
-};
-
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName  pin_tx;
-    PinName  pin_rx;
-};
-
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
-struct i2c_s {
-    I2CName  i2c;
-};
-
-struct pwmout_s {
-    PWMName pwm;
-    PinName pin;
-    uint32_t period;
-    uint32_t pulse;
-    uint32_t channel;
-    uint32_t inverted;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/rtc_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,203 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "rtc_api.h"
-
-#if DEVICE_RTC
-
-#include "mbed_error.h"
-
-static int rtc_inited = 0;
-
-static RTC_HandleTypeDef RtcHandle;
-
-void rtc_init(void)
-{
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    uint32_t rtc_freq = 0;
-
-    if (rtc_inited) return;
-    rtc_inited = 1;
-
-    RtcHandle.Instance = RTC;
-
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
-    // Enable LSE Oscillator
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-        // Connect LSE to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
-        rtc_freq = LSE_VALUE;
-    } else {
-        // Enable LSI clock
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
-        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-            error("RTC error: LSI clock initialization failed.");
-        }
-        // Connect LSI to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
-        // This value is LSI typical value. To be measured precisely using a timer input capture for example.
-        rtc_freq = 32000;
-    }
-
-    // Enable RTC
-    __HAL_RCC_RTC_ENABLE();
-
-    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
-    RtcHandle.Init.AsynchPrediv   = 127;
-    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
-    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
-    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
-    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
-
-    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
-        error("RTC error: RTC initialization failed.");
-    }
-}
-
-void rtc_free(void)
-{
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
-    // Disable access to Backup domain
-    HAL_PWR_DisableBkUpAccess();
-
-    // Disable LSI and LSE clocks
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
-    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
-    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-    HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-    rtc_inited = 0;
-}
-
-int rtc_isenabled(void)
-{
-    return rtc_inited;
-}
-
-/*
- RTC Registers
-   RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
-   RTC_Month   1=january, 2=february, ..., 12=december
-   RTC_Date    day of the month 1-31
-   RTC_Year    year 0-99
- struct tm
-   tm_sec      seconds after the minute 0-61
-   tm_min      minutes after the hour 0-59
-   tm_hour     hours since midnight 0-23
-   tm_mday     day of the month 1-31
-   tm_mon      months since January 0-11
-   tm_year     years since 1900
-   tm_wday     days since Sunday 0-6
-   tm_yday     days since January 1 0-365
-   tm_isdst    Daylight Saving Time flag
-*/
-time_t rtc_read(void)
-{
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
-    struct tm timeinfo;
-
-    RtcHandle.Instance = RTC;
-
-    // Read actual date and time
-    // Warning: the time must be read first!
-    HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
-    HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
-
-    // Setup a tm structure based on the RTC
-    timeinfo.tm_wday = dateStruct.WeekDay;
-    timeinfo.tm_mon  = dateStruct.Month - 1;
-    timeinfo.tm_mday = dateStruct.Date;
-    timeinfo.tm_year = dateStruct.Year + 100;
-    timeinfo.tm_hour = timeStruct.Hours;
-    timeinfo.tm_min  = timeStruct.Minutes;
-    timeinfo.tm_sec  = timeStruct.Seconds;
-
-    // Convert to timestamp
-    time_t t = mktime(&timeinfo);
-
-    return t;
-}
-
-void rtc_write(time_t t)
-{
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
-
-    RtcHandle.Instance = RTC;
-
-    // Convert the time into a tm
-    struct tm *timeinfo = localtime(&t);
-
-    // Fill RTC structures
-    dateStruct.WeekDay        = timeinfo->tm_wday;
-    dateStruct.Month          = timeinfo->tm_mon + 1;
-    dateStruct.Date           = timeinfo->tm_mday;
-    dateStruct.Year           = timeinfo->tm_year - 100;
-    timeStruct.Hours          = timeinfo->tm_hour;
-    timeStruct.Minutes        = timeinfo->tm_min;
-    timeStruct.Seconds        = timeinfo->tm_sec;
-    timeStruct.TimeFormat     = RTC_HOURFORMAT12_PM;
-    timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
-    timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
-
-    // Change the RTC current date/time
-    HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
-    HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,81 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
-    UART_1   = (int)USART1_BASE,
-    UART_2   = (int)USART2_BASE,
-    UART_4   = (int)USART4_BASE,
-    UART_5   = (int)USART5_BASE,
-    LPUART_1 = (int)LPUART1_BASE
-} UARTName;
-
-#define STDIO_UART_TX  PA_2
-#define STDIO_UART_RX  PA_3
-#define STDIO_UART     UART_2
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE,
-    I2C_3 = (int)I2C3_BASE
-} I2CName;
-
-typedef enum {
-    PWM_2  = (int)TIM2_BASE,
-    PWM_3  = (int)TIM3_BASE,
-    PWM_21 = (int)TIM21_BASE,
-    PWM_22 = (int)TIM22_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PeripheralPins.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,206 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
-    {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
-    {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
-    {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
-    {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
-    {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
-    {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
-    {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
-    {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
-    {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
-    {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
-    {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
-    {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
-    {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
-    {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
-    {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
-    {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
-    {NC,   NC,    0}
-};
-
-//*** DAC ***
-
-const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // DAC_OUT1
-    {PA_5, DAC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // DAC_OUT2
-    {NC,   NC,    0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
-    {PA_10, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
-    {PA_12, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_4,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)},
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_14, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {PC_1,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)},
-    {PC_9,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {PA_8,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)},
-    {PA_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C1)},
-    {PA_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF1_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF6_I2C2)},
-    {PB_13, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF5_I2C2)},
-    {PC_0,  I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF7_I2C3)},
-    {NC,    NC,    0}
-};
-
-//*** PWM ***
-
-// TIM21 cannot be used because already used by the us_ticker
-const PinMap PinMap_PWM[] = {
-    {PA_0,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 1, 0)},  // TIM2_CH1
-    {PA_1,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-//  {PA_2,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 1, 0)}, // TIM21_CH1
-//  {PA_2,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3 - used by STDIO TX
-//  {PA_3,  PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM21, 2, 0)}, // TIM21_CH2
-//  {PA_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4 - used by STDIO RX
-    {PA_5,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1 - used also to drive the LED
-    {PA_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 1, 0)}, // TIM22_CH1
-//  {PA_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
-    {PA_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM22, 2, 0)}, // TIM22_CH2
-//  {PA_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
-    {PA_15, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_TIM2, 1, 0)},  // TIM2_CH1
-    {PB_0,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
-    {PB_1,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
-    {PB_3,  PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 2, 0)},  // TIM2_CH2
-    {PB_4,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 1, 0)}, // TIM22_CH1
-//  {PB_4,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
-    {PB_5,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_TIM22, 2, 0)}, // TIM22_CH2
-//  {PB_5,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
-    {PB_10, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 3, 0)},  // TIM2_CH3
-    {PB_11, PWM_2,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM2, 4, 0)},  // TIM2_CH4
-//  {PB_13, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 1, 0)}, // TIM21_CH1
-//  {PB_14, PWM_21, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_TIM21, 2, 0)}, // TIM21_CH2
-    {PC_6,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 1, 0)}, // TIM22_CH1
-//  {PC_6,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)},  // TIM3_CH1
-    {PC_7,  PWM_22, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_TIM22, 2, 0)}, // TIM22_CH2
-//  {PC_7,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)},  // TIM3_CH2
-    {PC_8,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)},  // TIM3_CH3
-    {PC_9,  PWM_3,  STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)},  // TIM3_CH4
-    {NC,    NC,     0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
-    {PA_0,  UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)},
-    {PA_2,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-//  {PA_2,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PA_9,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-//  {PA_14, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)}, // Warning: this pin is used by SWCLK
-//  {PA_14, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Warning: this pin is used by SWCLK
-    {PB_3,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)},
-    {PB_6,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-    {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-//  {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Already used by UART_RX
-    {PC_1,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PC_4,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
-//  {PC_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
-    {PC_10, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)},
-    {PC_12, UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_USART5)},
-    {NC,    NC,       0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {PA_1,  UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)},
-    {PA_3,  UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-//  {PA_3,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PA_10, UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART1)},
-//  {PA_13, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Warning: this pin is used by SWDIO
-    {PA_15, UART_2,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_USART2)},
-    {PB_4,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)},
-    {PB_7,  UART_1,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_USART1)},
-//  {PB_10, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)}, // Already used by UART_TX
-    {PB_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF4_LPUART1)},
-    {PC_0,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_LPUART1)},
-    {PC_5,  LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_LPUART1)},
-//  {PC_11, LPUART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_LPUART1)},
-    {PC_11, UART_4,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART4)},
-    {PD_2,  UART_5,   STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_USART5)},
-    {NC,    NC,      0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {PC_3,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {PC_2,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI1)},
-    {PB_9,  SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF0_SPI2)},
-    {NC,    NC,    0}
-};

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PinNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,194 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((MODE  & 0x0F) << 0) |\
-                                                ((PUPD  & 0x07) << 4) |\
-                                                ((AFNUM & 0x0F) << 7)))
-
-#define STM_PIN_DATA_EXT(MODE, PUPD, AFNUM, CHANNEL, INVERTED)  ((int)(((MODE     & 0x0F) <<  0) |\
-                                                                       ((PUPD     & 0x07) <<  4) |\
-                                                                       ((AFNUM    & 0x0F) <<  7) |\
-                                                                       ((CHANNEL  & 0x0F) << 11) |\
-                                                                       ((INVERTED & 0x01) << 15)))
-
-#define STM_PIN_MODE(X)     (((X) >>  0) & 0x0F)
-#define STM_PIN_PUPD(X)     (((X) >>  4) & 0x07)
-#define STM_PIN_AFNUM(X)    (((X) >>  7) & 0x0F)
-#define STM_PIN_CHANNEL(X)  (((X) >> 11) & 0x0F)
-#define STM_PIN_INVERTED(X) (((X) >> 15) & 0x01)
-
-#define STM_MODE_INPUT              (0)
-#define STM_MODE_OUTPUT_PP          (1)
-#define STM_MODE_OUTPUT_OD          (2)
-#define STM_MODE_AF_PP              (3)
-#define STM_MODE_AF_OD              (4)
-#define STM_MODE_ANALOG             (5)
-#define STM_MODE_IT_RISING          (6)
-#define STM_MODE_IT_FALLING         (7)
-#define STM_MODE_IT_RISING_FALLING  (8)
-#define STM_MODE_EVT_RISING         (9)
-#define STM_MODE_EVT_FALLING        (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET       (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble  = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_0  = 0x20,
-    PC_1  = 0x21,
-    PC_2  = 0x22,
-    PC_3  = 0x23,
-    PC_4  = 0x24,
-    PC_5  = 0x25,
-    PC_6  = 0x26,
-    PC_7  = 0x27,
-    PC_8  = 0x28,
-    PC_9  = 0x29,
-    PC_10 = 0x2A,
-    PC_11 = 0x2B,
-    PC_12 = 0x2C,
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PD_2  = 0x32,
-
-    PH_0  = 0x70,
-    PH_1  = 0x71,
-
-    // Arduino connector namings
-    A0          = PA_0,
-    A1          = PA_1,
-    A2          = PA_4,
-    A3          = PB_0,
-    A4          = PC_1,
-    A5          = PC_0,
-    D0          = PA_3,
-    D1          = PA_2,
-    D2          = PA_10,
-    D3          = PB_3,
-    D4          = PB_5,
-    D5          = PB_4,
-    D6          = PB_10,
-    D7          = PA_8,
-    D8          = PA_9,
-    D9          = PC_7,
-    D10         = PB_6,
-    D11         = PA_7,
-    D12         = PA_6,
-    D13         = PA_5,
-    D14         = PB_9,
-    D15         = PB_8,
-
-    // Generic signals namings
-    LED1        = PA_5,
-    LED2        = PA_5,
-    LED3        = PA_5,
-    LED4        = PA_5,
-    USER_BUTTON = PC_13,
-    SERIAL_TX   = PA_2,
-    SERIAL_RX   = PA_3,
-    USBTX       = PA_2,
-    USBRX       = PA_3,
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PA_7,
-    SPI_MISO    = PA_6,
-    SPI_SCK     = PA_5,
-    SPI_CS      = PB_6,
-    PWM_OUT     = PB_3,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullNone  = 0,
-    PullUp    = 1,
-    PullDown  = 2,
-    OpenDrain = 3,
-    PullDefault = PullNone
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/PortNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PortA = 0,
-    PortB = 1,
-    PortC = 2,
-    PortD = 3,
-    PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SLEEP            1
-
-//=======================================
-
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       24
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        0
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/objects.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
-    ADCName adc;
-    PinName pin;
-    uint32_t channel;
-};
-
-struct dac_s {
-    DACName dac;
-    PinName pin;
-    uint32_t channel;
-};
-
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName  pin_tx;
-    PinName  pin_rx;
-};
-
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
-struct i2c_s {
-    I2CName  i2c;
-};
-
-struct pwmout_s {
-    PWMName pwm;
-    PinName pin;
-    uint32_t period;
-    uint32_t pulse;
-    uint32_t channel;
-    uint32_t inverted;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/rtc_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,203 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "rtc_api.h"
-
-#if DEVICE_RTC
-
-#include "mbed_error.h"
-
-static int rtc_inited = 0;
-
-static RTC_HandleTypeDef RtcHandle;
-
-void rtc_init(void)
-{
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    uint32_t rtc_freq = 0;
-
-    if (rtc_inited) return;
-    rtc_inited = 1;
-
-    RtcHandle.Instance = RTC;
-
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
-    // Enable LSE Oscillator
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-        // Connect LSE to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
-        rtc_freq = LSE_VALUE;
-    } else {
-        // Enable LSI clock
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
-        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-            error("RTC error: LSI clock initialization failed.");
-        }
-        // Connect LSI to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
-        // This value is LSI typical value. To be measured precisely using a timer input capture for example.
-        rtc_freq = 32000;
-    }
-
-    // Enable RTC
-    __HAL_RCC_RTC_ENABLE();
-
-    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
-    RtcHandle.Init.AsynchPrediv   = 127;
-    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
-    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
-    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
-    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
-
-    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
-        error("RTC error: RTC initialization failed.");
-    }
-}
-
-void rtc_free(void)
-{
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
-    // Disable access to Backup domain
-    HAL_PWR_DisableBkUpAccess();
-
-    // Disable LSI and LSE clocks
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
-    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
-    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-    HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-    rtc_inited = 0;
-}
-
-int rtc_isenabled(void)
-{
-    return rtc_inited;
-}
-
-/*
- RTC Registers
-   RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
-   RTC_Month   1=january, 2=february, ..., 12=december
-   RTC_Date    day of the month 1-31
-   RTC_Year    year 0-99
- struct tm
-   tm_sec      seconds after the minute 0-61
-   tm_min      minutes after the hour 0-59
-   tm_hour     hours since midnight 0-23
-   tm_mday     day of the month 1-31
-   tm_mon      months since January 0-11
-   tm_year     years since 1900
-   tm_wday     days since Sunday 0-6
-   tm_yday     days since January 1 0-365
-   tm_isdst    Daylight Saving Time flag
-*/
-time_t rtc_read(void)
-{
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
-    struct tm timeinfo;
-
-    RtcHandle.Instance = RTC;
-
-    // Read actual date and time
-    // Warning: the time must be read first!
-    HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
-    HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
-
-    // Setup a tm structure based on the RTC
-    timeinfo.tm_wday = dateStruct.WeekDay;
-    timeinfo.tm_mon  = dateStruct.Month - 1;
-    timeinfo.tm_mday = dateStruct.Date;
-    timeinfo.tm_year = dateStruct.Year + 100;
-    timeinfo.tm_hour = timeStruct.Hours;
-    timeinfo.tm_min  = timeStruct.Minutes;
-    timeinfo.tm_sec  = timeStruct.Seconds;
-
-    // Convert to timestamp
-    time_t t = mktime(&timeinfo);
-
-    return t;
-}
-
-void rtc_write(time_t t)
-{
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
-
-    RtcHandle.Instance = RTC;
-
-    // Convert the time into a tm
-    struct tm *timeinfo = localtime(&t);
-
-    // Fill RTC structures
-    dateStruct.WeekDay        = timeinfo->tm_wday;
-    dateStruct.Month          = timeinfo->tm_mon + 1;
-    dateStruct.Date           = timeinfo->tm_mday;
-    dateStruct.Year           = timeinfo->tm_year - 100;
-    timeStruct.Hours          = timeinfo->tm_hour;
-    timeStruct.Minutes        = timeinfo->tm_min;
-    timeStruct.Seconds        = timeinfo->tm_sec;
-    timeStruct.TimeFormat     = RTC_HOURFORMAT12_PM;
-    timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
-    timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
-
-    // Change the RTC current date/time
-    HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
-    HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/analogin_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,185 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-ADC_HandleTypeDef AdcHandle;
-
-int adc_inited = 0;
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    // Get the peripheral name from the pin and assign it to the object
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-    MBED_ASSERT(obj->adc != (ADCName)NC);
-
-    // Get the pin function and assign the used channel to the object
-    uint32_t function = pinmap_function(pin, PinMap_ADC);
-    MBED_ASSERT(function != (uint32_t)NC);
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Configure GPIO
-    pinmap_pinout(pin, PinMap_ADC);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // The ADC initialization is done once
-    if (adc_inited == 0) {
-        adc_inited = 1;
-
-        AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
-        // Enable ADC clock
-        __ADC1_CLK_ENABLE();
-
-        // Configure ADC
-        AdcHandle.Init.OversamplingMode      = DISABLE;
-        AdcHandle.Init.ClockPrescaler        = ADC_CLOCKPRESCALER_PCLK_DIV1;
-        AdcHandle.Init.Resolution            = ADC_RESOLUTION12b;
-        AdcHandle.Init.SamplingTime          = ADC_SAMPLETIME_41CYCLES_5;
-        AdcHandle.Init.ScanConvMode          = ADC_SCAN_DIRECTION_FORWARD;
-        AdcHandle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-        AdcHandle.Init.ContinuousConvMode    = DISABLE;
-        AdcHandle.Init.DiscontinuousConvMode = DISABLE;
-        AdcHandle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIG_EDGE_NONE;
-        AdcHandle.Init.ExternalTrigConv      = ADC_EXTERNALTRIG0_T6_TRGO; // Not used here
-        AdcHandle.Init.DMAContinuousRequests = DISABLE;
-        AdcHandle.Init.EOCSelection          = EOC_SINGLE_CONV;
-        AdcHandle.Init.Overrun               = OVR_DATA_OVERWRITTEN;
-        AdcHandle.Init.LowPowerAutoWait      = ENABLE;
-        AdcHandle.Init.LowPowerFrequencyMode = DISABLE; // To be enabled only if ADC clock < 2.8 MHz
-        AdcHandle.Init.LowPowerAutoPowerOff  = DISABLE;
-
-        if (HAL_ADC_Init(&AdcHandle) != HAL_OK) {
-            error("Cannot initialize ADC");
-        }
-
-        // Calibration
-        HAL_ADCEx_Calibration_Start(&AdcHandle, ADC_SINGLE_ENDED);
-
-        __HAL_ADC_ENABLE(&AdcHandle);
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig = {0};
-
-    AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
-    // Configure ADC channel
-    switch (obj->channel) {
-        case 0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case 1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case 2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case 3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case 4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case 5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case 6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case 7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case 8:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case 9:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case 10:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case 11:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case 12:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case 13:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case 14:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case 15:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        default:
-            return 0;
-    }
-
-    ADC1->CHSELR = 0; // [TODO] Workaround. To be removed after Cube driver is corrected.
-    HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
-
-    HAL_ADC_Start(&AdcHandle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&AdcHandle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/analogout_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,168 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogout_api.h"
-
-#if DEVICE_ANALOGOUT
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-#define DAC_RANGE (0xFFF) // 12 bits
-
-static DAC_HandleTypeDef DacHandle;
-
-// These variables are used for the "free" function
-static int channel1_used = 0;
-static int channel2_used = 0;
-
-void analogout_init(dac_t *obj, PinName pin)
-{
-    DAC_ChannelConfTypeDef sConfig;
-
-    // Get the peripheral name from the pin and assign it to the object
-    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
-    MBED_ASSERT(obj->dac != (DACName)NC);
-
-    // Get the pin function and assign the used channel to the object
-    uint32_t function = pinmap_function(pin, PinMap_DAC);
-    MBED_ASSERT(function != (uint32_t)NC);
-    obj->channel = STM_PIN_CHANNEL(function);
-
-    // Configure GPIO
-    pinmap_pinout(pin, PinMap_DAC);
-
-    // Save the pin for future use
-    obj->pin = pin;
-
-    // Enable DAC clock
-    __DAC_CLK_ENABLE();
-
-    // Configure DAC
-    DacHandle.Instance = DAC;
-
-    sConfig.DAC_Trigger      = DAC_TRIGGER_NONE;
-    sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
-
-#if defined(DAC_CHANNEL_2)
-    if (obj->channel == 2) {
-        if (HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2) != HAL_OK) {
-            error("Cannot configure DAC channel 2");
-        }
-        channel2_used = 1;
-    } else
-#endif
-    {
-        // channel 1 per default
-        if (HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1) != HAL_OK) {
-            error("Cannot configure DAC channel 1");
-        }
-        obj->channel = 1;
-        channel1_used = 1;
-    }
-
-    analogout_write_u16(obj, 0);
-}
-
-void analogout_free(dac_t *obj)
-{
-    // Reset DAC and disable clock
-    if (obj->channel == 1) channel1_used = 0;
-    if (obj->channel == 2) channel2_used = 0;
-
-    if ((channel1_used == 0) && (channel2_used == 0)) {
-        __DAC_FORCE_RESET();
-        __DAC_RELEASE_RESET();
-        __DAC_CLK_DISABLE();
-    }
-
-    // Configure GPIO
-    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-static inline void dac_write(dac_t *obj, uint16_t value)
-{
-    if (obj->channel == 1) {
-        HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value);
-        HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1);
-    }
-#if defined(DAC_CHANNEL_2)
-    if (obj->channel == 2) {
-        HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value);
-        HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2);
-    }
-#endif
-}
-
-static inline int dac_read(dac_t *obj)
-{
-    if (obj->channel == 1) {
-        return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1);
-    }
-#if defined(DAC_CHANNEL_2)
-    if (obj->channel == 2) {
-        return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2);
-    }
-#endif
-    return 0;
-}
-
-void analogout_write(dac_t *obj, float value)
-{
-    if (value < 0.0f) {
-        dac_write(obj, 0); // Min value
-    } else if (value > 1.0f) {
-        dac_write(obj, (uint16_t)DAC_RANGE); // Max value
-    } else {
-        dac_write(obj, (uint16_t)(value * (float)DAC_RANGE));
-    }
-}
-
-void analogout_write_u16(dac_t *obj, uint16_t value)
-{
-    if (value > (uint16_t)DAC_RANGE) {
-        dac_write(obj, (uint16_t)DAC_RANGE); // Max value
-    } else {
-        dac_write(obj, value);
-    }
-}
-
-float analogout_read(dac_t *obj)
-{
-    uint32_t value = dac_read(obj);
-    return (float)((float)value * (1.0f / (float)DAC_RANGE));
-}
-
-uint16_t analogout_read_u16(dac_t *obj)
-{
-    return (uint16_t)dac_read(obj);
-}
-
-#endif // DEVICE_ANALOGOUT

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/gpio_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
-    MBED_ASSERT(pin != (PinName)NC);
-
-    pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
-    obj->pin = pin;
-    if (pin == (PinName)NC)
-        return;
-
-    uint32_t port_index = STM_PORT(pin);
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
-    // Fill GPIO object structure for future use
-    obj->mask    = gpio_set(pin);
-    obj->reg_in  = &gpio->IDR;
-    obj->reg_set = &gpio->BSRR;
-    obj->reg_clr = &gpio->BRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
-    pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    if (direction == PIN_OUTPUT) {
-        pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
-    } else { // PIN_INPUT
-        pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    }
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/gpio_irq_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,267 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include <stddef.h>
-#include "cmsis.h"
-#include "gpio_irq_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-#define EDGE_NONE (0)
-#define EDGE_RISE (1)
-#define EDGE_FALL (2)
-#define EDGE_BOTH (3)
-
-// Number of EXTI irq vectors (EXTI0_1, EXTI2_3, EXTI4_15)
-#define CHANNEL_NUM (3)
-
-// Max pins for one line (max with EXTI4_15)
-#define MAX_PIN_LINE (12)
-
-typedef struct gpio_channel {
-    uint32_t pin_mask;                   // bitmask representing which pins are configured for receiving interrupts
-    uint32_t channel_ids[MAX_PIN_LINE];  // mbed "gpio_irq_t gpio_irq" field of instance
-    uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
-    uint32_t channel_pin[MAX_PIN_LINE];  // pin number in port group
-} gpio_channel_t;
-
-static gpio_channel_t channels[CHANNEL_NUM] = {
-    {.pin_mask = 0},
-    {.pin_mask = 0},
-    {.pin_mask = 0}
-};
-
-// Used to return the index for channels array.
-static uint32_t pin_base_nr[16] = {
-    // EXTI0_1
-    0, // pin 0
-    1, // pin 1
-    // EXTI2_3
-    0, // pin 2
-    1, // pin 3
-    // EXTI4_15
-    0, // pin 4
-    1, // pin 5
-    2, // pin 6
-    3, // pin 7
-    4, // pin 8
-    5, // pin 9
-    6, // pin 10
-    7, // pin 11
-    8, // pin 12
-    9, // pin 13
-    10, // pin 14
-    11  // pin 15
-};
-
-static gpio_irq_handler irq_handler;
-
-static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
-{
-    gpio_channel_t *gpio_channel = &channels[irq_index];
-    uint32_t gpio_idx;
-
-    for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
-        uint32_t current_mask = (1 << gpio_idx);
-
-        if (gpio_channel->pin_mask & current_mask) {
-            // Retrieve the gpio and pin that generate the irq
-            GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
-            uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
-
-            // Clear interrupt flag
-            if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
-                __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
-
-                if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
-
-                // Check which edge has generated the irq
-                if ((gpio->IDR & pin) == 0) {
-                    irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
-                } else  {
-                    irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
-                }
-            }
-        }
-    }
-}
-
-// EXTI lines 0 to 1
-static void gpio_irq0(void)
-{
-    handle_interrupt_in(0, 2);
-}
-
-// EXTI lines 2 to 3
-static void gpio_irq1(void)
-{
-    handle_interrupt_in(1, 2);
-}
-
-// EXTI lines 4 to 15
-static void gpio_irq2(void)
-{
-    handle_interrupt_in(2, 12);
-}
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
-{
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    uint32_t irq_index;
-    gpio_channel_t *gpio_channel;
-    uint32_t gpio_idx;
-
-    if (pin == NC) return -1;
-
-    uint32_t port_index = STM_PORT(pin);
-    uint32_t pin_index  = STM_PIN(pin);
-
-    // Select irq number and interrupt routine
-    if ((pin_index == 0) || (pin_index == 1)) {
-        irq_n = EXTI0_1_IRQn;
-        vector = (uint32_t)&gpio_irq0;
-        irq_index = 0;
-    } else if ((pin_index == 2) || (pin_index == 3)) {
-        irq_n = EXTI2_3_IRQn;
-        vector = (uint32_t)&gpio_irq1;
-        irq_index = 1;
-    } else if ((pin_index > 3) && (pin_index < 16)) {
-        irq_n = EXTI4_15_IRQn;
-        vector = (uint32_t)&gpio_irq2;
-        irq_index = 2;
-    } else {
-        error("InterruptIn error: pin not supported.\n");
-        return -1;
-    }
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-
-    // Configure GPIO
-    pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
-
-    // Enable EXTI interrupt
-    NVIC_SetVector(irq_n, vector);
-    NVIC_EnableIRQ(irq_n);
-
-    // Save informations for future use
-    obj->irq_n = irq_n;
-    obj->irq_index = irq_index;
-    obj->event = EDGE_NONE;
-    obj->pin = pin;
-
-    gpio_channel = &channels[irq_index];
-    gpio_idx = pin_base_nr[pin_index];
-    gpio_channel->pin_mask |= (1 << gpio_idx);
-    gpio_channel->channel_ids[gpio_idx] = id;
-    gpio_channel->channel_gpio[gpio_idx] = gpio_add;
-    gpio_channel->channel_pin[gpio_idx] = pin_index;
-
-    irq_handler = handler;
-
-    return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj)
-{
-    gpio_channel_t *gpio_channel = &channels[obj->irq_index];
-    uint32_t pin_index  = STM_PIN(obj->pin);
-    uint32_t gpio_idx = pin_base_nr[pin_index];
-
-    gpio_channel->pin_mask &= ~(1 << gpio_idx);
-    gpio_channel->channel_ids[gpio_idx] = 0;
-    gpio_channel->channel_gpio[gpio_idx] = 0;
-    gpio_channel->channel_pin[gpio_idx] = 0;
-
-    // Disable EXTI line
-    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    obj->event = EDGE_NONE;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
-{
-    uint32_t mode = STM_MODE_IT_EVT_RESET;
-    uint32_t pull = GPIO_NOPULL;
-
-    if (enable) {
-        if (event == IRQ_RISE) {
-            if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
-                mode = STM_MODE_IT_RISING_FALLING;
-                obj->event = EDGE_BOTH;
-            } else { // NONE or RISE
-                mode = STM_MODE_IT_RISING;
-                obj->event = EDGE_RISE;
-            }
-        }
-        if (event == IRQ_FALL) {
-            if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
-                mode = STM_MODE_IT_RISING_FALLING;
-                obj->event = EDGE_BOTH;
-            } else { // NONE or FALL
-                mode = STM_MODE_IT_FALLING;
-                obj->event = EDGE_FALL;
-            }
-        }
-    } else { // Disable
-        if (event == IRQ_RISE) {
-            if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
-                mode = STM_MODE_IT_FALLING;
-                obj->event = EDGE_FALL;
-            } else { // NONE or RISE
-                mode = STM_MODE_IT_EVT_RESET;
-                obj->event = EDGE_NONE;
-            }
-        }
-        if (event == IRQ_FALL) {
-            if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
-                mode = STM_MODE_IT_RISING;
-                obj->event = EDGE_RISE;
-            } else { // NONE or FALL
-                mode = STM_MODE_IT_EVT_RESET;
-                obj->event = EDGE_NONE;
-            }
-        }
-    }
-
-    pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
-}
-
-void gpio_irq_enable(gpio_irq_t *obj)
-{
-    NVIC_EnableIRQ(obj->irq_n);
-}
-
-void gpio_irq_disable(gpio_irq_t *obj)
-{
-    NVIC_DisableIRQ(obj->irq_n);
-    obj->event = EDGE_NONE;
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/gpio_object.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,76 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    if (value) {
-        *obj->reg_set = obj->mask;
-    } else {
-        *obj->reg_clr = obj->mask;
-    }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj)
-{
-    return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/i2c_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,413 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "i2c_api.h"
-
-#if DEVICE_I2C
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-/* Timeout values for flags and events waiting loops. These timeouts are
-   not based on accurate values, they just guarantee that the application will
-   not remain stuck if the I2C communication is corrupted. */
-#define FLAG_TIMEOUT ((int)0x1000)
-#define LONG_TIMEOUT ((int)0x8000)
-
-I2C_HandleTypeDef I2cHandle;
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl)
-{
-    static int i2c1_inited = 0;
-    static int i2c2_inited = 0;
-#if defined(I2C3_BASE)
-    static int i2c3_inited = 0;
-#endif
-
-    // Determine the I2C to use
-    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
-    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
-
-    obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
-    MBED_ASSERT(obj->i2c != (I2CName)NC);
-
-    // Enable I2C1 clock and pinout if not done
-    if ((obj->i2c == I2C_1) && !i2c1_inited) {
-        i2c1_inited = 1;
-        __HAL_RCC_I2C1_CONFIG(RCC_I2C1CLKSOURCE_SYSCLK);
-        __I2C1_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrain);
-        pin_mode(scl, OpenDrain);
-    }
-
-    // Enable I2C2 clock and pinout if not done
-    if ((obj->i2c == I2C_2) && !i2c2_inited) {
-        i2c2_inited = 1;
-        __I2C2_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrain);
-        pin_mode(scl, OpenDrain);
-    }
-
-#if defined(I2C3_BASE)
-    // Enable I2C3 clock and pinout if not done
-    if ((obj->i2c == I2C_3) && !i2c3_inited) {
-        i2c3_inited = 1;
-        __I2C3_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrain);
-        pin_mode(scl, OpenDrain);
-    }
-#endif
-
-    // Reset to clear pending flags if any
-    i2c_reset(obj);
-
-    // I2C configuration
-    i2c_frequency(obj, 100000); // 100 kHz per default
-}
-
-void i2c_frequency(i2c_t *obj, int hz)
-{
-    MBED_ASSERT((hz == 100000) || (hz == 400000) || (hz == 1000000));
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-
-    // wait before init
-    timeout = LONG_TIMEOUT;
-    while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
-
-    // Common settings: I2C clock = 32 MHz, Analog filter = ON, Digital filter coefficient = 0
-    switch (hz) {
-        case 100000:
-            I2cHandle.Init.Timing = 0x20602938; // Standard mode with Rise Time = 400ns and Fall Time = 100ns
-            break;
-        case 400000:
-            I2cHandle.Init.Timing = 0x00B0122A; // Fast mode with Rise Time = 250ns and Fall Time = 100ns
-            break;
-        case 1000000:
-            I2cHandle.Init.Timing = 0x0030040E; // Fast mode Plus with Rise Time = 60ns and Fall Time = 100ns
-            break;
-        default:
-            break;
-    }
-
-    // I2C configuration
-    I2cHandle.Init.AddressingMode   = I2C_ADDRESSINGMODE_7BIT;
-    I2cHandle.Init.DualAddressMode  = I2C_DUALADDRESS_DISABLED;
-    I2cHandle.Init.GeneralCallMode  = I2C_GENERALCALL_DISABLED;
-    I2cHandle.Init.NoStretchMode    = I2C_NOSTRETCH_DISABLED;
-    I2cHandle.Init.OwnAddress1      = 0;
-    I2cHandle.Init.OwnAddress2      = 0;
-    I2cHandle.Init.OwnAddress2Masks = I2C_OA2_NOMASK;
-
-    if (HAL_I2C_Init(&I2cHandle) != HAL_OK) {
-        error("Cannot initialize I2C");
-    }
-}
-
-inline int i2c_start(i2c_t *obj)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-
-    // Clear Acknowledge failure flag
-    __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
-
-    // Generate the START condition
-    i2c->CR2 |= I2C_CR2_START;
-
-    // Wait the START condition has been correctly sent
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == RESET) {
-        if ((timeout--) == 0) {
-            return 1;
-        }
-    }
-
-    return 0;
-}
-
-inline int i2c_stop(i2c_t *obj)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-
-    // Generate the STOP condition
-    i2c->CR2 |= I2C_CR2_STOP;
-
-    return 0;
-}
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-    int count;
-    int value;
-
-    /* update CR2 register */
-    i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)))
-               | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_READ);
-
-    // Read all bytes
-    for (count = 0; count < length; count++) {
-        value = i2c_byte_read(obj, 0);
-        data[count] = (char)value;
-    }
-
-    // Wait transfer complete
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) {
-        timeout--;
-        if (timeout == 0) {
-            return -1;
-        }
-    }
-
-    __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC);
-
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-        /* Wait until STOPF flag is set */
-        timeout = FLAG_TIMEOUT;
-        while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
-            timeout--;
-            if (timeout == 0) {
-                return -1;
-            }
-        }
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF);
-    }
-
-    return length;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-    int count;
-
-    /* update CR2 register */
-    i2c->CR2 = (i2c->CR2 & (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP)))
-               | (uint32_t)(((uint32_t)address & I2C_CR2_SADD) | (((uint32_t)length << 16) & I2C_CR2_NBYTES) | (uint32_t)I2C_SOFTEND_MODE | (uint32_t)I2C_GENERATE_START_WRITE);
-
-    for (count = 0; count < length; count++) {
-        i2c_byte_write(obj, data[count]);
-    }
-
-    // Wait transfer complete
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TC) == RESET) {
-        timeout--;
-        if (timeout == 0) {
-            return -1;
-        }
-    }
-
-    __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_TC);
-
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-        /* Wait until STOPF flag is set */
-        timeout = FLAG_TIMEOUT;
-        while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
-            timeout--;
-            if (timeout == 0) {
-                return -1;
-            }
-        }
-        /* Clear STOP Flag */
-        __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_STOPF);
-    }
-
-    return count;
-}
-
-int i2c_byte_read(i2c_t *obj, int last)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-
-    // Wait until the byte is received
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
-        if ((timeout--) == 0) {
-            return -1;
-        }
-    }
-
-    return (int)i2c->RXDR;
-}
-
-int i2c_byte_write(i2c_t *obj, int data)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-
-    // Wait until the previous byte is transmitted
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXIS) == RESET) {
-        if ((timeout--) == 0) {
-            return 0;
-        }
-    }
-
-    i2c->TXDR = (uint8_t)data;
-
-    return 1;
-}
-
-void i2c_reset(i2c_t *obj)
-{
-    int timeout;
-
-    // wait before reset
-    timeout = LONG_TIMEOUT;
-    while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
-
-    if (obj->i2c == I2C_1) {
-        __I2C1_FORCE_RESET();
-        __I2C1_RELEASE_RESET();
-    }
-    if (obj->i2c == I2C_2) {
-        __I2C2_FORCE_RESET();
-        __I2C2_RELEASE_RESET();
-    }
-}
-
-#if DEVICE_I2CSLAVE
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    uint16_t tmpreg;
-
-    // disable
-    i2c->OAR1 &= (uint32_t)(~I2C_OAR1_OA1EN);
-    // Get the old register value
-    tmpreg = i2c->OAR1;
-    // Reset address bits
-    tmpreg &= 0xFC00;
-    // Set new address
-    tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
-    // Store the new register value
-    i2c->OAR1 = tmpreg;
-    // enable
-    i2c->OAR1 |= I2C_OAR1_OA1EN;
-}
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave)
-{
-
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    uint16_t tmpreg;
-
-    // Get the old register value
-    tmpreg = i2c->OAR1;
-
-    // Enable / disable slave
-    if (enable_slave == 1) {
-        tmpreg |= I2C_OAR1_OA1EN;
-    } else {
-        tmpreg &= (uint32_t)(~I2C_OAR1_OA1EN);
-    }
-
-    // Set new mode
-    i2c->OAR1 = tmpreg;
-
-}
-
-// See I2CSlave.h
-#define NoData         0 // the slave has not been addressed
-#define ReadAddressed  1 // the master has requested a read from this slave (slave = transmitter)
-#define WriteGeneral   2 // the master is writing to all slave
-#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
-
-int i2c_slave_receive(i2c_t *obj)
-{
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-    int retValue = NoData;
-
-    if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) {
-        if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) {
-            if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_DIR) == 1)
-                retValue = ReadAddressed;
-            else
-                retValue = WriteAddressed;
-            __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR);
-        }
-    }
-
-    return (retValue);
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length)
-{
-    char size = 0;
-
-    while (size < length) data[size++] = (char)i2c_byte_read(obj, 0);
-
-    return size;
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length)
-{
-    char size = 0;
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-
-    do {
-        i2c_byte_write(obj, data[size]);
-        size++;
-    } while (size < length);
-
-    return size;
-}
-
-
-#endif // DEVICE_I2CSLAVE
-
-#endif // DEVICE_I2C

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/mbed_overrides.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "cmsis.h"
-
-// This function is called after RAM initialization and before main.
-void mbed_sdk_init()
-{
-    // Update the SystemCoreClock variable.
-    SystemCoreClockUpdate();
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/pinmap.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,150 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "pinmap.h"
-#include "PortNames.h"
-#include "mbed_error.h"
-
-// GPIO mode look-up table
-// Warning: order must be the same as the one defined in PinNames.h !!!
-static const uint32_t gpio_mode[13] = {
-    0x00000000, //  0 = GPIO_MODE_INPUT
-    0x00000001, //  1 = GPIO_MODE_OUTPUT_PP
-    0x00000011, //  2 = GPIO_MODE_OUTPUT_OD
-    0x00000002, //  3 = GPIO_MODE_AF_PP
-    0x00000012, //  4 = GPIO_MODE_AF_OD
-    0x00000003, //  5 = GPIO_MODE_ANALOG
-    0x10110000, //  6 = GPIO_MODE_IT_RISING
-    0x10210000, //  7 = GPIO_MODE_IT_FALLING
-    0x10310000, //  8 = GPIO_MODE_IT_RISING_FALLING
-    0x10120000, //  9 = GPIO_MODE_EVT_RISING
-    0x10220000, // 10 = GPIO_MODE_EVT_FALLING
-    0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING
-    0x10000000  // 12 = Reset IT and EVT (not in STM32Cube HAL)
-};
-
-// Enable GPIO clock and return GPIO base address
-uint32_t Set_GPIO_Clock(uint32_t port_idx)
-{
-    uint32_t gpio_add = 0;
-    switch (port_idx) {
-        case PortA:
-            gpio_add = GPIOA_BASE;
-            __GPIOA_CLK_ENABLE();
-            break;
-        case PortB:
-            gpio_add = GPIOB_BASE;
-            __GPIOB_CLK_ENABLE();
-            break;
-#if defined(GPIOC_BASE)
-        case PortC:
-            gpio_add = GPIOC_BASE;
-            __GPIOC_CLK_ENABLE();
-            break;
-#endif
-#if defined(GPIOD_BASE)
-        case PortD:
-            gpio_add = GPIOD_BASE;
-            __GPIOD_CLK_ENABLE();
-            break;
-#endif
-#if defined(GPIOH_BASE)
-        case PortH:
-            gpio_add = GPIOH_BASE;
-            __GPIOH_CLK_ENABLE();
-            break;
-#endif
-        default:
-            error("Pinmap error: wrong port number.");
-            break;
-    }
-    return gpio_add;
-}
-
-/**
- * Configure pin (mode, speed, output type and pull-up/pull-down)
- */
-void pin_function(PinName pin, int data)
-{
-    MBED_ASSERT(pin != (PinName)NC);
-    // Get the pin informations
-    uint32_t mode  = STM_PIN_MODE(data);
-    uint32_t pupd  = STM_PIN_PUPD(data);
-    uint32_t afnum = STM_PIN_AFNUM(data);
-
-    uint32_t port_index = STM_PORT(pin);
-    uint32_t pin_index  = STM_PIN(pin);
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
-    // Configure GPIO
-    GPIO_InitTypeDef GPIO_InitStructure;
-    GPIO_InitStructure.Pin       = (uint32_t)(1 << pin_index);
-    GPIO_InitStructure.Mode      = gpio_mode[mode];
-    GPIO_InitStructure.Pull      = pupd;
-    GPIO_InitStructure.Speed     = GPIO_SPEED_HIGH;
-    GPIO_InitStructure.Alternate = afnum;
-    HAL_GPIO_Init(gpio, &GPIO_InitStructure);
-
-    // [TODO] Disconnect JTAG-DP + SW-DP signals.
-    // Warning: Need to reconnect under reset
-    //if ((pin == PA_13) || (pin == PA_14)) {
-    //
-    //}
-    //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
-    //
-    //}
-}
-
-/**
- * Configure pin pull-up/pull-down
- */
-void pin_mode(PinName pin, PinMode mode)
-{
-    MBED_ASSERT(pin != (PinName)NC);
-    uint32_t port_index = STM_PORT(pin);
-    uint32_t pin_index  = STM_PIN(pin);
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
-    // Configure pull-up/pull-down resistors
-    uint32_t pupd = (uint32_t)mode;
-    if (pupd > 2)
-    {
-        pupd = 0; // Open-drain = No pull-up/No pull-down
-    }
-    gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPD0 << (pin_index * 2)));
-    gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2));
-
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/port_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-#include "mbed_error.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
-// low nibble  = pin number
-PinName port_pin(PortName port, int pin_n)
-{
-    return (PinName)(pin_n + (port << 4));
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
-{
-    uint32_t port_index = (uint32_t)port;
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
-    // Fill PORT object structure for future use
-    obj->port      = port;
-    obj->mask      = mask;
-    obj->direction = dir;
-    obj->reg_in    = &gpio->IDR;
-    obj->reg_out   = &gpio->ODR;
-
-    port_dir(obj, dir);
-}
-
-void port_dir(port_t *obj, PinDirection dir)
-{
-    uint32_t i;
-    obj->direction = dir;
-    for (i = 0; i < 16; i++) { // Process all pins
-        if (obj->mask & (1 << i)) { // If the pin is used
-            if (dir == PIN_OUTPUT) {
-                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
-            } else { // PIN_INPUT
-                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-            }
-        }
-    }
-}
-
-void port_mode(port_t *obj, PinMode mode)
-{
-    uint32_t i;
-    for (i = 0; i < 16; i++) { // Process all pins
-        if (obj->mask & (1 << i)) { // If the pin is used
-            pin_mode(port_pin(obj->port, i), mode);
-        }
-    }
-}
-
-void port_write(port_t *obj, int value)
-{
-    *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
-}
-
-int port_read(port_t *obj)
-{
-    if (obj->direction == PIN_OUTPUT) {
-        return (*obj->reg_out & obj->mask);
-    } else { // PIN_INPUT
-        return (*obj->reg_in & obj->mask);
-    }
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/pwmout_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,183 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "pwmout_api.h"
-
-#if DEVICE_PWMOUT
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-static TIM_HandleTypeDef TimHandle;
-
-void pwmout_init(pwmout_t* obj, PinName pin)
-{
-    // Get the peripheral name from the pin and assign it to the object
-    obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-    MBED_ASSERT(obj->pwm != (PWMName)NC);
-
-    // Get the pin function and assign the used channel to the object
-    uint32_t function = pinmap_function(pin, PinMap_PWM);
-    MBED_ASSERT(function != (uint32_t)NC);
-    obj->channel = STM_PIN_CHANNEL(function);
-    obj->inverted = STM_PIN_INVERTED(function);
-
-    // Enable TIM clock
-    if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE();
-#if defined(TIM3_BASE)
-    if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
-#endif
-    if (obj->pwm == PWM_21) __TIM21_CLK_ENABLE();
-    if (obj->pwm == PWM_22) __TIM22_CLK_ENABLE();
-
-    // Configure GPIO
-    pinmap_pinout(pin, PinMap_PWM);
-
-    obj->pin = pin;
-    obj->period = 0;
-    obj->pulse = 0;
-
-    pwmout_period_us(obj, 20000); // 20 ms per default
-}
-
-void pwmout_free(pwmout_t* obj)
-{
-    // Configure GPIO
-    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void pwmout_write(pwmout_t* obj, float value)
-{
-    TIM_OC_InitTypeDef sConfig;
-    int channel = 0;
-
-    TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
-
-    if (value < (float)0.0) {
-        value = 0.0;
-    } else if (value > (float)1.0) {
-        value = 1.0;
-    }
-
-    obj->pulse = (uint32_t)((float)obj->period * value);
-
-    // Configure channels
-    sConfig.OCMode       = TIM_OCMODE_PWM1;
-    sConfig.Pulse        = obj->pulse;
-    sConfig.OCPolarity   = TIM_OCPOLARITY_HIGH;
-    sConfig.OCFastMode   = TIM_OCFAST_ENABLE;
-
-    switch (obj->channel) {
-        case 1:
-            channel = TIM_CHANNEL_1;
-            break;
-        case 2:
-            channel = TIM_CHANNEL_2;
-            break;
-        case 3:
-            channel = TIM_CHANNEL_3;
-            break;
-        case 4:
-            channel = TIM_CHANNEL_4;
-            break;
-        default:
-            return;
-    }
-
-    if (HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel) != HAL_OK) {
-        error("Cannot initialize PWM");
-    }
-
-    HAL_TIM_PWM_Start(&TimHandle, channel);
-}
-
-float pwmout_read(pwmout_t* obj)
-{
-    float value = 0;
-    if (obj->period > 0) {
-        value = (float)(obj->pulse) / (float)(obj->period);
-    }
-    return ((value > (float)1.0) ? (float)(1.0) : (value));
-}
-
-void pwmout_period(pwmout_t* obj, float seconds)
-{
-    pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms)
-{
-    pwmout_period_us(obj, ms * 1000);
-}
-
-void pwmout_period_us(pwmout_t* obj, int us)
-{
-    TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
-
-    float dc = pwmout_read(obj);
-
-    __HAL_TIM_DISABLE(&TimHandle);
-
-    TimHandle.Init.Period        = us - 1;
-    TimHandle.Init.Prescaler     = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
-    TimHandle.Init.ClockDivision = 0;
-    TimHandle.Init.CounterMode   = TIM_COUNTERMODE_UP;
-
-    if (HAL_TIM_PWM_Init(&TimHandle) != HAL_OK) {
-        error("Cannot initialize PWM");
-    }
-
-    // Set duty cycle again
-    pwmout_write(obj, dc);
-
-    // Save for future use
-    obj->period = us;
-
-    __HAL_TIM_ENABLE(&TimHandle);
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds)
-{
-    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
-{
-    pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us)
-{
-    float value = (float)us / (float)obj->period;
-    pwmout_write(obj, value);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/serial_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,409 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "serial_api.h"
-
-#if DEVICE_SERIAL
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include <string.h>
-#include "PeripheralPins.h"
-
-#define UART_NUM (5)
-
-static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0};
-
-static uart_irq_handler irq_handler;
-
-UART_HandleTypeDef UartHandle;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-static void init_uart(serial_t *obj)
-{
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-
-    if (obj->uart == LPUART_1) {
-        UartHandle.Init.BaudRate = obj->baudrate >> 1;
-    } else {
-        UartHandle.Init.BaudRate = obj->baudrate;
-    }
-    UartHandle.Init.WordLength = obj->databits;
-    UartHandle.Init.StopBits   = obj->stopbits;
-    UartHandle.Init.Parity     = obj->parity;
-    UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-
-    if (obj->pin_rx == NC) {
-        UartHandle.Init.Mode = UART_MODE_TX;
-    } else if (obj->pin_tx == NC) {
-        UartHandle.Init.Mode = UART_MODE_RX;
-    } else {
-        UartHandle.Init.Mode = UART_MODE_TX_RX;
-    }
-
-    // Disable the reception overrun detection
-    UartHandle.AdvancedInit.AdvFeatureInit = UART_ADVFEATURE_RXOVERRUNDISABLE_INIT;
-    UartHandle.AdvancedInit.OverrunDisable = UART_ADVFEATURE_OVERRUN_DISABLE;
-
-    if (HAL_UART_Init(&UartHandle) != HAL_OK) {
-        error("Cannot initialize UART");
-    }
-}
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj->uart != (UARTName)NC);
-
-    // Enable UART clock
-    if (obj->uart == UART_1) {
-        __HAL_RCC_USART1_CLK_ENABLE();
-        obj->index = 0;
-    }
-
-    if (obj->uart == UART_2) {
-        __HAL_RCC_USART2_CLK_ENABLE();
-        obj->index = 1;
-    }
-
-    if (obj->uart == LPUART_1) {
-        __HAL_RCC_LPUART1_CLK_ENABLE();
-        obj->index = 2;
-    }
-
-#if defined(USART4_BASE)
-    if (obj->uart == UART_4) {
-        __HAL_RCC_USART4_CLK_ENABLE();
-        obj->index = 3;
-    }
-#endif
-
-#if defined(USART5_BASE)
-    if (obj->uart == UART_5) {
-        __HAL_RCC_USART5_CLK_ENABLE();
-        obj->index = 4;
-    }
-#endif
-
-    // Configure the UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj->baudrate = 9600;
-    obj->databits = UART_WORDLENGTH_8B;
-    obj->stopbits = UART_STOPBITS_1;
-    obj->parity   = UART_PARITY_NONE;
-    obj->pin_tx   = tx;
-    obj->pin_rx   = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    // Reset UART and disable clock
-    if (obj->uart == UART_1) {
-        __HAL_RCC_USART1_FORCE_RESET();
-        __HAL_RCC_USART1_RELEASE_RESET();
-        __HAL_RCC_USART1_CLK_DISABLE();
-    }
-
-    if (obj->uart == UART_2) {
-        __HAL_RCC_USART2_FORCE_RESET();
-        __HAL_RCC_USART2_RELEASE_RESET();
-        __HAL_RCC_USART2_CLK_DISABLE();
-    }
-
-    if (obj->uart == LPUART_1) {
-        __HAL_RCC_LPUART1_FORCE_RESET();
-        __HAL_RCC_LPUART1_RELEASE_RESET();
-        __HAL_RCC_LPUART1_CLK_DISABLE();
-    }
-
-#if defined(USART4_BASE)
-    if (obj->uart == UART_4) {
-        __HAL_RCC_USART4_FORCE_RESET();
-        __HAL_RCC_USART4_RELEASE_RESET();
-        __HAL_RCC_USART4_CLK_DISABLE();
-    }
-#endif
-
-#if defined(USART5_BASE)
-    if (obj->uart == UART_5) {
-        __HAL_RCC_USART5_FORCE_RESET();
-        __HAL_RCC_USART5_RELEASE_RESET();
-        __HAL_RCC_USART5_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    obj->baudrate = baudrate;
-    init_uart(obj);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
-{
-    if (data_bits == 9) {
-        obj->databits = UART_WORDLENGTH_9B;
-    } else {
-        obj->databits = UART_WORDLENGTH_8B;
-    }
-
-    switch (parity) {
-        case ParityOdd:
-        case ParityForced0:
-            obj->parity = UART_PARITY_ODD;
-            break;
-        case ParityEven:
-        case ParityForced1:
-            obj->parity = UART_PARITY_EVEN;
-            break;
-        default: // ParityNone
-            obj->parity = UART_PARITY_NONE;
-            break;
-    }
-
-    if (stop_bits == 2) {
-        obj->stopbits = UART_STOPBITS_2;
-    } else {
-        obj->stopbits = UART_STOPBITS_1;
-    }
-
-    init_uart(obj);
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-
-static void uart_irq(UARTName name, int id)
-{
-    UartHandle.Instance = (USART_TypeDef *)name;
-    if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
-            irq_handler(serial_irq_ids[id], TxIrq);
-            __HAL_UART_CLEAR_IT(&UartHandle, UART_CLEAR_TCF);
-        }
-        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
-            irq_handler(serial_irq_ids[id], RxIrq);
-            volatile uint32_t tmpval = UartHandle.Instance->RDR; // Clear RXNE bit
-        }
-    }
-}
-
-static void uart1_irq(void)
-{
-    uart_irq(UART_1, 0);
-}
-
-static void uart2_irq(void)
-{
-    uart_irq(UART_2, 1);
-}
-
-static void lpuart1_irq(void)
-{
-    uart_irq(LPUART_1, 2);
-}
-
-#if defined(USART4_BASE)
-static void uart4_irq(void)
-{
-    uart_irq(UART_4, 3);
-}
-#endif
-
-#if defined(USART5_BASE)
-static void uart5_irq(void)
-{
-    uart_irq(UART_5, 4);
-}
-#endif
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
-{
-    irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
-{
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-
-    if (obj->uart == UART_1) {
-        irq_n = USART1_IRQn;
-        vector = (uint32_t)&uart1_irq;
-    }
-
-    if (obj->uart == UART_2) {
-        irq_n = USART2_IRQn;
-        vector = (uint32_t)&uart2_irq;
-    }
-
-    if (obj->uart == LPUART_1) {
-        irq_n = RNG_LPUART1_IRQn;
-        vector = (uint32_t)&lpuart1_irq;
-    }
-
-#if defined(USART4_BASE)
-    if (obj->uart == UART_4) {
-        irq_n = USART4_5_IRQn;
-        vector = (uint32_t)&uart4_irq;
-    }
-#endif
-
-#if defined(USART5_BASE)
-    if (obj->uart == UART_5) {
-        irq_n = USART4_5_IRQn;
-        vector = (uint32_t)&uart5_irq;
-    }
-#endif
-
-    if (enable) {
-
-        if (irq == RxIrq) {
-            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
-        } else { // TxIrq
-            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
-        }
-
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-
-    } else { // disable
-
-        int all_disabled = 0;
-
-        if (irq == RxIrq) {
-            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
-            // Check if TxIrq is disabled too
-            if ((UartHandle.Instance->CR1 & USART_CR1_TCIE) == 0) all_disabled = 1;
-        } else { // TxIrq
-            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TC);
-            // Check if RxIrq is disabled too
-            if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
-        }
-
-        if (all_disabled) NVIC_DisableIRQ(irq_n);
-
-    }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-
-int serial_getc(serial_t *obj)
-{
-    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
-    while (!serial_readable(obj));
-    return (int)(uart->RDR & (uint32_t)0xFF);
-}
-
-void serial_putc(serial_t *obj, int c)
-{
-    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
-    while (!serial_writable(obj));
-    uart->TDR = (uint32_t)(c & (uint32_t)0xFF);
-}
-
-int serial_readable(serial_t *obj)
-{
-    int status;
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    // Check if data is received
-    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-int serial_writable(serial_t *obj)
-{
-    int status;
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    // Check if data is transmitted
-    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-void serial_clear(serial_t *obj)
-{
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    __HAL_UART_CLEAR_IT(&UartHandle, UART_CLEAR_TCF);
-    __HAL_UART_SEND_REQ(&UartHandle, UART_RXDATA_FLUSH_REQUEST);
-}
-
-void serial_pinout_tx(PinName tx)
-{
-    pinmap_pinout(tx, PinMap_UART_TX);
-}
-
-void serial_break_set(serial_t *obj)
-{
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    __HAL_UART_SEND_REQ(&UartHandle, UART_SENDBREAK_REQUEST);
-}
-
-void serial_break_clear(serial_t *obj)
-{
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/sleep.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,63 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "sleep_api.h"
-
-#if DEVICE_SLEEP
-
-#include "cmsis.h"
-
-static TIM_HandleTypeDef TimMasterHandle;
-
-void sleep(void)
-{
-    TimMasterHandle.Instance = TIM21;
-
-    // Disable HAL tick interrupt
-    __HAL_TIM_DISABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE));
-
-    // Request to enter SLEEP mode
-    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
-
-    // Enable HAL tick interrupt
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, (TIM_IT_CC2 | TIM_IT_UPDATE));
-}
-
-void deepsleep(void)
-{
-
-
-    // Request to enter STOP mode with regulator in low power mode
-    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
-
-    // After wake-up from STOP reconfigure the PLL
-    SetSysClock();
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/spi_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,268 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "spi_api.h"
-
-#if DEVICE_SPI
-
-#include <math.h>
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-static SPI_HandleTypeDef SpiHandle;
-
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    if (HAL_SPI_Init(&SpiHandle) != HAL_OK) {
-        error("Cannot initialize SPI");
-    }
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __SPI1_CLK_ENABLE();
-    }
-    if (obj->spi == SPI_2) {
-        __SPI2_CLK_ENABLE();
-    }
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __SPI1_FORCE_RESET();
-        __SPI1_RELEASE_RESET();
-        __SPI1_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_2) {
-        __SPI2_FORCE_RESET();
-        __SPI2_RELEASE_RESET();
-        __SPI2_CLK_DISABLE();
-    }
-
-    // Configure GPIO
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz)
-{
-    // Note: The frequencies are obtained with SPI1 clock = 32 MHz (APB2 clock)
-    if (hz < 250000) {
-        obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz
-    } else if ((hz >= 250000) && (hz < 500000)) {
-        obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz
-    } else if ((hz >= 500000) && (hz < 1000000)) {
-        obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz
-    } else if ((hz >= 1000000) && (hz < 2000000)) {
-        obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz
-    } else if ((hz >= 2000000) && (hz < 4000000)) {
-        obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz
-    } else if ((hz >= 4000000) && (hz < 8000000)) {
-        obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz
-    } else if ((hz >= 8000000) && (hz < 16000000)) {
-        obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz
-    } else { // >= 16000000
-        obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz
-    }
-
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return (ssp_readable(obj) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L0/us_ticker.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,113 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-// Timer selection
-#define TIM_MST TIM21
-
-static TIM_HandleTypeDef TimMasterHandle;
-static int us_ticker_inited = 0;
-
-volatile uint32_t SlaveCounter = 0;
-volatile uint32_t oc_int_part = 0;
-volatile uint16_t oc_rem_part = 0;
-
-void set_compare(uint16_t count)
-{
-    TimMasterHandle.Instance = TIM_MST;
-    // Set new output compare value
-    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, count);
-    // Enable IT
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
-}
-
-void us_ticker_init(void)
-{
-    if (us_ticker_inited) return;
-    us_ticker_inited = 1;
-
-    HAL_InitTick(0); // The passed value is not used
-}
-
-uint32_t us_ticker_read()
-{
-    uint32_t counter, counter2;
-    if (!us_ticker_inited) us_ticker_init();
-    // A situation might appear when Master overflows right after Slave is read and before the
-    // new (overflowed) value of Master is read. Which would make the code below consider the
-    // previous (incorrect) value of Slave and the new value of Master, which would return a
-    // value in the past. Avoid this by computing consecutive values of the timer until they
-    // are properly ordered.
-    counter = (uint32_t)(SlaveCounter << 16);
-    counter += TIM_MST->CNT;
-    while (1) {
-        counter2 = (uint32_t)(SlaveCounter << 16);
-        counter2 += TIM_MST->CNT;
-        if (counter2 > counter) {
-            break;
-        }
-        counter = counter2;
-    }
-    return counter2;
-}
-
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
-    int delta = (int)((uint32_t)timestamp - us_ticker_read());
-    uint16_t cval = TIM_MST->CNT;
-
-    if (delta <= 0) { // This event was in the past
-        us_ticker_irq_handler();
-    } else {
-        oc_int_part = (uint32_t)(delta >> 16);
-        oc_rem_part = (uint16_t)(delta & 0xFFFF);
-        if (oc_rem_part <= (0xFFFF - cval)) {
-            set_compare(cval + oc_rem_part);
-            oc_rem_part = 0;
-        } else {
-            set_compare(0xFFFF);
-            oc_rem_part = oc_rem_part - (0xFFFF - cval);
-        }
-    }
-}
-
-void us_ticker_disable_interrupt(void)
-{
-    TimMasterHandle.Instance = TIM_MST;
-    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
-}
-
-void us_ticker_clear_interrupt(void)
-{
-    TimMasterHandle.Instance = TIM_MST;
-    if (__HAL_TIM_GET_FLAG(&TimMasterHandle, TIM_FLAG_CC1) == SET) {
-        __HAL_TIM_CLEAR_FLAG(&TimMasterHandle, TIM_FLAG_CC1);
-    }
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/PeripheralPins.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,66 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#ifndef MBED_PERIPHERALPINS_H
-#define MBED_PERIPHERALPINS_H
-
-#include "pinmap.h"
-#include "PeripheralNames.h"
-
-//*** ADC ***
-
-extern const PinMap PinMap_ADC[];
-
-//*** DAC ***
-
-extern const PinMap PinMap_DAC[];
-
-//*** I2C ***
-
-extern const PinMap PinMap_I2C_SDA[];
-extern const PinMap PinMap_I2C_SCL[];
-
-//*** PWM ***
-
-extern const PinMap PinMap_PWM[];
-
-//*** SERIAL ***
-
-extern const PinMap PinMap_UART_TX[];
-extern const PinMap PinMap_UART_RX[];
-
-//*** SPI ***
-
-extern const PinMap PinMap_SPI_MOSI[];
-extern const PinMap PinMap_SPI_MISO[];
-extern const PinMap PinMap_SPI_SCLK[];
-extern const PinMap PinMap_SPI_SSEL[];
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,82 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
-    UART_1 = (int)USART1_BASE,
-    UART_2 = (int)USART2_BASE,
-    UART_3 = (int)USART3_BASE
-} UARTName;
-
-#define STDIO_UART_TX  PA_2
-#define STDIO_UART_RX  PA_3
-#define STDIO_UART     UART_2
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE,
-    SPI_3 = (int)SPI3_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_2  = (int)TIM2_BASE,
-    PWM_3  = (int)TIM3_BASE,
-    PWM_4  = (int)TIM4_BASE,
-    PWM_5  = (int)TIM5_BASE,
-    PWM_9  = (int)TIM9_BASE,
-    PWM_10 = (int)TIM10_BASE,
-    PWM_11 = (int)TIM11_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PeripheralPins.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,188 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
-    {PA_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN0
-    {PA_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN1
-    {PA_2,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN2
-    {PA_3,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN3
-    {PA_4,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN4
-    {PA_5,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN5
-    {PA_6,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN6
-    {PA_7,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN7
-    {PB_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN8
-    {PB_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN9
-    {PB_12, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN18
-    {PB_13, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN19
-    {PB_14, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN20
-    {PB_15, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN21
-    {PC_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN10
-    {PC_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN11
-    {PC_2,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN12
-    {PC_3,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN13
-    {PC_4,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN14
-    {PC_5,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN15
-    {NC,    NC,    0}
-};
-
-//*** DAC ***
-
-const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT1
-    {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT2 (Warning: LED1 is also on this pin)
-    {NC,   NC,    0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
-    {NC,    NC,    0}
-};
-
-//*** PWM ***
-
-// TIM5 cannot be used because already used by the us_ticker.
-const PinMap PinMap_PWM[] = {
-//  {PA_0,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH1
-    {PA_1,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH2
-//  {PA_1,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH1
-    {PA_2,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH3
-//  {PA_2,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH3
-//  {PA_2,  PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH1
-    {PA_3,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH4
-//  {PA_3,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH4
-//  {PA_3,  PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH2
-    {PA_6,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-//  {PA_6,  PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PA_7,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-//  {PA_7,  PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PB_0,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH3
-    {PB_1,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH4
-    {PB_3,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH2
-    {PB_4,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-    {PB_5,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-    {PB_6,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH1
-    {PB_7,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH2
-    {PB_8,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH3
-//  {PB_8,  PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PB_9,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH4
-//  {PB_9,  PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PB_10, PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH3
-    {PB_11, PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH4
-    {PB_12, PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PB_13, PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH1
-    {PB_14, PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH2
-    {PB_15, PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PC_6,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-    {PC_7,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-    {PC_8,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH3
-    {PC_9,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH4
-    {NC,    NC,     0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-//  {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {NC,    NC,     0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-//  {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {NC,    NC,     0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_5,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {NC,    NC,    0}
-};

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PinNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,183 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// See stm32l0xx_hal_gpio.h and stm32l0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_MODE_INPUT              (0)
-#define STM_MODE_OUTPUT_PP          (1)
-#define STM_MODE_OUTPUT_OD          (2)
-#define STM_MODE_AF_PP              (3)
-#define STM_MODE_AF_OD              (4)
-#define STM_MODE_ANALOG             (5)
-#define STM_MODE_IT_RISING          (6)
-#define STM_MODE_IT_FALLING         (7)
-#define STM_MODE_IT_RISING_FALLING  (8)
-#define STM_MODE_EVT_RISING         (9)
-#define STM_MODE_EVT_FALLING        (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET       (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble  = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_0  = 0x20,
-    PC_1  = 0x21,
-    PC_2  = 0x22,
-    PC_3  = 0x23,
-    PC_4  = 0x24,
-    PC_5  = 0x25,
-    PC_6  = 0x26,
-    PC_7  = 0x27,
-    PC_8  = 0x28,
-    PC_9  = 0x29,
-    PC_10 = 0x2A,
-    PC_11 = 0x2B,
-    PC_12 = 0x2C,
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PD_2  = 0x32,
-
-    //PH_0  = 0x70,
-    //PH_1  = 0x71,
-
-    // Arduino connector namings
-    A0          = PA_0,
-    A1          = PA_1,
-    A2          = PA_4,
-    A3          = PB_0,
-    A4          = PC_1,
-    A5          = PC_0,
-    D0          = PA_3,
-    D1          = PA_2,
-    D2          = PA_10,
-    D3          = PB_3,
-    D4          = PB_5,
-    D5          = PB_4,
-    D6          = PB_10,
-    D7          = PA_8,
-    D8          = PA_9,
-    D9          = PC_7,
-    D10         = PB_6,
-    D11         = PA_7,
-    D12         = PA_6,
-    D13         = PA_5,
-    D14         = PB_9,
-    D15         = PB_8,
-
-    // Generic signals namings
-    LED1        = PB_1,
-    LED2        = PB_7,
-    LED3        = PA_10,
-    //LED4        = PA_5,
-    //USER_BUTTON = PC_13,
-    SERIAL_TX   = PA_2,
-    SERIAL_RX   = PA_3,
-    USBTX       = PA_2,
-    USBRX       = PA_3,
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PA_7,
-    SPI_MISO    = PA_6,
-    SPI_SCK     = PA_5,
-    SPI_CS      = PB_6,
-    PWM_OUT     = PB_3,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullNone  = 0,
-    PullUp    = 1,
-    PullDown  = 2,
-    OpenDrain = 3,
-    PullDefault = PullNone
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/PortNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PortA = 0,
-    PortB = 1,
-    PortC = 2,
-    PortD = 3,
-    PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/device.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SLEEP            1
-
-//=======================================
-
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       24
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        0
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_MOTE_L152RC/objects.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
-    ADCName adc;
-    PinName pin;
-};
-
-struct dac_s {
-    DACName dac;
-    PinName pin;
-};
-
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName  pin_tx;
-    PinName  pin_rx;
-};
-
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
-struct i2c_s {
-    I2CName  i2c;
-    uint32_t slave;
-};
-
-struct pwmout_s {
-    PWMName pwm;
-    PinName pin;
-    uint32_t period;
-    uint32_t pulse;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,84 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
-    UART_1 = (int)USART1_BASE,
-    UART_2 = (int)USART2_BASE,
-    UART_3 = (int)USART3_BASE,
-    UART_4 = (int)UART4_BASE,
-    UART_5 = (int)UART5_BASE
-} UARTName;
-
-#define STDIO_UART_TX  PA_2
-#define STDIO_UART_RX  PA_3
-#define STDIO_UART     UART_2
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE,
-    SPI_3 = (int)SPI3_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_2  = (int)TIM2_BASE,
-    PWM_3  = (int)TIM3_BASE,
-    PWM_4  = (int)TIM4_BASE,
-    PWM_5  = (int)TIM5_BASE,
-    PWM_9  = (int)TIM9_BASE,
-    PWM_10 = (int)TIM10_BASE,
-    PWM_11 = (int)TIM11_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PeripheralPins.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,192 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
-    {PA_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN0
-    {PA_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN1
-    {PA_2,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN2
-    {PA_3,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN3
-    {PA_4,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN4
-    {PA_5,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN5
-    {PA_6,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN6
-    {PA_7,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN7
-    {PB_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN8
-    {PB_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN9
-    {PB_12, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN18
-    {PB_13, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN19
-    {PB_14, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN20
-    {PB_15, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN21
-    {PC_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN10
-    {PC_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN11
-    {PC_2,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN12
-    {PC_3,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN13
-    {PC_4,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN14
-    {PC_5,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN15
-    {NC,    NC,    0}
-};
-
-//*** DAC ***
-
-const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT1
-    {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT2 (Warning: LED1 is also on this pin)
-    {NC,   NC,    0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
-    {NC,    NC,    0}
-};
-
-//*** PWM ***
-
-// TIM5 cannot be used because already used by the us_ticker.
-const PinMap PinMap_PWM[] = {
-//  {PA_0,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH1
-    {PA_1,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH2
-//  {PA_1,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH1
-    {PA_2,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH3
-//  {PA_2,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH3
-//  {PA_2,  PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH1
-    {PA_3,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH4
-//  {PA_3,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH4
-//  {PA_3,  PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH2
-    {PA_6,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-//  {PA_6,  PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PA_7,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-//  {PA_7,  PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PB_0,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH3
-    {PB_1,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH4
-    {PB_3,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH2
-    {PB_4,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-    {PB_5,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-    {PB_6,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH1
-    {PB_7,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH2
-    {PB_8,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH3
-//  {PB_8,  PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PB_9,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH4
-//  {PB_9,  PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PB_10, PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH3
-    {PB_11, PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH4
-    {PB_12, PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PB_13, PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH1
-    {PB_14, PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH2
-    {PB_15, PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PC_6,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-    {PC_7,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-    {PC_8,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH3
-    {PC_9,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH4
-    {NC,    NC,     0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-//  {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
-    {NC,    NC,     0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-//  {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-    {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
-    {NC,    NC,     0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_5,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {NC,    NC,    0}
-};

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PinNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,183 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// See stm32l0xx_hal_gpio.h and stm32l0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_MODE_INPUT              (0)
-#define STM_MODE_OUTPUT_PP          (1)
-#define STM_MODE_OUTPUT_OD          (2)
-#define STM_MODE_AF_PP              (3)
-#define STM_MODE_AF_OD              (4)
-#define STM_MODE_ANALOG             (5)
-#define STM_MODE_IT_RISING          (6)
-#define STM_MODE_IT_FALLING         (7)
-#define STM_MODE_IT_RISING_FALLING  (8)
-#define STM_MODE_EVT_RISING         (9)
-#define STM_MODE_EVT_FALLING        (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET       (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble  = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_0  = 0x20,
-    PC_1  = 0x21,
-    PC_2  = 0x22,
-    PC_3  = 0x23,
-    PC_4  = 0x24,
-    PC_5  = 0x25,
-    PC_6  = 0x26,
-    PC_7  = 0x27,
-    PC_8  = 0x28,
-    PC_9  = 0x29,
-    PC_10 = 0x2A,
-    PC_11 = 0x2B,
-    PC_12 = 0x2C,
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PD_2  = 0x32,
-
-    PH_0  = 0x70,
-    PH_1  = 0x71,
-
-    // Arduino connector namings
-    A0          = PA_0,
-    A1          = PA_1,
-    A2          = PA_4,
-    A3          = PB_0,
-    A4          = PC_1,
-    A5          = PC_0,
-    D0          = PA_3,
-    D1          = PA_2,
-    D2          = PA_10,
-    D3          = PB_3,
-    D4          = PB_5,
-    D5          = PB_4,
-    D6          = PB_10,
-    D7          = PA_8,
-    D8          = PA_9,
-    D9          = PC_7,
-    D10         = PB_6,
-    D11         = PA_7,
-    D12         = PA_6,
-    D13         = PA_5,
-    D14         = PB_9,
-    D15         = PB_8,
-
-    // Generic signals namings
-    LED1        = PA_5,
-    LED2        = PA_5,
-    LED3        = PA_5,
-    LED4        = PA_5,
-    USER_BUTTON = PC_13,
-    SERIAL_TX   = PA_2,
-    SERIAL_RX   = PA_3,
-    USBTX       = PA_2,
-    USBRX       = PA_3,
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PA_7,
-    SPI_MISO    = PA_6,
-    SPI_SCK     = PA_5,
-    SPI_CS      = PB_6,
-    PWM_OUT     = PB_3,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullNone  = 0,
-    PullUp    = 1,
-    PullDown  = 2,
-    OpenDrain = 3,
-    PullDefault = PullNone
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/PortNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PortA = 0,
-    PortB = 1,
-    PortC = 2,
-    PortD = 3,
-    PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/device.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,70 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SLEEP            1
-
-//=======================================
-
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       24
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        0
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NUCLEO_L152RE/objects.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
-    ADCName adc;
-    PinName pin;
-};
-
-struct dac_s {
-    DACName dac;
-    PinName pin;
-};
-
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName  pin_tx;
-    PinName  pin_rx;
-};
-
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
-struct i2c_s {
-    I2CName  i2c;
-    uint32_t slave;
-};
-
-struct pwmout_s {
-    PWMName pwm;
-    PinName pin;
-    uint32_t period;
-    uint32_t pulse;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PeripheralNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,95 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PERIPHERALNAMES_H
-#define MBED_PERIPHERALNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    ADC_1 = (int)ADC1_BASE
-} ADCName;
-
-typedef enum {
-    DAC_1 = (int)DAC_BASE
-} DACName;
-
-typedef enum {
-    UART_1 = (int)USART1_BASE,
-    UART_2 = (int)USART2_BASE,
-    UART_3 = (int)USART3_BASE
-} UARTName;
-
-#if (MX_DEFAULT_SERIAL_PINS == 0)
-    //Use B10/B11 as default serial port
-    #define STDIO_UART_TX  PB_10
-    #define STDIO_UART_RX  PB_11
-    #define STDIO_UART     UART_3
-#elif (MX_DEFAULT_SERIAL_PINS == 1)
-    //Use A2/A3 as default serial port
-    #define STDIO_UART_TX  PA_2
-    #define STDIO_UART_RX  PA_3
-    #define STDIO_UART     UART_2
-#else
-    //Use A2/A3 as default serial port
-    #define STDIO_UART_TX  PA_2
-    #define STDIO_UART_RX  PA_3
-    #define STDIO_UART     UART_2
-#endif
-
-typedef enum {
-    SPI_1 = (int)SPI1_BASE,
-    SPI_2 = (int)SPI2_BASE,
-    SPI_3 = (int)SPI3_BASE
-} SPIName;
-
-typedef enum {
-    I2C_1 = (int)I2C1_BASE,
-    I2C_2 = (int)I2C2_BASE
-} I2CName;
-
-typedef enum {
-    PWM_2  = (int)TIM2_BASE,
-    PWM_3  = (int)TIM3_BASE,
-    PWM_4  = (int)TIM4_BASE,
-    PWM_5  = (int)TIM5_BASE,
-    PWM_9  = (int)TIM9_BASE,
-    PWM_10 = (int)TIM10_BASE,
-    PWM_11 = (int)TIM11_BASE
-} PWMName;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PeripheralPins.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,192 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-
-#include "PeripheralPins.h"
-
-// =====
-// Note: Commented lines are alternative possibilities which are not used per default.
-//       If you change them, you will have also to modify the corresponding xxx_api.c file
-//       for pwmout, analogin, analogout, ...
-// =====
-
-//*** ADC ***
-
-const PinMap PinMap_ADC[] = {
-    {PA_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN0
-    {PA_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN1
-    {PA_2,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN2
-    {PA_3,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN3
-    {PA_4,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN4
-    {PA_5,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN5
-    {PA_6,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN6
-    {PA_7,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN7
-    {PB_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN8
-    {PB_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN9
-    {PB_12, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN18
-    {PB_13, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN19
-    {PB_14, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN20
-    {PB_15, ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN21
-    {PC_0,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN10
-    {PC_1,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN11
-    {PC_2,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN12
-    {PC_3,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN13
-    {PC_4,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN14
-    {PC_5,  ADC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // ADC_IN15
-    {NC,    NC,    0}
-};
-
-//*** DAC ***
-
-const PinMap PinMap_DAC[] = {
-    {PA_4, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT1
-    {PA_5, DAC_1, STM_PIN_DATA(STM_MODE_ANALOG, GPIO_NOPULL, 0)}, // DAC_OUT2 (Warning: LED1 is also on this pin)
-    {NC,   NC,    0}
-};
-
-//*** I2C ***
-
-const PinMap PinMap_I2C_SDA[] = {
-    {PB_7,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_9,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_11, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_I2C_SCL[] = {
-    {PB_6,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_8,  I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
-    {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
-    {NC,    NC,    0}
-};
-
-//*** PWM ***
-
-// TIM5 cannot be used because already used by the us_ticker.
-const PinMap PinMap_PWM[] = {
-//  {PA_0,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH1
-    {PA_1,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH2
-//  {PA_1,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH1
-    {PA_2,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH3
-//  {PA_2,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH3
-//  {PA_2,  PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH1
-    {PA_3,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH4
-//  {PA_3,  PWM_5,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5)},  // TIM5_CH4
-//  {PA_3,  PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH2
-    {PA_6,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-//  {PA_6,  PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PA_7,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-//  {PA_7,  PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PB_0,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH3
-    {PB_1,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH4
-    {PB_3,  PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH2
-    {PB_4,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-    {PB_5,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-    {PB_6,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH1
-    {PB_7,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH2
-    {PB_8,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH3
-//  {PB_8,  PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PB_9,  PWM_4,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4)},  // TIM4_CH4
-//  {PB_9,  PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PB_10, PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH3
-    {PB_11, PWM_2,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2)},  // TIM2_CH4
-    {PB_12, PWM_10, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10)}, // TIM10_CH1
-    {PB_13, PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH1
-    {PB_14, PWM_9,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9)},  // TIM9_CH2
-    {PB_15, PWM_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11)}, // TIM11_CH1
-    {PC_6,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH1
-    {PC_7,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH2
-    {PC_8,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH3
-    {PC_9,  PWM_3,  STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3)},  // TIM3_CH4
-    {NC,    NC,     0}
-};
-
-//*** SERIAL ***
-
-const PinMap PinMap_UART_TX[] = {
-    {PA_2,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_9,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_6,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PC_10, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-//  {PC_10, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-//  {PC_12, UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
-    {NC,    NC,     0}
-};
-
-const PinMap PinMap_UART_RX[] = {
-    {PA_3,  UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
-    {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_7,  UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
-    {PB_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-    {PC_11, UART_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART3)},
-//  {PC_11, UART_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART4)},
-//  {PD_2,  UART_5, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_UART5)},
-    {NC,    NC,     0}
-};
-
-//*** SPI ***
-
-const PinMap PinMap_SPI_MOSI[] = {
-    {PA_7,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_12, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_5,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_MISO[] = {
-    {PA_6,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PA_11, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SCLK[] = {
-    {PA_5,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-    {PB_3,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PB_3,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {NC,    NC,    0}
-};
-
-const PinMap PinMap_SPI_SSEL[] = {
-    {PA_4,  SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PA_4,  SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
-//  {PA_15, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
-    {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
-    {NC,    NC,    0}
-};

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PinNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,176 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PINNAMES_H
-#define MBED_PINNAMES_H
-
-#include "cmsis.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-// See stm32l0xx_hal_gpio.h and stm32l0xx_hal_gpio_ex.h for values of MODE, PUPD and AFNUM
-#define STM_PIN_DATA(MODE, PUPD, AFNUM)  ((int)(((AFNUM) << 7) | ((PUPD) << 4) | ((MODE) << 0)))
-#define STM_PIN_MODE(X)   (((X) >> 0) & 0x0F)
-#define STM_PIN_PUPD(X)   (((X) >> 4) & 0x07)
-#define STM_PIN_AFNUM(X)  (((X) >> 7) & 0x0F)
-#define STM_MODE_INPUT              (0)
-#define STM_MODE_OUTPUT_PP          (1)
-#define STM_MODE_OUTPUT_OD          (2)
-#define STM_MODE_AF_PP              (3)
-#define STM_MODE_AF_OD              (4)
-#define STM_MODE_ANALOG             (5)
-#define STM_MODE_IT_RISING          (6)
-#define STM_MODE_IT_FALLING         (7)
-#define STM_MODE_IT_RISING_FALLING  (8)
-#define STM_MODE_EVT_RISING         (9)
-#define STM_MODE_EVT_FALLING        (10)
-#define STM_MODE_EVT_RISING_FALLING (11)
-#define STM_MODE_IT_EVT_RESET       (12)
-
-// High nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, 6=G, 7=H)
-// Low nibble  = pin number
-#define STM_PORT(X) (((uint32_t)(X) >> 4) & 0xF)
-#define STM_PIN(X)  ((uint32_t)(X) & 0xF)
-
-typedef enum {
-    PIN_INPUT,
-    PIN_OUTPUT
-} PinDirection;
-
-typedef enum {
-    PA_0  = 0x00,
-    PA_1  = 0x01,
-    PA_2  = 0x02,
-    PA_3  = 0x03,
-    PA_4  = 0x04,
-    PA_5  = 0x05,
-    PA_6  = 0x06,
-    PA_7  = 0x07,
-    PA_8  = 0x08,
-    PA_9  = 0x09,
-    PA_10 = 0x0A,
-    PA_11 = 0x0B,
-    PA_12 = 0x0C,
-    PA_13 = 0x0D,
-    PA_14 = 0x0E,
-    PA_15 = 0x0F,
-
-    PB_0  = 0x10,
-    PB_1  = 0x11,
-    PB_2  = 0x12,
-    PB_3  = 0x13,
-    PB_4  = 0x14,
-    PB_5  = 0x15,
-    PB_6  = 0x16,
-    PB_7  = 0x17,
-    PB_8  = 0x18,
-    PB_9  = 0x19,
-    PB_10 = 0x1A,
-    PB_11 = 0x1B,
-    PB_12 = 0x1C,
-    PB_13 = 0x1D,
-    PB_14 = 0x1E,
-    PB_15 = 0x1F,
-
-    PC_0  = 0x20,
-    PC_1  = 0x21,
-    PC_2  = 0x22,
-    PC_3  = 0x23,
-    PC_4  = 0x24,
-    PC_5  = 0x25,
-    PC_6  = 0x26,
-    PC_7  = 0x27,
-    PC_8  = 0x28,
-    PC_9  = 0x29,
-    PC_10 = 0x2A,
-    PC_11 = 0x2B,
-    PC_12 = 0x2C,
-    PC_13 = 0x2D,
-    PC_14 = 0x2E,
-    PC_15 = 0x2F,
-
-    PD_2  = 0x32,
-
-    PH_0  = 0x70,
-    PH_1  = 0x71,
-
-    // Generic signals namings
-    LED1        = PB_2,
-    LED2        = PB_2,
-    LED3        = PB_2,
-    LED4        = PB_2,
-    USER_BUTTON = PC_3,
-
-#if (MX_DEFAULT_SERIAL_PINS == 0)
-    //Use B10/B11 as default serial port
-    SERIAL_TX   = PB_10,
-    SERIAL_RX   = PB_11,
-    USBTX       = PB_10,
-    USBRX       = PB_11,
-#elif (MX_DEFAULT_SERIAL_PINS == 1)
-    //Use A2/A3 as default serial port
-    SERIAL_TX   = PA_2,
-    SERIAL_RX   = PA_3,
-    USBTX       = PA_2,
-    USBRX       = PA_3,
-#else
-    //Use A2/A3 as default serial port
-    SERIAL_TX   = PA_2,
-    SERIAL_RX   = PA_3,
-    USBTX       = PA_2,
-    USBRX       = PA_3,
-#endif
-
-    I2C_SCL     = PB_8,
-    I2C_SDA     = PB_9,
-    SPI_MOSI    = PB_15,
-    SPI_MISO    = PB_14,
-    SPI_SCK     = PB_13,
-    SPI_CS      = PA_1,
-    PWM_OUT     = PC_7,
-
-    // Not connected
-    NC = (int)0xFFFFFFFF
-} PinName;
-
-typedef enum {
-    PullNone  = 0,
-    PullUp    = 1,
-    PullDown  = 2,
-    OpenDrain = 3,
-    PullDefault = PullNone
-} PinMode;
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/PortNames.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_PORTNAMES_H
-#define MBED_PORTNAMES_H
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef enum {
-    PortA = 0,
-    PortB = 1,
-    PortC = 2,
-    PortD = 3,
-    PortH = 7
-} PortName;
-
-#ifdef __cplusplus
-}
-#endif
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/device.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_DEVICE_H
-#define MBED_DEVICE_H
-
-
-//MODTRONIX BEGIN - mbed Defines //////////////////////////////////////////////
-//Provide place for adding mbed defines. Alternative to adding them in IDE project properties.
-//Add project defines here, or add them to your toolchain compiler preprocessor
-
-
-//MODTRONIX END ///////////////////////////////////////////////////////////////
-
-
-#define DEVICE_PORTIN           1
-#define DEVICE_PORTOUT          1
-#define DEVICE_PORTINOUT        1
-
-#define DEVICE_INTERRUPTIN      1
-
-#define DEVICE_ANALOGIN         1
-#define DEVICE_ANALOGOUT        1
-
-#define DEVICE_SERIAL           1
-
-#define DEVICE_I2C              1
-#define DEVICE_I2CSLAVE         1
-
-#define DEVICE_SPI              1
-#define DEVICE_SPISLAVE         1
-
-#define DEVICE_RTC              1
-
-#define DEVICE_PWMOUT           1
-
-#define DEVICE_SLEEP            1
-
-//=======================================
-
-#define DEVICE_SEMIHOST         0
-#define DEVICE_LOCALFILESYSTEM  0
-#define DEVICE_ID_LENGTH       24
-
-#define DEVICE_DEBUG_AWARENESS  0
-
-#define DEVICE_STDIO_MESSAGES   1
-
-#define DEVICE_ERROR_RED        0
-
-#include "objects.h"
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/TARGET_NZ32SC151/objects.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,110 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2015, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_OBJECTS_H
-#define MBED_OBJECTS_H
-
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-struct gpio_irq_s {
-    IRQn_Type irq_n;
-    uint32_t irq_index;
-    uint32_t event;
-    PinName pin;
-};
-
-struct port_s {
-    PortName port;
-    uint32_t mask;
-    PinDirection direction;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_out;
-};
-
-struct analogin_s {
-    ADCName adc;
-    PinName pin;
-};
-
-struct dac_s {
-    DACName dac;
-    PinName pin;
-};
-
-struct serial_s {
-    UARTName uart;
-    int index; // Used by irq
-    uint32_t baudrate;
-    uint32_t databits;
-    uint32_t stopbits;
-    uint32_t parity;
-    PinName  pin_tx;
-    PinName  pin_rx;
-};
-
-struct spi_s {
-    SPIName spi;
-    uint32_t bits;
-    uint32_t cpol;
-    uint32_t cpha;
-    uint32_t mode;
-    uint32_t nss;
-    uint32_t br_presc;
-    PinName  pin_miso;
-    PinName  pin_mosi;
-    PinName  pin_sclk;
-    PinName  pin_ssel;
-};
-
-struct i2c_s {
-    I2CName  i2c;
-    uint32_t slave;
-};
-
-struct pwmout_s {
-    PWMName pwm;
-    PinName pin;
-    uint32_t period;
-    uint32_t pulse;
-};
-
-#include "gpio_object.h"
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/analogin_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,193 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogin_api.h"
-
-#if DEVICE_ANALOGIN
-
-#include "wait_api.h"
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-
-ADC_HandleTypeDef AdcHandle;
-
-int adc_inited = 0;
-
-void analogin_init(analogin_t *obj, PinName pin)
-{
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-
-    // Get the peripheral name from the pin and assign it to the object
-    obj->adc = (ADCName)pinmap_peripheral(pin, PinMap_ADC);
-
-    MBED_ASSERT(obj->adc != (ADCName)NC);
-
-    // Configure GPIO
-    pinmap_pinout(pin, PinMap_ADC);
-
-    // Save pin number for the read function
-    obj->pin = pin;
-
-    // The ADC initialization is done once
-    if (adc_inited == 0) {
-        adc_inited = 1;
-
-        // Enable the HSI (to clock the ADC)
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
-        RCC_OscInitStruct.HSIState       = RCC_HSI_ON;
-        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
-        HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-        AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
-        // Enable ADC clock
-        __ADC1_CLK_ENABLE();
-
-        // Configure ADC
-        AdcHandle.Init.ClockPrescaler        = ADC_CLOCK_ASYNC_DIV4;
-        AdcHandle.Init.Resolution            = ADC_RESOLUTION12b;
-        AdcHandle.Init.DataAlign             = ADC_DATAALIGN_RIGHT;
-        AdcHandle.Init.ScanConvMode          = DISABLE;                       // Sequencer disabled (ADC conversion on only 1 channel: channel set on rank 1)
-        AdcHandle.Init.EOCSelection          = EOC_SINGLE_CONV;               // On STM32L1xx ADC, overrun detection is enabled only if EOC selection is set to each conversion (or transfer by DMA enabled, this is not the case in this example).
-        AdcHandle.Init.LowPowerAutoWait      = ADC_AUTOWAIT_UNTIL_DATA_READ;  // Enable the dynamic low power Auto Delay: new conversion start only when the previous conversion (for regular group) or previous sequence (for injected group) has been treated by user software.
-        AdcHandle.Init.LowPowerAutoPowerOff  = ADC_AUTOPOWEROFF_IDLE_PHASE;   // Enable the auto-off mode: the ADC automatically powers-off after a conversion and automatically wakes-up when a new conversion is triggered (with startup time between trigger and start of sampling).
-        AdcHandle.Init.ChannelsBank          = ADC_CHANNELS_BANK_A;
-        AdcHandle.Init.ContinuousConvMode    = DISABLE;                       // Continuous mode disabled to have only 1 conversion at each conversion trig
-        AdcHandle.Init.NbrOfConversion       = 1;                             // Parameter discarded because sequencer is disabled
-        AdcHandle.Init.DiscontinuousConvMode = DISABLE;                       // Parameter discarded because sequencer is disabled
-        AdcHandle.Init.NbrOfDiscConversion   = 1;                             // Parameter discarded because sequencer is disabled
-        AdcHandle.Init.ExternalTrigConv      = 0;                             // Not used
-        AdcHandle.Init.ExternalTrigConvEdge  = ADC_EXTERNALTRIGCONVEDGE_NONE;
-        AdcHandle.Init.DMAContinuousRequests = DISABLE;
-        HAL_ADC_Init(&AdcHandle);
-    }
-}
-
-static inline uint16_t adc_read(analogin_t *obj)
-{
-    ADC_ChannelConfTypeDef sConfig;
-
-    AdcHandle.Instance = (ADC_TypeDef *)(obj->adc);
-
-    // Configure ADC channel
-    switch (obj->pin) {
-        case PA_0:
-            sConfig.Channel = ADC_CHANNEL_0;
-            break;
-        case PA_1:
-            sConfig.Channel = ADC_CHANNEL_1;
-            break;
-        case PA_2:
-            sConfig.Channel = ADC_CHANNEL_2;
-            break;
-        case PA_3:
-            sConfig.Channel = ADC_CHANNEL_3;
-            break;
-        case PA_4:
-            sConfig.Channel = ADC_CHANNEL_4;
-            break;
-        case PA_5:
-            sConfig.Channel = ADC_CHANNEL_5;
-            break;
-        case PA_6:
-            sConfig.Channel = ADC_CHANNEL_6;
-            break;
-        case PA_7:
-            sConfig.Channel = ADC_CHANNEL_7;
-            break;
-        case PB_0:
-            sConfig.Channel = ADC_CHANNEL_8;
-            break;
-        case PB_1:
-            sConfig.Channel = ADC_CHANNEL_9;
-            break;
-        case PC_0:
-            sConfig.Channel = ADC_CHANNEL_10;
-            break;
-        case PC_1:
-            sConfig.Channel = ADC_CHANNEL_11;
-            break;
-        case PC_2:
-            sConfig.Channel = ADC_CHANNEL_12;
-            break;
-        case PC_3:
-            sConfig.Channel = ADC_CHANNEL_13;
-            break;
-        case PC_4:
-            sConfig.Channel = ADC_CHANNEL_14;
-            break;
-        case PC_5:
-            sConfig.Channel = ADC_CHANNEL_15;
-            break;
-        case PB_12:
-            sConfig.Channel = ADC_CHANNEL_18;
-            break;
-        case PB_13:
-            sConfig.Channel = ADC_CHANNEL_19;
-            break;
-        case PB_14:
-            sConfig.Channel = ADC_CHANNEL_20;
-            break;
-        case PB_15:
-            sConfig.Channel = ADC_CHANNEL_21;
-            break;
-        default:
-            return 0;
-    }
-
-    sConfig.Rank         = ADC_REGULAR_RANK_1;
-    sConfig.SamplingTime = ADC_SAMPLETIME_16CYCLES;
-
-    HAL_ADC_ConfigChannel(&AdcHandle, &sConfig);
-
-    HAL_ADC_Start(&AdcHandle); // Start conversion
-
-    // Wait end of conversion and get value
-    if (HAL_ADC_PollForConversion(&AdcHandle, 10) == HAL_OK) {
-        return (HAL_ADC_GetValue(&AdcHandle));
-    } else {
-        return 0;
-    }
-}
-
-uint16_t analogin_read_u16(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    // 12-bit to 16-bit conversion
-    value = ((value << 4) & (uint16_t)0xFFF0) | ((value >> 8) & (uint16_t)0x000F);
-    return value;
-}
-
-float analogin_read(analogin_t *obj)
-{
-    uint16_t value = adc_read(obj);
-    return (float)value * (1.0f / (float)0xFFF); // 12 bits range
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/analogout_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,146 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "mbed_assert.h"
-#include "analogout_api.h"
-
-#if DEVICE_ANALOGOUT
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-#define DAC_RANGE (0xFFF) // 12 bits
-
-static DAC_HandleTypeDef DacHandle;
-
-// These variables are used for the "free" function
-static int pa4_used = 0;
-static int pa5_used = 0;
-
-void analogout_init(dac_t *obj, PinName pin)
-{
-    DAC_ChannelConfTypeDef sConfig;
-
-    DacHandle.Instance = DAC;
-
-    // Get the peripheral name (DAC_1, ...) from the pin and assign it to the object
-    obj->dac = (DACName)pinmap_peripheral(pin, PinMap_DAC);
-    MBED_ASSERT(obj->dac != (DACName)NC);
-
-    // Configure GPIO
-    pinmap_pinout(pin, PinMap_DAC);
-
-    // Save the channel for future use
-    obj->pin = pin;
-
-    // Enable DAC clock
-    __DAC_CLK_ENABLE();
-
-    // Configure DAC
-    sConfig.DAC_Trigger      = DAC_TRIGGER_NONE;
-    sConfig.DAC_OutputBuffer = DAC_OUTPUTBUFFER_DISABLE;
-
-    if (pin == PA_4) {
-        HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_1);
-        pa4_used = 1;
-    } else { // PA_5
-        HAL_DAC_ConfigChannel(&DacHandle, &sConfig, DAC_CHANNEL_2);
-        pa5_used = 1;
-    }
-
-    analogout_write_u16(obj, 0);
-}
-
-void analogout_free(dac_t *obj)
-{
-    // Reset DAC and disable clock
-    if (obj->pin == PA_4) pa4_used = 0;
-    if (obj->pin == PA_5) pa5_used = 0;
-    if ((pa4_used == 0) && (pa5_used == 0)) {
-        __DAC_FORCE_RESET();
-        __DAC_RELEASE_RESET();
-        __DAC_CLK_DISABLE();
-    }
-
-    // Configure GPIO
-    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-static inline void dac_write(dac_t *obj, uint16_t value)
-{
-    if (obj->pin == PA_4) {
-        HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_1, DAC_ALIGN_12B_R, value);
-        HAL_DAC_Start(&DacHandle, DAC_CHANNEL_1);
-    } else { // PA_5
-        HAL_DAC_SetValue(&DacHandle, DAC_CHANNEL_2, DAC_ALIGN_12B_R, value);
-        HAL_DAC_Start(&DacHandle, DAC_CHANNEL_2);
-    }
-}
-
-static inline int dac_read(dac_t *obj)
-{
-    if (obj->pin == PA_4) {
-        return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_1);
-    } else { // PA_5
-        return (int)HAL_DAC_GetValue(&DacHandle, DAC_CHANNEL_2);
-    }
-}
-
-void analogout_write(dac_t *obj, float value)
-{
-    if (value < 0.0f) {
-        dac_write(obj, 0); // Min value
-    } else if (value > 1.0f) {
-        dac_write(obj, (uint16_t)DAC_RANGE); // Max value
-    } else {
-        dac_write(obj, (uint16_t)(value * (float)DAC_RANGE));
-    }
-}
-
-void analogout_write_u16(dac_t *obj, uint16_t value)
-{
-    if (value > (uint16_t)DAC_RANGE) {
-        dac_write(obj, (uint16_t)DAC_RANGE); // Max value
-    } else {
-        dac_write(obj, value);
-    }
-}
-
-float analogout_read(dac_t *obj)
-{
-    uint32_t value = dac_read(obj);
-    return (float)((float)value * (1.0f / (float)DAC_RANGE));
-}
-
-uint16_t analogout_read_u16(dac_t *obj)
-{
-    return (uint16_t)dac_read(obj);
-}
-
-#endif // DEVICE_ANALOGOUT

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,77 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "gpio_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-uint32_t gpio_set(PinName pin)
-{
-    MBED_ASSERT(pin != (PinName)NC);
-
-    pin_function(pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    return (uint32_t)(1 << ((uint32_t)pin & 0xF)); // Return the pin mask
-}
-
-void gpio_init(gpio_t *obj, PinName pin)
-{
-    obj->pin = pin;
-    if (pin == (PinName)NC)
-        return;
-
-    uint32_t port_index = STM_PORT(pin);
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
-    // Fill GPIO object structure for future use
-    obj->mask    = gpio_set(pin);
-    obj->reg_in  = &gpio->IDR;
-    obj->reg_set = &gpio->BSRR;
-    obj->reg_clr = &gpio->BRR;
-}
-
-void gpio_mode(gpio_t *obj, PinMode mode)
-{
-    pin_mode(obj->pin, mode);
-}
-
-void gpio_dir(gpio_t *obj, PinDirection direction)
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    if (direction == PIN_OUTPUT) {
-        pin_function(obj->pin, STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
-    } else { // PIN_INPUT
-        pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    }
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_irq_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,332 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include <stddef.h>
-#include "cmsis.h"
-#include "gpio_irq_api.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-
-#define EDGE_NONE (0)
-#define EDGE_RISE (1)
-#define EDGE_FALL (2)
-#define EDGE_BOTH (3)
-
-// Number of EXTI irq vectors (EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5_9, EXTI10_15)
-#define CHANNEL_NUM (7)
-
-// Max pins for one line (max with EXTI10_15)
-#define MAX_PIN_LINE (6)
-
-typedef struct gpio_channel {
-    uint32_t pin_mask;                   // bitmask representing which pins are configured for receiving interrupts
-    uint32_t channel_ids[MAX_PIN_LINE];  // mbed "gpio_irq_t gpio_irq" field of instance
-    uint32_t channel_gpio[MAX_PIN_LINE]; // base address of gpio port group
-    uint32_t channel_pin[MAX_PIN_LINE];  // pin number in port group
-} gpio_channel_t;
-
-static gpio_channel_t channels[CHANNEL_NUM] = {
-    {.pin_mask = 0},
-    {.pin_mask = 0},
-    {.pin_mask = 0},
-    {.pin_mask = 0},
-    {.pin_mask = 0},
-    {.pin_mask = 0},
-    {.pin_mask = 0}
-};
-
-// Used to return the index for channels array.
-static uint32_t pin_base_nr[16] = {
-    // EXTI0
-    0, // pin 0
-    // EXTI1
-    0, // pin 1
-    // EXTI2
-    0, // pin 2
-    // EXTI3
-    0, // pin 3
-    // EXTI4
-    0, // pin 4
-    // EXTI5_9
-    0, // pin 5
-    1, // pin 6
-    2, // pin 7
-    3, // pin 8
-    4, // pin 9
-    // EXTI10_15
-    0, // pin 10
-    1, // pin 11
-    2, // pin 12
-    3, // pin 13
-    4, // pin 14
-    5  // pin 15
-};
-
-static gpio_irq_handler irq_handler;
-
-static void handle_interrupt_in(uint32_t irq_index, uint32_t max_num_pin_line)
-{
-    gpio_channel_t *gpio_channel = &channels[irq_index];
-    uint32_t gpio_idx;
-
-    for (gpio_idx = 0; gpio_idx < max_num_pin_line; gpio_idx++) {
-        uint32_t current_mask = (1 << gpio_idx);
-
-        if (gpio_channel->pin_mask & current_mask) {
-            // Retrieve the gpio and pin that generate the irq
-            GPIO_TypeDef *gpio = (GPIO_TypeDef *)(gpio_channel->channel_gpio[gpio_idx]);
-            uint32_t pin = (uint32_t)(1 << (gpio_channel->channel_pin[gpio_idx]));
-
-            // Clear interrupt flag
-            if (__HAL_GPIO_EXTI_GET_FLAG(pin) != RESET) {
-                __HAL_GPIO_EXTI_CLEAR_FLAG(pin);
-
-                if (gpio_channel->channel_ids[gpio_idx] == 0) continue;
-
-                // Check which edge has generated the irq
-                if ((gpio->IDR & pin) == 0) {
-                    irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_FALL);
-                } else  {
-                    irq_handler(gpio_channel->channel_ids[gpio_idx], IRQ_RISE);
-                }
-            }
-        }
-    }
-}
-
-// EXTI line 0
-static void gpio_irq0(void)
-{
-    handle_interrupt_in(0, 1);
-}
-
-// EXTI line 1
-static void gpio_irq1(void)
-{
-    handle_interrupt_in(1, 1);
-}
-
-// EXTI line 2
-static void gpio_irq2(void)
-{
-    handle_interrupt_in(2, 1);
-}
-
-// EXTI line 3
-static void gpio_irq3(void)
-{
-    handle_interrupt_in(3, 1);
-}
-
-// EXTI line 4
-static void gpio_irq4(void)
-{
-    handle_interrupt_in(4, 1);
-}
-
-// EXTI lines 5 to 9
-static void gpio_irq5(void)
-{
-    handle_interrupt_in(5, 5);
-}
-
-// EXTI lines 10 to 15
-static void gpio_irq6(void)
-{
-    handle_interrupt_in(6, 6);
-}
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-int gpio_irq_init(gpio_irq_t *obj, PinName pin, gpio_irq_handler handler, uint32_t id)
-{
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-    uint32_t irq_index;
-    gpio_channel_t *gpio_channel;
-    uint32_t gpio_idx;
-
-    if (pin == NC) return -1;
-
-    uint32_t port_index = STM_PORT(pin);
-    uint32_t pin_index  = STM_PIN(pin);
-
-    // Select irq number and interrupt routine
-    switch (pin_index) {
-        case 0:
-            irq_n = EXTI0_IRQn;
-            vector = (uint32_t)&gpio_irq0;
-            irq_index = 0;
-            break;
-        case 1:
-            irq_n = EXTI1_IRQn;
-            vector = (uint32_t)&gpio_irq1;
-            irq_index = 1;
-            break;
-        case 2:
-            irq_n = EXTI2_IRQn;
-            vector = (uint32_t)&gpio_irq2;
-            irq_index = 2;
-            break;
-        case 3:
-            irq_n = EXTI3_IRQn;
-            vector = (uint32_t)&gpio_irq3;
-            irq_index = 3;
-            break;
-        case 4:
-            irq_n = EXTI4_IRQn;
-            vector = (uint32_t)&gpio_irq4;
-            irq_index = 4;
-            break;
-        case 5:
-        case 6:
-        case 7:
-        case 8:
-        case 9:
-            irq_n = EXTI9_5_IRQn;
-            vector = (uint32_t)&gpio_irq5;
-            irq_index = 5;
-            break;
-        case 10:
-        case 11:
-        case 12:
-        case 13:
-        case 14:
-        case 15:
-            irq_n = EXTI15_10_IRQn;
-            vector = (uint32_t)&gpio_irq6;
-            irq_index = 6;
-            break;
-        default:
-            error("InterruptIn error: pin not supported.\n");
-            return -1;
-    }
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-
-    // Configure GPIO
-    pin_function(pin, STM_PIN_DATA(STM_MODE_IT_FALLING, GPIO_NOPULL, 0));
-
-    // Enable EXTI interrupt
-    NVIC_SetVector(irq_n, vector);
-    NVIC_EnableIRQ(irq_n);
-
-    // Save informations for future use
-    obj->irq_n = irq_n;
-    obj->irq_index = irq_index;
-    obj->event = EDGE_NONE;
-    obj->pin = pin;
-
-    gpio_channel = &channels[irq_index];
-    gpio_idx = pin_base_nr[pin_index];
-    gpio_channel->pin_mask |= (1 << gpio_idx);
-    gpio_channel->channel_ids[gpio_idx] = id;
-    gpio_channel->channel_gpio[gpio_idx] = gpio_add;
-    gpio_channel->channel_pin[gpio_idx] = pin_index;
-
-    irq_handler = handler;
-
-    return 0;
-}
-
-void gpio_irq_free(gpio_irq_t *obj)
-{
-    gpio_channel_t *gpio_channel = &channels[obj->irq_index];
-    uint32_t pin_index  = STM_PIN(obj->pin);
-    uint32_t gpio_idx = pin_base_nr[pin_index];
-
-    gpio_channel->pin_mask &= ~(1 << gpio_idx);
-    gpio_channel->channel_ids[gpio_idx] = 0;
-    gpio_channel->channel_gpio[gpio_idx] = 0;
-    gpio_channel->channel_pin[gpio_idx] = 0;
-
-    // Disable EXTI line
-    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    obj->event = EDGE_NONE;
-}
-
-void gpio_irq_set(gpio_irq_t *obj, gpio_irq_event event, uint32_t enable)
-{
-    uint32_t mode = STM_MODE_IT_EVT_RESET;
-    uint32_t pull = GPIO_NOPULL;
-
-    if (enable) {
-        if (event == IRQ_RISE) {
-            if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
-                mode = STM_MODE_IT_RISING_FALLING;
-                obj->event = EDGE_BOTH;
-            } else { // NONE or RISE
-                mode = STM_MODE_IT_RISING;
-                obj->event = EDGE_RISE;
-            }
-        }
-        if (event == IRQ_FALL) {
-            if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
-                mode = STM_MODE_IT_RISING_FALLING;
-                obj->event = EDGE_BOTH;
-            } else { // NONE or FALL
-                mode = STM_MODE_IT_FALLING;
-                obj->event = EDGE_FALL;
-            }
-        }
-    } else { // Disable
-        if (event == IRQ_RISE) {
-            if ((obj->event == EDGE_FALL) || (obj->event == EDGE_BOTH)) {
-                mode = STM_MODE_IT_FALLING;
-                obj->event = EDGE_FALL;
-            } else { // NONE or RISE
-                mode = STM_MODE_IT_EVT_RESET;
-                obj->event = EDGE_NONE;
-            }
-        }
-        if (event == IRQ_FALL) {
-            if ((obj->event == EDGE_RISE) || (obj->event == EDGE_BOTH)) {
-                mode = STM_MODE_IT_RISING;
-                obj->event = EDGE_RISE;
-            } else { // NONE or FALL
-                mode = STM_MODE_IT_EVT_RESET;
-                obj->event = EDGE_NONE;
-            }
-        }
-    }
-
-    pin_function(obj->pin, STM_PIN_DATA(mode, pull, 0));
-}
-
-void gpio_irq_enable(gpio_irq_t *obj)
-{
-    NVIC_EnableIRQ(obj->irq_n);
-}
-
-void gpio_irq_disable(gpio_irq_t *obj)
-{
-    NVIC_DisableIRQ(obj->irq_n);
-    obj->event = EDGE_NONE;
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/gpio_object.h	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,79 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#ifndef MBED_GPIO_OBJECT_H
-#define MBED_GPIO_OBJECT_H
-
-#include "mbed_assert.h"
-#include "cmsis.h"
-#include "PortNames.h"
-#include "PeripheralNames.h"
-#include "PinNames.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-typedef struct {
-    PinName  pin;
-    uint32_t mask;
-    __IO uint32_t *reg_in;
-    __IO uint32_t *reg_set;
-    __IO uint32_t *reg_clr;
-} gpio_t;
-
-static inline void gpio_write(gpio_t *obj, int value)
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    if (value) {
-        *obj->reg_set = obj->mask;
-    } else {
-#if defined(TARGET_STM32L152RC) || defined(TARGET_STM32L151RC)
-        *obj->reg_set = obj->mask << 16;
-#else
-        *obj->reg_clr = obj->mask;
-#endif
-    }
-}
-
-static inline int gpio_read(gpio_t *obj)
-{
-    MBED_ASSERT(obj->pin != (PinName)NC);
-    return ((*obj->reg_in & obj->mask) ? 1 : 0);
-}
-
-static inline int gpio_is_connected(const gpio_t *obj) {
-    return obj->pin != (PinName)NC;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/i2c_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,480 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "i2c_api.h"
-
-#if DEVICE_I2C
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-
-/* Timeout values for flags and events waiting loops. These timeouts are
-   not based on accurate values, they just guarantee that the application will
-   not remain stuck if the I2C communication is corrupted. */
-#define FLAG_TIMEOUT ((int)0x1000)
-#define LONG_TIMEOUT ((int)0x8000)
-
-I2C_HandleTypeDef I2cHandle;
-
-int i2c1_inited = 0;
-int i2c2_inited = 0;
-
-void i2c_init(i2c_t *obj, PinName sda, PinName scl)
-{
-    // Determine the I2C to use
-    I2CName i2c_sda = (I2CName)pinmap_peripheral(sda, PinMap_I2C_SDA);
-    I2CName i2c_scl = (I2CName)pinmap_peripheral(scl, PinMap_I2C_SCL);
-
-    obj->i2c = (I2CName)pinmap_merge(i2c_sda, i2c_scl);
-    MBED_ASSERT(obj->i2c != (I2CName)NC);
-
-    // Enable I2C1 clock and pinout if not done
-    if ((obj->i2c == I2C_1) && !i2c1_inited) {
-        i2c1_inited = 1;
-        __I2C1_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrain);
-        pin_mode(scl, OpenDrain);
-    }
-    // Enable I2C2 clock and pinout if not done
-    if ((obj->i2c == I2C_2) && !i2c2_inited) {
-        i2c2_inited = 1;
-        __I2C2_CLK_ENABLE();
-        // Configure I2C pins
-        pinmap_pinout(sda, PinMap_I2C_SDA);
-        pinmap_pinout(scl, PinMap_I2C_SCL);
-        pin_mode(sda, OpenDrain);
-        pin_mode(scl, OpenDrain);
-    }
-
-    // Reset to clear pending flags if any
-    i2c_reset(obj);
-
-    // I2C configuration
-    i2c_frequency(obj, 100000); // 100 kHz per default
-
-    // I2C master by default
-    obj->slave = 0;
-}
-
-void i2c_frequency(i2c_t *obj, int hz)
-{
-    MBED_ASSERT((hz != 0) && (hz <= 400000));
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-
-    // wait before init
-    timeout = LONG_TIMEOUT;
-    while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
-
-    // I2C configuration
-    I2cHandle.Init.AddressingMode  = I2C_ADDRESSINGMODE_7BIT;
-    I2cHandle.Init.ClockSpeed      = hz;
-    I2cHandle.Init.DualAddressMode = I2C_DUALADDRESS_DISABLED;
-    I2cHandle.Init.DutyCycle       = I2C_DUTYCYCLE_2;
-    I2cHandle.Init.GeneralCallMode = I2C_GENERALCALL_DISABLED;
-    I2cHandle.Init.NoStretchMode   = I2C_NOSTRETCH_DISABLED;
-    I2cHandle.Init.OwnAddress1     = 0;
-    I2cHandle.Init.OwnAddress2     = 0;
-    HAL_I2C_Init(&I2cHandle);
-    if (obj->slave) {
-        /* Enable Address Acknowledge */
-        I2cHandle.Instance->CR1 |= I2C_CR1_ACK;
-    }
-
-}
-
-inline int i2c_start(i2c_t *obj)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-
-    // Clear Acknowledge failure flag
-    __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
-
-    // Generate the START condition
-    i2c->CR1 |= I2C_CR1_START;
-
-    // Wait the START condition has been correctly sent
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) {
-        if ((timeout--) == 0) {
-            return 1;
-        }
-    }
-
-    return 0;
-}
-
-inline int i2c_stop(i2c_t *obj)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-
-    // Generate the STOP condition
-    i2c->CR1 |= I2C_CR1_STOP;
-
-    return 0;
-}
-
-int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-    int count;
-    int value;
-
-    i2c_start(obj);
-
-    // Wait until SB flag is set
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) {
-        timeout--;
-        if (timeout == 0) {
-            return -1;
-        }
-    }
-
-    i2c->DR = I2C_7BIT_ADD_READ(address);
-
-
-    // Wait address is acknowledged
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) {
-        timeout--;
-        if (timeout == 0) {
-            return -1;
-        }
-    }
-    __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle);
-
-    // Read all bytes except last one
-    for (count = 0; count < (length - 1); count++) {
-        value = i2c_byte_read(obj, 0);
-        data[count] = (char)value;
-    }
-
-    // If not repeated start, send stop.
-    // Warning: must be done BEFORE the data is read.
-    if (stop) {
-        i2c_stop(obj);
-    }
-
-    // Read the last byte
-    value = i2c_byte_read(obj, 1);
-    data[count] = (char)value;
-
-    return length;
-}
-
-int i2c_write(i2c_t *obj, int address, const char *data, int length, int stop)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-    int count;
-
-    i2c_start(obj);
-
-    // Wait until SB flag is set
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_SB) == RESET) {
-        timeout--;
-        if (timeout == 0) {
-            return -1;
-        }
-    }
-
-    i2c->DR = I2C_7BIT_ADD_WRITE(address);
-
-
-    // Wait address is acknowledged
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == RESET) {
-        timeout--;
-        if (timeout == 0) {
-            return -1;
-        }
-    }
-    __HAL_I2C_CLEAR_ADDRFLAG(&I2cHandle);
-
-    for (count = 0; count < length; count++) {
-        if (i2c_byte_write(obj, data[count]) != 1) {
-            i2c_stop(obj);
-            return -1;
-        }
-    }
-
-    // If not repeated start, send stop.
-    if (stop) {
-        i2c_stop(obj);
-    }
-
-    return count;
-}
-
-int i2c_byte_read(i2c_t *obj, int last)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-
-    if (last) {
-        // Don't acknowledge the last byte
-        i2c->CR1 &= ~I2C_CR1_ACK;
-    } else {
-        // Acknowledge the byte
-        i2c->CR1 |= I2C_CR1_ACK;
-    }
-
-    // Wait until the byte is received
-    timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
-        if ((timeout--) == 0) {
-            return -1;
-        }
-    }
-
-    return (int)i2c->DR;
-}
-
-int i2c_byte_write(i2c_t *obj, int data)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    int timeout;
-
-    i2c->DR = (uint8_t)data;
-
-    // Wait until the byte is transmitted
-    timeout = FLAG_TIMEOUT;
-    while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) &&
-            (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == RESET)) {
-        if ((timeout--) == 0) {
-            return 0;
-        }
-    }
-
-    return 1;
-}
-
-void i2c_reset(i2c_t *obj)
-{
-    int timeout;
-
-    // wait before reset
-    timeout = LONG_TIMEOUT;
-    while ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY)) && (timeout-- != 0));
-
-    if (obj->i2c == I2C_1) {
-        __I2C1_FORCE_RESET();
-        __I2C1_RELEASE_RESET();
-    }
-    if (obj->i2c == I2C_2) {
-        __I2C2_FORCE_RESET();
-        __I2C2_RELEASE_RESET();
-    }
-}
-
-#if DEVICE_I2CSLAVE
-
-void i2c_slave_address(i2c_t *obj, int idx, uint32_t address, uint32_t mask)
-{
-    I2C_TypeDef *i2c = (I2C_TypeDef *)(obj->i2c);
-    uint16_t tmpreg = 0;
-
-    // Get the old register value
-    tmpreg = i2c->OAR1;
-    // Reset address bits
-    tmpreg &= 0xFC00;
-    // Set new address
-    tmpreg |= (uint16_t)((uint16_t)address & (uint16_t)0x00FE); // 7-bits
-    // Store the new register value
-    i2c->OAR1 = tmpreg;
-}
-
-void i2c_slave_mode(i2c_t *obj, int enable_slave)
-{
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-    if (enable_slave) {
-        obj->slave = 1;
-        /* Enable Address Acknowledge */
-        I2cHandle.Instance->CR1 |= I2C_CR1_ACK;
-    }
-}
-
-// See I2CSlave.h
-#define NoData         0 // the slave has not been addressed
-#define ReadAddressed  1 // the master has requested a read from this slave (slave = transmitter)
-#define WriteGeneral   2 // the master is writing to all slave
-#define WriteAddressed 3 // the master is writing to this slave (slave = receiver)
-
-int i2c_slave_receive(i2c_t *obj)
-{
-    int retValue = NoData;
-
-    if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == 1) {
-        if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_ADDR) == 1) {
-            if (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TRA) == 1)
-                retValue = ReadAddressed;
-            else
-                retValue = WriteAddressed;
-
-            __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_ADDR);
-        }
-    }
-
-    return (retValue);
-}
-
-int i2c_slave_read(i2c_t *obj, char *data, int length)
-{
-    uint32_t Timeout;
-    int size = 0;
-
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-
-    while (length > 0) {
-        /* Wait until RXNE flag is set */
-        // Wait until the byte is received
-        Timeout = FLAG_TIMEOUT;
-        while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_RXNE) == RESET) {
-            Timeout--;
-            if (Timeout == 0) {
-                return -1;
-            }
-        }
-
-        /* Read data from DR */
-        (*data++) = I2cHandle.Instance->DR;
-        length--;
-        size++;
-
-        if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) {
-            /* Read data from DR */
-            (*data++) = I2cHandle.Instance->DR;
-            length--;
-            size++;
-        }
-    }
-
-    /* Wait until STOP flag is set */
-    Timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_STOPF) == RESET) {
-        Timeout--;
-        if (Timeout == 0) {
-            return -1;
-        }
-    }
-
-    /* Clear STOP flag */
-    __HAL_I2C_CLEAR_STOPFLAG(&I2cHandle);
-
-    /* Wait until BUSY flag is reset */
-    Timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) {
-        Timeout--;
-        if (Timeout == 0) {
-            return -1;
-        }
-    }
-
-    return size;
-}
-
-int i2c_slave_write(i2c_t *obj, const char *data, int length)
-{
-    uint32_t Timeout;
-    int size = 0;
-
-    I2cHandle.Instance = (I2C_TypeDef *)(obj->i2c);
-
-    while (length > 0) {
-        /* Wait until TXE flag is set */
-        Timeout = FLAG_TIMEOUT;
-        while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_TXE) == RESET) {
-            Timeout--;
-            if (Timeout == 0) {
-                return -1;
-            }
-        }
-
-
-        /* Write data to DR */
-        I2cHandle.Instance->DR = (*data++);
-        length--;
-        size++;
-
-        if ((__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BTF) == SET) && (length != 0)) {
-            /* Write data to DR */
-            I2cHandle.Instance->DR = (*data++);
-            length--;
-            size++;
-        }
-    }
-
-    /* Wait until AF flag is set */
-    Timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_AF) == RESET) {
-        Timeout--;
-        if (Timeout == 0) {
-            return -1;
-        }
-    }
-
-
-    /* Clear AF flag */
-    __HAL_I2C_CLEAR_FLAG(&I2cHandle, I2C_FLAG_AF);
-
-
-    /* Wait until BUSY flag is reset */
-    Timeout = FLAG_TIMEOUT;
-    while (__HAL_I2C_GET_FLAG(&I2cHandle, I2C_FLAG_BUSY) == SET) {
-        Timeout--;
-        if (Timeout == 0) {
-            return -1;
-        }
-    }
-
-    I2cHandle.State = HAL_I2C_STATE_READY;
-
-    /* Process Unlocked */
-    __HAL_UNLOCK(&I2cHandle);
-
-    return size;
-}
-
-
-#endif // DEVICE_I2CSLAVE
-
-#endif // DEVICE_I2C

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/mbed_overrides.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,35 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "cmsis.h"
-
-// This function is called after RAM initialization and before main.
-void mbed_sdk_init()
-{
-    // Update the SystemCoreClock variable.
-    SystemCoreClockUpdate();
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/pinmap.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,143 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "pinmap.h"
-#include "PortNames.h"
-#include "mbed_error.h"
-
-// GPIO mode look-up table
-static const uint32_t gpio_mode[13] = {
-    0x00000000, //  0 = GPIO_MODE_INPUT
-    0x00000001, //  1 = GPIO_MODE_OUTPUT_PP
-    0x00000011, //  2 = GPIO_MODE_OUTPUT_OD
-    0x00000002, //  3 = GPIO_MODE_AF_PP
-    0x00000012, //  4 = GPIO_MODE_AF_OD
-    0x00000003, //  5 = GPIO_MODE_ANALOG
-    0x10110000, //  6 = GPIO_MODE_IT_RISING
-    0x10210000, //  7 = GPIO_MODE_IT_FALLING
-    0x10310000, //  8 = GPIO_MODE_IT_RISING_FALLING
-    0x10120000, //  9 = GPIO_MODE_EVT_RISING
-    0x10220000, // 10 = GPIO_MODE_EVT_FALLING
-    0x10320000, // 11 = GPIO_MODE_EVT_RISING_FALLING
-    0x10000000  // 12 = Reset IT and EVT (not in STM32Cube HAL)
-};
-
-// Enable GPIO clock and return GPIO base address
-uint32_t Set_GPIO_Clock(uint32_t port_idx)
-{
-    uint32_t gpio_add = 0;
-    switch (port_idx) {
-        case PortA:
-            gpio_add = GPIOA_BASE;
-            __GPIOA_CLK_ENABLE();
-            break;
-        case PortB:
-            gpio_add = GPIOB_BASE;
-            __GPIOB_CLK_ENABLE();
-            break;
-        case PortC:
-            gpio_add = GPIOC_BASE;
-            __GPIOC_CLK_ENABLE();
-            break;
-        case PortD:
-            gpio_add = GPIOD_BASE;
-            __GPIOD_CLK_ENABLE();
-            break;
-        case PortH:
-            gpio_add = GPIOH_BASE;
-            __GPIOH_CLK_ENABLE();
-            break;
-        default:
-            error("Pinmap error: wrong port number.");
-            break;
-    }
-    return gpio_add;
-}
-
-/**
- * Configure pin (mode, speed, output type and pull-up/pull-down)
- */
-void pin_function(PinName pin, int data)
-{
-    MBED_ASSERT(pin != (PinName)NC);
-    // Get the pin informations
-    uint32_t mode  = STM_PIN_MODE(data);
-    uint32_t pupd  = STM_PIN_PUPD(data);
-    uint32_t afnum = STM_PIN_AFNUM(data);
-
-    uint32_t port_index = STM_PORT(pin);
-    uint32_t pin_index  = STM_PIN(pin);
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
-    // Configure GPIO
-    GPIO_InitTypeDef GPIO_InitStructure;
-    GPIO_InitStructure.Pin       = (uint32_t)(1 << pin_index);
-    GPIO_InitStructure.Mode      = gpio_mode[mode];
-    GPIO_InitStructure.Pull      = pupd;
-    GPIO_InitStructure.Speed     = GPIO_SPEED_HIGH;
-    GPIO_InitStructure.Alternate = afnum;
-    HAL_GPIO_Init(gpio, &GPIO_InitStructure);
-
-    // [TODO] Disconnect JTAG-DP + SW-DP signals.
-    // Warning: Need to reconnect under reset
-    //if ((pin == PA_13) || (pin == PA_14)) {
-    //
-    //}
-    //if ((pin == PA_15) || (pin == PB_3) || (pin == PB_4)) {
-    //
-    //}
-}
-
-/**
- * Configure pin pull-up/pull-down
- */
-void pin_mode(PinName pin, PinMode mode)
-{
-    MBED_ASSERT(pin != (PinName)NC);
-    uint32_t port_index = STM_PORT(pin);
-    uint32_t pin_index  = STM_PIN(pin);
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
-    // Configure pull-up/pull-down resistors
-    uint32_t pupd = (uint32_t)mode;
-    if (pupd > 2)
-    {
-        pupd = 0; // Open-drain = No pull-up/No pull-down
-    }
-    gpio->PUPDR &= (uint32_t)(~(GPIO_PUPDR_PUPDR0 << (pin_index * 2)));
-    gpio->PUPDR |= (uint32_t)(pupd << (pin_index * 2));
-
-}

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/port_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,103 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "port_api.h"
-#include "pinmap.h"
-#include "gpio_api.h"
-#include "mbed_error.h"
-
-#if DEVICE_PORTIN || DEVICE_PORTOUT
-
-extern uint32_t Set_GPIO_Clock(uint32_t port_idx);
-
-// high nibble = port number (0=A, 1=B, 2=C, 3=D, 4=E, 5=F, ...)
-// low nibble  = pin number
-PinName port_pin(PortName port, int pin_n)
-{
-    return (PinName)(pin_n + (port << 4));
-}
-
-void port_init(port_t *obj, PortName port, int mask, PinDirection dir)
-{
-    uint32_t port_index = (uint32_t)port;
-
-    // Enable GPIO clock
-    uint32_t gpio_add = Set_GPIO_Clock(port_index);
-    GPIO_TypeDef *gpio = (GPIO_TypeDef *)gpio_add;
-
-    // Fill PORT object structure for future use
-    obj->port      = port;
-    obj->mask      = mask;
-    obj->direction = dir;
-    obj->reg_in    = &gpio->IDR;
-    obj->reg_out   = &gpio->ODR;
-
-    port_dir(obj, dir);
-}
-
-void port_dir(port_t *obj, PinDirection dir)
-{
-    uint32_t i;
-    obj->direction = dir;
-    for (i = 0; i < 16; i++) { // Process all pins
-        if (obj->mask & (1 << i)) { // If the pin is used
-            if (dir == PIN_OUTPUT) {
-                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_OUTPUT_PP, GPIO_NOPULL, 0));
-            } else { // PIN_INPUT
-                pin_function(port_pin(obj->port, i), STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-            }
-        }
-    }
-}
-
-void port_mode(port_t *obj, PinMode mode)
-{
-    uint32_t i;
-    for (i = 0; i < 16; i++) { // Process all pins
-        if (obj->mask & (1 << i)) { // If the pin is used
-            pin_mode(port_pin(obj->port, i), mode);
-        }
-    }
-}
-
-void port_write(port_t *obj, int value)
-{
-    *obj->reg_out = (*obj->reg_out & ~obj->mask) | (value & obj->mask);
-}
-
-int port_read(port_t *obj)
-{
-    if (obj->direction == PIN_OUTPUT) {
-        return (*obj->reg_out & obj->mask);
-    } else { // PIN_INPUT
-        return (*obj->reg_in & obj->mask);
-    }
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/pwmout_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,201 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "pwmout_api.h"
-
-#if DEVICE_PWMOUT
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include "mbed_error.h"
-#include "PeripheralPins.h"
-
-static TIM_HandleTypeDef TimHandle;
-
-void pwmout_init(pwmout_t* obj, PinName pin)
-{
-    // Get the peripheral name from the pin and assign it to the object
-    obj->pwm = (PWMName)pinmap_peripheral(pin, PinMap_PWM);
-
-    if (obj->pwm == (PWMName)NC) {
-        error("PWM error: pinout mapping failed.");
-    }
-
-    // Enable TIM clock
-    if (obj->pwm == PWM_2) __TIM2_CLK_ENABLE();
-    if (obj->pwm == PWM_3) __TIM3_CLK_ENABLE();
-    if (obj->pwm == PWM_4) __TIM4_CLK_ENABLE();
-    if (obj->pwm == PWM_5) __TIM5_CLK_ENABLE();
-    if (obj->pwm == PWM_9) __TIM9_CLK_ENABLE();
-    if (obj->pwm == PWM_10) __TIM10_CLK_ENABLE();
-    if (obj->pwm == PWM_11) __TIM11_CLK_ENABLE();
-
-    // Configure GPIO
-    pinmap_pinout(pin, PinMap_PWM);
-
-    obj->pin = pin;
-    obj->period = 0;
-    obj->pulse = 0;
-
-    pwmout_period_us(obj, 20000); // 20 ms per default
-}
-
-void pwmout_free(pwmout_t* obj)
-{
-    // Configure GPIO
-    pin_function(obj->pin, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void pwmout_write(pwmout_t* obj, float value)
-{
-    TIM_OC_InitTypeDef sConfig;
-    int channel = 0;
-
-    TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
-
-    if (value < (float)0.0) {
-        value = 0.0;
-    } else if (value > (float)1.0) {
-        value = 1.0;
-    }
-
-    obj->pulse = (uint32_t)((float)obj->period * value);
-
-    // Configure channels
-    sConfig.OCMode       = TIM_OCMODE_PWM1;
-    sConfig.Pulse        = obj->pulse;
-    sConfig.OCPolarity   = TIM_OCPOLARITY_HIGH;
-    sConfig.OCFastMode   = TIM_OCFAST_ENABLE;
-
-    switch (obj->pin) {
-        // Channels 1
-        case PA_6:
-        case PB_4:
-        case PB_6:
-        case PB_12:
-        case PB_13:
-        case PB_15:
-        case PC_6:
-            channel = TIM_CHANNEL_1;
-            break;
-        // Channels 2
-        case PA_1:
-        case PA_7:
-        case PB_3:
-        case PB_5:
-        case PB_7:
-        case PB_14:
-        case PC_7:
-            channel = TIM_CHANNEL_2;
-            break;
-        // Channels 3
-        case PA_2:
-        case PB_0:
-        case PB_8:
-        case PB_10:
-        case PC_8:
-            channel = TIM_CHANNEL_3;
-            break;
-        // Channels 4
-        case PA_3:
-        case PB_1:
-        case PB_9:
-        case PB_11:
-        case PC_9:
-            channel = TIM_CHANNEL_4;
-            break;
-        default:
-            return;
-    }
-
-    HAL_TIM_PWM_ConfigChannel(&TimHandle, &sConfig, channel);
-    HAL_TIM_PWM_Start(&TimHandle, channel);
-}
-
-float pwmout_read(pwmout_t* obj)
-{
-    float value = 0;
-    if (obj->period > 0) {
-        value = (float)(obj->pulse) / (float)(obj->period);
-    }
-    return ((value > (float)1.0) ? (float)(1.0) : (value));
-}
-
-void pwmout_period(pwmout_t* obj, float seconds)
-{
-    pwmout_period_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_period_ms(pwmout_t* obj, int ms)
-{
-    pwmout_period_us(obj, ms * 1000);
-}
-
-void pwmout_period_us(pwmout_t* obj, int us)
-{
-    TimHandle.Instance = (TIM_TypeDef *)(obj->pwm);
-
-    float dc = pwmout_read(obj);
-
-    __HAL_TIM_DISABLE(&TimHandle);
-
-    SystemCoreClockUpdate();
-
-    TimHandle.Init.Period        = us - 1;
-    TimHandle.Init.Prescaler     = (uint16_t)(SystemCoreClock / 1000000) - 1; // 1 us tick
-    TimHandle.Init.ClockDivision = 0;
-    TimHandle.Init.CounterMode   = TIM_COUNTERMODE_UP;
-    HAL_TIM_PWM_Init(&TimHandle);
-
-    // Set duty cycle again
-    pwmout_write(obj, dc);
-
-    // Save for future use
-    obj->period = us;
-
-    __HAL_TIM_ENABLE(&TimHandle);
-}
-
-void pwmout_pulsewidth(pwmout_t* obj, float seconds)
-{
-    pwmout_pulsewidth_us(obj, seconds * 1000000.0f);
-}
-
-void pwmout_pulsewidth_ms(pwmout_t* obj, int ms)
-{
-    pwmout_pulsewidth_us(obj, ms * 1000);
-}
-
-void pwmout_pulsewidth_us(pwmout_t* obj, int us)
-{
-    float value = (float)us / (float)obj->period;
-    pwmout_write(obj, value);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/rtc_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,209 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "rtc_api.h"
-
-#if DEVICE_RTC
-
-#include "mbed_error.h"
-
-static int rtc_inited = 0;
-
-RTC_HandleTypeDef RtcHandle;
-
-void rtc_init(void)
-{
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    uint32_t rtc_freq = 0;
-
-    if (rtc_inited) return;
-    rtc_inited = 1;
-
-    RtcHandle.Instance = RTC;
-
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
-    // Enable LSE Oscillator
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-    RCC_OscInitStruct.LSEState       = RCC_LSE_ON; // External 32.768 kHz clock on OSC_IN/OSC_OUT
-    if (HAL_RCC_OscConfig(&RCC_OscInitStruct) == HAL_OK) {
-        // Connect LSE to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSE);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSE);
-        rtc_freq = LSE_VALUE;
-    } else {
-        // Enable LSI clock
-        RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-        RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE; // Mandatory, otherwise the PLL is reconfigured!
-        RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-        RCC_OscInitStruct.LSIState       = RCC_LSI_ON;
-        if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
-            error("RTC error: LSI clock initialization failed.");
-        }
-        // Connect LSI to RTC
-        __HAL_RCC_RTC_CLKPRESCALER(RCC_RTCCLKSOURCE_LSI);
-        __HAL_RCC_RTC_CONFIG(RCC_RTCCLKSOURCE_LSI);
-        // This value is LSI typical value. To be measured precisely using a timer input capture for example.
-        rtc_freq = 40000;
-    }
-
-    // Enable RTC
-    __HAL_RCC_RTC_ENABLE();
-
-    RtcHandle.Init.HourFormat     = RTC_HOURFORMAT_24;
-#ifdef TARGET_MOTE_L152RC
-    /* SubSecond resolution of 16384Hz */
-    RtcHandle.Init.AsynchPrediv   = 1;
-    RtcHandle.Init.SynchPrediv    = (rtc_freq / 2) - 1;
-#else
-    RtcHandle.Init.AsynchPrediv   = 127;
-    RtcHandle.Init.SynchPrediv    = (rtc_freq / 128) - 1;
-#endif
-    RtcHandle.Init.OutPut         = RTC_OUTPUT_DISABLE;
-    RtcHandle.Init.OutPutPolarity = RTC_OUTPUT_POLARITY_HIGH;
-    RtcHandle.Init.OutPutType     = RTC_OUTPUT_TYPE_OPENDRAIN;
-
-    if (HAL_RTC_Init(&RtcHandle) != HAL_OK) {
-        error("RTC error: RTC initialization failed.");
-    }
-}
-
-void rtc_free(void)
-{
-    // Enable Power clock
-    __PWR_CLK_ENABLE();
-
-    // Enable access to Backup domain
-    HAL_PWR_EnableBkUpAccess();
-
-    // Reset Backup domain
-    __HAL_RCC_BACKUPRESET_FORCE();
-    __HAL_RCC_BACKUPRESET_RELEASE();
-
-    // Disable access to Backup domain
-    HAL_PWR_DisableBkUpAccess();
-
-    // Disable LSI and LSE clocks
-    RCC_OscInitTypeDef RCC_OscInitStruct;
-    RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
-    RCC_OscInitStruct.PLL.PLLState   = RCC_PLL_NONE;
-    RCC_OscInitStruct.LSIState       = RCC_LSI_OFF;
-    RCC_OscInitStruct.LSEState       = RCC_LSE_OFF;
-    HAL_RCC_OscConfig(&RCC_OscInitStruct);
-
-    rtc_inited = 0;
-}
-
-int rtc_isenabled(void)
-{
-    return rtc_inited;
-}
-
-/*
- RTC Registers
-   RTC_WeekDay 1=monday, 2=tuesday, ..., 7=sunday
-   RTC_Month   1=january, 2=february, ..., 12=december
-   RTC_Date    day of the month 1-31
-   RTC_Year    year 0-99
- struct tm
-   tm_sec      seconds after the minute 0-61
-   tm_min      minutes after the hour 0-59
-   tm_hour     hours since midnight 0-23
-   tm_mday     day of the month 1-31
-   tm_mon      months since January 0-11
-   tm_year     years since 1900
-   tm_wday     days since Sunday 0-6
-   tm_yday     days since January 1 0-365
-   tm_isdst    Daylight Saving Time flag
-*/
-time_t rtc_read(void)
-{
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
-    struct tm timeinfo;
-
-    RtcHandle.Instance = RTC;
-
-    // Read actual date and time
-    // Warning: the time must be read first!
-    HAL_RTC_GetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
-    HAL_RTC_GetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
-
-    // Setup a tm structure based on the RTC
-    timeinfo.tm_wday = dateStruct.WeekDay;
-    timeinfo.tm_mon  = dateStruct.Month - 1;
-    timeinfo.tm_mday = dateStruct.Date;
-    timeinfo.tm_year = dateStruct.Year + 100;
-    timeinfo.tm_hour = timeStruct.Hours;
-    timeinfo.tm_min  = timeStruct.Minutes;
-    timeinfo.tm_sec  = timeStruct.Seconds;
-
-    // Convert to timestamp
-    time_t t = mktime(&timeinfo);
-
-    return t;
-}
-
-void rtc_write(time_t t)
-{
-    RTC_DateTypeDef dateStruct;
-    RTC_TimeTypeDef timeStruct;
-
-    RtcHandle.Instance = RTC;
-
-    // Convert the time into a tm
-    struct tm *timeinfo = localtime(&t);
-
-    // Fill RTC structures
-    dateStruct.WeekDay        = timeinfo->tm_wday;
-    dateStruct.Month          = timeinfo->tm_mon + 1;
-    dateStruct.Date           = timeinfo->tm_mday;
-    dateStruct.Year           = timeinfo->tm_year - 100;
-    timeStruct.Hours          = timeinfo->tm_hour;
-    timeStruct.Minutes        = timeinfo->tm_min;
-    timeStruct.Seconds        = timeinfo->tm_sec;
-    timeStruct.TimeFormat     = RTC_HOURFORMAT12_PM;
-    timeStruct.DayLightSaving = RTC_DAYLIGHTSAVING_NONE;
-    timeStruct.StoreOperation = RTC_STOREOPERATION_RESET;
-
-    // Change the RTC current date/time
-    HAL_RTC_SetDate(&RtcHandle, &dateStruct, FORMAT_BIN);
-    HAL_RTC_SetTime(&RtcHandle, &timeStruct, FORMAT_BIN);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/serial_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,396 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "serial_api.h"
-
-#if DEVICE_SERIAL
-
-#include "cmsis.h"
-#include "pinmap.h"
-#include <string.h>
-#include "PeripheralPins.h"
-
-#define UART_NUM (5)
-
-static uint32_t serial_irq_ids[UART_NUM] = {0, 0, 0, 0, 0};
-
-static uart_irq_handler irq_handler;
-
-UART_HandleTypeDef UartHandle;
-
-int stdio_uart_inited = 0;
-serial_t stdio_uart;
-
-static void init_uart(serial_t *obj)
-{
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-
-    UartHandle.Init.BaudRate   = obj->baudrate;
-    UartHandle.Init.WordLength = obj->databits;
-    UartHandle.Init.StopBits   = obj->stopbits;
-    UartHandle.Init.Parity     = obj->parity;
-    UartHandle.Init.HwFlowCtl  = UART_HWCONTROL_NONE;
-
-    if (obj->pin_rx == NC) {
-        UartHandle.Init.Mode = UART_MODE_TX;
-    } else if (obj->pin_tx == NC) {
-        UartHandle.Init.Mode = UART_MODE_RX;
-    } else {
-        UartHandle.Init.Mode = UART_MODE_TX_RX;
-    }
-
-    HAL_UART_Init(&UartHandle);
-}
-
-void serial_init(serial_t *obj, PinName tx, PinName rx)
-{
-    // Determine the UART to use (UART_1, UART_2, ...)
-    UARTName uart_tx = (UARTName)pinmap_peripheral(tx, PinMap_UART_TX);
-    UARTName uart_rx = (UARTName)pinmap_peripheral(rx, PinMap_UART_RX);
-
-    // Get the peripheral name (UART_1, UART_2, ...) from the pin and assign it to the object
-    obj->uart = (UARTName)pinmap_merge(uart_tx, uart_rx);
-    MBED_ASSERT(obj->uart != (UARTName)NC);
-
-    // Enable UART clock
-    if (obj->uart == UART_1) {
-        __USART1_CLK_ENABLE();
-        obj->index = 0;
-    }
-
-    if (obj->uart == UART_2) {
-        __USART2_CLK_ENABLE();
-        obj->index = 1;
-    }
-
-    if (obj->uart == UART_3) {
-        __USART3_CLK_ENABLE();
-        obj->index = 2;
-    }
-
-#if defined(USART4_BASE)
-    if (obj->uart == UART_4) {
-        __UART4_CLK_ENABLE();
-        obj->index = 3;
-    }
-#endif
-#if defined(USART5_BASE)
-    if (obj->uart == UART_5) {
-        __UART5_CLK_ENABLE();
-        obj->index = 4;
-    }
-#endif
-
-    // Configure the UART pins
-    pinmap_pinout(tx, PinMap_UART_TX);
-    pinmap_pinout(rx, PinMap_UART_RX);
-    if (tx != NC) {
-        pin_mode(tx, PullUp);
-    }
-    if (rx != NC) {
-        pin_mode(rx, PullUp);
-    }
-
-    // Configure UART
-    obj->baudrate = 9600;
-    obj->databits = UART_WORDLENGTH_8B;
-    obj->stopbits = UART_STOPBITS_1;
-    obj->parity   = UART_PARITY_NONE;
-    obj->pin_tx   = tx;
-    obj->pin_rx   = rx;
-
-    init_uart(obj);
-
-    // For stdio management
-    if (obj->uart == STDIO_UART) {
-        stdio_uart_inited = 1;
-        memcpy(&stdio_uart, obj, sizeof(serial_t));
-    }
-}
-
-void serial_free(serial_t *obj)
-{
-    // Reset UART and disable clock
-    if (obj->uart == UART_1) {
-        __USART1_FORCE_RESET();
-        __USART1_RELEASE_RESET();
-        __USART1_CLK_DISABLE();
-    }
-
-    if (obj->uart == UART_2) {
-        __USART2_FORCE_RESET();
-        __USART2_RELEASE_RESET();
-        __USART2_CLK_DISABLE();
-    }
-
-    if (obj->uart == UART_3) {
-        __USART3_FORCE_RESET();
-        __USART3_RELEASE_RESET();
-        __USART3_CLK_DISABLE();
-    }
-
-#if defined(USART4_BASE)
-    if (obj->uart == UART_4) {
-        __UART4_FORCE_RESET();
-        __UART4_RELEASE_RESET();
-        __UART4_CLK_DISABLE();
-    }
-#endif
-#if defined(USART5_BASE)
-    if (obj->uart == UART_5) {
-        __UART5_FORCE_RESET();
-        __UART5_RELEASE_RESET();
-        __UART5_CLK_DISABLE();
-    }
-#endif
-
-    // Configure GPIOs
-    pin_function(obj->pin_tx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_rx, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-
-    serial_irq_ids[obj->index] = 0;
-}
-
-void serial_baud(serial_t *obj, int baudrate)
-{
-    obj->baudrate = baudrate;
-    init_uart(obj);
-}
-
-void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
-{
-    if (data_bits == 9) {
-        obj->databits = UART_WORDLENGTH_9B;
-    } else {
-        obj->databits = UART_WORDLENGTH_8B;
-    }
-
-    switch (parity) {
-        case ParityOdd:
-        case ParityForced0:
-            obj->parity = UART_PARITY_ODD;
-            break;
-        case ParityEven:
-        case ParityForced1:
-            obj->parity = UART_PARITY_EVEN;
-            break;
-        default: // ParityNone
-            obj->parity = UART_PARITY_NONE;
-            break;
-    }
-
-    if (stop_bits == 2) {
-        obj->stopbits = UART_STOPBITS_2;
-    } else {
-        obj->stopbits = UART_STOPBITS_1;
-    }
-
-    init_uart(obj);
-}
-
-/******************************************************************************
- * INTERRUPTS HANDLING
- ******************************************************************************/
-
-static void uart_irq(UARTName name, int id)
-{
-    UartHandle.Instance = (USART_TypeDef *)name;
-    if (serial_irq_ids[id] != 0) {
-        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TC) != RESET) {
-            irq_handler(serial_irq_ids[id], TxIrq);
-            __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TC);
-        }
-        if (__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) {
-            irq_handler(serial_irq_ids[id], RxIrq);
-            __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE);
-        }
-    }
-}
-
-static void uart1_irq(void)
-{
-    uart_irq(UART_1, 0);
-}
-
-static void uart2_irq(void)
-{
-    uart_irq(UART_2, 1);
-}
-
-static void uart3_irq(void)
-{
-    uart_irq(UART_3, 2);
-}
-
-#if defined(USART4_BASE)
-static void uart4_irq(void)
-{
-    uart_irq(UART_4, 3);
-}
-#endif
-
-#if defined(USART5_BASE)
-static void uart5_irq(void)
-{
-    uart_irq(UART_5, 4);
-}
-#endif
-
-void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
-{
-    irq_handler = handler;
-    serial_irq_ids[obj->index] = id;
-}
-
-void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
-{
-    IRQn_Type irq_n = (IRQn_Type)0;
-    uint32_t vector = 0;
-
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-
-    if (obj->uart == UART_1) {
-        irq_n = USART1_IRQn;
-        vector = (uint32_t)&uart1_irq;
-    }
-
-    if (obj->uart == UART_2) {
-        irq_n = USART2_IRQn;
-        vector = (uint32_t)&uart2_irq;
-    }
-
-    if (obj->uart == UART_3) {
-        irq_n = USART3_IRQn;
-        vector = (uint32_t)&uart3_irq;
-    }
-
-#if defined(USART4_BASE)
-    if (obj->uart == UART_4) {
-        irq_n = UART4_IRQn;
-        vector = (uint32_t)&uart4_irq;
-    }
-#endif
-
-#if defined(USART5_BASE)
-    if (obj->uart == UART_5) {
-        irq_n = UART5_IRQn;
-        vector = (uint32_t)&uart5_irq;
-    }
-#endif
-
-    if (enable) {
-
-        if (irq == RxIrq) {
-            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_RXNE);
-        } else { // TxIrq
-            __HAL_UART_ENABLE_IT(&UartHandle, UART_IT_TC);
-        }
-
-        NVIC_SetVector(irq_n, vector);
-        NVIC_EnableIRQ(irq_n);
-
-    } else { // disable
-
-        int all_disabled = 0;
-
-        if (irq == RxIrq) {
-            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_RXNE);
-            // Check if TxIrq is disabled too
-            if ((UartHandle.Instance->CR1 & USART_CR1_TXEIE) == 0) all_disabled = 1;
-        } else { // TxIrq
-            __HAL_UART_DISABLE_IT(&UartHandle, UART_IT_TXE);
-            // Check if RxIrq is disabled too
-            if ((UartHandle.Instance->CR1 & USART_CR1_RXNEIE) == 0) all_disabled = 1;
-        }
-
-        if (all_disabled) NVIC_DisableIRQ(irq_n);
-
-    }
-}
-
-/******************************************************************************
- * READ/WRITE
- ******************************************************************************/
-
-int serial_getc(serial_t *obj)
-{
-    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
-    while (!serial_readable(obj));
-    return (int)(uart->DR & 0xFF);
-}
-
-void serial_putc(serial_t *obj, int c)
-{
-    USART_TypeDef *uart = (USART_TypeDef *)(obj->uart);
-    while (!serial_writable(obj));
-    uart->DR = (uint32_t)(c & 0xFF);
-}
-
-int serial_readable(serial_t *obj)
-{
-    int status;
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    // Check if data is received
-    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-int serial_writable(serial_t *obj)
-{
-    int status;
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    // Check if data is transmitted
-    status = ((__HAL_UART_GET_FLAG(&UartHandle, UART_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-void serial_clear(serial_t *obj)
-{
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_TXE);
-    __HAL_UART_CLEAR_FLAG(&UartHandle, UART_FLAG_RXNE);
-}
-
-void serial_pinout_tx(PinName tx)
-{
-    pinmap_pinout(tx, PinMap_UART_TX);
-}
-
-void serial_break_set(serial_t *obj)
-{
-    UartHandle.Instance = (USART_TypeDef *)(obj->uart);
-    HAL_LIN_SendBreak(&UartHandle);
-}
-
-void serial_break_clear(serial_t *obj)
-{
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/sleep.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,98 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "sleep_api.h"
-
-#if DEVICE_SLEEP
-
-#include "cmsis.h"
-
-static TIM_HandleTypeDef TimMasterHandle;
-
-void sleep(void)
-{
-    // Disable HAL tick interrupt
-    TimMasterHandle.Instance = TIM5;
-    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
-
-    // Request to enter SLEEP mode
-    HAL_PWR_EnterSLEEPMode(PWR_MAINREGULATOR_ON, PWR_SLEEPENTRY_WFI);
-
-    // Enable HAL tick interrupt
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
-}
-
-void deepsleep(void)
-{
-#if defined(TARGET_MOTE_L152RC)
-    int8_t STOPEntry = PWR_STOPENTRY_WFI;
-#endif
-
-    // Disable HAL tick interrupt
-    TimMasterHandle.Instance = TIM5;
-    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC2);
-
-#if defined(TARGET_MOTE_L152RC)
-    /* Select the regulator state in Stop mode: Set PDDS and LPSDSR bit according to PWR_Regulator value */
-    MODIFY_REG(PWR->CR, (PWR_CR_PDDS | PWR_CR_LPSDSR), PWR_LOWPOWERREGULATOR_ON);
-
-    /* Set SLEEPDEEP bit of Cortex System Control Register */
-    SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-
-    /* Select Stop mode entry --------------------------------------------------*/
-    if(STOPEntry == PWR_STOPENTRY_WFI)
-    {
-        /* Request Wait For Interrupt */
-        __WFI();
-    }
-    else
-    {
-        /* Request Wait For Event */
-        __SEV();
-        __WFE();
-        __WFE();
-    }
-    __NOP();
-    __NOP();
-    __NOP();
-    /* Reset SLEEPDEEP bit of Cortex System Control Register */
-    CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
-#else
-    // Request to enter STOP mode with regulator in low power mode
-    HAL_PWR_EnterSTOPMode(PWR_LOWPOWERREGULATOR_ON, PWR_STOPENTRY_WFI);
-#endif
-
-    // After wake-up from STOP reconfigure the PLL
-    SetSysClock();
-
-    // Enable HAL tick interrupt
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC2);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/spi_api.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,293 +0,0 @@
-/* mbed Microcontroller Library
- *******************************************************************************
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *******************************************************************************
- */
-#include "mbed_assert.h"
-#include "spi_api.h"
-
-#if DEVICE_SPI
-
-#include <math.h>
-#include "cmsis.h"
-#include "pinmap.h"
-#include "PeripheralPins.h"
-
-static SPI_HandleTypeDef SpiHandle;
-
-static void init_spi(spi_t *obj)
-{
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-
-    __HAL_SPI_DISABLE(&SpiHandle);
-
-    SpiHandle.Init.Mode              = obj->mode;
-    SpiHandle.Init.BaudRatePrescaler = obj->br_presc;
-    SpiHandle.Init.Direction         = SPI_DIRECTION_2LINES;
-    SpiHandle.Init.CLKPhase          = obj->cpha;
-    SpiHandle.Init.CLKPolarity       = obj->cpol;
-    SpiHandle.Init.CRCCalculation    = SPI_CRCCALCULATION_DISABLED;
-    SpiHandle.Init.CRCPolynomial     = 7;
-    SpiHandle.Init.DataSize          = obj->bits;
-    SpiHandle.Init.FirstBit          = SPI_FIRSTBIT_MSB;
-    SpiHandle.Init.NSS               = obj->nss;
-    SpiHandle.Init.TIMode            = SPI_TIMODE_DISABLED;
-
-    HAL_SPI_Init(&SpiHandle);
-
-    __HAL_SPI_ENABLE(&SpiHandle);
-}
-
-void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel)
-{
-    // Determine the SPI to use
-    SPIName spi_mosi = (SPIName)pinmap_peripheral(mosi, PinMap_SPI_MOSI);
-    SPIName spi_miso = (SPIName)pinmap_peripheral(miso, PinMap_SPI_MISO);
-    SPIName spi_sclk = (SPIName)pinmap_peripheral(sclk, PinMap_SPI_SCLK);
-    SPIName spi_ssel = (SPIName)pinmap_peripheral(ssel, PinMap_SPI_SSEL);
-
-    SPIName spi_data = (SPIName)pinmap_merge(spi_mosi, spi_miso);
-    SPIName spi_cntl = (SPIName)pinmap_merge(spi_sclk, spi_ssel);
-
-    obj->spi = (SPIName)pinmap_merge(spi_data, spi_cntl);
-    MBED_ASSERT(obj->spi != (SPIName)NC);
-
-    // Enable SPI clock
-    if (obj->spi == SPI_1) {
-        __SPI1_CLK_ENABLE();
-    }
-    if (obj->spi == SPI_2) {
-        __SPI2_CLK_ENABLE();
-    }
-    if (obj->spi == SPI_3) {
-        __SPI3_CLK_ENABLE();
-    }
-
-    // Configure the SPI pins
-    pinmap_pinout(mosi, PinMap_SPI_MOSI);
-    pinmap_pinout(miso, PinMap_SPI_MISO);
-    pinmap_pinout(sclk, PinMap_SPI_SCLK);
-
-    // Save new values
-    obj->bits = SPI_DATASIZE_8BIT;
-    obj->cpol = SPI_POLARITY_LOW;
-    obj->cpha = SPI_PHASE_1EDGE;
-    obj->br_presc = SPI_BAUDRATEPRESCALER_256;
-
-    obj->pin_miso = miso;
-    obj->pin_mosi = mosi;
-    obj->pin_sclk = sclk;
-    obj->pin_ssel = ssel;
-
-    if (ssel != NC) {
-        pinmap_pinout(ssel, PinMap_SPI_SSEL);
-    } else {
-        obj->nss = SPI_NSS_SOFT;
-    }
-
-    init_spi(obj);
-}
-
-void spi_free(spi_t *obj)
-{
-    // Reset SPI and disable clock
-    if (obj->spi == SPI_1) {
-        __SPI1_FORCE_RESET();
-        __SPI1_RELEASE_RESET();
-        __SPI1_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_2) {
-        __SPI2_FORCE_RESET();
-        __SPI2_RELEASE_RESET();
-        __SPI2_CLK_DISABLE();
-    }
-
-    if (obj->spi == SPI_3) {
-        __SPI3_FORCE_RESET();
-        __SPI3_RELEASE_RESET();
-        __SPI3_CLK_DISABLE();
-    }
-
-    // Configure GPIO
-    pin_function(obj->pin_miso, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_mosi, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_sclk, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-    pin_function(obj->pin_ssel, STM_PIN_DATA(STM_MODE_INPUT, GPIO_NOPULL, 0));
-}
-
-void spi_format(spi_t *obj, int bits, int mode, int slave)
-{
-    // Save new values
-    if (bits == 16) {
-        obj->bits = SPI_DATASIZE_16BIT;
-    } else {
-        obj->bits = SPI_DATASIZE_8BIT;
-    }
-
-    switch (mode) {
-        case 0:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        case 1:
-            obj->cpol = SPI_POLARITY_LOW;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-        case 2:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_1EDGE;
-            break;
-        default:
-            obj->cpol = SPI_POLARITY_HIGH;
-            obj->cpha = SPI_PHASE_2EDGE;
-            break;
-    }
-
-    if (obj->nss != SPI_NSS_SOFT) {
-        obj->nss = (slave) ? SPI_NSS_HARD_INPUT : SPI_NSS_HARD_OUTPUT;
-    }
-
-    obj->mode = (slave) ? SPI_MODE_SLAVE : SPI_MODE_MASTER;
-
-    init_spi(obj);
-}
-
-void spi_frequency(spi_t *obj, int hz)
-{
-    // Values depend of PCLK1 and PCLK2: 32 MHz if HSI is used, 24 MHz if HSE is used
-    if (SystemCoreClock == 32000000) { // HSI
-        if (hz < 250000) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 125 kHz
-        } else if ((hz >= 250000) && (hz < 500000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 250 kHz
-        } else if ((hz >= 500000) && (hz < 1000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 500 kHz
-        } else if ((hz >= 1000000) && (hz < 2000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 1 MHz
-        } else if ((hz >= 2000000) && (hz < 4000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 2 MHz
-        } else if ((hz >= 4000000) && (hz < 8000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 4 MHz
-        } else if ((hz >= 8000000) && (hz < 16000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 8 MHz
-        } else { // >= 16000000
-            obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 16 MHz
-        }
-    } else { // 24 MHz - HSE
-        if (hz < 180000) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_256; // 94 kHz
-        } else if ((hz >= 180000) && (hz < 350000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_128; // 188 kHz
-        } else if ((hz >= 350000) && (hz < 750000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_64; // 375 kHz
-        } else if ((hz >= 750000) && (hz < 1000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_32; // 750 kHz
-        } else if ((hz >= 1000000) && (hz < 3000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_16; // 1.5 MHz
-        } else if ((hz >= 3000000) && (hz < 6000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_8; // 3 MHz
-        } else if ((hz >= 6000000) && (hz < 12000000)) {
-            obj->br_presc = SPI_BAUDRATEPRESCALER_4; // 6 MHz
-        } else { // >= 12000000
-            obj->br_presc = SPI_BAUDRATEPRESCALER_2; // 12 MHz
-        }
-    }
-    init_spi(obj);
-}
-
-static inline int ssp_readable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is received
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_RXNE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline int ssp_writeable(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    // Check if data is transmitted
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_TXE) != RESET) ? 1 : 0);
-    return status;
-}
-
-static inline void ssp_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-static inline int ssp_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-static inline int ssp_busy(spi_t *obj)
-{
-    int status;
-    SpiHandle.Instance = (SPI_TypeDef *)(obj->spi);
-    status = ((__HAL_SPI_GET_FLAG(&SpiHandle, SPI_FLAG_BSY) != RESET) ? 1 : 0);
-    return status;
-}
-
-int spi_master_write(spi_t *obj, int value)
-{
-    ssp_write(obj, value);
-    return ssp_read(obj);
-}
-
-int spi_slave_receive(spi_t *obj)
-{
-    return (ssp_readable(obj) ? 1 : 0);
-};
-
-int spi_slave_read(spi_t *obj)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_readable(obj));
-    return (int)spi->DR;
-}
-
-void spi_slave_write(spi_t *obj, int value)
-{
-    SPI_TypeDef *spi = (SPI_TypeDef *)(obj->spi);
-    while (!ssp_writeable(obj));
-    spi->DR = (uint16_t)value;
-}
-
-int spi_busy(spi_t *obj)
-{
-    return ssp_busy(obj);
-}
-
-#endif

--- a/targets/hal/TARGET_STM/TARGET_STM32L1/us_ticker.c	Thu Sep 08 02:46:37 2016 +0000
+++ /dev/null	Thu Jan 01 00:00:00 1970 +0000
@@ -1,69 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2014, STMicroelectronics
- * All rights reserved.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions are met:
- *
- * 1. Redistributions of source code must retain the above copyright notice,
- *    this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright notice,
- *    this list of conditions and the following disclaimer in the documentation
- *    and/or other materials provided with the distribution.
- * 3. Neither the name of STMicroelectronics nor the names of its contributors
- *    may be used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include <stddef.h>
-#include "us_ticker_api.h"
-#include "PeripheralNames.h"
-
-#define TIM_MST TIM5
-
-static TIM_HandleTypeDef TimMasterHandle;
-static int us_ticker_inited = 0;
-
-void us_ticker_init(void)
-{
-    if (us_ticker_inited) return;
-    us_ticker_inited = 1;
-
-    TimMasterHandle.Instance = TIM_MST;
-
-    HAL_InitTick(0); // The passed value is not used
-}
-
-uint32_t us_ticker_read()
-{
-    if (!us_ticker_inited) us_ticker_init();
-    return TIM_MST->CNT;
-}
-
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
-    // Set new output compare value
-    __HAL_TIM_SetCompare(&TimMasterHandle, TIM_CHANNEL_1, (uint32_t)timestamp);
-    // Enable IT
-    __HAL_TIM_ENABLE_IT(&TimMasterHandle, TIM_IT_CC1);
-}
-
-void us_ticker_disable_interrupt(void)
-{
-    __HAL_TIM_DISABLE_IT(&TimMasterHandle, TIM_IT_CC1);
-}
-
-void us_ticker_clear_interrupt(void)
-{
-    __HAL_TIM_CLEAR_IT(&TimMasterHandle, TIM_IT_CC1);
-}