Firis SA / SX1276Lib

Correction in RX config error. If REG_LR_PAYLOADLENGTH and REG_LR_PAYLOADMAXLENGTH is not set, the RX is limited to 64 bytes.

Fork of SX1276Lib by Semtech

sx1276/sx1276.cpp@25:7ab8cc20ae64, 2016-05-03 (annotated)

Committer:
firis
Date:
Tue May 03 19:18:20 2016 +0000
Revision:
25:7ab8cc20ae64
Parent:
24:79c5b50b2b9c 
Correction in RX config error. If REG_LR_PAYLOADLENGTH and REG_LR_PAYLOADMAXLENGTH is not set, the RX is limited to 64 bytes.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
GregCr 0:e6ceb13d2d05 15 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 16
GregCr 0:e6ceb13d2d05 17 const FskBandwidth_t SX1276::FskBandwidths[] =
GregCr 0:e6ceb13d2d05 18 {
GregCr 0:e6ceb13d2d05 19 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 20 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 21 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 22 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 23 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 24 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 25 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 26 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 27 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 28 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 29 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 30 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 31 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 32 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 33 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 34 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 35 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 36 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 37 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 38 { 200000, 0x09 },
mluis 15:04374b1c33fa 39 { 250000, 0x01 },
mluis 16:d447f8d2d2d6 40 { 300000, 0x00 }, // Invalid Badwidth
GregCr 0:e6ceb13d2d05 41 };
GregCr 0:e6ceb13d2d05 42
GregCr 0:e6ceb13d2d05 43
mluis 21:2e496deb7858 44 SX1276::SX1276( RadioEvents_t *events,
mluis 13:618826a997e2 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
GregCr 0:e6ceb13d2d05 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 21:2e496deb7858 47 : Radio( events ),
mluis 13:618826a997e2 48 spi( mosi, miso, sclk ),
mluis 13:618826a997e2 49 nss( nss ),
mluis 13:618826a997e2 50 reset( reset ),
mluis 13:618826a997e2 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 13:618826a997e2 52 isRadioActive( false )
GregCr 0:e6ceb13d2d05 53 {
mluis 13:618826a997e2 54 wait_ms( 10 );
mluis 13:618826a997e2 55 this->rxTx = 0;
GregCr 23:1e143575df0f 56 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 57 previousOpMode = RF_OPMODE_STANDBY;
mluis 13:618826a997e2 58
mluis 21:2e496deb7858 59 this->RadioEvents = events;
mluis 21:2e496deb7858 60
mluis 13:618826a997e2 61 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 62
mluis 13:618826a997e2 63 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 64 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 65 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 66 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 67 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 68 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 69
mluis 21:2e496deb7858 70 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 71 }
GregCr 0:e6ceb13d2d05 72
GregCr 0:e6ceb13d2d05 73 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 74 {
GregCr 23:1e143575df0f 75 delete this->rxtxBuffer;
mluis 13:618826a997e2 76 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 77 }
GregCr 0:e6ceb13d2d05 78
mluis 21:2e496deb7858 79 void SX1276::Init( RadioEvents_t *events )
mluis 21:2e496deb7858 80 {
mluis 21:2e496deb7858 81 this->RadioEvents = events;
mluis 21:2e496deb7858 82 }
mluis 21:2e496deb7858 83
GregCr 19:71a47bb03fbb 84 RadioState SX1276::GetStatus( void )
GregCr 0:e6ceb13d2d05 85 {
GregCr 0:e6ceb13d2d05 86 return this->settings.State;
GregCr 0:e6ceb13d2d05 87 }
GregCr 0:e6ceb13d2d05 88
GregCr 0:e6ceb13d2d05 89 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 90 {
GregCr 0:e6ceb13d2d05 91 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 92 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 93 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 94 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 95 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 96 }
GregCr 0:e6ceb13d2d05 97
mluis 22:7f3aab69cca9 98 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
GregCr 0:e6ceb13d2d05 99 {
GregCr 7:2b555111463f 100 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 101
GregCr 0:e6ceb13d2d05 102 SetModem( modem );
GregCr 0:e6ceb13d2d05 103
GregCr 0:e6ceb13d2d05 104 SetChannel( freq );
GregCr 0:e6ceb13d2d05 105
GregCr 0:e6ceb13d2d05 106 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 107
GregCr 4:f0ce52e94d3f 108 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 109
GregCr 0:e6ceb13d2d05 110 rssi = GetRssi( modem );
GregCr 0:e6ceb13d2d05 111
GregCr 0:e6ceb13d2d05 112 Sleep( );
GregCr 0:e6ceb13d2d05 113
mluis 22:7f3aab69cca9 114 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 115 {
GregCr 0:e6ceb13d2d05 116 return false;
GregCr 0:e6ceb13d2d05 117 }
GregCr 0:e6ceb13d2d05 118 return true;
GregCr 0:e6ceb13d2d05 119 }
GregCr 0:e6ceb13d2d05 120
GregCr 0:e6ceb13d2d05 121 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 122 {
GregCr 0:e6ceb13d2d05 123 uint8_t i;
GregCr 0:e6ceb13d2d05 124 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 125
GregCr 0:e6ceb13d2d05 126 /*
GregCr 0:e6ceb13d2d05 127 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 128 */
GregCr 0:e6ceb13d2d05 129 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 130 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 131
GregCr 0:e6ceb13d2d05 132 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 133 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 134 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 135 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 136 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 137 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 138 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 139 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 140 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 141
GregCr 0:e6ceb13d2d05 142 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 143 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 144
GregCr 0:e6ceb13d2d05 145 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 146 {
GregCr 4:f0ce52e94d3f 147 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 148 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 149 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 150 }
GregCr 0:e6ceb13d2d05 151
GregCr 0:e6ceb13d2d05 152 Sleep( );
GregCr 0:e6ceb13d2d05 153
GregCr 0:e6ceb13d2d05 154 return rnd;
GregCr 0:e6ceb13d2d05 155 }
GregCr 0:e6ceb13d2d05 156
GregCr 0:e6ceb13d2d05 157 /*!
mluis 22:7f3aab69cca9 158 * Performs the Rx chain calibration for LF and HF bands
mluis 22:7f3aab69cca9 159 * \remark Must be called just after the reset so all registers are at their
mluis 22:7f3aab69cca9 160 * default values
mluis 22:7f3aab69cca9 161 */
mluis 22:7f3aab69cca9 162 void SX1276::RxChainCalibration( void )
mluis 22:7f3aab69cca9 163 {
mluis 22:7f3aab69cca9 164 uint8_t regPaConfigInitVal;
mluis 22:7f3aab69cca9 165 uint32_t initialFreq;
mluis 22:7f3aab69cca9 166
mluis 22:7f3aab69cca9 167 // Save context
mluis 22:7f3aab69cca9 168 regPaConfigInitVal = this->Read( REG_PACONFIG );
mluis 22:7f3aab69cca9 169 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
mluis 22:7f3aab69cca9 170 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
mluis 22:7f3aab69cca9 171 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
mluis 22:7f3aab69cca9 172
mluis 22:7f3aab69cca9 173 // Cut the PA just in case, RFO output, power = -1 dBm
mluis 22:7f3aab69cca9 174 this->Write( REG_PACONFIG, 0x00 );
mluis 22:7f3aab69cca9 175
mluis 22:7f3aab69cca9 176 // Launch Rx chain calibration for LF band
mluis 22:7f3aab69cca9 177 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 178 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 179 {
mluis 22:7f3aab69cca9 180 }
mluis 22:7f3aab69cca9 181
mluis 22:7f3aab69cca9 182 // Sets a Frequency in HF band
mluis 22:7f3aab69cca9 183 SetChannel( 868000000 );
mluis 22:7f3aab69cca9 184
mluis 22:7f3aab69cca9 185 // Launch Rx chain calibration for HF band
mluis 22:7f3aab69cca9 186 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 187 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 188 {
mluis 22:7f3aab69cca9 189 }
mluis 22:7f3aab69cca9 190
mluis 22:7f3aab69cca9 191 // Restore context
mluis 22:7f3aab69cca9 192 this->Write( REG_PACONFIG, regPaConfigInitVal );
mluis 22:7f3aab69cca9 193 SetChannel( initialFreq );
mluis 22:7f3aab69cca9 194 }
mluis 22:7f3aab69cca9 195
mluis 22:7f3aab69cca9 196 /*!
GregCr 0:e6ceb13d2d05 197 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 198 *
GregCr 0:e6ceb13d2d05 199 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 200 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 201 */
GregCr 0:e6ceb13d2d05 202 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 203 {
GregCr 0:e6ceb13d2d05 204 uint8_t i;
GregCr 0:e6ceb13d2d05 205
GregCr 0:e6ceb13d2d05 206 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 207 {
GregCr 0:e6ceb13d2d05 208 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 209 {
GregCr 0:e6ceb13d2d05 210 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 211 }
GregCr 0:e6ceb13d2d05 212 }
GregCr 0:e6ceb13d2d05 213 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 214 while( 1 );
GregCr 0:e6ceb13d2d05 215 }
GregCr 0:e6ceb13d2d05 216
mluis 22:7f3aab69cca9 217 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 218 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 219 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 220 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 221 uint8_t payloadLen,
mluis 13:618826a997e2 222 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 223 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 224 {
GregCr 0:e6ceb13d2d05 225 SetModem( modem );
GregCr 0:e6ceb13d2d05 226
GregCr 0:e6ceb13d2d05 227 switch( modem )
GregCr 0:e6ceb13d2d05 228 {
GregCr 0:e6ceb13d2d05 229 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 230 {
GregCr 0:e6ceb13d2d05 231 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 232 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 233 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 234 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 235 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 236 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 237 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 238 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 239 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 240
GregCr 0:e6ceb13d2d05 241 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 242 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 243 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 244
GregCr 0:e6ceb13d2d05 245 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 246 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 247
mluis 14:8552d0b840be 248 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 249 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 22:7f3aab69cca9 250
mluis 22:7f3aab69cca9 251 if( fixLen == 1 )
mluis 22:7f3aab69cca9 252 {
mluis 22:7f3aab69cca9 253 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 22:7f3aab69cca9 254 }
GregCr 23:1e143575df0f 255 else
GregCr 23:1e143575df0f 256 {
GregCr 23:1e143575df0f 257 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
GregCr 23:1e143575df0f 258 }
GregCr 23:1e143575df0f 259
GregCr 0:e6ceb13d2d05 260 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 261 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 262 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 263 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 264 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 265 ( crcOn << 4 ) );
GregCr 0:e6ceb13d2d05 266 }
GregCr 0:e6ceb13d2d05 267 break;
GregCr 0:e6ceb13d2d05 268 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 269 {
GregCr 0:e6ceb13d2d05 270 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 271 {
GregCr 0:e6ceb13d2d05 272 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 273 while( 1 );
GregCr 0:e6ceb13d2d05 274 }
GregCr 0:e6ceb13d2d05 275 bandwidth += 7;
GregCr 0:e6ceb13d2d05 276 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 277 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 278 this->settings.LoRa.Coderate = coderate;
mluis 22:7f3aab69cca9 279 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 280 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 281 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 282 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 283 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 284 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 285 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 286 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 22:7f3aab69cca9 287
GregCr 0:e6ceb13d2d05 288 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 289 {
GregCr 0:e6ceb13d2d05 290 datarate = 12;
GregCr 0:e6ceb13d2d05 291 }
GregCr 0:e6ceb13d2d05 292 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 293 {
GregCr 0:e6ceb13d2d05 294 datarate = 6;
GregCr 0:e6ceb13d2d05 295 }
GregCr 0:e6ceb13d2d05 296
GregCr 0:e6ceb13d2d05 297 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 298 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 299 {
GregCr 0:e6ceb13d2d05 300 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 301 }
GregCr 0:e6ceb13d2d05 302 else
GregCr 0:e6ceb13d2d05 303 {
GregCr 0:e6ceb13d2d05 304 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 305 }
GregCr 0:e6ceb13d2d05 306
GregCr 0:e6ceb13d2d05 307 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 308 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 309 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 310 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 311 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 312 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 313 fixLen );
GregCr 0:e6ceb13d2d05 314
GregCr 0:e6ceb13d2d05 315 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 316 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 317 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 318 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 319 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 320 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 321 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 322
GregCr 0:e6ceb13d2d05 323 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 324 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 325 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 326 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 327
GregCr 0:e6ceb13d2d05 328 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
GregCr 0:e6ceb13d2d05 329
GregCr 0:e6ceb13d2d05 330 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 331 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 332
firis 25:7ab8cc20ae64 333 //write PAYLOADLENGTH and PAYLOADMAXLENGTH even if it's not in fixedLength
firis 25:7ab8cc20ae64 334 if (payloadLen == 0)
mluis 13:618826a997e2 335 {
firis 25:7ab8cc20ae64 336 Write(REG_LR_PAYLOADLENGTH, RX_BUFFER_SIZE);
firis 25:7ab8cc20ae64 337 Write(REG_LR_PAYLOADMAXLENGTH, RX_BUFFER_SIZE);
firis 25:7ab8cc20ae64 338 }
firis 25:7ab8cc20ae64 339 else
firis 25:7ab8cc20ae64 340 {
firis 25:7ab8cc20ae64 341 Write(REG_LR_PAYLOADLENGTH, payloadLen);
firis 25:7ab8cc20ae64 342 Write(REG_LR_PAYLOADMAXLENGTH, payloadLen);
mluis 13:618826a997e2 343 }
mluis 13:618826a997e2 344
GregCr 6:e7f02929cd3d 345 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 346 {
GregCr 6:e7f02929cd3d 347 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 348 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 349 }
GregCr 6:e7f02929cd3d 350
mluis 24:79c5b50b2b9c 351 if( ( bandwidth == 9 ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
mluis 22:7f3aab69cca9 352 {
mluis 22:7f3aab69cca9 353 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 354 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 355 Write( REG_LR_TEST3A, 0x64 );
mluis 22:7f3aab69cca9 356 }
mluis 22:7f3aab69cca9 357 else if( bandwidth == 9 )
mluis 22:7f3aab69cca9 358 {
mluis 22:7f3aab69cca9 359 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 360 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 361 Write( REG_LR_TEST3A, 0x7F );
mluis 22:7f3aab69cca9 362 }
mluis 22:7f3aab69cca9 363 else
mluis 22:7f3aab69cca9 364 {
mluis 22:7f3aab69cca9 365 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 366 Write( REG_LR_TEST36, 0x03 );
mluis 22:7f3aab69cca9 367 }
mluis 22:7f3aab69cca9 368
GregCr 0:e6ceb13d2d05 369 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 370 {
GregCr 0:e6ceb13d2d05 371 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 372 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 373 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 374 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 375 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 376 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 377 }
GregCr 0:e6ceb13d2d05 378 else
GregCr 0:e6ceb13d2d05 379 {
GregCr 0:e6ceb13d2d05 380 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 381 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 382 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 383 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 384 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 385 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 386 }
GregCr 0:e6ceb13d2d05 387 }
GregCr 0:e6ceb13d2d05 388 break;
GregCr 0:e6ceb13d2d05 389 }
GregCr 0:e6ceb13d2d05 390 }
GregCr 0:e6ceb13d2d05 391
mluis 22:7f3aab69cca9 392 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 393 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 394 uint8_t coderate, uint16_t preambleLen,
mluis 13:618826a997e2 395 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 396 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 397 {
GregCr 0:e6ceb13d2d05 398 uint8_t paConfig = 0;
GregCr 0:e6ceb13d2d05 399 uint8_t paDac = 0;
GregCr 0:e6ceb13d2d05 400
GregCr 0:e6ceb13d2d05 401 SetModem( modem );
GregCr 0:e6ceb13d2d05 402
GregCr 0:e6ceb13d2d05 403 paConfig = Read( REG_PACONFIG );
GregCr 0:e6ceb13d2d05 404 paDac = Read( REG_PADAC );
GregCr 0:e6ceb13d2d05 405
GregCr 0:e6ceb13d2d05 406 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
GregCr 0:e6ceb13d2d05 407 paConfig = ( paConfig & RF_PACONFIG_MAX_POWER_MASK ) | 0x70;
GregCr 0:e6ceb13d2d05 408
GregCr 0:e6ceb13d2d05 409 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
GregCr 0:e6ceb13d2d05 410 {
GregCr 0:e6ceb13d2d05 411 if( power > 17 )
GregCr 0:e6ceb13d2d05 412 {
GregCr 0:e6ceb13d2d05 413 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
GregCr 0:e6ceb13d2d05 414 }
GregCr 0:e6ceb13d2d05 415 else
GregCr 0:e6ceb13d2d05 416 {
GregCr 0:e6ceb13d2d05 417 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
GregCr 0:e6ceb13d2d05 418 }
GregCr 0:e6ceb13d2d05 419 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
GregCr 0:e6ceb13d2d05 420 {
GregCr 0:e6ceb13d2d05 421 if( power < 5 )
GregCr 0:e6ceb13d2d05 422 {
GregCr 0:e6ceb13d2d05 423 power = 5;
GregCr 0:e6ceb13d2d05 424 }
GregCr 0:e6ceb13d2d05 425 if( power > 20 )
GregCr 0:e6ceb13d2d05 426 {
GregCr 0:e6ceb13d2d05 427 power = 20;
GregCr 0:e6ceb13d2d05 428 }
GregCr 0:e6ceb13d2d05 429 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
GregCr 0:e6ceb13d2d05 430 }
GregCr 0:e6ceb13d2d05 431 else
GregCr 0:e6ceb13d2d05 432 {
GregCr 0:e6ceb13d2d05 433 if( power < 2 )
GregCr 0:e6ceb13d2d05 434 {
GregCr 0:e6ceb13d2d05 435 power = 2;
GregCr 0:e6ceb13d2d05 436 }
GregCr 0:e6ceb13d2d05 437 if( power > 17 )
GregCr 0:e6ceb13d2d05 438 {
GregCr 0:e6ceb13d2d05 439 power = 17;
GregCr 0:e6ceb13d2d05 440 }
GregCr 0:e6ceb13d2d05 441 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
GregCr 0:e6ceb13d2d05 442 }
GregCr 0:e6ceb13d2d05 443 }
GregCr 0:e6ceb13d2d05 444 else
GregCr 0:e6ceb13d2d05 445 {
GregCr 0:e6ceb13d2d05 446 if( power < -1 )
GregCr 0:e6ceb13d2d05 447 {
GregCr 0:e6ceb13d2d05 448 power = -1;
GregCr 0:e6ceb13d2d05 449 }
GregCr 0:e6ceb13d2d05 450 if( power > 14 )
GregCr 0:e6ceb13d2d05 451 {
GregCr 0:e6ceb13d2d05 452 power = 14;
GregCr 0:e6ceb13d2d05 453 }
GregCr 0:e6ceb13d2d05 454 paConfig = ( paConfig & RF_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
GregCr 0:e6ceb13d2d05 455 }
GregCr 0:e6ceb13d2d05 456 Write( REG_PACONFIG, paConfig );
GregCr 0:e6ceb13d2d05 457 Write( REG_PADAC, paDac );
GregCr 0:e6ceb13d2d05 458
GregCr 0:e6ceb13d2d05 459 switch( modem )
GregCr 0:e6ceb13d2d05 460 {
GregCr 0:e6ceb13d2d05 461 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 462 {
GregCr 0:e6ceb13d2d05 463 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 464 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 465 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 466 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 467 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 468 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 469 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 470 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 471 this->settings.Fsk.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 472
GregCr 0:e6ceb13d2d05 473 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 474 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 475 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 476
GregCr 0:e6ceb13d2d05 477 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 478 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 479 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 480
GregCr 0:e6ceb13d2d05 481 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 482 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 483
GregCr 0:e6ceb13d2d05 484 Write( REG_PACKETCONFIG1,
GregCr 0:e6ceb13d2d05 485 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 486 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 487 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 488 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 489 ( crcOn << 4 ) );
mluis 22:7f3aab69cca9 490
GregCr 0:e6ceb13d2d05 491 }
GregCr 0:e6ceb13d2d05 492 break;
GregCr 0:e6ceb13d2d05 493 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 494 {
GregCr 0:e6ceb13d2d05 495 this->settings.LoRa.Power = power;
GregCr 0:e6ceb13d2d05 496 if( bandwidth > 2 )
GregCr 0:e6ceb13d2d05 497 {
GregCr 0:e6ceb13d2d05 498 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 499 while( 1 );
GregCr 0:e6ceb13d2d05 500 }
GregCr 0:e6ceb13d2d05 501 bandwidth += 7;
GregCr 0:e6ceb13d2d05 502 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 503 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 504 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 505 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 506 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 507 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 508 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 22:7f3aab69cca9 509 this->settings.LoRa.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 510 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 511 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 512
GregCr 0:e6ceb13d2d05 513 if( datarate > 12 )
GregCr 0:e6ceb13d2d05 514 {
GregCr 0:e6ceb13d2d05 515 datarate = 12;
GregCr 0:e6ceb13d2d05 516 }
GregCr 0:e6ceb13d2d05 517 else if( datarate < 6 )
GregCr 0:e6ceb13d2d05 518 {
GregCr 0:e6ceb13d2d05 519 datarate = 6;
GregCr 0:e6ceb13d2d05 520 }
GregCr 0:e6ceb13d2d05 521 if( ( ( bandwidth == 7 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
GregCr 0:e6ceb13d2d05 522 ( ( bandwidth == 8 ) && ( datarate == 12 ) ) )
GregCr 0:e6ceb13d2d05 523 {
GregCr 0:e6ceb13d2d05 524 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 525 }
GregCr 0:e6ceb13d2d05 526 else
GregCr 0:e6ceb13d2d05 527 {
GregCr 0:e6ceb13d2d05 528 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 529 }
mluis 22:7f3aab69cca9 530
GregCr 6:e7f02929cd3d 531 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 532 {
GregCr 6:e7f02929cd3d 533 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 534 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 535 }
mluis 22:7f3aab69cca9 536
GregCr 0:e6ceb13d2d05 537 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 538 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 539 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 540 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 541 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
GregCr 0:e6ceb13d2d05 542 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 543 fixLen );
GregCr 0:e6ceb13d2d05 544
GregCr 0:e6ceb13d2d05 545 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 546 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 547 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 548 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 549 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 550
GregCr 0:e6ceb13d2d05 551 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 552 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 553 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 554 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 555
GregCr 0:e6ceb13d2d05 556 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 557 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 558
GregCr 0:e6ceb13d2d05 559 if( datarate == 6 )
GregCr 0:e6ceb13d2d05 560 {
GregCr 0:e6ceb13d2d05 561 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 562 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 563 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 564 RFLR_DETECTIONOPTIMIZE_SF6 );
GregCr 0:e6ceb13d2d05 565 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 566 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 567 }
GregCr 0:e6ceb13d2d05 568 else
GregCr 0:e6ceb13d2d05 569 {
GregCr 0:e6ceb13d2d05 570 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 571 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 572 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 573 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 574 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 575 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 576 }
GregCr 0:e6ceb13d2d05 577 }
GregCr 0:e6ceb13d2d05 578 break;
GregCr 0:e6ceb13d2d05 579 }
GregCr 0:e6ceb13d2d05 580 }
GregCr 0:e6ceb13d2d05 581
mluis 22:7f3aab69cca9 582 double SX1276::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
GregCr 0:e6ceb13d2d05 583 {
mluis 22:7f3aab69cca9 584 uint32_t airTime = 0;
GregCr 0:e6ceb13d2d05 585
GregCr 0:e6ceb13d2d05 586 switch( modem )
GregCr 0:e6ceb13d2d05 587 {
GregCr 0:e6ceb13d2d05 588 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 589 {
mluis 22:7f3aab69cca9 590 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 591 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 592 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 593 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 594 pktLen +
GregCr 0:e6ceb13d2d05 595 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
GregCr 0:e6ceb13d2d05 596 this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 597 }
GregCr 0:e6ceb13d2d05 598 break;
GregCr 0:e6ceb13d2d05 599 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 600 {
GregCr 0:e6ceb13d2d05 601 double bw = 0.0;
GregCr 0:e6ceb13d2d05 602 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 603 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 604 {
GregCr 0:e6ceb13d2d05 605 //case 0: // 7.8 kHz
GregCr 0:e6ceb13d2d05 606 // bw = 78e2;
GregCr 0:e6ceb13d2d05 607 // break;
GregCr 0:e6ceb13d2d05 608 //case 1: // 10.4 kHz
GregCr 0:e6ceb13d2d05 609 // bw = 104e2;
GregCr 0:e6ceb13d2d05 610 // break;
GregCr 0:e6ceb13d2d05 611 //case 2: // 15.6 kHz
GregCr 0:e6ceb13d2d05 612 // bw = 156e2;
GregCr 0:e6ceb13d2d05 613 // break;
GregCr 0:e6ceb13d2d05 614 //case 3: // 20.8 kHz
GregCr 0:e6ceb13d2d05 615 // bw = 208e2;
GregCr 0:e6ceb13d2d05 616 // break;
GregCr 0:e6ceb13d2d05 617 //case 4: // 31.2 kHz
GregCr 0:e6ceb13d2d05 618 // bw = 312e2;
GregCr 0:e6ceb13d2d05 619 // break;
GregCr 0:e6ceb13d2d05 620 //case 5: // 41.4 kHz
GregCr 0:e6ceb13d2d05 621 // bw = 414e2;
GregCr 0:e6ceb13d2d05 622 // break;
GregCr 0:e6ceb13d2d05 623 //case 6: // 62.5 kHz
GregCr 0:e6ceb13d2d05 624 // bw = 625e2;
GregCr 0:e6ceb13d2d05 625 // break;
GregCr 0:e6ceb13d2d05 626 case 7: // 125 kHz
GregCr 0:e6ceb13d2d05 627 bw = 125e3;
GregCr 0:e6ceb13d2d05 628 break;
GregCr 0:e6ceb13d2d05 629 case 8: // 250 kHz
GregCr 0:e6ceb13d2d05 630 bw = 250e3;
GregCr 0:e6ceb13d2d05 631 break;
GregCr 0:e6ceb13d2d05 632 case 9: // 500 kHz
GregCr 0:e6ceb13d2d05 633 bw = 500e3;
GregCr 0:e6ceb13d2d05 634 break;
GregCr 0:e6ceb13d2d05 635 }
GregCr 0:e6ceb13d2d05 636
GregCr 0:e6ceb13d2d05 637 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 638 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 639 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 640 // time of preamble
GregCr 0:e6ceb13d2d05 641 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 642 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 643 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 644 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 645 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
GregCr 0:e6ceb13d2d05 646 ( double )( 4 * this->settings.LoRa.Datarate -
mluis 22:7f3aab69cca9 647 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) *
GregCr 0:e6ceb13d2d05 648 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 649 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 650 double tPayload = nPayload * ts;
GregCr 0:e6ceb13d2d05 651 // Time on air
GregCr 0:e6ceb13d2d05 652 double tOnAir = tPreamble + tPayload;
GregCr 0:e6ceb13d2d05 653 // return us secs
GregCr 0:e6ceb13d2d05 654 airTime = floor( tOnAir * 1e6 + 0.999 );
GregCr 0:e6ceb13d2d05 655 }
GregCr 0:e6ceb13d2d05 656 break;
GregCr 0:e6ceb13d2d05 657 }
GregCr 0:e6ceb13d2d05 658 return airTime;
GregCr 0:e6ceb13d2d05 659 }
GregCr 0:e6ceb13d2d05 660
GregCr 0:e6ceb13d2d05 661 void SX1276::Send( uint8_t *buffer, uint8_t size )
GregCr 0:e6ceb13d2d05 662 {
GregCr 0:e6ceb13d2d05 663 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 664
GregCr 0:e6ceb13d2d05 665 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 666 {
GregCr 0:e6ceb13d2d05 667 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 668 {
GregCr 0:e6ceb13d2d05 669 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 670 this->settings.FskPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 671
GregCr 0:e6ceb13d2d05 672 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 673 {
GregCr 0:e6ceb13d2d05 674 WriteFifo( ( uint8_t* )&size, 1 );
GregCr 0:e6ceb13d2d05 675 }
GregCr 0:e6ceb13d2d05 676 else
GregCr 0:e6ceb13d2d05 677 {
GregCr 0:e6ceb13d2d05 678 Write( REG_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 679 }
GregCr 0:e6ceb13d2d05 680
GregCr 0:e6ceb13d2d05 681 if( ( size > 0 ) && ( size <= 64 ) )
GregCr 0:e6ceb13d2d05 682 {
GregCr 0:e6ceb13d2d05 683 this->settings.FskPacketHandler.ChunkSize = size;
GregCr 0:e6ceb13d2d05 684 }
GregCr 0:e6ceb13d2d05 685 else
GregCr 0:e6ceb13d2d05 686 {
GregCr 23:1e143575df0f 687 memcpy( rxtxBuffer, buffer, size );
GregCr 0:e6ceb13d2d05 688 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 689 }
GregCr 0:e6ceb13d2d05 690
GregCr 0:e6ceb13d2d05 691 // Write payload buffer
GregCr 0:e6ceb13d2d05 692 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 693 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 694 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 695 }
GregCr 0:e6ceb13d2d05 696 break;
GregCr 0:e6ceb13d2d05 697 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 698 {
GregCr 0:e6ceb13d2d05 699 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 700 {
GregCr 0:e6ceb13d2d05 701 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 22:7f3aab69cca9 702 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 703 }
GregCr 0:e6ceb13d2d05 704 else
GregCr 0:e6ceb13d2d05 705 {
GregCr 0:e6ceb13d2d05 706 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 707 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
GregCr 0:e6ceb13d2d05 708 }
GregCr 0:e6ceb13d2d05 709
GregCr 0:e6ceb13d2d05 710 this->settings.LoRaPacketHandler.Size = size;
GregCr 0:e6ceb13d2d05 711
GregCr 0:e6ceb13d2d05 712 // Initializes the payload size
GregCr 0:e6ceb13d2d05 713 Write( REG_LR_PAYLOADLENGTH, size );
GregCr 0:e6ceb13d2d05 714
GregCr 0:e6ceb13d2d05 715 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 716 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 717 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 718
GregCr 0:e6ceb13d2d05 719 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 720 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 721 {
GregCr 0:e6ceb13d2d05 722 Standby( );
GregCr 4:f0ce52e94d3f 723 wait_ms( 1 );
GregCr 0:e6ceb13d2d05 724 }
GregCr 0:e6ceb13d2d05 725 // Write payload buffer
GregCr 0:e6ceb13d2d05 726 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 727 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 728 }
GregCr 0:e6ceb13d2d05 729 break;
GregCr 0:e6ceb13d2d05 730 }
GregCr 0:e6ceb13d2d05 731
GregCr 0:e6ceb13d2d05 732 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 733 }
GregCr 0:e6ceb13d2d05 734
GregCr 0:e6ceb13d2d05 735 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 736 {
mluis 13:618826a997e2 737 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 738 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 739
GregCr 0:e6ceb13d2d05 740 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 741 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 742 }
GregCr 0:e6ceb13d2d05 743
GregCr 0:e6ceb13d2d05 744 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 745 {
GregCr 0:e6ceb13d2d05 746 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 747 rxTimeoutTimer.detach( );
mluis 22:7f3aab69cca9 748
GregCr 0:e6ceb13d2d05 749 SetOpMode( RF_OPMODE_STANDBY );
mluis 22:7f3aab69cca9 750 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 751 }
GregCr 0:e6ceb13d2d05 752
GregCr 0:e6ceb13d2d05 753 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 754 {
GregCr 0:e6ceb13d2d05 755 bool rxContinuous = false;
mluis 22:7f3aab69cca9 756
GregCr 0:e6ceb13d2d05 757 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 758 {
GregCr 0:e6ceb13d2d05 759 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 760 {
GregCr 0:e6ceb13d2d05 761 rxContinuous = this->settings.Fsk.RxContinuous;
GregCr 0:e6ceb13d2d05 762
GregCr 0:e6ceb13d2d05 763 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 764 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 765 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 766 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 767 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 768 // DIO5=ModeReady
mluis 22:7f3aab69cca9 769 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 23:1e143575df0f 770 RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 771 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 772 RF_DIOMAPPING1_DIO0_00 |
GregCr 0:e6ceb13d2d05 773 RF_DIOMAPPING1_DIO2_11 );
GregCr 0:e6ceb13d2d05 774
GregCr 0:e6ceb13d2d05 775 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 776 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 777 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 778 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
GregCr 0:e6ceb13d2d05 779
GregCr 0:e6ceb13d2d05 780 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 781
GregCr 0:e6ceb13d2d05 782 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 783 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 784 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 785 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 786 }
GregCr 0:e6ceb13d2d05 787 break;
GregCr 0:e6ceb13d2d05 788 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 789 {
GregCr 0:e6ceb13d2d05 790 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 791 {
GregCr 0:e6ceb13d2d05 792 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 793 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 794 }
GregCr 0:e6ceb13d2d05 795 else
GregCr 0:e6ceb13d2d05 796 {
GregCr 0:e6ceb13d2d05 797 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 798 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
GregCr 0:e6ceb13d2d05 799 }
GregCr 0:e6ceb13d2d05 800
mluis 22:7f3aab69cca9 801
mluis 22:7f3aab69cca9 802 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
mluis 22:7f3aab69cca9 803 if( this->settings.LoRa.Bandwidth < 9 )
mluis 22:7f3aab69cca9 804 {
mluis 22:7f3aab69cca9 805 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
mluis 22:7f3aab69cca9 806 Write( REG_LR_TEST30, 0x00 );
mluis 22:7f3aab69cca9 807 switch( this->settings.LoRa.Bandwidth )
mluis 22:7f3aab69cca9 808 {
mluis 22:7f3aab69cca9 809 case 0: // 7.8 kHz
mluis 22:7f3aab69cca9 810 Write( REG_LR_TEST2F, 0x48 );
mluis 22:7f3aab69cca9 811 SetChannel(this->settings.Channel + 7.81e3 );
mluis 22:7f3aab69cca9 812 break;
mluis 22:7f3aab69cca9 813 case 1: // 10.4 kHz
mluis 22:7f3aab69cca9 814 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 815 SetChannel(this->settings.Channel + 10.42e3 );
mluis 22:7f3aab69cca9 816 break;
mluis 22:7f3aab69cca9 817 case 2: // 15.6 kHz
mluis 22:7f3aab69cca9 818 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 819 SetChannel(this->settings.Channel + 15.62e3 );
mluis 22:7f3aab69cca9 820 break;
mluis 22:7f3aab69cca9 821 case 3: // 20.8 kHz
mluis 22:7f3aab69cca9 822 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 823 SetChannel(this->settings.Channel + 20.83e3 );
mluis 22:7f3aab69cca9 824 break;
mluis 22:7f3aab69cca9 825 case 4: // 31.2 kHz
mluis 22:7f3aab69cca9 826 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 827 SetChannel(this->settings.Channel + 31.25e3 );
mluis 22:7f3aab69cca9 828 break;
mluis 22:7f3aab69cca9 829 case 5: // 41.4 kHz
mluis 22:7f3aab69cca9 830 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 831 SetChannel(this->settings.Channel + 41.67e3 );
mluis 22:7f3aab69cca9 832 break;
mluis 22:7f3aab69cca9 833 case 6: // 62.5 kHz
mluis 22:7f3aab69cca9 834 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 835 break;
mluis 22:7f3aab69cca9 836 case 7: // 125 kHz
mluis 22:7f3aab69cca9 837 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 838 break;
mluis 22:7f3aab69cca9 839 case 8: // 250 kHz
mluis 22:7f3aab69cca9 840 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 841 break;
mluis 22:7f3aab69cca9 842 }
mluis 22:7f3aab69cca9 843 }
mluis 22:7f3aab69cca9 844 else
mluis 22:7f3aab69cca9 845 {
mluis 22:7f3aab69cca9 846 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
mluis 22:7f3aab69cca9 847 }
mluis 22:7f3aab69cca9 848
GregCr 0:e6ceb13d2d05 849 rxContinuous = this->settings.LoRa.RxContinuous;
GregCr 0:e6ceb13d2d05 850
GregCr 6:e7f02929cd3d 851 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 852 {
GregCr 6:e7f02929cd3d 853 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 854 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 855 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 856 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 857 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 858 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 859 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 860 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 861
mluis 13:618826a997e2 862 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 863 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 864 }
GregCr 6:e7f02929cd3d 865 else
GregCr 6:e7f02929cd3d 866 {
GregCr 6:e7f02929cd3d 867 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 868 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 869 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 870 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 871 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 872 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 873 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 874 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 875
GregCr 6:e7f02929cd3d 876 // DIO0=RxDone
GregCr 6:e7f02929cd3d 877 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 878 }
GregCr 0:e6ceb13d2d05 879 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 880 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 881 }
GregCr 0:e6ceb13d2d05 882 break;
GregCr 0:e6ceb13d2d05 883 }
GregCr 0:e6ceb13d2d05 884
GregCr 23:1e143575df0f 885 memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
GregCr 0:e6ceb13d2d05 886
mluis 21:2e496deb7858 887 this->settings.State = RF_RX_RUNNING;
GregCr 0:e6ceb13d2d05 888 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 889 {
GregCr 0:e6ceb13d2d05 890 rxTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 891 }
GregCr 0:e6ceb13d2d05 892
GregCr 0:e6ceb13d2d05 893 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 894 {
GregCr 0:e6ceb13d2d05 895 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 896
GregCr 0:e6ceb13d2d05 897 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 898 {
GregCr 0:e6ceb13d2d05 899 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 900 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 901 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 902 1.0 ) + 10.0 ) /
mluis 22:7f3aab69cca9 903 ( double )this->settings.Fsk.Datarate ) * 1e6 );
GregCr 0:e6ceb13d2d05 904 }
GregCr 0:e6ceb13d2d05 905 }
GregCr 0:e6ceb13d2d05 906 else
GregCr 0:e6ceb13d2d05 907 {
GregCr 0:e6ceb13d2d05 908 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 909 {
GregCr 0:e6ceb13d2d05 910 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 911 }
GregCr 0:e6ceb13d2d05 912 else
GregCr 0:e6ceb13d2d05 913 {
GregCr 0:e6ceb13d2d05 914 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 915 }
GregCr 0:e6ceb13d2d05 916 }
GregCr 0:e6ceb13d2d05 917 }
GregCr 0:e6ceb13d2d05 918
GregCr 0:e6ceb13d2d05 919 void SX1276::Tx( uint32_t timeout )
mluis 22:7f3aab69cca9 920 {
mluis 22:7f3aab69cca9 921
GregCr 0:e6ceb13d2d05 922 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 923 {
GregCr 0:e6ceb13d2d05 924 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 925 {
GregCr 0:e6ceb13d2d05 926 // DIO0=PacketSent
GregCr 23:1e143575df0f 927 // DIO1=FifoEmpty
GregCr 0:e6ceb13d2d05 928 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 929 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 930 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 931 // DIO5=ModeReady
mluis 22:7f3aab69cca9 932 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 23:1e143575df0f 933 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 23:1e143575df0f 934 RF_DIOMAPPING1_DIO1_01 );
GregCr 0:e6ceb13d2d05 935
GregCr 0:e6ceb13d2d05 936 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 937 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 938 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 939 }
GregCr 0:e6ceb13d2d05 940 break;
GregCr 0:e6ceb13d2d05 941 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 942 {
GregCr 6:e7f02929cd3d 943 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 944 {
GregCr 6:e7f02929cd3d 945 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 946 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 947 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 948 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 949 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 950 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 951 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 952 RFLR_IRQFLAGS_CADDETECTED );
GregCr 6:e7f02929cd3d 953
mluis 22:7f3aab69cca9 954 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 22:7f3aab69cca9 955 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 956 }
GregCr 6:e7f02929cd3d 957 else
GregCr 6:e7f02929cd3d 958 {
GregCr 6:e7f02929cd3d 959 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 960 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 961 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 962 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 963 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 964 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 965 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 966 RFLR_IRQFLAGS_CADDETECTED );
mluis 22:7f3aab69cca9 967
GregCr 6:e7f02929cd3d 968 // DIO0=TxDone
mluis 22:7f3aab69cca9 969 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 970 }
GregCr 0:e6ceb13d2d05 971 }
GregCr 0:e6ceb13d2d05 972 break;
GregCr 0:e6ceb13d2d05 973 }
GregCr 0:e6ceb13d2d05 974
mluis 21:2e496deb7858 975 this->settings.State = RF_TX_RUNNING;
mluis 13:618826a997e2 976 txTimeoutTimer.attach_us( this, &SX1276::OnTimeoutIrq, timeout );
GregCr 0:e6ceb13d2d05 977 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 978 }
GregCr 0:e6ceb13d2d05 979
GregCr 7:2b555111463f 980 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 981 {
GregCr 7:2b555111463f 982 switch( this->settings.Modem )
GregCr 7:2b555111463f 983 {
GregCr 7:2b555111463f 984 case MODEM_FSK:
GregCr 7:2b555111463f 985 {
GregCr 7:2b555111463f 986
GregCr 7:2b555111463f 987 }
GregCr 7:2b555111463f 988 break;
GregCr 7:2b555111463f 989 case MODEM_LORA:
GregCr 7:2b555111463f 990 {
GregCr 7:2b555111463f 991 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 992 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 993 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 994 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 995 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 996 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 997 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
GregCr 12:aa5b3bf7fdf4 998 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 999 );
GregCr 7:2b555111463f 1000
GregCr 7:2b555111463f 1001 // DIO3=CADDone
GregCr 7:2b555111463f 1002 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 7:2b555111463f 1003
mluis 21:2e496deb7858 1004 this->settings.State = RF_CAD;
GregCr 7:2b555111463f 1005 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 1006 }
GregCr 7:2b555111463f 1007 break;
GregCr 7:2b555111463f 1008 default:
GregCr 7:2b555111463f 1009 break;
GregCr 7:2b555111463f 1010 }
GregCr 7:2b555111463f 1011 }
GregCr 7:2b555111463f 1012
mluis 22:7f3aab69cca9 1013 int16_t SX1276::GetRssi( RadioModems_t modem )
GregCr 7:2b555111463f 1014 {
GregCr 7:2b555111463f 1015 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 1016
GregCr 0:e6ceb13d2d05 1017 switch( modem )
GregCr 0:e6ceb13d2d05 1018 {
GregCr 0:e6ceb13d2d05 1019 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1020 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1021 break;
GregCr 0:e6ceb13d2d05 1022 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1023 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1024 {
GregCr 0:e6ceb13d2d05 1025 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1026 }
GregCr 0:e6ceb13d2d05 1027 else
GregCr 0:e6ceb13d2d05 1028 {
GregCr 0:e6ceb13d2d05 1029 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1030 }
GregCr 0:e6ceb13d2d05 1031 break;
GregCr 0:e6ceb13d2d05 1032 default:
GregCr 0:e6ceb13d2d05 1033 rssi = -1;
GregCr 0:e6ceb13d2d05 1034 break;
GregCr 0:e6ceb13d2d05 1035 }
GregCr 0:e6ceb13d2d05 1036 return rssi;
GregCr 0:e6ceb13d2d05 1037 }
GregCr 0:e6ceb13d2d05 1038
GregCr 0:e6ceb13d2d05 1039 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 1040 {
GregCr 0:e6ceb13d2d05 1041 if( opMode != previousOpMode )
GregCr 0:e6ceb13d2d05 1042 {
GregCr 0:e6ceb13d2d05 1043 previousOpMode = opMode;
GregCr 0:e6ceb13d2d05 1044 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 1045 {
GregCr 0:e6ceb13d2d05 1046 SetAntSwLowPower( true );
GregCr 0:e6ceb13d2d05 1047 }
GregCr 0:e6ceb13d2d05 1048 else
GregCr 0:e6ceb13d2d05 1049 {
GregCr 0:e6ceb13d2d05 1050 SetAntSwLowPower( false );
GregCr 0:e6ceb13d2d05 1051 if( opMode == RF_OPMODE_TRANSMITTER )
GregCr 0:e6ceb13d2d05 1052 {
GregCr 0:e6ceb13d2d05 1053 SetAntSw( 1 );
GregCr 0:e6ceb13d2d05 1054 }
GregCr 0:e6ceb13d2d05 1055 else
GregCr 0:e6ceb13d2d05 1056 {
GregCr 0:e6ceb13d2d05 1057 SetAntSw( 0 );
GregCr 0:e6ceb13d2d05 1058 }
GregCr 0:e6ceb13d2d05 1059 }
GregCr 0:e6ceb13d2d05 1060 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1061 }
GregCr 0:e6ceb13d2d05 1062 }
GregCr 0:e6ceb13d2d05 1063
mluis 22:7f3aab69cca9 1064 void SX1276::SetModem( RadioModems_t modem )
GregCr 0:e6ceb13d2d05 1065 {
mluis 22:7f3aab69cca9 1066 if( this->settings.Modem == modem )
mluis 22:7f3aab69cca9 1067 {
mluis 22:7f3aab69cca9 1068 return;
mluis 22:7f3aab69cca9 1069 }
mluis 22:7f3aab69cca9 1070
mluis 22:7f3aab69cca9 1071 this->settings.Modem = modem;
mluis 22:7f3aab69cca9 1072 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1073 {
mluis 22:7f3aab69cca9 1074 default:
mluis 22:7f3aab69cca9 1075 case MODEM_FSK:
mluis 22:7f3aab69cca9 1076 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1077 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 22:7f3aab69cca9 1078
mluis 22:7f3aab69cca9 1079 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1080 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 22:7f3aab69cca9 1081 break;
mluis 22:7f3aab69cca9 1082 case MODEM_LORA:
mluis 22:7f3aab69cca9 1083 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 1084 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 22:7f3aab69cca9 1085
mluis 22:7f3aab69cca9 1086 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1087 Write( REG_DIOMAPPING2, 0x00 );
mluis 22:7f3aab69cca9 1088 break;
GregCr 0:e6ceb13d2d05 1089 }
GregCr 0:e6ceb13d2d05 1090 }
GregCr 0:e6ceb13d2d05 1091
mluis 22:7f3aab69cca9 1092 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 20:e05596ba4166 1093 {
mluis 20:e05596ba4166 1094 this->SetModem( modem );
mluis 20:e05596ba4166 1095
mluis 20:e05596ba4166 1096 switch( modem )
mluis 20:e05596ba4166 1097 {
mluis 20:e05596ba4166 1098 case MODEM_FSK:
mluis 20:e05596ba4166 1099 if( this->settings.Fsk.FixLen == false )
mluis 20:e05596ba4166 1100 {
mluis 20:e05596ba4166 1101 this->Write( REG_PAYLOADLENGTH, max );
mluis 20:e05596ba4166 1102 }
mluis 20:e05596ba4166 1103 break;
mluis 20:e05596ba4166 1104 case MODEM_LORA:
mluis 20:e05596ba4166 1105 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 20:e05596ba4166 1106 break;
mluis 20:e05596ba4166 1107 }
mluis 20:e05596ba4166 1108 }
mluis 20:e05596ba4166 1109
GregCr 0:e6ceb13d2d05 1110 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1111 {
GregCr 0:e6ceb13d2d05 1112 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1113 {
mluis 21:2e496deb7858 1114 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1115 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1116 {
GregCr 0:e6ceb13d2d05 1117 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1118 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1119 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1120 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1121
GregCr 0:e6ceb13d2d05 1122 // Clear Irqs
GregCr 0:e6ceb13d2d05 1123 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1124 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1125 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1126 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1127
GregCr 0:e6ceb13d2d05 1128 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1129 {
GregCr 0:e6ceb13d2d05 1130 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1131 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1132 }
GregCr 0:e6ceb13d2d05 1133 else
GregCr 0:e6ceb13d2d05 1134 {
mluis 21:2e496deb7858 1135 this->settings.State = RF_IDLE;
GregCr 5:11ec8a6ba4f0 1136 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1137 }
GregCr 0:e6ceb13d2d05 1138 }
mluis 22:7f3aab69cca9 1139 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1140 {
mluis 21:2e496deb7858 1141 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1142 }
GregCr 0:e6ceb13d2d05 1143 break;
mluis 21:2e496deb7858 1144 case RF_TX_RUNNING:
mluis 21:2e496deb7858 1145 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1146 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1147 {
mluis 21:2e496deb7858 1148 this->RadioEvents->TxTimeout( );
GregCr 0:e6ceb13d2d05 1149 }
GregCr 0:e6ceb13d2d05 1150 break;
GregCr 0:e6ceb13d2d05 1151 default:
GregCr 0:e6ceb13d2d05 1152 break;
GregCr 0:e6ceb13d2d05 1153 }
GregCr 0:e6ceb13d2d05 1154 }
GregCr 0:e6ceb13d2d05 1155
GregCr 0:e6ceb13d2d05 1156 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1157 {
mluis 20:e05596ba4166 1158 volatile uint8_t irqFlags = 0;
mluis 22:7f3aab69cca9 1159
GregCr 0:e6ceb13d2d05 1160 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1161 {
mluis 21:2e496deb7858 1162 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1163 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1164 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1165 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1166 {
GregCr 0:e6ceb13d2d05 1167 case MODEM_FSK:
GregCr 18:99c6e44c1672 1168 if( this->settings.Fsk.CrcOn == true )
GregCr 0:e6ceb13d2d05 1169 {
GregCr 18:99c6e44c1672 1170 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 18:99c6e44c1672 1171 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1172 {
GregCr 18:99c6e44c1672 1173 // Clear Irqs
GregCr 18:99c6e44c1672 1174 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 18:99c6e44c1672 1175 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 18:99c6e44c1672 1176 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 18:99c6e44c1672 1177 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 18:99c6e44c1672 1178
GregCr 18:99c6e44c1672 1179 if( this->settings.Fsk.RxContinuous == false )
GregCr 18:99c6e44c1672 1180 {
mluis 21:2e496deb7858 1181 this->settings.State = RF_IDLE;
GregCr 18:99c6e44c1672 1182 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 18:99c6e44c1672 1183 ( ( Read( REG_SYNCCONFIG ) &
GregCr 18:99c6e44c1672 1184 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 1185 1.0 ) + 10.0 ) /
GregCr 18:99c6e44c1672 1186 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 18:99c6e44c1672 1187 }
GregCr 18:99c6e44c1672 1188 else
GregCr 18:99c6e44c1672 1189 {
GregCr 18:99c6e44c1672 1190 // Continuous mode restart Rx chain
GregCr 18:99c6e44c1672 1191 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 18:99c6e44c1672 1192 }
GregCr 18:99c6e44c1672 1193 rxTimeoutTimer.detach( );
GregCr 18:99c6e44c1672 1194
mluis 22:7f3aab69cca9 1195 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 18:99c6e44c1672 1196 {
mluis 22:7f3aab69cca9 1197 this->RadioEvents->RxError( );
GregCr 18:99c6e44c1672 1198 }
GregCr 18:99c6e44c1672 1199 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 18:99c6e44c1672 1200 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 18:99c6e44c1672 1201 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 18:99c6e44c1672 1202 this->settings.FskPacketHandler.Size = 0;
GregCr 18:99c6e44c1672 1203 break;
GregCr 0:e6ceb13d2d05 1204 }
GregCr 0:e6ceb13d2d05 1205 }
GregCr 18:99c6e44c1672 1206
GregCr 0:e6ceb13d2d05 1207 // Read received packet size
GregCr 0:e6ceb13d2d05 1208 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1209 {
GregCr 0:e6ceb13d2d05 1210 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1211 {
GregCr 0:e6ceb13d2d05 1212 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1213 }
GregCr 0:e6ceb13d2d05 1214 else
GregCr 0:e6ceb13d2d05 1215 {
GregCr 0:e6ceb13d2d05 1216 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1217 }
GregCr 23:1e143575df0f 1218 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1219 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1220 }
GregCr 0:e6ceb13d2d05 1221 else
GregCr 0:e6ceb13d2d05 1222 {
GregCr 23:1e143575df0f 1223 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1224 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1225 }
GregCr 0:e6ceb13d2d05 1226
GregCr 0:e6ceb13d2d05 1227 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1228 {
mluis 21:2e496deb7858 1229 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1230 rxTimeoutSyncWord.attach_us( this, &SX1276::OnTimeoutIrq, ( 8.0 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 1231 ( ( Read( REG_SYNCCONFIG ) &
GregCr 0:e6ceb13d2d05 1232 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 22:7f3aab69cca9 1233 1.0 ) + 10.0 ) /
GregCr 0:e6ceb13d2d05 1234 ( double )this->settings.Fsk.Datarate ) * 1e6 ) ;
GregCr 0:e6ceb13d2d05 1235 }
GregCr 0:e6ceb13d2d05 1236 else
GregCr 0:e6ceb13d2d05 1237 {
GregCr 0:e6ceb13d2d05 1238 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1239 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
GregCr 0:e6ceb13d2d05 1240 }
GregCr 0:e6ceb13d2d05 1241 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1242
mluis 22:7f3aab69cca9 1243 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1244 {
GregCr 23:1e143575df0f 1245 this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
GregCr 0:e6ceb13d2d05 1246 }
GregCr 0:e6ceb13d2d05 1247 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1248 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1249 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1250 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1251 break;
GregCr 0:e6ceb13d2d05 1252 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1253 {
mluis 22:7f3aab69cca9 1254 int8_t snr = 0;
GregCr 0:e6ceb13d2d05 1255
GregCr 0:e6ceb13d2d05 1256 // Clear Irq
GregCr 0:e6ceb13d2d05 1257 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1258
GregCr 0:e6ceb13d2d05 1259 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1260 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1261 {
GregCr 0:e6ceb13d2d05 1262 // Clear Irq
GregCr 0:e6ceb13d2d05 1263 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1264
GregCr 0:e6ceb13d2d05 1265 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1266 {
mluis 21:2e496deb7858 1267 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1268 }
GregCr 0:e6ceb13d2d05 1269 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1270
mluis 22:7f3aab69cca9 1271 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
GregCr 0:e6ceb13d2d05 1272 {
mluis 22:7f3aab69cca9 1273 this->RadioEvents->RxError( );
GregCr 0:e6ceb13d2d05 1274 }
GregCr 0:e6ceb13d2d05 1275 break;
GregCr 0:e6ceb13d2d05 1276 }
GregCr 0:e6ceb13d2d05 1277
GregCr 0:e6ceb13d2d05 1278 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1279 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1280 {
GregCr 0:e6ceb13d2d05 1281 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1282 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1283 snr = -snr;
GregCr 0:e6ceb13d2d05 1284 }
GregCr 0:e6ceb13d2d05 1285 else
GregCr 0:e6ceb13d2d05 1286 {
GregCr 0:e6ceb13d2d05 1287 // Divide by 4
GregCr 0:e6ceb13d2d05 1288 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1289 }
GregCr 0:e6ceb13d2d05 1290
GregCr 7:2b555111463f 1291 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 22:7f3aab69cca9 1292 if( snr < 0 )
GregCr 0:e6ceb13d2d05 1293 {
GregCr 0:e6ceb13d2d05 1294 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1295 {
GregCr 0:e6ceb13d2d05 1296 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1297 snr;
GregCr 0:e6ceb13d2d05 1298 }
GregCr 0:e6ceb13d2d05 1299 else
GregCr 0:e6ceb13d2d05 1300 {
GregCr 0:e6ceb13d2d05 1301 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1302 snr;
GregCr 0:e6ceb13d2d05 1303 }
GregCr 0:e6ceb13d2d05 1304 }
GregCr 0:e6ceb13d2d05 1305 else
GregCr 0:e6ceb13d2d05 1306 {
GregCr 0:e6ceb13d2d05 1307 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1308 {
GregCr 0:e6ceb13d2d05 1309 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1310 }
GregCr 0:e6ceb13d2d05 1311 else
GregCr 0:e6ceb13d2d05 1312 {
GregCr 0:e6ceb13d2d05 1313 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1314 }
GregCr 0:e6ceb13d2d05 1315 }
GregCr 0:e6ceb13d2d05 1316
GregCr 0:e6ceb13d2d05 1317 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 23:1e143575df0f 1318 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
GregCr 0:e6ceb13d2d05 1319
GregCr 0:e6ceb13d2d05 1320 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1321 {
mluis 21:2e496deb7858 1322 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1323 }
GregCr 0:e6ceb13d2d05 1324 rxTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1325
mluis 22:7f3aab69cca9 1326 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1327 {
GregCr 23:1e143575df0f 1328 this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1329 }
GregCr 0:e6ceb13d2d05 1330 }
GregCr 0:e6ceb13d2d05 1331 break;
GregCr 0:e6ceb13d2d05 1332 default:
GregCr 0:e6ceb13d2d05 1333 break;
GregCr 0:e6ceb13d2d05 1334 }
GregCr 0:e6ceb13d2d05 1335 break;
mluis 21:2e496deb7858 1336 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1337 txTimeoutTimer.detach( );
GregCr 0:e6ceb13d2d05 1338 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1339 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1340 {
GregCr 0:e6ceb13d2d05 1341 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1342 // Clear Irq
GregCr 0:e6ceb13d2d05 1343 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1344 // Intentional fall through
GregCr 0:e6ceb13d2d05 1345 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1346 default:
mluis 21:2e496deb7858 1347 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1348 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
GregCr 0:e6ceb13d2d05 1349 {
mluis 22:7f3aab69cca9 1350 this->RadioEvents->TxDone( );
GregCr 0:e6ceb13d2d05 1351 }
GregCr 0:e6ceb13d2d05 1352 break;
GregCr 0:e6ceb13d2d05 1353 }
GregCr 0:e6ceb13d2d05 1354 break;
GregCr 0:e6ceb13d2d05 1355 default:
GregCr 0:e6ceb13d2d05 1356 break;
GregCr 0:e6ceb13d2d05 1357 }
GregCr 0:e6ceb13d2d05 1358 }
GregCr 0:e6ceb13d2d05 1359
GregCr 0:e6ceb13d2d05 1360 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1361 {
GregCr 0:e6ceb13d2d05 1362 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1363 {
mluis 21:2e496deb7858 1364 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1365 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1366 {
GregCr 0:e6ceb13d2d05 1367 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1368 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1369 // Read received packet size
GregCr 0:e6ceb13d2d05 1370 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1371 {
GregCr 0:e6ceb13d2d05 1372 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1373 {
GregCr 0:e6ceb13d2d05 1374 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1375 }
GregCr 0:e6ceb13d2d05 1376 else
GregCr 0:e6ceb13d2d05 1377 {
GregCr 0:e6ceb13d2d05 1378 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1379 }
GregCr 0:e6ceb13d2d05 1380 }
GregCr 0:e6ceb13d2d05 1381
GregCr 0:e6ceb13d2d05 1382 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1383 {
GregCr 23:1e143575df0f 1384 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1385 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1386 }
GregCr 0:e6ceb13d2d05 1387 else
GregCr 0:e6ceb13d2d05 1388 {
GregCr 23:1e143575df0f 1389 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1390 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1391 }
GregCr 0:e6ceb13d2d05 1392 break;
GregCr 0:e6ceb13d2d05 1393 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1394 // Sync time out
GregCr 0:e6ceb13d2d05 1395 rxTimeoutTimer.detach( );
mluis 21:2e496deb7858 1396 this->settings.State = RF_IDLE;
mluis 22:7f3aab69cca9 1397 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
GregCr 0:e6ceb13d2d05 1398 {
mluis 21:2e496deb7858 1399 this->RadioEvents->RxTimeout( );
GregCr 0:e6ceb13d2d05 1400 }
GregCr 0:e6ceb13d2d05 1401 break;
GregCr 0:e6ceb13d2d05 1402 default:
GregCr 0:e6ceb13d2d05 1403 break;
GregCr 0:e6ceb13d2d05 1404 }
GregCr 0:e6ceb13d2d05 1405 break;
mluis 21:2e496deb7858 1406 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1407 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1408 {
GregCr 0:e6ceb13d2d05 1409 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1410 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1411 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1412 {
GregCr 23:1e143575df0f 1413 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1414 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1415 }
GregCr 0:e6ceb13d2d05 1416 else
GregCr 0:e6ceb13d2d05 1417 {
GregCr 0:e6ceb13d2d05 1418 // Write the last chunk of data
GregCr 23:1e143575df0f 1419 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1420 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1421 }
GregCr 0:e6ceb13d2d05 1422 break;
GregCr 0:e6ceb13d2d05 1423 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1424 break;
GregCr 0:e6ceb13d2d05 1425 default:
GregCr 0:e6ceb13d2d05 1426 break;
GregCr 0:e6ceb13d2d05 1427 }
mluis 22:7f3aab69cca9 1428 break;
GregCr 0:e6ceb13d2d05 1429 default:
GregCr 0:e6ceb13d2d05 1430 break;
GregCr 0:e6ceb13d2d05 1431 }
GregCr 0:e6ceb13d2d05 1432 }
GregCr 0:e6ceb13d2d05 1433
GregCr 0:e6ceb13d2d05 1434 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1435 {
GregCr 0:e6ceb13d2d05 1436 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1437 {
mluis 21:2e496deb7858 1438 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1439 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1440 {
GregCr 0:e6ceb13d2d05 1441 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1442 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1443 {
GregCr 0:e6ceb13d2d05 1444 rxTimeoutSyncWord.detach( );
GregCr 0:e6ceb13d2d05 1445
GregCr 0:e6ceb13d2d05 1446 this->settings.FskPacketHandler.SyncWordDetected = true;
GregCr 0:e6ceb13d2d05 1447
GregCr 0:e6ceb13d2d05 1448 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1449
GregCr 0:e6ceb13d2d05 1450 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1451 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1452 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1453 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1454 }
GregCr 0:e6ceb13d2d05 1455 break;
GregCr 0:e6ceb13d2d05 1456 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1457 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1458 {
GregCr 6:e7f02929cd3d 1459 // Clear Irq
GregCr 6:e7f02929cd3d 1460 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1461
mluis 22:7f3aab69cca9 1462 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1463 {
mluis 21:2e496deb7858 1464 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1465 }
mluis 22:7f3aab69cca9 1466 }
GregCr 0:e6ceb13d2d05 1467 break;
GregCr 0:e6ceb13d2d05 1468 default:
GregCr 0:e6ceb13d2d05 1469 break;
GregCr 0:e6ceb13d2d05 1470 }
GregCr 0:e6ceb13d2d05 1471 break;
mluis 21:2e496deb7858 1472 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1473 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1474 {
GregCr 0:e6ceb13d2d05 1475 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1476 break;
GregCr 0:e6ceb13d2d05 1477 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1478 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1479 {
GregCr 6:e7f02929cd3d 1480 // Clear Irq
GregCr 6:e7f02929cd3d 1481 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
GregCr 6:e7f02929cd3d 1482
mluis 22:7f3aab69cca9 1483 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 13:618826a997e2 1484 {
mluis 21:2e496deb7858 1485 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1486 }
mluis 22:7f3aab69cca9 1487 }
GregCr 0:e6ceb13d2d05 1488 break;
GregCr 0:e6ceb13d2d05 1489 default:
GregCr 0:e6ceb13d2d05 1490 break;
GregCr 0:e6ceb13d2d05 1491 }
mluis 22:7f3aab69cca9 1492 break;
GregCr 0:e6ceb13d2d05 1493 default:
GregCr 0:e6ceb13d2d05 1494 break;
GregCr 0:e6ceb13d2d05 1495 }
GregCr 0:e6ceb13d2d05 1496 }
GregCr 0:e6ceb13d2d05 1497
GregCr 0:e6ceb13d2d05 1498 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1499 {
GregCr 0:e6ceb13d2d05 1500 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1501 {
GregCr 0:e6ceb13d2d05 1502 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1503 break;
GregCr 0:e6ceb13d2d05 1504 case MODEM_LORA:
mluis 22:7f3aab69cca9 1505 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 13:618826a997e2 1506 {
mluis 13:618826a997e2 1507 // Clear Irq
mluis 22:7f3aab69cca9 1508 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1509 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1510 {
mluis 21:2e496deb7858 1511 this->RadioEvents->CadDone( true );
mluis 13:618826a997e2 1512 }
GregCr 12:aa5b3bf7fdf4 1513 }
GregCr 12:aa5b3bf7fdf4 1514 else
mluis 13:618826a997e2 1515 {
mluis 13:618826a997e2 1516 // Clear Irq
mluis 13:618826a997e2 1517 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 22:7f3aab69cca9 1518 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 13:618826a997e2 1519 {
mluis 21:2e496deb7858 1520 this->RadioEvents->CadDone( false );
mluis 13:618826a997e2 1521 }
GregCr 7:2b555111463f 1522 }
GregCr 0:e6ceb13d2d05 1523 break;
GregCr 0:e6ceb13d2d05 1524 default:
GregCr 0:e6ceb13d2d05 1525 break;
GregCr 0:e6ceb13d2d05 1526 }
GregCr 0:e6ceb13d2d05 1527 }
GregCr 0:e6ceb13d2d05 1528
GregCr 0:e6ceb13d2d05 1529 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1530 {
GregCr 0:e6ceb13d2d05 1531 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1532 {
GregCr 0:e6ceb13d2d05 1533 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1534 {
GregCr 0:e6ceb13d2d05 1535 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1536 {
GregCr 0:e6ceb13d2d05 1537 this->settings.FskPacketHandler.PreambleDetected = true;
GregCr 0:e6ceb13d2d05 1538 }
GregCr 0:e6ceb13d2d05 1539 }
GregCr 0:e6ceb13d2d05 1540 break;
GregCr 0:e6ceb13d2d05 1541 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1542 break;
GregCr 0:e6ceb13d2d05 1543 default:
GregCr 0:e6ceb13d2d05 1544 break;
GregCr 0:e6ceb13d2d05 1545 }
GregCr 0:e6ceb13d2d05 1546 }
GregCr 0:e6ceb13d2d05 1547
GregCr 0:e6ceb13d2d05 1548 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1549 {
GregCr 0:e6ceb13d2d05 1550 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1551 {
GregCr 0:e6ceb13d2d05 1552 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1553 break;
GregCr 0:e6ceb13d2d05 1554 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1555 break;
GregCr 0:e6ceb13d2d05 1556 default:
GregCr 0:e6ceb13d2d05 1557 break;
GregCr 0:e6ceb13d2d05 1558 }
mluis 13:618826a997e2 1559 }