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TARGET_NUCLEO_F030R8/stm32f0xx.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:: emilmont
Date:: Fri Feb 14 14:36:43 2014 +0000
Revision:: 77:869cf507173a
Child:: 81:7d30d6019079

Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f0xx.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
emilmont	77:869cf507173a	5	* @version V1.3.1
emilmont	77:869cf507173a	6	* @date 17-January-2014
emilmont	77:869cf507173a	7	* @brief CMSIS Cortex-M0 Device Peripheral Access Layer Header File.
emilmont	77:869cf507173a	8	* This file contains all the peripheral register's definitions, bits
emilmont	77:869cf507173a	9	* definitions and memory mapping for STM32F0xx devices.
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* The file is the unique include file that the application programmer
emilmont	77:869cf507173a	12	* is using in the C source code, usually in main.c. This file contains:
emilmont	77:869cf507173a	13	* - Configuration section that allows to select:
emilmont	77:869cf507173a	14	* - The device used in the target application
emilmont	77:869cf507173a	15	* - To use or not the peripheral’s drivers in application code(i.e.
emilmont	77:869cf507173a	16	* code will be based on direct access to peripheral’s registers
emilmont	77:869cf507173a	17	* rather than drivers API), this option is controlled by
emilmont	77:869cf507173a	18	* "#define USE_STDPERIPH_DRIVER"
emilmont	77:869cf507173a	19	* - To change few application-specific parameters such as the HSE
emilmont	77:869cf507173a	20	* crystal frequency
emilmont	77:869cf507173a	21	* - Data structures and the address mapping for all peripherals
emilmont	77:869cf507173a	22	* - Peripheral's registers declarations and bits definition
emilmont	77:869cf507173a	23	* - Macros to access peripheral’s registers hardware
emilmont	77:869cf507173a	24	*
emilmont	77:869cf507173a	25	******************************************************************************
emilmont	77:869cf507173a	26	* @attention
emilmont	77:869cf507173a	27	*
emilmont	77:869cf507173a	28	* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	29	*
emilmont	77:869cf507173a	30	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
emilmont	77:869cf507173a	31	* You may not use this file except in compliance with the License.
emilmont	77:869cf507173a	32	* You may obtain a copy of the License at:
emilmont	77:869cf507173a	33	*
emilmont	77:869cf507173a	34	* http://www.st.com/software_license_agreement_liberty_v2
emilmont	77:869cf507173a	35	*
emilmont	77:869cf507173a	36	* Unless required by applicable law or agreed to in writing, software
emilmont	77:869cf507173a	37	* distributed under the License is distributed on an "AS IS" BASIS,
emilmont	77:869cf507173a	38	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
emilmont	77:869cf507173a	39	* See the License for the specific language governing permissions and
emilmont	77:869cf507173a	40	* limitations under the License.
emilmont	77:869cf507173a	41	*
emilmont	77:869cf507173a	42	******************************************************************************
emilmont	77:869cf507173a	43	*/
emilmont	77:869cf507173a	44
emilmont	77:869cf507173a	45	/** @addtogroup CMSIS
emilmont	77:869cf507173a	46	* @{
emilmont	77:869cf507173a	47	*/
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup stm32f0xx
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
emilmont	77:869cf507173a	52
emilmont	77:869cf507173a	53	#ifndef __STM32F0XX_H
emilmont	77:869cf507173a	54	#define __STM32F0XX_H
emilmont	77:869cf507173a	55
emilmont	77:869cf507173a	56	#ifdef __cplusplus
emilmont	77:869cf507173a	57	extern "C" {
emilmont	77:869cf507173a	58	#endif
emilmont	77:869cf507173a	59
emilmont	77:869cf507173a	60	/** @addtogroup Library_configuration_section
emilmont	77:869cf507173a	61	* @{
emilmont	77:869cf507173a	62	*/
emilmont	77:869cf507173a	63
emilmont	77:869cf507173a	64	/* Uncomment the line below according to the target STM32F0 device used in your
emilmont	77:869cf507173a	65	application
emilmont	77:869cf507173a	66	*/
emilmont	77:869cf507173a	67
emilmont	77:869cf507173a	68	#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
emilmont	77:869cf507173a	69	#define STM32F030
emilmont	77:869cf507173a	70	/* #define STM32F031 */
emilmont	77:869cf507173a	71	/* #define STM32F051 */
emilmont	77:869cf507173a	72	/* #define STM32F072 */
emilmont	77:869cf507173a	73	/* #define STM32F042 */
emilmont	77:869cf507173a	74	#endif
emilmont	77:869cf507173a	75
emilmont	77:869cf507173a	76	/* Tip: To avoid modifying this file each time you need to switch between these
emilmont	77:869cf507173a	77	devices, you can define the device in your toolchain compiler preprocessor.
emilmont	77:869cf507173a	78	*/
emilmont	77:869cf507173a	79
emilmont	77:869cf507173a	80	/* Old STM32F0XX definition, maintained for legacy purpose */
emilmont	77:869cf507173a	81	#if defined(STM32F0XX) \|\| defined(STM32F0XX_MD)
emilmont	77:869cf507173a	82	#define STM32F051
emilmont	77:869cf507173a	83	#endif /* STM32F0XX */
emilmont	77:869cf507173a	84
emilmont	77:869cf507173a	85	/* Old STM32F0XX_LD definition, maintained for legacy purpose */
emilmont	77:869cf507173a	86	#ifdef STM32F0XX_LD
emilmont	77:869cf507173a	87	#define STM32F031
emilmont	77:869cf507173a	88	#endif /* STM32F0XX_LD */
emilmont	77:869cf507173a	89
emilmont	77:869cf507173a	90	/* Old STM32F0XX_HD definition, maintained for legacy purpose */
emilmont	77:869cf507173a	91	#ifdef STM32F0XX_HD
emilmont	77:869cf507173a	92	#define STM32F072
emilmont	77:869cf507173a	93	#endif /* STM32F0XX_HD */
emilmont	77:869cf507173a	94
emilmont	77:869cf507173a	95	/* Old STM32F030X6/X8 definition, maintained for legacy purpose */
emilmont	77:869cf507173a	96	#if defined (STM32F030X8) \|\| defined (STM32F030X6)
emilmont	77:869cf507173a	97	#define STM32F030
emilmont	77:869cf507173a	98	#endif /* STM32F030X8 or STM32F030X6 */
emilmont	77:869cf507173a	99
emilmont	77:869cf507173a	100
emilmont	77:869cf507173a	101	#if !defined (STM32F030) && !defined (STM32F031) && !defined (STM32F051) && !defined (STM32F072) && !defined (STM32F042)
emilmont	77:869cf507173a	102	#error "Please select first the target STM32F0xx device used in your application (in stm32f0xx.h file)"
emilmont	77:869cf507173a	103	#endif
emilmont	77:869cf507173a	104
emilmont	77:869cf507173a	105	#if !defined USE_STDPERIPH_DRIVER
emilmont	77:869cf507173a	106	/**
emilmont	77:869cf507173a	107	* @brief Comment the line below if you will not use the peripherals drivers.
emilmont	77:869cf507173a	108	In this case, these drivers will not be included and the application code will
emilmont	77:869cf507173a	109	be based on direct access to peripherals registers
emilmont	77:869cf507173a	110	*/
emilmont	77:869cf507173a	111	#define USE_STDPERIPH_DRIVER
emilmont	77:869cf507173a	112	#endif /* USE_STDPERIPH_DRIVER */
emilmont	77:869cf507173a	113
emilmont	77:869cf507173a	114	/**
emilmont	77:869cf507173a	115	* @brief In the following line adjust the value of External High Speed oscillator (HSE)
emilmont	77:869cf507173a	116	used in your application
emilmont	77:869cf507173a	117
emilmont	77:869cf507173a	118	Tip: To avoid modifying this file each time you need to use different HSE, you
emilmont	77:869cf507173a	119	can define the HSE value in your toolchain compiler preprocessor.
emilmont	77:869cf507173a	120	*/
emilmont	77:869cf507173a	121	#if !defined (HSE_VALUE)
emilmont	77:869cf507173a	122	#define HSE_VALUE ((uint32_t)8000000) /!< Value of the External oscillator in Hz/
emilmont	77:869cf507173a	123	#endif /* HSE_VALUE */
emilmont	77:869cf507173a	124
emilmont	77:869cf507173a	125	/**
emilmont	77:869cf507173a	126	* @brief In the following line adjust the External High Speed oscillator (HSE) Startup
emilmont	77:869cf507173a	127	Timeout value
emilmont	77:869cf507173a	128	*/
emilmont	77:869cf507173a	129	#if !defined (HSE_STARTUP_TIMEOUT)
emilmont	77:869cf507173a	130	#define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /!< Time out for HSE start up /
emilmont	77:869cf507173a	131	#endif /* HSE_STARTUP_TIMEOUT */
emilmont	77:869cf507173a	132
emilmont	77:869cf507173a	133	/**
emilmont	77:869cf507173a	134	* @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
emilmont	77:869cf507173a	135	Timeout value
emilmont	77:869cf507173a	136	*/
emilmont	77:869cf507173a	137	#if !defined (HSI_STARTUP_TIMEOUT)
emilmont	77:869cf507173a	138	#define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /!< Time out for HSI start up /
emilmont	77:869cf507173a	139	#endif /* HSI_STARTUP_TIMEOUT */
emilmont	77:869cf507173a	140
emilmont	77:869cf507173a	141	#if !defined (HSI_VALUE)
emilmont	77:869cf507173a	142	#define HSI_VALUE ((uint32_t)8000000) /*!< Value of the Internal High Speed oscillator in Hz.
emilmont	77:869cf507173a	143	The real value may vary depending on the variations
emilmont	77:869cf507173a	144	in voltage and temperature. */
emilmont	77:869cf507173a	145	#endif /* HSI_VALUE */
emilmont	77:869cf507173a	146
emilmont	77:869cf507173a	147	#if !defined (HSI14_VALUE)
emilmont	77:869cf507173a	148	#define HSI14_VALUE ((uint32_t)14000000) /*!< Value of the Internal High Speed oscillator for ADC in Hz.
emilmont	77:869cf507173a	149	The real value may vary depending on the variations
emilmont	77:869cf507173a	150	in voltage and temperature. */
emilmont	77:869cf507173a	151	#endif /* HSI14_VALUE */
emilmont	77:869cf507173a	152
emilmont	77:869cf507173a	153	#if !defined (HSI48_VALUE)
emilmont	77:869cf507173a	154	#define HSI48_VALUE ((uint32_t)48000000) /*!< Value of the Internal High Speed oscillator for USB in Hz.
emilmont	77:869cf507173a	155	The real value may vary depending on the variations
emilmont	77:869cf507173a	156	in voltage and temperature. */
emilmont	77:869cf507173a	157	#endif /* HSI48_VALUE */
emilmont	77:869cf507173a	158
emilmont	77:869cf507173a	159	#if !defined (LSI_VALUE)
emilmont	77:869cf507173a	160	#define LSI_VALUE ((uint32_t)40000) /*!< Value of the Internal Low Speed oscillator in Hz
emilmont	77:869cf507173a	161	The real value may vary depending on the variations
emilmont	77:869cf507173a	162	in voltage and temperature. */
emilmont	77:869cf507173a	163	#endif /* LSI_VALUE */
emilmont	77:869cf507173a	164
emilmont	77:869cf507173a	165	#if !defined (LSE_VALUE)
emilmont	77:869cf507173a	166	#define LSE_VALUE ((uint32_t)32768) /!< Value of the External Low Speed oscillator in Hz /
emilmont	77:869cf507173a	167	#endif /* LSE_VALUE */
emilmont	77:869cf507173a	168
emilmont	77:869cf507173a	169	/**
emilmont	77:869cf507173a	170	* @brief STM32F0xx Standard Peripheral Library version number V1.3.1
emilmont	77:869cf507173a	171	*/
emilmont	77:869cf507173a	172	#define __STM32F0XX_STDPERIPH_VERSION_MAIN (0x01) /!< [31:24] main version /
emilmont	77:869cf507173a	173	#define __STM32F0XX_STDPERIPH_VERSION_SUB1 (0x03) /!< [23:16] sub1 version /
emilmont	77:869cf507173a	174	#define __STM32F0XX_STDPERIPH_VERSION_SUB2 (0x01) /!< [15:8] sub2 version /
emilmont	77:869cf507173a	175	#define __STM32F0XX_STDPERIPH_VERSION_RC (0x00) /!< [7:0] release candidate /
emilmont	77:869cf507173a	176	#define __STM32F0XX_STDPERIPH_VERSION ((__STM32F0XX_STDPERIPH_VERSION_MAIN << 24)\
emilmont	77:869cf507173a	177	\|(__STM32F0XX_STDPERIPH_VERSION_SUB1 << 16)\
emilmont	77:869cf507173a	178	\|(__STM32F0XX_STDPERIPH_VERSION_SUB2 << 8)\
emilmont	77:869cf507173a	179	\|(__STM32F0XX_STDPERIPH_VERSION_RC))
emilmont	77:869cf507173a	180
emilmont	77:869cf507173a	181	/**
emilmont	77:869cf507173a	182	* @}
emilmont	77:869cf507173a	183	*/
emilmont	77:869cf507173a	184
emilmont	77:869cf507173a	185	/** @addtogroup Configuration_section_for_CMSIS
emilmont	77:869cf507173a	186	* @{
emilmont	77:869cf507173a	187	*/
emilmont	77:869cf507173a	188
emilmont	77:869cf507173a	189	/**
emilmont	77:869cf507173a	190	* @brief STM32F0xx Interrupt Number Definition, according to the selected device
emilmont	77:869cf507173a	191	* in @ref Library_configuration_section
emilmont	77:869cf507173a	192	*/
emilmont	77:869cf507173a	193	#define __CM0_REV 0 /!< Core Revision r0p0 /
emilmont	77:869cf507173a	194	#define __MPU_PRESENT 0 /!< STM32F0xx do not provide MPU /
emilmont	77:869cf507173a	195	#define __NVIC_PRIO_BITS 2 /!< STM32F0xx uses 2 Bits for the Priority Levels /
emilmont	77:869cf507173a	196	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
emilmont	77:869cf507173a	197
emilmont	77:869cf507173a	198	/!< Interrupt Number Definition /
emilmont	77:869cf507173a	199	typedef enum IRQn
emilmont	77:869cf507173a	200	{
emilmont	77:869cf507173a	201	/**** Cortex-M0 Processor Exceptions Numbers ****************************************************/
emilmont	77:869cf507173a	202	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
emilmont	77:869cf507173a	203	HardFault_IRQn = -13, /!< 3 Cortex-M0 Hard Fault Interrupt /
emilmont	77:869cf507173a	204	SVC_IRQn = -5, /!< 11 Cortex-M0 SV Call Interrupt /
emilmont	77:869cf507173a	205	PendSV_IRQn = -2, /!< 14 Cortex-M0 Pend SV Interrupt /
emilmont	77:869cf507173a	206	SysTick_IRQn = -1, /!< 15 Cortex-M0 System Tick Interrupt /
emilmont	77:869cf507173a	207
emilmont	77:869cf507173a	208	#if defined (STM32F051)
emilmont	77:869cf507173a	209	/**** STM32F051 specific Interrupt Numbers ***********************************/
emilmont	77:869cf507173a	210	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
emilmont	77:869cf507173a	211	PVD_IRQn = 1, /!< PVD through EXTI Line detect Interrupt /
emilmont	77:869cf507173a	212	RTC_IRQn = 2, /!< RTC through EXTI Line Interrupt /
emilmont	77:869cf507173a	213	FLASH_IRQn = 3, /!< FLASH Interrupt /
emilmont	77:869cf507173a	214	RCC_IRQn = 4, /!< RCC Interrupt /
emilmont	77:869cf507173a	215	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
emilmont	77:869cf507173a	216	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
emilmont	77:869cf507173a	217	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
emilmont	77:869cf507173a	218	TS_IRQn = 8, /!< Touch sense controller Interrupt /
emilmont	77:869cf507173a	219	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
emilmont	77:869cf507173a	220	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
emilmont	77:869cf507173a	221	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
emilmont	77:869cf507173a	222	ADC1_COMP_IRQn = 12, /!< ADC1, COMP1 and COMP2 Interrupts /
emilmont	77:869cf507173a	223	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
emilmont	77:869cf507173a	224	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
emilmont	77:869cf507173a	225	TIM2_IRQn = 15, /!< TIM2 Interrupt /
emilmont	77:869cf507173a	226	TIM3_IRQn = 16, /!< TIM3 Interrupt /
emilmont	77:869cf507173a	227	TIM6_DAC_IRQn = 17, /!< TIM6 and DAC Interrupts /
emilmont	77:869cf507173a	228	TIM14_IRQn = 19, /!< TIM14 Interrupt /
emilmont	77:869cf507173a	229	TIM15_IRQn = 20, /!< TIM15 Interrupt /
emilmont	77:869cf507173a	230	TIM16_IRQn = 21, /!< TIM16 Interrupt /
emilmont	77:869cf507173a	231	TIM17_IRQn = 22, /!< TIM17 Interrupt /
emilmont	77:869cf507173a	232	I2C1_IRQn = 23, /!< I2C1 Interrupt /
emilmont	77:869cf507173a	233	I2C2_IRQn = 24, /!< I2C2 Interrupt /
emilmont	77:869cf507173a	234	SPI1_IRQn = 25, /!< SPI1 Interrupt /
emilmont	77:869cf507173a	235	SPI2_IRQn = 26, /!< SPI2 Interrupt /
emilmont	77:869cf507173a	236	USART1_IRQn = 27, /!< USART1 Interrupt /
emilmont	77:869cf507173a	237	USART2_IRQn = 28, /!< USART2 Interrupt /
emilmont	77:869cf507173a	238	CEC_IRQn = 30 /!< CEC Interrupt /
emilmont	77:869cf507173a	239	#elif defined (STM32F031)
emilmont	77:869cf507173a	240	/**** STM32F031 specific Interrupt Numbers ***********************************/
emilmont	77:869cf507173a	241	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
emilmont	77:869cf507173a	242	PVD_IRQn = 1, /!< PVD through EXTI Line detect Interrupt /
emilmont	77:869cf507173a	243	RTC_IRQn = 2, /!< RTC through EXTI Line Interrupt /
emilmont	77:869cf507173a	244	FLASH_IRQn = 3, /!< FLASH Interrupt /
emilmont	77:869cf507173a	245	RCC_IRQn = 4, /!< RCC Interrupt /
emilmont	77:869cf507173a	246	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
emilmont	77:869cf507173a	247	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
emilmont	77:869cf507173a	248	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
emilmont	77:869cf507173a	249	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
emilmont	77:869cf507173a	250	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
emilmont	77:869cf507173a	251	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
emilmont	77:869cf507173a	252	ADC1_IRQn = 12, /!< ADC1 Interrupt /
emilmont	77:869cf507173a	253	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
emilmont	77:869cf507173a	254	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
emilmont	77:869cf507173a	255	TIM2_IRQn = 15, /!< TIM2 Interrupt /
emilmont	77:869cf507173a	256	TIM3_IRQn = 16, /!< TIM3 Interrupt /
emilmont	77:869cf507173a	257	TIM14_IRQn = 19, /!< TIM14 Interrupt /
emilmont	77:869cf507173a	258	TIM16_IRQn = 21, /!< TIM16 Interrupt /
emilmont	77:869cf507173a	259	TIM17_IRQn = 22, /!< TIM17 Interrupt /
emilmont	77:869cf507173a	260	I2C1_IRQn = 23, /!< I2C1 Interrupt /
emilmont	77:869cf507173a	261	SPI1_IRQn = 25, /!< SPI1 Interrupt /
emilmont	77:869cf507173a	262	USART1_IRQn = 27 /!< USART1 Interrupt /
emilmont	77:869cf507173a	263	#elif defined (STM32F030)
emilmont	77:869cf507173a	264	/**** STM32F030 specific Interrupt Numbers ***********************************/
emilmont	77:869cf507173a	265	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
emilmont	77:869cf507173a	266	RTC_IRQn = 2, /!< RTC through EXTI Line Interrupt /
emilmont	77:869cf507173a	267	FLASH_IRQn = 3, /!< FLASH Interrupt /
emilmont	77:869cf507173a	268	RCC_IRQn = 4, /!< RCC Interrupt /
emilmont	77:869cf507173a	269	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
emilmont	77:869cf507173a	270	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
emilmont	77:869cf507173a	271	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
emilmont	77:869cf507173a	272	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
emilmont	77:869cf507173a	273	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
emilmont	77:869cf507173a	274	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4 and Channel 5 Interrupts /
emilmont	77:869cf507173a	275	ADC1_IRQn = 12, /!< ADC1 Interrupt /
emilmont	77:869cf507173a	276	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
emilmont	77:869cf507173a	277	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
emilmont	77:869cf507173a	278	TIM3_IRQn = 16, /!< TIM3 Interrupt /
emilmont	77:869cf507173a	279	TIM14_IRQn = 19, /!< TIM14 Interrupt /
emilmont	77:869cf507173a	280	TIM15_IRQn = 20, /!< TIM15 Interrupt /
emilmont	77:869cf507173a	281	TIM16_IRQn = 21, /!< TIM16 Interrupt /
emilmont	77:869cf507173a	282	TIM17_IRQn = 22, /!< TIM17 Interrupt /
emilmont	77:869cf507173a	283	I2C1_IRQn = 23, /!< I2C1 Interrupt /
emilmont	77:869cf507173a	284	I2C2_IRQn = 24, /!< I2C2 Interrupt /
emilmont	77:869cf507173a	285	SPI1_IRQn = 25, /!< SPI1 Interrupt /
emilmont	77:869cf507173a	286	SPI2_IRQn = 26, /!< SPI2 Interrupt /
emilmont	77:869cf507173a	287	USART1_IRQn = 27, /!< USART1 Interrupt /
emilmont	77:869cf507173a	288	USART2_IRQn = 28 /!< USART2 Interrupt /
emilmont	77:869cf507173a	289	#elif defined (STM32F072)
emilmont	77:869cf507173a	290	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
emilmont	77:869cf507173a	291	PVD_VDDIO2_IRQn = 1, /!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt /
emilmont	77:869cf507173a	292	RTC_IRQn = 2, /!< RTC through EXTI Line Interrupt /
emilmont	77:869cf507173a	293	FLASH_IRQn = 3, /!< FLASH Interrupt /
emilmont	77:869cf507173a	294	RCC_CRS_IRQn = 4, /!< RCC and CRS Interrupts /
emilmont	77:869cf507173a	295	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
emilmont	77:869cf507173a	296	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
emilmont	77:869cf507173a	297	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
emilmont	77:869cf507173a	298	TSC_IRQn = 8, /!< TSC Interrupt /
emilmont	77:869cf507173a	299	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
emilmont	77:869cf507173a	300	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
emilmont	77:869cf507173a	301	DMA1_Channel4_5_6_7_IRQn = 11, /!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts /
emilmont	77:869cf507173a	302	ADC1_COMP_IRQn = 12, /!< ADC1, COMP1 and COMP2 Interrupts /
emilmont	77:869cf507173a	303	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
emilmont	77:869cf507173a	304	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
emilmont	77:869cf507173a	305	TIM2_IRQn = 15, /!< TIM2 Interrupt /
emilmont	77:869cf507173a	306	TIM3_IRQn = 16, /!< TIM3 Interrupt /
emilmont	77:869cf507173a	307	TIM6_DAC_IRQn = 17, /!< TIM6 and DAC Interrupts /
emilmont	77:869cf507173a	308	TIM7_IRQn = 18, /!< TIM7 Interrupts /
emilmont	77:869cf507173a	309	TIM14_IRQn = 19, /!< TIM14 Interrupt /
emilmont	77:869cf507173a	310	TIM15_IRQn = 20, /!< TIM15 Interrupt /
emilmont	77:869cf507173a	311	TIM16_IRQn = 21, /!< TIM16 Interrupt /
emilmont	77:869cf507173a	312	TIM17_IRQn = 22, /!< TIM17 Interrupt /
emilmont	77:869cf507173a	313	I2C1_IRQn = 23, /!< I2C1 Interrupt /
emilmont	77:869cf507173a	314	I2C2_IRQn = 24, /!< I2C2 Interrupt /
emilmont	77:869cf507173a	315	SPI1_IRQn = 25, /!< SPI1 Interrupt /
emilmont	77:869cf507173a	316	SPI2_IRQn = 26, /!< SPI2 Interrupt /
emilmont	77:869cf507173a	317	USART1_IRQn = 27, /!< USART1 Interrupt /
emilmont	77:869cf507173a	318	USART2_IRQn = 28, /!< USART2 Interrupt /
emilmont	77:869cf507173a	319	USART3_4_IRQn = 29, /!< USART3 and USART4 Interrupts /
emilmont	77:869cf507173a	320	CEC_CAN_IRQn = 30, /!< CEC and CAN Interrupts /
emilmont	77:869cf507173a	321	USB_IRQn = 31 /!< USB Low Priority global Interrupt /
emilmont	77:869cf507173a	322	#elif defined (STM32F042)
emilmont	77:869cf507173a	323	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
emilmont	77:869cf507173a	324	PVD_VDDIO2_IRQn = 1, /!< PVD and VDDIO2 supply comparator through EXTI Line detect Interrupt /
emilmont	77:869cf507173a	325	RTC_IRQn = 2, /!< RTC through EXTI Line Interrupt /
emilmont	77:869cf507173a	326	FLASH_IRQn = 3, /!< FLASH Interrupt /
emilmont	77:869cf507173a	327	RCC_CRS_IRQn = 4, /!< RCC and CRS Interrupts /
emilmont	77:869cf507173a	328	EXTI0_1_IRQn = 5, /!< EXTI Line 0 and 1 Interrupts /
emilmont	77:869cf507173a	329	EXTI2_3_IRQn = 6, /!< EXTI Line 2 and 3 Interrupts /
emilmont	77:869cf507173a	330	EXTI4_15_IRQn = 7, /!< EXTI Line 4 to 15 Interrupts /
emilmont	77:869cf507173a	331	TSC_IRQn = 8, /!< TSC Interrupt /
emilmont	77:869cf507173a	332	DMA1_Channel1_IRQn = 9, /!< DMA1 Channel 1 Interrupt /
emilmont	77:869cf507173a	333	DMA1_Channel2_3_IRQn = 10, /!< DMA1 Channel 2 and Channel 3 Interrupts /
emilmont	77:869cf507173a	334	DMA1_Channel4_5_IRQn = 11, /!< DMA1 Channel 4, Channel 5 Interrupts /
emilmont	77:869cf507173a	335	ADC1_IRQn = 12, /!< ADC1 Interrupts /
emilmont	77:869cf507173a	336	TIM1_BRK_UP_TRG_COM_IRQn = 13, /!< TIM1 Break, Update, Trigger and Commutation Interrupts /
emilmont	77:869cf507173a	337	TIM1_CC_IRQn = 14, /!< TIM1 Capture Compare Interrupt /
emilmont	77:869cf507173a	338	TIM2_IRQn = 15, /!< TIM2 Interrupt /
emilmont	77:869cf507173a	339	TIM3_IRQn = 16, /!< TIM3 Interrupt /
emilmont	77:869cf507173a	340	TIM14_IRQn = 19, /!< TIM14 Interrupt /
emilmont	77:869cf507173a	341	TIM16_IRQn = 21, /!< TIM16 Interrupt /
emilmont	77:869cf507173a	342	TIM17_IRQn = 22, /!< TIM17 Interrupt /
emilmont	77:869cf507173a	343	I2C1_IRQn = 23, /!< I2C1 Interrupt /
emilmont	77:869cf507173a	344	SPI1_IRQn = 25, /!< SPI1 Interrupt /
emilmont	77:869cf507173a	345	SPI2_IRQn = 26, /!< SPI2 Interrupt /
emilmont	77:869cf507173a	346	USART1_IRQn = 27, /!< USART1 Interrupt /
emilmont	77:869cf507173a	347	USART2_IRQn = 28, /!< USART2 Interrupt /
emilmont	77:869cf507173a	348	CEC_CAN_IRQn = 30, /!< CEC and CAN Interrupts /
emilmont	77:869cf507173a	349	USB_IRQn = 31 /!< USB Low Priority global Interrupt /
emilmont	77:869cf507173a	350	#endif /* STM32F051 */
emilmont	77:869cf507173a	351	} IRQn_Type;
emilmont	77:869cf507173a	352
emilmont	77:869cf507173a	353	/**
emilmont	77:869cf507173a	354	* @}
emilmont	77:869cf507173a	355	*/
emilmont	77:869cf507173a	356
emilmont	77:869cf507173a	357	#include "core_cm0.h"
emilmont	77:869cf507173a	358	#include "system_stm32f0xx.h"
emilmont	77:869cf507173a	359	#include <stdint.h>
emilmont	77:869cf507173a	360
emilmont	77:869cf507173a	361	/** @addtogroup Exported_types
emilmont	77:869cf507173a	362	* @{
emilmont	77:869cf507173a	363	*/
emilmont	77:869cf507173a	364
emilmont	77:869cf507173a	365	typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
emilmont	77:869cf507173a	366
emilmont	77:869cf507173a	367	typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
emilmont	77:869cf507173a	368	#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) \|\| ((STATE) == ENABLE))
emilmont	77:869cf507173a	369
emilmont	77:869cf507173a	370	typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
emilmont	77:869cf507173a	371
emilmont	77:869cf507173a	372	/** @addtogroup Peripheral_registers_structures
emilmont	77:869cf507173a	373	* @{
emilmont	77:869cf507173a	374	*/
emilmont	77:869cf507173a	375
emilmont	77:869cf507173a	376	/**
emilmont	77:869cf507173a	377	* @brief Analog to Digital Converter
emilmont	77:869cf507173a	378	*/
emilmont	77:869cf507173a	379
emilmont	77:869cf507173a	380	typedef struct
emilmont	77:869cf507173a	381	{
emilmont	77:869cf507173a	382	__IO uint32_t ISR; /!< ADC Interrupt and Status register, Address offset:0x00 /
emilmont	77:869cf507173a	383	__IO uint32_t IER; /!< ADC Interrupt Enable register, Address offset:0x04 /
emilmont	77:869cf507173a	384	__IO uint32_t CR; /!< ADC Control register, Address offset:0x08 /
emilmont	77:869cf507173a	385	__IO uint32_t CFGR1; /!< ADC Configuration register 1, Address offset:0x0C /
emilmont	77:869cf507173a	386	__IO uint32_t CFGR2; /!< ADC Configuration register 2, Address offset:0x10 /
emilmont	77:869cf507173a	387	__IO uint32_t SMPR; /!< ADC Sampling time register, Address offset:0x14 /
emilmont	77:869cf507173a	388	uint32_t RESERVED1; /!< Reserved, 0x18 /
emilmont	77:869cf507173a	389	uint32_t RESERVED2; /!< Reserved, 0x1C /
emilmont	77:869cf507173a	390	__IO uint32_t TR; /!< ADC watchdog threshold register, Address offset:0x20 /
emilmont	77:869cf507173a	391	uint32_t RESERVED3; /!< Reserved, 0x24 /
emilmont	77:869cf507173a	392	__IO uint32_t CHSELR; /!< ADC channel selection register, Address offset:0x28 /
emilmont	77:869cf507173a	393	uint32_t RESERVED4[5]; /!< Reserved, 0x2C /
emilmont	77:869cf507173a	394	__IO uint32_t DR; /!< ADC data register, Address offset:0x40 /
emilmont	77:869cf507173a	395	} ADC_TypeDef;
emilmont	77:869cf507173a	396
emilmont	77:869cf507173a	397	typedef struct
emilmont	77:869cf507173a	398	{
emilmont	77:869cf507173a	399	__IO uint32_t CCR;
emilmont	77:869cf507173a	400	} ADC_Common_TypeDef;
emilmont	77:869cf507173a	401
emilmont	77:869cf507173a	402
emilmont	77:869cf507173a	403	/**
emilmont	77:869cf507173a	404	* @brief Controller Area Network TxMailBox
emilmont	77:869cf507173a	405	*/
emilmont	77:869cf507173a	406	typedef struct
emilmont	77:869cf507173a	407	{
emilmont	77:869cf507173a	408	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
emilmont	77:869cf507173a	409	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
emilmont	77:869cf507173a	410	__IO uint32_t TDLR; /!< CAN mailbox data low register /
emilmont	77:869cf507173a	411	__IO uint32_t TDHR; /!< CAN mailbox data high register /
emilmont	77:869cf507173a	412	} CAN_TxMailBox_TypeDef;
emilmont	77:869cf507173a	413
emilmont	77:869cf507173a	414	/**
emilmont	77:869cf507173a	415	* @brief Controller Area Network FIFOMailBox
emilmont	77:869cf507173a	416	*/
emilmont	77:869cf507173a	417	typedef struct
emilmont	77:869cf507173a	418	{
emilmont	77:869cf507173a	419	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
emilmont	77:869cf507173a	420	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
emilmont	77:869cf507173a	421	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
emilmont	77:869cf507173a	422	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
emilmont	77:869cf507173a	423	} CAN_FIFOMailBox_TypeDef;
emilmont	77:869cf507173a	424
emilmont	77:869cf507173a	425	/**
emilmont	77:869cf507173a	426	* @brief Controller Area Network FilterRegister
emilmont	77:869cf507173a	427	*/
emilmont	77:869cf507173a	428	typedef struct
emilmont	77:869cf507173a	429	{
emilmont	77:869cf507173a	430	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
emilmont	77:869cf507173a	431	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
emilmont	77:869cf507173a	432	} CAN_FilterRegister_TypeDef;
emilmont	77:869cf507173a	433
emilmont	77:869cf507173a	434	/**
emilmont	77:869cf507173a	435	* @brief Controller Area Network
emilmont	77:869cf507173a	436	*/
emilmont	77:869cf507173a	437	typedef struct
emilmont	77:869cf507173a	438	{
emilmont	77:869cf507173a	439	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
emilmont	77:869cf507173a	440	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
emilmont	77:869cf507173a	441	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
emilmont	77:869cf507173a	442	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
emilmont	77:869cf507173a	443	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
emilmont	77:869cf507173a	444	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
emilmont	77:869cf507173a	445	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
emilmont	77:869cf507173a	446	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
emilmont	77:869cf507173a	447	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
emilmont	77:869cf507173a	448	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
emilmont	77:869cf507173a	449	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
emilmont	77:869cf507173a	450	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
emilmont	77:869cf507173a	451	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
emilmont	77:869cf507173a	452	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
emilmont	77:869cf507173a	453	uint32_t RESERVED2; /!< Reserved, 0x208 /
emilmont	77:869cf507173a	454	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
emilmont	77:869cf507173a	455	uint32_t RESERVED3; /!< Reserved, 0x210 /
emilmont	77:869cf507173a	456	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
emilmont	77:869cf507173a	457	uint32_t RESERVED4; /!< Reserved, 0x218 /
emilmont	77:869cf507173a	458	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
emilmont	77:869cf507173a	459	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
emilmont	77:869cf507173a	460	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
emilmont	77:869cf507173a	461	} CAN_TypeDef;
emilmont	77:869cf507173a	462
emilmont	77:869cf507173a	463	/**
emilmont	77:869cf507173a	464	* @brief HDMI-CEC
emilmont	77:869cf507173a	465	*/
emilmont	77:869cf507173a	466
emilmont	77:869cf507173a	467	typedef struct
emilmont	77:869cf507173a	468	{
emilmont	77:869cf507173a	469	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
emilmont	77:869cf507173a	470	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
emilmont	77:869cf507173a	471	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
emilmont	77:869cf507173a	472	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
emilmont	77:869cf507173a	473	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
emilmont	77:869cf507173a	474	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
emilmont	77:869cf507173a	475	}CEC_TypeDef;
emilmont	77:869cf507173a	476
emilmont	77:869cf507173a	477	/**
emilmont	77:869cf507173a	478	* @brief Comparator
emilmont	77:869cf507173a	479	*/
emilmont	77:869cf507173a	480
emilmont	77:869cf507173a	481	typedef struct
emilmont	77:869cf507173a	482	{
emilmont	77:869cf507173a	483	__IO uint32_t CSR; /!< COMP comparator control and status register, Address offset: 0x1C /
emilmont	77:869cf507173a	484	} COMP_TypeDef;
emilmont	77:869cf507173a	485
emilmont	77:869cf507173a	486
emilmont	77:869cf507173a	487	/**
emilmont	77:869cf507173a	488	* @brief CRC calculation unit
emilmont	77:869cf507173a	489	*/
emilmont	77:869cf507173a	490
emilmont	77:869cf507173a	491	typedef struct
emilmont	77:869cf507173a	492	{
emilmont	77:869cf507173a	493	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
emilmont	77:869cf507173a	494	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
emilmont	77:869cf507173a	495	uint8_t RESERVED0; /!< Reserved, 0x05 /
emilmont	77:869cf507173a	496	uint16_t RESERVED1; /!< Reserved, 0x06 /
emilmont	77:869cf507173a	497	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
emilmont	77:869cf507173a	498	uint32_t RESERVED2; /!< Reserved, 0x0C /
emilmont	77:869cf507173a	499	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
emilmont	77:869cf507173a	500	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
emilmont	77:869cf507173a	501	} CRC_TypeDef;
emilmont	77:869cf507173a	502
emilmont	77:869cf507173a	503	/**
emilmont	77:869cf507173a	504	* @brief Clock Recovery System
emilmont	77:869cf507173a	505	*/
emilmont	77:869cf507173a	506	typedef struct
emilmont	77:869cf507173a	507	{
emilmont	77:869cf507173a	508	__IO uint32_t CR; /!< CRS ccontrol register, Address offset: 0x00 /
emilmont	77:869cf507173a	509	__IO uint32_t CFGR; /!< CRS configuration register, Address offset: 0x04 /
emilmont	77:869cf507173a	510	__IO uint32_t ISR; /!< CRS interrupt and status register, Address offset: 0x08 /
emilmont	77:869cf507173a	511	__IO uint32_t ICR; /!< CRS interrupt flag clear register, Address offset: 0x0C /
emilmont	77:869cf507173a	512	} CRS_TypeDef;
emilmont	77:869cf507173a	513
emilmont	77:869cf507173a	514	/**
emilmont	77:869cf507173a	515	* @brief Digital to Analog Converter
emilmont	77:869cf507173a	516	*/
emilmont	77:869cf507173a	517
emilmont	77:869cf507173a	518	typedef struct
emilmont	77:869cf507173a	519	{
emilmont	77:869cf507173a	520	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
emilmont	77:869cf507173a	521	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
emilmont	77:869cf507173a	522	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
emilmont	77:869cf507173a	523	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
emilmont	77:869cf507173a	524	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
emilmont	77:869cf507173a	525	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
emilmont	77:869cf507173a	526	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
emilmont	77:869cf507173a	527	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
emilmont	77:869cf507173a	528	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
emilmont	77:869cf507173a	529	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
emilmont	77:869cf507173a	530	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
emilmont	77:869cf507173a	531	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
emilmont	77:869cf507173a	532	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
emilmont	77:869cf507173a	533	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
emilmont	77:869cf507173a	534	} DAC_TypeDef;
emilmont	77:869cf507173a	535
emilmont	77:869cf507173a	536	/**
emilmont	77:869cf507173a	537	* @brief Debug MCU
emilmont	77:869cf507173a	538	*/
emilmont	77:869cf507173a	539
emilmont	77:869cf507173a	540	typedef struct
emilmont	77:869cf507173a	541	{
emilmont	77:869cf507173a	542	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
emilmont	77:869cf507173a	543	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
emilmont	77:869cf507173a	544	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
emilmont	77:869cf507173a	545	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
emilmont	77:869cf507173a	546	}DBGMCU_TypeDef;
emilmont	77:869cf507173a	547
emilmont	77:869cf507173a	548	/**
emilmont	77:869cf507173a	549	* @brief DMA Controller
emilmont	77:869cf507173a	550	*/
emilmont	77:869cf507173a	551
emilmont	77:869cf507173a	552	typedef struct
emilmont	77:869cf507173a	553	{
emilmont	77:869cf507173a	554	__IO uint32_t CCR; /!< DMA channel x configuration register /
emilmont	77:869cf507173a	555	__IO uint32_t CNDTR; /!< DMA channel x number of data register /
emilmont	77:869cf507173a	556	__IO uint32_t CPAR; /!< DMA channel x peripheral address register /
emilmont	77:869cf507173a	557	__IO uint32_t CMAR; /!< DMA channel x memory address register /
emilmont	77:869cf507173a	558	} DMA_Channel_TypeDef;
emilmont	77:869cf507173a	559
emilmont	77:869cf507173a	560	typedef struct
emilmont	77:869cf507173a	561	{
emilmont	77:869cf507173a	562	__IO uint32_t ISR; /!< DMA interrupt status register, Address offset: 0x00 /
emilmont	77:869cf507173a	563	__IO uint32_t IFCR; /!< DMA interrupt flag clear register, Address offset: 0x04 /
emilmont	77:869cf507173a	564	} DMA_TypeDef;
emilmont	77:869cf507173a	565
emilmont	77:869cf507173a	566	/**
emilmont	77:869cf507173a	567	* @brief External Interrupt/Event Controller
emilmont	77:869cf507173a	568	*/
emilmont	77:869cf507173a	569
emilmont	77:869cf507173a	570	typedef struct
emilmont	77:869cf507173a	571	{
emilmont	77:869cf507173a	572	__IO uint32_t IMR; /!<EXTI Interrupt mask register, Address offset: 0x00 /
emilmont	77:869cf507173a	573	__IO uint32_t EMR; /!<EXTI Event mask register, Address offset: 0x04 /
emilmont	77:869cf507173a	574	__IO uint32_t RTSR; /!<EXTI Rising trigger selection register , Address offset: 0x08 /
emilmont	77:869cf507173a	575	__IO uint32_t FTSR; /!<EXTI Falling trigger selection register, Address offset: 0x0C /
emilmont	77:869cf507173a	576	__IO uint32_t SWIER; /!<EXTI Software interrupt event register, Address offset: 0x10 /
emilmont	77:869cf507173a	577	__IO uint32_t PR; /!<EXTI Pending register, Address offset: 0x14 /
emilmont	77:869cf507173a	578	}EXTI_TypeDef;
emilmont	77:869cf507173a	579
emilmont	77:869cf507173a	580	/**
emilmont	77:869cf507173a	581	* @brief FLASH Registers
emilmont	77:869cf507173a	582	*/
emilmont	77:869cf507173a	583	typedef struct
emilmont	77:869cf507173a	584	{
emilmont	77:869cf507173a	585	__IO uint32_t ACR; /!<FLASH access control register, Address offset: 0x00 /
emilmont	77:869cf507173a	586	__IO uint32_t KEYR; /!<FLASH key register, Address offset: 0x04 /
emilmont	77:869cf507173a	587	__IO uint32_t OPTKEYR; /!<FLASH OPT key register, Address offset: 0x08 /
emilmont	77:869cf507173a	588	__IO uint32_t SR; /!<FLASH status register, Address offset: 0x0C /
emilmont	77:869cf507173a	589	__IO uint32_t CR; /!<FLASH control register, Address offset: 0x10 /
emilmont	77:869cf507173a	590	__IO uint32_t AR; /!<FLASH address register, Address offset: 0x14 /
emilmont	77:869cf507173a	591	__IO uint32_t RESERVED; /!< Reserved, 0x18 /
emilmont	77:869cf507173a	592	__IO uint32_t OBR; /!<FLASH option bytes register, Address offset: 0x1C /
emilmont	77:869cf507173a	593	__IO uint32_t WRPR; /!<FLASH option bytes register, Address offset: 0x20 /
emilmont	77:869cf507173a	594	} FLASH_TypeDef;
emilmont	77:869cf507173a	595
emilmont	77:869cf507173a	596
emilmont	77:869cf507173a	597	/**
emilmont	77:869cf507173a	598	* @brief Option Bytes Registers
emilmont	77:869cf507173a	599	*/
emilmont	77:869cf507173a	600	typedef struct
emilmont	77:869cf507173a	601	{
emilmont	77:869cf507173a	602	__IO uint16_t RDP; /!< FLASH option byte Read protection, Address offset: 0x00 /
emilmont	77:869cf507173a	603	__IO uint16_t USER; /!< FLASH option byte user options, Address offset: 0x02 /
emilmont	77:869cf507173a	604	__IO uint16_t DATA0; /!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 /
emilmont	77:869cf507173a	605	__IO uint16_t DATA1; /!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 /
emilmont	77:869cf507173a	606	__IO uint16_t WRP0; /!< FLASH option byte write protection 0, Address offset: 0x08 /
emilmont	77:869cf507173a	607	__IO uint16_t WRP1; /!< FLASH option byte write protection 1, Address offset: 0x0A /
emilmont	77:869cf507173a	608	__IO uint16_t WRP2; /!< FLASH option byte write protection 2, Address offset: 0x0C /
emilmont	77:869cf507173a	609	__IO uint16_t WRP3; /!< FLASH option byte write protection 3, Address offset: 0x0E /
emilmont	77:869cf507173a	610	} OB_TypeDef;
emilmont	77:869cf507173a	611
emilmont	77:869cf507173a	612
emilmont	77:869cf507173a	613	/**
emilmont	77:869cf507173a	614	* @brief General Purpose IO
emilmont	77:869cf507173a	615	*/
emilmont	77:869cf507173a	616
emilmont	77:869cf507173a	617	typedef struct
emilmont	77:869cf507173a	618	{
emilmont	77:869cf507173a	619	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
emilmont	77:869cf507173a	620	__IO uint16_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
emilmont	77:869cf507173a	621	uint16_t RESERVED0; /!< Reserved, 0x06 /
emilmont	77:869cf507173a	622	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
emilmont	77:869cf507173a	623	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
emilmont	77:869cf507173a	624	__IO uint16_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
emilmont	77:869cf507173a	625	uint16_t RESERVED1; /!< Reserved, 0x12 /
emilmont	77:869cf507173a	626	__IO uint16_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
emilmont	77:869cf507173a	627	uint16_t RESERVED2; /!< Reserved, 0x16 /
emilmont	77:869cf507173a	628	__IO uint32_t BSRR; /!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 /
emilmont	77:869cf507173a	629	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
emilmont	77:869cf507173a	630	__IO uint32_t AFR[2]; /!< GPIO alternate function low register, Address offset: 0x20-0x24 /
emilmont	77:869cf507173a	631	__IO uint16_t BRR; /!< GPIO bit reset register, Address offset: 0x28 /
emilmont	77:869cf507173a	632	uint16_t RESERVED3; /!< Reserved, 0x2A /
emilmont	77:869cf507173a	633	}GPIO_TypeDef;
emilmont	77:869cf507173a	634
emilmont	77:869cf507173a	635	/**
emilmont	77:869cf507173a	636	* @brief SysTem Configuration
emilmont	77:869cf507173a	637	*/
emilmont	77:869cf507173a	638
emilmont	77:869cf507173a	639	typedef struct
emilmont	77:869cf507173a	640	{
emilmont	77:869cf507173a	641	__IO uint32_t CFGR1; /!< SYSCFG configuration register 1, Address offset: 0x00 /
emilmont	77:869cf507173a	642	uint32_t RESERVED; /!< Reserved, 0x04 /
emilmont	77:869cf507173a	643	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 /
emilmont	77:869cf507173a	644	__IO uint32_t CFGR2; /!< SYSCFG configuration register 2, Address offset: 0x18 /
emilmont	77:869cf507173a	645	} SYSCFG_TypeDef;
emilmont	77:869cf507173a	646
emilmont	77:869cf507173a	647	/**
emilmont	77:869cf507173a	648	* @brief Inter-integrated Circuit Interface
emilmont	77:869cf507173a	649	*/
emilmont	77:869cf507173a	650
emilmont	77:869cf507173a	651	typedef struct
emilmont	77:869cf507173a	652	{
emilmont	77:869cf507173a	653	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
emilmont	77:869cf507173a	654	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
emilmont	77:869cf507173a	655	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
emilmont	77:869cf507173a	656	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
emilmont	77:869cf507173a	657	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
emilmont	77:869cf507173a	658	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
emilmont	77:869cf507173a	659	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
emilmont	77:869cf507173a	660	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
emilmont	77:869cf507173a	661	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
emilmont	77:869cf507173a	662	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
emilmont	77:869cf507173a	663	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
emilmont	77:869cf507173a	664	}I2C_TypeDef;
emilmont	77:869cf507173a	665
emilmont	77:869cf507173a	666
emilmont	77:869cf507173a	667	/**
emilmont	77:869cf507173a	668	* @brief Independent WATCHDOG
emilmont	77:869cf507173a	669	*/
emilmont	77:869cf507173a	670	typedef struct
emilmont	77:869cf507173a	671	{
emilmont	77:869cf507173a	672	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
emilmont	77:869cf507173a	673	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
emilmont	77:869cf507173a	674	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
emilmont	77:869cf507173a	675	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
emilmont	77:869cf507173a	676	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
emilmont	77:869cf507173a	677	} IWDG_TypeDef;
emilmont	77:869cf507173a	678
emilmont	77:869cf507173a	679	/**
emilmont	77:869cf507173a	680	* @brief Power Control
emilmont	77:869cf507173a	681	*/
emilmont	77:869cf507173a	682
emilmont	77:869cf507173a	683	typedef struct
emilmont	77:869cf507173a	684	{
emilmont	77:869cf507173a	685	__IO uint32_t CR; /!< PWR power control register, Address offset: 0x00 /
emilmont	77:869cf507173a	686	__IO uint32_t CSR; /!< PWR power control/status register, Address offset: 0x04 /
emilmont	77:869cf507173a	687	} PWR_TypeDef;
emilmont	77:869cf507173a	688
emilmont	77:869cf507173a	689
emilmont	77:869cf507173a	690	/**
emilmont	77:869cf507173a	691	* @brief Reset and Clock Control
emilmont	77:869cf507173a	692	*/
emilmont	77:869cf507173a	693	typedef struct
emilmont	77:869cf507173a	694	{
emilmont	77:869cf507173a	695	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
emilmont	77:869cf507173a	696	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x04 /
emilmont	77:869cf507173a	697	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x08 /
emilmont	77:869cf507173a	698	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x0C /
emilmont	77:869cf507173a	699	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x10 /
emilmont	77:869cf507173a	700	__IO uint32_t AHBENR; /!< RCC AHB peripheral clock register, Address offset: 0x14 /
emilmont	77:869cf507173a	701	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x18 /
emilmont	77:869cf507173a	702	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x1C /
emilmont	77:869cf507173a	703	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x20 /
emilmont	77:869cf507173a	704	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x24 /
emilmont	77:869cf507173a	705	__IO uint32_t AHBRSTR; /!< RCC AHB peripheral reset register, Address offset: 0x28 /
emilmont	77:869cf507173a	706	__IO uint32_t CFGR2; /!< RCC clock configuration register 2, Address offset: 0x2C /
emilmont	77:869cf507173a	707	__IO uint32_t CFGR3; /!< RCC clock configuration register 3, Address offset: 0x30 /
emilmont	77:869cf507173a	708	__IO uint32_t CR2; /!< RCC clock control register 2, Address offset: 0x34 /
emilmont	77:869cf507173a	709	} RCC_TypeDef;
emilmont	77:869cf507173a	710
emilmont	77:869cf507173a	711	/**
emilmont	77:869cf507173a	712	* @brief Real-Time Clock
emilmont	77:869cf507173a	713	*/
emilmont	77:869cf507173a	714
emilmont	77:869cf507173a	715	typedef struct
emilmont	77:869cf507173a	716	{
emilmont	77:869cf507173a	717	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
emilmont	77:869cf507173a	718	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
emilmont	77:869cf507173a	719	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
emilmont	77:869cf507173a	720	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
emilmont	77:869cf507173a	721	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
emilmont	77:869cf507173a	722	__IO uint32_t WUTR; /!< RTC wakeup timer register,(only for STM32F072 devices) Address offset: 0x14 /
emilmont	77:869cf507173a	723	uint32_t RESERVED1; /!< Reserved, Address offset: 0x18 /
emilmont	77:869cf507173a	724	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
emilmont	77:869cf507173a	725	uint32_t RESERVED2; /!< Reserved, Address offset: 0x20 /
emilmont	77:869cf507173a	726	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
emilmont	77:869cf507173a	727	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
emilmont	77:869cf507173a	728	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
emilmont	77:869cf507173a	729	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
emilmont	77:869cf507173a	730	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
emilmont	77:869cf507173a	731	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
emilmont	77:869cf507173a	732	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
emilmont	77:869cf507173a	733	__IO uint32_t TAFCR; /!< RTC tamper and alternate function configuration register, Address offset: 0x40 /
emilmont	77:869cf507173a	734	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
emilmont	77:869cf507173a	735	uint32_t RESERVED3; /!< Reserved, Address offset: 0x48 /
emilmont	77:869cf507173a	736	uint32_t RESERVED4; /!< Reserved, Address offset: 0x4C /
emilmont	77:869cf507173a	737	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
emilmont	77:869cf507173a	738	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
emilmont	77:869cf507173a	739	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
emilmont	77:869cf507173a	740	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
emilmont	77:869cf507173a	741	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
emilmont	77:869cf507173a	742	} RTC_TypeDef;
emilmont	77:869cf507173a	743
emilmont	77:869cf507173a	744	/* Old register name definition maintained for legacy purpose */
emilmont	77:869cf507173a	745	#define CAL CALR
emilmont	77:869cf507173a	746
emilmont	77:869cf507173a	747	/**
emilmont	77:869cf507173a	748	* @brief Serial Peripheral Interface
emilmont	77:869cf507173a	749	*/
emilmont	77:869cf507173a	750
emilmont	77:869cf507173a	751	typedef struct
emilmont	77:869cf507173a	752	{
emilmont	77:869cf507173a	753	__IO uint16_t CR1; /!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 /
emilmont	77:869cf507173a	754	uint16_t RESERVED0; /!< Reserved, 0x02 /
emilmont	77:869cf507173a	755	__IO uint16_t CR2; /!< SPI Control register 2, Address offset: 0x04 /
emilmont	77:869cf507173a	756	uint16_t RESERVED1; /!< Reserved, 0x06 /
emilmont	77:869cf507173a	757	__IO uint16_t SR; /!< SPI Status register, Address offset: 0x08 /
emilmont	77:869cf507173a	758	uint16_t RESERVED2; /!< Reserved, 0x0A /
emilmont	77:869cf507173a	759	__IO uint16_t DR; /!< SPI data register, Address offset: 0x0C /
emilmont	77:869cf507173a	760	uint16_t RESERVED3; /!< Reserved, 0x0E /
emilmont	77:869cf507173a	761	__IO uint16_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
emilmont	77:869cf507173a	762	uint16_t RESERVED4; /!< Reserved, 0x12 /
emilmont	77:869cf507173a	763	__IO uint16_t RXCRCR; /!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 /
emilmont	77:869cf507173a	764	uint16_t RESERVED5; /!< Reserved, 0x16 /
emilmont	77:869cf507173a	765	__IO uint16_t TXCRCR; /!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 /
emilmont	77:869cf507173a	766	uint16_t RESERVED6; /!< Reserved, 0x1A /
emilmont	77:869cf507173a	767	__IO uint16_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
emilmont	77:869cf507173a	768	uint16_t RESERVED7; /!< Reserved, 0x1E /
emilmont	77:869cf507173a	769	__IO uint16_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
emilmont	77:869cf507173a	770	uint16_t RESERVED8; /!< Reserved, 0x22 /
emilmont	77:869cf507173a	771	} SPI_TypeDef;
emilmont	77:869cf507173a	772
emilmont	77:869cf507173a	773
emilmont	77:869cf507173a	774	/**
emilmont	77:869cf507173a	775	* @brief TIM
emilmont	77:869cf507173a	776	*/
emilmont	77:869cf507173a	777	typedef struct
emilmont	77:869cf507173a	778	{
emilmont	77:869cf507173a	779	__IO uint16_t CR1; /!< TIM control register 1, Address offset: 0x00 /
emilmont	77:869cf507173a	780	uint16_t RESERVED0; /!< Reserved, 0x02 /
emilmont	77:869cf507173a	781	__IO uint16_t CR2; /!< TIM control register 2, Address offset: 0x04 /
emilmont	77:869cf507173a	782	uint16_t RESERVED1; /!< Reserved, 0x06 /
emilmont	77:869cf507173a	783	__IO uint16_t SMCR; /!< TIM slave Mode Control register, Address offset: 0x08 /
emilmont	77:869cf507173a	784	uint16_t RESERVED2; /!< Reserved, 0x0A /
emilmont	77:869cf507173a	785	__IO uint16_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
emilmont	77:869cf507173a	786	uint16_t RESERVED3; /!< Reserved, 0x0E /
emilmont	77:869cf507173a	787	__IO uint16_t SR; /!< TIM status register, Address offset: 0x10 /
emilmont	77:869cf507173a	788	uint16_t RESERVED4; /!< Reserved, 0x12 /
emilmont	77:869cf507173a	789	__IO uint16_t EGR; /!< TIM event generation register, Address offset: 0x14 /
emilmont	77:869cf507173a	790	uint16_t RESERVED5; /!< Reserved, 0x16 /
emilmont	77:869cf507173a	791	__IO uint16_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
emilmont	77:869cf507173a	792	uint16_t RESERVED6; /!< Reserved, 0x1A /
emilmont	77:869cf507173a	793	__IO uint16_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
emilmont	77:869cf507173a	794	uint16_t RESERVED7; /!< Reserved, 0x1E /
emilmont	77:869cf507173a	795	__IO uint16_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
emilmont	77:869cf507173a	796	uint16_t RESERVED8; /!< Reserved, 0x22 /
emilmont	77:869cf507173a	797	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
emilmont	77:869cf507173a	798	__IO uint16_t PSC; /!< TIM prescaler register, Address offset: 0x28 /
emilmont	77:869cf507173a	799	uint16_t RESERVED10; /!< Reserved, 0x2A /
emilmont	77:869cf507173a	800	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
emilmont	77:869cf507173a	801	__IO uint16_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
emilmont	77:869cf507173a	802	uint16_t RESERVED12; /!< Reserved, 0x32 /
emilmont	77:869cf507173a	803	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
emilmont	77:869cf507173a	804	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
emilmont	77:869cf507173a	805	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
emilmont	77:869cf507173a	806	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
emilmont	77:869cf507173a	807	__IO uint16_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
emilmont	77:869cf507173a	808	uint16_t RESERVED17; /!< Reserved, 0x26 /
emilmont	77:869cf507173a	809	__IO uint16_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
emilmont	77:869cf507173a	810	uint16_t RESERVED18; /!< Reserved, 0x4A /
emilmont	77:869cf507173a	811	__IO uint16_t DMAR; /!< TIM DMA address for full transfer register, Address offset: 0x4C /
emilmont	77:869cf507173a	812	uint16_t RESERVED19; /!< Reserved, 0x4E /
emilmont	77:869cf507173a	813	__IO uint16_t OR; /!< TIM option register, Address offset: 0x50 /
emilmont	77:869cf507173a	814	uint16_t RESERVED20; /!< Reserved, 0x52 /
emilmont	77:869cf507173a	815	} TIM_TypeDef;
emilmont	77:869cf507173a	816
emilmont	77:869cf507173a	817	/**
emilmont	77:869cf507173a	818	* @brief Touch Sensing Controller (TSC)
emilmont	77:869cf507173a	819	*/
emilmont	77:869cf507173a	820	typedef struct
emilmont	77:869cf507173a	821	{
emilmont	77:869cf507173a	822	__IO uint32_t CR; /!< TSC control register, Address offset: 0x00 /
emilmont	77:869cf507173a	823	__IO uint32_t IER; /!< TSC interrupt enable register, Address offset: 0x04 /
emilmont	77:869cf507173a	824	__IO uint32_t ICR; /!< TSC interrupt clear register, Address offset: 0x08 /
emilmont	77:869cf507173a	825	__IO uint32_t ISR; /!< TSC interrupt status register, Address offset: 0x0C /
emilmont	77:869cf507173a	826	__IO uint32_t IOHCR; /!< TSC I/O hysteresis control register, Address offset: 0x10 /
emilmont	77:869cf507173a	827	__IO uint32_t RESERVED1; /!< Reserved, Address offset: 0x14 /
emilmont	77:869cf507173a	828	__IO uint32_t IOASCR; /!< TSC I/O analog switch control register, Address offset: 0x18 /
emilmont	77:869cf507173a	829	__IO uint32_t RESERVED2; /!< Reserved, Address offset: 0x1C /
emilmont	77:869cf507173a	830	__IO uint32_t IOSCR; /!< TSC I/O sampling control register, Address offset: 0x20 /
emilmont	77:869cf507173a	831	__IO uint32_t RESERVED3; /!< Reserved, Address offset: 0x24 /
emilmont	77:869cf507173a	832	__IO uint32_t IOCCR; /!< TSC I/O channel control register, Address offset: 0x28 /
emilmont	77:869cf507173a	833	__IO uint32_t RESERVED4; /!< Reserved, Address offset: 0x2C /
emilmont	77:869cf507173a	834	__IO uint32_t IOGCSR; /!< TSC I/O group control status register, Address offset: 0x30 /
emilmont	77:869cf507173a	835	__IO uint32_t IOGXCR[8]; /!< TSC I/O group x counter register, Address offset: 0x34-50 /
emilmont	77:869cf507173a	836	} TSC_TypeDef;
emilmont	77:869cf507173a	837
emilmont	77:869cf507173a	838	/**
emilmont	77:869cf507173a	839	* @brief Universal Synchronous Asynchronous Receiver Transmitter
emilmont	77:869cf507173a	840	*/
emilmont	77:869cf507173a	841
emilmont	77:869cf507173a	842	typedef struct
emilmont	77:869cf507173a	843	{
emilmont	77:869cf507173a	844	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
emilmont	77:869cf507173a	845	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
emilmont	77:869cf507173a	846	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
emilmont	77:869cf507173a	847	__IO uint16_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
emilmont	77:869cf507173a	848	uint16_t RESERVED1; /!< Reserved, 0x0E /
emilmont	77:869cf507173a	849	__IO uint16_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
emilmont	77:869cf507173a	850	uint16_t RESERVED2; /!< Reserved, 0x12 /
emilmont	77:869cf507173a	851	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
emilmont	77:869cf507173a	852	__IO uint16_t RQR; /!< USART Request register, Address offset: 0x18 /
emilmont	77:869cf507173a	853	uint16_t RESERVED3; /!< Reserved, 0x1A /
emilmont	77:869cf507173a	854	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
emilmont	77:869cf507173a	855	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
emilmont	77:869cf507173a	856	__IO uint16_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
emilmont	77:869cf507173a	857	uint16_t RESERVED4; /!< Reserved, 0x26 /
emilmont	77:869cf507173a	858	__IO uint16_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
emilmont	77:869cf507173a	859	uint16_t RESERVED5; /!< Reserved, 0x2A /
emilmont	77:869cf507173a	860	} USART_TypeDef;
emilmont	77:869cf507173a	861
emilmont	77:869cf507173a	862
emilmont	77:869cf507173a	863	/**
emilmont	77:869cf507173a	864	* @brief Window WATCHDOG
emilmont	77:869cf507173a	865	*/
emilmont	77:869cf507173a	866	typedef struct
emilmont	77:869cf507173a	867	{
emilmont	77:869cf507173a	868	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
emilmont	77:869cf507173a	869	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
emilmont	77:869cf507173a	870	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
emilmont	77:869cf507173a	871	} WWDG_TypeDef;
emilmont	77:869cf507173a	872
emilmont	77:869cf507173a	873
emilmont	77:869cf507173a	874	/**
emilmont	77:869cf507173a	875	* @}
emilmont	77:869cf507173a	876	*/
emilmont	77:869cf507173a	877
emilmont	77:869cf507173a	878	/** @addtogroup Peripheral_memory_map
emilmont	77:869cf507173a	879	* @{
emilmont	77:869cf507173a	880	*/
emilmont	77:869cf507173a	881
emilmont	77:869cf507173a	882	#define FLASH_BASE ((uint32_t)0x08000000) /!< FLASH base address in the alias region /
emilmont	77:869cf507173a	883	#define SRAM_BASE ((uint32_t)0x20000000) /!< SRAM base address in the alias region /
emilmont	77:869cf507173a	884	#define PERIPH_BASE ((uint32_t)0x40000000) /!< Peripheral base address in the alias region /
emilmont	77:869cf507173a	885
emilmont	77:869cf507173a	886	/!< Peripheral memory map /
emilmont	77:869cf507173a	887	#define APBPERIPH_BASE PERIPH_BASE
emilmont	77:869cf507173a	888	#define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
emilmont	77:869cf507173a	889	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
emilmont	77:869cf507173a	890
emilmont	77:869cf507173a	891	#define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
emilmont	77:869cf507173a	892	#define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
emilmont	77:869cf507173a	893	#define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
emilmont	77:869cf507173a	894	#define TIM7_BASE (APBPERIPH_BASE + 0x00001400)
emilmont	77:869cf507173a	895	#define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
emilmont	77:869cf507173a	896	#define RTC_BASE (APBPERIPH_BASE + 0x00002800)
emilmont	77:869cf507173a	897	#define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
emilmont	77:869cf507173a	898	#define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
emilmont	77:869cf507173a	899	#define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
emilmont	77:869cf507173a	900	#define USART2_BASE (APBPERIPH_BASE + 0x00004400)
emilmont	77:869cf507173a	901	#define USART3_BASE (APBPERIPH_BASE + 0x00004800)
emilmont	77:869cf507173a	902	#define USART4_BASE (APBPERIPH_BASE + 0x00004C00)
emilmont	77:869cf507173a	903	#define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
emilmont	77:869cf507173a	904	#define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
emilmont	77:869cf507173a	905	#define CAN_BASE (APBPERIPH_BASE + 0x00006400)
emilmont	77:869cf507173a	906	#define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
emilmont	77:869cf507173a	907	#define PWR_BASE (APBPERIPH_BASE + 0x00007000)
emilmont	77:869cf507173a	908	#define DAC_BASE (APBPERIPH_BASE + 0x00007400)
emilmont	77:869cf507173a	909	#define CEC_BASE (APBPERIPH_BASE + 0x00007800)
emilmont	77:869cf507173a	910
emilmont	77:869cf507173a	911	#define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
emilmont	77:869cf507173a	912	#define COMP_BASE (APBPERIPH_BASE + 0x0001001C)
emilmont	77:869cf507173a	913	#define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
emilmont	77:869cf507173a	914	#define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
emilmont	77:869cf507173a	915	#define ADC_BASE (APBPERIPH_BASE + 0x00012708)
emilmont	77:869cf507173a	916	#define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
emilmont	77:869cf507173a	917	#define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
emilmont	77:869cf507173a	918	#define USART1_BASE (APBPERIPH_BASE + 0x00013800)
emilmont	77:869cf507173a	919	#define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
emilmont	77:869cf507173a	920	#define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
emilmont	77:869cf507173a	921	#define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
emilmont	77:869cf507173a	922	#define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
emilmont	77:869cf507173a	923
emilmont	77:869cf507173a	924	#define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
emilmont	77:869cf507173a	925	#define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
emilmont	77:869cf507173a	926	#define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
emilmont	77:869cf507173a	927	#define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
emilmont	77:869cf507173a	928	#define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
emilmont	77:869cf507173a	929	#define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
emilmont	77:869cf507173a	930	#define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
emilmont	77:869cf507173a	931	#define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
emilmont	77:869cf507173a	932
emilmont	77:869cf507173a	933	#define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
emilmont	77:869cf507173a	934	#define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /!< FLASH registers base address /
emilmont	77:869cf507173a	935	#define OB_BASE ((uint32_t)0x1FFFF800) /!< FLASH Option Bytes base address /
emilmont	77:869cf507173a	936	#define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
emilmont	77:869cf507173a	937	#define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
emilmont	77:869cf507173a	938
emilmont	77:869cf507173a	939	#define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
emilmont	77:869cf507173a	940	#define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
emilmont	77:869cf507173a	941	#define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
emilmont	77:869cf507173a	942	#define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
emilmont	77:869cf507173a	943	#define GPIOE_BASE (AHB2PERIPH_BASE + 0x00001000)
emilmont	77:869cf507173a	944	#define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
emilmont	77:869cf507173a	945
emilmont	77:869cf507173a	946	/**
emilmont	77:869cf507173a	947	* @}
emilmont	77:869cf507173a	948	*/
emilmont	77:869cf507173a	949
emilmont	77:869cf507173a	950	/** @addtogroup Peripheral_declaration
emilmont	77:869cf507173a	951	* @{
emilmont	77:869cf507173a	952	*/
emilmont	77:869cf507173a	953
emilmont	77:869cf507173a	954	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
emilmont	77:869cf507173a	955	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
emilmont	77:869cf507173a	956	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
emilmont	77:869cf507173a	957	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
emilmont	77:869cf507173a	958	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
emilmont	77:869cf507173a	959	#define RTC ((RTC_TypeDef *) RTC_BASE)
emilmont	77:869cf507173a	960	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
emilmont	77:869cf507173a	961	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
emilmont	77:869cf507173a	962	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
emilmont	77:869cf507173a	963	#define USART2 ((USART_TypeDef *) USART2_BASE)
emilmont	77:869cf507173a	964	#define USART3 ((USART_TypeDef *) USART3_BASE)
emilmont	77:869cf507173a	965	#define USART4 ((USART_TypeDef *) USART4_BASE)
emilmont	77:869cf507173a	966	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
emilmont	77:869cf507173a	967	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
emilmont	77:869cf507173a	968	#define CAN ((CAN_TypeDef *) CAN_BASE)
emilmont	77:869cf507173a	969	#define CRS ((CRS_TypeDef *) CRS_BASE)
emilmont	77:869cf507173a	970	#define PWR ((PWR_TypeDef *) PWR_BASE)
emilmont	77:869cf507173a	971	#define DAC ((DAC_TypeDef *) DAC_BASE)
emilmont	77:869cf507173a	972	#define CEC ((CEC_TypeDef *) CEC_BASE)
emilmont	77:869cf507173a	973
emilmont	77:869cf507173a	974	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
emilmont	77:869cf507173a	975	#define COMP ((COMP_TypeDef *) COMP_BASE)
emilmont	77:869cf507173a	976	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
emilmont	77:869cf507173a	977	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
emilmont	77:869cf507173a	978	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
emilmont	77:869cf507173a	979	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
emilmont	77:869cf507173a	980	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
emilmont	77:869cf507173a	981	#define USART1 ((USART_TypeDef *) USART1_BASE)
emilmont	77:869cf507173a	982	#define TIM15 ((TIM_TypeDef *) TIM15_BASE)
emilmont	77:869cf507173a	983	#define TIM16 ((TIM_TypeDef *) TIM16_BASE)
emilmont	77:869cf507173a	984	#define TIM17 ((TIM_TypeDef *) TIM17_BASE)
emilmont	77:869cf507173a	985	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
emilmont	77:869cf507173a	986
emilmont	77:869cf507173a	987	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
emilmont	77:869cf507173a	988	#define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
emilmont	77:869cf507173a	989	#define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
emilmont	77:869cf507173a	990	#define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
emilmont	77:869cf507173a	991	#define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
emilmont	77:869cf507173a	992	#define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
emilmont	77:869cf507173a	993	#define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
emilmont	77:869cf507173a	994	#define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
emilmont	77:869cf507173a	995	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
emilmont	77:869cf507173a	996	#define OB ((OB_TypeDef *) OB_BASE)
emilmont	77:869cf507173a	997	#define RCC ((RCC_TypeDef *) RCC_BASE)
emilmont	77:869cf507173a	998	#define CRC ((CRC_TypeDef *) CRC_BASE)
emilmont	77:869cf507173a	999	#define TSC ((TSC_TypeDef *) TSC_BASE)
emilmont	77:869cf507173a	1000
emilmont	77:869cf507173a	1001	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
emilmont	77:869cf507173a	1002	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
emilmont	77:869cf507173a	1003	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
emilmont	77:869cf507173a	1004	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
emilmont	77:869cf507173a	1005	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
emilmont	77:869cf507173a	1006	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
emilmont	77:869cf507173a	1007
emilmont	77:869cf507173a	1008	/**
emilmont	77:869cf507173a	1009	* @}
emilmont	77:869cf507173a	1010	*/
emilmont	77:869cf507173a	1011
emilmont	77:869cf507173a	1012	/** @addtogroup Exported_constants
emilmont	77:869cf507173a	1013	* @{
emilmont	77:869cf507173a	1014	*/
emilmont	77:869cf507173a	1015
emilmont	77:869cf507173a	1016	/** @addtogroup Peripheral_Registers_Bits_Definition
emilmont	77:869cf507173a	1017	* @{
emilmont	77:869cf507173a	1018	*/
emilmont	77:869cf507173a	1019
emilmont	77:869cf507173a	1020	/******************************************************************************/
emilmont	77:869cf507173a	1021	/* Peripheral Registers Bits Definition */
emilmont	77:869cf507173a	1022	/******************************************************************************/
emilmont	77:869cf507173a	1023	/******************************************************************************/
emilmont	77:869cf507173a	1024	/* */
emilmont	77:869cf507173a	1025	/* Analog to Digital Converter (ADC) */
emilmont	77:869cf507173a	1026	/* */
emilmont	77:869cf507173a	1027	/******************************************************************************/
emilmont	77:869cf507173a	1028	/****************** Bits definition for ADC_ISR register ****************/
emilmont	77:869cf507173a	1029	#define ADC_ISR_AWD ((uint32_t)0x00000080) /!< Analog watchdog flag /
emilmont	77:869cf507173a	1030	#define ADC_ISR_OVR ((uint32_t)0x00000010) /!< Overrun flag /
emilmont	77:869cf507173a	1031	#define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /!< End of Sequence flag /
emilmont	77:869cf507173a	1032	#define ADC_ISR_EOC ((uint32_t)0x00000004) /!< End of Conversion /
emilmont	77:869cf507173a	1033	#define ADC_ISR_EOSMP ((uint32_t)0x00000002) /!< End of sampling flag /
emilmont	77:869cf507173a	1034	#define ADC_ISR_ADRDY ((uint32_t)0x00000001) /!< ADC Ready /
emilmont	77:869cf507173a	1035
emilmont	77:869cf507173a	1036	/* Old EOSEQ bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	1037	#define ADC_ISR_EOS ADC_ISR_EOSEQ
emilmont	77:869cf507173a	1038
emilmont	77:869cf507173a	1039	/****************** Bits definition for ADC_IER register ****************/
emilmont	77:869cf507173a	1040	#define ADC_IER_AWDIE ((uint32_t)0x00000080) /!< Analog Watchdog interrupt enable /
emilmont	77:869cf507173a	1041	#define ADC_IER_OVRIE ((uint32_t)0x00000010) /!< Overrun interrupt enable /
emilmont	77:869cf507173a	1042	#define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /!< End of Sequence of conversion interrupt enable /
emilmont	77:869cf507173a	1043	#define ADC_IER_EOCIE ((uint32_t)0x00000004) /!< End of Conversion interrupt enable /
emilmont	77:869cf507173a	1044	#define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /!< End of sampling interrupt enable /
emilmont	77:869cf507173a	1045	#define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /!< ADC Ready interrupt enable /
emilmont	77:869cf507173a	1046
emilmont	77:869cf507173a	1047	/* Old EOSEQIE bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	1048	#define ADC_IER_EOSIE ADC_IER_EOSEQIE
emilmont	77:869cf507173a	1049
emilmont	77:869cf507173a	1050	/****************** Bits definition for ADC_CR register *****************/
emilmont	77:869cf507173a	1051	#define ADC_CR_ADCAL ((uint32_t)0x80000000) /!< ADC calibration /
emilmont	77:869cf507173a	1052	#define ADC_CR_ADSTP ((uint32_t)0x00000010) /!< ADC stop of conversion command /
emilmont	77:869cf507173a	1053	#define ADC_CR_ADSTART ((uint32_t)0x00000004) /!< ADC start of conversion /
emilmont	77:869cf507173a	1054	#define ADC_CR_ADDIS ((uint32_t)0x00000002) /!< ADC disable command /
emilmont	77:869cf507173a	1055	#define ADC_CR_ADEN ((uint32_t)0x00000001) /!< ADC enable control /
emilmont	77:869cf507173a	1056
emilmont	77:869cf507173a	1057	/***************** Bits definition for ADC_CFGR1 register ***************/
emilmont	77:869cf507173a	1058	#define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /!< AWDCH[4:0] bits (Analog watchdog channel select bits) /
emilmont	77:869cf507173a	1059	#define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /!< Bit 0 /
emilmont	77:869cf507173a	1060	#define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /!< Bit 1 /
emilmont	77:869cf507173a	1061	#define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /!< Bit 2 /
emilmont	77:869cf507173a	1062	#define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /!< Bit 3 /
emilmont	77:869cf507173a	1063	#define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /!< Bit 4 /
emilmont	77:869cf507173a	1064	#define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /!< Analog watchdog enable on regular channels /
emilmont	77:869cf507173a	1065	#define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /!< Enable the watchdog on a single channel or on all channels /
emilmont	77:869cf507173a	1066	#define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /!< Discontinuous mode on regular channels /
emilmont	77:869cf507173a	1067	#define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /!< ADC auto power off /
emilmont	77:869cf507173a	1068	#define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /!< ADC wait conversion mode /
emilmont	77:869cf507173a	1069	#define ADC_CFGR1_CONT ((uint32_t)0x00002000) /!< Continuous Conversion /
emilmont	77:869cf507173a	1070	#define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /!< Overrun mode /
emilmont	77:869cf507173a	1071	#define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) /
emilmont	77:869cf507173a	1072	#define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /!< Bit 0 /
emilmont	77:869cf507173a	1073	#define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /!< Bit 1 /
emilmont	77:869cf507173a	1074	#define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /!< EXTSEL[2:0] bits (External Event Select for regular group) /
emilmont	77:869cf507173a	1075	#define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /!< Bit 0 /
emilmont	77:869cf507173a	1076	#define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /!< Bit 1 /
emilmont	77:869cf507173a	1077	#define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /!< Bit 2 /
emilmont	77:869cf507173a	1078	#define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /!< Data Alignment /
emilmont	77:869cf507173a	1079	#define ADC_CFGR1_RES ((uint32_t)0x00000018) /!< RES[1:0] bits (Resolution) /
emilmont	77:869cf507173a	1080	#define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /!< Bit 0 /
emilmont	77:869cf507173a	1081	#define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /!< Bit 1 /
emilmont	77:869cf507173a	1082	#define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /!< Sequence scan direction /
emilmont	77:869cf507173a	1083	#define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /!< Direct memory access configuration /
emilmont	77:869cf507173a	1084	#define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /!< Direct memory access enable /
emilmont	77:869cf507173a	1085
emilmont	77:869cf507173a	1086	/* Old WAIT bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	1087	#define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
emilmont	77:869cf507173a	1088
emilmont	77:869cf507173a	1089	/***************** Bits definition for ADC_CFGR2 register ***************/
emilmont	77:869cf507173a	1090	#define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /!< ADC clock mode /
emilmont	77:869cf507173a	1091	#define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /!< ADC clocked by PCLK div4 /
emilmont	77:869cf507173a	1092	#define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /!< ADC clocked by PCLK div2 /
emilmont	77:869cf507173a	1093
emilmont	77:869cf507173a	1094	/* Old bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	1095	#define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /!< ADC clocked by PCLK div4 /
emilmont	77:869cf507173a	1096	#define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /!< ADC clocked by PCLK div2 /
emilmont	77:869cf507173a	1097
emilmont	77:869cf507173a	1098	/**************** Bit definition for ADC_SMPR register ******************/
emilmont	77:869cf507173a	1099	#define ADC_SMPR_SMP ((uint32_t)0x00000007) /!< SMP[2:0] bits (Sampling time selection) /
emilmont	77:869cf507173a	1100	#define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /!< Bit 0 /
emilmont	77:869cf507173a	1101	#define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /!< Bit 1 /
emilmont	77:869cf507173a	1102	#define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /!< Bit 2 /
emilmont	77:869cf507173a	1103
emilmont	77:869cf507173a	1104	/* Old bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	1105	#define ADC_SMPR1_SMPR ADC_SMPR_SMP /!< SMP[2:0] bits (Sampling time selection) /
emilmont	77:869cf507173a	1106	#define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /!< Bit 0 /
emilmont	77:869cf507173a	1107	#define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /!< Bit 1 /
emilmont	77:869cf507173a	1108	#define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /!< Bit 2 /
emilmont	77:869cf507173a	1109
emilmont	77:869cf507173a	1110	/***************** Bit definition for ADC_TR register ******************/
emilmont	77:869cf507173a	1111	#define ADC_TR_HT ((uint32_t)0x0FFF0000) /!< Analog watchdog high threshold /
emilmont	77:869cf507173a	1112	#define ADC_TR_LT ((uint32_t)0x00000FFF) /!< Analog watchdog low threshold /
emilmont	77:869cf507173a	1113
emilmont	77:869cf507173a	1114	/* Old bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	1115	#define ADC_HTR_HT ADC_TR_HT /!< Analog watchdog high threshold /
emilmont	77:869cf507173a	1116	#define ADC_LTR_LT ADC_TR_LT /!< Analog watchdog low threshold /
emilmont	77:869cf507173a	1117
emilmont	77:869cf507173a	1118	/**************** Bit definition for ADC_CHSELR register ****************/
emilmont	77:869cf507173a	1119	#define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /!< Channel 18 selection /
emilmont	77:869cf507173a	1120	#define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /!< Channel 17 selection /
emilmont	77:869cf507173a	1121	#define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /!< Channel 16 selection /
emilmont	77:869cf507173a	1122	#define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /!< Channel 15 selection /
emilmont	77:869cf507173a	1123	#define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /!< Channel 14 selection /
emilmont	77:869cf507173a	1124	#define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /!< Channel 13 selection /
emilmont	77:869cf507173a	1125	#define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /!< Channel 12 selection /
emilmont	77:869cf507173a	1126	#define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /!< Channel 11 selection /
emilmont	77:869cf507173a	1127	#define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /!< Channel 10 selection /
emilmont	77:869cf507173a	1128	#define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /!< Channel 9 selection /
emilmont	77:869cf507173a	1129	#define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /!< Channel 8 selection /
emilmont	77:869cf507173a	1130	#define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /!< Channel 7 selection /
emilmont	77:869cf507173a	1131	#define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /!< Channel 6 selection /
emilmont	77:869cf507173a	1132	#define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /!< Channel 5 selection /
emilmont	77:869cf507173a	1133	#define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /!< Channel 4 selection /
emilmont	77:869cf507173a	1134	#define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /!< Channel 3 selection /
emilmont	77:869cf507173a	1135	#define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /!< Channel 2 selection /
emilmont	77:869cf507173a	1136	#define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /!< Channel 1 selection /
emilmont	77:869cf507173a	1137	#define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /!< Channel 0 selection /
emilmont	77:869cf507173a	1138
emilmont	77:869cf507173a	1139	/****************** Bit definition for ADC_DR register ******************/
emilmont	77:869cf507173a	1140	#define ADC_DR_DATA ((uint32_t)0x0000FFFF) /!< Regular data /
emilmont	77:869cf507173a	1141
emilmont	77:869cf507173a	1142	/***************** Bit definition for ADC_CCR register ******************/
emilmont	77:869cf507173a	1143	#define ADC_CCR_VBATEN ((uint32_t)0x01000000) /!< Voltage battery enable /
emilmont	77:869cf507173a	1144	#define ADC_CCR_TSEN ((uint32_t)0x00800000) /!< Tempurature sensore enable /
emilmont	77:869cf507173a	1145	#define ADC_CCR_VREFEN ((uint32_t)0x00400000) /!< Vrefint enable /
emilmont	77:869cf507173a	1146
emilmont	77:869cf507173a	1147	/******************************************************************************/
emilmont	77:869cf507173a	1148	/* */
emilmont	77:869cf507173a	1149	/* Controller Area Network (CAN ) */
emilmont	77:869cf507173a	1150	/* */
emilmont	77:869cf507173a	1151	/******************************************************************************/
emilmont	77:869cf507173a	1152	/***************** Bit definition for CAN_MCR register ******************/
emilmont	77:869cf507173a	1153	#define CAN_MCR_INRQ ((uint16_t)0x0001) /!<Initialization Request /
emilmont	77:869cf507173a	1154	#define CAN_MCR_SLEEP ((uint16_t)0x0002) /!<Sleep Mode Request /
emilmont	77:869cf507173a	1155	#define CAN_MCR_TXFP ((uint16_t)0x0004) /!<Transmit FIFO Priority /
emilmont	77:869cf507173a	1156	#define CAN_MCR_RFLM ((uint16_t)0x0008) /!<Receive FIFO Locked Mode /
emilmont	77:869cf507173a	1157	#define CAN_MCR_NART ((uint16_t)0x0010) /!<No Automatic Retransmission /
emilmont	77:869cf507173a	1158	#define CAN_MCR_AWUM ((uint16_t)0x0020) /!<Automatic Wakeup Mode /
emilmont	77:869cf507173a	1159	#define CAN_MCR_ABOM ((uint16_t)0x0040) /!<Automatic Bus-Off Management /
emilmont	77:869cf507173a	1160	#define CAN_MCR_TTCM ((uint16_t)0x0080) /!<Time Triggered Communication Mode /
emilmont	77:869cf507173a	1161	#define CAN_MCR_RESET ((uint16_t)0x8000) /!<bxCAN software master reset /
emilmont	77:869cf507173a	1162
emilmont	77:869cf507173a	1163	/***************** Bit definition for CAN_MSR register ******************/
emilmont	77:869cf507173a	1164	#define CAN_MSR_INAK ((uint16_t)0x0001) /!<Initialization Acknowledge /
emilmont	77:869cf507173a	1165	#define CAN_MSR_SLAK ((uint16_t)0x0002) /!<Sleep Acknowledge /
emilmont	77:869cf507173a	1166	#define CAN_MSR_ERRI ((uint16_t)0x0004) /!<Error Interrupt /
emilmont	77:869cf507173a	1167	#define CAN_MSR_WKUI ((uint16_t)0x0008) /!<Wakeup Interrupt /
emilmont	77:869cf507173a	1168	#define CAN_MSR_SLAKI ((uint16_t)0x0010) /!<Sleep Acknowledge Interrupt /
emilmont	77:869cf507173a	1169	#define CAN_MSR_TXM ((uint16_t)0x0100) /!<Transmit Mode /
emilmont	77:869cf507173a	1170	#define CAN_MSR_RXM ((uint16_t)0x0200) /!<Receive Mode /
emilmont	77:869cf507173a	1171	#define CAN_MSR_SAMP ((uint16_t)0x0400) /!<Last Sample Point /
emilmont	77:869cf507173a	1172	#define CAN_MSR_RX ((uint16_t)0x0800) /!<CAN Rx Signal /
emilmont	77:869cf507173a	1173
emilmont	77:869cf507173a	1174	/***************** Bit definition for CAN_TSR register ******************/
emilmont	77:869cf507173a	1175	#define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /!<Request Completed Mailbox0 /
emilmont	77:869cf507173a	1176	#define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /!<Transmission OK of Mailbox0 /
emilmont	77:869cf507173a	1177	#define CAN_TSR_ALST0 ((uint32_t)0x00000004) /!<Arbitration Lost for Mailbox0 /
emilmont	77:869cf507173a	1178	#define CAN_TSR_TERR0 ((uint32_t)0x00000008) /!<Transmission Error of Mailbox0 /
emilmont	77:869cf507173a	1179	#define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /!<Abort Request for Mailbox0 /
emilmont	77:869cf507173a	1180	#define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /!<Request Completed Mailbox1 /
emilmont	77:869cf507173a	1181	#define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /!<Transmission OK of Mailbox1 /
emilmont	77:869cf507173a	1182	#define CAN_TSR_ALST1 ((uint32_t)0x00000400) /!<Arbitration Lost for Mailbox1 /
emilmont	77:869cf507173a	1183	#define CAN_TSR_TERR1 ((uint32_t)0x00000800) /!<Transmission Error of Mailbox1 /
emilmont	77:869cf507173a	1184	#define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /!<Abort Request for Mailbox 1 /
emilmont	77:869cf507173a	1185	#define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /!<Request Completed Mailbox2 /
emilmont	77:869cf507173a	1186	#define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /!<Transmission OK of Mailbox 2 /
emilmont	77:869cf507173a	1187	#define CAN_TSR_ALST2 ((uint32_t)0x00040000) /!<Arbitration Lost for mailbox 2 /
emilmont	77:869cf507173a	1188	#define CAN_TSR_TERR2 ((uint32_t)0x00080000) /!<Transmission Error of Mailbox 2 /
emilmont	77:869cf507173a	1189	#define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /!<Abort Request for Mailbox 2 /
emilmont	77:869cf507173a	1190	#define CAN_TSR_CODE ((uint32_t)0x03000000) /!<Mailbox Code /
emilmont	77:869cf507173a	1191
emilmont	77:869cf507173a	1192	#define CAN_TSR_TME ((uint32_t)0x1C000000) /!<TME[2:0] bits /
emilmont	77:869cf507173a	1193	#define CAN_TSR_TME0 ((uint32_t)0x04000000) /!<Transmit Mailbox 0 Empty /
emilmont	77:869cf507173a	1194	#define CAN_TSR_TME1 ((uint32_t)0x08000000) /!<Transmit Mailbox 1 Empty /
emilmont	77:869cf507173a	1195	#define CAN_TSR_TME2 ((uint32_t)0x10000000) /!<Transmit Mailbox 2 Empty /
emilmont	77:869cf507173a	1196
emilmont	77:869cf507173a	1197	#define CAN_TSR_LOW ((uint32_t)0xE0000000) /!<LOW[2:0] bits /
emilmont	77:869cf507173a	1198	#define CAN_TSR_LOW0 ((uint32_t)0x20000000) /!<Lowest Priority Flag for Mailbox 0 /
emilmont	77:869cf507173a	1199	#define CAN_TSR_LOW1 ((uint32_t)0x40000000) /!<Lowest Priority Flag for Mailbox 1 /
emilmont	77:869cf507173a	1200	#define CAN_TSR_LOW2 ((uint32_t)0x80000000) /!<Lowest Priority Flag for Mailbox 2 /
emilmont	77:869cf507173a	1201
emilmont	77:869cf507173a	1202	/***************** Bit definition for CAN_RF0R register *****************/
emilmont	77:869cf507173a	1203	#define CAN_RF0R_FMP0 ((uint8_t)0x03) /!<FIFO 0 Message Pending /
emilmont	77:869cf507173a	1204	#define CAN_RF0R_FULL0 ((uint8_t)0x08) /!<FIFO 0 Full /
emilmont	77:869cf507173a	1205	#define CAN_RF0R_FOVR0 ((uint8_t)0x10) /!<FIFO 0 Overrun /
emilmont	77:869cf507173a	1206	#define CAN_RF0R_RFOM0 ((uint8_t)0x20) /!<Release FIFO 0 Output Mailbox /
emilmont	77:869cf507173a	1207
emilmont	77:869cf507173a	1208	/***************** Bit definition for CAN_RF1R register *****************/
emilmont	77:869cf507173a	1209	#define CAN_RF1R_FMP1 ((uint8_t)0x03) /!<FIFO 1 Message Pending /
emilmont	77:869cf507173a	1210	#define CAN_RF1R_FULL1 ((uint8_t)0x08) /!<FIFO 1 Full /
emilmont	77:869cf507173a	1211	#define CAN_RF1R_FOVR1 ((uint8_t)0x10) /!<FIFO 1 Overrun /
emilmont	77:869cf507173a	1212	#define CAN_RF1R_RFOM1 ((uint8_t)0x20) /!<Release FIFO 1 Output Mailbox /
emilmont	77:869cf507173a	1213
emilmont	77:869cf507173a	1214	/****************** Bit definition for CAN_IER register *****************/
emilmont	77:869cf507173a	1215	#define CAN_IER_TMEIE ((uint32_t)0x00000001) /!<Transmit Mailbox Empty Interrupt Enable /
emilmont	77:869cf507173a	1216	#define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /!<FIFO Message Pending Interrupt Enable /
emilmont	77:869cf507173a	1217	#define CAN_IER_FFIE0 ((uint32_t)0x00000004) /!<FIFO Full Interrupt Enable /
emilmont	77:869cf507173a	1218	#define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /!<FIFO Overrun Interrupt Enable /
emilmont	77:869cf507173a	1219	#define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /!<FIFO Message Pending Interrupt Enable /
emilmont	77:869cf507173a	1220	#define CAN_IER_FFIE1 ((uint32_t)0x00000020) /!<FIFO Full Interrupt Enable /
emilmont	77:869cf507173a	1221	#define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /!<FIFO Overrun Interrupt Enable /
emilmont	77:869cf507173a	1222	#define CAN_IER_EWGIE ((uint32_t)0x00000100) /!<Error Warning Interrupt Enable /
emilmont	77:869cf507173a	1223	#define CAN_IER_EPVIE ((uint32_t)0x00000200) /!<Error Passive Interrupt Enable /
emilmont	77:869cf507173a	1224	#define CAN_IER_BOFIE ((uint32_t)0x00000400) /!<Bus-Off Interrupt Enable /
emilmont	77:869cf507173a	1225	#define CAN_IER_LECIE ((uint32_t)0x00000800) /!<Last Error Code Interrupt Enable /
emilmont	77:869cf507173a	1226	#define CAN_IER_ERRIE ((uint32_t)0x00008000) /!<Error Interrupt Enable /
emilmont	77:869cf507173a	1227	#define CAN_IER_WKUIE ((uint32_t)0x00010000) /!<Wakeup Interrupt Enable /
emilmont	77:869cf507173a	1228	#define CAN_IER_SLKIE ((uint32_t)0x00020000) /!<Sleep Interrupt Enable /
emilmont	77:869cf507173a	1229
emilmont	77:869cf507173a	1230	/****************** Bit definition for CAN_ESR register *****************/
emilmont	77:869cf507173a	1231	#define CAN_ESR_EWGF ((uint32_t)0x00000001) /!<Error Warning Flag /
emilmont	77:869cf507173a	1232	#define CAN_ESR_EPVF ((uint32_t)0x00000002) /!<Error Passive Flag /
emilmont	77:869cf507173a	1233	#define CAN_ESR_BOFF ((uint32_t)0x00000004) /!<Bus-Off Flag /
emilmont	77:869cf507173a	1234
emilmont	77:869cf507173a	1235	#define CAN_ESR_LEC ((uint32_t)0x00000070) /!<LEC[2:0] bits (Last Error Code) /
emilmont	77:869cf507173a	1236	#define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /!<Bit 0 /
emilmont	77:869cf507173a	1237	#define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /!<Bit 1 /
emilmont	77:869cf507173a	1238	#define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /!<Bit 2 /
emilmont	77:869cf507173a	1239
emilmont	77:869cf507173a	1240	#define CAN_ESR_TEC ((uint32_t)0x00FF0000) /!<Least significant byte of the 9-bit Transmit Error Counter /
emilmont	77:869cf507173a	1241	#define CAN_ESR_REC ((uint32_t)0xFF000000) /!<Receive Error Counter /
emilmont	77:869cf507173a	1242
emilmont	77:869cf507173a	1243	/***************** Bit definition for CAN_BTR register ******************/
emilmont	77:869cf507173a	1244	#define CAN_BTR_BRP ((uint32_t)0x000003FF) /!<Baud Rate Prescaler /
emilmont	77:869cf507173a	1245	#define CAN_BTR_TS1 ((uint32_t)0x000F0000) /!<Time Segment 1 /
emilmont	77:869cf507173a	1246	#define CAN_BTR_TS2 ((uint32_t)0x00700000) /!<Time Segment 2 /
emilmont	77:869cf507173a	1247	#define CAN_BTR_SJW ((uint32_t)0x03000000) /!<Resynchronization Jump Width /
emilmont	77:869cf507173a	1248	#define CAN_BTR_LBKM ((uint32_t)0x40000000) /!<Loop Back Mode (Debug) /
emilmont	77:869cf507173a	1249	#define CAN_BTR_SILM ((uint32_t)0x80000000) /!<Silent Mode /
emilmont	77:869cf507173a	1250
emilmont	77:869cf507173a	1251	/!<Mailbox registers /
emilmont	77:869cf507173a	1252	/**************** Bit definition for CAN_TI0R register ******************/
emilmont	77:869cf507173a	1253	#define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
emilmont	77:869cf507173a	1254	#define CAN_TI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
emilmont	77:869cf507173a	1255	#define CAN_TI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
emilmont	77:869cf507173a	1256	#define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
emilmont	77:869cf507173a	1257	#define CAN_TI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
emilmont	77:869cf507173a	1258
emilmont	77:869cf507173a	1259	/**************** Bit definition for CAN_TDT0R register *****************/
emilmont	77:869cf507173a	1260	#define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
emilmont	77:869cf507173a	1261	#define CAN_TDT0R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
emilmont	77:869cf507173a	1262	#define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
emilmont	77:869cf507173a	1263
emilmont	77:869cf507173a	1264	/**************** Bit definition for CAN_TDL0R register *****************/
emilmont	77:869cf507173a	1265	#define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
emilmont	77:869cf507173a	1266	#define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
emilmont	77:869cf507173a	1267	#define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
emilmont	77:869cf507173a	1268	#define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
emilmont	77:869cf507173a	1269
emilmont	77:869cf507173a	1270	/**************** Bit definition for CAN_TDH0R register *****************/
emilmont	77:869cf507173a	1271	#define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
emilmont	77:869cf507173a	1272	#define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
emilmont	77:869cf507173a	1273	#define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
emilmont	77:869cf507173a	1274	#define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
emilmont	77:869cf507173a	1275
emilmont	77:869cf507173a	1276	/***************** Bit definition for CAN_TI1R register *****************/
emilmont	77:869cf507173a	1277	#define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
emilmont	77:869cf507173a	1278	#define CAN_TI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
emilmont	77:869cf507173a	1279	#define CAN_TI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
emilmont	77:869cf507173a	1280	#define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
emilmont	77:869cf507173a	1281	#define CAN_TI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
emilmont	77:869cf507173a	1282
emilmont	77:869cf507173a	1283	/***************** Bit definition for CAN_TDT1R register ****************/
emilmont	77:869cf507173a	1284	#define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
emilmont	77:869cf507173a	1285	#define CAN_TDT1R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
emilmont	77:869cf507173a	1286	#define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
emilmont	77:869cf507173a	1287
emilmont	77:869cf507173a	1288	/***************** Bit definition for CAN_TDL1R register ****************/
emilmont	77:869cf507173a	1289	#define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
emilmont	77:869cf507173a	1290	#define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
emilmont	77:869cf507173a	1291	#define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
emilmont	77:869cf507173a	1292	#define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
emilmont	77:869cf507173a	1293
emilmont	77:869cf507173a	1294	/***************** Bit definition for CAN_TDH1R register ****************/
emilmont	77:869cf507173a	1295	#define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
emilmont	77:869cf507173a	1296	#define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
emilmont	77:869cf507173a	1297	#define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
emilmont	77:869cf507173a	1298	#define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
emilmont	77:869cf507173a	1299
emilmont	77:869cf507173a	1300	/***************** Bit definition for CAN_TI2R register *****************/
emilmont	77:869cf507173a	1301	#define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /!<Transmit Mailbox Request /
emilmont	77:869cf507173a	1302	#define CAN_TI2R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
emilmont	77:869cf507173a	1303	#define CAN_TI2R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
emilmont	77:869cf507173a	1304	#define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
emilmont	77:869cf507173a	1305	#define CAN_TI2R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
emilmont	77:869cf507173a	1306
emilmont	77:869cf507173a	1307	/***************** Bit definition for CAN_TDT2R register ****************/
emilmont	77:869cf507173a	1308	#define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
emilmont	77:869cf507173a	1309	#define CAN_TDT2R_TGT ((uint32_t)0x00000100) /!<Transmit Global Time /
emilmont	77:869cf507173a	1310	#define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
emilmont	77:869cf507173a	1311
emilmont	77:869cf507173a	1312	/***************** Bit definition for CAN_TDL2R register ****************/
emilmont	77:869cf507173a	1313	#define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
emilmont	77:869cf507173a	1314	#define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
emilmont	77:869cf507173a	1315	#define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
emilmont	77:869cf507173a	1316	#define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
emilmont	77:869cf507173a	1317
emilmont	77:869cf507173a	1318	/***************** Bit definition for CAN_TDH2R register ****************/
emilmont	77:869cf507173a	1319	#define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
emilmont	77:869cf507173a	1320	#define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
emilmont	77:869cf507173a	1321	#define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
emilmont	77:869cf507173a	1322	#define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
emilmont	77:869cf507173a	1323
emilmont	77:869cf507173a	1324	/***************** Bit definition for CAN_RI0R register *****************/
emilmont	77:869cf507173a	1325	#define CAN_RI0R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
emilmont	77:869cf507173a	1326	#define CAN_RI0R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
emilmont	77:869cf507173a	1327	#define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /!<Extended Identifier /
emilmont	77:869cf507173a	1328	#define CAN_RI0R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
emilmont	77:869cf507173a	1329
emilmont	77:869cf507173a	1330	/***************** Bit definition for CAN_RDT0R register ****************/
emilmont	77:869cf507173a	1331	#define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
emilmont	77:869cf507173a	1332	#define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
emilmont	77:869cf507173a	1333	#define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
emilmont	77:869cf507173a	1334
emilmont	77:869cf507173a	1335	/***************** Bit definition for CAN_RDL0R register ****************/
emilmont	77:869cf507173a	1336	#define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
emilmont	77:869cf507173a	1337	#define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
emilmont	77:869cf507173a	1338	#define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
emilmont	77:869cf507173a	1339	#define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
emilmont	77:869cf507173a	1340
emilmont	77:869cf507173a	1341	/***************** Bit definition for CAN_RDH0R register ****************/
emilmont	77:869cf507173a	1342	#define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
emilmont	77:869cf507173a	1343	#define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
emilmont	77:869cf507173a	1344	#define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
emilmont	77:869cf507173a	1345	#define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
emilmont	77:869cf507173a	1346
emilmont	77:869cf507173a	1347	/***************** Bit definition for CAN_RI1R register *****************/
emilmont	77:869cf507173a	1348	#define CAN_RI1R_RTR ((uint32_t)0x00000002) /!<Remote Transmission Request /
emilmont	77:869cf507173a	1349	#define CAN_RI1R_IDE ((uint32_t)0x00000004) /!<Identifier Extension /
emilmont	77:869cf507173a	1350	#define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /!<Extended identifier /
emilmont	77:869cf507173a	1351	#define CAN_RI1R_STID ((uint32_t)0xFFE00000) /!<Standard Identifier or Extended Identifier /
emilmont	77:869cf507173a	1352
emilmont	77:869cf507173a	1353	/***************** Bit definition for CAN_RDT1R register ****************/
emilmont	77:869cf507173a	1354	#define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /!<Data Length Code /
emilmont	77:869cf507173a	1355	#define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /!<Filter Match Index /
emilmont	77:869cf507173a	1356	#define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /!<Message Time Stamp /
emilmont	77:869cf507173a	1357
emilmont	77:869cf507173a	1358	/***************** Bit definition for CAN_RDL1R register ****************/
emilmont	77:869cf507173a	1359	#define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /!<Data byte 0 /
emilmont	77:869cf507173a	1360	#define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /!<Data byte 1 /
emilmont	77:869cf507173a	1361	#define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /!<Data byte 2 /
emilmont	77:869cf507173a	1362	#define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /!<Data byte 3 /
emilmont	77:869cf507173a	1363
emilmont	77:869cf507173a	1364	/***************** Bit definition for CAN_RDH1R register ****************/
emilmont	77:869cf507173a	1365	#define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /!<Data byte 4 /
emilmont	77:869cf507173a	1366	#define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /!<Data byte 5 /
emilmont	77:869cf507173a	1367	#define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /!<Data byte 6 /
emilmont	77:869cf507173a	1368	#define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /!<Data byte 7 /
emilmont	77:869cf507173a	1369
emilmont	77:869cf507173a	1370	/!<CAN filter registers /
emilmont	77:869cf507173a	1371	/***************** Bit definition for CAN_FMR register ******************/
emilmont	77:869cf507173a	1372	#define CAN_FMR_FINIT ((uint8_t)0x01) /!<Filter Init Mode /
emilmont	77:869cf507173a	1373
emilmont	77:869cf507173a	1374	/***************** Bit definition for CAN_FM1R register *****************/
emilmont	77:869cf507173a	1375	#define CAN_FM1R_FBM ((uint16_t)0x3FFF) /!<Filter Mode /
emilmont	77:869cf507173a	1376	#define CAN_FM1R_FBM0 ((uint16_t)0x0001) /!<Filter Init Mode bit 0 /
emilmont	77:869cf507173a	1377	#define CAN_FM1R_FBM1 ((uint16_t)0x0002) /!<Filter Init Mode bit 1 /
emilmont	77:869cf507173a	1378	#define CAN_FM1R_FBM2 ((uint16_t)0x0004) /!<Filter Init Mode bit 2 /
emilmont	77:869cf507173a	1379	#define CAN_FM1R_FBM3 ((uint16_t)0x0008) /!<Filter Init Mode bit 3 /
emilmont	77:869cf507173a	1380	#define CAN_FM1R_FBM4 ((uint16_t)0x0010) /!<Filter Init Mode bit 4 /
emilmont	77:869cf507173a	1381	#define CAN_FM1R_FBM5 ((uint16_t)0x0020) /!<Filter Init Mode bit 5 /
emilmont	77:869cf507173a	1382	#define CAN_FM1R_FBM6 ((uint16_t)0x0040) /!<Filter Init Mode bit 6 /
emilmont	77:869cf507173a	1383	#define CAN_FM1R_FBM7 ((uint16_t)0x0080) /!<Filter Init Mode bit 7 /
emilmont	77:869cf507173a	1384	#define CAN_FM1R_FBM8 ((uint16_t)0x0100) /!<Filter Init Mode bit 8 /
emilmont	77:869cf507173a	1385	#define CAN_FM1R_FBM9 ((uint16_t)0x0200) /!<Filter Init Mode bit 9 /
emilmont	77:869cf507173a	1386	#define CAN_FM1R_FBM10 ((uint16_t)0x0400) /!<Filter Init Mode bit 10 /
emilmont	77:869cf507173a	1387	#define CAN_FM1R_FBM11 ((uint16_t)0x0800) /!<Filter Init Mode bit 11 /
emilmont	77:869cf507173a	1388	#define CAN_FM1R_FBM12 ((uint16_t)0x1000) /!<Filter Init Mode bit 12 /
emilmont	77:869cf507173a	1389	#define CAN_FM1R_FBM13 ((uint16_t)0x2000) /!<Filter Init Mode bit 13 /
emilmont	77:869cf507173a	1390
emilmont	77:869cf507173a	1391	/***************** Bit definition for CAN_FS1R register *****************/
emilmont	77:869cf507173a	1392	#define CAN_FS1R_FSC ((uint16_t)0x3FFF) /!<Filter Scale Configuration /
emilmont	77:869cf507173a	1393	#define CAN_FS1R_FSC0 ((uint16_t)0x0001) /!<Filter Scale Configuration bit 0 /
emilmont	77:869cf507173a	1394	#define CAN_FS1R_FSC1 ((uint16_t)0x0002) /!<Filter Scale Configuration bit 1 /
emilmont	77:869cf507173a	1395	#define CAN_FS1R_FSC2 ((uint16_t)0x0004) /!<Filter Scale Configuration bit 2 /
emilmont	77:869cf507173a	1396	#define CAN_FS1R_FSC3 ((uint16_t)0x0008) /!<Filter Scale Configuration bit 3 /
emilmont	77:869cf507173a	1397	#define CAN_FS1R_FSC4 ((uint16_t)0x0010) /!<Filter Scale Configuration bit 4 /
emilmont	77:869cf507173a	1398	#define CAN_FS1R_FSC5 ((uint16_t)0x0020) /!<Filter Scale Configuration bit 5 /
emilmont	77:869cf507173a	1399	#define CAN_FS1R_FSC6 ((uint16_t)0x0040) /!<Filter Scale Configuration bit 6 /
emilmont	77:869cf507173a	1400	#define CAN_FS1R_FSC7 ((uint16_t)0x0080) /!<Filter Scale Configuration bit 7 /
emilmont	77:869cf507173a	1401	#define CAN_FS1R_FSC8 ((uint16_t)0x0100) /!<Filter Scale Configuration bit 8 /
emilmont	77:869cf507173a	1402	#define CAN_FS1R_FSC9 ((uint16_t)0x0200) /!<Filter Scale Configuration bit 9 /
emilmont	77:869cf507173a	1403	#define CAN_FS1R_FSC10 ((uint16_t)0x0400) /!<Filter Scale Configuration bit 10 /
emilmont	77:869cf507173a	1404	#define CAN_FS1R_FSC11 ((uint16_t)0x0800) /!<Filter Scale Configuration bit 11 /
emilmont	77:869cf507173a	1405	#define CAN_FS1R_FSC12 ((uint16_t)0x1000) /!<Filter Scale Configuration bit 12 /
emilmont	77:869cf507173a	1406	#define CAN_FS1R_FSC13 ((uint16_t)0x2000) /!<Filter Scale Configuration bit 13 /
emilmont	77:869cf507173a	1407
emilmont	77:869cf507173a	1408	/**************** Bit definition for CAN_FFA1R register *****************/
emilmont	77:869cf507173a	1409	#define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /!<Filter FIFO Assignment /
emilmont	77:869cf507173a	1410	#define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /!<Filter FIFO Assignment for Filter 0 /
emilmont	77:869cf507173a	1411	#define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /!<Filter FIFO Assignment for Filter 1 /
emilmont	77:869cf507173a	1412	#define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /!<Filter FIFO Assignment for Filter 2 /
emilmont	77:869cf507173a	1413	#define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /!<Filter FIFO Assignment for Filter 3 /
emilmont	77:869cf507173a	1414	#define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /!<Filter FIFO Assignment for Filter 4 /
emilmont	77:869cf507173a	1415	#define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /!<Filter FIFO Assignment for Filter 5 /
emilmont	77:869cf507173a	1416	#define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /!<Filter FIFO Assignment for Filter 6 /
emilmont	77:869cf507173a	1417	#define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /!<Filter FIFO Assignment for Filter 7 /
emilmont	77:869cf507173a	1418	#define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /!<Filter FIFO Assignment for Filter 8 /
emilmont	77:869cf507173a	1419	#define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /!<Filter FIFO Assignment for Filter 9 /
emilmont	77:869cf507173a	1420	#define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /!<Filter FIFO Assignment for Filter 10 /
emilmont	77:869cf507173a	1421	#define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /!<Filter FIFO Assignment for Filter 11 /
emilmont	77:869cf507173a	1422	#define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /!<Filter FIFO Assignment for Filter 12 /
emilmont	77:869cf507173a	1423	#define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /!<Filter FIFO Assignment for Filter 13 /
emilmont	77:869cf507173a	1424
emilmont	77:869cf507173a	1425	/***************** Bit definition for CAN_FA1R register *****************/
emilmont	77:869cf507173a	1426	#define CAN_FA1R_FACT ((uint16_t)0x3FFF) /!<Filter Active /
emilmont	77:869cf507173a	1427	#define CAN_FA1R_FACT0 ((uint16_t)0x0001) /!<Filter 0 Active /
emilmont	77:869cf507173a	1428	#define CAN_FA1R_FACT1 ((uint16_t)0x0002) /!<Filter 1 Active /
emilmont	77:869cf507173a	1429	#define CAN_FA1R_FACT2 ((uint16_t)0x0004) /!<Filter 2 Active /
emilmont	77:869cf507173a	1430	#define CAN_FA1R_FACT3 ((uint16_t)0x0008) /!<Filter 3 Active /
emilmont	77:869cf507173a	1431	#define CAN_FA1R_FACT4 ((uint16_t)0x0010) /!<Filter 4 Active /
emilmont	77:869cf507173a	1432	#define CAN_FA1R_FACT5 ((uint16_t)0x0020) /!<Filter 5 Active /
emilmont	77:869cf507173a	1433	#define CAN_FA1R_FACT6 ((uint16_t)0x0040) /!<Filter 6 Active /
emilmont	77:869cf507173a	1434	#define CAN_FA1R_FACT7 ((uint16_t)0x0080) /!<Filter 7 Active /
emilmont	77:869cf507173a	1435	#define CAN_FA1R_FACT8 ((uint16_t)0x0100) /!<Filter 8 Active /
emilmont	77:869cf507173a	1436	#define CAN_FA1R_FACT9 ((uint16_t)0x0200) /!<Filter 9 Active /
emilmont	77:869cf507173a	1437	#define CAN_FA1R_FACT10 ((uint16_t)0x0400) /!<Filter 10 Active /
emilmont	77:869cf507173a	1438	#define CAN_FA1R_FACT11 ((uint16_t)0x0800) /!<Filter 11 Active /
emilmont	77:869cf507173a	1439	#define CAN_FA1R_FACT12 ((uint16_t)0x1000) /!<Filter 12 Active /
emilmont	77:869cf507173a	1440	#define CAN_FA1R_FACT13 ((uint16_t)0x2000) /!<Filter 13 Active /
emilmont	77:869cf507173a	1441
emilmont	77:869cf507173a	1442	/***************** Bit definition for CAN_F0R1 register *****************/
emilmont	77:869cf507173a	1443	#define CAN_F0R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1444	#define CAN_F0R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1445	#define CAN_F0R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1446	#define CAN_F0R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1447	#define CAN_F0R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1448	#define CAN_F0R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1449	#define CAN_F0R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1450	#define CAN_F0R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1451	#define CAN_F0R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1452	#define CAN_F0R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1453	#define CAN_F0R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1454	#define CAN_F0R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1455	#define CAN_F0R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1456	#define CAN_F0R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1457	#define CAN_F0R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1458	#define CAN_F0R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1459	#define CAN_F0R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1460	#define CAN_F0R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1461	#define CAN_F0R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1462	#define CAN_F0R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1463	#define CAN_F0R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1464	#define CAN_F0R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1465	#define CAN_F0R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1466	#define CAN_F0R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1467	#define CAN_F0R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1468	#define CAN_F0R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1469	#define CAN_F0R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1470	#define CAN_F0R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1471	#define CAN_F0R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1472	#define CAN_F0R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1473	#define CAN_F0R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1474	#define CAN_F0R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1475
emilmont	77:869cf507173a	1476	/***************** Bit definition for CAN_F1R1 register *****************/
emilmont	77:869cf507173a	1477	#define CAN_F1R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1478	#define CAN_F1R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1479	#define CAN_F1R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1480	#define CAN_F1R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1481	#define CAN_F1R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1482	#define CAN_F1R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1483	#define CAN_F1R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1484	#define CAN_F1R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1485	#define CAN_F1R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1486	#define CAN_F1R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1487	#define CAN_F1R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1488	#define CAN_F1R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1489	#define CAN_F1R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1490	#define CAN_F1R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1491	#define CAN_F1R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1492	#define CAN_F1R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1493	#define CAN_F1R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1494	#define CAN_F1R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1495	#define CAN_F1R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1496	#define CAN_F1R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1497	#define CAN_F1R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1498	#define CAN_F1R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1499	#define CAN_F1R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1500	#define CAN_F1R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1501	#define CAN_F1R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1502	#define CAN_F1R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1503	#define CAN_F1R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1504	#define CAN_F1R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1505	#define CAN_F1R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1506	#define CAN_F1R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1507	#define CAN_F1R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1508	#define CAN_F1R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1509
emilmont	77:869cf507173a	1510	/***************** Bit definition for CAN_F2R1 register *****************/
emilmont	77:869cf507173a	1511	#define CAN_F2R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1512	#define CAN_F2R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1513	#define CAN_F2R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1514	#define CAN_F2R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1515	#define CAN_F2R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1516	#define CAN_F2R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1517	#define CAN_F2R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1518	#define CAN_F2R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1519	#define CAN_F2R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1520	#define CAN_F2R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1521	#define CAN_F2R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1522	#define CAN_F2R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1523	#define CAN_F2R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1524	#define CAN_F2R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1525	#define CAN_F2R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1526	#define CAN_F2R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1527	#define CAN_F2R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1528	#define CAN_F2R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1529	#define CAN_F2R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1530	#define CAN_F2R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1531	#define CAN_F2R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1532	#define CAN_F2R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1533	#define CAN_F2R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1534	#define CAN_F2R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1535	#define CAN_F2R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1536	#define CAN_F2R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1537	#define CAN_F2R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1538	#define CAN_F2R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1539	#define CAN_F2R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1540	#define CAN_F2R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1541	#define CAN_F2R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1542	#define CAN_F2R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1543
emilmont	77:869cf507173a	1544	/***************** Bit definition for CAN_F3R1 register *****************/
emilmont	77:869cf507173a	1545	#define CAN_F3R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1546	#define CAN_F3R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1547	#define CAN_F3R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1548	#define CAN_F3R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1549	#define CAN_F3R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1550	#define CAN_F3R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1551	#define CAN_F3R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1552	#define CAN_F3R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1553	#define CAN_F3R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1554	#define CAN_F3R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1555	#define CAN_F3R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1556	#define CAN_F3R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1557	#define CAN_F3R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1558	#define CAN_F3R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1559	#define CAN_F3R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1560	#define CAN_F3R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1561	#define CAN_F3R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1562	#define CAN_F3R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1563	#define CAN_F3R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1564	#define CAN_F3R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1565	#define CAN_F3R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1566	#define CAN_F3R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1567	#define CAN_F3R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1568	#define CAN_F3R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1569	#define CAN_F3R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1570	#define CAN_F3R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1571	#define CAN_F3R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1572	#define CAN_F3R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1573	#define CAN_F3R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1574	#define CAN_F3R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1575	#define CAN_F3R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1576	#define CAN_F3R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1577
emilmont	77:869cf507173a	1578	/***************** Bit definition for CAN_F4R1 register *****************/
emilmont	77:869cf507173a	1579	#define CAN_F4R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1580	#define CAN_F4R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1581	#define CAN_F4R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1582	#define CAN_F4R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1583	#define CAN_F4R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1584	#define CAN_F4R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1585	#define CAN_F4R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1586	#define CAN_F4R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1587	#define CAN_F4R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1588	#define CAN_F4R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1589	#define CAN_F4R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1590	#define CAN_F4R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1591	#define CAN_F4R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1592	#define CAN_F4R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1593	#define CAN_F4R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1594	#define CAN_F4R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1595	#define CAN_F4R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1596	#define CAN_F4R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1597	#define CAN_F4R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1598	#define CAN_F4R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1599	#define CAN_F4R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1600	#define CAN_F4R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1601	#define CAN_F4R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1602	#define CAN_F4R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1603	#define CAN_F4R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1604	#define CAN_F4R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1605	#define CAN_F4R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1606	#define CAN_F4R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1607	#define CAN_F4R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1608	#define CAN_F4R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1609	#define CAN_F4R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1610	#define CAN_F4R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1611
emilmont	77:869cf507173a	1612	/***************** Bit definition for CAN_F5R1 register *****************/
emilmont	77:869cf507173a	1613	#define CAN_F5R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1614	#define CAN_F5R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1615	#define CAN_F5R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1616	#define CAN_F5R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1617	#define CAN_F5R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1618	#define CAN_F5R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1619	#define CAN_F5R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1620	#define CAN_F5R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1621	#define CAN_F5R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1622	#define CAN_F5R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1623	#define CAN_F5R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1624	#define CAN_F5R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1625	#define CAN_F5R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1626	#define CAN_F5R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1627	#define CAN_F5R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1628	#define CAN_F5R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1629	#define CAN_F5R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1630	#define CAN_F5R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1631	#define CAN_F5R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1632	#define CAN_F5R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1633	#define CAN_F5R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1634	#define CAN_F5R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1635	#define CAN_F5R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1636	#define CAN_F5R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1637	#define CAN_F5R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1638	#define CAN_F5R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1639	#define CAN_F5R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1640	#define CAN_F5R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1641	#define CAN_F5R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1642	#define CAN_F5R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1643	#define CAN_F5R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1644	#define CAN_F5R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1645
emilmont	77:869cf507173a	1646	/***************** Bit definition for CAN_F6R1 register *****************/
emilmont	77:869cf507173a	1647	#define CAN_F6R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1648	#define CAN_F6R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1649	#define CAN_F6R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1650	#define CAN_F6R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1651	#define CAN_F6R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1652	#define CAN_F6R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1653	#define CAN_F6R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1654	#define CAN_F6R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1655	#define CAN_F6R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1656	#define CAN_F6R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1657	#define CAN_F6R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1658	#define CAN_F6R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1659	#define CAN_F6R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1660	#define CAN_F6R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1661	#define CAN_F6R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1662	#define CAN_F6R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1663	#define CAN_F6R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1664	#define CAN_F6R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1665	#define CAN_F6R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1666	#define CAN_F6R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1667	#define CAN_F6R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1668	#define CAN_F6R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1669	#define CAN_F6R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1670	#define CAN_F6R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1671	#define CAN_F6R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1672	#define CAN_F6R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1673	#define CAN_F6R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1674	#define CAN_F6R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1675	#define CAN_F6R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1676	#define CAN_F6R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1677	#define CAN_F6R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1678	#define CAN_F6R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1679
emilmont	77:869cf507173a	1680	/***************** Bit definition for CAN_F7R1 register *****************/
emilmont	77:869cf507173a	1681	#define CAN_F7R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1682	#define CAN_F7R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1683	#define CAN_F7R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1684	#define CAN_F7R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1685	#define CAN_F7R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1686	#define CAN_F7R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1687	#define CAN_F7R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1688	#define CAN_F7R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1689	#define CAN_F7R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1690	#define CAN_F7R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1691	#define CAN_F7R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1692	#define CAN_F7R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1693	#define CAN_F7R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1694	#define CAN_F7R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1695	#define CAN_F7R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1696	#define CAN_F7R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1697	#define CAN_F7R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1698	#define CAN_F7R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1699	#define CAN_F7R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1700	#define CAN_F7R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1701	#define CAN_F7R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1702	#define CAN_F7R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1703	#define CAN_F7R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1704	#define CAN_F7R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1705	#define CAN_F7R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1706	#define CAN_F7R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1707	#define CAN_F7R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1708	#define CAN_F7R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1709	#define CAN_F7R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1710	#define CAN_F7R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1711	#define CAN_F7R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1712	#define CAN_F7R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1713
emilmont	77:869cf507173a	1714	/***************** Bit definition for CAN_F8R1 register *****************/
emilmont	77:869cf507173a	1715	#define CAN_F8R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1716	#define CAN_F8R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1717	#define CAN_F8R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1718	#define CAN_F8R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1719	#define CAN_F8R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1720	#define CAN_F8R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1721	#define CAN_F8R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1722	#define CAN_F8R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1723	#define CAN_F8R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1724	#define CAN_F8R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1725	#define CAN_F8R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1726	#define CAN_F8R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1727	#define CAN_F8R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1728	#define CAN_F8R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1729	#define CAN_F8R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1730	#define CAN_F8R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1731	#define CAN_F8R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1732	#define CAN_F8R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1733	#define CAN_F8R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1734	#define CAN_F8R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1735	#define CAN_F8R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1736	#define CAN_F8R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1737	#define CAN_F8R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1738	#define CAN_F8R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1739	#define CAN_F8R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1740	#define CAN_F8R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1741	#define CAN_F8R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1742	#define CAN_F8R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1743	#define CAN_F8R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1744	#define CAN_F8R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1745	#define CAN_F8R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1746	#define CAN_F8R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1747
emilmont	77:869cf507173a	1748	/***************** Bit definition for CAN_F9R1 register *****************/
emilmont	77:869cf507173a	1749	#define CAN_F9R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1750	#define CAN_F9R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1751	#define CAN_F9R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1752	#define CAN_F9R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1753	#define CAN_F9R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1754	#define CAN_F9R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1755	#define CAN_F9R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1756	#define CAN_F9R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1757	#define CAN_F9R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1758	#define CAN_F9R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1759	#define CAN_F9R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1760	#define CAN_F9R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1761	#define CAN_F9R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1762	#define CAN_F9R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1763	#define CAN_F9R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1764	#define CAN_F9R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1765	#define CAN_F9R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1766	#define CAN_F9R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1767	#define CAN_F9R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1768	#define CAN_F9R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1769	#define CAN_F9R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1770	#define CAN_F9R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1771	#define CAN_F9R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1772	#define CAN_F9R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1773	#define CAN_F9R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1774	#define CAN_F9R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1775	#define CAN_F9R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1776	#define CAN_F9R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1777	#define CAN_F9R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1778	#define CAN_F9R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1779	#define CAN_F9R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1780	#define CAN_F9R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1781
emilmont	77:869cf507173a	1782	/***************** Bit definition for CAN_F10R1 register ****************/
emilmont	77:869cf507173a	1783	#define CAN_F10R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1784	#define CAN_F10R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1785	#define CAN_F10R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1786	#define CAN_F10R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1787	#define CAN_F10R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1788	#define CAN_F10R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1789	#define CAN_F10R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1790	#define CAN_F10R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1791	#define CAN_F10R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1792	#define CAN_F10R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1793	#define CAN_F10R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1794	#define CAN_F10R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1795	#define CAN_F10R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1796	#define CAN_F10R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1797	#define CAN_F10R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1798	#define CAN_F10R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1799	#define CAN_F10R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1800	#define CAN_F10R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1801	#define CAN_F10R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1802	#define CAN_F10R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1803	#define CAN_F10R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1804	#define CAN_F10R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1805	#define CAN_F10R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1806	#define CAN_F10R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1807	#define CAN_F10R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1808	#define CAN_F10R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1809	#define CAN_F10R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1810	#define CAN_F10R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1811	#define CAN_F10R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1812	#define CAN_F10R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1813	#define CAN_F10R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1814	#define CAN_F10R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1815
emilmont	77:869cf507173a	1816	/***************** Bit definition for CAN_F11R1 register ****************/
emilmont	77:869cf507173a	1817	#define CAN_F11R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1818	#define CAN_F11R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1819	#define CAN_F11R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1820	#define CAN_F11R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1821	#define CAN_F11R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1822	#define CAN_F11R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1823	#define CAN_F11R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1824	#define CAN_F11R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1825	#define CAN_F11R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1826	#define CAN_F11R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1827	#define CAN_F11R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1828	#define CAN_F11R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1829	#define CAN_F11R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1830	#define CAN_F11R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1831	#define CAN_F11R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1832	#define CAN_F11R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1833	#define CAN_F11R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1834	#define CAN_F11R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1835	#define CAN_F11R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1836	#define CAN_F11R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1837	#define CAN_F11R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1838	#define CAN_F11R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1839	#define CAN_F11R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1840	#define CAN_F11R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1841	#define CAN_F11R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1842	#define CAN_F11R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1843	#define CAN_F11R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1844	#define CAN_F11R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1845	#define CAN_F11R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1846	#define CAN_F11R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1847	#define CAN_F11R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1848	#define CAN_F11R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1849
emilmont	77:869cf507173a	1850	/***************** Bit definition for CAN_F12R1 register ****************/
emilmont	77:869cf507173a	1851	#define CAN_F12R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1852	#define CAN_F12R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1853	#define CAN_F12R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1854	#define CAN_F12R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1855	#define CAN_F12R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1856	#define CAN_F12R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1857	#define CAN_F12R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1858	#define CAN_F12R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1859	#define CAN_F12R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1860	#define CAN_F12R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1861	#define CAN_F12R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1862	#define CAN_F12R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1863	#define CAN_F12R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1864	#define CAN_F12R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1865	#define CAN_F12R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1866	#define CAN_F12R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1867	#define CAN_F12R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1868	#define CAN_F12R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1869	#define CAN_F12R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1870	#define CAN_F12R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1871	#define CAN_F12R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1872	#define CAN_F12R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1873	#define CAN_F12R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1874	#define CAN_F12R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1875	#define CAN_F12R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1876	#define CAN_F12R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1877	#define CAN_F12R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1878	#define CAN_F12R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1879	#define CAN_F12R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1880	#define CAN_F12R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1881	#define CAN_F12R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1882	#define CAN_F12R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1883
emilmont	77:869cf507173a	1884	/***************** Bit definition for CAN_F13R1 register ****************/
emilmont	77:869cf507173a	1885	#define CAN_F13R1_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1886	#define CAN_F13R1_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1887	#define CAN_F13R1_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1888	#define CAN_F13R1_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1889	#define CAN_F13R1_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1890	#define CAN_F13R1_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1891	#define CAN_F13R1_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1892	#define CAN_F13R1_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1893	#define CAN_F13R1_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1894	#define CAN_F13R1_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1895	#define CAN_F13R1_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1896	#define CAN_F13R1_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1897	#define CAN_F13R1_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1898	#define CAN_F13R1_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1899	#define CAN_F13R1_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1900	#define CAN_F13R1_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1901	#define CAN_F13R1_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1902	#define CAN_F13R1_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1903	#define CAN_F13R1_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1904	#define CAN_F13R1_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1905	#define CAN_F13R1_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1906	#define CAN_F13R1_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1907	#define CAN_F13R1_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1908	#define CAN_F13R1_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1909	#define CAN_F13R1_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1910	#define CAN_F13R1_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1911	#define CAN_F13R1_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1912	#define CAN_F13R1_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1913	#define CAN_F13R1_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1914	#define CAN_F13R1_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1915	#define CAN_F13R1_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1916	#define CAN_F13R1_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1917
emilmont	77:869cf507173a	1918	/***************** Bit definition for CAN_F0R2 register *****************/
emilmont	77:869cf507173a	1919	#define CAN_F0R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1920	#define CAN_F0R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1921	#define CAN_F0R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1922	#define CAN_F0R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1923	#define CAN_F0R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1924	#define CAN_F0R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1925	#define CAN_F0R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1926	#define CAN_F0R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1927	#define CAN_F0R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1928	#define CAN_F0R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1929	#define CAN_F0R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1930	#define CAN_F0R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1931	#define CAN_F0R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1932	#define CAN_F0R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1933	#define CAN_F0R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1934	#define CAN_F0R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1935	#define CAN_F0R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1936	#define CAN_F0R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1937	#define CAN_F0R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1938	#define CAN_F0R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1939	#define CAN_F0R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1940	#define CAN_F0R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1941	#define CAN_F0R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1942	#define CAN_F0R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1943	#define CAN_F0R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1944	#define CAN_F0R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1945	#define CAN_F0R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1946	#define CAN_F0R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1947	#define CAN_F0R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1948	#define CAN_F0R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1949	#define CAN_F0R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1950	#define CAN_F0R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1951
emilmont	77:869cf507173a	1952	/***************** Bit definition for CAN_F1R2 register *****************/
emilmont	77:869cf507173a	1953	#define CAN_F1R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1954	#define CAN_F1R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1955	#define CAN_F1R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1956	#define CAN_F1R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1957	#define CAN_F1R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1958	#define CAN_F1R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1959	#define CAN_F1R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1960	#define CAN_F1R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1961	#define CAN_F1R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1962	#define CAN_F1R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1963	#define CAN_F1R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1964	#define CAN_F1R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1965	#define CAN_F1R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	1966	#define CAN_F1R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	1967	#define CAN_F1R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	1968	#define CAN_F1R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	1969	#define CAN_F1R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	1970	#define CAN_F1R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	1971	#define CAN_F1R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	1972	#define CAN_F1R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	1973	#define CAN_F1R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	1974	#define CAN_F1R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	1975	#define CAN_F1R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	1976	#define CAN_F1R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	1977	#define CAN_F1R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	1978	#define CAN_F1R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	1979	#define CAN_F1R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	1980	#define CAN_F1R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	1981	#define CAN_F1R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	1982	#define CAN_F1R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	1983	#define CAN_F1R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	1984	#define CAN_F1R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	1985
emilmont	77:869cf507173a	1986	/***************** Bit definition for CAN_F2R2 register *****************/
emilmont	77:869cf507173a	1987	#define CAN_F2R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	1988	#define CAN_F2R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	1989	#define CAN_F2R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	1990	#define CAN_F2R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	1991	#define CAN_F2R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	1992	#define CAN_F2R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	1993	#define CAN_F2R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	1994	#define CAN_F2R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	1995	#define CAN_F2R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	1996	#define CAN_F2R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	1997	#define CAN_F2R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	1998	#define CAN_F2R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	1999	#define CAN_F2R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2000	#define CAN_F2R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2001	#define CAN_F2R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2002	#define CAN_F2R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2003	#define CAN_F2R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2004	#define CAN_F2R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2005	#define CAN_F2R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2006	#define CAN_F2R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2007	#define CAN_F2R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2008	#define CAN_F2R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2009	#define CAN_F2R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2010	#define CAN_F2R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2011	#define CAN_F2R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2012	#define CAN_F2R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2013	#define CAN_F2R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2014	#define CAN_F2R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2015	#define CAN_F2R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2016	#define CAN_F2R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2017	#define CAN_F2R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2018	#define CAN_F2R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2019
emilmont	77:869cf507173a	2020	/***************** Bit definition for CAN_F3R2 register *****************/
emilmont	77:869cf507173a	2021	#define CAN_F3R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2022	#define CAN_F3R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2023	#define CAN_F3R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2024	#define CAN_F3R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2025	#define CAN_F3R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2026	#define CAN_F3R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2027	#define CAN_F3R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2028	#define CAN_F3R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2029	#define CAN_F3R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2030	#define CAN_F3R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2031	#define CAN_F3R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2032	#define CAN_F3R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2033	#define CAN_F3R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2034	#define CAN_F3R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2035	#define CAN_F3R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2036	#define CAN_F3R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2037	#define CAN_F3R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2038	#define CAN_F3R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2039	#define CAN_F3R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2040	#define CAN_F3R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2041	#define CAN_F3R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2042	#define CAN_F3R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2043	#define CAN_F3R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2044	#define CAN_F3R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2045	#define CAN_F3R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2046	#define CAN_F3R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2047	#define CAN_F3R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2048	#define CAN_F3R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2049	#define CAN_F3R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2050	#define CAN_F3R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2051	#define CAN_F3R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2052	#define CAN_F3R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2053
emilmont	77:869cf507173a	2054	/***************** Bit definition for CAN_F4R2 register *****************/
emilmont	77:869cf507173a	2055	#define CAN_F4R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2056	#define CAN_F4R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2057	#define CAN_F4R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2058	#define CAN_F4R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2059	#define CAN_F4R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2060	#define CAN_F4R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2061	#define CAN_F4R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2062	#define CAN_F4R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2063	#define CAN_F4R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2064	#define CAN_F4R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2065	#define CAN_F4R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2066	#define CAN_F4R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2067	#define CAN_F4R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2068	#define CAN_F4R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2069	#define CAN_F4R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2070	#define CAN_F4R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2071	#define CAN_F4R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2072	#define CAN_F4R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2073	#define CAN_F4R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2074	#define CAN_F4R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2075	#define CAN_F4R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2076	#define CAN_F4R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2077	#define CAN_F4R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2078	#define CAN_F4R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2079	#define CAN_F4R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2080	#define CAN_F4R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2081	#define CAN_F4R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2082	#define CAN_F4R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2083	#define CAN_F4R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2084	#define CAN_F4R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2085	#define CAN_F4R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2086	#define CAN_F4R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2087
emilmont	77:869cf507173a	2088	/***************** Bit definition for CAN_F5R2 register *****************/
emilmont	77:869cf507173a	2089	#define CAN_F5R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2090	#define CAN_F5R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2091	#define CAN_F5R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2092	#define CAN_F5R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2093	#define CAN_F5R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2094	#define CAN_F5R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2095	#define CAN_F5R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2096	#define CAN_F5R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2097	#define CAN_F5R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2098	#define CAN_F5R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2099	#define CAN_F5R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2100	#define CAN_F5R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2101	#define CAN_F5R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2102	#define CAN_F5R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2103	#define CAN_F5R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2104	#define CAN_F5R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2105	#define CAN_F5R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2106	#define CAN_F5R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2107	#define CAN_F5R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2108	#define CAN_F5R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2109	#define CAN_F5R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2110	#define CAN_F5R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2111	#define CAN_F5R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2112	#define CAN_F5R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2113	#define CAN_F5R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2114	#define CAN_F5R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2115	#define CAN_F5R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2116	#define CAN_F5R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2117	#define CAN_F5R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2118	#define CAN_F5R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2119	#define CAN_F5R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2120	#define CAN_F5R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2121
emilmont	77:869cf507173a	2122	/***************** Bit definition for CAN_F6R2 register *****************/
emilmont	77:869cf507173a	2123	#define CAN_F6R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2124	#define CAN_F6R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2125	#define CAN_F6R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2126	#define CAN_F6R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2127	#define CAN_F6R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2128	#define CAN_F6R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2129	#define CAN_F6R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2130	#define CAN_F6R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2131	#define CAN_F6R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2132	#define CAN_F6R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2133	#define CAN_F6R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2134	#define CAN_F6R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2135	#define CAN_F6R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2136	#define CAN_F6R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2137	#define CAN_F6R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2138	#define CAN_F6R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2139	#define CAN_F6R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2140	#define CAN_F6R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2141	#define CAN_F6R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2142	#define CAN_F6R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2143	#define CAN_F6R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2144	#define CAN_F6R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2145	#define CAN_F6R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2146	#define CAN_F6R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2147	#define CAN_F6R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2148	#define CAN_F6R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2149	#define CAN_F6R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2150	#define CAN_F6R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2151	#define CAN_F6R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2152	#define CAN_F6R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2153	#define CAN_F6R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2154	#define CAN_F6R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2155
emilmont	77:869cf507173a	2156	/***************** Bit definition for CAN_F7R2 register *****************/
emilmont	77:869cf507173a	2157	#define CAN_F7R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2158	#define CAN_F7R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2159	#define CAN_F7R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2160	#define CAN_F7R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2161	#define CAN_F7R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2162	#define CAN_F7R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2163	#define CAN_F7R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2164	#define CAN_F7R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2165	#define CAN_F7R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2166	#define CAN_F7R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2167	#define CAN_F7R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2168	#define CAN_F7R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2169	#define CAN_F7R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2170	#define CAN_F7R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2171	#define CAN_F7R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2172	#define CAN_F7R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2173	#define CAN_F7R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2174	#define CAN_F7R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2175	#define CAN_F7R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2176	#define CAN_F7R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2177	#define CAN_F7R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2178	#define CAN_F7R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2179	#define CAN_F7R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2180	#define CAN_F7R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2181	#define CAN_F7R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2182	#define CAN_F7R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2183	#define CAN_F7R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2184	#define CAN_F7R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2185	#define CAN_F7R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2186	#define CAN_F7R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2187	#define CAN_F7R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2188	#define CAN_F7R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2189
emilmont	77:869cf507173a	2190	/***************** Bit definition for CAN_F8R2 register *****************/
emilmont	77:869cf507173a	2191	#define CAN_F8R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2192	#define CAN_F8R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2193	#define CAN_F8R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2194	#define CAN_F8R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2195	#define CAN_F8R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2196	#define CAN_F8R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2197	#define CAN_F8R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2198	#define CAN_F8R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2199	#define CAN_F8R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2200	#define CAN_F8R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2201	#define CAN_F8R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2202	#define CAN_F8R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2203	#define CAN_F8R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2204	#define CAN_F8R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2205	#define CAN_F8R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2206	#define CAN_F8R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2207	#define CAN_F8R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2208	#define CAN_F8R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2209	#define CAN_F8R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2210	#define CAN_F8R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2211	#define CAN_F8R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2212	#define CAN_F8R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2213	#define CAN_F8R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2214	#define CAN_F8R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2215	#define CAN_F8R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2216	#define CAN_F8R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2217	#define CAN_F8R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2218	#define CAN_F8R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2219	#define CAN_F8R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2220	#define CAN_F8R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2221	#define CAN_F8R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2222	#define CAN_F8R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2223
emilmont	77:869cf507173a	2224	/***************** Bit definition for CAN_F9R2 register *****************/
emilmont	77:869cf507173a	2225	#define CAN_F9R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2226	#define CAN_F9R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2227	#define CAN_F9R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2228	#define CAN_F9R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2229	#define CAN_F9R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2230	#define CAN_F9R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2231	#define CAN_F9R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2232	#define CAN_F9R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2233	#define CAN_F9R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2234	#define CAN_F9R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2235	#define CAN_F9R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2236	#define CAN_F9R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2237	#define CAN_F9R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2238	#define CAN_F9R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2239	#define CAN_F9R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2240	#define CAN_F9R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2241	#define CAN_F9R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2242	#define CAN_F9R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2243	#define CAN_F9R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2244	#define CAN_F9R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2245	#define CAN_F9R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2246	#define CAN_F9R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2247	#define CAN_F9R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2248	#define CAN_F9R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2249	#define CAN_F9R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2250	#define CAN_F9R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2251	#define CAN_F9R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2252	#define CAN_F9R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2253	#define CAN_F9R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2254	#define CAN_F9R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2255	#define CAN_F9R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2256	#define CAN_F9R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2257
emilmont	77:869cf507173a	2258	/***************** Bit definition for CAN_F10R2 register ****************/
emilmont	77:869cf507173a	2259	#define CAN_F10R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2260	#define CAN_F10R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2261	#define CAN_F10R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2262	#define CAN_F10R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2263	#define CAN_F10R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2264	#define CAN_F10R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2265	#define CAN_F10R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2266	#define CAN_F10R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2267	#define CAN_F10R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2268	#define CAN_F10R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2269	#define CAN_F10R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2270	#define CAN_F10R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2271	#define CAN_F10R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2272	#define CAN_F10R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2273	#define CAN_F10R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2274	#define CAN_F10R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2275	#define CAN_F10R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2276	#define CAN_F10R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2277	#define CAN_F10R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2278	#define CAN_F10R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2279	#define CAN_F10R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2280	#define CAN_F10R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2281	#define CAN_F10R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2282	#define CAN_F10R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2283	#define CAN_F10R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2284	#define CAN_F10R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2285	#define CAN_F10R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2286	#define CAN_F10R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2287	#define CAN_F10R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2288	#define CAN_F10R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2289	#define CAN_F10R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2290	#define CAN_F10R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2291
emilmont	77:869cf507173a	2292	/***************** Bit definition for CAN_F11R2 register ****************/
emilmont	77:869cf507173a	2293	#define CAN_F11R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2294	#define CAN_F11R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2295	#define CAN_F11R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2296	#define CAN_F11R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2297	#define CAN_F11R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2298	#define CAN_F11R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2299	#define CAN_F11R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2300	#define CAN_F11R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2301	#define CAN_F11R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2302	#define CAN_F11R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2303	#define CAN_F11R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2304	#define CAN_F11R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2305	#define CAN_F11R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2306	#define CAN_F11R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2307	#define CAN_F11R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2308	#define CAN_F11R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2309	#define CAN_F11R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2310	#define CAN_F11R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2311	#define CAN_F11R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2312	#define CAN_F11R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2313	#define CAN_F11R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2314	#define CAN_F11R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2315	#define CAN_F11R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2316	#define CAN_F11R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2317	#define CAN_F11R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2318	#define CAN_F11R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2319	#define CAN_F11R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2320	#define CAN_F11R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2321	#define CAN_F11R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2322	#define CAN_F11R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2323	#define CAN_F11R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2324	#define CAN_F11R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2325
emilmont	77:869cf507173a	2326	/***************** Bit definition for CAN_F12R2 register ****************/
emilmont	77:869cf507173a	2327	#define CAN_F12R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2328	#define CAN_F12R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2329	#define CAN_F12R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2330	#define CAN_F12R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2331	#define CAN_F12R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2332	#define CAN_F12R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2333	#define CAN_F12R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2334	#define CAN_F12R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2335	#define CAN_F12R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2336	#define CAN_F12R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2337	#define CAN_F12R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2338	#define CAN_F12R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2339	#define CAN_F12R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2340	#define CAN_F12R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2341	#define CAN_F12R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2342	#define CAN_F12R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2343	#define CAN_F12R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2344	#define CAN_F12R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2345	#define CAN_F12R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2346	#define CAN_F12R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2347	#define CAN_F12R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2348	#define CAN_F12R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2349	#define CAN_F12R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2350	#define CAN_F12R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2351	#define CAN_F12R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2352	#define CAN_F12R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2353	#define CAN_F12R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2354	#define CAN_F12R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2355	#define CAN_F12R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2356	#define CAN_F12R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2357	#define CAN_F12R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2358	#define CAN_F12R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2359
emilmont	77:869cf507173a	2360	/***************** Bit definition for CAN_F13R2 register ****************/
emilmont	77:869cf507173a	2361	#define CAN_F13R2_FB0 ((uint32_t)0x00000001) /!<Filter bit 0 /
emilmont	77:869cf507173a	2362	#define CAN_F13R2_FB1 ((uint32_t)0x00000002) /!<Filter bit 1 /
emilmont	77:869cf507173a	2363	#define CAN_F13R2_FB2 ((uint32_t)0x00000004) /!<Filter bit 2 /
emilmont	77:869cf507173a	2364	#define CAN_F13R2_FB3 ((uint32_t)0x00000008) /!<Filter bit 3 /
emilmont	77:869cf507173a	2365	#define CAN_F13R2_FB4 ((uint32_t)0x00000010) /!<Filter bit 4 /
emilmont	77:869cf507173a	2366	#define CAN_F13R2_FB5 ((uint32_t)0x00000020) /!<Filter bit 5 /
emilmont	77:869cf507173a	2367	#define CAN_F13R2_FB6 ((uint32_t)0x00000040) /!<Filter bit 6 /
emilmont	77:869cf507173a	2368	#define CAN_F13R2_FB7 ((uint32_t)0x00000080) /!<Filter bit 7 /
emilmont	77:869cf507173a	2369	#define CAN_F13R2_FB8 ((uint32_t)0x00000100) /!<Filter bit 8 /
emilmont	77:869cf507173a	2370	#define CAN_F13R2_FB9 ((uint32_t)0x00000200) /!<Filter bit 9 /
emilmont	77:869cf507173a	2371	#define CAN_F13R2_FB10 ((uint32_t)0x00000400) /!<Filter bit 10 /
emilmont	77:869cf507173a	2372	#define CAN_F13R2_FB11 ((uint32_t)0x00000800) /!<Filter bit 11 /
emilmont	77:869cf507173a	2373	#define CAN_F13R2_FB12 ((uint32_t)0x00001000) /!<Filter bit 12 /
emilmont	77:869cf507173a	2374	#define CAN_F13R2_FB13 ((uint32_t)0x00002000) /!<Filter bit 13 /
emilmont	77:869cf507173a	2375	#define CAN_F13R2_FB14 ((uint32_t)0x00004000) /!<Filter bit 14 /
emilmont	77:869cf507173a	2376	#define CAN_F13R2_FB15 ((uint32_t)0x00008000) /!<Filter bit 15 /
emilmont	77:869cf507173a	2377	#define CAN_F13R2_FB16 ((uint32_t)0x00010000) /!<Filter bit 16 /
emilmont	77:869cf507173a	2378	#define CAN_F13R2_FB17 ((uint32_t)0x00020000) /!<Filter bit 17 /
emilmont	77:869cf507173a	2379	#define CAN_F13R2_FB18 ((uint32_t)0x00040000) /!<Filter bit 18 /
emilmont	77:869cf507173a	2380	#define CAN_F13R2_FB19 ((uint32_t)0x00080000) /!<Filter bit 19 /
emilmont	77:869cf507173a	2381	#define CAN_F13R2_FB20 ((uint32_t)0x00100000) /!<Filter bit 20 /
emilmont	77:869cf507173a	2382	#define CAN_F13R2_FB21 ((uint32_t)0x00200000) /!<Filter bit 21 /
emilmont	77:869cf507173a	2383	#define CAN_F13R2_FB22 ((uint32_t)0x00400000) /!<Filter bit 22 /
emilmont	77:869cf507173a	2384	#define CAN_F13R2_FB23 ((uint32_t)0x00800000) /!<Filter bit 23 /
emilmont	77:869cf507173a	2385	#define CAN_F13R2_FB24 ((uint32_t)0x01000000) /!<Filter bit 24 /
emilmont	77:869cf507173a	2386	#define CAN_F13R2_FB25 ((uint32_t)0x02000000) /!<Filter bit 25 /
emilmont	77:869cf507173a	2387	#define CAN_F13R2_FB26 ((uint32_t)0x04000000) /!<Filter bit 26 /
emilmont	77:869cf507173a	2388	#define CAN_F13R2_FB27 ((uint32_t)0x08000000) /!<Filter bit 27 /
emilmont	77:869cf507173a	2389	#define CAN_F13R2_FB28 ((uint32_t)0x10000000) /!<Filter bit 28 /
emilmont	77:869cf507173a	2390	#define CAN_F13R2_FB29 ((uint32_t)0x20000000) /!<Filter bit 29 /
emilmont	77:869cf507173a	2391	#define CAN_F13R2_FB30 ((uint32_t)0x40000000) /!<Filter bit 30 /
emilmont	77:869cf507173a	2392	#define CAN_F13R2_FB31 ((uint32_t)0x80000000) /!<Filter bit 31 /
emilmont	77:869cf507173a	2393
emilmont	77:869cf507173a	2394
emilmont	77:869cf507173a	2395	/******************************************************************************/
emilmont	77:869cf507173a	2396	/* */
emilmont	77:869cf507173a	2397	/* HDMI-CEC (CEC) */
emilmont	77:869cf507173a	2398	/* */
emilmont	77:869cf507173a	2399	/******************************************************************************/
emilmont	77:869cf507173a	2400
emilmont	77:869cf507173a	2401	/***************** Bit definition for CEC_CR register *******************/
emilmont	77:869cf507173a	2402	#define CEC_CR_CECEN ((uint32_t)0x00000001) /!< CEC Enable /
emilmont	77:869cf507173a	2403	#define CEC_CR_TXSOM ((uint32_t)0x00000002) /!< CEC Tx Start Of Message /
emilmont	77:869cf507173a	2404	#define CEC_CR_TXEOM ((uint32_t)0x00000004) /!< CEC Tx End Of Message /
emilmont	77:869cf507173a	2405
emilmont	77:869cf507173a	2406	/***************** Bit definition for CEC_CFGR register *****************/
emilmont	77:869cf507173a	2407	#define CEC_CFGR_SFT ((uint32_t)0x00000007) /!< CEC Signal Free Time /
emilmont	77:869cf507173a	2408	#define CEC_CFGR_RXTOL ((uint32_t)0x00000008) /!< CEC Tolerance /
emilmont	77:869cf507173a	2409	#define CEC_CFGR_BRESTP ((uint32_t)0x00000010) /!< CEC Rx Stop /
emilmont	77:869cf507173a	2410	#define CEC_CFGR_BREGEN ((uint32_t)0x00000020) /!< CEC Bit Rising Error generation /
emilmont	77:869cf507173a	2411	#define CEC_CFGR_LREGEN ((uint32_t)0x00000040) /!< CEC Long Period Error generation /
emilmont	77:869cf507173a	2412	#define CEC_CFGR_BRDNOGEN ((uint32_t)0x00000080) /!< CEC Broadcast no Error generation /
emilmont	77:869cf507173a	2413	#define CEC_CFGR_SFTOPT ((uint32_t)0x00000100) /!< CEC Signal Free Time optional /
emilmont	77:869cf507173a	2414	#define CEC_CFGR_OAR ((uint32_t)0x7FFF0000) /!< CEC Own Address /
emilmont	77:869cf507173a	2415	#define CEC_CFGR_LSTN ((uint32_t)0x80000000) /!< CEC Listen mode /
emilmont	77:869cf507173a	2416
emilmont	77:869cf507173a	2417	/***************** Bit definition for CEC_TXDR register *****************/
emilmont	77:869cf507173a	2418	#define CEC_TXDR_TXD ((uint32_t)0x000000FF) /!< CEC Tx Data /
emilmont	77:869cf507173a	2419
emilmont	77:869cf507173a	2420	/***************** Bit definition for CEC_RXDR register *****************/
emilmont	77:869cf507173a	2421	#define CEC_TXDR_RXD ((uint32_t)0x000000FF) /!< CEC Rx Data /
emilmont	77:869cf507173a	2422
emilmont	77:869cf507173a	2423	/***************** Bit definition for CEC_ISR register ******************/
emilmont	77:869cf507173a	2424	#define CEC_ISR_RXBR ((uint32_t)0x00000001) /!< CEC Rx-Byte Received /
emilmont	77:869cf507173a	2425	#define CEC_ISR_RXEND ((uint32_t)0x00000002) /!< CEC End Of Reception /
emilmont	77:869cf507173a	2426	#define CEC_ISR_RXOVR ((uint32_t)0x00000004) /!< CEC Rx-Overrun /
emilmont	77:869cf507173a	2427	#define CEC_ISR_BRE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error /
emilmont	77:869cf507173a	2428	#define CEC_ISR_SBPE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error /
emilmont	77:869cf507173a	2429	#define CEC_ISR_LBPE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error /
emilmont	77:869cf507173a	2430	#define CEC_ISR_RXACKE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge /
emilmont	77:869cf507173a	2431	#define CEC_ISR_ARBLST ((uint32_t)0x00000080) /!< CEC Arbitration Lost /
emilmont	77:869cf507173a	2432	#define CEC_ISR_TXBR ((uint32_t)0x00000100) /!< CEC Tx Byte Request /
emilmont	77:869cf507173a	2433	#define CEC_ISR_TXEND ((uint32_t)0x00000200) /!< CEC End of Transmission /
emilmont	77:869cf507173a	2434	#define CEC_ISR_TXUDR ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun /
emilmont	77:869cf507173a	2435	#define CEC_ISR_TXERR ((uint32_t)0x00000800) /!< CEC Tx-Error /
emilmont	77:869cf507173a	2436	#define CEC_ISR_TXACKE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge /
emilmont	77:869cf507173a	2437
emilmont	77:869cf507173a	2438	/***************** Bit definition for CEC_IER register ******************/
emilmont	77:869cf507173a	2439	#define CEC_IER_RXBRIE ((uint32_t)0x00000001) /!< CEC Rx-Byte Received IT Enable /
emilmont	77:869cf507173a	2440	#define CEC_IER_RXENDIE ((uint32_t)0x00000002) /!< CEC End Of Reception IT Enable /
emilmont	77:869cf507173a	2441	#define CEC_IER_RXOVRIE ((uint32_t)0x00000004) /!< CEC Rx-Overrun IT Enable /
emilmont	77:869cf507173a	2442	#define CEC_IER_BREIEIE ((uint32_t)0x00000008) /!< CEC Rx Bit Rising Error IT Enable /
emilmont	77:869cf507173a	2443	#define CEC_IER_SBPEIE ((uint32_t)0x00000010) /!< CEC Rx Short Bit period Error IT Enable/
emilmont	77:869cf507173a	2444	#define CEC_IER_LBPEIE ((uint32_t)0x00000020) /!< CEC Rx Long Bit period Error IT Enable /
emilmont	77:869cf507173a	2445	#define CEC_IER_RXACKEIE ((uint32_t)0x00000040) /!< CEC Rx Missing Acknowledge IT Enable /
emilmont	77:869cf507173a	2446	#define CEC_IER_ARBLSTIE ((uint32_t)0x00000080) /!< CEC Arbitration Lost IT Enable /
emilmont	77:869cf507173a	2447	#define CEC_IER_TXBRIE ((uint32_t)0x00000100) /!< CEC Tx Byte Request IT Enable /
emilmont	77:869cf507173a	2448	#define CEC_IER_TXENDIE ((uint32_t)0x00000200) /!< CEC End of Transmission IT Enable /
emilmont	77:869cf507173a	2449	#define CEC_IER_TXUDRIE ((uint32_t)0x00000400) /!< CEC Tx-Buffer Underrun IT Enable /
emilmont	77:869cf507173a	2450	#define CEC_IER_TXERRIE ((uint32_t)0x00000800) /!< CEC Tx-Error IT Enable /
emilmont	77:869cf507173a	2451	#define CEC_IER_TXACKEIE ((uint32_t)0x00001000) /!< CEC Tx Missing Acknowledge IT Enable /
emilmont	77:869cf507173a	2452
emilmont	77:869cf507173a	2453	/******************************************************************************/
emilmont	77:869cf507173a	2454	/* */
emilmont	77:869cf507173a	2455	/* Analog Comparators (COMP) */
emilmont	77:869cf507173a	2456	/* */
emilmont	77:869cf507173a	2457	/******************************************************************************/
emilmont	77:869cf507173a	2458	/********************* Bit definition for COMP_CSR register *************/
emilmont	77:869cf507173a	2459	/* COMP1 bits definition */
emilmont	77:869cf507173a	2460	#define COMP_CSR_COMP1EN ((uint32_t)0x00000001) /!< COMP1 enable /
emilmont	77:869cf507173a	2461	#define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /!< SW1 switch control /
emilmont	77:869cf507173a	2462	#define COMP_CSR_COMP1MODE ((uint32_t)0x0000000C) /!< COMP1 power mode /
emilmont	77:869cf507173a	2463	#define COMP_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /!< COMP1 power mode bit 0 /
emilmont	77:869cf507173a	2464	#define COMP_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /!< COMP1 power mode bit 1 /
emilmont	77:869cf507173a	2465	#define COMP_CSR_COMP1INSEL ((uint32_t)0x00000070) /!< COMP1 inverting input select /
emilmont	77:869cf507173a	2466	#define COMP_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /!< COMP1 inverting input select bit 0 /
emilmont	77:869cf507173a	2467	#define COMP_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /!< COMP1 inverting input select bit 1 /
emilmont	77:869cf507173a	2468	#define COMP_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /!< COMP1 inverting input select bit 2 /
emilmont	77:869cf507173a	2469	#define COMP_CSR_COMP1OUTSEL ((uint32_t)0x00000700) /!< COMP1 output select /
emilmont	77:869cf507173a	2470	#define COMP_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000100) /!< COMP1 output select bit 0 /
emilmont	77:869cf507173a	2471	#define COMP_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000200) /!< COMP1 output select bit 1 /
emilmont	77:869cf507173a	2472	#define COMP_CSR_COMP1OUTSEL_2 ((uint32_t)0x00000400) /!< COMP1 output select bit 2 /
emilmont	77:869cf507173a	2473	#define COMP_CSR_COMP1POL ((uint32_t)0x00000800) /!< COMP1 output polarity /
emilmont	77:869cf507173a	2474	#define COMP_CSR_COMP1HYST ((uint32_t)0x00003000) /!< COMP1 hysteresis /
emilmont	77:869cf507173a	2475	#define COMP_CSR_COMP1HYST_0 ((uint32_t)0x00001000) /!< COMP1 hysteresis bit 0 /
emilmont	77:869cf507173a	2476	#define COMP_CSR_COMP1HYST_1 ((uint32_t)0x00002000) /!< COMP1 hysteresis bit 1 /
emilmont	77:869cf507173a	2477	#define COMP_CSR_COMP1OUT ((uint32_t)0x00004000) /!< COMP1 output level /
emilmont	77:869cf507173a	2478	#define COMP_CSR_COMP1LOCK ((uint32_t)0x00008000) /!< COMP1 lock /
emilmont	77:869cf507173a	2479	/* COMP2 bits definition */
emilmont	77:869cf507173a	2480	#define COMP_CSR_COMP2EN ((uint32_t)0x00010000) /!< COMP2 enable /
emilmont	77:869cf507173a	2481	#define COMP_CSR_COMP2MODE ((uint32_t)0x000C0000) /!< COMP2 power mode /
emilmont	77:869cf507173a	2482	#define COMP_CSR_COMP2MODE_0 ((uint32_t)0x00040000) /!< COMP2 power mode bit 0 /
emilmont	77:869cf507173a	2483	#define COMP_CSR_COMP2MODE_1 ((uint32_t)0x00080000) /!< COMP2 power mode bit 1 /
emilmont	77:869cf507173a	2484	#define COMP_CSR_COMP2INSEL ((uint32_t)0x00700000) /!< COMP2 inverting input select /
emilmont	77:869cf507173a	2485	#define COMP_CSR_COMP2INSEL_0 ((uint32_t)0x00100000) /!< COMP2 inverting input select bit 0 /
emilmont	77:869cf507173a	2486	#define COMP_CSR_COMP2INSEL_1 ((uint32_t)0x00200000) /!< COMP2 inverting input select bit 1 /
emilmont	77:869cf507173a	2487	#define COMP_CSR_COMP2INSEL_2 ((uint32_t)0x00400000) /!< COMP2 inverting input select bit 2 /
emilmont	77:869cf507173a	2488	#define COMP_CSR_WNDWEN ((uint32_t)0x00800000) /!< Comparators window mode enable /
emilmont	77:869cf507173a	2489	#define COMP_CSR_COMP2OUTSEL ((uint32_t)0x07000000) /!< COMP2 output select /
emilmont	77:869cf507173a	2490	#define COMP_CSR_COMP2OUTSEL_0 ((uint32_t)0x01000000) /!< COMP2 output select bit 0 /
emilmont	77:869cf507173a	2491	#define COMP_CSR_COMP2OUTSEL_1 ((uint32_t)0x02000000) /!< COMP2 output select bit 1 /
emilmont	77:869cf507173a	2492	#define COMP_CSR_COMP2OUTSEL_2 ((uint32_t)0x04000000) /!< COMP2 output select bit 2 /
emilmont	77:869cf507173a	2493	#define COMP_CSR_COMP2POL ((uint32_t)0x08000000) /!< COMP2 output polarity /
emilmont	77:869cf507173a	2494	#define COMP_CSR_COMP2HYST ((uint32_t)0x30000000) /!< COMP2 hysteresis /
emilmont	77:869cf507173a	2495	#define COMP_CSR_COMP2HYST_0 ((uint32_t)0x10000000) /!< COMP2 hysteresis bit 0 /
emilmont	77:869cf507173a	2496	#define COMP_CSR_COMP2HYST_1 ((uint32_t)0x20000000) /!< COMP2 hysteresis bit 1 /
emilmont	77:869cf507173a	2497	#define COMP_CSR_COMP2OUT ((uint32_t)0x40000000) /!< COMP2 output level /
emilmont	77:869cf507173a	2498	#define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000) /!< COMP2 lock /
emilmont	77:869cf507173a	2499
emilmont	77:869cf507173a	2500	/******************************************************************************/
emilmont	77:869cf507173a	2501	/* */
emilmont	77:869cf507173a	2502	/* CRC calculation unit (CRC) */
emilmont	77:869cf507173a	2503	/* */
emilmont	77:869cf507173a	2504	/******************************************************************************/
emilmont	77:869cf507173a	2505	/***************** Bit definition for CRC_DR register *******************/
emilmont	77:869cf507173a	2506	#define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /!< Data register bits /
emilmont	77:869cf507173a	2507
emilmont	77:869cf507173a	2508	/***************** Bit definition for CRC_IDR register ******************/
emilmont	77:869cf507173a	2509	#define CRC_IDR_IDR ((uint8_t)0xFF) /!< General-purpose 8-bit data register bits /
emilmont	77:869cf507173a	2510
emilmont	77:869cf507173a	2511	/****************** Bit definition for CRC_CR register ******************/
emilmont	77:869cf507173a	2512	#define CRC_CR_RESET ((uint32_t)0x00000001) /!< RESET the CRC computation unit bit /
emilmont	77:869cf507173a	2513	#define CRC_CR_POLSIZE ((uint32_t)0x00000018) /!< Polynomial size bits (only for STM32F072 devices)/
emilmont	77:869cf507173a	2514	#define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /!< Polynomial size bit 0 (only for STM32F072 devices) /
emilmont	77:869cf507173a	2515	#define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /!< Polynomial size bit 1 (only for STM32F072 devices) /
emilmont	77:869cf507173a	2516	#define CRC_CR_REV_IN ((uint32_t)0x00000060) /!< REV_IN Reverse Input Data bits /
emilmont	77:869cf507173a	2517	#define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /!< REV_IN Bit 0 /
emilmont	77:869cf507173a	2518	#define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /!< REV_IN Bit 1 /
emilmont	77:869cf507173a	2519	#define CRC_CR_REV_OUT ((uint32_t)0x00000080) /!< REV_OUT Reverse Output Data bits /
emilmont	77:869cf507173a	2520
emilmont	77:869cf507173a	2521	/***************** Bit definition for CRC_INIT register *****************/
emilmont	77:869cf507173a	2522	#define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /!< Initial CRC value bits /
emilmont	77:869cf507173a	2523
emilmont	77:869cf507173a	2524	/***************** Bit definition for CRC_POL register ******************/
emilmont	77:869cf507173a	2525	#define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /!< Coefficients of the polynomial (only for STM32F072 devices) /
emilmont	77:869cf507173a	2526
emilmont	77:869cf507173a	2527	/******************************************************************************/
emilmont	77:869cf507173a	2528	/* */
emilmont	77:869cf507173a	2529	/* CRS Clock Recovery System */
emilmont	77:869cf507173a	2530	/* (Available only for STM32F072 devices) */
emilmont	77:869cf507173a	2531	/******************************************************************************/
emilmont	77:869cf507173a	2532
emilmont	77:869cf507173a	2533	/***************** Bit definition for CRS_CR register *******************/
emilmont	77:869cf507173a	2534	#define CRS_CR_SYNCOKIE ((uint32_t)0x00000001) /* SYNC event OK interrupt enable */
emilmont	77:869cf507173a	2535	#define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002) /* SYNC warning interrupt enable */
emilmont	77:869cf507173a	2536	#define CRS_CR_ERRIE ((uint32_t)0x00000004) /* SYNC error interrupt enable */
emilmont	77:869cf507173a	2537	#define CRS_CR_ESYNCIE ((uint32_t)0x00000008) /* Expected SYNC(ESYNCF) interrupt Enable*/
emilmont	77:869cf507173a	2538	#define CRS_CR_CEN ((uint32_t)0x00000020) /* Frequency error counter enable */
emilmont	77:869cf507173a	2539	#define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040) /* Automatic trimming enable */
emilmont	77:869cf507173a	2540	#define CRS_CR_SWSYNC ((uint32_t)0x00000080) /* A Software SYNC event is generated */
emilmont	77:869cf507173a	2541	#define CRS_CR_TRIM ((uint32_t)0x00003F00) /* HSI48 oscillator smooth trimming */
emilmont	77:869cf507173a	2542
emilmont	77:869cf507173a	2543	/***************** Bit definition for CRS_CFGR register *******************/
emilmont	77:869cf507173a	2544	#define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFF) /* Counter reload value */
emilmont	77:869cf507173a	2545	#define CRS_CFGR_FELIM ((uint32_t)0x00FF0000) /* Frequency error limit */
emilmont	77:869cf507173a	2546	#define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000) /* SYNC divider */
emilmont	77:869cf507173a	2547	#define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000) /* Bit 0 */
emilmont	77:869cf507173a	2548	#define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000) /* Bit 1 */
emilmont	77:869cf507173a	2549	#define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000) /* Bit 2 */
emilmont	77:869cf507173a	2550	#define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000) /* SYNC signal source selection */
emilmont	77:869cf507173a	2551	#define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000) /* Bit 0 */
emilmont	77:869cf507173a	2552	#define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000) /* Bit 1 */
emilmont	77:869cf507173a	2553	#define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000) /* SYNC polarity selection */
emilmont	77:869cf507173a	2554
emilmont	77:869cf507173a	2555	/***************** Bit definition for CRS_ISR register *******************/
emilmont	77:869cf507173a	2556	#define CRS_ISR_SYNCOKF ((uint32_t)0x00000001) /* SYNC event OK flag */
emilmont	77:869cf507173a	2557	#define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002) /* SYNC warning */
emilmont	77:869cf507173a	2558	#define CRS_ISR_ERRF ((uint32_t)0x00000004) /* SYNC error flag */
emilmont	77:869cf507173a	2559	#define CRS_ISR_ESYNCF ((uint32_t)0x00000008) /* Expected SYNC flag */
emilmont	77:869cf507173a	2560	#define CRS_ISR_SYNCERR ((uint32_t)0x00000100) /* SYNC error */
emilmont	77:869cf507173a	2561	#define CRS_ISR_SYNCMISS ((uint32_t)0x00000200) /* SYNC missed */
emilmont	77:869cf507173a	2562	#define CRS_ISR_TRIMOVF ((uint32_t)0x00000400) /* Trimming overflow or underflow */
emilmont	77:869cf507173a	2563	#define CRS_ISR_FEDIR ((uint32_t)0x00008000) /* Frequency error direction */
emilmont	77:869cf507173a	2564	#define CRS_ISR_FECAP ((uint32_t)0xFFFF0000) /* Frequency error capture */
emilmont	77:869cf507173a	2565
emilmont	77:869cf507173a	2566	/***************** Bit definition for CRS_ICR register *******************/
emilmont	77:869cf507173a	2567	#define CRS_ICR_SYNCOKC ((uint32_t)0x00000001) /* SYNC event OK clear flag */
emilmont	77:869cf507173a	2568	#define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002) /* SYNC warning clear flag */
emilmont	77:869cf507173a	2569	#define CRS_ICR_ERRC ((uint32_t)0x00000004) /* Error clear flag */
emilmont	77:869cf507173a	2570	#define CRS_ICR_ESYNCC ((uint32_t)0x00000008) /* Expected SYNC clear flag */
emilmont	77:869cf507173a	2571
emilmont	77:869cf507173a	2572	/******************************************************************************/
emilmont	77:869cf507173a	2573	/* */
emilmont	77:869cf507173a	2574	/* Digital to Analog Converter (DAC) */
emilmont	77:869cf507173a	2575	/* */
emilmont	77:869cf507173a	2576	/******************************************************************************/
emilmont	77:869cf507173a	2577	/****************** Bit definition for DAC_CR register ******************/
emilmont	77:869cf507173a	2578	#define DAC_CR_EN1 ((uint32_t)0x00000001) /!< DAC channel1 enable /
emilmont	77:869cf507173a	2579	#define DAC_CR_BOFF1 ((uint32_t)0x00000002) /!< DAC channel1 output buffer disable /
emilmont	77:869cf507173a	2580	#define DAC_CR_TEN1 ((uint32_t)0x00000004) /!< DAC channel1 Trigger enable /
emilmont	77:869cf507173a	2581
emilmont	77:869cf507173a	2582	#define DAC_CR_TSEL1 ((uint32_t)0x00000038) /!< TSEL1[2:0] (DAC channel1 Trigger selection) /
emilmont	77:869cf507173a	2583	#define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /!< Bit 0 /
emilmont	77:869cf507173a	2584	#define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /!< Bit 1 /
emilmont	77:869cf507173a	2585	#define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /!< Bit 2 /
emilmont	77:869cf507173a	2586
emilmont	77:869cf507173a	2587	#define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable)(only for STM32F072 devices) /
emilmont	77:869cf507173a	2588	#define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /!< Bit 0 /
emilmont	77:869cf507173a	2589	#define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /!< Bit 1 /
emilmont	77:869cf507173a	2590
emilmont	77:869cf507173a	2591	#define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) (only for STM32F072 devices) /
emilmont	77:869cf507173a	2592	#define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /!< Bit 0 /
emilmont	77:869cf507173a	2593	#define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /!< Bit 1 /
emilmont	77:869cf507173a	2594	#define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /!< Bit 2 /
emilmont	77:869cf507173a	2595	#define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /!< Bit 3 /
emilmont	77:869cf507173a	2596
emilmont	77:869cf507173a	2597	#define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /!< DAC channel1 DMA enable /
emilmont	77:869cf507173a	2598	#define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /!<DAC channel1 DMA Underrun Interrupt enable /
emilmont	77:869cf507173a	2599	#define DAC_CR_EN2 ((uint32_t)0x00010000) /!< DAC channel2 enable /
emilmont	77:869cf507173a	2600	#define DAC_CR_BOFF2 ((uint32_t)0x00020000) /!< DAC channel2 output buffer disable /
emilmont	77:869cf507173a	2601	#define DAC_CR_TEN2 ((uint32_t)0x00040000) /!< DAC channel2 Trigger enable /
emilmont	77:869cf507173a	2602
emilmont	77:869cf507173a	2603	#define DAC_CR_TSEL2 ((uint32_t)0x00380000) /!< TSEL2[2:0] (DAC channel2 Trigger selection) /
emilmont	77:869cf507173a	2604	#define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /!< Bit 0 /
emilmont	77:869cf507173a	2605	#define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /!< Bit 1 /
emilmont	77:869cf507173a	2606	#define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /!< Bit 2 /
emilmont	77:869cf507173a	2607
emilmont	77:869cf507173a	2608	#define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
emilmont	77:869cf507173a	2609	#define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /!< Bit 0 /
emilmont	77:869cf507173a	2610	#define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /!< Bit 1 /
emilmont	77:869cf507173a	2611
emilmont	77:869cf507173a	2612	#define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
emilmont	77:869cf507173a	2613	#define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /!< Bit 0 /
emilmont	77:869cf507173a	2614	#define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /!< Bit 1 /
emilmont	77:869cf507173a	2615	#define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /!< Bit 2 /
emilmont	77:869cf507173a	2616	#define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /!< Bit 3 /
emilmont	77:869cf507173a	2617
emilmont	77:869cf507173a	2618	#define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /!< DAC channel2 DMA enabled /
emilmont	77:869cf507173a	2619	#define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /!<DAC channel2 DMA Underrun Interrupt enable /
emilmont	77:869cf507173a	2620
emilmont	77:869cf507173a	2621	/*************** Bit definition for DAC_SWTRIGR register ****************/
emilmont	77:869cf507173a	2622	#define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001) /!<DAC channel1 software trigger /
emilmont	77:869cf507173a	2623	#define DAC_SWTRIGR_SWTRIG2 ((uint32_t)0x00000002) /!<DAC channel2 software trigger /
emilmont	77:869cf507173a	2624
emilmont	77:869cf507173a	2625	/*************** Bit definition for DAC_DHR12R1 register ****************/
emilmont	77:869cf507173a	2626	#define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFF) /!<DAC channel1 12-bit Right aligned data /
emilmont	77:869cf507173a	2627
emilmont	77:869cf507173a	2628	/*************** Bit definition for DAC_DHR12L1 register ****************/
emilmont	77:869cf507173a	2629	#define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0) /!<DAC channel1 12-bit Left aligned data /
emilmont	77:869cf507173a	2630
emilmont	77:869cf507173a	2631	/**************** Bit definition for DAC_DHR8R1 register ****************/
emilmont	77:869cf507173a	2632	#define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FF) /!<DAC channel1 8-bit Right aligned data /
emilmont	77:869cf507173a	2633
emilmont	77:869cf507173a	2634	/***************** Bit definition for DAC_DOR1 register *****************/
emilmont	77:869cf507173a	2635	#define DAC_DOR1_DACC1DOR ((uint32_t)0x00000FFF) /!<DAC channel1 data output /
emilmont	77:869cf507173a	2636
emilmont	77:869cf507173a	2637	/****************** Bit definition for DAC_SR register ******************/
emilmont	77:869cf507173a	2638	#define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /!< DAC channel1 DMA underrun flag /
emilmont	77:869cf507173a	2639	#define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /!< DAC channel2 DMA underrun flag (only for STM32F072 and STM32F042 devices) /
emilmont	77:869cf507173a	2640
emilmont	77:869cf507173a	2641	/******************************************************************************/
emilmont	77:869cf507173a	2642	/* */
emilmont	77:869cf507173a	2643	/* Debug MCU (DBGMCU) */
emilmont	77:869cf507173a	2644	/* */
emilmont	77:869cf507173a	2645	/******************************************************************************/
emilmont	77:869cf507173a	2646
emilmont	77:869cf507173a	2647	/************** Bit definition for DBGMCU_IDCODE register ***************/
emilmont	77:869cf507173a	2648	#define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /!< Device Identifier /
emilmont	77:869cf507173a	2649
emilmont	77:869cf507173a	2650	#define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /!< REV_ID[15:0] bits (Revision Identifier) /
emilmont	77:869cf507173a	2651	#define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /!< Bit 0 /
emilmont	77:869cf507173a	2652	#define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /!< Bit 1 /
emilmont	77:869cf507173a	2653	#define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /!< Bit 2 /
emilmont	77:869cf507173a	2654	#define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /!< Bit 3 /
emilmont	77:869cf507173a	2655	#define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /!< Bit 4 /
emilmont	77:869cf507173a	2656	#define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /!< Bit 5 /
emilmont	77:869cf507173a	2657	#define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /!< Bit 6 /
emilmont	77:869cf507173a	2658	#define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /!< Bit 7 /
emilmont	77:869cf507173a	2659	#define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /!< Bit 8 /
emilmont	77:869cf507173a	2660	#define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /!< Bit 9 /
emilmont	77:869cf507173a	2661	#define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /!< Bit 10 /
emilmont	77:869cf507173a	2662	#define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /!< Bit 11 /
emilmont	77:869cf507173a	2663	#define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /!< Bit 12 /
emilmont	77:869cf507173a	2664	#define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /!< Bit 13 /
emilmont	77:869cf507173a	2665	#define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /!< Bit 14 /
emilmont	77:869cf507173a	2666	#define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /!< Bit 15 /
emilmont	77:869cf507173a	2667
emilmont	77:869cf507173a	2668	/**************** Bit definition for DBGMCU_CR register *****************/
emilmont	77:869cf507173a	2669	#define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /!< Debug Stop Mode /
emilmont	77:869cf507173a	2670	#define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /!< Debug Standby mode /
emilmont	77:869cf507173a	2671
emilmont	77:869cf507173a	2672	/**************** Bit definition for DBGMCU_APB1_FZ register ************/
emilmont	77:869cf507173a	2673	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /!< TIM2 counter stopped when core is halted /
emilmont	77:869cf507173a	2674	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /!< TIM3 counter stopped when core is halted /
emilmont	77:869cf507173a	2675	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /!< TIM6 counter stopped when core is halted (not available on STM32F042 devices)/
emilmont	77:869cf507173a	2676	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /!< TIM7 counter stopped when core is halted (only for STM32F072 devices) /
emilmont	77:869cf507173a	2677	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /!< TIM14 counter stopped when core is halted /
emilmont	77:869cf507173a	2678	#define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /!< RTC Calendar frozen when core is halted /
emilmont	77:869cf507173a	2679	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /!< Debug Window Watchdog stopped when Core is halted /
emilmont	77:869cf507173a	2680	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /!< Debug Independent Watchdog stopped when Core is halted /
emilmont	77:869cf507173a	2681	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /!< I2C1 SMBUS timeout mode stopped when Core is halted /
emilmont	77:869cf507173a	2682	#define DBGMCU_APB1_FZ_DBG_CAN_STOP ((uint32_t)0x02000000) /!< CAN debug stopped when Core is halted (only for STM32F072 devices) /
emilmont	77:869cf507173a	2683
emilmont	77:869cf507173a	2684	/**************** Bit definition for DBGMCU_APB2_FZ register ************/
emilmont	77:869cf507173a	2685	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /!< TIM1 counter stopped when core is halted /
emilmont	77:869cf507173a	2686	#define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /!< TIM15 counter stopped when core is halted (not available on STM32F042 devices) /
emilmont	77:869cf507173a	2687	#define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /!< TIM16 counter stopped when core is halted /
emilmont	77:869cf507173a	2688	#define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /!< TIM17 counter stopped when core is halted /
emilmont	77:869cf507173a	2689
emilmont	77:869cf507173a	2690	/******************************************************************************/
emilmont	77:869cf507173a	2691	/* */
emilmont	77:869cf507173a	2692	/* DMA Controller (DMA) */
emilmont	77:869cf507173a	2693	/* */
emilmont	77:869cf507173a	2694	/******************************************************************************/
emilmont	77:869cf507173a	2695
emilmont	77:869cf507173a	2696	/***************** Bit definition for DMA_ISR register ******************/
emilmont	77:869cf507173a	2697	#define DMA_ISR_GIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt flag /
emilmont	77:869cf507173a	2698	#define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete flag /
emilmont	77:869cf507173a	2699	#define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer flag /
emilmont	77:869cf507173a	2700	#define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error flag /
emilmont	77:869cf507173a	2701	#define DMA_ISR_GIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt flag /
emilmont	77:869cf507173a	2702	#define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete flag /
emilmont	77:869cf507173a	2703	#define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer flag /
emilmont	77:869cf507173a	2704	#define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error flag /
emilmont	77:869cf507173a	2705	#define DMA_ISR_GIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt flag /
emilmont	77:869cf507173a	2706	#define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete flag /
emilmont	77:869cf507173a	2707	#define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer flag /
emilmont	77:869cf507173a	2708	#define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error flag /
emilmont	77:869cf507173a	2709	#define DMA_ISR_GIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt flag /
emilmont	77:869cf507173a	2710	#define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete flag /
emilmont	77:869cf507173a	2711	#define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer flag /
emilmont	77:869cf507173a	2712	#define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error flag /
emilmont	77:869cf507173a	2713	#define DMA_ISR_GIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt flag /
emilmont	77:869cf507173a	2714	#define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete flag /
emilmont	77:869cf507173a	2715	#define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer flag /
emilmont	77:869cf507173a	2716	#define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error flag /
emilmont	77:869cf507173a	2717	#define DMA_ISR_GIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt flag (only for STM32F072 devices) /
emilmont	77:869cf507173a	2718	#define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete flag (only for STM32F072 devices) /
emilmont	77:869cf507173a	2719	#define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer flag (only for STM32F072 devices) /
emilmont	77:869cf507173a	2720	#define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error flag (only for STM32F072 devices) /
emilmont	77:869cf507173a	2721	#define DMA_ISR_GIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt flag (only for STM32F072 devices) /
emilmont	77:869cf507173a	2722	#define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete flag (only for STM32F072 devices) /
emilmont	77:869cf507173a	2723	#define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer flag (only for STM32F072 devices) /
emilmont	77:869cf507173a	2724	#define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error flag (only for STM32F072 devices) /
emilmont	77:869cf507173a	2725
emilmont	77:869cf507173a	2726	/***************** Bit definition for DMA_IFCR register *****************/
emilmont	77:869cf507173a	2727	#define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /!< Channel 1 Global interrupt clear /
emilmont	77:869cf507173a	2728	#define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /!< Channel 1 Transfer Complete clear /
emilmont	77:869cf507173a	2729	#define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /!< Channel 1 Half Transfer clear /
emilmont	77:869cf507173a	2730	#define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /!< Channel 1 Transfer Error clear /
emilmont	77:869cf507173a	2731	#define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /!< Channel 2 Global interrupt clear /
emilmont	77:869cf507173a	2732	#define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /!< Channel 2 Transfer Complete clear /
emilmont	77:869cf507173a	2733	#define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /!< Channel 2 Half Transfer clear /
emilmont	77:869cf507173a	2734	#define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /!< Channel 2 Transfer Error clear /
emilmont	77:869cf507173a	2735	#define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /!< Channel 3 Global interrupt clear /
emilmont	77:869cf507173a	2736	#define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /!< Channel 3 Transfer Complete clear /
emilmont	77:869cf507173a	2737	#define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /!< Channel 3 Half Transfer clear /
emilmont	77:869cf507173a	2738	#define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /!< Channel 3 Transfer Error clear /
emilmont	77:869cf507173a	2739	#define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /!< Channel 4 Global interrupt clear /
emilmont	77:869cf507173a	2740	#define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /!< Channel 4 Transfer Complete clear /
emilmont	77:869cf507173a	2741	#define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /!< Channel 4 Half Transfer clear /
emilmont	77:869cf507173a	2742	#define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /!< Channel 4 Transfer Error clear /
emilmont	77:869cf507173a	2743	#define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /!< Channel 5 Global interrupt clear /
emilmont	77:869cf507173a	2744	#define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /!< Channel 5 Transfer Complete clear /
emilmont	77:869cf507173a	2745	#define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /!< Channel 5 Half Transfer clear /
emilmont	77:869cf507173a	2746	#define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /!< Channel 5 Transfer Error clear /
emilmont	77:869cf507173a	2747	#define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /!< Channel 6 Global interrupt clear (only for STM32F072 devices) /
emilmont	77:869cf507173a	2748	#define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /!< Channel 6 Transfer Complete clear (only for STM32F072 devices) /
emilmont	77:869cf507173a	2749	#define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /!< Channel 6 Half Transfer clear (only for STM32F072 devices) /
emilmont	77:869cf507173a	2750	#define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /!< Channel 6 Transfer Error clear (only for STM32F072 devices) /
emilmont	77:869cf507173a	2751	#define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /!< Channel 7 Global interrupt clear (only for STM32F072 devices) /
emilmont	77:869cf507173a	2752	#define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /!< Channel 7 Transfer Complete clear (only for STM32F072 devices) /
emilmont	77:869cf507173a	2753	#define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /!< Channel 7 Half Transfer clear (only for STM32F072 devices) /
emilmont	77:869cf507173a	2754	#define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /!< Channel 7 Transfer Error clear (only for STM32F072 devices) /
emilmont	77:869cf507173a	2755
emilmont	77:869cf507173a	2756	/***************** Bit definition for DMA_CCR register ******************/
emilmont	77:869cf507173a	2757	#define DMA_CCR_EN ((uint32_t)0x00000001) /!< Channel enable /
emilmont	77:869cf507173a	2758	#define DMA_CCR_TCIE ((uint32_t)0x00000002) /!< Transfer complete interrupt enable /
emilmont	77:869cf507173a	2759	#define DMA_CCR_HTIE ((uint32_t)0x00000004) /!< Half Transfer interrupt enable /
emilmont	77:869cf507173a	2760	#define DMA_CCR_TEIE ((uint32_t)0x00000008) /!< Transfer error interrupt enable /
emilmont	77:869cf507173a	2761	#define DMA_CCR_DIR ((uint32_t)0x00000010) /!< Data transfer direction /
emilmont	77:869cf507173a	2762	#define DMA_CCR_CIRC ((uint32_t)0x00000020) /!< Circular mode /
emilmont	77:869cf507173a	2763	#define DMA_CCR_PINC ((uint32_t)0x00000040) /!< Peripheral increment mode /
emilmont	77:869cf507173a	2764	#define DMA_CCR_MINC ((uint32_t)0x00000080) /!< Memory increment mode /
emilmont	77:869cf507173a	2765
emilmont	77:869cf507173a	2766	#define DMA_CCR_PSIZE ((uint32_t)0x00000300) /!< PSIZE[1:0] bits (Peripheral size) /
emilmont	77:869cf507173a	2767	#define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /!< Bit 0 /
emilmont	77:869cf507173a	2768	#define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /!< Bit 1 /
emilmont	77:869cf507173a	2769
emilmont	77:869cf507173a	2770	#define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /!< MSIZE[1:0] bits (Memory size) /
emilmont	77:869cf507173a	2771	#define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /!< Bit 0 /
emilmont	77:869cf507173a	2772	#define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /!< Bit 1 /
emilmont	77:869cf507173a	2773
emilmont	77:869cf507173a	2774	#define DMA_CCR_PL ((uint32_t)0x00003000) /!< PL[1:0] bits(Channel Priority level)/
emilmont	77:869cf507173a	2775	#define DMA_CCR_PL_0 ((uint32_t)0x00001000) /!< Bit 0 /
emilmont	77:869cf507173a	2776	#define DMA_CCR_PL_1 ((uint32_t)0x00002000) /!< Bit 1 /
emilmont	77:869cf507173a	2777
emilmont	77:869cf507173a	2778	#define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /!< Memory to memory mode /
emilmont	77:869cf507173a	2779
emilmont	77:869cf507173a	2780	/**************** Bit definition for DMA_CNDTR register *****************/
emilmont	77:869cf507173a	2781	#define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /!< Number of data to Transfer /
emilmont	77:869cf507173a	2782
emilmont	77:869cf507173a	2783	/**************** Bit definition for DMA_CPAR register ******************/
emilmont	77:869cf507173a	2784	#define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /!< Peripheral Address /
emilmont	77:869cf507173a	2785
emilmont	77:869cf507173a	2786	/**************** Bit definition for DMA_CMAR register ******************/
emilmont	77:869cf507173a	2787	#define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /!< Memory Address /
emilmont	77:869cf507173a	2788
emilmont	77:869cf507173a	2789	/******************************************************************************/
emilmont	77:869cf507173a	2790	/* */
emilmont	77:869cf507173a	2791	/* External Interrupt/Event Controller (EXTI) */
emilmont	77:869cf507173a	2792	/* */
emilmont	77:869cf507173a	2793	/******************************************************************************/
emilmont	77:869cf507173a	2794	/***************** Bit definition for EXTI_IMR register *****************/
emilmont	77:869cf507173a	2795	#define EXTI_IMR_MR0 ((uint32_t)0x00000001) /!< Interrupt Mask on line 0 /
emilmont	77:869cf507173a	2796	#define EXTI_IMR_MR1 ((uint32_t)0x00000002) /!< Interrupt Mask on line 1 /
emilmont	77:869cf507173a	2797	#define EXTI_IMR_MR2 ((uint32_t)0x00000004) /!< Interrupt Mask on line 2 /
emilmont	77:869cf507173a	2798	#define EXTI_IMR_MR3 ((uint32_t)0x00000008) /!< Interrupt Mask on line 3 /
emilmont	77:869cf507173a	2799	#define EXTI_IMR_MR4 ((uint32_t)0x00000010) /!< Interrupt Mask on line 4 /
emilmont	77:869cf507173a	2800	#define EXTI_IMR_MR5 ((uint32_t)0x00000020) /!< Interrupt Mask on line 5 /
emilmont	77:869cf507173a	2801	#define EXTI_IMR_MR6 ((uint32_t)0x00000040) /!< Interrupt Mask on line 6 /
emilmont	77:869cf507173a	2802	#define EXTI_IMR_MR7 ((uint32_t)0x00000080) /!< Interrupt Mask on line 7 /
emilmont	77:869cf507173a	2803	#define EXTI_IMR_MR8 ((uint32_t)0x00000100) /!< Interrupt Mask on line 8 /
emilmont	77:869cf507173a	2804	#define EXTI_IMR_MR9 ((uint32_t)0x00000200) /!< Interrupt Mask on line 9 /
emilmont	77:869cf507173a	2805	#define EXTI_IMR_MR10 ((uint32_t)0x00000400) /!< Interrupt Mask on line 10 /
emilmont	77:869cf507173a	2806	#define EXTI_IMR_MR11 ((uint32_t)0x00000800) /!< Interrupt Mask on line 11 /
emilmont	77:869cf507173a	2807	#define EXTI_IMR_MR12 ((uint32_t)0x00001000) /!< Interrupt Mask on line 12 /
emilmont	77:869cf507173a	2808	#define EXTI_IMR_MR13 ((uint32_t)0x00002000) /!< Interrupt Mask on line 13 /
emilmont	77:869cf507173a	2809	#define EXTI_IMR_MR14 ((uint32_t)0x00004000) /!< Interrupt Mask on line 14 /
emilmont	77:869cf507173a	2810	#define EXTI_IMR_MR15 ((uint32_t)0x00008000) /!< Interrupt Mask on line 15 /
emilmont	77:869cf507173a	2811	#define EXTI_IMR_MR16 ((uint32_t)0x00010000) /!< Interrupt Mask on line 16 /
emilmont	77:869cf507173a	2812	#define EXTI_IMR_MR17 ((uint32_t)0x00020000) /!< Interrupt Mask on line 17 /
emilmont	77:869cf507173a	2813	#define EXTI_IMR_MR18 ((uint32_t)0x00040000) /!< Interrupt Mask on line 18 /
emilmont	77:869cf507173a	2814	#define EXTI_IMR_MR19 ((uint32_t)0x00080000) /!< Interrupt Mask on line 19 /
emilmont	77:869cf507173a	2815	#define EXTI_IMR_MR20 ((uint32_t)0x00100000) /!< Interrupt Mask on line 20 /
emilmont	77:869cf507173a	2816	#define EXTI_IMR_MR21 ((uint32_t)0x00200000) /!< Interrupt Mask on line 21 /
emilmont	77:869cf507173a	2817	#define EXTI_IMR_MR22 ((uint32_t)0x00400000) /!< Interrupt Mask on line 22 /
emilmont	77:869cf507173a	2818	#define EXTI_IMR_MR23 ((uint32_t)0x00800000) /!< Interrupt Mask on line 23 /
emilmont	77:869cf507173a	2819	#define EXTI_IMR_MR24 ((uint32_t)0x01000000) /!< Interrupt Mask on line 24 /
emilmont	77:869cf507173a	2820	#define EXTI_IMR_MR25 ((uint32_t)0x02000000) /!< Interrupt Mask on line 25 /
emilmont	77:869cf507173a	2821	#define EXTI_IMR_MR26 ((uint32_t)0x04000000) /!< Interrupt Mask on line 26 /
emilmont	77:869cf507173a	2822	#define EXTI_IMR_MR27 ((uint32_t)0x08000000) /!< Interrupt Mask on line 27 /
emilmont	77:869cf507173a	2823	#define EXTI_IMR_MR28 ((uint32_t)0x10000000) /!< Interrupt Mask on line 28 /
emilmont	77:869cf507173a	2824	#define EXTI_IMR_MR29 ((uint32_t)0x20000000) /!< Interrupt Mask on line 29 /
emilmont	77:869cf507173a	2825	#define EXTI_IMR_MR30 ((uint32_t)0x40000000) /!< Interrupt Mask on line 30 /
emilmont	77:869cf507173a	2826	#define EXTI_IMR_MR31 ((uint32_t)0x80000000) /!< Interrupt Mask on line 31 /
emilmont	77:869cf507173a	2827
emilmont	77:869cf507173a	2828	/**************** Bit definition for EXTI_EMR register ******************/
emilmont	77:869cf507173a	2829	#define EXTI_EMR_MR0 ((uint32_t)0x00000001) /!< Event Mask on line 0 /
emilmont	77:869cf507173a	2830	#define EXTI_EMR_MR1 ((uint32_t)0x00000002) /!< Event Mask on line 1 /
emilmont	77:869cf507173a	2831	#define EXTI_EMR_MR2 ((uint32_t)0x00000004) /!< Event Mask on line 2 /
emilmont	77:869cf507173a	2832	#define EXTI_EMR_MR3 ((uint32_t)0x00000008) /!< Event Mask on line 3 /
emilmont	77:869cf507173a	2833	#define EXTI_EMR_MR4 ((uint32_t)0x00000010) /!< Event Mask on line 4 /
emilmont	77:869cf507173a	2834	#define EXTI_EMR_MR5 ((uint32_t)0x00000020) /!< Event Mask on line 5 /
emilmont	77:869cf507173a	2835	#define EXTI_EMR_MR6 ((uint32_t)0x00000040) /!< Event Mask on line 6 /
emilmont	77:869cf507173a	2836	#define EXTI_EMR_MR7 ((uint32_t)0x00000080) /!< Event Mask on line 7 /
emilmont	77:869cf507173a	2837	#define EXTI_EMR_MR8 ((uint32_t)0x00000100) /!< Event Mask on line 8 /
emilmont	77:869cf507173a	2838	#define EXTI_EMR_MR9 ((uint32_t)0x00000200) /!< Event Mask on line 9 /
emilmont	77:869cf507173a	2839	#define EXTI_EMR_MR10 ((uint32_t)0x00000400) /!< Event Mask on line 10 /
emilmont	77:869cf507173a	2840	#define EXTI_EMR_MR11 ((uint32_t)0x00000800) /!< Event Mask on line 11 /
emilmont	77:869cf507173a	2841	#define EXTI_EMR_MR12 ((uint32_t)0x00001000) /!< Event Mask on line 12 /
emilmont	77:869cf507173a	2842	#define EXTI_EMR_MR13 ((uint32_t)0x00002000) /!< Event Mask on line 13 /
emilmont	77:869cf507173a	2843	#define EXTI_EMR_MR14 ((uint32_t)0x00004000) /!< Event Mask on line 14 /
emilmont	77:869cf507173a	2844	#define EXTI_EMR_MR15 ((uint32_t)0x00008000) /!< Event Mask on line 15 /
emilmont	77:869cf507173a	2845	#define EXTI_EMR_MR16 ((uint32_t)0x00010000) /!< Event Mask on line 16 /
emilmont	77:869cf507173a	2846	#define EXTI_EMR_MR17 ((uint32_t)0x00020000) /!< Event Mask on line 17 /
emilmont	77:869cf507173a	2847	#define EXTI_EMR_MR18 ((uint32_t)0x00040000) /!< Event Mask on line 18 /
emilmont	77:869cf507173a	2848	#define EXTI_EMR_MR19 ((uint32_t)0x00080000) /!< Event Mask on line 19 /
emilmont	77:869cf507173a	2849	#define EXTI_EMR_MR20 ((uint32_t)0x00100000) /!< Event Mask on line 20 /
emilmont	77:869cf507173a	2850	#define EXTI_EMR_MR21 ((uint32_t)0x00200000) /!< Event Mask on line 21 /
emilmont	77:869cf507173a	2851	#define EXTI_EMR_MR22 ((uint32_t)0x00400000) /!< Event Mask on line 22 /
emilmont	77:869cf507173a	2852	#define EXTI_EMR_MR23 ((uint32_t)0x00800000) /!< Event Mask on line 23 /
emilmont	77:869cf507173a	2853	#define EXTI_EMR_MR24 ((uint32_t)0x01000000) /!< Event Mask on line 24 /
emilmont	77:869cf507173a	2854	#define EXTI_EMR_MR25 ((uint32_t)0x02000000) /!< Event Mask on line 25 /
emilmont	77:869cf507173a	2855	#define EXTI_EMR_MR26 ((uint32_t)0x04000000) /!< Event Mask on line 26 /
emilmont	77:869cf507173a	2856	#define EXTI_EMR_MR27 ((uint32_t)0x08000000) /!< Event Mask on line 27 /
emilmont	77:869cf507173a	2857	#define EXTI_EMR_MR28 ((uint32_t)0x10000000) /!< Event Mask on line 28 /
emilmont	77:869cf507173a	2858	#define EXTI_EMR_MR29 ((uint32_t)0x20000000) /!< Event Mask on line 29 /
emilmont	77:869cf507173a	2859	#define EXTI_EMR_MR30 ((uint32_t)0x40000000) /!< Event Mask on line 30 /
emilmont	77:869cf507173a	2860	#define EXTI_EMR_MR31 ((uint32_t)0x80000000) /!< Event Mask on line 31 /
emilmont	77:869cf507173a	2861
emilmont	77:869cf507173a	2862	/***************** Bit definition for EXTI_RTSR register ****************/
emilmont	77:869cf507173a	2863	#define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /!< Rising trigger event configuration bit of line 0 /
emilmont	77:869cf507173a	2864	#define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /!< Rising trigger event configuration bit of line 1 /
emilmont	77:869cf507173a	2865	#define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /!< Rising trigger event configuration bit of line 2 /
emilmont	77:869cf507173a	2866	#define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /!< Rising trigger event configuration bit of line 3 /
emilmont	77:869cf507173a	2867	#define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /!< Rising trigger event configuration bit of line 4 /
emilmont	77:869cf507173a	2868	#define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /!< Rising trigger event configuration bit of line 5 /
emilmont	77:869cf507173a	2869	#define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /!< Rising trigger event configuration bit of line 6 /
emilmont	77:869cf507173a	2870	#define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /!< Rising trigger event configuration bit of line 7 /
emilmont	77:869cf507173a	2871	#define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /!< Rising trigger event configuration bit of line 8 /
emilmont	77:869cf507173a	2872	#define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /!< Rising trigger event configuration bit of line 9 /
emilmont	77:869cf507173a	2873	#define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /!< Rising trigger event configuration bit of line 10 /
emilmont	77:869cf507173a	2874	#define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /!< Rising trigger event configuration bit of line 11 /
emilmont	77:869cf507173a	2875	#define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /!< Rising trigger event configuration bit of line 12 /
emilmont	77:869cf507173a	2876	#define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /!< Rising trigger event configuration bit of line 13 /
emilmont	77:869cf507173a	2877	#define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /!< Rising trigger event configuration bit of line 14 /
emilmont	77:869cf507173a	2878	#define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /!< Rising trigger event configuration bit of line 15 /
emilmont	77:869cf507173a	2879	#define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /!< Rising trigger event configuration bit of line 16 /
emilmont	77:869cf507173a	2880	#define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /!< Rising trigger event configuration bit of line 17 /
emilmont	77:869cf507173a	2881	#define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /!< Rising trigger event configuration bit of line 19 /
emilmont	77:869cf507173a	2882	#define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /!< Rising trigger event configuration bit of line 20 /
emilmont	77:869cf507173a	2883	#define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /!< Rising trigger event configuration bit of line 21 /
emilmont	77:869cf507173a	2884	#define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /!< Rising trigger event configuration bit of line 22 /
emilmont	77:869cf507173a	2885
emilmont	77:869cf507173a	2886	/***************** Bit definition for EXTI_FTSR register *****************/
emilmont	77:869cf507173a	2887	#define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /!< Falling trigger event configuration bit of line 0 /
emilmont	77:869cf507173a	2888	#define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /!< Falling trigger event configuration bit of line 1 /
emilmont	77:869cf507173a	2889	#define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /!< Falling trigger event configuration bit of line 2 /
emilmont	77:869cf507173a	2890	#define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /!< Falling trigger event configuration bit of line 3 /
emilmont	77:869cf507173a	2891	#define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /!< Falling trigger event configuration bit of line 4 /
emilmont	77:869cf507173a	2892	#define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /!< Falling trigger event configuration bit of line 5 /
emilmont	77:869cf507173a	2893	#define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /!< Falling trigger event configuration bit of line 6 /
emilmont	77:869cf507173a	2894	#define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /!< Falling trigger event configuration bit of line 7 /
emilmont	77:869cf507173a	2895	#define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /!< Falling trigger event configuration bit of line 8 /
emilmont	77:869cf507173a	2896	#define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /!< Falling trigger event configuration bit of line 9 /
emilmont	77:869cf507173a	2897	#define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /!< Falling trigger event configuration bit of line 10 /
emilmont	77:869cf507173a	2898	#define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /!< Falling trigger event configuration bit of line 11 /
emilmont	77:869cf507173a	2899	#define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /!< Falling trigger event configuration bit of line 12 /
emilmont	77:869cf507173a	2900	#define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /!< Falling trigger event configuration bit of line 13 /
emilmont	77:869cf507173a	2901	#define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /!< Falling trigger event configuration bit of line 14 /
emilmont	77:869cf507173a	2902	#define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /!< Falling trigger event configuration bit of line 15 /
emilmont	77:869cf507173a	2903	#define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /!< Falling trigger event configuration bit of line 16 /
emilmont	77:869cf507173a	2904	#define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /!< Falling trigger event configuration bit of line 17 /
emilmont	77:869cf507173a	2905	#define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /!< Falling trigger event configuration bit of line 19 /
emilmont	77:869cf507173a	2906	#define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /!< Falling trigger event configuration bit of line 20 /
emilmont	77:869cf507173a	2907	#define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /!< Falling trigger event configuration bit of line 21 /
emilmont	77:869cf507173a	2908	#define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /!< Falling trigger event configuration bit of line 22 /
emilmont	77:869cf507173a	2909
emilmont	77:869cf507173a	2910	/***************** Bit definition for EXTI_SWIER register *****************/
emilmont	77:869cf507173a	2911	#define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /!< Software Interrupt on line 0 /
emilmont	77:869cf507173a	2912	#define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /!< Software Interrupt on line 1 /
emilmont	77:869cf507173a	2913	#define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /!< Software Interrupt on line 2 /
emilmont	77:869cf507173a	2914	#define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /!< Software Interrupt on line 3 /
emilmont	77:869cf507173a	2915	#define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /!< Software Interrupt on line 4 /
emilmont	77:869cf507173a	2916	#define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /!< Software Interrupt on line 5 /
emilmont	77:869cf507173a	2917	#define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /!< Software Interrupt on line 6 /
emilmont	77:869cf507173a	2918	#define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /!< Software Interrupt on line 7 /
emilmont	77:869cf507173a	2919	#define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /!< Software Interrupt on line 8 /
emilmont	77:869cf507173a	2920	#define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /!< Software Interrupt on line 9 /
emilmont	77:869cf507173a	2921	#define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /!< Software Interrupt on line 10 /
emilmont	77:869cf507173a	2922	#define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /!< Software Interrupt on line 11 /
emilmont	77:869cf507173a	2923	#define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /!< Software Interrupt on line 12 /
emilmont	77:869cf507173a	2924	#define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /!< Software Interrupt on line 13 /
emilmont	77:869cf507173a	2925	#define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /!< Software Interrupt on line 14 /
emilmont	77:869cf507173a	2926	#define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /!< Software Interrupt on line 15 /
emilmont	77:869cf507173a	2927	#define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /!< Software Interrupt on line 16 /
emilmont	77:869cf507173a	2928	#define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /!< Software Interrupt on line 17 /
emilmont	77:869cf507173a	2929	#define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /!< Software Interrupt on line 19 /
emilmont	77:869cf507173a	2930	#define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /!< Software Interrupt on line 20 /
emilmont	77:869cf507173a	2931	#define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /!< Software Interrupt on line 21 /
emilmont	77:869cf507173a	2932	#define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /!< Software Interrupt on line 22 /
emilmont	77:869cf507173a	2933
emilmont	77:869cf507173a	2934	/**************** Bit definition for EXTI_PR register *******************/
emilmont	77:869cf507173a	2935	#define EXTI_PR_PR0 ((uint32_t)0x00000001) /!< Pending bit 0 /
emilmont	77:869cf507173a	2936	#define EXTI_PR_PR1 ((uint32_t)0x00000002) /!< Pending bit 1 /
emilmont	77:869cf507173a	2937	#define EXTI_PR_PR2 ((uint32_t)0x00000004) /!< Pending bit 2 /
emilmont	77:869cf507173a	2938	#define EXTI_PR_PR3 ((uint32_t)0x00000008) /!< Pending bit 3 /
emilmont	77:869cf507173a	2939	#define EXTI_PR_PR4 ((uint32_t)0x00000010) /!< Pending bit 4 /
emilmont	77:869cf507173a	2940	#define EXTI_PR_PR5 ((uint32_t)0x00000020) /!< Pending bit 5 /
emilmont	77:869cf507173a	2941	#define EXTI_PR_PR6 ((uint32_t)0x00000040) /!< Pending bit 6 /
emilmont	77:869cf507173a	2942	#define EXTI_PR_PR7 ((uint32_t)0x00000080) /!< Pending bit 7 /
emilmont	77:869cf507173a	2943	#define EXTI_PR_PR8 ((uint32_t)0x00000100) /!< Pending bit 8 /
emilmont	77:869cf507173a	2944	#define EXTI_PR_PR9 ((uint32_t)0x00000200) /!< Pending bit 9 /
emilmont	77:869cf507173a	2945	#define EXTI_PR_PR10 ((uint32_t)0x00000400) /!< Pending bit 10 /
emilmont	77:869cf507173a	2946	#define EXTI_PR_PR11 ((uint32_t)0x00000800) /!< Pending bit 11 /
emilmont	77:869cf507173a	2947	#define EXTI_PR_PR12 ((uint32_t)0x00001000) /!< Pending bit 12 /
emilmont	77:869cf507173a	2948	#define EXTI_PR_PR13 ((uint32_t)0x00002000) /!< Pending bit 13 /
emilmont	77:869cf507173a	2949	#define EXTI_PR_PR14 ((uint32_t)0x00004000) /!< Pending bit 14 /
emilmont	77:869cf507173a	2950	#define EXTI_PR_PR15 ((uint32_t)0x00008000) /!< Pending bit 15 /
emilmont	77:869cf507173a	2951	#define EXTI_PR_PR16 ((uint32_t)0x00010000) /!< Pending bit 16 /
emilmont	77:869cf507173a	2952	#define EXTI_PR_PR17 ((uint32_t)0x00020000) /!< Pending bit 17 /
emilmont	77:869cf507173a	2953	#define EXTI_PR_PR19 ((uint32_t)0x00080000) /!< Pending bit 19 /
emilmont	77:869cf507173a	2954	#define EXTI_PR_PR20 ((uint32_t)0x00100000) /!< Pending bit 20 /
emilmont	77:869cf507173a	2955	#define EXTI_PR_PR21 ((uint32_t)0x00200000) /!< Pending bit 21 /
emilmont	77:869cf507173a	2956	#define EXTI_PR_PR22 ((uint32_t)0x00400000) /!< Pending bit 22 /
emilmont	77:869cf507173a	2957
emilmont	77:869cf507173a	2958	/******************************************************************************/
emilmont	77:869cf507173a	2959	/* */
emilmont	77:869cf507173a	2960	/* FLASH and Option Bytes Registers */
emilmont	77:869cf507173a	2961	/* */
emilmont	77:869cf507173a	2962	/******************************************************************************/
emilmont	77:869cf507173a	2963
emilmont	77:869cf507173a	2964	/***************** Bit definition for FLASH_ACR register ****************/
emilmont	77:869cf507173a	2965	#define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /!< LATENCY bit (Latency) /
emilmont	77:869cf507173a	2966
emilmont	77:869cf507173a	2967	#define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /!< Prefetch Buffer Enable /
emilmont	77:869cf507173a	2968	#define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /!< Prefetch Buffer Status /
emilmont	77:869cf507173a	2969
emilmont	77:869cf507173a	2970	/**************** Bit definition for FLASH_KEYR register ****************/
emilmont	77:869cf507173a	2971	#define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /!< FPEC Key /
emilmont	77:869cf507173a	2972
emilmont	77:869cf507173a	2973	/*************** Bit definition for FLASH_OPTKEYR register **************/
emilmont	77:869cf507173a	2974	#define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /!< Option Byte Key /
emilmont	77:869cf507173a	2975
emilmont	77:869cf507173a	2976	/**************** FLASH Keys ********************************************/
emilmont	77:869cf507173a	2977	#define FLASH_FKEY1 ((uint32_t)0x45670123) /!< Flash program erase key1 /
emilmont	77:869cf507173a	2978	#define FLASH_FKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
emilmont	77:869cf507173a	2979	to unlock the write access to the FPEC. */
emilmont	77:869cf507173a	2980
emilmont	77:869cf507173a	2981	#define FLASH_OPTKEY1 ((uint32_t)0x45670123) /!< Flash option key1 /
emilmont	77:869cf507173a	2982	#define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
emilmont	77:869cf507173a	2983	unlock the write access to the option byte block */
emilmont	77:869cf507173a	2984
emilmont	77:869cf507173a	2985	/**************** Bit definition for FLASH_SR register *****************/
emilmont	77:869cf507173a	2986	#define FLASH_SR_BSY ((uint32_t)0x00000001) /!< Busy /
emilmont	77:869cf507173a	2987	#define FLASH_SR_PGERR ((uint32_t)0x00000004) /!< Programming Error /
emilmont	77:869cf507173a	2988	#define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /!< Write Protection Error /
emilmont	77:869cf507173a	2989	#define FLASH_SR_EOP ((uint32_t)0x00000020) /!< End of operation /
emilmont	77:869cf507173a	2990	#define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /!< Legacy of Write Protection Error /
emilmont	77:869cf507173a	2991
emilmont	77:869cf507173a	2992	/***************** Bit definition for FLASH_CR register *****************/
emilmont	77:869cf507173a	2993	#define FLASH_CR_PG ((uint32_t)0x00000001) /!< Programming /
emilmont	77:869cf507173a	2994	#define FLASH_CR_PER ((uint32_t)0x00000002) /!< Page Erase /
emilmont	77:869cf507173a	2995	#define FLASH_CR_MER ((uint32_t)0x00000004) /!< Mass Erase /
emilmont	77:869cf507173a	2996	#define FLASH_CR_OPTPG ((uint32_t)0x00000010) /!< Option Byte Programming /
emilmont	77:869cf507173a	2997	#define FLASH_CR_OPTER ((uint32_t)0x00000020) /!< Option Byte Erase /
emilmont	77:869cf507173a	2998	#define FLASH_CR_STRT ((uint32_t)0x00000040) /!< Start /
emilmont	77:869cf507173a	2999	#define FLASH_CR_LOCK ((uint32_t)0x00000080) /!< Lock /
emilmont	77:869cf507173a	3000	#define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /!< Option Bytes Write Enable /
emilmont	77:869cf507173a	3001	#define FLASH_CR_ERRIE ((uint32_t)0x00000400) /!< Error Interrupt Enable /
emilmont	77:869cf507173a	3002	#define FLASH_CR_EOPIE ((uint32_t)0x00001000) /!< End of operation interrupt enable /
emilmont	77:869cf507173a	3003	#define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /!< Option Bytes Loader Launch /
emilmont	77:869cf507173a	3004
emilmont	77:869cf507173a	3005	/***************** Bit definition for FLASH_AR register *****************/
emilmont	77:869cf507173a	3006	#define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /!< Flash Address /
emilmont	77:869cf507173a	3007
emilmont	77:869cf507173a	3008	/**************** Bit definition for FLASH_OBR register *****************/
emilmont	77:869cf507173a	3009	#define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /!< Option Byte Error /
emilmont	77:869cf507173a	3010	#define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /!< Read protection Level bit 1 /
emilmont	77:869cf507173a	3011	#define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /!< Read protection Level bit 2 /
emilmont	77:869cf507173a	3012
emilmont	77:869cf507173a	3013	#define FLASH_OBR_USER ((uint32_t)0x00003700) /!< User Option Bytes /
emilmont	77:869cf507173a	3014	#define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /!< IWDG SW /
emilmont	77:869cf507173a	3015	#define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /!< nRST_STOP /
emilmont	77:869cf507173a	3016	#define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /!< nRST_STDBY /
emilmont	77:869cf507173a	3017	#define FLASH_OBR_nBOOT0 ((uint32_t)0x00000800) /!< nBOOT0 /
emilmont	77:869cf507173a	3018	#define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /!< nBOOT1 /
emilmont	77:869cf507173a	3019	#define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /!< VDDA power supply supervisor /
emilmont	77:869cf507173a	3020	#define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /!< RAM Parity Check /
emilmont	77:869cf507173a	3021	#define FLASH_OBR_nBOOT0_SW ((uint32_t)0x00008000) /!< nBOOT0 SW (available only in the STM32F042 devices)/
emilmont	77:869cf507173a	3022	#define FLASH_OBR_DATA0 ((uint32_t)0x00FF0000) /!< DATA0 /
emilmont	77:869cf507173a	3023	#define FLASH_OBR_DATA1 ((uint32_t)0xFF000000) /!< DATA0 /
emilmont	77:869cf507173a	3024
emilmont	77:869cf507173a	3025	/* Old BOOT1 bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	3026	#define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
emilmont	77:869cf507173a	3027
emilmont	77:869cf507173a	3028	/* Old OBR_VDDA bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	3029	#define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
emilmont	77:869cf507173a	3030
emilmont	77:869cf507173a	3031	/**************** Bit definition for FLASH_WRPR register ****************/
emilmont	77:869cf507173a	3032	#define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /!< Write Protect /
emilmont	77:869cf507173a	3033
emilmont	77:869cf507173a	3034	/----------------------------------------------------------------------------/
emilmont	77:869cf507173a	3035
emilmont	77:869cf507173a	3036	/**************** Bit definition for OB_RDP register ********************/
emilmont	77:869cf507173a	3037	#define OB_RDP_RDP ((uint32_t)0x000000FF) /!< Read protection option byte /
emilmont	77:869cf507173a	3038	#define OB_RDP_nRDP ((uint32_t)0x0000FF00) /!< Read protection complemented option byte /
emilmont	77:869cf507173a	3039
emilmont	77:869cf507173a	3040	/**************** Bit definition for OB_USER register *******************/
emilmont	77:869cf507173a	3041	#define OB_USER_USER ((uint32_t)0x00FF0000) /!< User option byte /
emilmont	77:869cf507173a	3042	#define OB_USER_nUSER ((uint32_t)0xFF000000) /!< User complemented option byte /
emilmont	77:869cf507173a	3043
emilmont	77:869cf507173a	3044	/**************** Bit definition for OB_WRP0 register *******************/
emilmont	77:869cf507173a	3045	#define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes /
emilmont	77:869cf507173a	3046	#define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes /
emilmont	77:869cf507173a	3047
emilmont	77:869cf507173a	3048	/**************** Bit definition for OB_WRP1 register *******************/
emilmont	77:869cf507173a	3049	#define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes /
emilmont	77:869cf507173a	3050	#define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes /
emilmont	77:869cf507173a	3051
emilmont	77:869cf507173a	3052	/**************** Bit definition for OB_WRP2 register *******************/
emilmont	77:869cf507173a	3053	#define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /!< Flash memory write protection option bytes (only for STM32F072 devices) /
emilmont	77:869cf507173a	3054	#define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /!< Flash memory write protection complemented option bytes (only for STM32F072 devices) /
emilmont	77:869cf507173a	3055
emilmont	77:869cf507173a	3056	/**************** Bit definition for OB_WRP3 register *******************/
emilmont	77:869cf507173a	3057	#define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /!< Flash memory write protection option bytes (only for STM32F072 devices) /
emilmont	77:869cf507173a	3058	#define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /!< Flash memory write protection complemented option bytes (only for STM32F072 devices) /
emilmont	77:869cf507173a	3059
emilmont	77:869cf507173a	3060	/******************************************************************************/
emilmont	77:869cf507173a	3061	/* */
emilmont	77:869cf507173a	3062	/* General Purpose IOs (GPIO) */
emilmont	77:869cf507173a	3063	/* */
emilmont	77:869cf507173a	3064	/******************************************************************************/
emilmont	77:869cf507173a	3065	/***************** Bit definition for GPIO_MODER register ***************/
emilmont	77:869cf507173a	3066	#define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
emilmont	77:869cf507173a	3067	#define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3068	#define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3069	#define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
emilmont	77:869cf507173a	3070	#define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3071	#define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3072	#define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
emilmont	77:869cf507173a	3073	#define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3074	#define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3075	#define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
emilmont	77:869cf507173a	3076	#define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3077	#define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3078	#define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
emilmont	77:869cf507173a	3079	#define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3080	#define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3081	#define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
emilmont	77:869cf507173a	3082	#define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3083	#define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3084	#define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
emilmont	77:869cf507173a	3085	#define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3086	#define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3087	#define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
emilmont	77:869cf507173a	3088	#define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3089	#define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3090	#define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
emilmont	77:869cf507173a	3091	#define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	3092	#define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	3093	#define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
emilmont	77:869cf507173a	3094	#define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	3095	#define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	3096	#define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
emilmont	77:869cf507173a	3097	#define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
emilmont	77:869cf507173a	3098	#define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	3099	#define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
emilmont	77:869cf507173a	3100	#define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
emilmont	77:869cf507173a	3101	#define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
emilmont	77:869cf507173a	3102	#define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
emilmont	77:869cf507173a	3103	#define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
emilmont	77:869cf507173a	3104	#define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
emilmont	77:869cf507173a	3105	#define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
emilmont	77:869cf507173a	3106	#define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
emilmont	77:869cf507173a	3107	#define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
emilmont	77:869cf507173a	3108	#define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
emilmont	77:869cf507173a	3109	#define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
emilmont	77:869cf507173a	3110	#define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
emilmont	77:869cf507173a	3111	#define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
emilmont	77:869cf507173a	3112	#define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
emilmont	77:869cf507173a	3113	#define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
emilmont	77:869cf507173a	3114
emilmont	77:869cf507173a	3115	/**************** Bit definition for GPIO_OTYPER register ***************/
emilmont	77:869cf507173a	3116	#define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3117	#define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3118	#define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3119	#define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3120	#define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3121	#define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3122	#define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3123	#define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3124	#define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3125	#define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3126	#define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3127	#define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3128	#define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3129	#define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3130	#define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3131	#define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3132
emilmont	77:869cf507173a	3133	/************** Bit definition for GPIO_OSPEEDR register ****************/
emilmont	77:869cf507173a	3134	#define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
emilmont	77:869cf507173a	3135	#define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3136	#define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3137	#define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
emilmont	77:869cf507173a	3138	#define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3139	#define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3140	#define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
emilmont	77:869cf507173a	3141	#define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3142	#define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3143	#define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
emilmont	77:869cf507173a	3144	#define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3145	#define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3146	#define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
emilmont	77:869cf507173a	3147	#define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3148	#define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3149	#define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
emilmont	77:869cf507173a	3150	#define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3151	#define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3152	#define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
emilmont	77:869cf507173a	3153	#define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3154	#define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3155	#define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
emilmont	77:869cf507173a	3156	#define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3157	#define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3158	#define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
emilmont	77:869cf507173a	3159	#define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	3160	#define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	3161	#define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
emilmont	77:869cf507173a	3162	#define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	3163	#define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	3164	#define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
emilmont	77:869cf507173a	3165	#define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
emilmont	77:869cf507173a	3166	#define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	3167	#define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
emilmont	77:869cf507173a	3168	#define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
emilmont	77:869cf507173a	3169	#define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
emilmont	77:869cf507173a	3170	#define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
emilmont	77:869cf507173a	3171	#define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
emilmont	77:869cf507173a	3172	#define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
emilmont	77:869cf507173a	3173	#define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
emilmont	77:869cf507173a	3174	#define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
emilmont	77:869cf507173a	3175	#define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
emilmont	77:869cf507173a	3176	#define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
emilmont	77:869cf507173a	3177	#define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
emilmont	77:869cf507173a	3178	#define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
emilmont	77:869cf507173a	3179	#define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
emilmont	77:869cf507173a	3180	#define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
emilmont	77:869cf507173a	3181	#define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
emilmont	77:869cf507173a	3182
emilmont	77:869cf507173a	3183	/* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
emilmont	77:869cf507173a	3184	#define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
emilmont	77:869cf507173a	3185	#define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
emilmont	77:869cf507173a	3186	#define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
emilmont	77:869cf507173a	3187	#define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
emilmont	77:869cf507173a	3188	#define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
emilmont	77:869cf507173a	3189	#define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
emilmont	77:869cf507173a	3190	#define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
emilmont	77:869cf507173a	3191	#define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
emilmont	77:869cf507173a	3192	#define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
emilmont	77:869cf507173a	3193	#define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
emilmont	77:869cf507173a	3194	#define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
emilmont	77:869cf507173a	3195	#define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
emilmont	77:869cf507173a	3196	#define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
emilmont	77:869cf507173a	3197	#define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
emilmont	77:869cf507173a	3198	#define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
emilmont	77:869cf507173a	3199	#define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
emilmont	77:869cf507173a	3200	#define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
emilmont	77:869cf507173a	3201	#define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
emilmont	77:869cf507173a	3202	#define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
emilmont	77:869cf507173a	3203	#define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
emilmont	77:869cf507173a	3204	#define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
emilmont	77:869cf507173a	3205	#define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
emilmont	77:869cf507173a	3206	#define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
emilmont	77:869cf507173a	3207	#define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
emilmont	77:869cf507173a	3208	#define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
emilmont	77:869cf507173a	3209	#define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
emilmont	77:869cf507173a	3210	#define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
emilmont	77:869cf507173a	3211	#define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
emilmont	77:869cf507173a	3212	#define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
emilmont	77:869cf507173a	3213	#define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
emilmont	77:869cf507173a	3214	#define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
emilmont	77:869cf507173a	3215	#define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
emilmont	77:869cf507173a	3216	#define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
emilmont	77:869cf507173a	3217	#define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
emilmont	77:869cf507173a	3218	#define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
emilmont	77:869cf507173a	3219	#define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
emilmont	77:869cf507173a	3220	#define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
emilmont	77:869cf507173a	3221	#define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
emilmont	77:869cf507173a	3222	#define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
emilmont	77:869cf507173a	3223	#define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
emilmont	77:869cf507173a	3224	#define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
emilmont	77:869cf507173a	3225	#define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
emilmont	77:869cf507173a	3226	#define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
emilmont	77:869cf507173a	3227	#define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
emilmont	77:869cf507173a	3228	#define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
emilmont	77:869cf507173a	3229	#define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
emilmont	77:869cf507173a	3230	#define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
emilmont	77:869cf507173a	3231	#define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
emilmont	77:869cf507173a	3232
emilmont	77:869cf507173a	3233	/***************** Bit definition for GPIO_PUPDR register ****************/
emilmont	77:869cf507173a	3234	#define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
emilmont	77:869cf507173a	3235	#define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3236	#define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3237	#define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
emilmont	77:869cf507173a	3238	#define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3239	#define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3240	#define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
emilmont	77:869cf507173a	3241	#define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3242	#define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3243	#define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
emilmont	77:869cf507173a	3244	#define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3245	#define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3246	#define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
emilmont	77:869cf507173a	3247	#define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3248	#define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3249	#define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
emilmont	77:869cf507173a	3250	#define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3251	#define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3252	#define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
emilmont	77:869cf507173a	3253	#define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3254	#define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3255	#define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
emilmont	77:869cf507173a	3256	#define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3257	#define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3258	#define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
emilmont	77:869cf507173a	3259	#define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	3260	#define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	3261	#define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
emilmont	77:869cf507173a	3262	#define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	3263	#define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	3264	#define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
emilmont	77:869cf507173a	3265	#define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
emilmont	77:869cf507173a	3266	#define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	3267	#define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
emilmont	77:869cf507173a	3268	#define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
emilmont	77:869cf507173a	3269	#define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
emilmont	77:869cf507173a	3270	#define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
emilmont	77:869cf507173a	3271	#define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
emilmont	77:869cf507173a	3272	#define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
emilmont	77:869cf507173a	3273	#define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
emilmont	77:869cf507173a	3274	#define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
emilmont	77:869cf507173a	3275	#define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
emilmont	77:869cf507173a	3276	#define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
emilmont	77:869cf507173a	3277	#define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
emilmont	77:869cf507173a	3278	#define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
emilmont	77:869cf507173a	3279	#define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
emilmont	77:869cf507173a	3280	#define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
emilmont	77:869cf507173a	3281	#define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
emilmont	77:869cf507173a	3282
emilmont	77:869cf507173a	3283	/***************** Bit definition for GPIO_IDR register *****************/
emilmont	77:869cf507173a	3284	#define GPIO_IDR_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3285	#define GPIO_IDR_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3286	#define GPIO_IDR_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3287	#define GPIO_IDR_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3288	#define GPIO_IDR_4 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3289	#define GPIO_IDR_5 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3290	#define GPIO_IDR_6 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3291	#define GPIO_IDR_7 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3292	#define GPIO_IDR_8 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3293	#define GPIO_IDR_9 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3294	#define GPIO_IDR_10 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3295	#define GPIO_IDR_11 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3296	#define GPIO_IDR_12 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3297	#define GPIO_IDR_13 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3298	#define GPIO_IDR_14 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3299	#define GPIO_IDR_15 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3300
emilmont	77:869cf507173a	3301	/**************** Bit definition for GPIO_ODR register ******************/
emilmont	77:869cf507173a	3302	#define GPIO_ODR_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3303	#define GPIO_ODR_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3304	#define GPIO_ODR_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3305	#define GPIO_ODR_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3306	#define GPIO_ODR_4 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3307	#define GPIO_ODR_5 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3308	#define GPIO_ODR_6 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3309	#define GPIO_ODR_7 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3310	#define GPIO_ODR_8 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3311	#define GPIO_ODR_9 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3312	#define GPIO_ODR_10 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3313	#define GPIO_ODR_11 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3314	#define GPIO_ODR_12 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3315	#define GPIO_ODR_13 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3316	#define GPIO_ODR_14 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3317	#define GPIO_ODR_15 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3318
emilmont	77:869cf507173a	3319	/**************** Bit definition for GPIO_BSRR register ******************/
emilmont	77:869cf507173a	3320	#define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3321	#define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3322	#define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3323	#define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3324	#define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3325	#define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3326	#define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3327	#define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3328	#define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3329	#define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3330	#define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3331	#define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3332	#define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3333	#define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3334	#define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3335	#define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3336	#define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	3337	#define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	3338	#define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	3339	#define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	3340	#define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
emilmont	77:869cf507173a	3341	#define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	3342	#define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
emilmont	77:869cf507173a	3343	#define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
emilmont	77:869cf507173a	3344	#define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
emilmont	77:869cf507173a	3345	#define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
emilmont	77:869cf507173a	3346	#define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
emilmont	77:869cf507173a	3347	#define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
emilmont	77:869cf507173a	3348	#define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
emilmont	77:869cf507173a	3349	#define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
emilmont	77:869cf507173a	3350	#define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
emilmont	77:869cf507173a	3351	#define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
emilmont	77:869cf507173a	3352
emilmont	77:869cf507173a	3353	/**************** Bit definition for GPIO_LCKR register ******************/
emilmont	77:869cf507173a	3354	#define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3355	#define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3356	#define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3357	#define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3358	#define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3359	#define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3360	#define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3361	#define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3362	#define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3363	#define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3364	#define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3365	#define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3366	#define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3367	#define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3368	#define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3369	#define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3370	#define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
emilmont	77:869cf507173a	3371
emilmont	77:869cf507173a	3372	/**************** Bit definition for GPIO_AFRL register ******************/
emilmont	77:869cf507173a	3373	#define GPIO_AFRL_AFR0 ((uint32_t)0x0000000F)
emilmont	77:869cf507173a	3374	#define GPIO_AFRL_AFR1 ((uint32_t)0x000000F0)
emilmont	77:869cf507173a	3375	#define GPIO_AFRL_AFR2 ((uint32_t)0x00000F00)
emilmont	77:869cf507173a	3376	#define GPIO_AFRL_AFR3 ((uint32_t)0x0000F000)
emilmont	77:869cf507173a	3377	#define GPIO_AFRL_AFR4 ((uint32_t)0x000F0000)
emilmont	77:869cf507173a	3378	#define GPIO_AFRL_AFR5 ((uint32_t)0x00F00000)
emilmont	77:869cf507173a	3379	#define GPIO_AFRL_AFR6 ((uint32_t)0x0F000000)
emilmont	77:869cf507173a	3380	#define GPIO_AFRL_AFR7 ((uint32_t)0xF0000000)
emilmont	77:869cf507173a	3381
emilmont	77:869cf507173a	3382	/**************** Bit definition for GPIO_AFRH register ******************/
emilmont	77:869cf507173a	3383	#define GPIO_AFRH_AFR8 ((uint32_t)0x0000000F)
emilmont	77:869cf507173a	3384	#define GPIO_AFRH_AFR9 ((uint32_t)0x000000F0)
emilmont	77:869cf507173a	3385	#define GPIO_AFRH_AFR10 ((uint32_t)0x00000F00)
emilmont	77:869cf507173a	3386	#define GPIO_AFRH_AFR11 ((uint32_t)0x0000F000)
emilmont	77:869cf507173a	3387	#define GPIO_AFRH_AFR12 ((uint32_t)0x000F0000)
emilmont	77:869cf507173a	3388	#define GPIO_AFRH_AFR13 ((uint32_t)0x00F00000)
emilmont	77:869cf507173a	3389	#define GPIO_AFRH_AFR14 ((uint32_t)0x0F000000)
emilmont	77:869cf507173a	3390	#define GPIO_AFRH_AFR15 ((uint32_t)0xF0000000)
emilmont	77:869cf507173a	3391
emilmont	77:869cf507173a	3392	/* Old Bit definition for GPIO_AFRL register maintained for legacy purpose ****/
emilmont	77:869cf507173a	3393	#define GPIO_AFRL_AFRL0 GPIO_AFRL_AFR0
emilmont	77:869cf507173a	3394	#define GPIO_AFRL_AFRL1 GPIO_AFRL_AFR1
emilmont	77:869cf507173a	3395	#define GPIO_AFRL_AFRL2 GPIO_AFRL_AFR2
emilmont	77:869cf507173a	3396	#define GPIO_AFRL_AFRL3 GPIO_AFRL_AFR3
emilmont	77:869cf507173a	3397	#define GPIO_AFRL_AFRL4 GPIO_AFRL_AFR4
emilmont	77:869cf507173a	3398	#define GPIO_AFRL_AFRL5 GPIO_AFRL_AFR5
emilmont	77:869cf507173a	3399	#define GPIO_AFRL_AFRL6 GPIO_AFRL_AFR6
emilmont	77:869cf507173a	3400	#define GPIO_AFRL_AFRL7 GPIO_AFRL_AFR7
emilmont	77:869cf507173a	3401
emilmont	77:869cf507173a	3402	/* Old Bit definition for GPIO_AFRH register maintained for legacy purpose ****/
emilmont	77:869cf507173a	3403	#define GPIO_AFRH_AFRH0 GPIO_AFRH_AFR8
emilmont	77:869cf507173a	3404	#define GPIO_AFRH_AFRH1 GPIO_AFRH_AFR9
emilmont	77:869cf507173a	3405	#define GPIO_AFRH_AFRH2 GPIO_AFRH_AFR10
emilmont	77:869cf507173a	3406	#define GPIO_AFRH_AFRH3 GPIO_AFRH_AFR11
emilmont	77:869cf507173a	3407	#define GPIO_AFRH_AFRH4 GPIO_AFRH_AFR12
emilmont	77:869cf507173a	3408	#define GPIO_AFRH_AFRH5 GPIO_AFRH_AFR13
emilmont	77:869cf507173a	3409	#define GPIO_AFRH_AFRH6 GPIO_AFRH_AFR14
emilmont	77:869cf507173a	3410	#define GPIO_AFRH_AFRH7 GPIO_AFRH_AFR15
emilmont	77:869cf507173a	3411
emilmont	77:869cf507173a	3412	/**************** Bit definition for GPIO_BRR register *******************/
emilmont	77:869cf507173a	3413	#define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	3414	#define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	3415	#define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	3416	#define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	3417	#define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	3418	#define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	3419	#define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	3420	#define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	3421	#define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3422	#define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3423	#define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3424	#define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	3425	#define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3426	#define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3427	#define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3428	#define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	3429
emilmont	77:869cf507173a	3430	/******************************************************************************/
emilmont	77:869cf507173a	3431	/* */
emilmont	77:869cf507173a	3432	/* Inter-integrated Circuit Interface (I2C) */
emilmont	77:869cf507173a	3433	/* */
emilmont	77:869cf507173a	3434	/******************************************************************************/
emilmont	77:869cf507173a	3435
emilmont	77:869cf507173a	3436	/***************** Bit definition for I2C_CR1 register *****************/
emilmont	77:869cf507173a	3437	#define I2C_CR1_PE ((uint32_t)0x00000001) /!< Peripheral enable /
emilmont	77:869cf507173a	3438	#define I2C_CR1_TXIE ((uint32_t)0x00000002) /!< TX interrupt enable /
emilmont	77:869cf507173a	3439	#define I2C_CR1_RXIE ((uint32_t)0x00000004) /!< RX interrupt enable /
emilmont	77:869cf507173a	3440	#define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /!< Address match interrupt enable /
emilmont	77:869cf507173a	3441	#define I2C_CR1_NACKIE ((uint32_t)0x00000010) /!< NACK received interrupt enable /
emilmont	77:869cf507173a	3442	#define I2C_CR1_STOPIE ((uint32_t)0x00000020) /!< STOP detection interrupt enable /
emilmont	77:869cf507173a	3443	#define I2C_CR1_TCIE ((uint32_t)0x00000040) /!< Transfer complete interrupt enable /
emilmont	77:869cf507173a	3444	#define I2C_CR1_ERRIE ((uint32_t)0x00000080) /!< Errors interrupt enable /
emilmont	77:869cf507173a	3445	#define I2C_CR1_DFN ((uint32_t)0x00000F00) /!< Digital noise filter /
emilmont	77:869cf507173a	3446	#define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /!< Analog noise filter OFF /
emilmont	77:869cf507173a	3447	#define I2C_CR1_SWRST ((uint32_t)0x00002000) /!< Software reset /
emilmont	77:869cf507173a	3448	#define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /!< DMA transmission requests enable /
emilmont	77:869cf507173a	3449	#define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /!< DMA reception requests enable /
emilmont	77:869cf507173a	3450	#define I2C_CR1_SBC ((uint32_t)0x00010000) /!< Slave byte control /
emilmont	77:869cf507173a	3451	#define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /!< Clock stretching disable /
emilmont	77:869cf507173a	3452	#define I2C_CR1_WUPEN ((uint32_t)0x00040000) /!< Wakeup from STOP enable /
emilmont	77:869cf507173a	3453	#define I2C_CR1_GCEN ((uint32_t)0x00080000) /!< General call enable /
emilmont	77:869cf507173a	3454	#define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /!< SMBus host address enable /
emilmont	77:869cf507173a	3455	#define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /!< SMBus device default address enable /
emilmont	77:869cf507173a	3456	#define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /!< SMBus alert enable /
emilmont	77:869cf507173a	3457	#define I2C_CR1_PECEN ((uint32_t)0x00800000) /!< PEC enable /
emilmont	77:869cf507173a	3458
emilmont	77:869cf507173a	3459	/**************** Bit definition for I2C_CR2 register ******************/
emilmont	77:869cf507173a	3460	#define I2C_CR2_SADD ((uint32_t)0x000003FF) /!< Slave address (master mode) /
emilmont	77:869cf507173a	3461	#define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /!< Transfer direction (master mode) /
emilmont	77:869cf507173a	3462	#define I2C_CR2_ADD10 ((uint32_t)0x00000800) /!< 10-bit addressing mode (master mode) /
emilmont	77:869cf507173a	3463	#define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /!< 10-bit address header only read direction (master mode) /
emilmont	77:869cf507173a	3464	#define I2C_CR2_START ((uint32_t)0x00002000) /!< START generation /
emilmont	77:869cf507173a	3465	#define I2C_CR2_STOP ((uint32_t)0x00004000) /!< STOP generation (master mode) /
emilmont	77:869cf507173a	3466	#define I2C_CR2_NACK ((uint32_t)0x00008000) /!< NACK generation (slave mode) /
emilmont	77:869cf507173a	3467	#define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /!< Number of bytes /
emilmont	77:869cf507173a	3468	#define I2C_CR2_RELOAD ((uint32_t)0x01000000) /!< NBYTES reload mode /
emilmont	77:869cf507173a	3469	#define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /!< Automatic end mode (master mode) /
emilmont	77:869cf507173a	3470	#define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /!< Packet error checking byte /
emilmont	77:869cf507173a	3471
emilmont	77:869cf507173a	3472	/***************** Bit definition for I2C_OAR1 register ****************/
emilmont	77:869cf507173a	3473	#define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /!< Interface own address 1 /
emilmont	77:869cf507173a	3474	#define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /!< Own address 1 10-bit mode /
emilmont	77:869cf507173a	3475	#define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /!< Own address 1 enable /
emilmont	77:869cf507173a	3476
emilmont	77:869cf507173a	3477	/***************** Bit definition for I2C_OAR2 register ****************/
emilmont	77:869cf507173a	3478	#define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /!< Interface own address 2 /
emilmont	77:869cf507173a	3479	#define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /!< Own address 2 masks /
emilmont	77:869cf507173a	3480	#define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /!< Own address 2 enable /
emilmont	77:869cf507173a	3481
emilmont	77:869cf507173a	3482	/***************** Bit definition for I2C_TIMINGR register *****************/
emilmont	77:869cf507173a	3483	#define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /!< SCL low period (master mode) /
emilmont	77:869cf507173a	3484	#define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /!< SCL high period (master mode) /
emilmont	77:869cf507173a	3485	#define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /!< Data hold time /
emilmont	77:869cf507173a	3486	#define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /!< Data setup time /
emilmont	77:869cf507173a	3487	#define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /!< Timings prescaler /
emilmont	77:869cf507173a	3488
emilmont	77:869cf507173a	3489	/***************** Bit definition for I2C_TIMEOUTR register *****************/
emilmont	77:869cf507173a	3490	#define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /!< Bus timeout A /
emilmont	77:869cf507173a	3491	#define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /!< Idle clock timeout detection /
emilmont	77:869cf507173a	3492	#define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /!< Clock timeout enable /
emilmont	77:869cf507173a	3493	#define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /!< Bus timeout B/
emilmont	77:869cf507173a	3494	#define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /!< Extended clock timeout enable /
emilmont	77:869cf507173a	3495
emilmont	77:869cf507173a	3496	/**************** Bit definition for I2C_ISR register *******************/
emilmont	77:869cf507173a	3497	#define I2C_ISR_TXE ((uint32_t)0x00000001) /!< Transmit data register empty /
emilmont	77:869cf507173a	3498	#define I2C_ISR_TXIS ((uint32_t)0x00000002) /!< Transmit interrupt status /
emilmont	77:869cf507173a	3499	#define I2C_ISR_RXNE ((uint32_t)0x00000004) /!< Receive data register not empty /
emilmont	77:869cf507173a	3500	#define I2C_ISR_ADDR ((uint32_t)0x00000008) /!< Address matched (slave mode)/
emilmont	77:869cf507173a	3501	#define I2C_ISR_NACKF ((uint32_t)0x00000010) /!< NACK received flag /
emilmont	77:869cf507173a	3502	#define I2C_ISR_STOPF ((uint32_t)0x00000020) /!< STOP detection flag /
emilmont	77:869cf507173a	3503	#define I2C_ISR_TC ((uint32_t)0x00000040) /!< Transfer complete (master mode) /
emilmont	77:869cf507173a	3504	#define I2C_ISR_TCR ((uint32_t)0x00000080) /!< Transfer complete reload /
emilmont	77:869cf507173a	3505	#define I2C_ISR_BERR ((uint32_t)0x00000100) /!< Bus error /
emilmont	77:869cf507173a	3506	#define I2C_ISR_ARLO ((uint32_t)0x00000200) /!< Arbitration lost /
emilmont	77:869cf507173a	3507	#define I2C_ISR_OVR ((uint32_t)0x00000400) /!< Overrun/Underrun /
emilmont	77:869cf507173a	3508	#define I2C_ISR_PECERR ((uint32_t)0x00000800) /!< PEC error in reception /
emilmont	77:869cf507173a	3509	#define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /!< Timeout or Tlow detection flag /
emilmont	77:869cf507173a	3510	#define I2C_ISR_ALERT ((uint32_t)0x00002000) /!< SMBus alert /
emilmont	77:869cf507173a	3511	#define I2C_ISR_BUSY ((uint32_t)0x00008000) /!< Bus busy /
emilmont	77:869cf507173a	3512	#define I2C_ISR_DIR ((uint32_t)0x00010000) /!< Transfer direction (slave mode) /
emilmont	77:869cf507173a	3513	#define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /!< Address match code (slave mode) /
emilmont	77:869cf507173a	3514
emilmont	77:869cf507173a	3515	/**************** Bit definition for I2C_ICR register *******************/
emilmont	77:869cf507173a	3516	#define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /!< Address matched clear flag /
emilmont	77:869cf507173a	3517	#define I2C_ICR_NACKCF ((uint32_t)0x00000010) /!< NACK clear flag /
emilmont	77:869cf507173a	3518	#define I2C_ICR_STOPCF ((uint32_t)0x00000020) /!< STOP detection clear flag /
emilmont	77:869cf507173a	3519	#define I2C_ICR_BERRCF ((uint32_t)0x00000100) /!< Bus error clear flag /
emilmont	77:869cf507173a	3520	#define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /!< Arbitration lost clear flag /
emilmont	77:869cf507173a	3521	#define I2C_ICR_OVRCF ((uint32_t)0x00000400) /!< Overrun/Underrun clear flag /
emilmont	77:869cf507173a	3522	#define I2C_ICR_PECCF ((uint32_t)0x00000800) /!< PAC error clear flag /
emilmont	77:869cf507173a	3523	#define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /!< Timeout clear flag /
emilmont	77:869cf507173a	3524	#define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /!< Alert clear flag /
emilmont	77:869cf507173a	3525
emilmont	77:869cf507173a	3526	/**************** Bit definition for I2C_PECR register *******************/
emilmont	77:869cf507173a	3527	#define I2C_PECR_PEC ((uint32_t)0x000000FF) /!< PEC register /
emilmont	77:869cf507173a	3528
emilmont	77:869cf507173a	3529	/**************** Bit definition for I2C_RXDR register *******************/
emilmont	77:869cf507173a	3530	#define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /!< 8-bit receive data /
emilmont	77:869cf507173a	3531
emilmont	77:869cf507173a	3532	/**************** Bit definition for I2C_TXDR register *******************/
emilmont	77:869cf507173a	3533	#define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /!< 8-bit transmit data /
emilmont	77:869cf507173a	3534
emilmont	77:869cf507173a	3535	/******************************************************************************/
emilmont	77:869cf507173a	3536	/* */
emilmont	77:869cf507173a	3537	/* Independent WATCHDOG (IWDG) */
emilmont	77:869cf507173a	3538	/* */
emilmont	77:869cf507173a	3539	/******************************************************************************/
emilmont	77:869cf507173a	3540	/***************** Bit definition for IWDG_KR register ******************/
emilmont	77:869cf507173a	3541	#define IWDG_KR_KEY ((uint16_t)0xFFFF) /!< Key value (write only, read 0000h) /
emilmont	77:869cf507173a	3542
emilmont	77:869cf507173a	3543	/***************** Bit definition for IWDG_PR register ******************/
emilmont	77:869cf507173a	3544	#define IWDG_PR_PR ((uint8_t)0x07) /!< PR[2:0] (Prescaler divider) /
emilmont	77:869cf507173a	3545	#define IWDG_PR_PR_0 ((uint8_t)0x01) /!< Bit 0 /
emilmont	77:869cf507173a	3546	#define IWDG_PR_PR_1 ((uint8_t)0x02) /!< Bit 1 /
emilmont	77:869cf507173a	3547	#define IWDG_PR_PR_2 ((uint8_t)0x04) /!< Bit 2 /
emilmont	77:869cf507173a	3548
emilmont	77:869cf507173a	3549	/***************** Bit definition for IWDG_RLR register *****************/
emilmont	77:869cf507173a	3550	#define IWDG_RLR_RL ((uint16_t)0x0FFF) /!< Watchdog counter reload value /
emilmont	77:869cf507173a	3551
emilmont	77:869cf507173a	3552	/***************** Bit definition for IWDG_SR register ******************/
emilmont	77:869cf507173a	3553	#define IWDG_SR_PVU ((uint8_t)0x01) /!< Watchdog prescaler value update /
emilmont	77:869cf507173a	3554	#define IWDG_SR_RVU ((uint8_t)0x02) /!< Watchdog counter reload value update /
emilmont	77:869cf507173a	3555	#define IWDG_SR_WVU ((uint8_t)0x04) /!< Watchdog counter window value update /
emilmont	77:869cf507173a	3556
emilmont	77:869cf507173a	3557	/***************** Bit definition for IWDG_KR register ******************/
emilmont	77:869cf507173a	3558	#define IWDG_WINR_WIN ((uint16_t)0x0FFF) /!< Watchdog counter window value /
emilmont	77:869cf507173a	3559
emilmont	77:869cf507173a	3560	/******************************************************************************/
emilmont	77:869cf507173a	3561	/* */
emilmont	77:869cf507173a	3562	/* Power Control (PWR) */
emilmont	77:869cf507173a	3563	/* */
emilmont	77:869cf507173a	3564	/******************************************************************************/
emilmont	77:869cf507173a	3565
emilmont	77:869cf507173a	3566	/****************** Bit definition for PWR_CR register ******************/
emilmont	77:869cf507173a	3567	#define PWR_CR_LPDS ((uint16_t)0x0001) /!< Low-power deepsleep/sleep /
emilmont	77:869cf507173a	3568	#define PWR_CR_PDDS ((uint16_t)0x0002) /!< Power Down Deepsleep /
emilmont	77:869cf507173a	3569	#define PWR_CR_CWUF ((uint16_t)0x0004) /!< Clear Wakeup Flag /
emilmont	77:869cf507173a	3570	#define PWR_CR_CSBF ((uint16_t)0x0008) /!< Clear Standby Flag /
emilmont	77:869cf507173a	3571	#define PWR_CR_PVDE ((uint16_t)0x0010) /!< Power Voltage Detector Enable /
emilmont	77:869cf507173a	3572
emilmont	77:869cf507173a	3573	#define PWR_CR_PLS ((uint16_t)0x00E0) /!< PLS[2:0] bits (PVD Level Selection) /
emilmont	77:869cf507173a	3574	#define PWR_CR_PLS_0 ((uint16_t)0x0020) /!< Bit 0 /
emilmont	77:869cf507173a	3575	#define PWR_CR_PLS_1 ((uint16_t)0x0040) /!< Bit 1 /
emilmont	77:869cf507173a	3576	#define PWR_CR_PLS_2 ((uint16_t)0x0080) /!< Bit 2 /
emilmont	77:869cf507173a	3577	/* PVD level configuration */
emilmont	77:869cf507173a	3578	#define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /!< PVD level 0 /
emilmont	77:869cf507173a	3579	#define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /!< PVD level 1 /
emilmont	77:869cf507173a	3580	#define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /!< PVD level 2 /
emilmont	77:869cf507173a	3581	#define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /!< PVD level 3 /
emilmont	77:869cf507173a	3582	#define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /!< PVD level 4 /
emilmont	77:869cf507173a	3583	#define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /!< PVD level 5 /
emilmont	77:869cf507173a	3584	#define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /!< PVD level 6 /
emilmont	77:869cf507173a	3585	#define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /!< PVD level 7 /
emilmont	77:869cf507173a	3586
emilmont	77:869cf507173a	3587	#define PWR_CR_DBP ((uint16_t)0x0100) /!< Disable Backup Domain write protection /
emilmont	77:869cf507173a	3588
emilmont	77:869cf507173a	3589	/* Old Bit definition maintained for legacy purpose ****/
emilmont	77:869cf507173a	3590	#define PWR_CR_LPSDSR PWR_CR_LPDS /!< Low-power deepsleep /
emilmont	77:869cf507173a	3591
emilmont	77:869cf507173a	3592	/***************** Bit definition for PWR_CSR register ******************/
emilmont	77:869cf507173a	3593	#define PWR_CSR_WUF ((uint16_t)0x0001) /!< Wakeup Flag /
emilmont	77:869cf507173a	3594	#define PWR_CSR_SBF ((uint16_t)0x0002) /!< Standby Flag /
emilmont	77:869cf507173a	3595	#define PWR_CSR_PVDO ((uint16_t)0x0004) /!< PVD Output /
emilmont	77:869cf507173a	3596	#define PWR_CSR_VREFINTRDY ((uint16_t)0x0008) /!< Internal voltage reference (VREFINT) ready /
emilmont	77:869cf507173a	3597
emilmont	77:869cf507173a	3598	#define PWR_CSR_EWUP1 ((uint16_t)0x0100) /!< Enable WKUP pin 1 /
emilmont	77:869cf507173a	3599	#define PWR_CSR_EWUP2 ((uint16_t)0x0200) /!< Enable WKUP pin 2 /
emilmont	77:869cf507173a	3600	#define PWR_CSR_EWUP3 ((uint16_t)0x0400) /!< Enable WKUP pin 3 /
emilmont	77:869cf507173a	3601	#define PWR_CSR_EWUP4 ((uint16_t)0x0800) /!< Enable WKUP pin 4 /
emilmont	77:869cf507173a	3602	#define PWR_CSR_EWUP5 ((uint16_t)0x1000) /!< Enable WKUP pin 5 /
emilmont	77:869cf507173a	3603	#define PWR_CSR_EWUP6 ((uint16_t)0x2000) /!< Enable WKUP pin 6 /
emilmont	77:869cf507173a	3604	#define PWR_CSR_EWUP7 ((uint16_t)0x4000) /!< Enable WKUP pin 7 /
emilmont	77:869cf507173a	3605	#define PWR_CSR_EWUP8 ((uint16_t)0x8000) /!< Enable WKUP pin 8 /
emilmont	77:869cf507173a	3606
emilmont	77:869cf507173a	3607	/* Old Bit definition maintained for legacy purpose ****/
emilmont	77:869cf507173a	3608	#define PWR_CSR_VREFINTRDYF PWR_CSR_VREFINTRDY /!< Internal voltage reference (VREFINT) ready flag /
emilmont	77:869cf507173a	3609	/******************************************************************************/
emilmont	77:869cf507173a	3610	/* */
emilmont	77:869cf507173a	3611	/* Reset and Clock Control */
emilmont	77:869cf507173a	3612	/* */
emilmont	77:869cf507173a	3613	/******************************************************************************/
emilmont	77:869cf507173a	3614
emilmont	77:869cf507173a	3615	/****************** Bit definition for RCC_CR register ******************/
emilmont	77:869cf507173a	3616	#define RCC_CR_HSION ((uint32_t)0x00000001) /!< Internal High Speed clock enable /
emilmont	77:869cf507173a	3617	#define RCC_CR_HSIRDY ((uint32_t)0x00000002) /!< Internal High Speed clock ready flag /
emilmont	77:869cf507173a	3618	#define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /!< Internal High Speed clock trimming /
emilmont	77:869cf507173a	3619	#define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /!< Internal High Speed clock Calibration /
emilmont	77:869cf507173a	3620	#define RCC_CR_HSEON ((uint32_t)0x00010000) /!< External High Speed clock enable /
emilmont	77:869cf507173a	3621	#define RCC_CR_HSERDY ((uint32_t)0x00020000) /!< External High Speed clock ready flag /
emilmont	77:869cf507173a	3622	#define RCC_CR_HSEBYP ((uint32_t)0x00040000) /!< External High Speed clock Bypass /
emilmont	77:869cf507173a	3623	#define RCC_CR_CSSON ((uint32_t)0x00080000) /!< Clock Security System enable /
emilmont	77:869cf507173a	3624	#define RCC_CR_PLLON ((uint32_t)0x01000000) /!< PLL enable /
emilmont	77:869cf507173a	3625	#define RCC_CR_PLLRDY ((uint32_t)0x02000000) /!< PLL clock ready flag /
emilmont	77:869cf507173a	3626
emilmont	77:869cf507173a	3627	/***************** Bit definition for RCC_CFGR register *****************/
emilmont	77:869cf507173a	3628	#define RCC_CFGR_SW ((uint32_t)0x00000003) /!< SW[1:0] bits (System clock Switch) /
emilmont	77:869cf507173a	3629	#define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
emilmont	77:869cf507173a	3630	#define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
emilmont	77:869cf507173a	3631	/* SW configuration */
emilmont	77:869cf507173a	3632	#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /!< HSI selected as system clock /
emilmont	77:869cf507173a	3633	#define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /!< HSE selected as system clock /
emilmont	77:869cf507173a	3634	#define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /!< PLL selected as system clock /
emilmont	77:869cf507173a	3635	#define RCC_CFGR_SW_HSI48 ((uint32_t)0x00000003) /!< HSI48 selected as system clock /
emilmont	77:869cf507173a	3636
emilmont	77:869cf507173a	3637	#define RCC_CFGR_SWS ((uint32_t)0x0000000C) /!< SWS[1:0] bits (System Clock Switch Status) /
emilmont	77:869cf507173a	3638	#define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /!< Bit 0 /
emilmont	77:869cf507173a	3639	#define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /!< Bit 1 /
emilmont	77:869cf507173a	3640	/* SWS configuration */
emilmont	77:869cf507173a	3641	#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /!< HSI oscillator used as system clock /
emilmont	77:869cf507173a	3642	#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /!< HSE oscillator used as system clock /
emilmont	77:869cf507173a	3643	#define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /!< PLL used as system clock /
emilmont	77:869cf507173a	3644	#define RCC_CFGR_SWS_HSI48 ((uint32_t)0x0000000C) /!< HSI48 used as system clock /
emilmont	77:869cf507173a	3645
emilmont	77:869cf507173a	3646	#define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /!< HPRE[3:0] bits (AHB prescaler) /
emilmont	77:869cf507173a	3647	#define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /!< Bit 0 /
emilmont	77:869cf507173a	3648	#define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /!< Bit 1 /
emilmont	77:869cf507173a	3649	#define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /!< Bit 2 /
emilmont	77:869cf507173a	3650	#define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /!< Bit 3 /
emilmont	77:869cf507173a	3651	/* HPRE configuration */
emilmont	77:869cf507173a	3652	#define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /!< SYSCLK not divided /
emilmont	77:869cf507173a	3653	#define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /!< SYSCLK divided by 2 /
emilmont	77:869cf507173a	3654	#define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /!< SYSCLK divided by 4 /
emilmont	77:869cf507173a	3655	#define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /!< SYSCLK divided by 8 /
emilmont	77:869cf507173a	3656	#define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /!< SYSCLK divided by 16 /
emilmont	77:869cf507173a	3657	#define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /!< SYSCLK divided by 64 /
emilmont	77:869cf507173a	3658	#define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /!< SYSCLK divided by 128 /
emilmont	77:869cf507173a	3659	#define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /!< SYSCLK divided by 256 /
emilmont	77:869cf507173a	3660	#define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /!< SYSCLK divided by 512 /
emilmont	77:869cf507173a	3661
emilmont	77:869cf507173a	3662	#define RCC_CFGR_PPRE ((uint32_t)0x00000700) /!< PRE[2:0] bits (APB prescaler) /
emilmont	77:869cf507173a	3663	#define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /!< Bit 0 /
emilmont	77:869cf507173a	3664	#define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /!< Bit 1 /
emilmont	77:869cf507173a	3665	#define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /!< Bit 2 /
emilmont	77:869cf507173a	3666	/* PPRE configuration */
emilmont	77:869cf507173a	3667	#define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /!< HCLK not divided /
emilmont	77:869cf507173a	3668	#define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /!< HCLK divided by 2 /
emilmont	77:869cf507173a	3669	#define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /!< HCLK divided by 4 /
emilmont	77:869cf507173a	3670	#define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /!< HCLK divided by 8 /
emilmont	77:869cf507173a	3671	#define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /!< HCLK divided by 16 /
emilmont	77:869cf507173a	3672
emilmont	77:869cf507173a	3673	#define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADC prescaler: Obsolete. Proper ADC clock selection is
emilmont	77:869cf507173a	3674	done inside the ADC_CFGR2 */
emilmont	77:869cf507173a	3675
emilmont	77:869cf507173a	3676	#define RCC_CFGR_PLLSRC ((uint32_t)0x00018000) /!< PLL entry clock source /
emilmont	77:869cf507173a	3677	#define RCC_CFGR_PLLSRC_0 ((uint32_t)0x00008000) /!< Bit 0 (available only in the STM32F072 devices) /
emilmont	77:869cf507173a	3678	#define RCC_CFGR_PLLSRC_1 ((uint32_t)0x00010000) /!< Bit 1 /
emilmont	77:869cf507173a	3679
emilmont	77:869cf507173a	3680	#define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source;
emilmont	77:869cf507173a	3681	Old PREDIV1 bit definition, maintained for legacy purpose */
emilmont	77:869cf507173a	3682	#define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /!< HSI clock divided by 2 selected as PLL entry clock source /
emilmont	77:869cf507173a	3683	#define RCC_CFGR_PLLSRC_HSI_PREDIV ((uint32_t)0x00008000) /*!< HSI PREDIV clock selected as PLL entry clock source
emilmont	77:869cf507173a	3684	(This bit and configuration is only available for STM32F072 devices)*/
emilmont	77:869cf507173a	3685	#define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /!< HSE PREDIV clock selected as PLL entry clock source /
emilmont	77:869cf507173a	3686	#define RCC_CFGR_PLLSRC_HSI48_PREDIV ((uint32_t)0x00018000) /!< HSI48 PREDIV clock selected as PLL entry clock source /
emilmont	77:869cf507173a	3687
emilmont	77:869cf507173a	3688	#define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /!< HSE divider for PLL entry /
emilmont	77:869cf507173a	3689	#define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /!< PREDIV1 clock not divided for PLL entry /
emilmont	77:869cf507173a	3690	#define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /!< PREDIV1 clock divided by 2 for PLL entry /
emilmont	77:869cf507173a	3691
emilmont	77:869cf507173a	3692	/!< Old bit definition maintained for legacy purposes /
emilmont	77:869cf507173a	3693	#define RCC_CFGR_PLLSRC_HSI_Div2 RCC_CFGR_PLLSRC_HSI_DIV2
emilmont	77:869cf507173a	3694
emilmont	77:869cf507173a	3695	/* PLLMUL configuration */
emilmont	77:869cf507173a	3696	#define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /!< PLLMUL[3:0] bits (PLL multiplication factor) /
emilmont	77:869cf507173a	3697	#define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /!< Bit 0 /
emilmont	77:869cf507173a	3698	#define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /!< Bit 1 /
emilmont	77:869cf507173a	3699	#define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /!< Bit 2 /
emilmont	77:869cf507173a	3700	#define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /!< Bit 3 /
emilmont	77:869cf507173a	3701
emilmont	77:869cf507173a	3702	#define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /!< PLL input clock2 */
emilmont	77:869cf507173a	3703	#define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /!< PLL input clock3 */
emilmont	77:869cf507173a	3704	#define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /!< PLL input clock4 */
emilmont	77:869cf507173a	3705	#define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /!< PLL input clock5 */
emilmont	77:869cf507173a	3706	#define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /!< PLL input clock6 */
emilmont	77:869cf507173a	3707	#define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /!< PLL input clock7 */
emilmont	77:869cf507173a	3708	#define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /!< PLL input clock8 */
emilmont	77:869cf507173a	3709	#define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /!< PLL input clock9 */
emilmont	77:869cf507173a	3710	#define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /!< PLL input clock10 /
emilmont	77:869cf507173a	3711	#define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /!< PLL input clock11 */
emilmont	77:869cf507173a	3712	#define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /!< PLL input clock12 */
emilmont	77:869cf507173a	3713	#define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /!< PLL input clock13 */
emilmont	77:869cf507173a	3714	#define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /!< PLL input clock14 */
emilmont	77:869cf507173a	3715	#define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /!< PLL input clock15 */
emilmont	77:869cf507173a	3716	#define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /!< PLL input clock16 */
emilmont	77:869cf507173a	3717
emilmont	77:869cf507173a	3718	/* Old PLLMUL configuration bit definition maintained for legacy purposes */
emilmont	77:869cf507173a	3719	#define RCC_CFGR_PLLMULL RCC_CFGR_PLLMUL /!< PLLMUL[3:0] bits (PLL multiplication factor) /
emilmont	77:869cf507173a	3720	#define RCC_CFGR_PLLMULL_0 RCC_CFGR_PLLMUL_0 /!< Bit 0 /
emilmont	77:869cf507173a	3721	#define RCC_CFGR_PLLMULL_1 RCC_CFGR_PLLMUL_1 /!< Bit 1 /
emilmont	77:869cf507173a	3722	#define RCC_CFGR_PLLMULL_2 RCC_CFGR_PLLMUL_2 /!< Bit 2 /
emilmont	77:869cf507173a	3723	#define RCC_CFGR_PLLMULL_3 RCC_CFGR_PLLMUL_3 /!< Bit 3 /
emilmont	77:869cf507173a	3724
emilmont	77:869cf507173a	3725	#define RCC_CFGR_PLLMULL2 RCC_CFGR_PLLMUL2 /!< PLL input clock2 */
emilmont	77:869cf507173a	3726	#define RCC_CFGR_PLLMULL3 RCC_CFGR_PLLMUL3 /!< PLL input clock3 */
emilmont	77:869cf507173a	3727	#define RCC_CFGR_PLLMULL4 RCC_CFGR_PLLMUL4 /!< PLL input clock4 */
emilmont	77:869cf507173a	3728	#define RCC_CFGR_PLLMULL5 RCC_CFGR_PLLMUL5 /!< PLL input clock5 */
emilmont	77:869cf507173a	3729	#define RCC_CFGR_PLLMULL6 RCC_CFGR_PLLMUL6 /!< PLL input clock6 */
emilmont	77:869cf507173a	3730	#define RCC_CFGR_PLLMULL7 RCC_CFGR_PLLMUL7 /!< PLL input clock7 */
emilmont	77:869cf507173a	3731	#define RCC_CFGR_PLLMULL8 RCC_CFGR_PLLMUL8 /!< PLL input clock8 */
emilmont	77:869cf507173a	3732	#define RCC_CFGR_PLLMULL9 RCC_CFGR_PLLMUL9 /!< PLL input clock9 */
emilmont	77:869cf507173a	3733	#define RCC_CFGR_PLLMULL10 RCC_CFGR_PLLMUL10 /!< PLL input clock10 /
emilmont	77:869cf507173a	3734	#define RCC_CFGR_PLLMULL11 RCC_CFGR_PLLMUL11 /!< PLL input clock11 */
emilmont	77:869cf507173a	3735	#define RCC_CFGR_PLLMULL12 RCC_CFGR_PLLMUL12 /!< PLL input clock12 */
emilmont	77:869cf507173a	3736	#define RCC_CFGR_PLLMULL13 RCC_CFGR_PLLMUL13 /!< PLL input clock13 */
emilmont	77:869cf507173a	3737	#define RCC_CFGR_PLLMULL14 RCC_CFGR_PLLMUL14 /!< PLL input clock14 */
emilmont	77:869cf507173a	3738	#define RCC_CFGR_PLLMULL15 RCC_CFGR_PLLMUL15 /!< PLL input clock15 */
emilmont	77:869cf507173a	3739	#define RCC_CFGR_PLLMULL16 RCC_CFGR_PLLMUL16 /!< PLL input clock16 */
emilmont	77:869cf507173a	3740
emilmont	77:869cf507173a	3741	#define RCC_CFGR_MCO ((uint32_t)0x0F000000) /!< MCO[2:0] bits (Microcontroller Clock Output) /
emilmont	77:869cf507173a	3742	#define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /!< Bit 0 /
emilmont	77:869cf507173a	3743	#define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /!< Bit 1 /
emilmont	77:869cf507173a	3744	#define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /!< Bit 2 /
emilmont	77:869cf507173a	3745	#define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /!< Bit 3 /
emilmont	77:869cf507173a	3746	/* MCO configuration */
emilmont	77:869cf507173a	3747	#define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
emilmont	77:869cf507173a	3748	#define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /!< HSI14 clock selected as MCO source /
emilmont	77:869cf507173a	3749	#define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /!< LSI clock selected as MCO source /
emilmont	77:869cf507173a	3750	#define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /!< LSE clock selected as MCO source /
emilmont	77:869cf507173a	3751	#define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /!< System clock selected as MCO source /
emilmont	77:869cf507173a	3752	#define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /!< HSI clock selected as MCO source /
emilmont	77:869cf507173a	3753	#define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /!< HSE clock selected as MCO source /
emilmont	77:869cf507173a	3754	#define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /!< PLL clock selected as MCO source /
emilmont	77:869cf507173a	3755	#define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000) /!< HSI48 clock selected as MCO source /
emilmont	77:869cf507173a	3756
emilmont	77:869cf507173a	3757	#define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /!< MCO prescaler (these bits are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3758	#define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /!< MCO is divided by 1 (this bit are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3759	#define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /!< MCO is divided by 2 (this bit are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3760	#define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /!< MCO is divided by 4 (this bit are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3761	#define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /!< MCO is divided by 8 (this bit are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3762	#define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /!< MCO is divided by 16 (this bit are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3763	#define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /!< MCO is divided by 32 (this bit are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3764	#define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /!< MCO is divided by 64 (this bit are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3765	#define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /!< MCO is divided by 128 (this bit are not available in the STM32F051 devices)/
emilmont	77:869cf507173a	3766
emilmont	77:869cf507173a	3767	#define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /!< PLL is not divided to MCO (this bit are not available in the STM32F051 devices) /
emilmont	77:869cf507173a	3768
emilmont	77:869cf507173a	3769	/***************** Bit definition for RCC_CIR register ******************/
emilmont	77:869cf507173a	3770	#define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /!< LSI Ready Interrupt flag /
emilmont	77:869cf507173a	3771	#define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /!< LSE Ready Interrupt flag /
emilmont	77:869cf507173a	3772	#define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /!< HSI Ready Interrupt flag /
emilmont	77:869cf507173a	3773	#define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /!< HSE Ready Interrupt flag /
emilmont	77:869cf507173a	3774	#define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /!< PLL Ready Interrupt flag /
emilmont	77:869cf507173a	3775	#define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /!< HSI14 Ready Interrupt flag /
emilmont	77:869cf507173a	3776	#define RCC_CIR_HSI48RDYF ((uint32_t)0x00000040) /!< HSI48 Ready Interrupt flag /
emilmont	77:869cf507173a	3777	#define RCC_CIR_CSSF ((uint32_t)0x00000080) /!< Clock Security System Interrupt flag /
emilmont	77:869cf507173a	3778	#define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /!< LSI Ready Interrupt Enable /
emilmont	77:869cf507173a	3779	#define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /!< LSE Ready Interrupt Enable /
emilmont	77:869cf507173a	3780	#define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /!< HSI Ready Interrupt Enable /
emilmont	77:869cf507173a	3781	#define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /!< HSE Ready Interrupt Enable /
emilmont	77:869cf507173a	3782	#define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /!< PLL Ready Interrupt Enable /
emilmont	77:869cf507173a	3783	#define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /!< HSI14 Ready Interrupt Enable /
emilmont	77:869cf507173a	3784	#define RCC_CIR_HSI48RDYIE ((uint32_t)0x00004000) /!< HSI48 Ready Interrupt Enable /
emilmont	77:869cf507173a	3785	#define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /!< LSI Ready Interrupt Clear /
emilmont	77:869cf507173a	3786	#define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /!< LSE Ready Interrupt Clear /
emilmont	77:869cf507173a	3787	#define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /!< HSI Ready Interrupt Clear /
emilmont	77:869cf507173a	3788	#define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /!< HSE Ready Interrupt Clear /
emilmont	77:869cf507173a	3789	#define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /!< PLL Ready Interrupt Clear /
emilmont	77:869cf507173a	3790	#define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /!< HSI14 Ready Interrupt Clear /
emilmont	77:869cf507173a	3791	#define RCC_CIR_HSI48RDYC ((uint32_t)0x00400000) /!< HSI48 Ready Interrupt Clear /
emilmont	77:869cf507173a	3792	#define RCC_CIR_CSSC ((uint32_t)0x00800000) /!< Clock Security System Interrupt Clear /
emilmont	77:869cf507173a	3793
emilmont	77:869cf507173a	3794	/*************** Bit definition for RCC_APB2RSTR register ***************/
emilmont	77:869cf507173a	3795	#define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /!< SYSCFG clock reset /
emilmont	77:869cf507173a	3796	#define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /!< ADC clock reset /
emilmont	77:869cf507173a	3797	#define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /!< TIM1 clock reset /
emilmont	77:869cf507173a	3798	#define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /!< SPI1 clock reset /
emilmont	77:869cf507173a	3799	#define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /!< USART1 clock reset /
emilmont	77:869cf507173a	3800	#define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /!< TIM15 clock reset /
emilmont	77:869cf507173a	3801	#define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /!< TIM16 clock reset /
emilmont	77:869cf507173a	3802	#define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /!< TIM17 clock reset /
emilmont	77:869cf507173a	3803	#define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /!< DBGMCU clock reset /
emilmont	77:869cf507173a	3804
emilmont	77:869cf507173a	3805	/* Old ADC1 clock reset bit definition maintained for legacy purpose */
emilmont	77:869cf507173a	3806	#define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
emilmont	77:869cf507173a	3807
emilmont	77:869cf507173a	3808	/*************** Bit definition for RCC_APB1RSTR register ***************/
emilmont	77:869cf507173a	3809	#define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /!< Timer 2 clock reset /
emilmont	77:869cf507173a	3810	#define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /!< Timer 3 clock reset /
emilmont	77:869cf507173a	3811	#define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /!< Timer 6 clock reset /
emilmont	77:869cf507173a	3812	#define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /!< Timer 7 clock reset /
emilmont	77:869cf507173a	3813	#define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /!< Timer 14 clock reset /
emilmont	77:869cf507173a	3814	#define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /!< Window Watchdog clock reset /
emilmont	77:869cf507173a	3815	#define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /!< SPI2 clock reset /
emilmont	77:869cf507173a	3816	#define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /!< USART 2 clock reset /
emilmont	77:869cf507173a	3817	#define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /!< USART 3 clock reset /
emilmont	77:869cf507173a	3818	#define RCC_APB1RSTR_USART4RST ((uint32_t)0x00080000) /!< USART 4 clock reset /
emilmont	77:869cf507173a	3819	#define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /!< I2C 1 clock reset /
emilmont	77:869cf507173a	3820	#define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /!< I2C 2 clock reset /
emilmont	77:869cf507173a	3821	#define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /!< USB clock reset /
emilmont	77:869cf507173a	3822	#define RCC_APB1RSTR_CANRST ((uint32_t)0x02000000) /!< CAN clock reset /
emilmont	77:869cf507173a	3823	#define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000) /!< CRS clock reset /
emilmont	77:869cf507173a	3824	#define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /!< PWR clock reset /
emilmont	77:869cf507173a	3825	#define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /!< DAC clock reset /
emilmont	77:869cf507173a	3826	#define RCC_APB1RSTR_CECRST ((uint32_t)0x40000000) /!< CEC clock reset /
emilmont	77:869cf507173a	3827
emilmont	77:869cf507173a	3828	/**************** Bit definition for RCC_AHBENR register ****************/
emilmont	77:869cf507173a	3829	#define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /!< DMA clock enable /
emilmont	77:869cf507173a	3830	#define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /!< SRAM interface clock enable /
emilmont	77:869cf507173a	3831	#define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /!< FLITF clock enable /
emilmont	77:869cf507173a	3832	#define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /!< CRC clock enable /
emilmont	77:869cf507173a	3833	#define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /!< GPIOA clock enable /
emilmont	77:869cf507173a	3834	#define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /!< GPIOB clock enable /
emilmont	77:869cf507173a	3835	#define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /!< GPIOC clock enable /
emilmont	77:869cf507173a	3836	#define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /!< GPIOD clock enable /
emilmont	77:869cf507173a	3837	#define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /!< GPIOE clock enable /
emilmont	77:869cf507173a	3838	#define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /!< GPIOF clock enable /
emilmont	77:869cf507173a	3839	#define RCC_AHBENR_TSCEN ((uint32_t)0x01000000) /!< TS controller clock enable /
emilmont	77:869cf507173a	3840
emilmont	77:869cf507173a	3841	/* Old Bit definition maintained for legacy purpose */
emilmont	77:869cf507173a	3842	#define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /!< DMA1 clock enable /
emilmont	77:869cf507173a	3843	#define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /!< TS clock enable /
emilmont	77:869cf507173a	3844
emilmont	77:869cf507173a	3845	/*************** Bit definition for RCC_APB2ENR register ****************/
emilmont	77:869cf507173a	3846	#define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /!< SYSCFG and comparator clock enable /
emilmont	77:869cf507173a	3847	#define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /!< ADC1 clock enable /
emilmont	77:869cf507173a	3848	#define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /!< TIM1 clock enable /
emilmont	77:869cf507173a	3849	#define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /!< SPI1 clock enable /
emilmont	77:869cf507173a	3850	#define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /!< USART1 clock enable /
emilmont	77:869cf507173a	3851	#define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /!< TIM15 clock enable /
emilmont	77:869cf507173a	3852	#define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /!< TIM16 clock enable /
emilmont	77:869cf507173a	3853	#define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /!< TIM17 clock enable /
emilmont	77:869cf507173a	3854	#define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /!< DBGMCU clock enable /
emilmont	77:869cf507173a	3855
emilmont	77:869cf507173a	3856	/* Old Bit definition maintained for legacy purpose */
emilmont	77:869cf507173a	3857	#define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /!< SYSCFG clock enable /
emilmont	77:869cf507173a	3858	#define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /!< ADC1 clock enable /
emilmont	77:869cf507173a	3859
emilmont	77:869cf507173a	3860	/*************** Bit definition for RCC_APB1ENR register ****************/
emilmont	77:869cf507173a	3861	#define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /!< Timer 2 clock enable /
emilmont	77:869cf507173a	3862	#define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /!< Timer 3 clock enable /
emilmont	77:869cf507173a	3863	#define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /!< Timer 6 clock enable /
emilmont	77:869cf507173a	3864	#define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /!< Timer 7 clock enable /
emilmont	77:869cf507173a	3865	#define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /!< Timer 14 clock enable /
emilmont	77:869cf507173a	3866	#define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /!< Window Watchdog clock enable /
emilmont	77:869cf507173a	3867	#define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /!< SPI2 clock enable /
emilmont	77:869cf507173a	3868	#define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /!< USART2 clock enable /
emilmont	77:869cf507173a	3869	#define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /!< USART3 clock enable /
emilmont	77:869cf507173a	3870	#define RCC_APB1ENR_USART4EN ((uint32_t)0x00080000) /!< USART4 clock enable /
emilmont	77:869cf507173a	3871	#define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /!< I2C1 clock enable /
emilmont	77:869cf507173a	3872	#define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /!< I2C2 clock enable /
emilmont	77:869cf507173a	3873	#define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /!< USB clock enable /
emilmont	77:869cf507173a	3874	#define RCC_APB1ENR_CANEN ((uint32_t)0x02000000) /!< CAN clock enable /
emilmont	77:869cf507173a	3875	#define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000) /!< CRS clock enable /
emilmont	77:869cf507173a	3876	#define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /!< PWR clock enable /
emilmont	77:869cf507173a	3877	#define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /!< DAC clock enable /
emilmont	77:869cf507173a	3878	#define RCC_APB1ENR_CECEN ((uint32_t)0x40000000) /!< CEC clock enable /
emilmont	77:869cf507173a	3879
emilmont	77:869cf507173a	3880	/***************** Bit definition for RCC_BDCR register *****************/
emilmont	77:869cf507173a	3881	#define RCC_BDCR_LSEON ((uint32_t)0x00000001) /!< External Low Speed oscillator enable /
emilmont	77:869cf507173a	3882	#define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /!< External Low Speed oscillator Ready /
emilmont	77:869cf507173a	3883	#define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /!< External Low Speed oscillator Bypass /
emilmont	77:869cf507173a	3884
emilmont	77:869cf507173a	3885	#define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /!< LSEDRV[1:0] bits (LSE Osc. drive capability) /
emilmont	77:869cf507173a	3886	#define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /!< Bit 0 /
emilmont	77:869cf507173a	3887	#define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /!< Bit 1 /
emilmont	77:869cf507173a	3888
emilmont	77:869cf507173a	3889	#define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /!< RTCSEL[1:0] bits (RTC clock source selection) /
emilmont	77:869cf507173a	3890	#define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /!< Bit 0 /
emilmont	77:869cf507173a	3891	#define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /!< Bit 1 /
emilmont	77:869cf507173a	3892
emilmont	77:869cf507173a	3893	/* RTC configuration */
emilmont	77:869cf507173a	3894	#define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /!< No clock /
emilmont	77:869cf507173a	3895	#define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /!< LSE oscillator clock used as RTC clock /
emilmont	77:869cf507173a	3896	#define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /!< LSI oscillator clock used as RTC clock /
emilmont	77:869cf507173a	3897	#define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /!< HSE oscillator clock divided by 32 used as RTC clock /
emilmont	77:869cf507173a	3898
emilmont	77:869cf507173a	3899	#define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /!< RTC clock enable /
emilmont	77:869cf507173a	3900	#define RCC_BDCR_BDRST ((uint32_t)0x00010000) /!< Backup domain software reset /
emilmont	77:869cf507173a	3901
emilmont	77:869cf507173a	3902	/***************** Bit definition for RCC_CSR register ******************/
emilmont	77:869cf507173a	3903	#define RCC_CSR_LSION ((uint32_t)0x00000001) /!< Internal Low Speed oscillator enable /
emilmont	77:869cf507173a	3904	#define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /!< Internal Low Speed oscillator Ready /
emilmont	77:869cf507173a	3905	#define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /!< V1.8 power domain reset flag /
emilmont	77:869cf507173a	3906	#define RCC_CSR_RMVF ((uint32_t)0x01000000) /!< Remove reset flag /
emilmont	77:869cf507173a	3907	#define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /!< OBL reset flag /
emilmont	77:869cf507173a	3908	#define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /!< PIN reset flag /
emilmont	77:869cf507173a	3909	#define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /!< POR/PDR reset flag /
emilmont	77:869cf507173a	3910	#define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /!< Software Reset flag /
emilmont	77:869cf507173a	3911	#define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /!< Independent Watchdog reset flag /
emilmont	77:869cf507173a	3912	#define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /!< Window watchdog reset flag /
emilmont	77:869cf507173a	3913	#define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /!< Low-Power reset flag /
emilmont	77:869cf507173a	3914
emilmont	77:869cf507173a	3915	/* Old Bit definition maintained for legacy purpose */
emilmont	77:869cf507173a	3916	#define RCC_CSR_OBL RCC_CSR_OBLRSTF /!< OBL reset flag /
emilmont	77:869cf507173a	3917	/***************** Bit definition for RCC_AHBRSTR register **************/
emilmont	77:869cf507173a	3918	#define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /!< GPIOA clock reset /
emilmont	77:869cf507173a	3919	#define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /!< GPIOB clock reset /
emilmont	77:869cf507173a	3920	#define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /!< GPIOC clock reset /
emilmont	77:869cf507173a	3921	#define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /!< GPIOD clock reset /
emilmont	77:869cf507173a	3922	#define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00020000) /!< GPIOE clock reset /
emilmont	77:869cf507173a	3923	#define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /!< GPIOF clock reset /
emilmont	77:869cf507173a	3924	#define RCC_AHBRSTR_TSCRST ((uint32_t)0x00100000) /!< TS clock reset /
emilmont	77:869cf507173a	3925
emilmont	77:869cf507173a	3926	/* Old Bit definition maintained for legacy purpose */
emilmont	77:869cf507173a	3927	#define RCC_AHBRSTR_TSRST RCC_AHBRSTR_TSCRST /!< TS clock reset /
emilmont	77:869cf507173a	3928
emilmont	77:869cf507173a	3929	/***************** Bit definition for RCC_CFGR2 register ****************/
emilmont	77:869cf507173a	3930	/* PREDIV1 configuration */
emilmont	77:869cf507173a	3931	#define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /!< PREDIV1[3:0] bits /
emilmont	77:869cf507173a	3932	#define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /!< Bit 0 /
emilmont	77:869cf507173a	3933	#define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /!< Bit 1 /
emilmont	77:869cf507173a	3934	#define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /!< Bit 2 /
emilmont	77:869cf507173a	3935	#define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /!< Bit 3 /
emilmont	77:869cf507173a	3936
emilmont	77:869cf507173a	3937	#define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /!< PREDIV1 input clock not divided /
emilmont	77:869cf507173a	3938	#define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /!< PREDIV1 input clock divided by 2 /
emilmont	77:869cf507173a	3939	#define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /!< PREDIV1 input clock divided by 3 /
emilmont	77:869cf507173a	3940	#define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /!< PREDIV1 input clock divided by 4 /
emilmont	77:869cf507173a	3941	#define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /!< PREDIV1 input clock divided by 5 /
emilmont	77:869cf507173a	3942	#define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /!< PREDIV1 input clock divided by 6 /
emilmont	77:869cf507173a	3943	#define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /!< PREDIV1 input clock divided by 7 /
emilmont	77:869cf507173a	3944	#define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /!< PREDIV1 input clock divided by 8 /
emilmont	77:869cf507173a	3945	#define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /!< PREDIV1 input clock divided by 9 /
emilmont	77:869cf507173a	3946	#define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /!< PREDIV1 input clock divided by 10 /
emilmont	77:869cf507173a	3947	#define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /!< PREDIV1 input clock divided by 11 /
emilmont	77:869cf507173a	3948	#define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /!< PREDIV1 input clock divided by 12 /
emilmont	77:869cf507173a	3949	#define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /!< PREDIV1 input clock divided by 13 /
emilmont	77:869cf507173a	3950	#define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /!< PREDIV1 input clock divided by 14 /
emilmont	77:869cf507173a	3951	#define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /!< PREDIV1 input clock divided by 15 /
emilmont	77:869cf507173a	3952	#define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /!< PREDIV1 input clock divided by 16 /
emilmont	77:869cf507173a	3953
emilmont	77:869cf507173a	3954	/***************** Bit definition for RCC_CFGR3 register ****************/
emilmont	77:869cf507173a	3955	#define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /!< USART1SW[1:0] bits /
emilmont	77:869cf507173a	3956	#define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /!< Bit 0 /
emilmont	77:869cf507173a	3957	#define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /!< Bit 1 /
emilmont	77:869cf507173a	3958	#define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /!< I2C1SW bits /
emilmont	77:869cf507173a	3959	#define RCC_CFGR3_CECSW ((uint32_t)0x00000040) /!< CECSW bits /
emilmont	77:869cf507173a	3960	#define RCC_CFGR3_USBSW ((uint32_t)0x00000080) /!< USBSW bits /
emilmont	77:869cf507173a	3961	#define RCC_CFGR3_ADCSW ((uint32_t)0x00000100) /!< ADCSW bits /
emilmont	77:869cf507173a	3962	#define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /!< USART2SW[1:0] bits /
emilmont	77:869cf507173a	3963	#define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /!< Bit 0 /
emilmont	77:869cf507173a	3964	#define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /!< Bit 1 /
emilmont	77:869cf507173a	3965
emilmont	77:869cf507173a	3966	/***************** Bit definition for RCC_CR2 register ******************/
emilmont	77:869cf507173a	3967	#define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /!< Internal High Speed 14MHz clock enable /
emilmont	77:869cf507173a	3968	#define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /!< Internal High Speed 14MHz clock ready flag /
emilmont	77:869cf507173a	3969	#define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /!< Internal High Speed 14MHz clock disable /
emilmont	77:869cf507173a	3970	#define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /!< Internal High Speed 14MHz clock trimming /
emilmont	77:869cf507173a	3971	#define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /!< Internal High Speed 14MHz clock Calibration /
emilmont	77:869cf507173a	3972	#define RCC_CR2_HSI48ON ((uint32_t)0x00010000) /!< Internal High Speed 48MHz clock enable /
emilmont	77:869cf507173a	3973	#define RCC_CR2_HSI48RDY ((uint32_t)0x00020000) /!< Internal High Speed 48MHz clock ready flag /
emilmont	77:869cf507173a	3974	#define RCC_CR2_HSI48CAL ((uint32_t)0xFF000000) /!< Internal High Speed 48MHz clock Calibration /
emilmont	77:869cf507173a	3975
emilmont	77:869cf507173a	3976	/******************************************************************************/
emilmont	77:869cf507173a	3977	/* */
emilmont	77:869cf507173a	3978	/* Real-Time Clock (RTC) */
emilmont	77:869cf507173a	3979	/* */
emilmont	77:869cf507173a	3980	/******************************************************************************/
emilmont	77:869cf507173a	3981	/****************** Bits definition for RTC_TR register *****************/
emilmont	77:869cf507173a	3982	#define RTC_TR_PM ((uint32_t)0x00400000)
emilmont	77:869cf507173a	3983	#define RTC_TR_HT ((uint32_t)0x00300000)
emilmont	77:869cf507173a	3984	#define RTC_TR_HT_0 ((uint32_t)0x00100000)
emilmont	77:869cf507173a	3985	#define RTC_TR_HT_1 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	3986	#define RTC_TR_HU ((uint32_t)0x000F0000)
emilmont	77:869cf507173a	3987	#define RTC_TR_HU_0 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	3988	#define RTC_TR_HU_1 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	3989	#define RTC_TR_HU_2 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	3990	#define RTC_TR_HU_3 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	3991	#define RTC_TR_MNT ((uint32_t)0x00007000)
emilmont	77:869cf507173a	3992	#define RTC_TR_MNT_0 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	3993	#define RTC_TR_MNT_1 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	3994	#define RTC_TR_MNT_2 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	3995	#define RTC_TR_MNU ((uint32_t)0x00000F00)
emilmont	77:869cf507173a	3996	#define RTC_TR_MNU_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	3997	#define RTC_TR_MNU_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	3998	#define RTC_TR_MNU_2 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	3999	#define RTC_TR_MNU_3 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	4000	#define RTC_TR_ST ((uint32_t)0x00000070)
emilmont	77:869cf507173a	4001	#define RTC_TR_ST_0 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4002	#define RTC_TR_ST_1 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4003	#define RTC_TR_ST_2 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	4004	#define RTC_TR_SU ((uint32_t)0x0000000F)
emilmont	77:869cf507173a	4005	#define RTC_TR_SU_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4006	#define RTC_TR_SU_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	4007	#define RTC_TR_SU_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4008	#define RTC_TR_SU_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4009
emilmont	77:869cf507173a	4010	/****************** Bits definition for RTC_DR register *****************/
emilmont	77:869cf507173a	4011	#define RTC_DR_YT ((uint32_t)0x00F00000)
emilmont	77:869cf507173a	4012	#define RTC_DR_YT_0 ((uint32_t)0x00100000)
emilmont	77:869cf507173a	4013	#define RTC_DR_YT_1 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	4014	#define RTC_DR_YT_2 ((uint32_t)0x00400000)
emilmont	77:869cf507173a	4015	#define RTC_DR_YT_3 ((uint32_t)0x00800000)
emilmont	77:869cf507173a	4016	#define RTC_DR_YU ((uint32_t)0x000F0000)
emilmont	77:869cf507173a	4017	#define RTC_DR_YU_0 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	4018	#define RTC_DR_YU_1 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	4019	#define RTC_DR_YU_2 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	4020	#define RTC_DR_YU_3 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	4021	#define RTC_DR_WDU ((uint32_t)0x0000E000)
emilmont	77:869cf507173a	4022	#define RTC_DR_WDU_0 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	4023	#define RTC_DR_WDU_1 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	4024	#define RTC_DR_WDU_2 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	4025	#define RTC_DR_MT ((uint32_t)0x00001000)
emilmont	77:869cf507173a	4026	#define RTC_DR_MU ((uint32_t)0x00000F00)
emilmont	77:869cf507173a	4027	#define RTC_DR_MU_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	4028	#define RTC_DR_MU_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	4029	#define RTC_DR_MU_2 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	4030	#define RTC_DR_MU_3 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	4031	#define RTC_DR_DT ((uint32_t)0x00000030)
emilmont	77:869cf507173a	4032	#define RTC_DR_DT_0 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4033	#define RTC_DR_DT_1 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4034	#define RTC_DR_DU ((uint32_t)0x0000000F)
emilmont	77:869cf507173a	4035	#define RTC_DR_DU_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4036	#define RTC_DR_DU_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	4037	#define RTC_DR_DU_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4038	#define RTC_DR_DU_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4039
emilmont	77:869cf507173a	4040	/****************** Bits definition for RTC_CR register *****************/
emilmont	77:869cf507173a	4041	#define RTC_CR_COE ((uint32_t)0x00800000)
emilmont	77:869cf507173a	4042	#define RTC_CR_OSEL ((uint32_t)0x00600000)
emilmont	77:869cf507173a	4043	#define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	4044	#define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
emilmont	77:869cf507173a	4045	#define RTC_CR_POL ((uint32_t)0x00100000)
emilmont	77:869cf507173a	4046	#define RTC_CR_COSEL ((uint32_t)0x00080000)
emilmont	77:869cf507173a	4047	#define RTC_CR_BKP ((uint32_t)0x00040000)
emilmont	77:869cf507173a	4048	#define RTC_CR_SUB1H ((uint32_t)0x00020000)
emilmont	77:869cf507173a	4049	#define RTC_CR_ADD1H ((uint32_t)0x00010000)
emilmont	77:869cf507173a	4050	#define RTC_CR_TSIE ((uint32_t)0x00008000)
emilmont	77:869cf507173a	4051	#define RTC_CR_WUTIE ((uint32_t)0x00004000)
emilmont	77:869cf507173a	4052	#define RTC_CR_ALRAIE ((uint32_t)0x00001000)
emilmont	77:869cf507173a	4053	#define RTC_CR_TSE ((uint32_t)0x00000800)
emilmont	77:869cf507173a	4054	#define RTC_CR_WUTE ((uint32_t)0x00000400)
emilmont	77:869cf507173a	4055	#define RTC_CR_ALRAE ((uint32_t)0x00000100)
emilmont	77:869cf507173a	4056	#define RTC_CR_FMT ((uint32_t)0x00000040)
emilmont	77:869cf507173a	4057	#define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4058	#define RTC_CR_REFCKON ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4059	#define RTC_CR_TSEDGE ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4060	#define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
emilmont	77:869cf507173a	4061	#define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4062	#define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	4063	#define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4064
emilmont	77:869cf507173a	4065	/* Old bit definition maintained for legacy purpose */
emilmont	77:869cf507173a	4066	#define RTC_CR_BCK RTC_CR_BKP
emilmont	77:869cf507173a	4067	#define RTC_CR_CALSEL RTC_CR_COSEL
emilmont	77:869cf507173a	4068
emilmont	77:869cf507173a	4069	/****************** Bits definition for RTC_ISR register ****************/
emilmont	77:869cf507173a	4070	#define RTC_ISR_RECALPF ((uint32_t)0x00010000)
emilmont	77:869cf507173a	4071	#define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
emilmont	77:869cf507173a	4072	#define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
emilmont	77:869cf507173a	4073	#define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
emilmont	77:869cf507173a	4074	#define RTC_ISR_TSOVF ((uint32_t)0x00001000)
emilmont	77:869cf507173a	4075	#define RTC_ISR_TSF ((uint32_t)0x00000800)
emilmont	77:869cf507173a	4076	#define RTC_ISR_WUTF ((uint32_t)0x00000400)
emilmont	77:869cf507173a	4077	#define RTC_ISR_ALRAF ((uint32_t)0x00000100)
emilmont	77:869cf507173a	4078	#define RTC_ISR_INIT ((uint32_t)0x00000080)
emilmont	77:869cf507173a	4079	#define RTC_ISR_INITF ((uint32_t)0x00000040)
emilmont	77:869cf507173a	4080	#define RTC_ISR_RSF ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4081	#define RTC_ISR_INITS ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4082	#define RTC_ISR_SHPF ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4083	#define RTC_ISR_WUTWF ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4084	#define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4085
emilmont	77:869cf507173a	4086	/****************** Bits definition for RTC_PRER register ***************/
emilmont	77:869cf507173a	4087	#define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
emilmont	77:869cf507173a	4088	#define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
emilmont	77:869cf507173a	4089
emilmont	77:869cf507173a	4090	/****************** Bits definition for RTC_WUTR register ***************/
emilmont	77:869cf507173a	4091	#define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
emilmont	77:869cf507173a	4092
emilmont	77:869cf507173a	4093	/****************** Bits definition for RTC_ALRMAR register *************/
emilmont	77:869cf507173a	4094	#define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
emilmont	77:869cf507173a	4095	#define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
emilmont	77:869cf507173a	4096	#define RTC_ALRMAR_DT ((uint32_t)0x30000000)
emilmont	77:869cf507173a	4097	#define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
emilmont	77:869cf507173a	4098	#define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
emilmont	77:869cf507173a	4099	#define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
emilmont	77:869cf507173a	4100	#define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
emilmont	77:869cf507173a	4101	#define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
emilmont	77:869cf507173a	4102	#define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
emilmont	77:869cf507173a	4103	#define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
emilmont	77:869cf507173a	4104	#define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
emilmont	77:869cf507173a	4105	#define RTC_ALRMAR_PM ((uint32_t)0x00400000)
emilmont	77:869cf507173a	4106	#define RTC_ALRMAR_HT ((uint32_t)0x00300000)
emilmont	77:869cf507173a	4107	#define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
emilmont	77:869cf507173a	4108	#define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	4109	#define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
emilmont	77:869cf507173a	4110	#define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	4111	#define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	4112	#define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	4113	#define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	4114	#define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	4115	#define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
emilmont	77:869cf507173a	4116	#define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	4117	#define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	4118	#define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	4119	#define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
emilmont	77:869cf507173a	4120	#define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	4121	#define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	4122	#define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	4123	#define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	4124	#define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	4125	#define RTC_ALRMAR_ST ((uint32_t)0x00000070)
emilmont	77:869cf507173a	4126	#define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4127	#define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4128	#define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	4129	#define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
emilmont	77:869cf507173a	4130	#define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4131	#define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	4132	#define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4133	#define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4134
emilmont	77:869cf507173a	4135	/****************** Bits definition for RTC_WPR register ****************/
emilmont	77:869cf507173a	4136	#define RTC_WPR_KEY ((uint32_t)0x000000FF)
emilmont	77:869cf507173a	4137
emilmont	77:869cf507173a	4138	/****************** Bits definition for RTC_SSR register ****************/
emilmont	77:869cf507173a	4139	#define RTC_SSR_SS ((uint32_t)0x0003FFFF)
emilmont	77:869cf507173a	4140
emilmont	77:869cf507173a	4141	/****************** Bits definition for RTC_SHIFTR register *************/
emilmont	77:869cf507173a	4142	#define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
emilmont	77:869cf507173a	4143	#define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
emilmont	77:869cf507173a	4144
emilmont	77:869cf507173a	4145	/****************** Bits definition for RTC_TSTR register ***************/
emilmont	77:869cf507173a	4146	#define RTC_TSTR_PM ((uint32_t)0x00400000)
emilmont	77:869cf507173a	4147	#define RTC_TSTR_HT ((uint32_t)0x00300000)
emilmont	77:869cf507173a	4148	#define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
emilmont	77:869cf507173a	4149	#define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
emilmont	77:869cf507173a	4150	#define RTC_TSTR_HU ((uint32_t)0x000F0000)
emilmont	77:869cf507173a	4151	#define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
emilmont	77:869cf507173a	4152	#define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
emilmont	77:869cf507173a	4153	#define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
emilmont	77:869cf507173a	4154	#define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
emilmont	77:869cf507173a	4155	#define RTC_TSTR_MNT ((uint32_t)0x00007000)
emilmont	77:869cf507173a	4156	#define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	4157	#define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	4158	#define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	4159	#define RTC_TSTR_MNU ((uint32_t)0x00000F00)
emilmont	77:869cf507173a	4160	#define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	4161	#define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	4162	#define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	4163	#define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	4164	#define RTC_TSTR_ST ((uint32_t)0x00000070)
emilmont	77:869cf507173a	4165	#define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4166	#define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4167	#define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	4168	#define RTC_TSTR_SU ((uint32_t)0x0000000F)
emilmont	77:869cf507173a	4169	#define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4170	#define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	4171	#define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4172	#define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4173
emilmont	77:869cf507173a	4174	/****************** Bits definition for RTC_TSDR register ***************/
emilmont	77:869cf507173a	4175	#define RTC_TSDR_WDU ((uint32_t)0x0000E000)
emilmont	77:869cf507173a	4176	#define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	4177	#define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	4178	#define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
emilmont	77:869cf507173a	4179	#define RTC_TSDR_MT ((uint32_t)0x00001000)
emilmont	77:869cf507173a	4180	#define RTC_TSDR_MU ((uint32_t)0x00000F00)
emilmont	77:869cf507173a	4181	#define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	4182	#define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	4183	#define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	4184	#define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	4185	#define RTC_TSDR_DT ((uint32_t)0x00000030)
emilmont	77:869cf507173a	4186	#define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4187	#define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4188	#define RTC_TSDR_DU ((uint32_t)0x0000000F)
emilmont	77:869cf507173a	4189	#define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4190	#define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	4191	#define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4192	#define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4193
emilmont	77:869cf507173a	4194	/****************** Bits definition for RTC_TSSSR register **************/
emilmont	77:869cf507173a	4195	#define RTC_TSSSR_SS ((uint32_t)0x0003FFFF)
emilmont	77:869cf507173a	4196
emilmont	77:869cf507173a	4197	/****************** Bits definition for RTC_CALR register ****************/
emilmont	77:869cf507173a	4198	#define RTC_CALR_CALP ((uint32_t)0x00008000)
emilmont	77:869cf507173a	4199	#define RTC_CALR_CALW8 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	4200	#define RTC_CALR_CALW16 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	4201	#define RTC_CALR_CALM ((uint32_t)0x000001FF)
emilmont	77:869cf507173a	4202	#define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4203	#define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	4204	#define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4205	#define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4206	#define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4207	#define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4208	#define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	4209	#define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	4210	#define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	4211
emilmont	77:869cf507173a	4212	/* Old Bits definition for RTC_CAL register maintained for legacy purpose */
emilmont	77:869cf507173a	4213	#define RTC_CAL_CALP RTC_CALR_CALP
emilmont	77:869cf507173a	4214	#define RTC_CAL_CALW8 RTC_CALR_CALW8
emilmont	77:869cf507173a	4215	#define RTC_CAL_CALW16 RTC_CALR_CALW16
emilmont	77:869cf507173a	4216	#define RTC_CAL_CALM RTC_CALR_CALM
emilmont	77:869cf507173a	4217	#define RTC_CAL_CALM_0 RTC_CALR_CALM_0
emilmont	77:869cf507173a	4218	#define RTC_CAL_CALM_1 RTC_CALR_CALM_1
emilmont	77:869cf507173a	4219	#define RTC_CAL_CALM_2 RTC_CALR_CALM_2
emilmont	77:869cf507173a	4220	#define RTC_CAL_CALM_3 RTC_CALR_CALM_3
emilmont	77:869cf507173a	4221	#define RTC_CAL_CALM_4 RTC_CALR_CALM_4
emilmont	77:869cf507173a	4222	#define RTC_CAL_CALM_5 RTC_CALR_CALM_5
emilmont	77:869cf507173a	4223	#define RTC_CAL_CALM_6 RTC_CALR_CALM_6
emilmont	77:869cf507173a	4224	#define RTC_CAL_CALM_7 RTC_CALR_CALM_7
emilmont	77:869cf507173a	4225	#define RTC_CAL_CALM_8 RTC_CALR_CALM_8
emilmont	77:869cf507173a	4226
emilmont	77:869cf507173a	4227	/****************** Bits definition for RTC_TAFCR register **************/
emilmont	77:869cf507173a	4228	#define RTC_TAFCR_PC15MODE ((uint32_t)0x00800000)
emilmont	77:869cf507173a	4229	#define RTC_TAFCR_PC15VALUE ((uint32_t)0x00400000)
emilmont	77:869cf507173a	4230	#define RTC_TAFCR_PC14MODE ((uint32_t)0x00200000)
emilmont	77:869cf507173a	4231	#define RTC_TAFCR_PC14VALUE ((uint32_t)0x00100000)
emilmont	77:869cf507173a	4232	#define RTC_TAFCR_PC13MODE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	4233	#define RTC_TAFCR_PC13VALUE ((uint32_t)0x00040000)
emilmont	77:869cf507173a	4234	#define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
emilmont	77:869cf507173a	4235	#define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
emilmont	77:869cf507173a	4236	#define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	4237	#define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	4238	#define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
emilmont	77:869cf507173a	4239	#define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	4240	#define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
emilmont	77:869cf507173a	4241	#define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
emilmont	77:869cf507173a	4242	#define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	4243	#define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
emilmont	77:869cf507173a	4244	#define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
emilmont	77:869cf507173a	4245	#define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
emilmont	77:869cf507173a	4246	#define RTC_TAFCR_TAMP3EDGE ((uint32_t)0x00000040)
emilmont	77:869cf507173a	4247	#define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
emilmont	77:869cf507173a	4248	#define RTC_TAFCR_TAMP2EDGE ((uint32_t)0x00000010)
emilmont	77:869cf507173a	4249	#define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
emilmont	77:869cf507173a	4250	#define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	4251	#define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
emilmont	77:869cf507173a	4252	#define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
emilmont	77:869cf507173a	4253
emilmont	77:869cf507173a	4254	/* Old bit definition maintained for legacy purpose */
emilmont	77:869cf507173a	4255	#define RTC_TAFCR_ALARMOUTTYPE RTC_TAFCR_PC13VALUE
emilmont	77:869cf507173a	4256
emilmont	77:869cf507173a	4257	/****************** Bits definition for RTC_ALRMASSR register ***********/
emilmont	77:869cf507173a	4258	#define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
emilmont	77:869cf507173a	4259	#define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
emilmont	77:869cf507173a	4260	#define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
emilmont	77:869cf507173a	4261	#define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
emilmont	77:869cf507173a	4262	#define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
emilmont	77:869cf507173a	4263	#define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
emilmont	77:869cf507173a	4264
emilmont	77:869cf507173a	4265	/****************** Bits definition for RTC_BKP0R register **************/
emilmont	77:869cf507173a	4266	#define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
emilmont	77:869cf507173a	4267
emilmont	77:869cf507173a	4268	/****************** Bits definition for RTC_BKP1R register **************/
emilmont	77:869cf507173a	4269	#define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
emilmont	77:869cf507173a	4270
emilmont	77:869cf507173a	4271	/****************** Bits definition for RTC_BKP2R register **************/
emilmont	77:869cf507173a	4272	#define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
emilmont	77:869cf507173a	4273
emilmont	77:869cf507173a	4274	/****************** Bits definition for RTC_BKP3R register **************/
emilmont	77:869cf507173a	4275	#define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
emilmont	77:869cf507173a	4276
emilmont	77:869cf507173a	4277	/****************** Bits definition for RTC_BKP4R register **************/
emilmont	77:869cf507173a	4278	#define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
emilmont	77:869cf507173a	4279
emilmont	77:869cf507173a	4280	/******************************************************************************/
emilmont	77:869cf507173a	4281	/* */
emilmont	77:869cf507173a	4282	/* Serial Peripheral Interface (SPI) */
emilmont	77:869cf507173a	4283	/* */
emilmont	77:869cf507173a	4284	/******************************************************************************/
emilmont	77:869cf507173a	4285	/***************** Bit definition for SPI_CR1 register ******************/
emilmont	77:869cf507173a	4286	#define SPI_CR1_CPHA ((uint16_t)0x0001) /!< Clock Phase /
emilmont	77:869cf507173a	4287	#define SPI_CR1_CPOL ((uint16_t)0x0002) /!< Clock Polarity /
emilmont	77:869cf507173a	4288	#define SPI_CR1_MSTR ((uint16_t)0x0004) /!< Master Selection /
emilmont	77:869cf507173a	4289	#define SPI_CR1_BR ((uint16_t)0x0038) /!< BR[2:0] bits (Baud Rate Control) /
emilmont	77:869cf507173a	4290	#define SPI_CR1_BR_0 ((uint16_t)0x0008) /!< Bit 0 /
emilmont	77:869cf507173a	4291	#define SPI_CR1_BR_1 ((uint16_t)0x0010) /!< Bit 1 /
emilmont	77:869cf507173a	4292	#define SPI_CR1_BR_2 ((uint16_t)0x0020) /!< Bit 2 /
emilmont	77:869cf507173a	4293	#define SPI_CR1_SPE ((uint16_t)0x0040) /!< SPI Enable /
emilmont	77:869cf507173a	4294	#define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /!< Frame Format /
emilmont	77:869cf507173a	4295	#define SPI_CR1_SSI ((uint16_t)0x0100) /!< Internal slave select /
emilmont	77:869cf507173a	4296	#define SPI_CR1_SSM ((uint16_t)0x0200) /!< Software slave management /
emilmont	77:869cf507173a	4297	#define SPI_CR1_RXONLY ((uint16_t)0x0400) /!< Receive only /
emilmont	77:869cf507173a	4298	#define SPI_CR1_CRCL ((uint16_t)0x0800) /!< CRC Length /
emilmont	77:869cf507173a	4299	#define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /!< Transmit CRC next /
emilmont	77:869cf507173a	4300	#define SPI_CR1_CRCEN ((uint16_t)0x2000) /!< Hardware CRC calculation enable /
emilmont	77:869cf507173a	4301	#define SPI_CR1_BIDIOE ((uint16_t)0x4000) /!< Output enable in bidirectional mode /
emilmont	77:869cf507173a	4302	#define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /!< Bidirectional data mode enable /
emilmont	77:869cf507173a	4303
emilmont	77:869cf507173a	4304	/***************** Bit definition for SPI_CR2 register ******************/
emilmont	77:869cf507173a	4305	#define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /!< Rx Buffer DMA Enable /
emilmont	77:869cf507173a	4306	#define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /!< Tx Buffer DMA Enable /
emilmont	77:869cf507173a	4307	#define SPI_CR2_SSOE ((uint16_t)0x0004) /!< SS Output Enable /
emilmont	77:869cf507173a	4308	#define SPI_CR2_NSSP ((uint16_t)0x0008) /!< NSS pulse management Enable /
emilmont	77:869cf507173a	4309	#define SPI_CR2_FRF ((uint16_t)0x0010) /!< Frame Format Enable /
emilmont	77:869cf507173a	4310	#define SPI_CR2_ERRIE ((uint16_t)0x0020) /!< Error Interrupt Enable /
emilmont	77:869cf507173a	4311	#define SPI_CR2_RXNEIE ((uint16_t)0x0040) /!< RX buffer Not Empty Interrupt Enable /
emilmont	77:869cf507173a	4312	#define SPI_CR2_TXEIE ((uint16_t)0x0080) /!< Tx buffer Empty Interrupt Enable /
emilmont	77:869cf507173a	4313	#define SPI_CR2_DS ((uint16_t)0x0F00) /!< DS[3:0] Data Size /
emilmont	77:869cf507173a	4314	#define SPI_CR2_DS_0 ((uint16_t)0x0100) /!< Bit 0 /
emilmont	77:869cf507173a	4315	#define SPI_CR2_DS_1 ((uint16_t)0x0200) /!< Bit 1 /
emilmont	77:869cf507173a	4316	#define SPI_CR2_DS_2 ((uint16_t)0x0400) /!< Bit 2 /
emilmont	77:869cf507173a	4317	#define SPI_CR2_DS_3 ((uint16_t)0x0800) /!< Bit 3 /
emilmont	77:869cf507173a	4318	#define SPI_CR2_FRXTH ((uint16_t)0x1000) /!< FIFO reception Threshold /
emilmont	77:869cf507173a	4319	#define SPI_CR2_LDMARX ((uint16_t)0x2000) /!< Last DMA transfer for reception /
emilmont	77:869cf507173a	4320	#define SPI_CR2_LDMATX ((uint16_t)0x4000) /!< Last DMA transfer for transmission /
emilmont	77:869cf507173a	4321
emilmont	77:869cf507173a	4322	/****************** Bit definition for SPI_SR register ******************/
emilmont	77:869cf507173a	4323	#define SPI_SR_RXNE ((uint16_t)0x0001) /!< Receive buffer Not Empty /
emilmont	77:869cf507173a	4324	#define SPI_SR_TXE ((uint16_t)0x0002) /!< Transmit buffer Empty /
emilmont	77:869cf507173a	4325	#define SPI_SR_CHSIDE ((uint16_t)0x0004) /!< Channel side /
emilmont	77:869cf507173a	4326	#define SPI_SR_UDR ((uint16_t)0x0008) /!< Underrun flag /
emilmont	77:869cf507173a	4327	#define SPI_SR_CRCERR ((uint16_t)0x0010) /!< CRC Error flag /
emilmont	77:869cf507173a	4328	#define SPI_SR_MODF ((uint16_t)0x0020) /!< Mode fault /
emilmont	77:869cf507173a	4329	#define SPI_SR_OVR ((uint16_t)0x0040) /!< Overrun flag /
emilmont	77:869cf507173a	4330	#define SPI_SR_BSY ((uint16_t)0x0080) /!< Busy flag /
emilmont	77:869cf507173a	4331	#define SPI_SR_FRE ((uint16_t)0x0100) /!< TI frame format error /
emilmont	77:869cf507173a	4332	#define SPI_SR_FRLVL ((uint16_t)0x0600) /!< FIFO Reception Level /
emilmont	77:869cf507173a	4333	#define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /!< Bit 0 /
emilmont	77:869cf507173a	4334	#define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /!< Bit 1 /
emilmont	77:869cf507173a	4335	#define SPI_SR_FTLVL ((uint16_t)0x1800) /!< FIFO Transmission Level /
emilmont	77:869cf507173a	4336	#define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /!< Bit 0 /
emilmont	77:869cf507173a	4337	#define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /!< Bit 1 /
emilmont	77:869cf507173a	4338
emilmont	77:869cf507173a	4339	/****************** Bit definition for SPI_DR register ******************/
emilmont	77:869cf507173a	4340	#define SPI_DR_DR ((uint16_t)0xFFFF) /!< Data Register /
emilmont	77:869cf507173a	4341
emilmont	77:869cf507173a	4342	/***************** Bit definition for SPI_CRCPR register ****************/
emilmont	77:869cf507173a	4343	#define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /!< CRC polynomial register /
emilmont	77:869cf507173a	4344
emilmont	77:869cf507173a	4345	/**************** Bit definition for SPI_RXCRCR register ****************/
emilmont	77:869cf507173a	4346	#define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /!< Rx CRC Register /
emilmont	77:869cf507173a	4347
emilmont	77:869cf507173a	4348	/**************** Bit definition for SPI_TXCRCR register ****************/
emilmont	77:869cf507173a	4349	#define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /!< Tx CRC Register /
emilmont	77:869cf507173a	4350
emilmont	77:869cf507173a	4351	/**************** Bit definition for SPI_I2SCFGR register ***************/
emilmont	77:869cf507173a	4352	#define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /!<Channel length (number of bits per audio channel) /
emilmont	77:869cf507173a	4353	#define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /!<DATLEN[1:0] bits (Data length to be transferred) /
emilmont	77:869cf507173a	4354	#define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /!<Bit 0 /
emilmont	77:869cf507173a	4355	#define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /!<Bit 1 /
emilmont	77:869cf507173a	4356	#define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /!<steady state clock polarity /
emilmont	77:869cf507173a	4357	#define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /!<I2SSTD[1:0] bits (I2S standard selection) /
emilmont	77:869cf507173a	4358	#define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /!<Bit 0 /
emilmont	77:869cf507173a	4359	#define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /!<Bit 1 /
emilmont	77:869cf507173a	4360	#define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /!<PCM frame synchronization /
emilmont	77:869cf507173a	4361	#define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /!<I2SCFG[1:0] bits (I2S configuration mode) /
emilmont	77:869cf507173a	4362	#define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /!<Bit 0 /
emilmont	77:869cf507173a	4363	#define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /!<Bit 1 /
emilmont	77:869cf507173a	4364	#define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /!<I2S Enable /
emilmont	77:869cf507173a	4365	#define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /!<I2S mode selection /
emilmont	77:869cf507173a	4366
emilmont	77:869cf507173a	4367	/**************** Bit definition for SPI_I2SPR register *****************/
emilmont	77:869cf507173a	4368	#define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /!<I2S Linear prescaler /
emilmont	77:869cf507173a	4369	#define SPI_I2SPR_ODD ((uint16_t)0x0100) /!<Odd factor for the prescaler /
emilmont	77:869cf507173a	4370	#define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /!<Master Clock Output Enable /
emilmont	77:869cf507173a	4371
emilmont	77:869cf507173a	4372	/******************************************************************************/
emilmont	77:869cf507173a	4373	/* */
emilmont	77:869cf507173a	4374	/* System Configuration (SYSCFG) */
emilmont	77:869cf507173a	4375	/* */
emilmont	77:869cf507173a	4376	/******************************************************************************/
emilmont	77:869cf507173a	4377	/*************** Bit definition for SYSCFG_CFGR1 register **************/
emilmont	77:869cf507173a	4378	#define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /!< SYSCFG_Memory Remap Config /
emilmont	77:869cf507173a	4379	#define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /!< SYSCFG_Memory Remap Config Bit 0 /
emilmont	77:869cf507173a	4380	#define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /!< SYSCFG_Memory Remap Config Bit 1 /
emilmont	77:869cf507173a	4381	#define SYSCFG_CFGR1_PA11_PA12_RMP ((uint32_t)0x00000010) /!< PA11 and PA12 remap on QFN28 and TSSOP20 packages (only for STM32F042 devices)/
emilmont	77:869cf507173a	4382	#define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /!< ADC DMA remap /
emilmont	77:869cf507173a	4383	#define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /!< USART1 TX DMA remap /
emilmont	77:869cf507173a	4384	#define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /!< USART1 RX DMA remap /
emilmont	77:869cf507173a	4385	#define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /!< Timer 16 DMA remap /
emilmont	77:869cf507173a	4386	#define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /!< Timer 17 DMA remap /
emilmont	77:869cf507173a	4387	#define SYSCFG_CFGR1_TIM16_DMA_RMP2 ((uint32_t)0x00002000) /!< Timer 16 DMA remap 2 (only for STM32F072) /
emilmont	77:869cf507173a	4388	#define SYSCFG_CFGR1_TIM17_DMA_RMP2 ((uint32_t)0x00004000) /!< Timer 17 DMA remap 2 (only for STM32F072) /
emilmont	77:869cf507173a	4389	#define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /!< I2C PB6 Fast mode plus /
emilmont	77:869cf507173a	4390	#define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /!< I2C PB7 Fast mode plus /
emilmont	77:869cf507173a	4391	#define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /!< I2C PB8 Fast mode plus /
emilmont	77:869cf507173a	4392	#define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /!< I2C PB9 Fast mode plus /
emilmont	77:869cf507173a	4393	#define SYSCFG_CFGR1_I2C_FMP_I2C1 ((uint32_t)0x00100000) /!< Enable Fast Mode Plus on PB10, PB11, PF6 and PF7(only for STM32F030, STM32F031 and STM32F072 devices) /
emilmont	77:869cf507173a	4394	#define SYSCFG_CFGR1_I2C_FMP_I2C2 ((uint32_t)0x00200000) /!< Enable I2C2 Fast mode plus (only for STM32F072) /
emilmont	77:869cf507173a	4395	#define SYSCFG_CFGR1_I2C_FMP_PA9 ((uint32_t)0x00400000) /!< Enable Fast Mode Plus on PA9 (only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) /
emilmont	77:869cf507173a	4396	#define SYSCFG_CFGR1_I2C_FMP_PA10 ((uint32_t)0x00800000) /!< Enable Fast Mode Plus on PA10(only for STM32F030, STM32F031, STM32F042 and STM32F072 devices) /
emilmont	77:869cf507173a	4397	#define SYSCFG_CFGR1_SPI2_DMA_RMP ((uint32_t)0x01000000) /!< SPI2 DMA remap (only for STM32F072) /
emilmont	77:869cf507173a	4398	#define SYSCFG_CFGR1_USART2_DMA_RMP ((uint32_t)0x02000000) /!< USART2 DMA remap (only for STM32F072) /
emilmont	77:869cf507173a	4399	#define SYSCFG_CFGR1_USART3_DMA_RMP ((uint32_t)0x04000000) /!< USART3 DMA remap (only for STM32F072) /
emilmont	77:869cf507173a	4400	#define SYSCFG_CFGR1_I2C1_DMA_RMP ((uint32_t)0x08000000) /!< I2C1 DMA remap (only for STM32F072) /
emilmont	77:869cf507173a	4401	#define SYSCFG_CFGR1_TIM1_DMA_RMP ((uint32_t)0x10000000) /!< TIM1 DMA remap (only for STM32F072) /
emilmont	77:869cf507173a	4402	#define SYSCFG_CFGR1_TIM2_DMA_RMP ((uint32_t)0x20000000) /!< TIM2 DMA remap (only for STM32F072) /
emilmont	77:869cf507173a	4403	#define SYSCFG_CFGR1_TIM3_DMA_RMP ((uint32_t)0x40000000) /!< TIM3 DMA remap (only for STM32F072) /
emilmont	77:869cf507173a	4404
emilmont	77:869cf507173a	4405	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
emilmont	77:869cf507173a	4406	#define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /!< EXTI 0 configuration /
emilmont	77:869cf507173a	4407	#define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /!< EXTI 1 configuration /
emilmont	77:869cf507173a	4408	#define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /!< EXTI 2 configuration /
emilmont	77:869cf507173a	4409	#define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /!< EXTI 3 configuration /
emilmont	77:869cf507173a	4410
emilmont	77:869cf507173a	4411	/**
emilmont	77:869cf507173a	4412	* @brief EXTI0 configuration
emilmont	77:869cf507173a	4413	*/
emilmont	77:869cf507173a	4414	#define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /!< PA[0] pin /
emilmont	77:869cf507173a	4415	#define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /!< PB[0] pin /
emilmont	77:869cf507173a	4416	#define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /!< PC[0] pin /
emilmont	77:869cf507173a	4417	#define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /!< PD[0] pin /
emilmont	77:869cf507173a	4418	#define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /!< PE[0] pin /
emilmont	77:869cf507173a	4419	#define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /!< PF[0] pin /
emilmont	77:869cf507173a	4420
emilmont	77:869cf507173a	4421	/**
emilmont	77:869cf507173a	4422	* @brief EXTI1 configuration
emilmont	77:869cf507173a	4423	*/
emilmont	77:869cf507173a	4424	#define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /!< PA[1] pin /
emilmont	77:869cf507173a	4425	#define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /!< PB[1] pin /
emilmont	77:869cf507173a	4426	#define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /!< PC[1] pin /
emilmont	77:869cf507173a	4427	#define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /!< PD[1] pin /
emilmont	77:869cf507173a	4428	#define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /!< PE[1] pin /
emilmont	77:869cf507173a	4429	#define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /!< PF[1] pin /
emilmont	77:869cf507173a	4430
emilmont	77:869cf507173a	4431	/**
emilmont	77:869cf507173a	4432	* @brief EXTI2 configuration
emilmont	77:869cf507173a	4433	*/
emilmont	77:869cf507173a	4434	#define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /!< PA[2] pin /
emilmont	77:869cf507173a	4435	#define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /!< PB[2] pin /
emilmont	77:869cf507173a	4436	#define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /!< PC[2] pin /
emilmont	77:869cf507173a	4437	#define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /!< PD[2] pin /
emilmont	77:869cf507173a	4438	#define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /!< PE[2] pin /
emilmont	77:869cf507173a	4439	#define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /!< PF[2] pin /
emilmont	77:869cf507173a	4440
emilmont	77:869cf507173a	4441	/**
emilmont	77:869cf507173a	4442	* @brief EXTI3 configuration
emilmont	77:869cf507173a	4443	*/
emilmont	77:869cf507173a	4444	#define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /!< PA[3] pin /
emilmont	77:869cf507173a	4445	#define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /!< PB[3] pin /
emilmont	77:869cf507173a	4446	#define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /!< PC[3] pin /
emilmont	77:869cf507173a	4447	#define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /!< PD[3] pin /
emilmont	77:869cf507173a	4448	#define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /!< PE[3] pin /
emilmont	77:869cf507173a	4449	#define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x5000) /!< PF[3] pin /
emilmont	77:869cf507173a	4450
emilmont	77:869cf507173a	4451	/*************** Bit definition for SYSCFG_EXTICR2 register ***************/
emilmont	77:869cf507173a	4452	#define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /!< EXTI 4 configuration /
emilmont	77:869cf507173a	4453	#define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /!< EXTI 5 configuration /
emilmont	77:869cf507173a	4454	#define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /!< EXTI 6 configuration /
emilmont	77:869cf507173a	4455	#define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /!< EXTI 7 configuration /
emilmont	77:869cf507173a	4456
emilmont	77:869cf507173a	4457	/**
emilmont	77:869cf507173a	4458	* @brief EXTI4 configuration
emilmont	77:869cf507173a	4459	*/
emilmont	77:869cf507173a	4460	#define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /!< PA[4] pin /
emilmont	77:869cf507173a	4461	#define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /!< PB[4] pin /
emilmont	77:869cf507173a	4462	#define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /!< PC[4] pin /
emilmont	77:869cf507173a	4463	#define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /!< PD[4] pin /
emilmont	77:869cf507173a	4464	#define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /!< PE[4] pin /
emilmont	77:869cf507173a	4465	#define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0005) /!< PF[4] pin /
emilmont	77:869cf507173a	4466
emilmont	77:869cf507173a	4467	/**
emilmont	77:869cf507173a	4468	* @brief EXTI5 configuration
emilmont	77:869cf507173a	4469	*/
emilmont	77:869cf507173a	4470	#define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /!< PA[5] pin /
emilmont	77:869cf507173a	4471	#define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /!< PB[5] pin /
emilmont	77:869cf507173a	4472	#define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /!< PC[5] pin /
emilmont	77:869cf507173a	4473	#define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /!< PD[5] pin /
emilmont	77:869cf507173a	4474	#define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /!< PE[5] pin /
emilmont	77:869cf507173a	4475	#define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0050) /!< PF[5] pin /
emilmont	77:869cf507173a	4476
emilmont	77:869cf507173a	4477	/**
emilmont	77:869cf507173a	4478	* @brief EXTI6 configuration
emilmont	77:869cf507173a	4479	*/
emilmont	77:869cf507173a	4480	#define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /!< PA[6] pin /
emilmont	77:869cf507173a	4481	#define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /!< PB[6] pin /
emilmont	77:869cf507173a	4482	#define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /!< PC[6] pin /
emilmont	77:869cf507173a	4483	#define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /!< PD[6] pin /
emilmont	77:869cf507173a	4484	#define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /!< PE[6] pin /
emilmont	77:869cf507173a	4485	#define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0500) /!< PF[6] pin /
emilmont	77:869cf507173a	4486
emilmont	77:869cf507173a	4487	/**
emilmont	77:869cf507173a	4488	* @brief EXTI7 configuration
emilmont	77:869cf507173a	4489	*/
emilmont	77:869cf507173a	4490	#define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /!< PA[7] pin /
emilmont	77:869cf507173a	4491	#define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /!< PB[7] pin /
emilmont	77:869cf507173a	4492	#define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /!< PC[7] pin /
emilmont	77:869cf507173a	4493	#define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /!< PD[7] pin /
emilmont	77:869cf507173a	4494	#define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /!< PE[7] pin /
emilmont	77:869cf507173a	4495	#define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x5000) /!< PF[7] pin /
emilmont	77:869cf507173a	4496
emilmont	77:869cf507173a	4497	/*************** Bit definition for SYSCFG_EXTICR3 register ***************/
emilmont	77:869cf507173a	4498	#define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /!< EXTI 8 configuration /
emilmont	77:869cf507173a	4499	#define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /!< EXTI 9 configuration /
emilmont	77:869cf507173a	4500	#define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /!< EXTI 10 configuration /
emilmont	77:869cf507173a	4501	#define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /!< EXTI 11 configuration /
emilmont	77:869cf507173a	4502
emilmont	77:869cf507173a	4503	/**
emilmont	77:869cf507173a	4504	* @brief EXTI8 configuration
emilmont	77:869cf507173a	4505	*/
emilmont	77:869cf507173a	4506	#define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /!< PA[8] pin /
emilmont	77:869cf507173a	4507	#define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /!< PB[8] pin /
emilmont	77:869cf507173a	4508	#define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /!< PC[8] pin /
emilmont	77:869cf507173a	4509	#define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /!< PD[8] pin /
emilmont	77:869cf507173a	4510	#define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /!< PE[8] pin /
emilmont	77:869cf507173a	4511
emilmont	77:869cf507173a	4512	/**
emilmont	77:869cf507173a	4513	* @brief EXTI9 configuration
emilmont	77:869cf507173a	4514	*/
emilmont	77:869cf507173a	4515	#define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /!< PA[9] pin /
emilmont	77:869cf507173a	4516	#define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /!< PB[9] pin /
emilmont	77:869cf507173a	4517	#define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /!< PC[9] pin /
emilmont	77:869cf507173a	4518	#define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /!< PD[9] pin /
emilmont	77:869cf507173a	4519	#define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /!< PE[9] pin /
emilmont	77:869cf507173a	4520	#define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /!< PF[9] pin /
emilmont	77:869cf507173a	4521
emilmont	77:869cf507173a	4522	/**
emilmont	77:869cf507173a	4523	* @brief EXTI10 configuration
emilmont	77:869cf507173a	4524	*/
emilmont	77:869cf507173a	4525	#define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /!< PA[10] pin /
emilmont	77:869cf507173a	4526	#define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /!< PB[10] pin /
emilmont	77:869cf507173a	4527	#define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /!< PC[10] pin /
emilmont	77:869cf507173a	4528	#define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /!< PE[10] pin /
emilmont	77:869cf507173a	4529	#define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /!< PD[10] pin /
emilmont	77:869cf507173a	4530	#define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /!< PF[10] pin /
emilmont	77:869cf507173a	4531
emilmont	77:869cf507173a	4532	/**
emilmont	77:869cf507173a	4533	* @brief EXTI11 configuration
emilmont	77:869cf507173a	4534	*/
emilmont	77:869cf507173a	4535	#define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /!< PA[11] pin /
emilmont	77:869cf507173a	4536	#define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /!< PB[11] pin /
emilmont	77:869cf507173a	4537	#define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /!< PC[11] pin /
emilmont	77:869cf507173a	4538	#define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /!< PD[11] pin /
emilmont	77:869cf507173a	4539	#define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /!< PE[11] pin /
emilmont	77:869cf507173a	4540
emilmont	77:869cf507173a	4541	/*************** Bit definition for SYSCFG_EXTICR4 register ***************/
emilmont	77:869cf507173a	4542	#define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /!< EXTI 12 configuration /
emilmont	77:869cf507173a	4543	#define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /!< EXTI 13 configuration /
emilmont	77:869cf507173a	4544	#define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /!< EXTI 14 configuration /
emilmont	77:869cf507173a	4545	#define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /!< EXTI 15 configuration /
emilmont	77:869cf507173a	4546
emilmont	77:869cf507173a	4547	/**
emilmont	77:869cf507173a	4548	* @brief EXTI12 configuration
emilmont	77:869cf507173a	4549	*/
emilmont	77:869cf507173a	4550	#define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /!< PA[12] pin /
emilmont	77:869cf507173a	4551	#define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /!< PB[12] pin /
emilmont	77:869cf507173a	4552	#define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /!< PC[12] pin /
emilmont	77:869cf507173a	4553	#define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /!< PD[12] pin /
emilmont	77:869cf507173a	4554	#define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /!< PE[12] pin /
emilmont	77:869cf507173a	4555
emilmont	77:869cf507173a	4556	/**
emilmont	77:869cf507173a	4557	* @brief EXTI13 configuration
emilmont	77:869cf507173a	4558	*/
emilmont	77:869cf507173a	4559	#define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /!< PA[13] pin /
emilmont	77:869cf507173a	4560	#define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /!< PB[13] pin /
emilmont	77:869cf507173a	4561	#define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /!< PC[13] pin /
emilmont	77:869cf507173a	4562	#define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /!< PD[13] pin /
emilmont	77:869cf507173a	4563	#define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /!< PE[13] pin /
emilmont	77:869cf507173a	4564
emilmont	77:869cf507173a	4565	/**
emilmont	77:869cf507173a	4566	* @brief EXTI14 configuration
emilmont	77:869cf507173a	4567	*/
emilmont	77:869cf507173a	4568	#define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /!< PA[14] pin /
emilmont	77:869cf507173a	4569	#define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /!< PB[14] pin /
emilmont	77:869cf507173a	4570	#define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /!< PC[14] pin /
emilmont	77:869cf507173a	4571	#define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /!< PD[14] pin /
emilmont	77:869cf507173a	4572	#define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /!< PE[14] pin /
emilmont	77:869cf507173a	4573
emilmont	77:869cf507173a	4574	/**
emilmont	77:869cf507173a	4575	* @brief EXTI15 configuration
emilmont	77:869cf507173a	4576	*/
emilmont	77:869cf507173a	4577	#define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /!< PA[15] pin /
emilmont	77:869cf507173a	4578	#define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /!< PB[15] pin /
emilmont	77:869cf507173a	4579	#define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /!< PC[15] pin /
emilmont	77:869cf507173a	4580	#define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /!< PD[15] pin /
emilmont	77:869cf507173a	4581	#define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /!< PE[15] pin /
emilmont	77:869cf507173a	4582
emilmont	77:869cf507173a	4583	/*************** Bit definition for SYSCFG_CFGR2 register **************/
emilmont	77:869cf507173a	4584	#define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /!< Enables and locks the PVD connection with Timer1 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface /
emilmont	77:869cf507173a	4585	#define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 /
emilmont	77:869cf507173a	4586	#define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 /
emilmont	77:869cf507173a	4587	#define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /!< SRAM Parity error flag /
emilmont	77:869cf507173a	4588
emilmont	77:869cf507173a	4589	/* Old Bit definition maintained for legacy purpose */
emilmont	77:869cf507173a	4590	#define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF
emilmont	77:869cf507173a	4591	/******************************************************************************/
emilmont	77:869cf507173a	4592	/* */
emilmont	77:869cf507173a	4593	/* Timers (TIM) */
emilmont	77:869cf507173a	4594	/* */
emilmont	77:869cf507173a	4595	/******************************************************************************/
emilmont	77:869cf507173a	4596	/***************** Bit definition for TIM_CR1 register ******************/
emilmont	77:869cf507173a	4597	#define TIM_CR1_CEN ((uint16_t)0x0001) /!<Counter enable /
emilmont	77:869cf507173a	4598	#define TIM_CR1_UDIS ((uint16_t)0x0002) /!<Update disable /
emilmont	77:869cf507173a	4599	#define TIM_CR1_URS ((uint16_t)0x0004) /!<Update request source /
emilmont	77:869cf507173a	4600	#define TIM_CR1_OPM ((uint16_t)0x0008) /!<One pulse mode /
emilmont	77:869cf507173a	4601	#define TIM_CR1_DIR ((uint16_t)0x0010) /!<Direction /
emilmont	77:869cf507173a	4602
emilmont	77:869cf507173a	4603	#define TIM_CR1_CMS ((uint16_t)0x0060) /!<CMS[1:0] bits (Center-aligned mode selection) /
emilmont	77:869cf507173a	4604	#define TIM_CR1_CMS_0 ((uint16_t)0x0020) /!<Bit 0 /
emilmont	77:869cf507173a	4605	#define TIM_CR1_CMS_1 ((uint16_t)0x0040) /!<Bit 1 /
emilmont	77:869cf507173a	4606
emilmont	77:869cf507173a	4607	#define TIM_CR1_ARPE ((uint16_t)0x0080) /!<Auto-reload preload enable /
emilmont	77:869cf507173a	4608
emilmont	77:869cf507173a	4609	#define TIM_CR1_CKD ((uint16_t)0x0300) /!<CKD[1:0] bits (clock division) /
emilmont	77:869cf507173a	4610	#define TIM_CR1_CKD_0 ((uint16_t)0x0100) /!<Bit 0 /
emilmont	77:869cf507173a	4611	#define TIM_CR1_CKD_1 ((uint16_t)0x0200) /!<Bit 1 /
emilmont	77:869cf507173a	4612
emilmont	77:869cf507173a	4613	/***************** Bit definition for TIM_CR2 register ******************/
emilmont	77:869cf507173a	4614	#define TIM_CR2_CCPC ((uint16_t)0x0001) /!<Capture/Compare Preloaded Control /
emilmont	77:869cf507173a	4615	#define TIM_CR2_CCUS ((uint16_t)0x0004) /!<Capture/Compare Control Update Selection /
emilmont	77:869cf507173a	4616	#define TIM_CR2_CCDS ((uint16_t)0x0008) /!<Capture/Compare DMA Selection /
emilmont	77:869cf507173a	4617
emilmont	77:869cf507173a	4618	#define TIM_CR2_MMS ((uint16_t)0x0070) /!<MMS[2:0] bits (Master Mode Selection) /
emilmont	77:869cf507173a	4619	#define TIM_CR2_MMS_0 ((uint16_t)0x0010) /!<Bit 0 /
emilmont	77:869cf507173a	4620	#define TIM_CR2_MMS_1 ((uint16_t)0x0020) /!<Bit 1 /
emilmont	77:869cf507173a	4621	#define TIM_CR2_MMS_2 ((uint16_t)0x0040) /!<Bit 2 /
emilmont	77:869cf507173a	4622
emilmont	77:869cf507173a	4623	#define TIM_CR2_TI1S ((uint16_t)0x0080) /!<TI1 Selection /
emilmont	77:869cf507173a	4624	#define TIM_CR2_OIS1 ((uint16_t)0x0100) /!<Output Idle state 1 (OC1 output) /
emilmont	77:869cf507173a	4625	#define TIM_CR2_OIS1N ((uint16_t)0x0200) /!<Output Idle state 1 (OC1N output) /
emilmont	77:869cf507173a	4626	#define TIM_CR2_OIS2 ((uint16_t)0x0400) /!<Output Idle state 2 (OC2 output) /
emilmont	77:869cf507173a	4627	#define TIM_CR2_OIS2N ((uint16_t)0x0800) /!<Output Idle state 2 (OC2N output) /
emilmont	77:869cf507173a	4628	#define TIM_CR2_OIS3 ((uint16_t)0x1000) /!<Output Idle state 3 (OC3 output) /
emilmont	77:869cf507173a	4629	#define TIM_CR2_OIS3N ((uint16_t)0x2000) /!<Output Idle state 3 (OC3N output) /
emilmont	77:869cf507173a	4630	#define TIM_CR2_OIS4 ((uint16_t)0x4000) /!<Output Idle state 4 (OC4 output) /
emilmont	77:869cf507173a	4631
emilmont	77:869cf507173a	4632	/***************** Bit definition for TIM_SMCR register *****************/
emilmont	77:869cf507173a	4633	#define TIM_SMCR_SMS ((uint16_t)0x0007) /!<SMS[2:0] bits (Slave mode selection) /
emilmont	77:869cf507173a	4634	#define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /!<Bit 0 /
emilmont	77:869cf507173a	4635	#define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /!<Bit 1 /
emilmont	77:869cf507173a	4636	#define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /!<Bit 2 /
emilmont	77:869cf507173a	4637
emilmont	77:869cf507173a	4638	#define TIM_SMCR_OCCS ((uint16_t)0x0008) /!< OCREF clear selection /
emilmont	77:869cf507173a	4639
emilmont	77:869cf507173a	4640	#define TIM_SMCR_TS ((uint16_t)0x0070) /!<TS[2:0] bits (Trigger selection) /
emilmont	77:869cf507173a	4641	#define TIM_SMCR_TS_0 ((uint16_t)0x0010) /!<Bit 0 /
emilmont	77:869cf507173a	4642	#define TIM_SMCR_TS_1 ((uint16_t)0x0020) /!<Bit 1 /
emilmont	77:869cf507173a	4643	#define TIM_SMCR_TS_2 ((uint16_t)0x0040) /!<Bit 2 /
emilmont	77:869cf507173a	4644
emilmont	77:869cf507173a	4645	#define TIM_SMCR_MSM ((uint16_t)0x0080) /!<Master/slave mode /
emilmont	77:869cf507173a	4646
emilmont	77:869cf507173a	4647	#define TIM_SMCR_ETF ((uint16_t)0x0F00) /!<ETF[3:0] bits (External trigger filter) /
emilmont	77:869cf507173a	4648	#define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /!<Bit 0 /
emilmont	77:869cf507173a	4649	#define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /!<Bit 1 /
emilmont	77:869cf507173a	4650	#define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /!<Bit 2 /
emilmont	77:869cf507173a	4651	#define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /!<Bit 3 /
emilmont	77:869cf507173a	4652
emilmont	77:869cf507173a	4653	#define TIM_SMCR_ETPS ((uint16_t)0x3000) /!<ETPS[1:0] bits (External trigger prescaler) /
emilmont	77:869cf507173a	4654	#define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /!<Bit 0 /
emilmont	77:869cf507173a	4655	#define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /!<Bit 1 /
emilmont	77:869cf507173a	4656
emilmont	77:869cf507173a	4657	#define TIM_SMCR_ECE ((uint16_t)0x4000) /!<External clock enable /
emilmont	77:869cf507173a	4658	#define TIM_SMCR_ETP ((uint16_t)0x8000) /!<External trigger polarity /
emilmont	77:869cf507173a	4659
emilmont	77:869cf507173a	4660	/***************** Bit definition for TIM_DIER register *****************/
emilmont	77:869cf507173a	4661	#define TIM_DIER_UIE ((uint16_t)0x0001) /!<Update interrupt enable /
emilmont	77:869cf507173a	4662	#define TIM_DIER_CC1IE ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt enable /
emilmont	77:869cf507173a	4663	#define TIM_DIER_CC2IE ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt enable /
emilmont	77:869cf507173a	4664	#define TIM_DIER_CC3IE ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt enable /
emilmont	77:869cf507173a	4665	#define TIM_DIER_CC4IE ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt enable /
emilmont	77:869cf507173a	4666	#define TIM_DIER_COMIE ((uint16_t)0x0020) /!<COM interrupt enable /
emilmont	77:869cf507173a	4667	#define TIM_DIER_TIE ((uint16_t)0x0040) /!<Trigger interrupt enable /
emilmont	77:869cf507173a	4668	#define TIM_DIER_BIE ((uint16_t)0x0080) /!<Break interrupt enable /
emilmont	77:869cf507173a	4669	#define TIM_DIER_UDE ((uint16_t)0x0100) /!<Update DMA request enable /
emilmont	77:869cf507173a	4670	#define TIM_DIER_CC1DE ((uint16_t)0x0200) /!<Capture/Compare 1 DMA request enable /
emilmont	77:869cf507173a	4671	#define TIM_DIER_CC2DE ((uint16_t)0x0400) /!<Capture/Compare 2 DMA request enable /
emilmont	77:869cf507173a	4672	#define TIM_DIER_CC3DE ((uint16_t)0x0800) /!<Capture/Compare 3 DMA request enable /
emilmont	77:869cf507173a	4673	#define TIM_DIER_CC4DE ((uint16_t)0x1000) /!<Capture/Compare 4 DMA request enable /
emilmont	77:869cf507173a	4674	#define TIM_DIER_COMDE ((uint16_t)0x2000) /!<COM DMA request enable /
emilmont	77:869cf507173a	4675	#define TIM_DIER_TDE ((uint16_t)0x4000) /!<Trigger DMA request enable /
emilmont	77:869cf507173a	4676
emilmont	77:869cf507173a	4677	/****************** Bit definition for TIM_SR register ******************/
emilmont	77:869cf507173a	4678	#define TIM_SR_UIF ((uint16_t)0x0001) /!<Update interrupt Flag /
emilmont	77:869cf507173a	4679	#define TIM_SR_CC1IF ((uint16_t)0x0002) /!<Capture/Compare 1 interrupt Flag /
emilmont	77:869cf507173a	4680	#define TIM_SR_CC2IF ((uint16_t)0x0004) /!<Capture/Compare 2 interrupt Flag /
emilmont	77:869cf507173a	4681	#define TIM_SR_CC3IF ((uint16_t)0x0008) /!<Capture/Compare 3 interrupt Flag /
emilmont	77:869cf507173a	4682	#define TIM_SR_CC4IF ((uint16_t)0x0010) /!<Capture/Compare 4 interrupt Flag /
emilmont	77:869cf507173a	4683	#define TIM_SR_COMIF ((uint16_t)0x0020) /!<COM interrupt Flag /
emilmont	77:869cf507173a	4684	#define TIM_SR_TIF ((uint16_t)0x0040) /!<Trigger interrupt Flag /
emilmont	77:869cf507173a	4685	#define TIM_SR_BIF ((uint16_t)0x0080) /!<Break interrupt Flag /
emilmont	77:869cf507173a	4686	#define TIM_SR_CC1OF ((uint16_t)0x0200) /!<Capture/Compare 1 Overcapture Flag /
emilmont	77:869cf507173a	4687	#define TIM_SR_CC2OF ((uint16_t)0x0400) /!<Capture/Compare 2 Overcapture Flag /
emilmont	77:869cf507173a	4688	#define TIM_SR_CC3OF ((uint16_t)0x0800) /!<Capture/Compare 3 Overcapture Flag /
emilmont	77:869cf507173a	4689	#define TIM_SR_CC4OF ((uint16_t)0x1000) /!<Capture/Compare 4 Overcapture Flag /
emilmont	77:869cf507173a	4690
emilmont	77:869cf507173a	4691	/***************** Bit definition for TIM_EGR register ******************/
emilmont	77:869cf507173a	4692	#define TIM_EGR_UG ((uint8_t)0x01) /!<Update Generation /
emilmont	77:869cf507173a	4693	#define TIM_EGR_CC1G ((uint8_t)0x02) /!<Capture/Compare 1 Generation /
emilmont	77:869cf507173a	4694	#define TIM_EGR_CC2G ((uint8_t)0x04) /!<Capture/Compare 2 Generation /
emilmont	77:869cf507173a	4695	#define TIM_EGR_CC3G ((uint8_t)0x08) /!<Capture/Compare 3 Generation /
emilmont	77:869cf507173a	4696	#define TIM_EGR_CC4G ((uint8_t)0x10) /!<Capture/Compare 4 Generation /
emilmont	77:869cf507173a	4697	#define TIM_EGR_COMG ((uint8_t)0x20) /!<Capture/Compare Control Update Generation /
emilmont	77:869cf507173a	4698	#define TIM_EGR_TG ((uint8_t)0x40) /!<Trigger Generation /
emilmont	77:869cf507173a	4699	#define TIM_EGR_BG ((uint8_t)0x80) /!<Break Generation /
emilmont	77:869cf507173a	4700
emilmont	77:869cf507173a	4701	/**************** Bit definition for TIM_CCMR1 register *****************/
emilmont	77:869cf507173a	4702	#define TIM_CCMR1_CC1S ((uint16_t)0x0003) /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
emilmont	77:869cf507173a	4703	#define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /!<Bit 0 /
emilmont	77:869cf507173a	4704	#define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /!<Bit 1 /
emilmont	77:869cf507173a	4705
emilmont	77:869cf507173a	4706	#define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /!<Output Compare 1 Fast enable /
emilmont	77:869cf507173a	4707	#define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /!<Output Compare 1 Preload enable /
emilmont	77:869cf507173a	4708
emilmont	77:869cf507173a	4709	#define TIM_CCMR1_OC1M ((uint16_t)0x0070) /!<OC1M[2:0] bits (Output Compare 1 Mode) /
emilmont	77:869cf507173a	4710	#define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /!<Bit 0 /
emilmont	77:869cf507173a	4711	#define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /!<Bit 1 /
emilmont	77:869cf507173a	4712	#define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /!<Bit 2 /
emilmont	77:869cf507173a	4713
emilmont	77:869cf507173a	4714	#define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /!<Output Compare 1Clear Enable /
emilmont	77:869cf507173a	4715
emilmont	77:869cf507173a	4716	#define TIM_CCMR1_CC2S ((uint16_t)0x0300) /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
emilmont	77:869cf507173a	4717	#define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /!<Bit 0 /
emilmont	77:869cf507173a	4718	#define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /!<Bit 1 /
emilmont	77:869cf507173a	4719
emilmont	77:869cf507173a	4720	#define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /!<Output Compare 2 Fast enable /
emilmont	77:869cf507173a	4721	#define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /!<Output Compare 2 Preload enable /
emilmont	77:869cf507173a	4722
emilmont	77:869cf507173a	4723	#define TIM_CCMR1_OC2M ((uint16_t)0x7000) /!<OC2M[2:0] bits (Output Compare 2 Mode) /
emilmont	77:869cf507173a	4724	#define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /!<Bit 0 /
emilmont	77:869cf507173a	4725	#define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /!<Bit 1 /
emilmont	77:869cf507173a	4726	#define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /!<Bit 2 /
emilmont	77:869cf507173a	4727
emilmont	77:869cf507173a	4728	#define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /!<Output Compare 2 Clear Enable /
emilmont	77:869cf507173a	4729
emilmont	77:869cf507173a	4730	/----------------------------------------------------------------------------/
emilmont	77:869cf507173a	4731
emilmont	77:869cf507173a	4732	#define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
emilmont	77:869cf507173a	4733	#define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /!<Bit 0 /
emilmont	77:869cf507173a	4734	#define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /!<Bit 1 /
emilmont	77:869cf507173a	4735
emilmont	77:869cf507173a	4736	#define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /!<IC1F[3:0] bits (Input Capture 1 Filter) /
emilmont	77:869cf507173a	4737	#define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /!<Bit 0 /
emilmont	77:869cf507173a	4738	#define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /!<Bit 1 /
emilmont	77:869cf507173a	4739	#define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /!<Bit 2 /
emilmont	77:869cf507173a	4740	#define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /!<Bit 3 /
emilmont	77:869cf507173a	4741
emilmont	77:869cf507173a	4742	#define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
emilmont	77:869cf507173a	4743	#define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /!<Bit 0 /
emilmont	77:869cf507173a	4744	#define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /!<Bit 1 /
emilmont	77:869cf507173a	4745
emilmont	77:869cf507173a	4746	#define TIM_CCMR1_IC2F ((uint16_t)0xF000) /!<IC2F[3:0] bits (Input Capture 2 Filter) /
emilmont	77:869cf507173a	4747	#define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /!<Bit 0 /
emilmont	77:869cf507173a	4748	#define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /!<Bit 1 /
emilmont	77:869cf507173a	4749	#define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /!<Bit 2 /
emilmont	77:869cf507173a	4750	#define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /!<Bit 3 /
emilmont	77:869cf507173a	4751
emilmont	77:869cf507173a	4752	/**************** Bit definition for TIM_CCMR2 register *****************/
emilmont	77:869cf507173a	4753	#define TIM_CCMR2_CC3S ((uint16_t)0x0003) /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
emilmont	77:869cf507173a	4754	#define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /!<Bit 0 /
emilmont	77:869cf507173a	4755	#define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /!<Bit 1 /
emilmont	77:869cf507173a	4756
emilmont	77:869cf507173a	4757	#define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /!<Output Compare 3 Fast enable /
emilmont	77:869cf507173a	4758	#define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /!<Output Compare 3 Preload enable /
emilmont	77:869cf507173a	4759
emilmont	77:869cf507173a	4760	#define TIM_CCMR2_OC3M ((uint16_t)0x0070) /!<OC3M[2:0] bits (Output Compare 3 Mode) /
emilmont	77:869cf507173a	4761	#define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /!<Bit 0 /
emilmont	77:869cf507173a	4762	#define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /!<Bit 1 /
emilmont	77:869cf507173a	4763	#define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /!<Bit 2 /
emilmont	77:869cf507173a	4764
emilmont	77:869cf507173a	4765	#define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /!<Output Compare 3 Clear Enable /
emilmont	77:869cf507173a	4766
emilmont	77:869cf507173a	4767	#define TIM_CCMR2_CC4S ((uint16_t)0x0300) /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
emilmont	77:869cf507173a	4768	#define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /!<Bit 0 /
emilmont	77:869cf507173a	4769	#define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /!<Bit 1 /
emilmont	77:869cf507173a	4770
emilmont	77:869cf507173a	4771	#define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /!<Output Compare 4 Fast enable /
emilmont	77:869cf507173a	4772	#define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /!<Output Compare 4 Preload enable /
emilmont	77:869cf507173a	4773
emilmont	77:869cf507173a	4774	#define TIM_CCMR2_OC4M ((uint16_t)0x7000) /!<OC4M[2:0] bits (Output Compare 4 Mode) /
emilmont	77:869cf507173a	4775	#define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /!<Bit 0 /
emilmont	77:869cf507173a	4776	#define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /!<Bit 1 /
emilmont	77:869cf507173a	4777	#define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /!<Bit 2 /
emilmont	77:869cf507173a	4778
emilmont	77:869cf507173a	4779	#define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /!<Output Compare 4 Clear Enable /
emilmont	77:869cf507173a	4780
emilmont	77:869cf507173a	4781	/----------------------------------------------------------------------------/
emilmont	77:869cf507173a	4782
emilmont	77:869cf507173a	4783	#define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
emilmont	77:869cf507173a	4784	#define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /!<Bit 0 /
emilmont	77:869cf507173a	4785	#define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /!<Bit 1 /
emilmont	77:869cf507173a	4786
emilmont	77:869cf507173a	4787	#define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /!<IC3F[3:0] bits (Input Capture 3 Filter) /
emilmont	77:869cf507173a	4788	#define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /!<Bit 0 /
emilmont	77:869cf507173a	4789	#define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /!<Bit 1 /
emilmont	77:869cf507173a	4790	#define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /!<Bit 2 /
emilmont	77:869cf507173a	4791	#define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /!<Bit 3 /
emilmont	77:869cf507173a	4792
emilmont	77:869cf507173a	4793	#define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
emilmont	77:869cf507173a	4794	#define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /!<Bit 0 /
emilmont	77:869cf507173a	4795	#define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /!<Bit 1 /
emilmont	77:869cf507173a	4796
emilmont	77:869cf507173a	4797	#define TIM_CCMR2_IC4F ((uint16_t)0xF000) /!<IC4F[3:0] bits (Input Capture 4 Filter) /
emilmont	77:869cf507173a	4798	#define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /!<Bit 0 /
emilmont	77:869cf507173a	4799	#define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /!<Bit 1 /
emilmont	77:869cf507173a	4800	#define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /!<Bit 2 /
emilmont	77:869cf507173a	4801	#define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /!<Bit 3 /
emilmont	77:869cf507173a	4802
emilmont	77:869cf507173a	4803	/***************** Bit definition for TIM_CCER register *****************/
emilmont	77:869cf507173a	4804	#define TIM_CCER_CC1E ((uint16_t)0x0001) /!<Capture/Compare 1 output enable /
emilmont	77:869cf507173a	4805	#define TIM_CCER_CC1P ((uint16_t)0x0002) /!<Capture/Compare 1 output Polarity /
emilmont	77:869cf507173a	4806	#define TIM_CCER_CC1NE ((uint16_t)0x0004) /!<Capture/Compare 1 Complementary output enable /
emilmont	77:869cf507173a	4807	#define TIM_CCER_CC1NP ((uint16_t)0x0008) /!<Capture/Compare 1 Complementary output Polarity /
emilmont	77:869cf507173a	4808	#define TIM_CCER_CC2E ((uint16_t)0x0010) /!<Capture/Compare 2 output enable /
emilmont	77:869cf507173a	4809	#define TIM_CCER_CC2P ((uint16_t)0x0020) /!<Capture/Compare 2 output Polarity /
emilmont	77:869cf507173a	4810	#define TIM_CCER_CC2NE ((uint16_t)0x0040) /!<Capture/Compare 2 Complementary output enable /
emilmont	77:869cf507173a	4811	#define TIM_CCER_CC2NP ((uint16_t)0x0080) /!<Capture/Compare 2 Complementary output Polarity /
emilmont	77:869cf507173a	4812	#define TIM_CCER_CC3E ((uint16_t)0x0100) /!<Capture/Compare 3 output enable /
emilmont	77:869cf507173a	4813	#define TIM_CCER_CC3P ((uint16_t)0x0200) /!<Capture/Compare 3 output Polarity /
emilmont	77:869cf507173a	4814	#define TIM_CCER_CC3NE ((uint16_t)0x0400) /!<Capture/Compare 3 Complementary output enable /
emilmont	77:869cf507173a	4815	#define TIM_CCER_CC3NP ((uint16_t)0x0800) /!<Capture/Compare 3 Complementary output Polarity /
emilmont	77:869cf507173a	4816	#define TIM_CCER_CC4E ((uint16_t)0x1000) /!<Capture/Compare 4 output enable /
emilmont	77:869cf507173a	4817	#define TIM_CCER_CC4P ((uint16_t)0x2000) /!<Capture/Compare 4 output Polarity /
emilmont	77:869cf507173a	4818	#define TIM_CCER_CC4NP ((uint16_t)0x8000) /!<Capture/Compare 4 Complementary output Polarity /
emilmont	77:869cf507173a	4819
emilmont	77:869cf507173a	4820	/***************** Bit definition for TIM_CNT register ******************/
emilmont	77:869cf507173a	4821	#define TIM_CNT_CNT ((uint16_t)0xFFFF) /!<Counter Value /
emilmont	77:869cf507173a	4822
emilmont	77:869cf507173a	4823	/***************** Bit definition for TIM_PSC register ******************/
emilmont	77:869cf507173a	4824	#define TIM_PSC_PSC ((uint16_t)0xFFFF) /!<Prescaler Value /
emilmont	77:869cf507173a	4825
emilmont	77:869cf507173a	4826	/***************** Bit definition for TIM_ARR register ******************/
emilmont	77:869cf507173a	4827	#define TIM_ARR_ARR ((uint16_t)0xFFFF) /!<actual auto-reload Value /
emilmont	77:869cf507173a	4828
emilmont	77:869cf507173a	4829	/***************** Bit definition for TIM_RCR register ******************/
emilmont	77:869cf507173a	4830	#define TIM_RCR_REP ((uint8_t)0xFF) /!<Repetition Counter Value /
emilmont	77:869cf507173a	4831
emilmont	77:869cf507173a	4832	/***************** Bit definition for TIM_CCR1 register *****************/
emilmont	77:869cf507173a	4833	#define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /!<Capture/Compare 1 Value /
emilmont	77:869cf507173a	4834
emilmont	77:869cf507173a	4835	/***************** Bit definition for TIM_CCR2 register *****************/
emilmont	77:869cf507173a	4836	#define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /!<Capture/Compare 2 Value /
emilmont	77:869cf507173a	4837
emilmont	77:869cf507173a	4838	/***************** Bit definition for TIM_CCR3 register *****************/
emilmont	77:869cf507173a	4839	#define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /!<Capture/Compare 3 Value /
emilmont	77:869cf507173a	4840
emilmont	77:869cf507173a	4841	/***************** Bit definition for TIM_CCR4 register *****************/
emilmont	77:869cf507173a	4842	#define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /!<Capture/Compare 4 Value /
emilmont	77:869cf507173a	4843
emilmont	77:869cf507173a	4844	/***************** Bit definition for TIM_BDTR register *****************/
emilmont	77:869cf507173a	4845	#define TIM_BDTR_DTG ((uint16_t)0x00FF) /!<DTG[0:7] bits (Dead-Time Generator set-up) /
emilmont	77:869cf507173a	4846	#define TIM_BDTR_DTG_0 ((uint16_t)0x0001) /!<Bit 0 /
emilmont	77:869cf507173a	4847	#define TIM_BDTR_DTG_1 ((uint16_t)0x0002) /!<Bit 1 /
emilmont	77:869cf507173a	4848	#define TIM_BDTR_DTG_2 ((uint16_t)0x0004) /!<Bit 2 /
emilmont	77:869cf507173a	4849	#define TIM_BDTR_DTG_3 ((uint16_t)0x0008) /!<Bit 3 /
emilmont	77:869cf507173a	4850	#define TIM_BDTR_DTG_4 ((uint16_t)0x0010) /!<Bit 4 /
emilmont	77:869cf507173a	4851	#define TIM_BDTR_DTG_5 ((uint16_t)0x0020) /!<Bit 5 /
emilmont	77:869cf507173a	4852	#define TIM_BDTR_DTG_6 ((uint16_t)0x0040) /!<Bit 6 /
emilmont	77:869cf507173a	4853	#define TIM_BDTR_DTG_7 ((uint16_t)0x0080) /!<Bit 7 /
emilmont	77:869cf507173a	4854
emilmont	77:869cf507173a	4855	#define TIM_BDTR_LOCK ((uint16_t)0x0300) /!<LOCK[1:0] bits (Lock Configuration) /
emilmont	77:869cf507173a	4856	#define TIM_BDTR_LOCK_0 ((uint16_t)0x0100) /!<Bit 0 /
emilmont	77:869cf507173a	4857	#define TIM_BDTR_LOCK_1 ((uint16_t)0x0200) /!<Bit 1 /
emilmont	77:869cf507173a	4858
emilmont	77:869cf507173a	4859	#define TIM_BDTR_OSSI ((uint16_t)0x0400) /!<Off-State Selection for Idle mode /
emilmont	77:869cf507173a	4860	#define TIM_BDTR_OSSR ((uint16_t)0x0800) /!<Off-State Selection for Run mode /
emilmont	77:869cf507173a	4861	#define TIM_BDTR_BKE ((uint16_t)0x1000) /!<Break enable /
emilmont	77:869cf507173a	4862	#define TIM_BDTR_BKP ((uint16_t)0x2000) /!<Break Polarity /
emilmont	77:869cf507173a	4863	#define TIM_BDTR_AOE ((uint16_t)0x4000) /!<Automatic Output enable /
emilmont	77:869cf507173a	4864	#define TIM_BDTR_MOE ((uint16_t)0x8000) /!<Main Output enable /
emilmont	77:869cf507173a	4865
emilmont	77:869cf507173a	4866	/***************** Bit definition for TIM_DCR register ******************/
emilmont	77:869cf507173a	4867	#define TIM_DCR_DBA ((uint16_t)0x001F) /!<DBA[4:0] bits (DMA Base Address) /
emilmont	77:869cf507173a	4868	#define TIM_DCR_DBA_0 ((uint16_t)0x0001) /!<Bit 0 /
emilmont	77:869cf507173a	4869	#define TIM_DCR_DBA_1 ((uint16_t)0x0002) /!<Bit 1 /
emilmont	77:869cf507173a	4870	#define TIM_DCR_DBA_2 ((uint16_t)0x0004) /!<Bit 2 /
emilmont	77:869cf507173a	4871	#define TIM_DCR_DBA_3 ((uint16_t)0x0008) /!<Bit 3 /
emilmont	77:869cf507173a	4872	#define TIM_DCR_DBA_4 ((uint16_t)0x0010) /!<Bit 4 /
emilmont	77:869cf507173a	4873
emilmont	77:869cf507173a	4874	#define TIM_DCR_DBL ((uint16_t)0x1F00) /!<DBL[4:0] bits (DMA Burst Length) /
emilmont	77:869cf507173a	4875	#define TIM_DCR_DBL_0 ((uint16_t)0x0100) /!<Bit 0 /
emilmont	77:869cf507173a	4876	#define TIM_DCR_DBL_1 ((uint16_t)0x0200) /!<Bit 1 /
emilmont	77:869cf507173a	4877	#define TIM_DCR_DBL_2 ((uint16_t)0x0400) /!<Bit 2 /
emilmont	77:869cf507173a	4878	#define TIM_DCR_DBL_3 ((uint16_t)0x0800) /!<Bit 3 /
emilmont	77:869cf507173a	4879	#define TIM_DCR_DBL_4 ((uint16_t)0x1000) /!<Bit 4 /
emilmont	77:869cf507173a	4880
emilmont	77:869cf507173a	4881	/***************** Bit definition for TIM_DMAR register *****************/
emilmont	77:869cf507173a	4882	#define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /!<DMA register for burst accesses /
emilmont	77:869cf507173a	4883
emilmont	77:869cf507173a	4884	/***************** Bit definition for TIM_OR register *******************/
emilmont	77:869cf507173a	4885	#define TIM14_OR_TI1_RMP ((uint16_t)0x0003) /!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) /
emilmont	77:869cf507173a	4886	#define TIM14_OR_TI1_RMP_0 ((uint16_t)0x0001) /!<Bit 0 /
emilmont	77:869cf507173a	4887	#define TIM14_OR_TI1_RMP_1 ((uint16_t)0x0002) /!<Bit 1 /
emilmont	77:869cf507173a	4888
emilmont	77:869cf507173a	4889
emilmont	77:869cf507173a	4890	/******************************************************************************/
emilmont	77:869cf507173a	4891	/* */
emilmont	77:869cf507173a	4892	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
emilmont	77:869cf507173a	4893	/* */
emilmont	77:869cf507173a	4894	/******************************************************************************/
emilmont	77:869cf507173a	4895	/**************** Bit definition for USART_CR1 register *****************/
emilmont	77:869cf507173a	4896	#define USART_CR1_UE ((uint32_t)0x00000001) /!< USART Enable /
emilmont	77:869cf507173a	4897	#define USART_CR1_UESM ((uint32_t)0x00000002) /!< USART Enable in STOP Mode /
emilmont	77:869cf507173a	4898	#define USART_CR1_RE ((uint32_t)0x00000004) /!< Receiver Enable /
emilmont	77:869cf507173a	4899	#define USART_CR1_TE ((uint32_t)0x00000008) /!< Transmitter Enable /
emilmont	77:869cf507173a	4900	#define USART_CR1_IDLEIE ((uint32_t)0x00000010) /!< IDLE Interrupt Enable /
emilmont	77:869cf507173a	4901	#define USART_CR1_RXNEIE ((uint32_t)0x00000020) /!< RXNE Interrupt Enable /
emilmont	77:869cf507173a	4902	#define USART_CR1_TCIE ((uint32_t)0x00000040) /!< Transmission Complete Interrupt Enable /
emilmont	77:869cf507173a	4903	#define USART_CR1_TXEIE ((uint32_t)0x00000080) /!< TXE Interrupt Enable /
emilmont	77:869cf507173a	4904	#define USART_CR1_PEIE ((uint32_t)0x00000100) /!< PE Interrupt Enable /
emilmont	77:869cf507173a	4905	#define USART_CR1_PS ((uint32_t)0x00000200) /!< Parity Selection /
emilmont	77:869cf507173a	4906	#define USART_CR1_PCE ((uint32_t)0x00000400) /!< Parity Control Enable /
emilmont	77:869cf507173a	4907	#define USART_CR1_WAKE ((uint32_t)0x00000800) /!< Receiver Wakeup method /
emilmont	77:869cf507173a	4908	#define USART_CR1_M ((uint32_t)0x00001000) /!< Word length /
emilmont	77:869cf507173a	4909	#define USART_CR1_MME ((uint32_t)0x00002000) /!< Mute Mode Enable /
emilmont	77:869cf507173a	4910	#define USART_CR1_CMIE ((uint32_t)0x00004000) /!< Character match interrupt enable /
emilmont	77:869cf507173a	4911	#define USART_CR1_OVER8 ((uint32_t)0x00008000) /!< Oversampling by 8-bit or 16-bit mode /
emilmont	77:869cf507173a	4912	#define USART_CR1_DEDT ((uint32_t)0x001F0000) /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
emilmont	77:869cf507173a	4913	#define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /!< Bit 0 /
emilmont	77:869cf507173a	4914	#define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /!< Bit 1 /
emilmont	77:869cf507173a	4915	#define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /!< Bit 2 /
emilmont	77:869cf507173a	4916	#define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /!< Bit 3 /
emilmont	77:869cf507173a	4917	#define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /!< Bit 4 /
emilmont	77:869cf507173a	4918	#define USART_CR1_DEAT ((uint32_t)0x03E00000) /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
emilmont	77:869cf507173a	4919	#define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /!< Bit 0 /
emilmont	77:869cf507173a	4920	#define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /!< Bit 1 /
emilmont	77:869cf507173a	4921	#define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /!< Bit 2 /
emilmont	77:869cf507173a	4922	#define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /!< Bit 3 /
emilmont	77:869cf507173a	4923	#define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /!< Bit 4 /
emilmont	77:869cf507173a	4924	#define USART_CR1_RTOIE ((uint32_t)0x04000000) /!< Receive Time Out interrupt enable /
emilmont	77:869cf507173a	4925	#define USART_CR1_EOBIE ((uint32_t)0x08000000) /!< End of Block interrupt enable /
emilmont	77:869cf507173a	4926
emilmont	77:869cf507173a	4927	/**************** Bit definition for USART_CR2 register *****************/
emilmont	77:869cf507173a	4928	#define USART_CR2_ADDM7 ((uint32_t)0x00000010) /!< 7-bit or 4-bit Address Detection /
emilmont	77:869cf507173a	4929	#define USART_CR2_LBDL ((uint32_t)0x00000020) /!< LIN Break Detection Length /
emilmont	77:869cf507173a	4930	#define USART_CR2_LBDIE ((uint32_t)0x00000040) /!< LIN Break Detection Interrupt Enable /
emilmont	77:869cf507173a	4931	#define USART_CR2_LBCL ((uint32_t)0x00000100) /!< Last Bit Clock pulse /
emilmont	77:869cf507173a	4932	#define USART_CR2_CPHA ((uint32_t)0x00000200) /!< Clock Phase /
emilmont	77:869cf507173a	4933	#define USART_CR2_CPOL ((uint32_t)0x00000400) /!< Clock Polarity /
emilmont	77:869cf507173a	4934	#define USART_CR2_CLKEN ((uint32_t)0x00000800) /!< Clock Enable /
emilmont	77:869cf507173a	4935	#define USART_CR2_STOP ((uint32_t)0x00003000) /!< STOP[1:0] bits (STOP bits) /
emilmont	77:869cf507173a	4936	#define USART_CR2_STOP_0 ((uint32_t)0x00001000) /!< Bit 0 /
emilmont	77:869cf507173a	4937	#define USART_CR2_STOP_1 ((uint32_t)0x00002000) /!< Bit 1 /
emilmont	77:869cf507173a	4938	#define USART_CR2_LINEN ((uint32_t)0x00004000) /!< LIN mode enable /
emilmont	77:869cf507173a	4939	#define USART_CR2_SWAP ((uint32_t)0x00008000) /!< SWAP TX/RX pins /
emilmont	77:869cf507173a	4940	#define USART_CR2_RXINV ((uint32_t)0x00010000) /!< RX pin active level inversion /
emilmont	77:869cf507173a	4941	#define USART_CR2_TXINV ((uint32_t)0x00020000) /!< TX pin active level inversion /
emilmont	77:869cf507173a	4942	#define USART_CR2_DATAINV ((uint32_t)0x00040000) /!< Binary data inversion /
emilmont	77:869cf507173a	4943	#define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /!< Most Significant Bit First /
emilmont	77:869cf507173a	4944	#define USART_CR2_ABREN ((uint32_t)0x00100000) /!< Auto Baud-Rate Enable/
emilmont	77:869cf507173a	4945	#define USART_CR2_ABRMODE ((uint32_t)0x00600000) /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
emilmont	77:869cf507173a	4946	#define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /!< Bit 0 /
emilmont	77:869cf507173a	4947	#define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /!< Bit 1 /
emilmont	77:869cf507173a	4948	#define USART_CR2_RTOEN ((uint32_t)0x00800000) /!< Receiver Time-Out enable /
emilmont	77:869cf507173a	4949	#define USART_CR2_ADD ((uint32_t)0xFF000000) /!< Address of the USART node /
emilmont	77:869cf507173a	4950
emilmont	77:869cf507173a	4951	/**************** Bit definition for USART_CR3 register *****************/
emilmont	77:869cf507173a	4952	#define USART_CR3_EIE ((uint32_t)0x00000001) /!< Error Interrupt Enable /
emilmont	77:869cf507173a	4953	#define USART_CR3_IREN ((uint32_t)0x00000002) /!< IrDA mode Enable /
emilmont	77:869cf507173a	4954	#define USART_CR3_IRLP ((uint32_t)0x00000004) /!< IrDA Low-Power /
emilmont	77:869cf507173a	4955	#define USART_CR3_HDSEL ((uint32_t)0x00000008) /!< Half-Duplex Selection /
emilmont	77:869cf507173a	4956	#define USART_CR3_NACK ((uint32_t)0x00000010) /!< SmartCard NACK enable /
emilmont	77:869cf507173a	4957	#define USART_CR3_SCEN ((uint32_t)0x00000020) /!< SmartCard mode enable /
emilmont	77:869cf507173a	4958	#define USART_CR3_DMAR ((uint32_t)0x00000040) /!< DMA Enable Receiver /
emilmont	77:869cf507173a	4959	#define USART_CR3_DMAT ((uint32_t)0x00000080) /!< DMA Enable Transmitter /
emilmont	77:869cf507173a	4960	#define USART_CR3_RTSE ((uint32_t)0x00000100) /!< RTS Enable /
emilmont	77:869cf507173a	4961	#define USART_CR3_CTSE ((uint32_t)0x00000200) /!< CTS Enable /
emilmont	77:869cf507173a	4962	#define USART_CR3_CTSIE ((uint32_t)0x00000400) /!< CTS Interrupt Enable /
emilmont	77:869cf507173a	4963	#define USART_CR3_ONEBIT ((uint32_t)0x00000800) /!< One sample bit method enable /
emilmont	77:869cf507173a	4964	#define USART_CR3_OVRDIS ((uint32_t)0x00001000) /!< Overrun Disable /
emilmont	77:869cf507173a	4965	#define USART_CR3_DDRE ((uint32_t)0x00002000) /!< DMA Disable on Reception Error /
emilmont	77:869cf507173a	4966	#define USART_CR3_DEM ((uint32_t)0x00004000) /!< Driver Enable Mode /
emilmont	77:869cf507173a	4967	#define USART_CR3_DEP ((uint32_t)0x00008000) /!< Driver Enable Polarity Selection /
emilmont	77:869cf507173a	4968	#define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
emilmont	77:869cf507173a	4969	#define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /!< Bit 0 /
emilmont	77:869cf507173a	4970	#define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /!< Bit 1 /
emilmont	77:869cf507173a	4971	#define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /!< Bit 2 /
emilmont	77:869cf507173a	4972	#define USART_CR3_WUS ((uint32_t)0x00300000) /!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) /
emilmont	77:869cf507173a	4973	#define USART_CR3_WUS_0 ((uint32_t)0x00100000) /!< Bit 0 /
emilmont	77:869cf507173a	4974	#define USART_CR3_WUS_1 ((uint32_t)0x00200000) /!< Bit 1 /
emilmont	77:869cf507173a	4975	#define USART_CR3_WUFIE ((uint32_t)0x00400000) /!< Wake Up Interrupt Enable /
emilmont	77:869cf507173a	4976
emilmont	77:869cf507173a	4977	/**************** Bit definition for USART_BRR register *****************/
emilmont	77:869cf507173a	4978	#define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /!< Fraction of USARTDIV /
emilmont	77:869cf507173a	4979	#define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /!< Mantissa of USARTDIV /
emilmont	77:869cf507173a	4980
emilmont	77:869cf507173a	4981	/**************** Bit definition for USART_GTPR register ****************/
emilmont	77:869cf507173a	4982	#define USART_GTPR_PSC ((uint16_t)0x00FF) /!< PSC[7:0] bits (Prescaler value) /
emilmont	77:869cf507173a	4983	#define USART_GTPR_GT ((uint16_t)0xFF00) /!< GT[7:0] bits (Guard time value) /
emilmont	77:869cf507173a	4984
emilmont	77:869cf507173a	4985
emilmont	77:869cf507173a	4986	/***************** Bit definition for USART_RTOR register ***************/
emilmont	77:869cf507173a	4987	#define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /!< Receiver Time Out Value /
emilmont	77:869cf507173a	4988	#define USART_RTOR_BLEN ((uint32_t)0xFF000000) /!< Block Length /
emilmont	77:869cf507173a	4989
emilmont	77:869cf507173a	4990	/***************** Bit definition for USART_RQR register ****************/
emilmont	77:869cf507173a	4991	#define USART_RQR_ABRRQ ((uint16_t)0x0001) /!< Auto-Baud Rate Request /
emilmont	77:869cf507173a	4992	#define USART_RQR_SBKRQ ((uint16_t)0x0002) /!< Send Break Request /
emilmont	77:869cf507173a	4993	#define USART_RQR_MMRQ ((uint16_t)0x0004) /!< Mute Mode Request /
emilmont	77:869cf507173a	4994	#define USART_RQR_RXFRQ ((uint16_t)0x0008) /!< Receive Data flush Request /
emilmont	77:869cf507173a	4995	#define USART_RQR_TXFRQ ((uint16_t)0x0010) /!< Transmit data flush Request /
emilmont	77:869cf507173a	4996
emilmont	77:869cf507173a	4997	/***************** Bit definition for USART_ISR register ****************/
emilmont	77:869cf507173a	4998	#define USART_ISR_PE ((uint32_t)0x00000001) /!< Parity Error /
emilmont	77:869cf507173a	4999	#define USART_ISR_FE ((uint32_t)0x00000002) /!< Framing Error /
emilmont	77:869cf507173a	5000	#define USART_ISR_NE ((uint32_t)0x00000004) /!< Noise detected Flag /
emilmont	77:869cf507173a	5001	#define USART_ISR_ORE ((uint32_t)0x00000008) /!< OverRun Error /
emilmont	77:869cf507173a	5002	#define USART_ISR_IDLE ((uint32_t)0x00000010) /!< IDLE line detected /
emilmont	77:869cf507173a	5003	#define USART_ISR_RXNE ((uint32_t)0x00000020) /!< Read Data Register Not Empty /
emilmont	77:869cf507173a	5004	#define USART_ISR_TC ((uint32_t)0x00000040) /!< Transmission Complete /
emilmont	77:869cf507173a	5005	#define USART_ISR_TXE ((uint32_t)0x00000080) /!< Transmit Data Register Empty /
emilmont	77:869cf507173a	5006	#define USART_ISR_LBD ((uint32_t)0x00000100) /!< LIN Break Detection Flag /
emilmont	77:869cf507173a	5007	#define USART_ISR_CTSIF ((uint32_t)0x00000200) /!< CTS interrupt flag /
emilmont	77:869cf507173a	5008	#define USART_ISR_CTS ((uint32_t)0x00000400) /!< CTS flag /
emilmont	77:869cf507173a	5009	#define USART_ISR_RTOF ((uint32_t)0x00000800) /!< Receiver Time Out /
emilmont	77:869cf507173a	5010	#define USART_ISR_EOBF ((uint32_t)0x00001000) /!< End Of Block Flag /
emilmont	77:869cf507173a	5011	#define USART_ISR_ABRE ((uint32_t)0x00004000) /!< Auto-Baud Rate Error /
emilmont	77:869cf507173a	5012	#define USART_ISR_ABRF ((uint32_t)0x00008000) /!< Auto-Baud Rate Flag /
emilmont	77:869cf507173a	5013	#define USART_ISR_BUSY ((uint32_t)0x00010000) /!< Busy Flag /
emilmont	77:869cf507173a	5014	#define USART_ISR_CMF ((uint32_t)0x00020000) /!< Character Match Flag /
emilmont	77:869cf507173a	5015	#define USART_ISR_SBKF ((uint32_t)0x00040000) /!< Send Break Flag /
emilmont	77:869cf507173a	5016	#define USART_ISR_RWU ((uint32_t)0x00080000) /!< Receive Wake Up from mute mode Flag /
emilmont	77:869cf507173a	5017	#define USART_ISR_WUF ((uint32_t)0x00100000) /!< Wake Up from stop mode Flag /
emilmont	77:869cf507173a	5018	#define USART_ISR_TEACK ((uint32_t)0x00200000) /!< Transmit Enable Acknowledge Flag /
emilmont	77:869cf507173a	5019	#define USART_ISR_REACK ((uint32_t)0x00400000) /!< Receive Enable Acknowledge Flag /
emilmont	77:869cf507173a	5020
emilmont	77:869cf507173a	5021	/***************** Bit definition for USART_ICR register ****************/
emilmont	77:869cf507173a	5022	#define USART_ICR_PECF ((uint32_t)0x00000001) /!< Parity Error Clear Flag /
emilmont	77:869cf507173a	5023	#define USART_ICR_FECF ((uint32_t)0x00000002) /!< Framing Error Clear Flag /
emilmont	77:869cf507173a	5024	#define USART_ICR_NCF ((uint32_t)0x00000004) /!< Noise detected Clear Flag /
emilmont	77:869cf507173a	5025	#define USART_ICR_ORECF ((uint32_t)0x00000008) /!< OverRun Error Clear Flag /
emilmont	77:869cf507173a	5026	#define USART_ICR_IDLECF ((uint32_t)0x00000010) /!< IDLE line detected Clear Flag /
emilmont	77:869cf507173a	5027	#define USART_ICR_TCCF ((uint32_t)0x00000040) /!< Transmission Complete Clear Flag /
emilmont	77:869cf507173a	5028	#define USART_ICR_LBDCF ((uint32_t)0x00000100) /!< LIN Break Detection Clear Flag /
emilmont	77:869cf507173a	5029	#define USART_ICR_CTSCF ((uint32_t)0x00000200) /!< CTS Interrupt Clear Flag /
emilmont	77:869cf507173a	5030	#define USART_ICR_RTOCF ((uint32_t)0x00000800) /!< Receiver Time Out Clear Flag /
emilmont	77:869cf507173a	5031	#define USART_ICR_EOBCF ((uint32_t)0x00001000) /!< End Of Block Clear Flag /
emilmont	77:869cf507173a	5032	#define USART_ICR_CMCF ((uint32_t)0x00020000) /!< Character Match Clear Flag /
emilmont	77:869cf507173a	5033	#define USART_ICR_WUCF ((uint32_t)0x00100000) /!< Wake Up from stop mode Clear Flag /
emilmont	77:869cf507173a	5034
emilmont	77:869cf507173a	5035	/***************** Bit definition for USART_RDR register ****************/
emilmont	77:869cf507173a	5036	#define USART_RDR_RDR ((uint16_t)0x01FF) /!< RDR[8:0] bits (Receive Data value) /
emilmont	77:869cf507173a	5037
emilmont	77:869cf507173a	5038	/***************** Bit definition for USART_TDR register ****************/
emilmont	77:869cf507173a	5039	#define USART_TDR_TDR ((uint16_t)0x01FF) /!< TDR[8:0] bits (Transmit Data value) /
emilmont	77:869cf507173a	5040
emilmont	77:869cf507173a	5041	/******************************************************************************/
emilmont	77:869cf507173a	5042	/* */
emilmont	77:869cf507173a	5043	/* Window WATCHDOG (WWDG) */
emilmont	77:869cf507173a	5044	/* */
emilmont	77:869cf507173a	5045	/******************************************************************************/
emilmont	77:869cf507173a	5046
emilmont	77:869cf507173a	5047	/***************** Bit definition for WWDG_CR register ******************/
emilmont	77:869cf507173a	5048	#define WWDG_CR_T ((uint8_t)0x7F) /!< T[6:0] bits (7-Bit counter (MSB to LSB)) /
emilmont	77:869cf507173a	5049	#define WWDG_CR_T0 ((uint8_t)0x01) /!< Bit 0 /
emilmont	77:869cf507173a	5050	#define WWDG_CR_T1 ((uint8_t)0x02) /!< Bit 1 /
emilmont	77:869cf507173a	5051	#define WWDG_CR_T2 ((uint8_t)0x04) /!< Bit 2 /
emilmont	77:869cf507173a	5052	#define WWDG_CR_T3 ((uint8_t)0x08) /!< Bit 3 /
emilmont	77:869cf507173a	5053	#define WWDG_CR_T4 ((uint8_t)0x10) /!< Bit 4 /
emilmont	77:869cf507173a	5054	#define WWDG_CR_T5 ((uint8_t)0x20) /!< Bit 5 /
emilmont	77:869cf507173a	5055	#define WWDG_CR_T6 ((uint8_t)0x40) /!< Bit 6 /
emilmont	77:869cf507173a	5056
emilmont	77:869cf507173a	5057	#define WWDG_CR_WDGA ((uint8_t)0x80) /!< Activation bit /
emilmont	77:869cf507173a	5058
emilmont	77:869cf507173a	5059	/***************** Bit definition for WWDG_CFR register *****************/
emilmont	77:869cf507173a	5060	#define WWDG_CFR_W ((uint16_t)0x007F) /!< W[6:0] bits (7-bit window value) /
emilmont	77:869cf507173a	5061	#define WWDG_CFR_W0 ((uint16_t)0x0001) /!< Bit 0 /
emilmont	77:869cf507173a	5062	#define WWDG_CFR_W1 ((uint16_t)0x0002) /!< Bit 1 /
emilmont	77:869cf507173a	5063	#define WWDG_CFR_W2 ((uint16_t)0x0004) /!< Bit 2 /
emilmont	77:869cf507173a	5064	#define WWDG_CFR_W3 ((uint16_t)0x0008) /!< Bit 3 /
emilmont	77:869cf507173a	5065	#define WWDG_CFR_W4 ((uint16_t)0x0010) /!< Bit 4 /
emilmont	77:869cf507173a	5066	#define WWDG_CFR_W5 ((uint16_t)0x0020) /!< Bit 5 /
emilmont	77:869cf507173a	5067	#define WWDG_CFR_W6 ((uint16_t)0x0040) /!< Bit 6 /
emilmont	77:869cf507173a	5068
emilmont	77:869cf507173a	5069	#define WWDG_CFR_WDGTB ((uint16_t)0x0180) /!< WDGTB[1:0] bits (Timer Base) /
emilmont	77:869cf507173a	5070	#define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /!< Bit 0 /
emilmont	77:869cf507173a	5071	#define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /!< Bit 1 /
emilmont	77:869cf507173a	5072
emilmont	77:869cf507173a	5073	#define WWDG_CFR_EWI ((uint16_t)0x0200) /!< Early Wakeup Interrupt /
emilmont	77:869cf507173a	5074
emilmont	77:869cf507173a	5075	/***************** Bit definition for WWDG_SR register ******************/
emilmont	77:869cf507173a	5076	#define WWDG_SR_EWIF ((uint8_t)0x01) /!< Early Wakeup Interrupt Flag /
emilmont	77:869cf507173a	5077
emilmont	77:869cf507173a	5078	/**
emilmont	77:869cf507173a	5079	* @}
emilmont	77:869cf507173a	5080	*/
emilmont	77:869cf507173a	5081
emilmont	77:869cf507173a	5082	/**
emilmont	77:869cf507173a	5083	* @}
emilmont	77:869cf507173a	5084	*/
emilmont	77:869cf507173a	5085
emilmont	77:869cf507173a	5086	#ifdef USE_STDPERIPH_DRIVER
emilmont	77:869cf507173a	5087	#include "stm32f0xx_conf.h"
emilmont	77:869cf507173a	5088	#endif
emilmont	77:869cf507173a	5089
emilmont	77:869cf507173a	5090	/** @addtogroup Exported_macro
emilmont	77:869cf507173a	5091	* @{
emilmont	77:869cf507173a	5092	*/
emilmont	77:869cf507173a	5093	/**
emilmont	77:869cf507173a	5094	* @}
emilmont	77:869cf507173a	5095	*/
emilmont	77:869cf507173a	5096
emilmont	77:869cf507173a	5097	#ifdef __cplusplus
emilmont	77:869cf507173a	5098	}
emilmont	77:869cf507173a	5099	#endif
emilmont	77:869cf507173a	5100
emilmont	77:869cf507173a	5101	#endif /* __STM32F0XX_H */
emilmont	77:869cf507173a	5102
emilmont	77:869cf507173a	5103	/**
emilmont	77:869cf507173a	5104	* @}
emilmont	77:869cf507173a	5105	*/
emilmont	77:869cf507173a	5106
emilmont	77:869cf507173a	5107	/**
emilmont	77:869cf507173a	5108	* @}
emilmont	77:869cf507173a	5109	*/
emilmont	77:869cf507173a	5110
emilmont	77:869cf507173a	5111	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
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TARGET_NUCLEO_F030R8/stm32f0xx.h@77:869cf507173a, 2014-02-14 (annotated)

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