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TARGET_NUCLEO_L152RE/stm32l1xx_hal_pwr.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:
filartrix
Date:
Wed Apr 08 14:12:53 2015 +0000
Revision:
97:4298809c7c9e
Parent:
90:cb3d968589d8 
First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32l1xx_hal_pwr.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.0.0
Kojto 90:cb3d968589d8 6 * @date 5-September-2014
Kojto 90:cb3d968589d8 7 * @brief Header file of PWR HAL module.
Kojto 90:cb3d968589d8 8 ******************************************************************************
Kojto 90:cb3d968589d8 9 * @attention
Kojto 90:cb3d968589d8 10 *
Kojto 90:cb3d968589d8 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 12 *
Kojto 90:cb3d968589d8 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 14 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 16 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 18 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 19 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 21 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 22 * without specific prior written permission.
Kojto 90:cb3d968589d8 23 *
Kojto 90:cb3d968589d8 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 34 *
Kojto 90:cb3d968589d8 35 ******************************************************************************
Kojto 90:cb3d968589d8 36 */
Kojto 90:cb3d968589d8 37
Kojto 90:cb3d968589d8 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 90:cb3d968589d8 39 #ifndef __STM32L1xx_HAL_PWR_H
Kojto 90:cb3d968589d8 40 #define __STM32L1xx_HAL_PWR_H
Kojto 90:cb3d968589d8 41
Kojto 90:cb3d968589d8 42 #ifdef __cplusplus
Kojto 90:cb3d968589d8 43 extern "C" {
Kojto 90:cb3d968589d8 44 #endif
Kojto 90:cb3d968589d8 45
Kojto 90:cb3d968589d8 46 /* Includes ------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 47 #include "stm32l1xx_hal_def.h"
Kojto 90:cb3d968589d8 48
Kojto 90:cb3d968589d8 49 /** @addtogroup STM32L1xx_HAL_Driver
Kojto 90:cb3d968589d8 50 * @{
Kojto 90:cb3d968589d8 51 */
Kojto 90:cb3d968589d8 52
Kojto 90:cb3d968589d8 53 /** @addtogroup PWR
Kojto 90:cb3d968589d8 54 * @{
Kojto 90:cb3d968589d8 55 */
Kojto 90:cb3d968589d8 56
Kojto 90:cb3d968589d8 57 /* Exported types ------------------------------------------------------------*/
Kojto 90:cb3d968589d8 58
Kojto 90:cb3d968589d8 59 /** @defgroup PWR_Exported_Types PWR Exported Types
Kojto 90:cb3d968589d8 60 * @{
Kojto 90:cb3d968589d8 61 */
Kojto 90:cb3d968589d8 62
Kojto 90:cb3d968589d8 63 /**
Kojto 90:cb3d968589d8 64 * @brief PWR PVD configuration structure definition
Kojto 90:cb3d968589d8 65 */
Kojto 90:cb3d968589d8 66 typedef struct
Kojto 90:cb3d968589d8 67 {
Kojto 90:cb3d968589d8 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
Kojto 90:cb3d968589d8 69 This parameter can be a value of @ref PWR_PVD_detection_level */
Kojto 90:cb3d968589d8 70
Kojto 90:cb3d968589d8 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
Kojto 90:cb3d968589d8 72 This parameter can be a value of @ref PWR_PVD_Mode */
Kojto 90:cb3d968589d8 73 }PWR_PVDTypeDef;
Kojto 90:cb3d968589d8 74
Kojto 90:cb3d968589d8 75 /**
Kojto 90:cb3d968589d8 76 * @}
Kojto 90:cb3d968589d8 77 */
Kojto 90:cb3d968589d8 78
Kojto 90:cb3d968589d8 79 /* Exported constants --------------------------------------------------------*/
Kojto 90:cb3d968589d8 80
Kojto 90:cb3d968589d8 81 /** @defgroup PWR_Exported_Constants PWR Exported Constants
Kojto 90:cb3d968589d8 82 * @{
Kojto 90:cb3d968589d8 83 */
Kojto 90:cb3d968589d8 84
Kojto 90:cb3d968589d8 85 /** @defgroup PWR_register_alias_address PWR Register alias address
Kojto 90:cb3d968589d8 86 * @{
Kojto 90:cb3d968589d8 87 */
Kojto 90:cb3d968589d8 88 /* ------------- PWR registers bit address in the alias region ---------------*/
Kojto 90:cb3d968589d8 89 #define PWR_OFFSET (PWR_BASE - PERIPH_BASE)
Kojto 90:cb3d968589d8 90 #define PWR_CR_OFFSET 0x00
Kojto 90:cb3d968589d8 91 #define PWR_CSR_OFFSET 0x04
Kojto 90:cb3d968589d8 92 #define PWR_CR_OFFSET_BB (PWR_OFFSET + PWR_CR_OFFSET)
Kojto 90:cb3d968589d8 93 #define PWR_CSR_OFFSET_BB (PWR_OFFSET + PWR_CSR_OFFSET)
Kojto 90:cb3d968589d8 94 /**
Kojto 90:cb3d968589d8 95 * @}
Kojto 90:cb3d968589d8 96 */
Kojto 90:cb3d968589d8 97
Kojto 90:cb3d968589d8 98 /** @defgroup PWR_CR_register_alias PWR CR Register alias address
Kojto 90:cb3d968589d8 99 * @{
Kojto 90:cb3d968589d8 100 */
Kojto 90:cb3d968589d8 101 /* --- CR Register ---*/
Kojto 90:cb3d968589d8 102 /* Alias word address of LPSDSR bit */
Kojto 90:cb3d968589d8 103 #define LPSDSR_BIT_NUMBER POSITION_VAL(PWR_CR_LPSDSR)
Kojto 90:cb3d968589d8 104 #define CR_LPSDSR_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPSDSR_BIT_NUMBER * 4)))
Kojto 90:cb3d968589d8 105
Kojto 90:cb3d968589d8 106 /* Alias word address of DBP bit */
Kojto 90:cb3d968589d8 107 #define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP)
Kojto 90:cb3d968589d8 108 #define CR_DBP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (DBP_BIT_NUMBER * 4)))
Kojto 90:cb3d968589d8 109
Kojto 90:cb3d968589d8 110 /* Alias word address of LPRUN bit */
Kojto 90:cb3d968589d8 111 #define LPRUN_BIT_NUMBER POSITION_VAL(PWR_CR_LPRUN)
Kojto 90:cb3d968589d8 112 #define CR_LPRUN_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (LPRUN_BIT_NUMBER * 4)))
Kojto 90:cb3d968589d8 113
Kojto 90:cb3d968589d8 114 /* Alias word address of PVDE bit */
Kojto 90:cb3d968589d8 115 #define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE)
Kojto 90:cb3d968589d8 116 #define CR_PVDE_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (PVDE_BIT_NUMBER * 4)))
Kojto 90:cb3d968589d8 117
Kojto 90:cb3d968589d8 118 /* Alias word address of FWU bit */
Kojto 90:cb3d968589d8 119 #define FWU_BIT_NUMBER POSITION_VAL(PWR_CR_FWU)
Kojto 90:cb3d968589d8 120 #define CR_FWU_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (FWU_BIT_NUMBER * 4)))
Kojto 90:cb3d968589d8 121
Kojto 90:cb3d968589d8 122 /* Alias word address of ULP bit */
Kojto 90:cb3d968589d8 123 #define ULP_BIT_NUMBER POSITION_VAL(PWR_CR_ULP)
Kojto 90:cb3d968589d8 124 #define CR_ULP_BB ((uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32) + (ULP_BIT_NUMBER * 4)))
Kojto 90:cb3d968589d8 125 /**
Kojto 90:cb3d968589d8 126 * @}
Kojto 90:cb3d968589d8 127 */
Kojto 90:cb3d968589d8 128
Kojto 90:cb3d968589d8 129 /** @defgroup PWR_CSR_register_alias PWR CSR Register alias address
Kojto 90:cb3d968589d8 130 * @{
Kojto 90:cb3d968589d8 131 */
Kojto 90:cb3d968589d8 132
Kojto 90:cb3d968589d8 133 /* --- CSR Register ---*/
Kojto 90:cb3d968589d8 134 /* Alias word address of EWUP1, EWUP2 and EWUP3 bits */
Kojto 90:cb3d968589d8 135 #define CSR_EWUP_BB(VAL) ((uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32) + (POSITION_VAL(VAL) * 4)))
Kojto 90:cb3d968589d8 136 /**
Kojto 90:cb3d968589d8 137 * @}
Kojto 90:cb3d968589d8 138 */
Kojto 90:cb3d968589d8 139
Kojto 90:cb3d968589d8 140 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
Kojto 90:cb3d968589d8 141 * @{
Kojto 90:cb3d968589d8 142 */
Kojto 90:cb3d968589d8 143 #define PWR_PVDLEVEL_0 PWR_CR_PLS_LEV0
Kojto 90:cb3d968589d8 144 #define PWR_PVDLEVEL_1 PWR_CR_PLS_LEV1
Kojto 90:cb3d968589d8 145 #define PWR_PVDLEVEL_2 PWR_CR_PLS_LEV2
Kojto 90:cb3d968589d8 146 #define PWR_PVDLEVEL_3 PWR_CR_PLS_LEV3
Kojto 90:cb3d968589d8 147 #define PWR_PVDLEVEL_4 PWR_CR_PLS_LEV4
Kojto 90:cb3d968589d8 148 #define PWR_PVDLEVEL_5 PWR_CR_PLS_LEV5
Kojto 90:cb3d968589d8 149 #define PWR_PVDLEVEL_6 PWR_CR_PLS_LEV6
Kojto 90:cb3d968589d8 150 #define PWR_PVDLEVEL_7 PWR_CR_PLS_LEV7 /* External input analog voltage
Kojto 90:cb3d968589d8 151 (Compare internally to VREFINT) */
Kojto 90:cb3d968589d8 152 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
Kojto 90:cb3d968589d8 153 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
Kojto 90:cb3d968589d8 154 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
Kojto 90:cb3d968589d8 155 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
Kojto 90:cb3d968589d8 156 /**
Kojto 90:cb3d968589d8 157 * @}
Kojto 90:cb3d968589d8 158 */
Kojto 90:cb3d968589d8 159
Kojto 90:cb3d968589d8 160 /** @defgroup PWR_PVD_Mode PWR PVD Mode
Kojto 90:cb3d968589d8 161 * @{
Kojto 90:cb3d968589d8 162 */
Kojto 90:cb3d968589d8 163 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
Kojto 90:cb3d968589d8 164 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
Kojto 90:cb3d968589d8 165 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
Kojto 90:cb3d968589d8 166 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
Kojto 90:cb3d968589d8 167 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
Kojto 90:cb3d968589d8 168 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
Kojto 90:cb3d968589d8 169 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
Kojto 90:cb3d968589d8 170
Kojto 90:cb3d968589d8 171 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
Kojto 90:cb3d968589d8 172 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
Kojto 90:cb3d968589d8 173 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
Kojto 90:cb3d968589d8 174 ((MODE) == PWR_PVD_MODE_NORMAL))
Kojto 90:cb3d968589d8 175 /**
Kojto 90:cb3d968589d8 176 * @}
Kojto 90:cb3d968589d8 177 */
Kojto 90:cb3d968589d8 178
Kojto 90:cb3d968589d8 179 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
Kojto 90:cb3d968589d8 180 * @{
Kojto 90:cb3d968589d8 181 */
Kojto 90:cb3d968589d8 182 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
Kojto 90:cb3d968589d8 183 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPSDSR
Kojto 90:cb3d968589d8 184
Kojto 90:cb3d968589d8 185 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
Kojto 90:cb3d968589d8 186 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
Kojto 90:cb3d968589d8 187 /**
Kojto 90:cb3d968589d8 188 * @}
Kojto 90:cb3d968589d8 189 */
Kojto 90:cb3d968589d8 190
Kojto 90:cb3d968589d8 191 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
Kojto 90:cb3d968589d8 192 * @{
Kojto 90:cb3d968589d8 193 */
Kojto 90:cb3d968589d8 194 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
Kojto 90:cb3d968589d8 195 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
Kojto 90:cb3d968589d8 196 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
Kojto 90:cb3d968589d8 197 /**
Kojto 90:cb3d968589d8 198 * @}
Kojto 90:cb3d968589d8 199 */
Kojto 90:cb3d968589d8 200
Kojto 90:cb3d968589d8 201 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
Kojto 90:cb3d968589d8 202 * @{
Kojto 90:cb3d968589d8 203 */
Kojto 90:cb3d968589d8 204 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
Kojto 90:cb3d968589d8 205 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
Kojto 90:cb3d968589d8 206 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE) )
Kojto 90:cb3d968589d8 207 /**
Kojto 90:cb3d968589d8 208 * @}
Kojto 90:cb3d968589d8 209 */
Kojto 90:cb3d968589d8 210
Kojto 90:cb3d968589d8 211 /** @defgroup PWR_Regulator_Voltage_Scale PWR Regulator Voltage Scale
Kojto 90:cb3d968589d8 212 * @{
Kojto 90:cb3d968589d8 213 */
Kojto 90:cb3d968589d8 214
Kojto 90:cb3d968589d8 215 #define PWR_REGULATOR_VOLTAGE_SCALE1 PWR_CR_VOS_0
Kojto 90:cb3d968589d8 216 #define PWR_REGULATOR_VOLTAGE_SCALE2 PWR_CR_VOS_1
Kojto 90:cb3d968589d8 217 #define PWR_REGULATOR_VOLTAGE_SCALE3 PWR_CR_VOS
Kojto 90:cb3d968589d8 218
Kojto 90:cb3d968589d8 219 #define IS_PWR_VOLTAGE_SCALING_RANGE(RANGE) (((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE1) || \
Kojto 90:cb3d968589d8 220 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE2) || \
Kojto 90:cb3d968589d8 221 ((RANGE) == PWR_REGULATOR_VOLTAGE_SCALE3))
Kojto 90:cb3d968589d8 222 /**
Kojto 90:cb3d968589d8 223 * @}
Kojto 90:cb3d968589d8 224 */
Kojto 90:cb3d968589d8 225
Kojto 90:cb3d968589d8 226 /** @defgroup PWR_Flag PWR Flag
Kojto 90:cb3d968589d8 227 * @{
Kojto 90:cb3d968589d8 228 */
Kojto 90:cb3d968589d8 229 #define PWR_FLAG_WU PWR_CSR_WUF
Kojto 90:cb3d968589d8 230 #define PWR_FLAG_SB PWR_CSR_SBF
Kojto 90:cb3d968589d8 231 #define PWR_FLAG_PVDO PWR_CSR_PVDO
Kojto 90:cb3d968589d8 232 #define PWR_FLAG_VREFINTRDY PWR_CSR_VREFINTRDYF
Kojto 90:cb3d968589d8 233 #define PWR_FLAG_VOS PWR_CSR_VOSF
Kojto 90:cb3d968589d8 234 #define PWR_FLAG_REGLP PWR_CSR_REGLPF
Kojto 90:cb3d968589d8 235
Kojto 90:cb3d968589d8 236 /**
Kojto 90:cb3d968589d8 237 * @}
Kojto 90:cb3d968589d8 238 */
Kojto 90:cb3d968589d8 239
Kojto 90:cb3d968589d8 240 /**
Kojto 90:cb3d968589d8 241 * @}
Kojto 90:cb3d968589d8 242 */
Kojto 90:cb3d968589d8 243
Kojto 90:cb3d968589d8 244 /* Exported macro ------------------------------------------------------------*/
Kojto 90:cb3d968589d8 245 /** @defgroup PWR_Exported_Macro PWR Exported Macro
Kojto 90:cb3d968589d8 246 * @{
Kojto 90:cb3d968589d8 247 */
Kojto 90:cb3d968589d8 248
Kojto 90:cb3d968589d8 249 /** @brief macros configure the main internal regulator output voltage.
Kojto 90:cb3d968589d8 250 * @param __REGULATOR__: specifies the regulator output voltage to achieve
Kojto 90:cb3d968589d8 251 * a tradeoff between performance and power consumption when the device does
Kojto 90:cb3d968589d8 252 * not operate at the maximum frequency (refer to the datasheets for more details).
Kojto 90:cb3d968589d8 253 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 254 * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output Scale 1 mode,
Kojto 90:cb3d968589d8 255 * System frequency up to 32 MHz.
Kojto 90:cb3d968589d8 256 * @arg PWR_REGULATOR_VOLTAGE_SCALE2: Regulator voltage output Scale 2 mode,
Kojto 90:cb3d968589d8 257 * System frequency up to 16 MHz.
Kojto 90:cb3d968589d8 258 * @arg PWR_REGULATOR_VOLTAGE_SCALE3: Regulator voltage output Scale 3 mode,
Kojto 90:cb3d968589d8 259 * System frequency up to 4.2 MHz
Kojto 90:cb3d968589d8 260 * @retval None
Kojto 90:cb3d968589d8 261 */
Kojto 90:cb3d968589d8 262 #define __HAL_PWR_VOLTAGESCALING_CONFIG(__REGULATOR__) (MODIFY_REG(PWR->CR, PWR_CR_VOS, (__REGULATOR__)))
Kojto 90:cb3d968589d8 263
Kojto 90:cb3d968589d8 264 /** @brief Check PWR flag is set or not.
Kojto 90:cb3d968589d8 265 * @param __FLAG__: specifies the flag to check.
Kojto 90:cb3d968589d8 266 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 267 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
Kojto 90:cb3d968589d8 268 * was received from the WKUP pin or from the RTC alarm (Alarm B),
Kojto 90:cb3d968589d8 269 * RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
Kojto 90:cb3d968589d8 270 * An additional wakeup event is detected if the WKUP pin is enabled
Kojto 90:cb3d968589d8 271 * (by setting the EWUP bit) when the WKUP pin level is already high.
Kojto 90:cb3d968589d8 272 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
Kojto 90:cb3d968589d8 273 * resumed from StandBy mode.
Kojto 90:cb3d968589d8 274 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
Kojto 90:cb3d968589d8 275 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
Kojto 90:cb3d968589d8 276 * For this reason, this bit is equal to 0 after Standby or reset
Kojto 90:cb3d968589d8 277 * until the PVDE bit is set.
Kojto 90:cb3d968589d8 278 * @arg PWR_FLAG_VREFINTRDY: Internal voltage reference (VREFINT) ready flag.
Kojto 90:cb3d968589d8 279 * This bit indicates the state of the internal voltage reference, VREFINT.
Kojto 90:cb3d968589d8 280 * @arg PWR_FLAG_VOS: Voltage Scaling select flag. A delay is required for
Kojto 90:cb3d968589d8 281 * the internal regulator to be ready after the voltage range is changed.
Kojto 90:cb3d968589d8 282 * The VOSF bit indicates that the regulator has reached the voltage level
Kojto 90:cb3d968589d8 283 * defined with bits VOS of PWR_CR register.
Kojto 90:cb3d968589d8 284 * @arg PWR_FLAG_REGLP: Regulator LP flag. When the MCU exits from Low power run
Kojto 90:cb3d968589d8 285 * mode, this bit stays at 1 until the regulator is ready in main mode.
Kojto 90:cb3d968589d8 286 * A polling on this bit is recommended to wait for the regulator main mode.
Kojto 90:cb3d968589d8 287 * This bit is reset by hardware when the regulator is ready.
Kojto 90:cb3d968589d8 288 * @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto 90:cb3d968589d8 289 */
Kojto 90:cb3d968589d8 290 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
Kojto 90:cb3d968589d8 291
Kojto 90:cb3d968589d8 292 /** @brief Clear the PWR's pending flags.
Kojto 90:cb3d968589d8 293 * @param __FLAG__: specifies the flag to clear.
Kojto 90:cb3d968589d8 294 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 295 * @arg PWR_FLAG_WU: Wake Up flag
Kojto 90:cb3d968589d8 296 * @arg PWR_FLAG_SB: StandBy flag
Kojto 90:cb3d968589d8 297 */
Kojto 90:cb3d968589d8 298 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) (PWR->CR |= (__FLAG__) << 2)
Kojto 90:cb3d968589d8 299
Kojto 90:cb3d968589d8 300 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
Kojto 90:cb3d968589d8 301
Kojto 90:cb3d968589d8 302 /**
Kojto 90:cb3d968589d8 303 * @brief Enable interrupt on PVD Exti Line 16.
Kojto 90:cb3d968589d8 304 * @retval None.
Kojto 90:cb3d968589d8 305 */
Kojto 90:cb3d968589d8 306 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() (EXTI->IMR |= (PWR_EXTI_LINE_PVD))
Kojto 90:cb3d968589d8 307
Kojto 90:cb3d968589d8 308 /**
Kojto 90:cb3d968589d8 309 * @brief Disable interrupt on PVD Exti Line 16.
Kojto 90:cb3d968589d8 310 * @retval None.
Kojto 90:cb3d968589d8 311 */
Kojto 90:cb3d968589d8 312 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() (EXTI->IMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 90:cb3d968589d8 313
Kojto 90:cb3d968589d8 314 /**
Kojto 90:cb3d968589d8 315 * @brief Enable event on PVD Exti Line 16.
Kojto 90:cb3d968589d8 316 * @retval None.
Kojto 90:cb3d968589d8 317 */
Kojto 90:cb3d968589d8 318 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() (EXTI->EMR |= (PWR_EXTI_LINE_PVD))
Kojto 90:cb3d968589d8 319
Kojto 90:cb3d968589d8 320 /**
Kojto 90:cb3d968589d8 321 * @brief Disable event on PVD Exti Line 16.
Kojto 90:cb3d968589d8 322 * @retval None.
Kojto 90:cb3d968589d8 323 */
Kojto 90:cb3d968589d8 324 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() (EXTI->EMR &= ~(PWR_EXTI_LINE_PVD))
Kojto 90:cb3d968589d8 325
Kojto 90:cb3d968589d8 326 /**
Kojto 90:cb3d968589d8 327 * @brief PVD EXTI line configuration: clear falling edge trigger and set rising edge.
Kojto 90:cb3d968589d8 328 * @retval None.
Kojto 90:cb3d968589d8 329 */
Kojto 90:cb3d968589d8 330 #define __HAL_PWR_PVD_EXTI_CLEAR_EGDE_TRIGGER() EXTI->FTSR &= ~(PWR_EXTI_LINE_PVD); \
Kojto 90:cb3d968589d8 331 EXTI->RTSR &= ~(PWR_EXTI_LINE_PVD)
Kojto 90:cb3d968589d8 332
Kojto 90:cb3d968589d8 333 /**
Kojto 90:cb3d968589d8 334 * @brief PVD EXTI line configuration: set falling edge trigger.
Kojto 90:cb3d968589d8 335 * @retval None.
Kojto 90:cb3d968589d8 336 */
Kojto 90:cb3d968589d8 337 #define __HAL_PWR_PVD_EXTI_SET_FALLING_EGDE_TRIGGER() EXTI->FTSR |= (PWR_EXTI_LINE_PVD)
Kojto 90:cb3d968589d8 338
Kojto 90:cb3d968589d8 339 /**
Kojto 90:cb3d968589d8 340 * @brief PVD EXTI line configuration: set rising edge trigger.
Kojto 90:cb3d968589d8 341 * @retval None.
Kojto 90:cb3d968589d8 342 */
Kojto 90:cb3d968589d8 343 #define __HAL_PWR_PVD_EXTI_SET_RISING_EDGE_TRIGGER() EXTI->RTSR |= (PWR_EXTI_LINE_PVD)
Kojto 90:cb3d968589d8 344
Kojto 90:cb3d968589d8 345 /**
Kojto 90:cb3d968589d8 346 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
Kojto 90:cb3d968589d8 347 * @retval EXTI PVD Line Status.
Kojto 90:cb3d968589d8 348 */
Kojto 90:cb3d968589d8 349 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
Kojto 90:cb3d968589d8 350
Kojto 90:cb3d968589d8 351 /**
Kojto 90:cb3d968589d8 352 * @brief Clear the PVD EXTI flag.
Kojto 90:cb3d968589d8 353 * @retval None.
Kojto 90:cb3d968589d8 354 */
Kojto 90:cb3d968589d8 355 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
Kojto 90:cb3d968589d8 356
Kojto 90:cb3d968589d8 357 /**
Kojto 90:cb3d968589d8 358 * @brief Generate a Software interrupt on selected EXTI line.
Kojto 90:cb3d968589d8 359 * @retval None.
Kojto 90:cb3d968589d8 360 */
Kojto 90:cb3d968589d8 361 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() (EXTI->SWIER |= (PWR_EXTI_LINE_PVD))
Kojto 90:cb3d968589d8 362 /**
Kojto 90:cb3d968589d8 363 * @}
Kojto 90:cb3d968589d8 364 */
Kojto 90:cb3d968589d8 365
Kojto 90:cb3d968589d8 366 /* Include PWR HAL Extension module */
Kojto 90:cb3d968589d8 367 #include "stm32l1xx_hal_pwr_ex.h"
Kojto 90:cb3d968589d8 368
Kojto 90:cb3d968589d8 369 /* Exported functions --------------------------------------------------------*/
Kojto 90:cb3d968589d8 370
Kojto 90:cb3d968589d8 371 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
Kojto 90:cb3d968589d8 372 * @{
Kojto 90:cb3d968589d8 373 */
Kojto 90:cb3d968589d8 374
Kojto 90:cb3d968589d8 375 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
Kojto 90:cb3d968589d8 376 * @{
Kojto 90:cb3d968589d8 377 */
Kojto 90:cb3d968589d8 378
Kojto 90:cb3d968589d8 379 /* Initialization and de-initialization functions *******************************/
Kojto 90:cb3d968589d8 380 void HAL_PWR_DeInit(void);
Kojto 90:cb3d968589d8 381 void HAL_PWR_EnableBkUpAccess(void);
Kojto 90:cb3d968589d8 382 void HAL_PWR_DisableBkUpAccess(void);
Kojto 90:cb3d968589d8 383
Kojto 90:cb3d968589d8 384 /**
Kojto 90:cb3d968589d8 385 * @}
Kojto 90:cb3d968589d8 386 */
Kojto 90:cb3d968589d8 387
Kojto 90:cb3d968589d8 388 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
Kojto 90:cb3d968589d8 389 * @{
Kojto 90:cb3d968589d8 390 */
Kojto 90:cb3d968589d8 391
Kojto 90:cb3d968589d8 392 /* Peripheral Control functions ************************************************/
Kojto 90:cb3d968589d8 393 void HAL_PWR_PVDConfig(PWR_PVDTypeDef *sConfigPVD);
Kojto 90:cb3d968589d8 394 void HAL_PWR_EnablePVD(void);
Kojto 90:cb3d968589d8 395 void HAL_PWR_DisablePVD(void);
Kojto 90:cb3d968589d8 396
Kojto 90:cb3d968589d8 397 /* WakeUp pins configuration functions ****************************************/
Kojto 90:cb3d968589d8 398 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
Kojto 90:cb3d968589d8 399 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
Kojto 90:cb3d968589d8 400
Kojto 90:cb3d968589d8 401 /* Low Power modes configuration functions ************************************/
Kojto 90:cb3d968589d8 402 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
Kojto 90:cb3d968589d8 403 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
Kojto 90:cb3d968589d8 404 void HAL_PWR_EnterSTANDBYMode(void);
Kojto 90:cb3d968589d8 405
Kojto 90:cb3d968589d8 406 void HAL_PWR_PVD_IRQHandler(void);
Kojto 90:cb3d968589d8 407 void HAL_PWR_PVDCallback(void);
Kojto 90:cb3d968589d8 408 /**
Kojto 90:cb3d968589d8 409 * @}
Kojto 90:cb3d968589d8 410 */
Kojto 90:cb3d968589d8 411
Kojto 90:cb3d968589d8 412 /**
Kojto 90:cb3d968589d8 413 * @}
Kojto 90:cb3d968589d8 414 */
Kojto 90:cb3d968589d8 415
Kojto 90:cb3d968589d8 416 /**
Kojto 90:cb3d968589d8 417 * @}
Kojto 90:cb3d968589d8 418 */
Kojto 90:cb3d968589d8 419
Kojto 90:cb3d968589d8 420 /**
Kojto 90:cb3d968589d8 421 * @}
Kojto 90:cb3d968589d8 422 */
Kojto 90:cb3d968589d8 423
Kojto 90:cb3d968589d8 424 #ifdef __cplusplus
Kojto 90:cb3d968589d8 425 }
Kojto 90:cb3d968589d8 426 #endif
Kojto 90:cb3d968589d8 427
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 #endif /* __STM32L1xx_HAL_PWR_H */
Kojto 90:cb3d968589d8 430
Kojto 90:cb3d968589d8 431 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/