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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:: filartrix
Date:: Wed Apr 08 14:12:53 2015 +0000
Revision:: 97:4298809c7c9e
Parent:: 93:e188a91d3eaa

First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	85:024bf7f99721	1	/**
bogdanm	85:024bf7f99721	2	******************************************************************************
bogdanm	85:024bf7f99721	3	* @file stm32f0xx_hal_rcc_ex.h
bogdanm	85:024bf7f99721	4	* @author MCD Application Team
Kojto	93:e188a91d3eaa	5	* @version V1.2.0
Kojto	93:e188a91d3eaa	6	* @date 11-December-2014
bogdanm	85:024bf7f99721	7	* @brief Header file of RCC HAL Extension module.
bogdanm	85:024bf7f99721	8	******************************************************************************
bogdanm	85:024bf7f99721	9	* @attention
bogdanm	85:024bf7f99721	10	*
bogdanm	85:024bf7f99721	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	85:024bf7f99721	12	*
bogdanm	85:024bf7f99721	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	85:024bf7f99721	14	* are permitted provided that the following conditions are met:
bogdanm	85:024bf7f99721	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	85:024bf7f99721	16	* this list of conditions and the following disclaimer.
bogdanm	85:024bf7f99721	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	85:024bf7f99721	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	85:024bf7f99721	19	* and/or other materials provided with the distribution.
bogdanm	85:024bf7f99721	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	85:024bf7f99721	21	* may be used to endorse or promote products derived from this software
bogdanm	85:024bf7f99721	22	* without specific prior written permission.
bogdanm	85:024bf7f99721	23	*
bogdanm	85:024bf7f99721	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	85:024bf7f99721	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	85:024bf7f99721	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	85:024bf7f99721	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	85:024bf7f99721	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	85:024bf7f99721	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	85:024bf7f99721	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	85:024bf7f99721	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	85:024bf7f99721	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	85:024bf7f99721	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	85:024bf7f99721	34	*
bogdanm	85:024bf7f99721	35	******************************************************************************
bogdanm	85:024bf7f99721	36	*/
bogdanm	85:024bf7f99721	37
bogdanm	85:024bf7f99721	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	85:024bf7f99721	39	#ifndef __STM32F0xx_HAL_RCC_EX_H
bogdanm	85:024bf7f99721	40	#define __STM32F0xx_HAL_RCC_EX_H
bogdanm	85:024bf7f99721	41
bogdanm	85:024bf7f99721	42	#ifdef __cplusplus
bogdanm	85:024bf7f99721	43	extern "C" {
bogdanm	85:024bf7f99721	44	#endif
bogdanm	85:024bf7f99721	45
bogdanm	85:024bf7f99721	46	/* Includes ------------------------------------------------------------------*/
bogdanm	85:024bf7f99721	47	#include "stm32f0xx_hal_def.h"
bogdanm	85:024bf7f99721	48
bogdanm	85:024bf7f99721	49	/** @addtogroup STM32F0xx_HAL_Driver
bogdanm	85:024bf7f99721	50	* @{
bogdanm	85:024bf7f99721	51	*/
bogdanm	85:024bf7f99721	52
bogdanm	85:024bf7f99721	53	/** @addtogroup RCCEx
bogdanm	85:024bf7f99721	54	* @{
bogdanm	85:024bf7f99721	55	*/
bogdanm	85:024bf7f99721	56
bogdanm	85:024bf7f99721	57	/* Exported types ------------------------------------------------------------*/
bogdanm	85:024bf7f99721	58
bogdanm	92:4fc01daae5a5	59	/** @defgroup RCCEx_Exported_Types RCCEx Exported Types
bogdanm	92:4fc01daae5a5	60	* @{
bogdanm	92:4fc01daae5a5	61	*/
bogdanm	92:4fc01daae5a5	62
bogdanm	85:024bf7f99721	63	/**
bogdanm	85:024bf7f99721	64	* @brief RCC extended clocks structure definition
bogdanm	85:024bf7f99721	65	*/
Kojto	93:e188a91d3eaa	66	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
Kojto	93:e188a91d3eaa	67	defined(STM32F030xC)
bogdanm	85:024bf7f99721	68	typedef struct
bogdanm	85:024bf7f99721	69	{
bogdanm	85:024bf7f99721	70	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	71	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	72
bogdanm	85:024bf7f99721	73	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	74	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	75
bogdanm	85:024bf7f99721	76	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	77	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	78
bogdanm	85:024bf7f99721	79	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	80	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	81
bogdanm	85:024bf7f99721	82	}RCC_PeriphCLKInitTypeDef;
Kojto	93:e188a91d3eaa	83	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	93:e188a91d3eaa	84	STM32F030xC */
Kojto	93:e188a91d3eaa	85
Kojto	93:e188a91d3eaa	86	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	93:e188a91d3eaa	87	typedef struct
Kojto	93:e188a91d3eaa	88	{
Kojto	93:e188a91d3eaa	89	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	93:e188a91d3eaa	90	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	93:e188a91d3eaa	91
Kojto	93:e188a91d3eaa	92	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	93:e188a91d3eaa	93	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	93:e188a91d3eaa	94
Kojto	93:e188a91d3eaa	95	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	93:e188a91d3eaa	96	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	93:e188a91d3eaa	97
Kojto	93:e188a91d3eaa	98	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	93:e188a91d3eaa	99	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	93:e188a91d3eaa	100
Kojto	93:e188a91d3eaa	101	uint32_t UsbClockSelection; /*!< USB clock source
Kojto	93:e188a91d3eaa	102	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	93:e188a91d3eaa	103
Kojto	93:e188a91d3eaa	104	}RCC_PeriphCLKInitTypeDef;
Kojto	93:e188a91d3eaa	105	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	85:024bf7f99721	106
bogdanm	85:024bf7f99721	107	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	85:024bf7f99721	108	typedef struct
bogdanm	85:024bf7f99721	109	{
bogdanm	85:024bf7f99721	110	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	111	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	112
bogdanm	85:024bf7f99721	113	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	114	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	115
bogdanm	85:024bf7f99721	116	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	117	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	118
bogdanm	85:024bf7f99721	119	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	120	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	121
bogdanm	85:024bf7f99721	122	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	123	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	124
bogdanm	85:024bf7f99721	125	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	85:024bf7f99721	126	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	85:024bf7f99721	127
bogdanm	85:024bf7f99721	128	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	129	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	85:024bf7f99721	130
bogdanm	85:024bf7f99721	131	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	132	typedef struct
bogdanm	85:024bf7f99721	133	{
bogdanm	85:024bf7f99721	134	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	135	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	136
bogdanm	85:024bf7f99721	137	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	138	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	139
bogdanm	85:024bf7f99721	140	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	141	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	142
bogdanm	85:024bf7f99721	143	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	144	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	145
bogdanm	85:024bf7f99721	146	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	147	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	148
bogdanm	85:024bf7f99721	149	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	150	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	151
bogdanm	85:024bf7f99721	152	#if defined(STM32F071xB)
bogdanm	85:024bf7f99721	153	typedef struct
bogdanm	85:024bf7f99721	154	{
bogdanm	85:024bf7f99721	155	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	156	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	157
bogdanm	85:024bf7f99721	158	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	159	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	160
bogdanm	85:024bf7f99721	161	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	162	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	163
bogdanm	85:024bf7f99721	164	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	165	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	166
bogdanm	85:024bf7f99721	167	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	168	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	169
bogdanm	85:024bf7f99721	170	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	171	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	172
bogdanm	85:024bf7f99721	173	}RCC_PeriphCLKInitTypeDef;
bogdanm	85:024bf7f99721	174	#endif /* STM32F071xB */
bogdanm	85:024bf7f99721	175
bogdanm	92:4fc01daae5a5	176	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	177	typedef struct
bogdanm	85:024bf7f99721	178	{
bogdanm	85:024bf7f99721	179	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	180	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	181
bogdanm	85:024bf7f99721	182	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	183	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	184
bogdanm	85:024bf7f99721	185	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	186	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	187
bogdanm	85:024bf7f99721	188	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	189	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	190
bogdanm	85:024bf7f99721	191	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	192	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	193
bogdanm	85:024bf7f99721	194	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	195	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	196
bogdanm	85:024bf7f99721	197	uint32_t UsbClockSelection; /*!< USB clock source
bogdanm	85:024bf7f99721	198	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	85:024bf7f99721	199
bogdanm	85:024bf7f99721	200	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	201	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	202
bogdanm	92:4fc01daae5a5	203
bogdanm	92:4fc01daae5a5	204	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	205	typedef struct
bogdanm	85:024bf7f99721	206	{
bogdanm	85:024bf7f99721	207	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	85:024bf7f99721	208	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	85:024bf7f99721	209
bogdanm	85:024bf7f99721	210	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	85:024bf7f99721	211	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	85:024bf7f99721	212
bogdanm	85:024bf7f99721	213	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	85:024bf7f99721	214	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	85:024bf7f99721	215
bogdanm	85:024bf7f99721	216	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	85:024bf7f99721	217	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	85:024bf7f99721	218
bogdanm	92:4fc01daae5a5	219	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	92:4fc01daae5a5	220	This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
bogdanm	92:4fc01daae5a5	221
bogdanm	85:024bf7f99721	222	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	85:024bf7f99721	223	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	85:024bf7f99721	224
bogdanm	85:024bf7f99721	225	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	85:024bf7f99721	226	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	85:024bf7f99721	227
bogdanm	85:024bf7f99721	228	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	229	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	230
bogdanm	92:4fc01daae5a5	231	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	232	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	233	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	234
bogdanm	85:024bf7f99721	235	/**
bogdanm	85:024bf7f99721	236	* @brief RCC_CRS Init structure definition
bogdanm	85:024bf7f99721	237	*/
bogdanm	85:024bf7f99721	238	typedef struct
bogdanm	85:024bf7f99721	239	{
bogdanm	85:024bf7f99721	240	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	85:024bf7f99721	241	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	85:024bf7f99721	242
bogdanm	85:024bf7f99721	243	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	85:024bf7f99721	244	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	85:024bf7f99721	245
bogdanm	85:024bf7f99721	246	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	85:024bf7f99721	247	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	85:024bf7f99721	248
bogdanm	85:024bf7f99721	249	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm	85:024bf7f99721	250	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm	85:024bf7f99721	251	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	85:024bf7f99721	252
bogdanm	85:024bf7f99721	253	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	85:024bf7f99721	254	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	85:024bf7f99721	255
bogdanm	85:024bf7f99721	256	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	85:024bf7f99721	257	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm	85:024bf7f99721	258
bogdanm	85:024bf7f99721	259	}RCC_CRSInitTypeDef;
bogdanm	85:024bf7f99721	260
bogdanm	85:024bf7f99721	261	/**
bogdanm	85:024bf7f99721	262	* @brief RCC_CRS Synchronization structure definition
bogdanm	85:024bf7f99721	263	*/
bogdanm	85:024bf7f99721	264	typedef struct
bogdanm	85:024bf7f99721	265	{
bogdanm	85:024bf7f99721	266	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm	85:024bf7f99721	267	This parameter must be a number between 0 and 0xFFFF*/
bogdanm	85:024bf7f99721	268
bogdanm	85:024bf7f99721	269	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	85:024bf7f99721	270	This parameter must be a number between 0 and 0x3F */
bogdanm	85:024bf7f99721	271
bogdanm	85:024bf7f99721	272	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	85:024bf7f99721	273	value latched in the time of the last SYNC event.
bogdanm	85:024bf7f99721	274	This parameter must be a number between 0 and 0xFFFF */
bogdanm	85:024bf7f99721	275
bogdanm	85:024bf7f99721	276	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	85:024bf7f99721	277	frequency error counter latched in the time of the last SYNC event.
bogdanm	85:024bf7f99721	278	It shows whether the actual frequency is below or above the target.
bogdanm	85:024bf7f99721	279	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	85:024bf7f99721	280
bogdanm	85:024bf7f99721	281	}RCC_CRSSynchroInfoTypeDef;
bogdanm	85:024bf7f99721	282
Kojto	93:e188a91d3eaa	283	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	92:4fc01daae5a5	284	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	285	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	286
bogdanm	92:4fc01daae5a5	287	/**
bogdanm	92:4fc01daae5a5	288	* @}
bogdanm	92:4fc01daae5a5	289	*/
bogdanm	85:024bf7f99721	290
bogdanm	85:024bf7f99721	291	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	292
bogdanm	92:4fc01daae5a5	293	/** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
bogdanm	85:024bf7f99721	294	* @{
bogdanm	85:024bf7f99721	295	*/
bogdanm	85:024bf7f99721	296
Kojto	93:e188a91d3eaa	297	/** @defgroup RCCEx_CRS_Status RCCEx CRS Status
Kojto	93:e188a91d3eaa	298	* @{
Kojto	93:e188a91d3eaa	299	*/
Kojto	93:e188a91d3eaa	300	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	93:e188a91d3eaa	301	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	93:e188a91d3eaa	302	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	93:e188a91d3eaa	303
Kojto	93:e188a91d3eaa	304	#define RCC_CRS_NONE ((uint32_t)0x00000000)
Kojto	93:e188a91d3eaa	305	#define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	306	#define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
Kojto	93:e188a91d3eaa	307	#define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
Kojto	93:e188a91d3eaa	308	#define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
Kojto	93:e188a91d3eaa	309	#define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
Kojto	93:e188a91d3eaa	310	#define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
Kojto	93:e188a91d3eaa	311
Kojto	93:e188a91d3eaa	312	#endif /* STM32F042x6 \|\| STM32F048xx */
Kojto	93:e188a91d3eaa	313	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	93:e188a91d3eaa	314	/* STM32F091xC \|\| STM32F098xx */
Kojto	93:e188a91d3eaa	315	/**
Kojto	93:e188a91d3eaa	316	* @}
Kojto	93:e188a91d3eaa	317	*/
Kojto	93:e188a91d3eaa	318
bogdanm	92:4fc01daae5a5	319	/** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
bogdanm	85:024bf7f99721	320	* @{
bogdanm	85:024bf7f99721	321	*/
Kojto	93:e188a91d3eaa	322	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
Kojto	93:e188a91d3eaa	323	defined(STM32F030xC)
bogdanm	85:024bf7f99721	324	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	325	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	326	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	327
bogdanm	85:024bf7f99721	328	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	85:024bf7f99721	329	RCC_PERIPHCLK_RTC))
Kojto	93:e188a91d3eaa	330	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| STM32F031x6 \|\| STM32F038xx \|\|
Kojto	93:e188a91d3eaa	331	STM32F030xC */
Kojto	93:e188a91d3eaa	332
Kojto	93:e188a91d3eaa	333	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	93:e188a91d3eaa	334	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	93:e188a91d3eaa	335	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	93:e188a91d3eaa	336	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	93:e188a91d3eaa	337	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	93:e188a91d3eaa	338
Kojto	93:e188a91d3eaa	339	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
Kojto	93:e188a91d3eaa	340	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
Kojto	93:e188a91d3eaa	341	#endif /* STM32F070x6 \|\| STM32F070xB */
bogdanm	92:4fc01daae5a5	342
bogdanm	92:4fc01daae5a5	343	#if defined(STM32F042x6) \|\| defined(STM32F048xx)
bogdanm	92:4fc01daae5a5	344	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	345	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	346	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	92:4fc01daae5a5	347	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	348	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	92:4fc01daae5a5	349
bogdanm	92:4fc01daae5a5	350	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	92:4fc01daae5a5	351	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
bogdanm	92:4fc01daae5a5	352	RCC_PERIPHCLK_USB))
bogdanm	92:4fc01daae5a5	353	#endif /* STM32F042x6 \|\| STM32F048xx */
bogdanm	85:024bf7f99721	354
bogdanm	85:024bf7f99721	355	#if defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	356	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	357	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	358	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	359	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	360
bogdanm	92:4fc01daae5a5	361	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_I2C1 \| \
bogdanm	85:024bf7f99721	362	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
bogdanm	85:024bf7f99721	363	#endif /* STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	364
bogdanm	85:024bf7f99721	365	#if defined(STM32F071xB)
bogdanm	85:024bf7f99721	366	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	367	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	368	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	369	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	370	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	371
bogdanm	85:024bf7f99721	372	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	85:024bf7f99721	373	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	85:024bf7f99721	374	RCC_PERIPHCLK_RTC))
bogdanm	85:024bf7f99721	375	#endif /* STM32F071xB */
bogdanm	85:024bf7f99721	376
bogdanm	92:4fc01daae5a5	377	#if defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	378	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	379	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	380	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	381	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	382	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	85:024bf7f99721	383	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	85:024bf7f99721	384
bogdanm	85:024bf7f99721	385	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	85:024bf7f99721	386	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	85:024bf7f99721	387	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB))
bogdanm	92:4fc01daae5a5	388	#endif /* STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	389
bogdanm	92:4fc01daae5a5	390	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	391	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	85:024bf7f99721	392	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	85:024bf7f99721	393	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	85:024bf7f99721	394	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	85:024bf7f99721	395	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	396	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
bogdanm	85:024bf7f99721	397
bogdanm	85:024bf7f99721	398	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| \
bogdanm	85:024bf7f99721	399	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_CEC \| \
bogdanm	92:4fc01daae5a5	400	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USART3 ))
bogdanm	92:4fc01daae5a5	401	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	402
bogdanm	85:024bf7f99721	403	/**
bogdanm	85:024bf7f99721	404	* @}
bogdanm	85:024bf7f99721	405	*/
bogdanm	85:024bf7f99721	406
bogdanm	92:4fc01daae5a5	407	/** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
bogdanm	92:4fc01daae5a5	408	* @{
bogdanm	92:4fc01daae5a5	409	*/
bogdanm	92:4fc01daae5a5	410
Kojto	93:e188a91d3eaa	411	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6) \|\| defined(STM32F070xB) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	412
bogdanm	85:024bf7f99721	413	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
bogdanm	85:024bf7f99721	414
bogdanm	85:024bf7f99721	415	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	85:024bf7f99721	416	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	85:024bf7f99721	417	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	418	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	419	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	420	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	421	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
bogdanm	85:024bf7f99721	422	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	85:024bf7f99721	423	((SOURCE) == RCC_MCOSOURCE_HSI14))
bogdanm	85:024bf7f99721	424
Kojto	93:e188a91d3eaa	425	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| STM32F070xB \|\| STM32F030xC */
bogdanm	85:024bf7f99721	426
bogdanm	85:024bf7f99721	427	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	428
bogdanm	85:024bf7f99721	429	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	85:024bf7f99721	430	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	85:024bf7f99721	431	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	432	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	433	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	434	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	435	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	85:024bf7f99721	436	((SOURCE) == RCC_MCOSOURCE_HSI14))
bogdanm	85:024bf7f99721	437
bogdanm	85:024bf7f99721	438	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	439
bogdanm	85:024bf7f99721	440	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	441	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	442	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	443
bogdanm	85:024bf7f99721	444	#define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
bogdanm	85:024bf7f99721	445	#define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL \| RCC_CFGR_PLLNODIV)
bogdanm	85:024bf7f99721	446
bogdanm	85:024bf7f99721	447	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	85:024bf7f99721	448	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	85:024bf7f99721	449	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	450	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	451	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	452	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	453	((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) \|\| \
bogdanm	85:024bf7f99721	454	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) \|\| \
bogdanm	85:024bf7f99721	455	((SOURCE) == RCC_MCOSOURCE_HSI14) \|\| \
bogdanm	85:024bf7f99721	456	((SOURCE) == RCC_MCOSOURCE_HSI48))
bogdanm	85:024bf7f99721	457
bogdanm	85:024bf7f99721	458	#define RCC_IT_HSI48 ((uint8_t)0x40)
bogdanm	85:024bf7f99721	459
bogdanm	85:024bf7f99721	460	/* Flags in the CR2 register */
bogdanm	85:024bf7f99721	461	#define RCC_CR2_HSI48RDY_BitNumber 16
bogdanm	85:024bf7f99721	462
bogdanm	85:024bf7f99721	463	#define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI48RDY_BitNumber))
bogdanm	85:024bf7f99721	464
bogdanm	92:4fc01daae5a5	465	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	466	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	467	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	468	/**
bogdanm	92:4fc01daae5a5	469	* @}
bogdanm	92:4fc01daae5a5	470	*/
bogdanm	85:024bf7f99721	471
bogdanm	92:4fc01daae5a5	472	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx)
bogdanm	85:024bf7f99721	473
bogdanm	92:4fc01daae5a5	474	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
bogdanm	85:024bf7f99721	475	* @{
bogdanm	85:024bf7f99721	476	*/
bogdanm	85:024bf7f99721	477	#define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
bogdanm	85:024bf7f99721	478	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
bogdanm	85:024bf7f99721	479
bogdanm	85:024bf7f99721	480	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) \|\| \
bogdanm	85:024bf7f99721	481	((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
bogdanm	85:024bf7f99721	482	/**
bogdanm	85:024bf7f99721	483	* @}
bogdanm	85:024bf7f99721	484	*/
bogdanm	85:024bf7f99721	485
bogdanm	92:4fc01daae5a5	486	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| STM32F078xx */
bogdanm	85:024bf7f99721	487
Kojto	93:e188a91d3eaa	488	#if defined(STM32F070x6) \|\| defined(STM32F070xB)
Kojto	93:e188a91d3eaa	489
Kojto	93:e188a91d3eaa	490	/** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto	93:e188a91d3eaa	491	* @{
Kojto	93:e188a91d3eaa	492	*/
Kojto	93:e188a91d3eaa	493	#define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto	93:e188a91d3eaa	494
Kojto	93:e188a91d3eaa	495	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto	93:e188a91d3eaa	496	/**
Kojto	93:e188a91d3eaa	497	* @}
Kojto	93:e188a91d3eaa	498	*/
Kojto	93:e188a91d3eaa	499
Kojto	93:e188a91d3eaa	500	#endif /* STM32F070x6 \|\| STM32F070xB */
Kojto	93:e188a91d3eaa	501
bogdanm	92:4fc01daae5a5	502	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	503	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	504
bogdanm	92:4fc01daae5a5	505	/** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
bogdanm	85:024bf7f99721	506	* @{
bogdanm	85:024bf7f99721	507	*/
bogdanm	85:024bf7f99721	508	#define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
bogdanm	85:024bf7f99721	509	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
bogdanm	85:024bf7f99721	510	#define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
bogdanm	85:024bf7f99721	511	#define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
bogdanm	85:024bf7f99721	512
bogdanm	85:024bf7f99721	513	#define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
bogdanm	85:024bf7f99721	514	((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
bogdanm	85:024bf7f99721	515	((SOURCE) == RCC_USART2CLKSOURCE_LSE) \|\| \
bogdanm	85:024bf7f99721	516	((SOURCE) == RCC_USART2CLKSOURCE_HSI))
bogdanm	85:024bf7f99721	517	/**
bogdanm	85:024bf7f99721	518	* @}
bogdanm	85:024bf7f99721	519	*/
bogdanm	85:024bf7f99721	520
bogdanm	92:4fc01daae5a5	521	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	522	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	523
bogdanm	92:4fc01daae5a5	524	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	525
bogdanm	92:4fc01daae5a5	526	/** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
bogdanm	92:4fc01daae5a5	527	* @{
bogdanm	92:4fc01daae5a5	528	*/
bogdanm	92:4fc01daae5a5	529	#define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
bogdanm	92:4fc01daae5a5	530	#define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
bogdanm	92:4fc01daae5a5	531	#define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
bogdanm	92:4fc01daae5a5	532	#define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
bogdanm	92:4fc01daae5a5	533
bogdanm	92:4fc01daae5a5	534	#define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) \|\| \
bogdanm	92:4fc01daae5a5	535	((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) \|\| \
bogdanm	92:4fc01daae5a5	536	((SOURCE) == RCC_USART3CLKSOURCE_LSE) \|\| \
bogdanm	92:4fc01daae5a5	537	((SOURCE) == RCC_USART3CLKSOURCE_HSI))
bogdanm	92:4fc01daae5a5	538	/**
bogdanm	92:4fc01daae5a5	539	* @}
bogdanm	92:4fc01daae5a5	540	*/
bogdanm	92:4fc01daae5a5	541
bogdanm	92:4fc01daae5a5	542	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	543
bogdanm	85:024bf7f99721	544
bogdanm	85:024bf7f99721	545	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	546	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	547	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	548	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	549
bogdanm	92:4fc01daae5a5	550	/** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
bogdanm	85:024bf7f99721	551	* @{
bogdanm	85:024bf7f99721	552	*/
bogdanm	85:024bf7f99721	553	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm	85:024bf7f99721	554	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm	85:024bf7f99721	555
bogdanm	85:024bf7f99721	556	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	557	((SOURCE) == RCC_CECCLKSOURCE_LSE))
bogdanm	85:024bf7f99721	558	/**
bogdanm	85:024bf7f99721	559	* @}
bogdanm	85:024bf7f99721	560	*/
bogdanm	85:024bf7f99721	561
bogdanm	92:4fc01daae5a5	562	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	563	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	564	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	565	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	566
bogdanm	92:4fc01daae5a5	567	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	568	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	569	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	570
bogdanm	92:4fc01daae5a5	571	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
bogdanm	85:024bf7f99721	572	* @{
bogdanm	85:024bf7f99721	573	*/
bogdanm	85:024bf7f99721	574	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
bogdanm	85:024bf7f99721	575	#define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
bogdanm	85:024bf7f99721	576
bogdanm	85:024bf7f99721	577	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	578	((SOURCE) == RCC_PLLSOURCE_HSI48) \|\| \
bogdanm	85:024bf7f99721	579	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	85:024bf7f99721	580	/**
bogdanm	85:024bf7f99721	581	* @}
bogdanm	85:024bf7f99721	582	*/
bogdanm	85:024bf7f99721	583
bogdanm	92:4fc01daae5a5	584	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
bogdanm	85:024bf7f99721	585	* @{
bogdanm	85:024bf7f99721	586	*/
bogdanm	85:024bf7f99721	587	#define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
bogdanm	85:024bf7f99721	588
bogdanm	85:024bf7f99721	589	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	590	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	591	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) \|\| \
bogdanm	85:024bf7f99721	592	((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
bogdanm	85:024bf7f99721	593
bogdanm	85:024bf7f99721	594	#define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
bogdanm	85:024bf7f99721	595
bogdanm	85:024bf7f99721	596	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
bogdanm	85:024bf7f99721	597	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
bogdanm	85:024bf7f99721	598	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) \|\| \
bogdanm	85:024bf7f99721	599	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
bogdanm	85:024bf7f99721	600	/**
bogdanm	85:024bf7f99721	601	* @}
bogdanm	85:024bf7f99721	602	*/
bogdanm	85:024bf7f99721	603
bogdanm	92:4fc01daae5a5	604	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
bogdanm	85:024bf7f99721	605	* @{
bogdanm	85:024bf7f99721	606	*/
bogdanm	85:024bf7f99721	607	#define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm	85:024bf7f99721	608	#define RCC_HSI48_ON ((uint8_t)0x01)
bogdanm	85:024bf7f99721	609
bogdanm	85:024bf7f99721	610	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) \|\| ((HSI48) == RCC_HSI48_ON))
bogdanm	85:024bf7f99721	611	/**
bogdanm	85:024bf7f99721	612	* @}
bogdanm	85:024bf7f99721	613	*/
bogdanm	85:024bf7f99721	614	#else
bogdanm	92:4fc01daae5a5	615	/** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
bogdanm	85:024bf7f99721	616	* @{
bogdanm	85:024bf7f99721	617	*/
Kojto	93:e188a91d3eaa	618
Kojto	93:e188a91d3eaa	619	#if defined(STM32F070xB) \|\| defined(STM32F070x6) \|\| defined(STM32F030xC)
Kojto	93:e188a91d3eaa	620	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	93:e188a91d3eaa	621	#else
bogdanm	85:024bf7f99721	622	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto	93:e188a91d3eaa	623	#endif
bogdanm	85:024bf7f99721	624
bogdanm	85:024bf7f99721	625	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	626	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	85:024bf7f99721	627	/**
bogdanm	85:024bf7f99721	628	* @}
bogdanm	85:024bf7f99721	629	*/
bogdanm	92:4fc01daae5a5	630
bogdanm	92:4fc01daae5a5	631	/** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
bogdanm	85:024bf7f99721	632	* @{
bogdanm	85:024bf7f99721	633	*/
bogdanm	85:024bf7f99721	634	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
bogdanm	85:024bf7f99721	635	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
bogdanm	85:024bf7f99721	636	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
bogdanm	85:024bf7f99721	637
bogdanm	85:024bf7f99721	638	#define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) \|\| \
bogdanm	85:024bf7f99721	639	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) \|\| \
bogdanm	85:024bf7f99721	640	((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
bogdanm	85:024bf7f99721	641	/**
bogdanm	85:024bf7f99721	642	* @}
bogdanm	85:024bf7f99721	643	*/
bogdanm	85:024bf7f99721	644
bogdanm	92:4fc01daae5a5	645	/** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
bogdanm	85:024bf7f99721	646	* @{
bogdanm	85:024bf7f99721	647	*/
bogdanm	85:024bf7f99721	648	#define RCC_HSI48_OFF ((uint8_t)0x00)
bogdanm	85:024bf7f99721	649
bogdanm	85:024bf7f99721	650	#define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
bogdanm	85:024bf7f99721	651	/**
bogdanm	85:024bf7f99721	652	* @}
bogdanm	85:024bf7f99721	653	*/
bogdanm	85:024bf7f99721	654
bogdanm	92:4fc01daae5a5	655	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	656	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	657	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	658
bogdanm	85:024bf7f99721	659
bogdanm	92:4fc01daae5a5	660	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
bogdanm	92:4fc01daae5a5	661	* @{
bogdanm	92:4fc01daae5a5	662	*/
bogdanm	92:4fc01daae5a5	663
bogdanm	85:024bf7f99721	664	#if defined(STM32F030x8) \|\| defined(STM32F051x8) \|\| defined(STM32F058xx)
bogdanm	85:024bf7f99721	665
bogdanm	85:024bf7f99721	666	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	667
bogdanm	85:024bf7f99721	668	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
bogdanm	85:024bf7f99721	669
bogdanm	85:024bf7f99721	670	#endif /* STM32F030x8 \|\| STM32F051x8 \|\| STM32F058xx */
bogdanm	85:024bf7f99721	671
Kojto	93:e188a91d3eaa	672	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| defined(STM32F070x6) \|\| \
Kojto	93:e188a91d3eaa	673	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F071xB) \|\| defined(STM32F070xB) \|\| \
bogdanm	92:4fc01daae5a5	674	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	93:e188a91d3eaa	675	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	676
bogdanm	85:024bf7f99721	677	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
bogdanm	85:024bf7f99721	678	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
bogdanm	85:024bf7f99721	679	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
bogdanm	85:024bf7f99721	680	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
bogdanm	85:024bf7f99721	681	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
bogdanm	85:024bf7f99721	682	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
bogdanm	85:024bf7f99721	683	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
bogdanm	85:024bf7f99721	684	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
bogdanm	85:024bf7f99721	685
bogdanm	85:024bf7f99721	686	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
bogdanm	85:024bf7f99721	687	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
bogdanm	85:024bf7f99721	688	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
bogdanm	85:024bf7f99721	689	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
bogdanm	92:4fc01daae5a5	690
bogdanm	92:4fc01daae5a5	691	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	692	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070x6 \|\| STM32F070xB */
Kojto	93:e188a91d3eaa	693	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	92:4fc01daae5a5	694
bogdanm	85:024bf7f99721	695	/**
bogdanm	85:024bf7f99721	696	* @}
bogdanm	85:024bf7f99721	697	*/
bogdanm	85:024bf7f99721	698
bogdanm	92:4fc01daae5a5	699	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	700	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	701	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	702
bogdanm	92:4fc01daae5a5	703	/** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
bogdanm	85:024bf7f99721	704	* @{
bogdanm	85:024bf7f99721	705	*/
bogdanm	85:024bf7f99721	706	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal soucre GPIO /
bogdanm	85:024bf7f99721	707	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
bogdanm	85:024bf7f99721	708	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
bogdanm	85:024bf7f99721	709
bogdanm	85:024bf7f99721	710	#define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
bogdanm	92:4fc01daae5a5	711	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) \|\| \
bogdanm	92:4fc01daae5a5	712	((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
bogdanm	85:024bf7f99721	713	/**
bogdanm	85:024bf7f99721	714	* @}
bogdanm	85:024bf7f99721	715	*/
bogdanm	85:024bf7f99721	716
bogdanm	92:4fc01daae5a5	717	/** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
bogdanm	85:024bf7f99721	718	* @{
bogdanm	85:024bf7f99721	719	*/
bogdanm	85:024bf7f99721	720	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
bogdanm	85:024bf7f99721	721	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	85:024bf7f99721	722	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	85:024bf7f99721	723	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	85:024bf7f99721	724	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	85:024bf7f99721	725	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	85:024bf7f99721	726	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	85:024bf7f99721	727	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	85:024bf7f99721	728
bogdanm	92:4fc01daae5a5	729	#define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	730	((_DIV_) == RCC_CRS_SYNC_DIV4) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV8) \|\| \
bogdanm	92:4fc01daae5a5	731	((_DIV_) == RCC_CRS_SYNC_DIV16) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV32) \|\| \
bogdanm	92:4fc01daae5a5	732	((_DIV_) == RCC_CRS_SYNC_DIV64) \|\| ((_DIV_) == RCC_CRS_SYNC_DIV128))
bogdanm	85:024bf7f99721	733	/**
bogdanm	85:024bf7f99721	734	* @}
bogdanm	85:024bf7f99721	735	*/
bogdanm	85:024bf7f99721	736
bogdanm	92:4fc01daae5a5	737	/** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
bogdanm	85:024bf7f99721	738	* @{
bogdanm	85:024bf7f99721	739	*/
bogdanm	85:024bf7f99721	740	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
bogdanm	85:024bf7f99721	741	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	85:024bf7f99721	742
bogdanm	85:024bf7f99721	743	#define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
bogdanm	92:4fc01daae5a5	744	((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
bogdanm	85:024bf7f99721	745	/**
bogdanm	85:024bf7f99721	746	* @}
bogdanm	85:024bf7f99721	747	*/
bogdanm	85:024bf7f99721	748
bogdanm	92:4fc01daae5a5	749	/** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
bogdanm	85:024bf7f99721	750	* @{
bogdanm	85:024bf7f99721	751	*/
bogdanm	85:024bf7f99721	752	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm	92:4fc01daae5a5	753	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	92:4fc01daae5a5	754
bogdanm	85:024bf7f99721	755	#define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
bogdanm	85:024bf7f99721	756	/**
bogdanm	85:024bf7f99721	757	* @}
bogdanm	85:024bf7f99721	758	*/
bogdanm	85:024bf7f99721	759
bogdanm	92:4fc01daae5a5	760	/** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
bogdanm	85:024bf7f99721	761	* @{
bogdanm	85:024bf7f99721	762	*/
bogdanm	85:024bf7f99721	763	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
bogdanm	85:024bf7f99721	764
bogdanm	85:024bf7f99721	765	#define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
bogdanm	85:024bf7f99721	766	/**
bogdanm	85:024bf7f99721	767	* @}
bogdanm	85:024bf7f99721	768	*/
bogdanm	85:024bf7f99721	769
bogdanm	92:4fc01daae5a5	770	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
bogdanm	85:024bf7f99721	771	* @{
bogdanm	85:024bf7f99721	772	*/
bogdanm	92:4fc01daae5a5	773	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm	92:4fc01daae5a5	774	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm	92:4fc01daae5a5	775	corresponds to a higher output frequency */
bogdanm	85:024bf7f99721	776
bogdanm	85:024bf7f99721	777	#define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
bogdanm	85:024bf7f99721	778	/**
bogdanm	85:024bf7f99721	779	* @}
bogdanm	85:024bf7f99721	780	*/
bogdanm	85:024bf7f99721	781
bogdanm	92:4fc01daae5a5	782	/** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
bogdanm	85:024bf7f99721	783	* @{
bogdanm	85:024bf7f99721	784	*/
bogdanm	85:024bf7f99721	785	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
bogdanm	85:024bf7f99721	786	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	85:024bf7f99721	787
bogdanm	85:024bf7f99721	788	#define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) \|\| \
bogdanm	92:4fc01daae5a5	789	((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
bogdanm	85:024bf7f99721	790	/**
bogdanm	85:024bf7f99721	791	* @}
bogdanm	85:024bf7f99721	792	*/
bogdanm	85:024bf7f99721	793
bogdanm	92:4fc01daae5a5	794	/** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
bogdanm	85:024bf7f99721	795	* @{
bogdanm	85:024bf7f99721	796	*/
bogdanm	85:024bf7f99721	797	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
bogdanm	85:024bf7f99721	798	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
bogdanm	85:024bf7f99721	799	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
bogdanm	85:024bf7f99721	800	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
bogdanm	85:024bf7f99721	801	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	85:024bf7f99721	802	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	85:024bf7f99721	803	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	85:024bf7f99721	804
bogdanm	85:024bf7f99721	805	/**
bogdanm	85:024bf7f99721	806	* @}
bogdanm	85:024bf7f99721	807	*/
bogdanm	85:024bf7f99721	808
bogdanm	92:4fc01daae5a5	809	/** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
bogdanm	85:024bf7f99721	810	* @{
bogdanm	85:024bf7f99721	811	*/
bogdanm	85:024bf7f99721	812	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm	85:024bf7f99721	813	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm	85:024bf7f99721	814	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm	85:024bf7f99721	815	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm	85:024bf7f99721	816	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	85:024bf7f99721	817	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	85:024bf7f99721	818	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	85:024bf7f99721	819
bogdanm	85:024bf7f99721	820	/**
bogdanm	85:024bf7f99721	821	* @}
bogdanm	85:024bf7f99721	822	*/
bogdanm	85:024bf7f99721	823
Kojto	93:e188a91d3eaa	824	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	825	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	93:e188a91d3eaa	826	/* STM32F091xC \|\| STM32F098xx */
Kojto	93:e188a91d3eaa	827
bogdanm	85:024bf7f99721	828	/**
bogdanm	85:024bf7f99721	829	* @}
bogdanm	85:024bf7f99721	830	*/
bogdanm	85:024bf7f99721	831
bogdanm	92:4fc01daae5a5	832	/* Exported macros ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	833	/** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
bogdanm	85:024bf7f99721	834	* @{
bogdanm	85:024bf7f99721	835	*/
bogdanm	85:024bf7f99721	836
bogdanm	92:4fc01daae5a5	837	/** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
bogdanm	92:4fc01daae5a5	838	* @brief Enables or disables the AHB1 peripheral clock.
bogdanm	85:024bf7f99721	839	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	840	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	841	* using it.
bogdanm	92:4fc01daae5a5	842	* @{
bogdanm	85:024bf7f99721	843	*/
Kojto	93:e188a91d3eaa	844	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
Kojto	93:e188a91d3eaa	845	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| defined(STM32F070xB) \|\| \
bogdanm	92:4fc01daae5a5	846	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	93:e188a91d3eaa	847	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	848
bogdanm	85:024bf7f99721	849	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
bogdanm	85:024bf7f99721	850
bogdanm	85:024bf7f99721	851	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
bogdanm	85:024bf7f99721	852
Kojto	93:e188a91d3eaa	853	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
Kojto	93:e188a91d3eaa	854	/* STM32F051x8 \|\| STM32F058xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	855	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
Kojto	93:e188a91d3eaa	856	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	857
Kojto	93:e188a91d3eaa	858	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	859	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	860
bogdanm	85:024bf7f99721	861	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
bogdanm	85:024bf7f99721	862
bogdanm	85:024bf7f99721	863	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm	85:024bf7f99721	864
Kojto	93:e188a91d3eaa	865	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	866	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	867
bogdanm	92:4fc01daae5a5	868	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	869	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	870	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	871	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	872
bogdanm	85:024bf7f99721	873	#define __TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
bogdanm	85:024bf7f99721	874
bogdanm	85:024bf7f99721	875	#define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
bogdanm	85:024bf7f99721	876
bogdanm	92:4fc01daae5a5	877	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	878	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	879	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	880	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	881
bogdanm	92:4fc01daae5a5	882	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	883
bogdanm	92:4fc01daae5a5	884	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
bogdanm	92:4fc01daae5a5	885
bogdanm	92:4fc01daae5a5	886	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm	92:4fc01daae5a5	887
bogdanm	92:4fc01daae5a5	888	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	889
bogdanm	85:024bf7f99721	890	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	85:024bf7f99721	891	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	892	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	893	* using it.
bogdanm	85:024bf7f99721	894	*/
bogdanm	85:024bf7f99721	895	#if defined(STM32F030x8) \|\| \
bogdanm	92:4fc01daae5a5	896	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	897	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	93:e188a91d3eaa	898	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	899	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	900
bogdanm	85:024bf7f99721	901	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
bogdanm	85:024bf7f99721	902	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	85:024bf7f99721	903
bogdanm	85:024bf7f99721	904	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
bogdanm	85:024bf7f99721	905	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	85:024bf7f99721	906
bogdanm	92:4fc01daae5a5	907	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	908	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	909	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	910	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	911
bogdanm	85:024bf7f99721	912	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
bogdanm	92:4fc01daae5a5	913	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	914	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	915	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	916	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	917
bogdanm	85:024bf7f99721	918	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
bogdanm	85:024bf7f99721	919
bogdanm	85:024bf7f99721	920	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
bogdanm	85:024bf7f99721	921
bogdanm	92:4fc01daae5a5	922	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	92:4fc01daae5a5	923	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	924	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	925	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	926	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	927
bogdanm	85:024bf7f99721	928	#if defined(STM32F030x8) \|\| \
bogdanm	85:024bf7f99721	929	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	93:e188a91d3eaa	930	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	931	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	932
bogdanm	85:024bf7f99721	933	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
bogdanm	85:024bf7f99721	934	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	85:024bf7f99721	935
bogdanm	85:024bf7f99721	936	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
bogdanm	85:024bf7f99721	937	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	85:024bf7f99721	938
bogdanm	85:024bf7f99721	939	#endif /* STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	940	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	941	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	942	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	943
bogdanm	85:024bf7f99721	944	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	945	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	946	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	947
bogdanm	85:024bf7f99721	948	#define __DAC1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
bogdanm	85:024bf7f99721	949
bogdanm	85:024bf7f99721	950	#define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
bogdanm	85:024bf7f99721	951
bogdanm	85:024bf7f99721	952	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	953	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	954	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	955
bogdanm	92:4fc01daae5a5	956	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	957	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	958	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	959	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	960
bogdanm	85:024bf7f99721	961	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
bogdanm	85:024bf7f99721	962
bogdanm	85:024bf7f99721	963	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm	85:024bf7f99721	964
bogdanm	92:4fc01daae5a5	965	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	966	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	967	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	968	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	969
Kojto	93:e188a91d3eaa	970	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	971	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	972
bogdanm	85:024bf7f99721	973	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
bogdanm	85:024bf7f99721	974	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
bogdanm	85:024bf7f99721	975	#define __USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
bogdanm	85:024bf7f99721	976
bogdanm	85:024bf7f99721	977	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	85:024bf7f99721	978	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
bogdanm	85:024bf7f99721	979	#define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
bogdanm	85:024bf7f99721	980
Kojto	93:e188a91d3eaa	981	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	982	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	983
Kojto	93:e188a91d3eaa	984	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
Kojto	93:e188a91d3eaa	985	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	986
bogdanm	85:024bf7f99721	987	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
bogdanm	85:024bf7f99721	988
bogdanm	85:024bf7f99721	989	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm	85:024bf7f99721	990
Kojto	93:e188a91d3eaa	991	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	93:e188a91d3eaa	992	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	85:024bf7f99721	993
bogdanm	92:4fc01daae5a5	994	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
bogdanm	92:4fc01daae5a5	995	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	996
bogdanm	85:024bf7f99721	997	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
bogdanm	85:024bf7f99721	998	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm	85:024bf7f99721	999
bogdanm	92:4fc01daae5a5	1000	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	92:4fc01daae5a5	1001	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1002
bogdanm	92:4fc01daae5a5	1003	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	1004	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1005	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1006
bogdanm	85:024bf7f99721	1007	#define __CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
bogdanm	85:024bf7f99721	1008
bogdanm	85:024bf7f99721	1009	#define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
bogdanm	85:024bf7f99721	1010
bogdanm	92:4fc01daae5a5	1011	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1012	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1013	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1014
Kojto	93:e188a91d3eaa	1015	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	92:4fc01daae5a5	1016
bogdanm	92:4fc01daae5a5	1017	#define __USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
bogdanm	92:4fc01daae5a5	1018
bogdanm	92:4fc01daae5a5	1019	#define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
bogdanm	92:4fc01daae5a5	1020
Kojto	93:e188a91d3eaa	1021	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1022
bogdanm	85:024bf7f99721	1023	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	85:024bf7f99721	1024	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	85:024bf7f99721	1025	* is disabled and the application software has to enable this clock before
bogdanm	85:024bf7f99721	1026	* using it.
bogdanm	85:024bf7f99721	1027	*/
Kojto	93:e188a91d3eaa	1028	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
bogdanm	85:024bf7f99721	1029	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	93:e188a91d3eaa	1030	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	1031	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1032
bogdanm	85:024bf7f99721	1033	#define __TIM15_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM15EN))
bogdanm	85:024bf7f99721	1034
bogdanm	85:024bf7f99721	1035	#define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
bogdanm	85:024bf7f99721	1036
Kojto	93:e188a91d3eaa	1037	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1038	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1039	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1040	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	93:e188a91d3eaa	1041
Kojto	93:e188a91d3eaa	1042	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	93:e188a91d3eaa	1043
Kojto	93:e188a91d3eaa	1044	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
Kojto	93:e188a91d3eaa	1045
Kojto	93:e188a91d3eaa	1046	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto	93:e188a91d3eaa	1047
Kojto	93:e188a91d3eaa	1048	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	92:4fc01daae5a5	1049
bogdanm	92:4fc01daae5a5	1050	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1051
bogdanm	92:4fc01daae5a5	1052	#define __USART7_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART7EN))
bogdanm	92:4fc01daae5a5	1053	#define __USART8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART8EN))
bogdanm	92:4fc01daae5a5	1054
bogdanm	92:4fc01daae5a5	1055	#define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
bogdanm	92:4fc01daae5a5	1056	#define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
bogdanm	92:4fc01daae5a5	1057
bogdanm	92:4fc01daae5a5	1058	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1059
bogdanm	92:4fc01daae5a5	1060	/**
bogdanm	92:4fc01daae5a5	1061	* @}
bogdanm	92:4fc01daae5a5	1062	*/
bogdanm	92:4fc01daae5a5	1063
bogdanm	92:4fc01daae5a5	1064
bogdanm	92:4fc01daae5a5	1065	/** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
bogdanm	92:4fc01daae5a5	1066	* @brief Forces or releases peripheral reset.
bogdanm	92:4fc01daae5a5	1067	* @{
bogdanm	92:4fc01daae5a5	1068	*/
bogdanm	85:024bf7f99721	1069
bogdanm	85:024bf7f99721	1070	/** @brief Force or release AHB peripheral reset.
bogdanm	85:024bf7f99721	1071	*/
Kojto	93:e188a91d3eaa	1072	#if defined(STM32F030x6) \|\| defined(STM32F030x8) \|\| \
Kojto	93:e188a91d3eaa	1073	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	93:e188a91d3eaa	1074	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	1075	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1076
bogdanm	85:024bf7f99721	1077	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
bogdanm	85:024bf7f99721	1078
bogdanm	85:024bf7f99721	1079	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
bogdanm	85:024bf7f99721	1080
bogdanm	85:024bf7f99721	1081	#endif /* STM32F030x6 \|\| STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	1082	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1083	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1084	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1085
Kojto	93:e188a91d3eaa	1086	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	1087	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1088
bogdanm	85:024bf7f99721	1089	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
bogdanm	85:024bf7f99721	1090
bogdanm	85:024bf7f99721	1091	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm	85:024bf7f99721	1092
Kojto	93:e188a91d3eaa	1093	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1094	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1095
bogdanm	92:4fc01daae5a5	1096	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1097	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	1098	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1099	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1100
bogdanm	85:024bf7f99721	1101	#define __TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
bogdanm	85:024bf7f99721	1102
bogdanm	85:024bf7f99721	1103	#define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
bogdanm	85:024bf7f99721	1104
bogdanm	92:4fc01daae5a5	1105	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1106	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1107	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1108	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1109
bogdanm	85:024bf7f99721	1110	/** @brief Force or release APB1 peripheral reset.
bogdanm	85:024bf7f99721	1111	*/
bogdanm	85:024bf7f99721	1112	#if defined(STM32F030x8) \|\| \
Kojto	93:e188a91d3eaa	1113	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
bogdanm	85:024bf7f99721	1114	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	93:e188a91d3eaa	1115	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	1116	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1117
bogdanm	85:024bf7f99721	1118	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
bogdanm	85:024bf7f99721	1119	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	85:024bf7f99721	1120
bogdanm	85:024bf7f99721	1121	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
bogdanm	85:024bf7f99721	1122	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	85:024bf7f99721	1123
Kojto	93:e188a91d3eaa	1124	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1125	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1126	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1127	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1128
bogdanm	85:024bf7f99721	1129	#if defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
bogdanm	92:4fc01daae5a5	1130	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1131	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	1132	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1133	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1134
bogdanm	85:024bf7f99721	1135	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
bogdanm	85:024bf7f99721	1136
bogdanm	85:024bf7f99721	1137	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
bogdanm	85:024bf7f99721	1138
bogdanm	92:4fc01daae5a5	1139	#endif /* STM32F031x6 \|\| STM32F038xx \|\| */
bogdanm	92:4fc01daae5a5	1140	/* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1141	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1142	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1143	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1144
bogdanm	85:024bf7f99721	1145	#if defined(STM32F030x8) \|\| \
bogdanm	85:024bf7f99721	1146	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	93:e188a91d3eaa	1147	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\|\
Kojto	93:e188a91d3eaa	1148	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1149
bogdanm	85:024bf7f99721	1150	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
bogdanm	85:024bf7f99721	1151	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	85:024bf7f99721	1152
bogdanm	85:024bf7f99721	1153	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
bogdanm	85:024bf7f99721	1154	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	85:024bf7f99721	1155
bogdanm	85:024bf7f99721	1156	#endif /* STM32F030x8 \|\| */
bogdanm	85:024bf7f99721	1157	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1158	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1159	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1160
bogdanm	85:024bf7f99721	1161	#if defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	1162	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1163	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1164
bogdanm	85:024bf7f99721	1165	#define __DAC1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	85:024bf7f99721	1166
bogdanm	85:024bf7f99721	1167	#define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
bogdanm	85:024bf7f99721	1168
bogdanm	85:024bf7f99721	1169	#endif /* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1170	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1171	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1172
bogdanm	92:4fc01daae5a5	1173	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1174	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	1175	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1176	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1177
bogdanm	85:024bf7f99721	1178	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
bogdanm	85:024bf7f99721	1179
bogdanm	85:024bf7f99721	1180	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm	85:024bf7f99721	1181
bogdanm	92:4fc01daae5a5	1182	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1183	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1184	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1185	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1186
Kojto	93:e188a91d3eaa	1187	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	1188	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1189
bogdanm	85:024bf7f99721	1190	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	85:024bf7f99721	1191	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
bogdanm	85:024bf7f99721	1192	#define __USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
bogdanm	85:024bf7f99721	1193
bogdanm	85:024bf7f99721	1194	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	85:024bf7f99721	1195	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
bogdanm	85:024bf7f99721	1196	#define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
bogdanm	85:024bf7f99721	1197
Kojto	93:e188a91d3eaa	1198	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1199	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1200
Kojto	93:e188a91d3eaa	1201	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
Kojto	93:e188a91d3eaa	1202	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	1203
bogdanm	85:024bf7f99721	1204	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
bogdanm	85:024bf7f99721	1205
bogdanm	85:024bf7f99721	1206	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm	85:024bf7f99721	1207
Kojto	93:e188a91d3eaa	1208	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
Kojto	93:e188a91d3eaa	1209	/* STM32F072xB \|\| STM32F078xx \|\| STM32F070xB */
bogdanm	85:024bf7f99721	1210
bogdanm	92:4fc01daae5a5	1211	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F072xB) \|\| \
bogdanm	92:4fc01daae5a5	1212	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1213
bogdanm	85:024bf7f99721	1214	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
bogdanm	85:024bf7f99721	1215
bogdanm	85:024bf7f99721	1216	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm	85:024bf7f99721	1217
bogdanm	92:4fc01daae5a5	1218	#endif /* STM32F042x6 \|\| STM32F048xx \|\| STM32F072xB \|\| */
bogdanm	92:4fc01daae5a5	1219	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1220
bogdanm	92:4fc01daae5a5	1221	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	1222	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1223	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1224
bogdanm	85:024bf7f99721	1225	#define __CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
bogdanm	85:024bf7f99721	1226
bogdanm	85:024bf7f99721	1227	#define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
bogdanm	85:024bf7f99721	1228
bogdanm	92:4fc01daae5a5	1229	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1230	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1231	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1232
Kojto	93:e188a91d3eaa	1233	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	92:4fc01daae5a5	1234
bogdanm	92:4fc01daae5a5	1235	#define __USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
bogdanm	92:4fc01daae5a5	1236
bogdanm	92:4fc01daae5a5	1237	#define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
bogdanm	92:4fc01daae5a5	1238
Kojto	93:e188a91d3eaa	1239	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	85:024bf7f99721	1240
bogdanm	85:024bf7f99721	1241
bogdanm	85:024bf7f99721	1242	/** @brief Force or release APB2 peripheral reset.
bogdanm	85:024bf7f99721	1243	*/
Kojto	93:e188a91d3eaa	1244	#if defined(STM32F030x8) \|\| defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
bogdanm	85:024bf7f99721	1245	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
Kojto	93:e188a91d3eaa	1246	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	1247	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1248
bogdanm	85:024bf7f99721	1249	#define __TIM15_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM15RST))
bogdanm	85:024bf7f99721	1250
bogdanm	85:024bf7f99721	1251	#define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
bogdanm	85:024bf7f99721	1252
Kojto	93:e188a91d3eaa	1253	#endif /* STM32F030x8 \|\| STM32F042x6 \|\| STM32F048xx \|\| STM32F070x6 \|\| */
bogdanm	85:024bf7f99721	1254	/* STM32F051x8 \|\| STM32F058xx \|\| */
Kojto	93:e188a91d3eaa	1255	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1256	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	93:e188a91d3eaa	1257
Kojto	93:e188a91d3eaa	1258	#if defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
Kojto	93:e188a91d3eaa	1259
Kojto	93:e188a91d3eaa	1260	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
Kojto	93:e188a91d3eaa	1261
Kojto	93:e188a91d3eaa	1262	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto	93:e188a91d3eaa	1263
Kojto	93:e188a91d3eaa	1264	#endif /* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
bogdanm	92:4fc01daae5a5	1265
bogdanm	92:4fc01daae5a5	1266	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1267
bogdanm	92:4fc01daae5a5	1268	#define __USART7_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART7RST))
bogdanm	92:4fc01daae5a5	1269	#define __USART8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART8RST))
bogdanm	85:024bf7f99721	1270
bogdanm	92:4fc01daae5a5	1271	#define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
bogdanm	92:4fc01daae5a5	1272	#define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
bogdanm	92:4fc01daae5a5	1273
bogdanm	92:4fc01daae5a5	1274	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1275
bogdanm	92:4fc01daae5a5	1276	/**
bogdanm	92:4fc01daae5a5	1277	* @}
bogdanm	92:4fc01daae5a5	1278	*/
bogdanm	92:4fc01daae5a5	1279
bogdanm	92:4fc01daae5a5	1280	/** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
bogdanm	92:4fc01daae5a5	1281	* @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
bogdanm	85:024bf7f99721	1282	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
bogdanm	85:024bf7f99721	1283	* @note HSI48 can not be stopped if it is used as system clock source. In this case,
bogdanm	85:024bf7f99721	1284	* you have to select another source of the system clock then stop the HSI14.
bogdanm	85:024bf7f99721	1285	* @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
bogdanm	85:024bf7f99721	1286	* should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
bogdanm	85:024bf7f99721	1287	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
bogdanm	85:024bf7f99721	1288	* @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
bogdanm	85:024bf7f99721	1289	* clock cycles.
bogdanm	92:4fc01daae5a5	1290	* @{
bogdanm	85:024bf7f99721	1291	*/
bogdanm	92:4fc01daae5a5	1292	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	1293	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1294	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1295
bogdanm	85:024bf7f99721	1296	#define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	85:024bf7f99721	1297	#define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
bogdanm	85:024bf7f99721	1298
bogdanm	85:024bf7f99721	1299	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	85:024bf7f99721	1300	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1301	* @arg RCC_HSI48_ON: HSI48 enabled
bogdanm	85:024bf7f99721	1302	* @arg RCC_HSI48_OFF: HSI48 disabled
bogdanm	85:024bf7f99721	1303	*/
bogdanm	85:024bf7f99721	1304	#define __HAL_RCC_GET_HSI48_STATE() \
bogdanm	85:024bf7f99721	1305	(((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
bogdanm	85:024bf7f99721	1306
bogdanm	85:024bf7f99721	1307	#else
bogdanm	85:024bf7f99721	1308
bogdanm	85:024bf7f99721	1309	/** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
bogdanm	85:024bf7f99721	1310	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1311	* @arg RCC_HSI_OFF: HSI48 disabled
bogdanm	85:024bf7f99721	1312	*/
bogdanm	85:024bf7f99721	1313	#define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
bogdanm	85:024bf7f99721	1314
bogdanm	92:4fc01daae5a5	1315	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1316	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1317	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1318
bogdanm	92:4fc01daae5a5	1319	/**
bogdanm	92:4fc01daae5a5	1320	* @}
bogdanm	92:4fc01daae5a5	1321	*/
bogdanm	92:4fc01daae5a5	1322
bogdanm	92:4fc01daae5a5	1323	/** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
bogdanm	92:4fc01daae5a5	1324	* @{
bogdanm	92:4fc01daae5a5	1325	*/
Kojto	93:e188a91d3eaa	1326	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
Kojto	93:e188a91d3eaa	1327	defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	93:e188a91d3eaa	1328	defined(STM32F070x6) \|\| defined(STM32F070xB)
bogdanm	85:024bf7f99721	1329
bogdanm	85:024bf7f99721	1330	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	85:024bf7f99721	1331	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	85:024bf7f99721	1332	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	1333	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
bogdanm	85:024bf7f99721	1334	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	85:024bf7f99721	1335	*/
bogdanm	85:024bf7f99721	1336	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	85:024bf7f99721	1337	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
bogdanm	85:024bf7f99721	1338
bogdanm	85:024bf7f99721	1339	/** @brief Macro to get the USB clock source.
bogdanm	85:024bf7f99721	1340	* @retval The clock source can be one of the following values:
Kojto	93:e188a91d3eaa	1341	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
bogdanm	85:024bf7f99721	1342	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	85:024bf7f99721	1343	*/
bogdanm	85:024bf7f99721	1344	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
bogdanm	85:024bf7f99721	1345
bogdanm	92:4fc01daae5a5	1346	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	1347	/* STM32F072xB \|\| STM32F078xx \|\| */
Kojto	93:e188a91d3eaa	1348	/* STM32F070x6 \|\| STM32F070xB */
bogdanm	85:024bf7f99721	1349
bogdanm	92:4fc01daae5a5	1350	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	85:024bf7f99721	1351	defined(STM32F051x8) \|\| defined(STM32F058xx) \|\| \
bogdanm	92:4fc01daae5a5	1352	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1353	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1354
bogdanm	85:024bf7f99721	1355	/** @brief Macro to configure the CEC clock.
bogdanm	85:024bf7f99721	1356	* @param __CECCLKSource__: specifies the CEC clock source.
bogdanm	85:024bf7f99721	1357	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1358	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	85:024bf7f99721	1359	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	85:024bf7f99721	1360	*/
bogdanm	85:024bf7f99721	1361	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
bogdanm	85:024bf7f99721	1362	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
bogdanm	85:024bf7f99721	1363
bogdanm	85:024bf7f99721	1364	/** @brief Macro to get the HDMI CEC clock source.
bogdanm	85:024bf7f99721	1365	* @retval The clock source can be one of the following values:
bogdanm	85:024bf7f99721	1366	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	85:024bf7f99721	1367	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	85:024bf7f99721	1368	*/
bogdanm	85:024bf7f99721	1369	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm	85:024bf7f99721	1370
bogdanm	92:4fc01daae5a5	1371	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	85:024bf7f99721	1372	/* STM32F051x8 \|\| STM32F058xx \|\| */
bogdanm	92:4fc01daae5a5	1373	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1374	/* STM32F091xC \|\| defined(STM32F098xx) */
bogdanm	85:024bf7f99721	1375
bogdanm	85:024bf7f99721	1376	#if defined(STM32F030x6) \|\| defined(STM32F031x6) \|\| defined(STM32F038xx) \|\| \
Kojto	93:e188a91d3eaa	1377	defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| defined(STM32F070x6) \|\| \
Kojto	93:e188a91d3eaa	1378	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| defined(STM32F070xB) \|\| \
Kojto	93:e188a91d3eaa	1379	defined(STM32F091xC) \|\| defined(STM32F098xx) \|\| defined(STM32F030xC)
bogdanm	85:024bf7f99721	1380
bogdanm	85:024bf7f99721	1381	/** @brief Macro to configure the MCO clock.
bogdanm	85:024bf7f99721	1382	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	85:024bf7f99721	1383	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1384	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	85:024bf7f99721	1385	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	85:024bf7f99721	1386	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	85:024bf7f99721	1387	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	85:024bf7f99721	1388	* @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
bogdanm	85:024bf7f99721	1389	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	85:024bf7f99721	1390	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	85:024bf7f99721	1391	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm	85:024bf7f99721	1392	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm	85:024bf7f99721	1393	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	85:024bf7f99721	1394	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1395	* @arg RCC_MCO_DIV1: MCO clock source is divided by 1
bogdanm	85:024bf7f99721	1396	* @arg RCC_MCO_DIV2: MCO clock source is divided by 2
bogdanm	85:024bf7f99721	1397	* @arg RCC_MCO_DIV4: MCO clock source is divided by 4
bogdanm	85:024bf7f99721	1398	* @arg RCC_MCO_DIV8: MCO clock source is divided by 8
bogdanm	85:024bf7f99721	1399	* @arg RCC_MCO_DIV16: MCO clock source is divided by 16
bogdanm	85:024bf7f99721	1400	* @arg RCC_MCO_DIV32: MCO clock source is divided by 32
bogdanm	85:024bf7f99721	1401	* @arg RCC_MCO_DIV64: MCO clock source is divided by 64
bogdanm	85:024bf7f99721	1402	* @arg RCC_MCO_DIV128: MCO clock source is divided by 128
bogdanm	85:024bf7f99721	1403	*/
bogdanm	85:024bf7f99721	1404	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	85:024bf7f99721	1405	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
bogdanm	85:024bf7f99721	1406	#else
bogdanm	85:024bf7f99721	1407
bogdanm	85:024bf7f99721	1408	/** @brief Macro to configure the MCO clock.
bogdanm	85:024bf7f99721	1409	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	85:024bf7f99721	1410	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1411	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	85:024bf7f99721	1412	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	85:024bf7f99721	1413	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	85:024bf7f99721	1414	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	85:024bf7f99721	1415	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	85:024bf7f99721	1416	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	85:024bf7f99721	1417	* @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
bogdanm	85:024bf7f99721	1418	* @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
bogdanm	85:024bf7f99721	1419	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	85:024bf7f99721	1420	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1421	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
bogdanm	85:024bf7f99721	1422	*/
bogdanm	85:024bf7f99721	1423	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	85:024bf7f99721	1424	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
bogdanm	85:024bf7f99721	1425
Kojto	93:e188a91d3eaa	1426	#endif /* STM32F030x6 \|\| STM32F031x6 \|\| STM32F038xx \|\| STM32F070x6 \|\| */
Kojto	93:e188a91d3eaa	1427	/* STM32F042x6 \|\| STM32F048xx \|\| */
Kojto	93:e188a91d3eaa	1428	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F070xB \|\| */
Kojto	93:e188a91d3eaa	1429	/* STM32F091xC \|\| STM32F098xx \|\| STM32F030xC */
Kojto	93:e188a91d3eaa	1430
Kojto	93:e188a91d3eaa	1431	#if defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
Kojto	93:e188a91d3eaa	1432	defined(STM32F091xC) \|\| defined(STM32F098xx)
Kojto	93:e188a91d3eaa	1433	/** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto	93:e188a91d3eaa	1434	* @param __USART2CLKSource__: specifies the USART2 clock source.
Kojto	93:e188a91d3eaa	1435	* This parameter can be one of the following values:
Kojto	93:e188a91d3eaa	1436	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	93:e188a91d3eaa	1437	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	93:e188a91d3eaa	1438	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	93:e188a91d3eaa	1439	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	93:e188a91d3eaa	1440	*/
Kojto	93:e188a91d3eaa	1441	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
Kojto	93:e188a91d3eaa	1442	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
Kojto	93:e188a91d3eaa	1443
Kojto	93:e188a91d3eaa	1444	/** @brief Macro to get the USART2 clock source.
Kojto	93:e188a91d3eaa	1445	* @retval The clock source can be one of the following values:
Kojto	93:e188a91d3eaa	1446	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto	93:e188a91d3eaa	1447	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto	93:e188a91d3eaa	1448	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto	93:e188a91d3eaa	1449	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto	93:e188a91d3eaa	1450	*/
Kojto	93:e188a91d3eaa	1451	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto	93:e188a91d3eaa	1452	#endif /* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| STM32F091xC \|\| STM32F098xx*/
bogdanm	92:4fc01daae5a5	1453
bogdanm	92:4fc01daae5a5	1454	#if defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1455	/** @brief Macro to configure the USART3 clock (USART3CLK).
bogdanm	92:4fc01daae5a5	1456	* @param __USART3CLKSource__: specifies the USART3 clock source.
bogdanm	92:4fc01daae5a5	1457	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	1458	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	92:4fc01daae5a5	1459	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	92:4fc01daae5a5	1460	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	92:4fc01daae5a5	1461	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	92:4fc01daae5a5	1462	*/
bogdanm	92:4fc01daae5a5	1463	#define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
bogdanm	92:4fc01daae5a5	1464	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
bogdanm	85:024bf7f99721	1465
bogdanm	92:4fc01daae5a5	1466	/** @brief Macro to get the USART3 clock source.
bogdanm	92:4fc01daae5a5	1467	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	1468	* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
bogdanm	92:4fc01daae5a5	1469	* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
bogdanm	92:4fc01daae5a5	1470	* @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
bogdanm	92:4fc01daae5a5	1471	* @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
bogdanm	92:4fc01daae5a5	1472	*/
bogdanm	92:4fc01daae5a5	1473	#define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
bogdanm	92:4fc01daae5a5	1474
Kojto	93:e188a91d3eaa	1475	#endif /* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1476	/**
bogdanm	92:4fc01daae5a5	1477	* @}
bogdanm	92:4fc01daae5a5	1478	*/
bogdanm	92:4fc01daae5a5	1479
bogdanm	92:4fc01daae5a5	1480	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	1481	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1482	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	92:4fc01daae5a5	1483
bogdanm	92:4fc01daae5a5	1484	/** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
bogdanm	92:4fc01daae5a5	1485	* @{
bogdanm	92:4fc01daae5a5	1486	*/
bogdanm	85:024bf7f99721	1487	/* Interrupt & Flag management */
bogdanm	85:024bf7f99721	1488
bogdanm	85:024bf7f99721	1489	/**
bogdanm	85:024bf7f99721	1490	* @brief Enables the specified CRS interrupts.
bogdanm	85:024bf7f99721	1491	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm	85:024bf7f99721	1492	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	1493	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	1494	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	1495	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	1496	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	1497	* @retval None
bogdanm	85:024bf7f99721	1498	*/
bogdanm	85:024bf7f99721	1499	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
bogdanm	85:024bf7f99721	1500
bogdanm	85:024bf7f99721	1501	/**
bogdanm	85:024bf7f99721	1502	* @brief Disables the specified CRS interrupts.
bogdanm	85:024bf7f99721	1503	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm	85:024bf7f99721	1504	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	1505	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	1506	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	1507	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	1508	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	1509	* @retval None
bogdanm	85:024bf7f99721	1510	*/
bogdanm	85:024bf7f99721	1511	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
bogdanm	85:024bf7f99721	1512
bogdanm	85:024bf7f99721	1513	/** @brief Check the CRS's interrupt has occurred or not.
bogdanm	85:024bf7f99721	1514	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm	85:024bf7f99721	1515	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1516	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	1517	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	1518	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	1519	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	1520	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	85:024bf7f99721	1521	*/
bogdanm	85:024bf7f99721	1522	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm	85:024bf7f99721	1523
bogdanm	85:024bf7f99721	1524	/** @brief Clear the CRS's interrupt pending bits
bogdanm	85:024bf7f99721	1525	* bits to clear the selected interrupt pending bits.
bogdanm	85:024bf7f99721	1526	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	85:024bf7f99721	1527	* This parameter can be any combination of the following values:
bogdanm	85:024bf7f99721	1528	* @arg RCC_CRS_IT_SYNCOK
bogdanm	85:024bf7f99721	1529	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	85:024bf7f99721	1530	* @arg RCC_CRS_IT_ERR
bogdanm	85:024bf7f99721	1531	* @arg RCC_CRS_IT_ESYNC
bogdanm	85:024bf7f99721	1532	* @arg RCC_CRS_IT_TRIMOVF
bogdanm	85:024bf7f99721	1533	* @arg RCC_CRS_IT_SYNCERR
bogdanm	85:024bf7f99721	1534	* @arg RCC_CRS_IT_SYNCMISS
bogdanm	85:024bf7f99721	1535	*/
bogdanm	85:024bf7f99721	1536	/* CRS IT Error Mask */
bogdanm	85:024bf7f99721	1537	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
bogdanm	85:024bf7f99721	1538
bogdanm	92:4fc01daae5a5	1539	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	92:4fc01daae5a5	1540	(CRS->ICR \|= (__INTERRUPT__)))
bogdanm	85:024bf7f99721	1541
bogdanm	85:024bf7f99721	1542	/**
bogdanm	85:024bf7f99721	1543	* @brief Checks whether the specified CRS flag is set or not.
bogdanm	85:024bf7f99721	1544	* @param _FLAG_: specifies the flag to check.
bogdanm	85:024bf7f99721	1545	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1546	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	85:024bf7f99721	1547	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	85:024bf7f99721	1548	* @arg RCC_CRS_FLAG_ERR
bogdanm	85:024bf7f99721	1549	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	85:024bf7f99721	1550	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	85:024bf7f99721	1551	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	85:024bf7f99721	1552	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	85:024bf7f99721	1553	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	85:024bf7f99721	1554	*/
bogdanm	85:024bf7f99721	1555	#define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
bogdanm	85:024bf7f99721	1556
bogdanm	85:024bf7f99721	1557	/**
bogdanm	85:024bf7f99721	1558	* @brief Clears the CRS specified FLAG.
bogdanm	85:024bf7f99721	1559	* @param _FLAG_: specifies the flag to clear.
bogdanm	85:024bf7f99721	1560	* This parameter can be one of the following values:
bogdanm	85:024bf7f99721	1561	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	85:024bf7f99721	1562	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	85:024bf7f99721	1563	* @arg RCC_CRS_FLAG_ERR
bogdanm	85:024bf7f99721	1564	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	85:024bf7f99721	1565	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	85:024bf7f99721	1566	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	85:024bf7f99721	1567	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	85:024bf7f99721	1568	* @retval None
bogdanm	85:024bf7f99721	1569	*/
bogdanm	85:024bf7f99721	1570
bogdanm	85:024bf7f99721	1571	/* CRS Flag Error Mask */
bogdanm	85:024bf7f99721	1572	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
bogdanm	85:024bf7f99721	1573
bogdanm	85:024bf7f99721	1574	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	92:4fc01daae5a5	1575	(CRS->ICR \|= (__FLAG__)))
bogdanm	85:024bf7f99721	1576
bogdanm	92:4fc01daae5a5	1577	/**
bogdanm	92:4fc01daae5a5	1578	* @}
bogdanm	92:4fc01daae5a5	1579	*/
bogdanm	85:024bf7f99721	1580
bogdanm	92:4fc01daae5a5	1581	/** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
bogdanm	92:4fc01daae5a5	1582	* @{
bogdanm	92:4fc01daae5a5	1583	*/
bogdanm	85:024bf7f99721	1584	/**
bogdanm	85:024bf7f99721	1585	* @brief Enables the oscillator clock for frequency error counter.
bogdanm	85:024bf7f99721	1586	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	85:024bf7f99721	1587	* @retval None
bogdanm	85:024bf7f99721	1588	*/
bogdanm	85:024bf7f99721	1589	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
bogdanm	85:024bf7f99721	1590
bogdanm	85:024bf7f99721	1591	/**
bogdanm	85:024bf7f99721	1592	* @brief Disables the oscillator clock for frequency error counter.
bogdanm	85:024bf7f99721	1593	* @retval None
bogdanm	85:024bf7f99721	1594	*/
bogdanm	85:024bf7f99721	1595	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
bogdanm	85:024bf7f99721	1596
bogdanm	85:024bf7f99721	1597	/**
bogdanm	85:024bf7f99721	1598	* @brief Enables the automatic hardware adjustement of TRIM bits.
bogdanm	85:024bf7f99721	1599	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	85:024bf7f99721	1600	* @retval None
bogdanm	85:024bf7f99721	1601	*/
bogdanm	85:024bf7f99721	1602	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
bogdanm	85:024bf7f99721	1603
bogdanm	85:024bf7f99721	1604	/**
bogdanm	85:024bf7f99721	1605	* @brief Enables or disables the automatic hardware adjustement of TRIM bits.
bogdanm	85:024bf7f99721	1606	* @retval None
bogdanm	85:024bf7f99721	1607	*/
bogdanm	85:024bf7f99721	1608	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
bogdanm	85:024bf7f99721	1609
bogdanm	85:024bf7f99721	1610	/**
bogdanm	85:024bf7f99721	1611	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	85:024bf7f99721	1612	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	85:024bf7f99721	1613	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	85:024bf7f99721	1614	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	85:024bf7f99721	1615	* RELOAD = (fTARGET / fSYNC) -1
bogdanm	85:024bf7f99721	1616	* @param _FTARGET_ Target frequency (value in Hz)
bogdanm	85:024bf7f99721	1617	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
bogdanm	85:024bf7f99721	1618	* @retval None
bogdanm	85:024bf7f99721	1619	*/
bogdanm	85:024bf7f99721	1620	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
bogdanm	85:024bf7f99721	1621
bogdanm	92:4fc01daae5a5	1622	/**
bogdanm	92:4fc01daae5a5	1623	* @}
bogdanm	92:4fc01daae5a5	1624	*/
bogdanm	92:4fc01daae5a5	1625
bogdanm	92:4fc01daae5a5	1626	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1627	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1628	/* STM32F091xC \|\| STM32F098xx */
bogdanm	92:4fc01daae5a5	1629
bogdanm	85:024bf7f99721	1630	/**
bogdanm	85:024bf7f99721	1631	* @}
bogdanm	85:024bf7f99721	1632	*/
bogdanm	85:024bf7f99721	1633
bogdanm	85:024bf7f99721	1634	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1635	/** @addtogroup RCCEx_Exported_Functions
bogdanm	92:4fc01daae5a5	1636	* @{
bogdanm	92:4fc01daae5a5	1637	*/
bogdanm	92:4fc01daae5a5	1638
bogdanm	92:4fc01daae5a5	1639	/** @addtogroup RCCEx_Exported_Functions_Group1
bogdanm	92:4fc01daae5a5	1640	* @{
bogdanm	92:4fc01daae5a5	1641	*/
bogdanm	92:4fc01daae5a5	1642
bogdanm	85:024bf7f99721	1643	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	85:024bf7f99721	1644	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	85:024bf7f99721	1645
bogdanm	92:4fc01daae5a5	1646	#if defined(STM32F042x6) \|\| defined(STM32F048xx) \|\| \
bogdanm	92:4fc01daae5a5	1647	defined(STM32F071xB) \|\| defined(STM32F072xB) \|\| defined(STM32F078xx) \|\| \
bogdanm	92:4fc01daae5a5	1648	defined(STM32F091xC) \|\| defined(STM32F098xx)
bogdanm	85:024bf7f99721	1649	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm	85:024bf7f99721	1650	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm	85:024bf7f99721	1651	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto	93:e188a91d3eaa	1652	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
bogdanm	92:4fc01daae5a5	1653	#endif /* STM32F042x6 \|\| STM32F048xx \|\| */
bogdanm	92:4fc01daae5a5	1654	/* STM32F071xB \|\| STM32F072xB \|\| STM32F078xx \|\| */
bogdanm	92:4fc01daae5a5	1655	/* STM32F091xC \|\| STM32F098xx */
bogdanm	85:024bf7f99721	1656
bogdanm	85:024bf7f99721	1657
bogdanm	85:024bf7f99721	1658	/**
bogdanm	85:024bf7f99721	1659	* @}
bogdanm	85:024bf7f99721	1660	*/
bogdanm	85:024bf7f99721	1661
bogdanm	85:024bf7f99721	1662	/**
bogdanm	85:024bf7f99721	1663	* @}
bogdanm	85:024bf7f99721	1664	*/
bogdanm	92:4fc01daae5a5	1665
bogdanm	92:4fc01daae5a5	1666	/**
bogdanm	92:4fc01daae5a5	1667	* @}
bogdanm	92:4fc01daae5a5	1668	*/
bogdanm	92:4fc01daae5a5	1669
bogdanm	92:4fc01daae5a5	1670	/**
bogdanm	92:4fc01daae5a5	1671	* @}
bogdanm	92:4fc01daae5a5	1672	*/
bogdanm	85:024bf7f99721	1673
bogdanm	85:024bf7f99721	1674	#ifdef __cplusplus
bogdanm	85:024bf7f99721	1675	}
bogdanm	85:024bf7f99721	1676	#endif
bogdanm	85:024bf7f99721	1677
bogdanm	85:024bf7f99721	1678	#endif /* __STM32F0xx_HAL_RCC_EX_H */
bogdanm	85:024bf7f99721	1679
bogdanm	85:024bf7f99721	1680	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
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TARGET_NUCLEO_F072RB/stm32f0xx_hal_rcc_ex.h@97:4298809c7c9e, 2015-04-08 (annotated)

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