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TARGET_NUCLEO_F030R8/stm32f0xx_hal_rcc_ex.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:
filartrix
Date:
Wed Apr 08 14:12:53 2015 +0000
Revision:
97:4298809c7c9e
Parent:
93:e188a91d3eaa 
First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32f0xx_hal_rcc_ex.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.2.0
Kojto 93:e188a91d3eaa 6 * @date 11-December-2014
Kojto 90:cb3d968589d8 7 * @brief Header file of RCC HAL Extension module.
Kojto 90:cb3d968589d8 8 ******************************************************************************
Kojto 90:cb3d968589d8 9 * @attention
Kojto 90:cb3d968589d8 10 *
Kojto 90:cb3d968589d8 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 12 *
Kojto 90:cb3d968589d8 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 14 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 16 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 18 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 19 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 21 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 22 * without specific prior written permission.
Kojto 90:cb3d968589d8 23 *
Kojto 90:cb3d968589d8 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 34 *
Kojto 90:cb3d968589d8 35 ******************************************************************************
Kojto 90:cb3d968589d8 36 */
Kojto 90:cb3d968589d8 37
Kojto 90:cb3d968589d8 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 90:cb3d968589d8 39 #ifndef __STM32F0xx_HAL_RCC_EX_H
Kojto 90:cb3d968589d8 40 #define __STM32F0xx_HAL_RCC_EX_H
Kojto 90:cb3d968589d8 41
Kojto 90:cb3d968589d8 42 #ifdef __cplusplus
Kojto 90:cb3d968589d8 43 extern "C" {
Kojto 90:cb3d968589d8 44 #endif
Kojto 90:cb3d968589d8 45
Kojto 90:cb3d968589d8 46 /* Includes ------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 47 #include "stm32f0xx_hal_def.h"
Kojto 90:cb3d968589d8 48
Kojto 90:cb3d968589d8 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 90:cb3d968589d8 50 * @{
Kojto 90:cb3d968589d8 51 */
Kojto 90:cb3d968589d8 52
Kojto 90:cb3d968589d8 53 /** @addtogroup RCCEx
Kojto 90:cb3d968589d8 54 * @{
Kojto 90:cb3d968589d8 55 */
Kojto 90:cb3d968589d8 56
Kojto 90:cb3d968589d8 57 /* Exported types ------------------------------------------------------------*/
Kojto 90:cb3d968589d8 58
Kojto 90:cb3d968589d8 59 /** @defgroup RCCEx_Exported_Types RCCEx Exported Types
Kojto 90:cb3d968589d8 60 * @{
Kojto 90:cb3d968589d8 61 */
Kojto 90:cb3d968589d8 62
Kojto 90:cb3d968589d8 63 /**
Kojto 90:cb3d968589d8 64 * @brief RCC extended clocks structure definition
Kojto 90:cb3d968589d8 65 */
Kojto 93:e188a91d3eaa 66 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 93:e188a91d3eaa 67 defined(STM32F030xC)
Kojto 90:cb3d968589d8 68 typedef struct
Kojto 90:cb3d968589d8 69 {
Kojto 90:cb3d968589d8 70 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 90:cb3d968589d8 71 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 90:cb3d968589d8 72
Kojto 90:cb3d968589d8 73 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 90:cb3d968589d8 74 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 90:cb3d968589d8 75
Kojto 90:cb3d968589d8 76 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 90:cb3d968589d8 77 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 90:cb3d968589d8 78
Kojto 90:cb3d968589d8 79 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 90:cb3d968589d8 80 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 90:cb3d968589d8 81
Kojto 90:cb3d968589d8 82 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 83 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
Kojto 93:e188a91d3eaa 84 STM32F030xC */
Kojto 93:e188a91d3eaa 85
Kojto 93:e188a91d3eaa 86 #if defined(STM32F070x6) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 87 typedef struct
Kojto 93:e188a91d3eaa 88 {
Kojto 93:e188a91d3eaa 89 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 93:e188a91d3eaa 90 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 93:e188a91d3eaa 91
Kojto 93:e188a91d3eaa 92 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 93:e188a91d3eaa 93 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 93:e188a91d3eaa 94
Kojto 93:e188a91d3eaa 95 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 93:e188a91d3eaa 96 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 93:e188a91d3eaa 97
Kojto 93:e188a91d3eaa 98 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 93:e188a91d3eaa 99 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 93:e188a91d3eaa 100
Kojto 93:e188a91d3eaa 101 uint32_t UsbClockSelection; /*!< USB clock source
Kojto 93:e188a91d3eaa 102 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 93:e188a91d3eaa 103
Kojto 93:e188a91d3eaa 104 }RCC_PeriphCLKInitTypeDef;
Kojto 93:e188a91d3eaa 105 #endif /* STM32F070x6 || STM32F070xB */
Kojto 90:cb3d968589d8 106
Kojto 90:cb3d968589d8 107 #if defined(STM32F042x6) || defined(STM32F048xx)
Kojto 90:cb3d968589d8 108 typedef struct
Kojto 90:cb3d968589d8 109 {
Kojto 90:cb3d968589d8 110 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 90:cb3d968589d8 111 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 90:cb3d968589d8 112
Kojto 90:cb3d968589d8 113 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 90:cb3d968589d8 114 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 90:cb3d968589d8 115
Kojto 90:cb3d968589d8 116 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 90:cb3d968589d8 117 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 90:cb3d968589d8 118
Kojto 90:cb3d968589d8 119 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 90:cb3d968589d8 120 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 90:cb3d968589d8 121
Kojto 90:cb3d968589d8 122 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 90:cb3d968589d8 123 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 90:cb3d968589d8 124
Kojto 90:cb3d968589d8 125 uint32_t UsbClockSelection; /*!< USB clock source
Kojto 90:cb3d968589d8 126 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 90:cb3d968589d8 127
Kojto 90:cb3d968589d8 128 }RCC_PeriphCLKInitTypeDef;
Kojto 90:cb3d968589d8 129 #endif /* STM32F042x6 || STM32F048xx */
Kojto 90:cb3d968589d8 130
Kojto 90:cb3d968589d8 131 #if defined(STM32F051x8) || defined(STM32F058xx)
Kojto 90:cb3d968589d8 132 typedef struct
Kojto 90:cb3d968589d8 133 {
Kojto 90:cb3d968589d8 134 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 90:cb3d968589d8 135 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 90:cb3d968589d8 136
Kojto 90:cb3d968589d8 137 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 90:cb3d968589d8 138 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 90:cb3d968589d8 139
Kojto 90:cb3d968589d8 140 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 90:cb3d968589d8 141 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 90:cb3d968589d8 142
Kojto 90:cb3d968589d8 143 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 90:cb3d968589d8 144 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 90:cb3d968589d8 145
Kojto 90:cb3d968589d8 146 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 90:cb3d968589d8 147 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 90:cb3d968589d8 148
Kojto 90:cb3d968589d8 149 }RCC_PeriphCLKInitTypeDef;
Kojto 90:cb3d968589d8 150 #endif /* STM32F051x8 || STM32F058xx */
Kojto 90:cb3d968589d8 151
Kojto 90:cb3d968589d8 152 #if defined(STM32F071xB)
Kojto 90:cb3d968589d8 153 typedef struct
Kojto 90:cb3d968589d8 154 {
Kojto 90:cb3d968589d8 155 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 90:cb3d968589d8 156 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 90:cb3d968589d8 157
Kojto 90:cb3d968589d8 158 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 90:cb3d968589d8 159 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 90:cb3d968589d8 160
Kojto 90:cb3d968589d8 161 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 90:cb3d968589d8 162 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 90:cb3d968589d8 163
Kojto 90:cb3d968589d8 164 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 90:cb3d968589d8 165 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 90:cb3d968589d8 166
Kojto 90:cb3d968589d8 167 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 90:cb3d968589d8 168 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 90:cb3d968589d8 169
Kojto 90:cb3d968589d8 170 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 90:cb3d968589d8 171 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 90:cb3d968589d8 172
Kojto 90:cb3d968589d8 173 }RCC_PeriphCLKInitTypeDef;
Kojto 90:cb3d968589d8 174 #endif /* STM32F071xB */
Kojto 90:cb3d968589d8 175
Kojto 90:cb3d968589d8 176 #if defined(STM32F072xB) || defined(STM32F078xx)
Kojto 90:cb3d968589d8 177 typedef struct
Kojto 90:cb3d968589d8 178 {
Kojto 90:cb3d968589d8 179 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 90:cb3d968589d8 180 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 90:cb3d968589d8 181
Kojto 90:cb3d968589d8 182 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 90:cb3d968589d8 183 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 90:cb3d968589d8 184
Kojto 90:cb3d968589d8 185 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 90:cb3d968589d8 186 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 90:cb3d968589d8 187
Kojto 90:cb3d968589d8 188 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 90:cb3d968589d8 189 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 90:cb3d968589d8 190
Kojto 90:cb3d968589d8 191 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 90:cb3d968589d8 192 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 90:cb3d968589d8 193
Kojto 90:cb3d968589d8 194 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 90:cb3d968589d8 195 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 90:cb3d968589d8 196
Kojto 90:cb3d968589d8 197 uint32_t UsbClockSelection; /*!< USB clock source
Kojto 90:cb3d968589d8 198 This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto 90:cb3d968589d8 199
Kojto 90:cb3d968589d8 200 }RCC_PeriphCLKInitTypeDef;
Kojto 90:cb3d968589d8 201 #endif /* STM32F072xB || STM32F078xx */
Kojto 90:cb3d968589d8 202
Kojto 90:cb3d968589d8 203
Kojto 90:cb3d968589d8 204 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 205 typedef struct
Kojto 90:cb3d968589d8 206 {
Kojto 90:cb3d968589d8 207 uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto 90:cb3d968589d8 208 This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto 90:cb3d968589d8 209
Kojto 90:cb3d968589d8 210 uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto 90:cb3d968589d8 211 This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto 90:cb3d968589d8 212
Kojto 90:cb3d968589d8 213 uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto 90:cb3d968589d8 214 This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto 90:cb3d968589d8 215
Kojto 90:cb3d968589d8 216 uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto 90:cb3d968589d8 217 This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
Kojto 90:cb3d968589d8 218
Kojto 90:cb3d968589d8 219 uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto 90:cb3d968589d8 220 This parameter can be a value of @ref RCCEx_USART3_Clock_Source */
Kojto 90:cb3d968589d8 221
Kojto 90:cb3d968589d8 222 uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto 90:cb3d968589d8 223 This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto 90:cb3d968589d8 224
Kojto 90:cb3d968589d8 225 uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto 90:cb3d968589d8 226 This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto 90:cb3d968589d8 227
Kojto 90:cb3d968589d8 228 }RCC_PeriphCLKInitTypeDef;
Kojto 90:cb3d968589d8 229 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 230
Kojto 90:cb3d968589d8 231 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 232 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 233 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 234
Kojto 90:cb3d968589d8 235 /**
Kojto 90:cb3d968589d8 236 * @brief RCC_CRS Init structure definition
Kojto 90:cb3d968589d8 237 */
Kojto 90:cb3d968589d8 238 typedef struct
Kojto 90:cb3d968589d8 239 {
Kojto 90:cb3d968589d8 240 uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
Kojto 90:cb3d968589d8 241 This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
Kojto 90:cb3d968589d8 242
Kojto 90:cb3d968589d8 243 uint32_t Source; /*!< Specifies the SYNC signal source.
Kojto 90:cb3d968589d8 244 This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
Kojto 90:cb3d968589d8 245
Kojto 90:cb3d968589d8 246 uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
Kojto 90:cb3d968589d8 247 This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
Kojto 90:cb3d968589d8 248
Kojto 90:cb3d968589d8 249 uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
Kojto 90:cb3d968589d8 250 It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
Kojto 90:cb3d968589d8 251 This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
Kojto 90:cb3d968589d8 252
Kojto 90:cb3d968589d8 253 uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
Kojto 90:cb3d968589d8 254 This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
Kojto 90:cb3d968589d8 255
Kojto 90:cb3d968589d8 256 uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
Kojto 90:cb3d968589d8 257 This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
Kojto 90:cb3d968589d8 258
Kojto 90:cb3d968589d8 259 }RCC_CRSInitTypeDef;
Kojto 90:cb3d968589d8 260
Kojto 90:cb3d968589d8 261 /**
Kojto 90:cb3d968589d8 262 * @brief RCC_CRS Synchronization structure definition
Kojto 90:cb3d968589d8 263 */
Kojto 90:cb3d968589d8 264 typedef struct
Kojto 90:cb3d968589d8 265 {
Kojto 90:cb3d968589d8 266 uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
Kojto 90:cb3d968589d8 267 This parameter must be a number between 0 and 0xFFFF*/
Kojto 90:cb3d968589d8 268
Kojto 90:cb3d968589d8 269 uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
Kojto 90:cb3d968589d8 270 This parameter must be a number between 0 and 0x3F */
Kojto 90:cb3d968589d8 271
Kojto 90:cb3d968589d8 272 uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
Kojto 90:cb3d968589d8 273 value latched in the time of the last SYNC event.
Kojto 90:cb3d968589d8 274 This parameter must be a number between 0 and 0xFFFF */
Kojto 90:cb3d968589d8 275
Kojto 90:cb3d968589d8 276 uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
Kojto 90:cb3d968589d8 277 frequency error counter latched in the time of the last SYNC event.
Kojto 90:cb3d968589d8 278 It shows whether the actual frequency is below or above the target.
Kojto 90:cb3d968589d8 279 This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
Kojto 90:cb3d968589d8 280
Kojto 90:cb3d968589d8 281 }RCC_CRSSynchroInfoTypeDef;
Kojto 90:cb3d968589d8 282
Kojto 93:e188a91d3eaa 283 #endif /* STM32F042x6 || STM32F048xx */
Kojto 90:cb3d968589d8 284 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 285 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 286
Kojto 90:cb3d968589d8 287 /**
Kojto 90:cb3d968589d8 288 * @}
Kojto 90:cb3d968589d8 289 */
Kojto 90:cb3d968589d8 290
Kojto 90:cb3d968589d8 291 /* Exported constants --------------------------------------------------------*/
Kojto 90:cb3d968589d8 292
Kojto 90:cb3d968589d8 293 /** @defgroup RCCEx_Exported_Constants RCCEx Exported Constants
Kojto 90:cb3d968589d8 294 * @{
Kojto 90:cb3d968589d8 295 */
Kojto 90:cb3d968589d8 296
Kojto 93:e188a91d3eaa 297 /** @defgroup RCCEx_CRS_Status RCCEx CRS Status
Kojto 93:e188a91d3eaa 298 * @{
Kojto 93:e188a91d3eaa 299 */
Kojto 93:e188a91d3eaa 300 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 301 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 302 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 303
Kojto 93:e188a91d3eaa 304 #define RCC_CRS_NONE ((uint32_t)0x00000000)
Kojto 93:e188a91d3eaa 305 #define RCC_CRS_TIMEOUT ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 306 #define RCC_CRS_SYNCOK ((uint32_t)0x00000002)
Kojto 93:e188a91d3eaa 307 #define RCC_CRS_SYNCWARM ((uint32_t)0x00000004)
Kojto 93:e188a91d3eaa 308 #define RCC_CRS_SYNCERR ((uint32_t)0x00000008)
Kojto 93:e188a91d3eaa 309 #define RCC_CRS_SYNCMISS ((uint32_t)0x00000010)
Kojto 93:e188a91d3eaa 310 #define RCC_CRS_TRIMOV ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 311
Kojto 93:e188a91d3eaa 312 #endif /* STM32F042x6 || STM32F048xx */
Kojto 93:e188a91d3eaa 313 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 314 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 315 /**
Kojto 93:e188a91d3eaa 316 * @}
Kojto 93:e188a91d3eaa 317 */
Kojto 93:e188a91d3eaa 318
Kojto 90:cb3d968589d8 319 /** @defgroup RCCEx_Periph_Clock_Selection RCCEx Periph Clock Selection
Kojto 90:cb3d968589d8 320 * @{
Kojto 90:cb3d968589d8 321 */
Kojto 93:e188a91d3eaa 322 #if defined(STM32F030x6) || defined(STM32F030x8) || defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 93:e188a91d3eaa 323 defined(STM32F030xC)
Kojto 90:cb3d968589d8 324 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 325 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 326 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 327
Kojto 90:cb3d968589d8 328 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
Kojto 90:cb3d968589d8 329 RCC_PERIPHCLK_RTC))
Kojto 93:e188a91d3eaa 330 #endif /* STM32F030x6 || STM32F030x8 || STM32F031x6 || STM32F038xx ||
Kojto 93:e188a91d3eaa 331 STM32F030xC */
Kojto 93:e188a91d3eaa 332
Kojto 93:e188a91d3eaa 333 #if defined(STM32F070x6) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 334 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 93:e188a91d3eaa 335 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 93:e188a91d3eaa 336 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 93:e188a91d3eaa 337 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 93:e188a91d3eaa 338
Kojto 93:e188a91d3eaa 339 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
Kojto 93:e188a91d3eaa 340 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
Kojto 93:e188a91d3eaa 341 #endif /* STM32F070x6 || STM32F070xB */
Kojto 90:cb3d968589d8 342
Kojto 90:cb3d968589d8 343 #if defined(STM32F042x6) || defined(STM32F048xx)
Kojto 90:cb3d968589d8 344 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 345 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 346 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 347 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 348 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 349
Kojto 90:cb3d968589d8 350 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
Kojto 90:cb3d968589d8 351 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC | \
Kojto 90:cb3d968589d8 352 RCC_PERIPHCLK_USB))
Kojto 90:cb3d968589d8 353 #endif /* STM32F042x6 || STM32F048xx */
Kojto 90:cb3d968589d8 354
Kojto 90:cb3d968589d8 355 #if defined(STM32F051x8) || defined(STM32F058xx)
Kojto 90:cb3d968589d8 356 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 357 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 358 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 359 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 360
Kojto 90:cb3d968589d8 361 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_I2C1 | \
Kojto 90:cb3d968589d8 362 RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_RTC))
Kojto 90:cb3d968589d8 363 #endif /* STM32F051x8 || STM32F058xx */
Kojto 90:cb3d968589d8 364
Kojto 90:cb3d968589d8 365 #if defined(STM32F071xB)
Kojto 90:cb3d968589d8 366 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 367 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 368 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 369 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 370 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 371
Kojto 90:cb3d968589d8 372 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
Kojto 90:cb3d968589d8 373 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
Kojto 90:cb3d968589d8 374 RCC_PERIPHCLK_RTC))
Kojto 90:cb3d968589d8 375 #endif /* STM32F071xB */
Kojto 90:cb3d968589d8 376
Kojto 90:cb3d968589d8 377 #if defined(STM32F072xB) || defined(STM32F078xx)
Kojto 90:cb3d968589d8 378 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 379 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 380 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 381 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 382 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 383 #define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto 90:cb3d968589d8 384
Kojto 90:cb3d968589d8 385 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
Kojto 90:cb3d968589d8 386 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
Kojto 90:cb3d968589d8 387 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USB))
Kojto 90:cb3d968589d8 388 #endif /* STM32F072xB || STM32F078xx */
Kojto 90:cb3d968589d8 389
Kojto 90:cb3d968589d8 390 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 391 #define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto 90:cb3d968589d8 392 #define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto 90:cb3d968589d8 393 #define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto 90:cb3d968589d8 394 #define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto 90:cb3d968589d8 395 #define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto 90:cb3d968589d8 396 #define RCC_PERIPHCLK_USART3 ((uint32_t)0x00040000)
Kojto 90:cb3d968589d8 397
Kojto 90:cb3d968589d8 398 #define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 | RCC_PERIPHCLK_USART2 | \
Kojto 90:cb3d968589d8 399 RCC_PERIPHCLK_I2C1 | RCC_PERIPHCLK_CEC | \
Kojto 90:cb3d968589d8 400 RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_USART3 ))
Kojto 90:cb3d968589d8 401 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 402
Kojto 90:cb3d968589d8 403 /**
Kojto 90:cb3d968589d8 404 * @}
Kojto 90:cb3d968589d8 405 */
Kojto 90:cb3d968589d8 406
Kojto 90:cb3d968589d8 407 /** @defgroup RCCEx_MCO_Clock_Source RCCEx MCO Clock Source
Kojto 90:cb3d968589d8 408 * @{
Kojto 90:cb3d968589d8 409 */
Kojto 90:cb3d968589d8 410
Kojto 93:e188a91d3eaa 411 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 412
Kojto 90:cb3d968589d8 413 #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
Kojto 90:cb3d968589d8 414
Kojto 90:cb3d968589d8 415 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
Kojto 90:cb3d968589d8 416 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
Kojto 90:cb3d968589d8 417 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
Kojto 90:cb3d968589d8 418 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
Kojto 90:cb3d968589d8 419 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
Kojto 90:cb3d968589d8 420 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
Kojto 90:cb3d968589d8 421 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
Kojto 90:cb3d968589d8 422 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
Kojto 90:cb3d968589d8 423 ((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto 90:cb3d968589d8 424
Kojto 93:e188a91d3eaa 425 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || STM32F070xB || STM32F030xC */
Kojto 90:cb3d968589d8 426
Kojto 90:cb3d968589d8 427 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
Kojto 90:cb3d968589d8 430 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
Kojto 90:cb3d968589d8 431 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
Kojto 90:cb3d968589d8 432 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
Kojto 90:cb3d968589d8 433 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
Kojto 90:cb3d968589d8 434 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
Kojto 90:cb3d968589d8 435 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
Kojto 90:cb3d968589d8 436 ((SOURCE) == RCC_MCOSOURCE_HSI14))
Kojto 90:cb3d968589d8 437
Kojto 90:cb3d968589d8 438 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
Kojto 90:cb3d968589d8 439
Kojto 90:cb3d968589d8 440 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 441 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 442 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 443
Kojto 90:cb3d968589d8 444 #define RCC_MCOSOURCE_HSI48 RCC_CFGR_MCO_HSI48
Kojto 90:cb3d968589d8 445 #define RCC_MCOSOURCE_PLLCLK_NODIV (RCC_CFGR_MCO_PLL | RCC_CFGR_PLLNODIV)
Kojto 90:cb3d968589d8 446
Kojto 90:cb3d968589d8 447 #define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) || \
Kojto 90:cb3d968589d8 448 ((SOURCE) == RCC_MCOSOURCE_LSI) || \
Kojto 90:cb3d968589d8 449 ((SOURCE) == RCC_MCOSOURCE_LSE) || \
Kojto 90:cb3d968589d8 450 ((SOURCE) == RCC_MCOSOURCE_SYSCLK) || \
Kojto 90:cb3d968589d8 451 ((SOURCE) == RCC_MCOSOURCE_HSI) || \
Kojto 90:cb3d968589d8 452 ((SOURCE) == RCC_MCOSOURCE_HSE) || \
Kojto 90:cb3d968589d8 453 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_NODIV) || \
Kojto 90:cb3d968589d8 454 ((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2) || \
Kojto 90:cb3d968589d8 455 ((SOURCE) == RCC_MCOSOURCE_HSI14) || \
Kojto 90:cb3d968589d8 456 ((SOURCE) == RCC_MCOSOURCE_HSI48))
Kojto 90:cb3d968589d8 457
Kojto 90:cb3d968589d8 458 #define RCC_IT_HSI48 ((uint8_t)0x40)
Kojto 90:cb3d968589d8 459
Kojto 90:cb3d968589d8 460 /* Flags in the CR2 register */
Kojto 90:cb3d968589d8 461 #define RCC_CR2_HSI48RDY_BitNumber 16
Kojto 90:cb3d968589d8 462
Kojto 90:cb3d968589d8 463 #define RCC_FLAG_HSI48RDY ((uint8_t)((CR2_REG_INDEX << 5) | RCC_CR2_HSI48RDY_BitNumber))
Kojto 90:cb3d968589d8 464
Kojto 90:cb3d968589d8 465 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 466 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 467 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 468 /**
Kojto 90:cb3d968589d8 469 * @}
Kojto 90:cb3d968589d8 470 */
Kojto 90:cb3d968589d8 471
Kojto 90:cb3d968589d8 472 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || defined(STM32F078xx)
Kojto 90:cb3d968589d8 473
Kojto 90:cb3d968589d8 474 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto 90:cb3d968589d8 475 * @{
Kojto 90:cb3d968589d8 476 */
Kojto 90:cb3d968589d8 477 #define RCC_USBCLKSOURCE_HSI48 RCC_CFGR3_USBSW_HSI48
Kojto 90:cb3d968589d8 478 #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto 90:cb3d968589d8 479
Kojto 90:cb3d968589d8 480 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_HSI48) || \
Kojto 90:cb3d968589d8 481 ((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto 90:cb3d968589d8 482 /**
Kojto 90:cb3d968589d8 483 * @}
Kojto 90:cb3d968589d8 484 */
Kojto 90:cb3d968589d8 485
Kojto 90:cb3d968589d8 486 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || STM32F078xx */
Kojto 90:cb3d968589d8 487
Kojto 93:e188a91d3eaa 488 #if defined(STM32F070x6) || defined(STM32F070xB)
Kojto 93:e188a91d3eaa 489
Kojto 93:e188a91d3eaa 490 /** @defgroup RCCEx_USB_Clock_Source RCCEx USB Clock Source
Kojto 93:e188a91d3eaa 491 * @{
Kojto 93:e188a91d3eaa 492 */
Kojto 93:e188a91d3eaa 493 #define RCC_USBCLKSOURCE_PLLCLK RCC_CFGR3_USBSW_PLLCLK
Kojto 93:e188a91d3eaa 494
Kojto 93:e188a91d3eaa 495 #define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSOURCE_PLLCLK))
Kojto 93:e188a91d3eaa 496 /**
Kojto 93:e188a91d3eaa 497 * @}
Kojto 93:e188a91d3eaa 498 */
Kojto 93:e188a91d3eaa 499
Kojto 93:e188a91d3eaa 500 #endif /* STM32F070x6 || STM32F070xB */
Kojto 93:e188a91d3eaa 501
Kojto 90:cb3d968589d8 502 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 503 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 504
Kojto 90:cb3d968589d8 505 /** @defgroup RCCEx_USART2_Clock_Source RCCEx USART2 Clock Source
Kojto 90:cb3d968589d8 506 * @{
Kojto 90:cb3d968589d8 507 */
Kojto 90:cb3d968589d8 508 #define RCC_USART2CLKSOURCE_PCLK1 RCC_CFGR3_USART2SW_PCLK
Kojto 90:cb3d968589d8 509 #define RCC_USART2CLKSOURCE_SYSCLK RCC_CFGR3_USART2SW_SYSCLK
Kojto 90:cb3d968589d8 510 #define RCC_USART2CLKSOURCE_LSE RCC_CFGR3_USART2SW_LSE
Kojto 90:cb3d968589d8 511 #define RCC_USART2CLKSOURCE_HSI RCC_CFGR3_USART2SW_HSI
Kojto 90:cb3d968589d8 512
Kojto 90:cb3d968589d8 513 #define IS_RCC_USART2CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART2CLKSOURCE_PCLK1) || \
Kojto 90:cb3d968589d8 514 ((SOURCE) == RCC_USART2CLKSOURCE_SYSCLK) || \
Kojto 90:cb3d968589d8 515 ((SOURCE) == RCC_USART2CLKSOURCE_LSE) || \
Kojto 90:cb3d968589d8 516 ((SOURCE) == RCC_USART2CLKSOURCE_HSI))
Kojto 90:cb3d968589d8 517 /**
Kojto 90:cb3d968589d8 518 * @}
Kojto 90:cb3d968589d8 519 */
Kojto 90:cb3d968589d8 520
Kojto 90:cb3d968589d8 521 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 522 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 523
Kojto 90:cb3d968589d8 524 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 525
Kojto 90:cb3d968589d8 526 /** @defgroup RCCEx_USART3_Clock_Source RCCEx USART3 Clock Source
Kojto 90:cb3d968589d8 527 * @{
Kojto 90:cb3d968589d8 528 */
Kojto 90:cb3d968589d8 529 #define RCC_USART3CLKSOURCE_PCLK1 RCC_CFGR3_USART3SW_PCLK
Kojto 90:cb3d968589d8 530 #define RCC_USART3CLKSOURCE_SYSCLK RCC_CFGR3_USART3SW_SYSCLK
Kojto 90:cb3d968589d8 531 #define RCC_USART3CLKSOURCE_LSE RCC_CFGR3_USART3SW_LSE
Kojto 90:cb3d968589d8 532 #define RCC_USART3CLKSOURCE_HSI RCC_CFGR3_USART3SW_HSI
Kojto 90:cb3d968589d8 533
Kojto 90:cb3d968589d8 534 #define IS_RCC_USART3CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART3CLKSOURCE_PCLK1) || \
Kojto 90:cb3d968589d8 535 ((SOURCE) == RCC_USART3CLKSOURCE_SYSCLK) || \
Kojto 90:cb3d968589d8 536 ((SOURCE) == RCC_USART3CLKSOURCE_LSE) || \
Kojto 90:cb3d968589d8 537 ((SOURCE) == RCC_USART3CLKSOURCE_HSI))
Kojto 90:cb3d968589d8 538 /**
Kojto 90:cb3d968589d8 539 * @}
Kojto 90:cb3d968589d8 540 */
Kojto 90:cb3d968589d8 541
Kojto 90:cb3d968589d8 542 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 543
Kojto 90:cb3d968589d8 544
Kojto 90:cb3d968589d8 545 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 546 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 547 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 548 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 549
Kojto 90:cb3d968589d8 550 /** @defgroup RCCEx_CEC_Clock_Source RCCEx CEC Clock Source
Kojto 90:cb3d968589d8 551 * @{
Kojto 90:cb3d968589d8 552 */
Kojto 90:cb3d968589d8 553 #define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
Kojto 90:cb3d968589d8 554 #define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
Kojto 90:cb3d968589d8 555
Kojto 90:cb3d968589d8 556 #define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) || \
Kojto 90:cb3d968589d8 557 ((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto 90:cb3d968589d8 558 /**
Kojto 90:cb3d968589d8 559 * @}
Kojto 90:cb3d968589d8 560 */
Kojto 90:cb3d968589d8 561
Kojto 90:cb3d968589d8 562 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 563 /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 564 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 565 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 566
Kojto 90:cb3d968589d8 567 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 568 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 569 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 570
Kojto 90:cb3d968589d8 571 /** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
Kojto 90:cb3d968589d8 572 * @{
Kojto 90:cb3d968589d8 573 */
Kojto 90:cb3d968589d8 574 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto 90:cb3d968589d8 575 #define RCC_PLLSOURCE_HSI48 RCC_CFGR_PLLSRC_HSI48_PREDIV
Kojto 90:cb3d968589d8 576
Kojto 90:cb3d968589d8 577 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 90:cb3d968589d8 578 ((SOURCE) == RCC_PLLSOURCE_HSI48) || \
Kojto 90:cb3d968589d8 579 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 90:cb3d968589d8 580 /**
Kojto 90:cb3d968589d8 581 * @}
Kojto 90:cb3d968589d8 582 */
Kojto 90:cb3d968589d8 583
Kojto 90:cb3d968589d8 584 /** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
Kojto 90:cb3d968589d8 585 * @{
Kojto 90:cb3d968589d8 586 */
Kojto 90:cb3d968589d8 587 #define RCC_SYSCLKSOURCE_HSI48 RCC_CFGR_SW_HSI48
Kojto 90:cb3d968589d8 588
Kojto 90:cb3d968589d8 589 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 90:cb3d968589d8 590 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 90:cb3d968589d8 591 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK) || \
Kojto 90:cb3d968589d8 592 ((SOURCE) == RCC_SYSCLKSOURCE_HSI48))
Kojto 90:cb3d968589d8 593
Kojto 90:cb3d968589d8 594 #define RCC_SYSCLKSOURCE_STATUS_HSI48 RCC_CFGR_SWS_HSI48
Kojto 90:cb3d968589d8 595
Kojto 90:cb3d968589d8 596 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
Kojto 90:cb3d968589d8 597 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
Kojto 90:cb3d968589d8 598 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK) || \
Kojto 90:cb3d968589d8 599 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI48))
Kojto 90:cb3d968589d8 600 /**
Kojto 90:cb3d968589d8 601 * @}
Kojto 90:cb3d968589d8 602 */
Kojto 90:cb3d968589d8 603
Kojto 90:cb3d968589d8 604 /** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto 90:cb3d968589d8 605 * @{
Kojto 90:cb3d968589d8 606 */
Kojto 90:cb3d968589d8 607 #define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto 90:cb3d968589d8 608 #define RCC_HSI48_ON ((uint8_t)0x01)
Kojto 90:cb3d968589d8 609
Kojto 90:cb3d968589d8 610 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF) || ((HSI48) == RCC_HSI48_ON))
Kojto 90:cb3d968589d8 611 /**
Kojto 90:cb3d968589d8 612 * @}
Kojto 90:cb3d968589d8 613 */
Kojto 90:cb3d968589d8 614 #else
Kojto 90:cb3d968589d8 615 /** @defgroup RCCEx_PLL_Clock_Source RCCEx PLL Clock Source
Kojto 90:cb3d968589d8 616 * @{
Kojto 90:cb3d968589d8 617 */
Kojto 93:e188a91d3eaa 618
Kojto 93:e188a91d3eaa 619 #if defined(STM32F070xB) || defined(STM32F070x6) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 620 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto 93:e188a91d3eaa 621 #else
Kojto 90:cb3d968589d8 622 #define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto 93:e188a91d3eaa 623 #endif
Kojto 90:cb3d968589d8 624
Kojto 90:cb3d968589d8 625 #define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) || \
Kojto 90:cb3d968589d8 626 ((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto 90:cb3d968589d8 627 /**
Kojto 90:cb3d968589d8 628 * @}
Kojto 90:cb3d968589d8 629 */
Kojto 90:cb3d968589d8 630
Kojto 90:cb3d968589d8 631 /** @defgroup RCCEx_System_Clock_Source RCCEx System Clock Source
Kojto 90:cb3d968589d8 632 * @{
Kojto 90:cb3d968589d8 633 */
Kojto 90:cb3d968589d8 634 #define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) || \
Kojto 90:cb3d968589d8 635 ((SOURCE) == RCC_SYSCLKSOURCE_HSE) || \
Kojto 90:cb3d968589d8 636 ((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto 90:cb3d968589d8 637
Kojto 90:cb3d968589d8 638 #define IS_RCC_SYSCLKSOURCE_STATUS(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
Kojto 90:cb3d968589d8 639 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
Kojto 90:cb3d968589d8 640 ((SOURCE) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
Kojto 90:cb3d968589d8 641 /**
Kojto 90:cb3d968589d8 642 * @}
Kojto 90:cb3d968589d8 643 */
Kojto 90:cb3d968589d8 644
Kojto 90:cb3d968589d8 645 /** @defgroup RCCEx_HSI48_Config RCCEx HSI48 Config
Kojto 90:cb3d968589d8 646 * @{
Kojto 90:cb3d968589d8 647 */
Kojto 90:cb3d968589d8 648 #define RCC_HSI48_OFF ((uint8_t)0x00)
Kojto 90:cb3d968589d8 649
Kojto 90:cb3d968589d8 650 #define IS_RCC_HSI48(HSI48) (((HSI48) == RCC_HSI48_OFF))
Kojto 90:cb3d968589d8 651 /**
Kojto 90:cb3d968589d8 652 * @}
Kojto 90:cb3d968589d8 653 */
Kojto 90:cb3d968589d8 654
Kojto 90:cb3d968589d8 655 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 656 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 657 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 658
Kojto 90:cb3d968589d8 659
Kojto 90:cb3d968589d8 660 /** @defgroup RCCEx_MCOx_Clock_Prescaler RCCEx MCOx Clock Prescaler
Kojto 90:cb3d968589d8 661 * @{
Kojto 90:cb3d968589d8 662 */
Kojto 90:cb3d968589d8 663
Kojto 90:cb3d968589d8 664 #if defined(STM32F030x8) || defined(STM32F051x8) || defined(STM32F058xx)
Kojto 90:cb3d968589d8 665
Kojto 90:cb3d968589d8 666 #define RCC_MCO_NODIV ((uint32_t)0x00000000)
Kojto 90:cb3d968589d8 667
Kojto 90:cb3d968589d8 668 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
Kojto 90:cb3d968589d8 669
Kojto 90:cb3d968589d8 670 #endif /* STM32F030x8 || STM32F051x8 || STM32F058xx */
Kojto 90:cb3d968589d8 671
Kojto 93:e188a91d3eaa 672 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 673 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F071xB) || defined(STM32F070xB) || \
Kojto 90:cb3d968589d8 674 defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 675 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 676
Kojto 90:cb3d968589d8 677 #define RCC_MCO_DIV1 ((uint32_t)0x00000000)
Kojto 90:cb3d968589d8 678 #define RCC_MCO_DIV2 ((uint32_t)0x10000000)
Kojto 90:cb3d968589d8 679 #define RCC_MCO_DIV4 ((uint32_t)0x20000000)
Kojto 90:cb3d968589d8 680 #define RCC_MCO_DIV8 ((uint32_t)0x30000000)
Kojto 90:cb3d968589d8 681 #define RCC_MCO_DIV16 ((uint32_t)0x40000000)
Kojto 90:cb3d968589d8 682 #define RCC_MCO_DIV32 ((uint32_t)0x50000000)
Kojto 90:cb3d968589d8 683 #define RCC_MCO_DIV64 ((uint32_t)0x60000000)
Kojto 90:cb3d968589d8 684 #define RCC_MCO_DIV128 ((uint32_t)0x70000000)
Kojto 90:cb3d968589d8 685
Kojto 90:cb3d968589d8 686 #define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) || ((DIV) == RCC_MCO_DIV2) || \
Kojto 90:cb3d968589d8 687 ((DIV) == RCC_MCO_DIV4) || ((DIV) == RCC_MCO_DIV8) || \
Kojto 90:cb3d968589d8 688 ((DIV) == RCC_MCO_DIV16) || ((DIV) == RCC_MCO_DIV32) || \
Kojto 90:cb3d968589d8 689 ((DIV) == RCC_MCO_DIV64) || ((DIV) == RCC_MCO_DIV128))
Kojto 90:cb3d968589d8 690
Kojto 90:cb3d968589d8 691 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 692 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070x6 || STM32F070xB */
Kojto 93:e188a91d3eaa 693 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 694
Kojto 90:cb3d968589d8 695 /**
Kojto 90:cb3d968589d8 696 * @}
Kojto 90:cb3d968589d8 697 */
Kojto 90:cb3d968589d8 698
Kojto 90:cb3d968589d8 699 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 700 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 701 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 702
Kojto 90:cb3d968589d8 703 /** @defgroup RCCEx_CRS_SynchroSource RCCEx CRS SynchroSource
Kojto 90:cb3d968589d8 704 * @{
Kojto 90:cb3d968589d8 705 */
Kojto 90:cb3d968589d8 706 #define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /*!< Synchro Signal soucre GPIO */
Kojto 90:cb3d968589d8 707 #define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /*!< Synchro Signal source LSE */
Kojto 90:cb3d968589d8 708 #define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /*!< Synchro Signal source USB SOF (default)*/
Kojto 90:cb3d968589d8 709
Kojto 90:cb3d968589d8 710 #define IS_RCC_CRS_SYNC_SOURCE(_SOURCE_) (((_SOURCE_) == RCC_CRS_SYNC_SOURCE_GPIO) || \
Kojto 90:cb3d968589d8 711 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_LSE) || \
Kojto 90:cb3d968589d8 712 ((_SOURCE_) == RCC_CRS_SYNC_SOURCE_USB))
Kojto 90:cb3d968589d8 713 /**
Kojto 90:cb3d968589d8 714 * @}
Kojto 90:cb3d968589d8 715 */
Kojto 90:cb3d968589d8 716
Kojto 90:cb3d968589d8 717 /** @defgroup RCCEx_CRS_SynchroDivider RCCEx CRS SynchroDivider
Kojto 90:cb3d968589d8 718 * @{
Kojto 90:cb3d968589d8 719 */
Kojto 90:cb3d968589d8 720 #define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /*!< Synchro Signal not divided (default) */
Kojto 90:cb3d968589d8 721 #define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /*!< Synchro Signal divided by 2 */
Kojto 90:cb3d968589d8 722 #define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /*!< Synchro Signal divided by 4 */
Kojto 90:cb3d968589d8 723 #define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 8 */
Kojto 90:cb3d968589d8 724 #define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /*!< Synchro Signal divided by 16 */
Kojto 90:cb3d968589d8 725 #define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_0) /*!< Synchro Signal divided by 32 */
Kojto 90:cb3d968589d8 726 #define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 | CRS_CFGR_SYNCDIV_1) /*!< Synchro Signal divided by 64 */
Kojto 90:cb3d968589d8 727 #define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /*!< Synchro Signal divided by 128 */
Kojto 90:cb3d968589d8 728
Kojto 90:cb3d968589d8 729 #define IS_RCC_CRS_SYNC_DIV(_DIV_) (((_DIV_) == RCC_CRS_SYNC_DIV1) || ((_DIV_) == RCC_CRS_SYNC_DIV2) || \
Kojto 90:cb3d968589d8 730 ((_DIV_) == RCC_CRS_SYNC_DIV4) || ((_DIV_) == RCC_CRS_SYNC_DIV8) || \
Kojto 90:cb3d968589d8 731 ((_DIV_) == RCC_CRS_SYNC_DIV16) || ((_DIV_) == RCC_CRS_SYNC_DIV32) || \
Kojto 90:cb3d968589d8 732 ((_DIV_) == RCC_CRS_SYNC_DIV64) || ((_DIV_) == RCC_CRS_SYNC_DIV128))
Kojto 90:cb3d968589d8 733 /**
Kojto 90:cb3d968589d8 734 * @}
Kojto 90:cb3d968589d8 735 */
Kojto 90:cb3d968589d8 736
Kojto 90:cb3d968589d8 737 /** @defgroup RCCEx_CRS_SynchroPolarity RCCEx CRS SynchroPolarity
Kojto 90:cb3d968589d8 738 * @{
Kojto 90:cb3d968589d8 739 */
Kojto 90:cb3d968589d8 740 #define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /*!< Synchro Active on rising edge (default) */
Kojto 90:cb3d968589d8 741 #define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /*!< Synchro Active on falling edge */
Kojto 90:cb3d968589d8 742
Kojto 90:cb3d968589d8 743 #define IS_RCC_CRS_SYNC_POLARITY(_POLARITY_) (((_POLARITY_) == RCC_CRS_SYNC_POLARITY_RISING) || \
Kojto 90:cb3d968589d8 744 ((_POLARITY_) == RCC_CRS_SYNC_POLARITY_FALLING))
Kojto 90:cb3d968589d8 745 /**
Kojto 90:cb3d968589d8 746 * @}
Kojto 90:cb3d968589d8 747 */
Kojto 90:cb3d968589d8 748
Kojto 90:cb3d968589d8 749 /** @defgroup RCCEx_CRS_ReloadValueDefault RCCEx CRS ReloadValueDefault
Kojto 90:cb3d968589d8 750 * @{
Kojto 90:cb3d968589d8 751 */
Kojto 90:cb3d968589d8 752 #define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
Kojto 90:cb3d968589d8 753 to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
Kojto 90:cb3d968589d8 754
Kojto 90:cb3d968589d8 755 #define IS_RCC_CRS_RELOADVALUE(_VALUE_) (((_VALUE_) <= 0xFFFF))
Kojto 90:cb3d968589d8 756 /**
Kojto 90:cb3d968589d8 757 * @}
Kojto 90:cb3d968589d8 758 */
Kojto 90:cb3d968589d8 759
Kojto 90:cb3d968589d8 760 /** @defgroup RCCEx_CRS_ErrorLimitDefault RCCEx CRS ErrorLimitDefault
Kojto 90:cb3d968589d8 761 * @{
Kojto 90:cb3d968589d8 762 */
Kojto 90:cb3d968589d8 763 #define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /*!< Default Frequency error limit */
Kojto 90:cb3d968589d8 764
Kojto 90:cb3d968589d8 765 #define IS_RCC_CRS_ERRORLIMIT(_VALUE_) (((_VALUE_) <= 0xFF))
Kojto 90:cb3d968589d8 766 /**
Kojto 90:cb3d968589d8 767 * @}
Kojto 90:cb3d968589d8 768 */
Kojto 90:cb3d968589d8 769
Kojto 90:cb3d968589d8 770 /** @defgroup RCCEx_CRS_HSI48CalibrationDefault RCCEx CRS HSI48CalibrationDefault
Kojto 90:cb3d968589d8 771 * @{
Kojto 90:cb3d968589d8 772 */
Kojto 90:cb3d968589d8 773 #define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
Kojto 90:cb3d968589d8 774 The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
Kojto 90:cb3d968589d8 775 corresponds to a higher output frequency */
Kojto 90:cb3d968589d8 776
Kojto 90:cb3d968589d8 777 #define IS_RCC_CRS_HSI48CALIBRATION(_VALUE_) (((_VALUE_) <= 0x3F))
Kojto 90:cb3d968589d8 778 /**
Kojto 90:cb3d968589d8 779 * @}
Kojto 90:cb3d968589d8 780 */
Kojto 90:cb3d968589d8 781
Kojto 90:cb3d968589d8 782 /** @defgroup RCCEx_CRS_FreqErrorDirection RCCEx CRS FreqErrorDirection
Kojto 90:cb3d968589d8 783 * @{
Kojto 90:cb3d968589d8 784 */
Kojto 90:cb3d968589d8 785 #define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /*!< Upcounting direction, the actual frequency is above the target */
Kojto 90:cb3d968589d8 786 #define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /*!< Downcounting direction, the actual frequency is below the target */
Kojto 90:cb3d968589d8 787
Kojto 90:cb3d968589d8 788 #define IS_RCC_CRS_FREQERRORDIR(_DIR_) (((_DIR_) == RCC_CRS_FREQERRORDIR_UP) || \
Kojto 90:cb3d968589d8 789 ((_DIR_) == RCC_CRS_FREQERRORDIR_DOWN))
Kojto 90:cb3d968589d8 790 /**
Kojto 90:cb3d968589d8 791 * @}
Kojto 90:cb3d968589d8 792 */
Kojto 90:cb3d968589d8 793
Kojto 90:cb3d968589d8 794 /** @defgroup RCCEx_CRS_Interrupt_Sources RCCEx CRS Interrupt Sources
Kojto 90:cb3d968589d8 795 * @{
Kojto 90:cb3d968589d8 796 */
Kojto 90:cb3d968589d8 797 #define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /*!< SYNC event OK */
Kojto 90:cb3d968589d8 798 #define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /*!< SYNC warning */
Kojto 90:cb3d968589d8 799 #define RCC_CRS_IT_ERR CRS_ISR_ERRF /*!< error */
Kojto 90:cb3d968589d8 800 #define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /*!< Expected SYNC */
Kojto 90:cb3d968589d8 801 #define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
Kojto 90:cb3d968589d8 802 #define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
Kojto 90:cb3d968589d8 803 #define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
Kojto 90:cb3d968589d8 804
Kojto 90:cb3d968589d8 805 /**
Kojto 90:cb3d968589d8 806 * @}
Kojto 90:cb3d968589d8 807 */
Kojto 90:cb3d968589d8 808
Kojto 90:cb3d968589d8 809 /** @defgroup RCCEx_CRS_Flags RCCEx CRS Flags
Kojto 90:cb3d968589d8 810 * @{
Kojto 90:cb3d968589d8 811 */
Kojto 90:cb3d968589d8 812 #define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
Kojto 90:cb3d968589d8 813 #define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
Kojto 90:cb3d968589d8 814 #define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
Kojto 90:cb3d968589d8 815 #define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
Kojto 90:cb3d968589d8 816 #define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /*!< Trimming overflow or underflow */
Kojto 90:cb3d968589d8 817 #define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /*!< SYNC error */
Kojto 90:cb3d968589d8 818 #define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /*!< SYNC missed*/
Kojto 90:cb3d968589d8 819
Kojto 90:cb3d968589d8 820 /**
Kojto 90:cb3d968589d8 821 * @}
Kojto 90:cb3d968589d8 822 */
Kojto 90:cb3d968589d8 823
Kojto 93:e188a91d3eaa 824 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 825 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 826 /* STM32F091xC || STM32F098xx */
Kojto 93:e188a91d3eaa 827
Kojto 90:cb3d968589d8 828 /**
Kojto 90:cb3d968589d8 829 * @}
Kojto 90:cb3d968589d8 830 */
Kojto 90:cb3d968589d8 831
Kojto 90:cb3d968589d8 832 /* Exported macros ------------------------------------------------------------*/
Kojto 90:cb3d968589d8 833 /** @defgroup RCCEx_Exported_Macros RCCEx Exported Macros
Kojto 90:cb3d968589d8 834 * @{
Kojto 90:cb3d968589d8 835 */
Kojto 90:cb3d968589d8 836
Kojto 90:cb3d968589d8 837 /** @defgroup RCCEx_Peripheral_Clock_Enable_Disable RCCEx_Peripheral_Clock_Enable_Disable
Kojto 90:cb3d968589d8 838 * @brief Enables or disables the AHB1 peripheral clock.
Kojto 90:cb3d968589d8 839 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 840 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 841 * using it.
Kojto 90:cb3d968589d8 842 * @{
Kojto 90:cb3d968589d8 843 */
Kojto 93:e188a91d3eaa 844 #if defined(STM32F030x6) || defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 845 defined(STM32F051x8) || defined(STM32F058xx) || defined(STM32F070xB) || \
Kojto 90:cb3d968589d8 846 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 847 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 848
Kojto 90:cb3d968589d8 849 #define __GPIOD_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIODEN))
Kojto 90:cb3d968589d8 850
Kojto 90:cb3d968589d8 851 #define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto 90:cb3d968589d8 852
Kojto 93:e188a91d3eaa 853 #endif /* STM32F030x6 || STM32F030x8 || */
Kojto 93:e188a91d3eaa 854 /* STM32F051x8 || STM32F058xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 855 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 856 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 857
Kojto 93:e188a91d3eaa 858 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 859 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 860
Kojto 90:cb3d968589d8 861 #define __GPIOE_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_GPIOEEN))
Kojto 90:cb3d968589d8 862
Kojto 90:cb3d968589d8 863 #define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto 90:cb3d968589d8 864
Kojto 93:e188a91d3eaa 865 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 866 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 867
Kojto 90:cb3d968589d8 868 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 869 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 870 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 871 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 872
Kojto 90:cb3d968589d8 873 #define __TSC_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_TSCEN))
Kojto 90:cb3d968589d8 874
Kojto 90:cb3d968589d8 875 #define __TSC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_TSCEN))
Kojto 90:cb3d968589d8 876
Kojto 90:cb3d968589d8 877 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 878 /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 879 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 880 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 881
Kojto 90:cb3d968589d8 882 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 883
Kojto 90:cb3d968589d8 884 #define __DMA2_CLK_ENABLE() (RCC->AHBENR |= (RCC_AHBENR_DMA2EN))
Kojto 90:cb3d968589d8 885
Kojto 90:cb3d968589d8 886 #define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto 90:cb3d968589d8 887
Kojto 90:cb3d968589d8 888 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 889
Kojto 90:cb3d968589d8 890 /** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto 90:cb3d968589d8 891 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 892 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 893 * using it.
Kojto 90:cb3d968589d8 894 */
Kojto 90:cb3d968589d8 895 #if defined(STM32F030x8) || \
Kojto 90:cb3d968589d8 896 defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 897 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 898 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 899 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 900
Kojto 90:cb3d968589d8 901 #define __USART2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART2EN))
Kojto 90:cb3d968589d8 902 #define __SPI2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_SPI2EN))
Kojto 90:cb3d968589d8 903
Kojto 90:cb3d968589d8 904 #define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto 90:cb3d968589d8 905 #define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto 90:cb3d968589d8 906
Kojto 90:cb3d968589d8 907 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 908 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 909 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 910 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 911
Kojto 90:cb3d968589d8 912 #if defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 90:cb3d968589d8 913 defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 914 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 915 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 916 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 917
Kojto 90:cb3d968589d8 918 #define __TIM2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM2EN))
Kojto 90:cb3d968589d8 919
Kojto 90:cb3d968589d8 920 #define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto 90:cb3d968589d8 921
Kojto 90:cb3d968589d8 922 #endif /* STM32F031x6 || STM32F038xx || */
Kojto 90:cb3d968589d8 923 /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 924 /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 925 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 926 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 927
Kojto 90:cb3d968589d8 928 #if defined(STM32F030x8) || \
Kojto 90:cb3d968589d8 929 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 930 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 931 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 932
Kojto 90:cb3d968589d8 933 #define __TIM6_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM6EN))
Kojto 90:cb3d968589d8 934 #define __I2C2_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_I2C2EN))
Kojto 90:cb3d968589d8 935
Kojto 90:cb3d968589d8 936 #define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto 90:cb3d968589d8 937 #define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto 90:cb3d968589d8 938
Kojto 90:cb3d968589d8 939 #endif /* STM32F030x8 || */
Kojto 90:cb3d968589d8 940 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 941 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 942 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 943
Kojto 90:cb3d968589d8 944 #if defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 945 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 946 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 947
Kojto 90:cb3d968589d8 948 #define __DAC1_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_DACEN))
Kojto 90:cb3d968589d8 949
Kojto 90:cb3d968589d8 950 #define __DAC1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto 90:cb3d968589d8 951
Kojto 90:cb3d968589d8 952 #endif /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 953 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 954 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 955
Kojto 90:cb3d968589d8 956 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 957 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 958 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 959 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 960
Kojto 90:cb3d968589d8 961 #define __CEC_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CECEN))
Kojto 90:cb3d968589d8 962
Kojto 90:cb3d968589d8 963 #define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto 90:cb3d968589d8 964
Kojto 90:cb3d968589d8 965 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 966 /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 967 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 968 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 969
Kojto 93:e188a91d3eaa 970 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 971 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 972
Kojto 90:cb3d968589d8 973 #define __TIM7_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_TIM7EN))
Kojto 90:cb3d968589d8 974 #define __USART3_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART3EN))
Kojto 90:cb3d968589d8 975 #define __USART4_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART4EN))
Kojto 90:cb3d968589d8 976
Kojto 90:cb3d968589d8 977 #define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto 90:cb3d968589d8 978 #define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto 90:cb3d968589d8 979 #define __USART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART4EN))
Kojto 90:cb3d968589d8 980
Kojto 93:e188a91d3eaa 981 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 982 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 983
Kojto 93:e188a91d3eaa 984 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 985 defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
Kojto 90:cb3d968589d8 986
Kojto 90:cb3d968589d8 987 #define __USB_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USBEN))
Kojto 90:cb3d968589d8 988
Kojto 90:cb3d968589d8 989 #define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto 90:cb3d968589d8 990
Kojto 93:e188a91d3eaa 991 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 992 /* STM32F072xB || STM32F078xx || STM32F070xB */
Kojto 90:cb3d968589d8 993
Kojto 90:cb3d968589d8 994 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
Kojto 90:cb3d968589d8 995 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 996
Kojto 90:cb3d968589d8 997 #define __CAN_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CANEN))
Kojto 90:cb3d968589d8 998 #define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
Kojto 90:cb3d968589d8 999
Kojto 90:cb3d968589d8 1000 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
Kojto 90:cb3d968589d8 1001 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1002
Kojto 90:cb3d968589d8 1003 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1004 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1005 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1006
Kojto 90:cb3d968589d8 1007 #define __CRS_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_CRSEN))
Kojto 90:cb3d968589d8 1008
Kojto 90:cb3d968589d8 1009 #define __CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
Kojto 90:cb3d968589d8 1010
Kojto 90:cb3d968589d8 1011 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1012 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1013 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1014
Kojto 93:e188a91d3eaa 1015 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1016
Kojto 90:cb3d968589d8 1017 #define __USART5_CLK_ENABLE() (RCC->APB1ENR |= (RCC_APB1ENR_USART5EN))
Kojto 90:cb3d968589d8 1018
Kojto 90:cb3d968589d8 1019 #define __USART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART5EN))
Kojto 90:cb3d968589d8 1020
Kojto 93:e188a91d3eaa 1021 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1022
Kojto 90:cb3d968589d8 1023 /** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto 90:cb3d968589d8 1024 * @note After reset, the peripheral clock (used for registers read/write access)
Kojto 90:cb3d968589d8 1025 * is disabled and the application software has to enable this clock before
Kojto 90:cb3d968589d8 1026 * using it.
Kojto 90:cb3d968589d8 1027 */
Kojto 93:e188a91d3eaa 1028 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 90:cb3d968589d8 1029 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1030 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1031 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1032
Kojto 90:cb3d968589d8 1033 #define __TIM15_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_TIM15EN))
Kojto 90:cb3d968589d8 1034
Kojto 90:cb3d968589d8 1035 #define __TIM15_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM15EN))
Kojto 90:cb3d968589d8 1036
Kojto 93:e188a91d3eaa 1037 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 90:cb3d968589d8 1038 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1039 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1040 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1041
Kojto 93:e188a91d3eaa 1042 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1043
Kojto 93:e188a91d3eaa 1044 #define __USART6_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART6EN))
Kojto 93:e188a91d3eaa 1045
Kojto 93:e188a91d3eaa 1046 #define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
Kojto 93:e188a91d3eaa 1047
Kojto 93:e188a91d3eaa 1048 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1049
Kojto 90:cb3d968589d8 1050 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1051
Kojto 90:cb3d968589d8 1052 #define __USART7_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART7EN))
Kojto 90:cb3d968589d8 1053 #define __USART8_CLK_ENABLE() (RCC->APB2ENR |= (RCC_APB2ENR_USART8EN))
Kojto 90:cb3d968589d8 1054
Kojto 90:cb3d968589d8 1055 #define __USART7_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART7EN))
Kojto 90:cb3d968589d8 1056 #define __USART8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART8EN))
Kojto 90:cb3d968589d8 1057
Kojto 90:cb3d968589d8 1058 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1059
Kojto 90:cb3d968589d8 1060 /**
Kojto 90:cb3d968589d8 1061 * @}
Kojto 90:cb3d968589d8 1062 */
Kojto 90:cb3d968589d8 1063
Kojto 90:cb3d968589d8 1064
Kojto 90:cb3d968589d8 1065 /** @defgroup RCCEx_Force_Release_Peripheral_Reset RCCEx Force Release Peripheral Reset
Kojto 90:cb3d968589d8 1066 * @brief Forces or releases peripheral reset.
Kojto 90:cb3d968589d8 1067 * @{
Kojto 90:cb3d968589d8 1068 */
Kojto 90:cb3d968589d8 1069
Kojto 90:cb3d968589d8 1070 /** @brief Force or release AHB peripheral reset.
Kojto 90:cb3d968589d8 1071 */
Kojto 93:e188a91d3eaa 1072 #if defined(STM32F030x6) || defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 1073 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1074 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1075 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1076
Kojto 90:cb3d968589d8 1077 #define __GPIOD_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIODRST))
Kojto 90:cb3d968589d8 1078
Kojto 90:cb3d968589d8 1079 #define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto 90:cb3d968589d8 1080
Kojto 90:cb3d968589d8 1081 #endif /* STM32F030x6 || STM32F030x8 || */
Kojto 90:cb3d968589d8 1082 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1083 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1084 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1085
Kojto 93:e188a91d3eaa 1086 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1087 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1088
Kojto 90:cb3d968589d8 1089 #define __GPIOE_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_GPIOERST))
Kojto 90:cb3d968589d8 1090
Kojto 90:cb3d968589d8 1091 #define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto 90:cb3d968589d8 1092
Kojto 93:e188a91d3eaa 1093 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1094 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1095
Kojto 90:cb3d968589d8 1096 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1097 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 1098 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1099 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1100
Kojto 90:cb3d968589d8 1101 #define __TSC_FORCE_RESET() (RCC->AHBRSTR |= (RCC_AHBRSTR_TSCRST))
Kojto 90:cb3d968589d8 1102
Kojto 90:cb3d968589d8 1103 #define __TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_TSCRST))
Kojto 90:cb3d968589d8 1104
Kojto 90:cb3d968589d8 1105 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1106 /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 1107 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1108 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1109
Kojto 90:cb3d968589d8 1110 /** @brief Force or release APB1 peripheral reset.
Kojto 90:cb3d968589d8 1111 */
Kojto 90:cb3d968589d8 1112 #if defined(STM32F030x8) || \
Kojto 93:e188a91d3eaa 1113 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 90:cb3d968589d8 1114 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1115 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1116 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1117
Kojto 90:cb3d968589d8 1118 #define __USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
Kojto 90:cb3d968589d8 1119 #define __SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
Kojto 90:cb3d968589d8 1120
Kojto 90:cb3d968589d8 1121 #define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto 90:cb3d968589d8 1122 #define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto 90:cb3d968589d8 1123
Kojto 93:e188a91d3eaa 1124 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 90:cb3d968589d8 1125 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1126 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1127 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1128
Kojto 90:cb3d968589d8 1129 #if defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 90:cb3d968589d8 1130 defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1131 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 1132 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1133 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1134
Kojto 90:cb3d968589d8 1135 #define __TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
Kojto 90:cb3d968589d8 1136
Kojto 90:cb3d968589d8 1137 #define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto 90:cb3d968589d8 1138
Kojto 90:cb3d968589d8 1139 #endif /* STM32F031x6 || STM32F038xx || */
Kojto 90:cb3d968589d8 1140 /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1141 /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 1142 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1143 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1144
Kojto 90:cb3d968589d8 1145 #if defined(STM32F030x8) || \
Kojto 90:cb3d968589d8 1146 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1147 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) ||\
Kojto 93:e188a91d3eaa 1148 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1149
Kojto 90:cb3d968589d8 1150 #define __TIM6_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM6RST))
Kojto 90:cb3d968589d8 1151 #define __I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
Kojto 90:cb3d968589d8 1152
Kojto 90:cb3d968589d8 1153 #define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto 90:cb3d968589d8 1154 #define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto 90:cb3d968589d8 1155
Kojto 90:cb3d968589d8 1156 #endif /* STM32F030x8 || */
Kojto 90:cb3d968589d8 1157 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1158 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1159 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1160
Kojto 90:cb3d968589d8 1161 #if defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 1162 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1163 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1164
Kojto 90:cb3d968589d8 1165 #define __DAC1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_DACRST))
Kojto 90:cb3d968589d8 1166
Kojto 90:cb3d968589d8 1167 #define __DAC1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto 90:cb3d968589d8 1168
Kojto 90:cb3d968589d8 1169 #endif /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 1170 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1171 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1172
Kojto 90:cb3d968589d8 1173 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1174 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 1175 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1176 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1177
Kojto 90:cb3d968589d8 1178 #define __CEC_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CECRST))
Kojto 90:cb3d968589d8 1179
Kojto 90:cb3d968589d8 1180 #define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto 90:cb3d968589d8 1181
Kojto 90:cb3d968589d8 1182 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1183 /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 1184 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1185 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1186
Kojto 93:e188a91d3eaa 1187 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1188 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1189
Kojto 90:cb3d968589d8 1190 #define __TIM7_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM7RST))
Kojto 90:cb3d968589d8 1191 #define __USART3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART3RST))
Kojto 90:cb3d968589d8 1192 #define __USART4_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART4RST))
Kojto 90:cb3d968589d8 1193
Kojto 90:cb3d968589d8 1194 #define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto 90:cb3d968589d8 1195 #define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto 90:cb3d968589d8 1196 #define __USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART4RST))
Kojto 90:cb3d968589d8 1197
Kojto 93:e188a91d3eaa 1198 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1199 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1200
Kojto 93:e188a91d3eaa 1201 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 1202 defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB)
Kojto 90:cb3d968589d8 1203
Kojto 90:cb3d968589d8 1204 #define __USB_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USBRST))
Kojto 90:cb3d968589d8 1205
Kojto 90:cb3d968589d8 1206 #define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto 90:cb3d968589d8 1207
Kojto 93:e188a91d3eaa 1208 #endif /* STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 1209 /* STM32F072xB || STM32F078xx || STM32F070xB */
Kojto 90:cb3d968589d8 1210
Kojto 90:cb3d968589d8 1211 #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) || \
Kojto 90:cb3d968589d8 1212 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1213
Kojto 90:cb3d968589d8 1214 #define __CAN_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CANRST))
Kojto 90:cb3d968589d8 1215
Kojto 90:cb3d968589d8 1216 #define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
Kojto 90:cb3d968589d8 1217
Kojto 90:cb3d968589d8 1218 #endif /* STM32F042x6 || STM32F048xx || STM32F072xB || */
Kojto 90:cb3d968589d8 1219 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1220
Kojto 90:cb3d968589d8 1221 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1222 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1223 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1224
Kojto 90:cb3d968589d8 1225 #define __CRS_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_CRSRST))
Kojto 90:cb3d968589d8 1226
Kojto 90:cb3d968589d8 1227 #define __CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
Kojto 90:cb3d968589d8 1228
Kojto 90:cb3d968589d8 1229 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1230 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1231 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1232
Kojto 93:e188a91d3eaa 1233 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1234
Kojto 90:cb3d968589d8 1235 #define __USART5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART5RST))
Kojto 90:cb3d968589d8 1236
Kojto 90:cb3d968589d8 1237 #define __USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART5RST))
Kojto 90:cb3d968589d8 1238
Kojto 93:e188a91d3eaa 1239 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1240
Kojto 90:cb3d968589d8 1241
Kojto 90:cb3d968589d8 1242 /** @brief Force or release APB2 peripheral reset.
Kojto 90:cb3d968589d8 1243 */
Kojto 93:e188a91d3eaa 1244 #if defined(STM32F030x8) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 90:cb3d968589d8 1245 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 93:e188a91d3eaa 1246 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1247 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1248
Kojto 90:cb3d968589d8 1249 #define __TIM15_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM15RST))
Kojto 90:cb3d968589d8 1250
Kojto 90:cb3d968589d8 1251 #define __TIM15_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM15RST))
Kojto 90:cb3d968589d8 1252
Kojto 93:e188a91d3eaa 1253 #endif /* STM32F030x8 || STM32F042x6 || STM32F048xx || STM32F070x6 || */
Kojto 90:cb3d968589d8 1254 /* STM32F051x8 || STM32F058xx || */
Kojto 93:e188a91d3eaa 1255 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1256 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1257
Kojto 93:e188a91d3eaa 1258 #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 93:e188a91d3eaa 1259
Kojto 93:e188a91d3eaa 1260 #define __USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
Kojto 93:e188a91d3eaa 1261
Kojto 93:e188a91d3eaa 1262 #define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
Kojto 93:e188a91d3eaa 1263
Kojto 93:e188a91d3eaa 1264 #endif /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 90:cb3d968589d8 1265
Kojto 90:cb3d968589d8 1266 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1267
Kojto 90:cb3d968589d8 1268 #define __USART7_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART7RST))
Kojto 90:cb3d968589d8 1269 #define __USART8_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART8RST))
Kojto 90:cb3d968589d8 1270
Kojto 90:cb3d968589d8 1271 #define __USART7_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART7RST))
Kojto 90:cb3d968589d8 1272 #define __USART8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART8RST))
Kojto 90:cb3d968589d8 1273
Kojto 90:cb3d968589d8 1274 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1275
Kojto 90:cb3d968589d8 1276 /**
Kojto 90:cb3d968589d8 1277 * @}
Kojto 90:cb3d968589d8 1278 */
Kojto 90:cb3d968589d8 1279
Kojto 90:cb3d968589d8 1280 /** @defgroup RCCEx_HSI48_Enable_Disable RCCEx HSI48 Enable Disable
Kojto 90:cb3d968589d8 1281 * @brief Macros to enable or disable the Internal 48Mhz High Speed oscillator (HSI48).
Kojto 90:cb3d968589d8 1282 * @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
Kojto 90:cb3d968589d8 1283 * @note HSI48 can not be stopped if it is used as system clock source. In this case,
Kojto 90:cb3d968589d8 1284 * you have to select another source of the system clock then stop the HSI14.
Kojto 90:cb3d968589d8 1285 * @note After enabling the HSI48 with __HAL_RCC_HSI48_ENABLE(), the application software
Kojto 90:cb3d968589d8 1286 * should wait on HSI48RDY flag to be set indicating that HSI48 clock is stable and can be
Kojto 90:cb3d968589d8 1287 * used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
Kojto 90:cb3d968589d8 1288 * @note When the HSI48 is stopped, HSI48RDY flag goes low after 6 HSI48 oscillator
Kojto 90:cb3d968589d8 1289 * clock cycles.
Kojto 90:cb3d968589d8 1290 * @{
Kojto 90:cb3d968589d8 1291 */
Kojto 90:cb3d968589d8 1292 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1293 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1294 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1295
Kojto 90:cb3d968589d8 1296 #define __HAL_RCC_HSI48_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI48ON)
Kojto 90:cb3d968589d8 1297 #define __HAL_RCC_HSI48_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI48ON)
Kojto 90:cb3d968589d8 1298
Kojto 90:cb3d968589d8 1299 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Kojto 90:cb3d968589d8 1300 * @retval The clock source can be one of the following values:
Kojto 90:cb3d968589d8 1301 * @arg RCC_HSI48_ON: HSI48 enabled
Kojto 90:cb3d968589d8 1302 * @arg RCC_HSI48_OFF: HSI48 disabled
Kojto 90:cb3d968589d8 1303 */
Kojto 90:cb3d968589d8 1304 #define __HAL_RCC_GET_HSI48_STATE() \
Kojto 90:cb3d968589d8 1305 (((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CR2_HSI48ON)) != RESET) ? RCC_HSI48_ON : RCC_HSI48_OFF)
Kojto 90:cb3d968589d8 1306
Kojto 90:cb3d968589d8 1307 #else
Kojto 90:cb3d968589d8 1308
Kojto 90:cb3d968589d8 1309 /** @brief Macro to get the Internal 48Mhz High Speed oscillator (HSI48) state.
Kojto 90:cb3d968589d8 1310 * @retval The clock source can be one of the following values:
Kojto 90:cb3d968589d8 1311 * @arg RCC_HSI_OFF: HSI48 disabled
Kojto 90:cb3d968589d8 1312 */
Kojto 90:cb3d968589d8 1313 #define __HAL_RCC_GET_HSI48_STATE() RCC_HSI_OFF
Kojto 90:cb3d968589d8 1314
Kojto 90:cb3d968589d8 1315 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1316 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1317 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1318
Kojto 90:cb3d968589d8 1319 /**
Kojto 90:cb3d968589d8 1320 * @}
Kojto 90:cb3d968589d8 1321 */
Kojto 90:cb3d968589d8 1322
Kojto 90:cb3d968589d8 1323 /** @defgroup RCCEx_Peripheral_Clock_Source_Config RCCEx Peripheral Clock Source Config
Kojto 90:cb3d968589d8 1324 * @{
Kojto 90:cb3d968589d8 1325 */
Kojto 93:e188a91d3eaa 1326 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 93:e188a91d3eaa 1327 defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1328 defined(STM32F070x6) || defined(STM32F070xB)
Kojto 90:cb3d968589d8 1329
Kojto 90:cb3d968589d8 1330 /** @brief Macro to configure the USB clock (USBCLK).
Kojto 90:cb3d968589d8 1331 * @param __USBCLKSource__: specifies the USB clock source.
Kojto 90:cb3d968589d8 1332 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1333 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
Kojto 90:cb3d968589d8 1334 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto 90:cb3d968589d8 1335 */
Kojto 90:cb3d968589d8 1336 #define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
Kojto 90:cb3d968589d8 1337 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USBSW, (uint32_t)(__USBCLKSource__))
Kojto 90:cb3d968589d8 1338
Kojto 90:cb3d968589d8 1339 /** @brief Macro to get the USB clock source.
Kojto 90:cb3d968589d8 1340 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1341 * @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock (not available for STM32F070x6 & STM32F070xB)
Kojto 90:cb3d968589d8 1342 * @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
Kojto 90:cb3d968589d8 1343 */
Kojto 90:cb3d968589d8 1344 #define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USBSW)))
Kojto 90:cb3d968589d8 1345
Kojto 90:cb3d968589d8 1346 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1347 /* STM32F072xB || STM32F078xx || */
Kojto 93:e188a91d3eaa 1348 /* STM32F070x6 || STM32F070xB */
Kojto 90:cb3d968589d8 1349
Kojto 90:cb3d968589d8 1350 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1351 defined(STM32F051x8) || defined(STM32F058xx) || \
Kojto 90:cb3d968589d8 1352 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1353 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1354
Kojto 90:cb3d968589d8 1355 /** @brief Macro to configure the CEC clock.
Kojto 90:cb3d968589d8 1356 * @param __CECCLKSource__: specifies the CEC clock source.
Kojto 90:cb3d968589d8 1357 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1358 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 90:cb3d968589d8 1359 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 90:cb3d968589d8 1360 */
Kojto 90:cb3d968589d8 1361 #define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
Kojto 90:cb3d968589d8 1362 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Kojto 90:cb3d968589d8 1363
Kojto 90:cb3d968589d8 1364 /** @brief Macro to get the HDMI CEC clock source.
Kojto 90:cb3d968589d8 1365 * @retval The clock source can be one of the following values:
Kojto 90:cb3d968589d8 1366 * @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto 90:cb3d968589d8 1367 * @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto 90:cb3d968589d8 1368 */
Kojto 90:cb3d968589d8 1369 #define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Kojto 90:cb3d968589d8 1370
Kojto 90:cb3d968589d8 1371 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1372 /* STM32F051x8 || STM32F058xx || */
Kojto 90:cb3d968589d8 1373 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1374 /* STM32F091xC || defined(STM32F098xx) */
Kojto 90:cb3d968589d8 1375
Kojto 90:cb3d968589d8 1376 #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \
Kojto 93:e188a91d3eaa 1377 defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F070x6) || \
Kojto 93:e188a91d3eaa 1378 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || defined(STM32F070xB) || \
Kojto 93:e188a91d3eaa 1379 defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F030xC)
Kojto 90:cb3d968589d8 1380
Kojto 90:cb3d968589d8 1381 /** @brief Macro to configure the MCO clock.
Kojto 90:cb3d968589d8 1382 * @param __MCOCLKSource__: specifies the MCO clock source.
Kojto 90:cb3d968589d8 1383 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1384 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto 90:cb3d968589d8 1385 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto 90:cb3d968589d8 1386 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto 90:cb3d968589d8 1387 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto 90:cb3d968589d8 1388 * @arg RCC_MCOSOURCE_PLLCLK_NODIV: PLLCLK selected as MCO clock
Kojto 90:cb3d968589d8 1389 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto 90:cb3d968589d8 1390 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto 90:cb3d968589d8 1391 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
Kojto 90:cb3d968589d8 1392 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
Kojto 90:cb3d968589d8 1393 * @param __MCODiv__: specifies the MCO clock prescaler.
Kojto 90:cb3d968589d8 1394 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1395 * @arg RCC_MCO_DIV1: MCO clock source is divided by 1
Kojto 90:cb3d968589d8 1396 * @arg RCC_MCO_DIV2: MCO clock source is divided by 2
Kojto 90:cb3d968589d8 1397 * @arg RCC_MCO_DIV4: MCO clock source is divided by 4
Kojto 90:cb3d968589d8 1398 * @arg RCC_MCO_DIV8: MCO clock source is divided by 8
Kojto 90:cb3d968589d8 1399 * @arg RCC_MCO_DIV16: MCO clock source is divided by 16
Kojto 90:cb3d968589d8 1400 * @arg RCC_MCO_DIV32: MCO clock source is divided by 32
Kojto 90:cb3d968589d8 1401 * @arg RCC_MCO_DIV64: MCO clock source is divided by 64
Kojto 90:cb3d968589d8 1402 * @arg RCC_MCO_DIV128: MCO clock source is divided by 128
Kojto 90:cb3d968589d8 1403 */
Kojto 90:cb3d968589d8 1404 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto 90:cb3d968589d8 1405 MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO | RCC_CFGR_MCOPRE), ((__MCOCLKSource__) | (__MCODiv__)))
Kojto 90:cb3d968589d8 1406 #else
Kojto 90:cb3d968589d8 1407
Kojto 90:cb3d968589d8 1408 /** @brief Macro to configure the MCO clock.
Kojto 90:cb3d968589d8 1409 * @param __MCOCLKSource__: specifies the MCO clock source.
Kojto 90:cb3d968589d8 1410 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1411 * @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto 90:cb3d968589d8 1412 * @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto 90:cb3d968589d8 1413 * @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto 90:cb3d968589d8 1414 * @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto 90:cb3d968589d8 1415 * @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto 90:cb3d968589d8 1416 * @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto 90:cb3d968589d8 1417 * @arg RCC_MCOSOURCE_HSI14: HSI14 selected as MCO clock
Kojto 90:cb3d968589d8 1418 * @arg RCC_MCOSOURCE_HSI48: HSI48 selected as MCO clock
Kojto 90:cb3d968589d8 1419 * @param __MCODiv__: specifies the MCO clock prescaler.
Kojto 90:cb3d968589d8 1420 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1421 * @arg RCC_MCO_NODIV: No division applied on MCO clock source
Kojto 90:cb3d968589d8 1422 */
Kojto 90:cb3d968589d8 1423 #define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto 90:cb3d968589d8 1424 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, __MCOCLKSource__)
Kojto 90:cb3d968589d8 1425
Kojto 93:e188a91d3eaa 1426 #endif /* STM32F030x6 || STM32F031x6 || STM32F038xx || STM32F070x6 || */
Kojto 93:e188a91d3eaa 1427 /* STM32F042x6 || STM32F048xx || */
Kojto 93:e188a91d3eaa 1428 /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F070xB || */
Kojto 93:e188a91d3eaa 1429 /* STM32F091xC || STM32F098xx || STM32F030xC */
Kojto 93:e188a91d3eaa 1430
Kojto 93:e188a91d3eaa 1431 #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 93:e188a91d3eaa 1432 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 93:e188a91d3eaa 1433 /** @brief Macro to configure the USART2 clock (USART2CLK).
Kojto 93:e188a91d3eaa 1434 * @param __USART2CLKSource__: specifies the USART2 clock source.
Kojto 93:e188a91d3eaa 1435 * This parameter can be one of the following values:
Kojto 93:e188a91d3eaa 1436 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 93:e188a91d3eaa 1437 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 93:e188a91d3eaa 1438 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 93:e188a91d3eaa 1439 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 93:e188a91d3eaa 1440 */
Kojto 93:e188a91d3eaa 1441 #define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
Kojto 93:e188a91d3eaa 1442 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART2SW, (uint32_t)(__USART2CLKSource__))
Kojto 93:e188a91d3eaa 1443
Kojto 93:e188a91d3eaa 1444 /** @brief Macro to get the USART2 clock source.
Kojto 93:e188a91d3eaa 1445 * @retval The clock source can be one of the following values:
Kojto 93:e188a91d3eaa 1446 * @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
Kojto 93:e188a91d3eaa 1447 * @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
Kojto 93:e188a91d3eaa 1448 * @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
Kojto 93:e188a91d3eaa 1449 * @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
Kojto 93:e188a91d3eaa 1450 */
Kojto 93:e188a91d3eaa 1451 #define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART2SW)))
Kojto 93:e188a91d3eaa 1452 #endif /* STM32F071xB || STM32F072xB || STM32F078xx || STM32F091xC || STM32F098xx*/
Kojto 90:cb3d968589d8 1453
Kojto 90:cb3d968589d8 1454 #if defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1455 /** @brief Macro to configure the USART3 clock (USART3CLK).
Kojto 90:cb3d968589d8 1456 * @param __USART3CLKSource__: specifies the USART3 clock source.
Kojto 90:cb3d968589d8 1457 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1458 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 90:cb3d968589d8 1459 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 90:cb3d968589d8 1460 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 90:cb3d968589d8 1461 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 90:cb3d968589d8 1462 */
Kojto 90:cb3d968589d8 1463 #define __HAL_RCC_USART3_CONFIG(__USART3CLKSource__) \
Kojto 90:cb3d968589d8 1464 MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART3SW, (uint32_t)(__USART3CLKSource__))
Kojto 90:cb3d968589d8 1465
Kojto 90:cb3d968589d8 1466 /** @brief Macro to get the USART3 clock source.
Kojto 90:cb3d968589d8 1467 * @retval The clock source can be one of the following values:
Kojto 90:cb3d968589d8 1468 * @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
Kojto 90:cb3d968589d8 1469 * @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
Kojto 90:cb3d968589d8 1470 * @arg RCC_USART3CLKSOURCE_SYSCLK: System Clock selected as USART3 clock
Kojto 90:cb3d968589d8 1471 * @arg RCC_USART3CLKSOURCE_LSE: LSE selected as USART3 clock
Kojto 90:cb3d968589d8 1472 */
Kojto 90:cb3d968589d8 1473 #define __HAL_RCC_GET_USART3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART3SW)))
Kojto 90:cb3d968589d8 1474
Kojto 93:e188a91d3eaa 1475 #endif /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1476 /**
Kojto 90:cb3d968589d8 1477 * @}
Kojto 90:cb3d968589d8 1478 */
Kojto 90:cb3d968589d8 1479
Kojto 90:cb3d968589d8 1480 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1481 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1482 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1483
Kojto 90:cb3d968589d8 1484 /** @defgroup RCCEx_IT_And_Flag RCCEx IT and Flag
Kojto 90:cb3d968589d8 1485 * @{
Kojto 90:cb3d968589d8 1486 */
Kojto 90:cb3d968589d8 1487 /* Interrupt & Flag management */
Kojto 90:cb3d968589d8 1488
Kojto 90:cb3d968589d8 1489 /**
Kojto 90:cb3d968589d8 1490 * @brief Enables the specified CRS interrupts.
Kojto 90:cb3d968589d8 1491 * @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
Kojto 90:cb3d968589d8 1492 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 1493 * @arg RCC_CRS_IT_SYNCOK
Kojto 90:cb3d968589d8 1494 * @arg RCC_CRS_IT_SYNCWARN
Kojto 90:cb3d968589d8 1495 * @arg RCC_CRS_IT_ERR
Kojto 90:cb3d968589d8 1496 * @arg RCC_CRS_IT_ESYNC
Kojto 90:cb3d968589d8 1497 * @retval None
Kojto 90:cb3d968589d8 1498 */
Kojto 90:cb3d968589d8 1499 #define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR |= (__INTERRUPT__))
Kojto 90:cb3d968589d8 1500
Kojto 90:cb3d968589d8 1501 /**
Kojto 90:cb3d968589d8 1502 * @brief Disables the specified CRS interrupts.
Kojto 90:cb3d968589d8 1503 * @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
Kojto 90:cb3d968589d8 1504 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 1505 * @arg RCC_CRS_IT_SYNCOK
Kojto 90:cb3d968589d8 1506 * @arg RCC_CRS_IT_SYNCWARN
Kojto 90:cb3d968589d8 1507 * @arg RCC_CRS_IT_ERR
Kojto 90:cb3d968589d8 1508 * @arg RCC_CRS_IT_ESYNC
Kojto 90:cb3d968589d8 1509 * @retval None
Kojto 90:cb3d968589d8 1510 */
Kojto 90:cb3d968589d8 1511 #define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
Kojto 90:cb3d968589d8 1512
Kojto 90:cb3d968589d8 1513 /** @brief Check the CRS's interrupt has occurred or not.
Kojto 90:cb3d968589d8 1514 * @param __INTERRUPT__: specifies the CRS interrupt source to check.
Kojto 90:cb3d968589d8 1515 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1516 * @arg RCC_CRS_IT_SYNCOK
Kojto 90:cb3d968589d8 1517 * @arg RCC_CRS_IT_SYNCWARN
Kojto 90:cb3d968589d8 1518 * @arg RCC_CRS_IT_ERR
Kojto 90:cb3d968589d8 1519 * @arg RCC_CRS_IT_ESYNC
Kojto 90:cb3d968589d8 1520 * @retval The new state of __INTERRUPT__ (SET or RESET).
Kojto 90:cb3d968589d8 1521 */
Kojto 90:cb3d968589d8 1522 #define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
Kojto 90:cb3d968589d8 1523
Kojto 90:cb3d968589d8 1524 /** @brief Clear the CRS's interrupt pending bits
Kojto 90:cb3d968589d8 1525 * bits to clear the selected interrupt pending bits.
Kojto 90:cb3d968589d8 1526 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto 90:cb3d968589d8 1527 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 1528 * @arg RCC_CRS_IT_SYNCOK
Kojto 90:cb3d968589d8 1529 * @arg RCC_CRS_IT_SYNCWARN
Kojto 90:cb3d968589d8 1530 * @arg RCC_CRS_IT_ERR
Kojto 90:cb3d968589d8 1531 * @arg RCC_CRS_IT_ESYNC
Kojto 90:cb3d968589d8 1532 * @arg RCC_CRS_IT_TRIMOVF
Kojto 90:cb3d968589d8 1533 * @arg RCC_CRS_IT_SYNCERR
Kojto 90:cb3d968589d8 1534 * @arg RCC_CRS_IT_SYNCMISS
Kojto 90:cb3d968589d8 1535 */
Kojto 90:cb3d968589d8 1536 /* CRS IT Error Mask */
Kojto 90:cb3d968589d8 1537 #define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF | RCC_CRS_IT_SYNCERR | RCC_CRS_IT_SYNCMISS))
Kojto 90:cb3d968589d8 1538
Kojto 90:cb3d968589d8 1539 #define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
Kojto 90:cb3d968589d8 1540 (CRS->ICR |= (__INTERRUPT__)))
Kojto 90:cb3d968589d8 1541
Kojto 90:cb3d968589d8 1542 /**
Kojto 90:cb3d968589d8 1543 * @brief Checks whether the specified CRS flag is set or not.
Kojto 90:cb3d968589d8 1544 * @param _FLAG_: specifies the flag to check.
Kojto 90:cb3d968589d8 1545 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1546 * @arg RCC_CRS_FLAG_SYNCOK
Kojto 90:cb3d968589d8 1547 * @arg RCC_CRS_FLAG_SYNCWARN
Kojto 90:cb3d968589d8 1548 * @arg RCC_CRS_FLAG_ERR
Kojto 90:cb3d968589d8 1549 * @arg RCC_CRS_FLAG_ESYNC
Kojto 90:cb3d968589d8 1550 * @arg RCC_CRS_FLAG_TRIMOVF
Kojto 90:cb3d968589d8 1551 * @arg RCC_CRS_FLAG_SYNCERR
Kojto 90:cb3d968589d8 1552 * @arg RCC_CRS_FLAG_SYNCMISS
Kojto 90:cb3d968589d8 1553 * @retval The new state of _FLAG_ (TRUE or FALSE).
Kojto 90:cb3d968589d8 1554 */
Kojto 90:cb3d968589d8 1555 #define __HAL_RCC_CRS_GET_FLAG(_FLAG_) ((CRS->ISR & (_FLAG_)) == (_FLAG_))
Kojto 90:cb3d968589d8 1556
Kojto 90:cb3d968589d8 1557 /**
Kojto 90:cb3d968589d8 1558 * @brief Clears the CRS specified FLAG.
Kojto 90:cb3d968589d8 1559 * @param _FLAG_: specifies the flag to clear.
Kojto 90:cb3d968589d8 1560 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 1561 * @arg RCC_CRS_FLAG_SYNCOK
Kojto 90:cb3d968589d8 1562 * @arg RCC_CRS_FLAG_SYNCWARN
Kojto 90:cb3d968589d8 1563 * @arg RCC_CRS_FLAG_ERR
Kojto 90:cb3d968589d8 1564 * @arg RCC_CRS_FLAG_ESYNC
Kojto 90:cb3d968589d8 1565 * @arg RCC_CRS_FLAG_TRIMOVF
Kojto 90:cb3d968589d8 1566 * @arg RCC_CRS_FLAG_SYNCERR
Kojto 90:cb3d968589d8 1567 * @arg RCC_CRS_FLAG_SYNCMISS
Kojto 90:cb3d968589d8 1568 * @retval None
Kojto 90:cb3d968589d8 1569 */
Kojto 90:cb3d968589d8 1570
Kojto 90:cb3d968589d8 1571 /* CRS Flag Error Mask */
Kojto 90:cb3d968589d8 1572 #define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF | RCC_CRS_FLAG_SYNCERR | RCC_CRS_FLAG_SYNCMISS))
Kojto 90:cb3d968589d8 1573
Kojto 90:cb3d968589d8 1574 #define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR |= CRS_ICR_ERRC) : \
Kojto 90:cb3d968589d8 1575 (CRS->ICR |= (__FLAG__)))
Kojto 90:cb3d968589d8 1576
Kojto 90:cb3d968589d8 1577 /**
Kojto 90:cb3d968589d8 1578 * @}
Kojto 90:cb3d968589d8 1579 */
Kojto 90:cb3d968589d8 1580
Kojto 90:cb3d968589d8 1581 /** @defgroup RCCEx_CRS_Extended_Features RCCEx CRS Extended Features
Kojto 90:cb3d968589d8 1582 * @{
Kojto 90:cb3d968589d8 1583 */
Kojto 90:cb3d968589d8 1584 /**
Kojto 90:cb3d968589d8 1585 * @brief Enables the oscillator clock for frequency error counter.
Kojto 90:cb3d968589d8 1586 * @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 90:cb3d968589d8 1587 * @retval None
Kojto 90:cb3d968589d8 1588 */
Kojto 90:cb3d968589d8 1589 #define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR |= CRS_CR_CEN)
Kojto 90:cb3d968589d8 1590
Kojto 90:cb3d968589d8 1591 /**
Kojto 90:cb3d968589d8 1592 * @brief Disables the oscillator clock for frequency error counter.
Kojto 90:cb3d968589d8 1593 * @retval None
Kojto 90:cb3d968589d8 1594 */
Kojto 90:cb3d968589d8 1595 #define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
Kojto 90:cb3d968589d8 1596
Kojto 90:cb3d968589d8 1597 /**
Kojto 90:cb3d968589d8 1598 * @brief Enables the automatic hardware adjustement of TRIM bits.
Kojto 90:cb3d968589d8 1599 * @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
Kojto 90:cb3d968589d8 1600 * @retval None
Kojto 90:cb3d968589d8 1601 */
Kojto 90:cb3d968589d8 1602 #define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR |= CRS_CR_AUTOTRIMEN)
Kojto 90:cb3d968589d8 1603
Kojto 90:cb3d968589d8 1604 /**
Kojto 90:cb3d968589d8 1605 * @brief Enables or disables the automatic hardware adjustement of TRIM bits.
Kojto 90:cb3d968589d8 1606 * @retval None
Kojto 90:cb3d968589d8 1607 */
Kojto 90:cb3d968589d8 1608 #define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
Kojto 90:cb3d968589d8 1609
Kojto 90:cb3d968589d8 1610 /**
Kojto 90:cb3d968589d8 1611 * @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
Kojto 90:cb3d968589d8 1612 * @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
Kojto 90:cb3d968589d8 1613 * of the synchronization source after prescaling. It is then decreased by one in order to
Kojto 90:cb3d968589d8 1614 * reach the expected synchronization on the zero value. The formula is the following:
Kojto 90:cb3d968589d8 1615 * RELOAD = (fTARGET / fSYNC) -1
Kojto 90:cb3d968589d8 1616 * @param _FTARGET_ Target frequency (value in Hz)
Kojto 90:cb3d968589d8 1617 * @param _FSYNC_ Synchronization signal frequency (value in Hz)
Kojto 90:cb3d968589d8 1618 * @retval None
Kojto 90:cb3d968589d8 1619 */
Kojto 90:cb3d968589d8 1620 #define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_) (((_FTARGET_) / (_FSYNC_)) - 1)
Kojto 90:cb3d968589d8 1621
Kojto 90:cb3d968589d8 1622 /**
Kojto 90:cb3d968589d8 1623 * @}
Kojto 90:cb3d968589d8 1624 */
Kojto 90:cb3d968589d8 1625
Kojto 90:cb3d968589d8 1626 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1627 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1628 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1629
Kojto 90:cb3d968589d8 1630 /**
Kojto 90:cb3d968589d8 1631 * @}
Kojto 90:cb3d968589d8 1632 */
Kojto 90:cb3d968589d8 1633
Kojto 90:cb3d968589d8 1634 /* Exported functions --------------------------------------------------------*/
Kojto 90:cb3d968589d8 1635 /** @addtogroup RCCEx_Exported_Functions
Kojto 90:cb3d968589d8 1636 * @{
Kojto 90:cb3d968589d8 1637 */
Kojto 90:cb3d968589d8 1638
Kojto 90:cb3d968589d8 1639 /** @addtogroup RCCEx_Exported_Functions_Group1
Kojto 90:cb3d968589d8 1640 * @{
Kojto 90:cb3d968589d8 1641 */
Kojto 90:cb3d968589d8 1642
Kojto 90:cb3d968589d8 1643 HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 90:cb3d968589d8 1644 void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto 90:cb3d968589d8 1645
Kojto 90:cb3d968589d8 1646 #if defined(STM32F042x6) || defined(STM32F048xx) || \
Kojto 90:cb3d968589d8 1647 defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) || \
Kojto 90:cb3d968589d8 1648 defined(STM32F091xC) || defined(STM32F098xx)
Kojto 90:cb3d968589d8 1649 void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
Kojto 90:cb3d968589d8 1650 void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
Kojto 90:cb3d968589d8 1651 void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto 93:e188a91d3eaa 1652 uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto 90:cb3d968589d8 1653 #endif /* STM32F042x6 || STM32F048xx || */
Kojto 90:cb3d968589d8 1654 /* STM32F071xB || STM32F072xB || STM32F078xx || */
Kojto 90:cb3d968589d8 1655 /* STM32F091xC || STM32F098xx */
Kojto 90:cb3d968589d8 1656
Kojto 90:cb3d968589d8 1657
Kojto 90:cb3d968589d8 1658 /**
Kojto 90:cb3d968589d8 1659 * @}
Kojto 90:cb3d968589d8 1660 */
Kojto 90:cb3d968589d8 1661
Kojto 90:cb3d968589d8 1662 /**
Kojto 90:cb3d968589d8 1663 * @}
Kojto 90:cb3d968589d8 1664 */
Kojto 90:cb3d968589d8 1665
Kojto 90:cb3d968589d8 1666 /**
Kojto 90:cb3d968589d8 1667 * @}
Kojto 90:cb3d968589d8 1668 */
Kojto 90:cb3d968589d8 1669
Kojto 90:cb3d968589d8 1670 /**
Kojto 90:cb3d968589d8 1671 * @}
Kojto 90:cb3d968589d8 1672 */
Kojto 90:cb3d968589d8 1673
Kojto 90:cb3d968589d8 1674 #ifdef __cplusplus
Kojto 90:cb3d968589d8 1675 }
Kojto 90:cb3d968589d8 1676 #endif
Kojto 90:cb3d968589d8 1677
Kojto 90:cb3d968589d8 1678 #endif /* __STM32F0xx_HAL_RCC_EX_H */
Kojto 90:cb3d968589d8 1679
Kojto 90:cb3d968589d8 1680 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/