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TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:: Kojto
Date:: Tue Oct 28 16:40:41 2014 +0000
Revision:: 90:cb3d968589d8
Parent:: 85:024bf7f99721

Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_ll_fmc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
Kojto	90:cb3d968589d8	5	* @version V1.1.0
Kojto	90:cb3d968589d8	6	* @date 19-June-2014
emilmont	77:869cf507173a	7	* @brief Header file of FMC HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_LL_FMC_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_LL_FMC_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
emilmont	77:869cf507173a	47
emilmont	77:869cf507173a	48	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	49	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	50
emilmont	77:869cf507173a	51	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	52	* @{
emilmont	77:869cf507173a	53	*/
emilmont	77:869cf507173a	54
emilmont	77:869cf507173a	55	/** @addtogroup FMC
emilmont	77:869cf507173a	56	* @{
emilmont	77:869cf507173a	57	*/
emilmont	77:869cf507173a	58
emilmont	77:869cf507173a	59	/* Exported typedef ----------------------------------------------------------*/
emilmont	77:869cf507173a	60	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
emilmont	77:869cf507173a	61	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
emilmont	77:869cf507173a	62	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
emilmont	77:869cf507173a	63	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
emilmont	77:869cf507173a	64	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
emilmont	77:869cf507173a	65
bogdanm	85:024bf7f99721	66	#define FMC_NORSRAM_DEVICE FMC_Bank1
bogdanm	85:024bf7f99721	67	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
bogdanm	85:024bf7f99721	68	#define FMC_NAND_DEVICE FMC_Bank2_3
bogdanm	85:024bf7f99721	69	#define FMC_PCCARD_DEVICE FMC_Bank4
bogdanm	85:024bf7f99721	70	#define FMC_SDRAM_DEVICE FMC_Bank5_6
emilmont	77:869cf507173a	71
emilmont	77:869cf507173a	72	/**
bogdanm	85:024bf7f99721	73	* @brief FMC_NORSRAM Configuration Structure definition
emilmont	77:869cf507173a	74	*/
emilmont	77:869cf507173a	75	typedef struct
emilmont	77:869cf507173a	76	{
emilmont	77:869cf507173a	77	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	85:024bf7f99721	78	This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm	85:024bf7f99721	79
emilmont	77:869cf507173a	80	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
emilmont	77:869cf507173a	81	multiplexed on the data bus or not.
emilmont	77:869cf507173a	82	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm	85:024bf7f99721	83
emilmont	77:869cf507173a	84	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
emilmont	77:869cf507173a	85	the corresponding memory device.
emilmont	77:869cf507173a	86	This parameter can be a value of @ref FMC_Memory_Type */
bogdanm	85:024bf7f99721	87
emilmont	77:869cf507173a	88	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont	77:869cf507173a	89	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm	85:024bf7f99721	90
emilmont	77:869cf507173a	91	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
emilmont	77:869cf507173a	92	valid only with synchronous burst Flash memories.
emilmont	77:869cf507173a	93	This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm	85:024bf7f99721	94
emilmont	77:869cf507173a	95	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
emilmont	77:869cf507173a	96	the Flash memory in burst mode.
emilmont	77:869cf507173a	97	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm	85:024bf7f99721	98
emilmont	77:869cf507173a	99	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
emilmont	77:869cf507173a	100	memory, valid only when accessing Flash memories in burst mode.
emilmont	77:869cf507173a	101	This parameter can be a value of @ref FMC_Wrap_Mode */
bogdanm	85:024bf7f99721	102
emilmont	77:869cf507173a	103	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
emilmont	77:869cf507173a	104	clock cycle before the wait state or during the wait state,
emilmont	77:869cf507173a	105	valid only when accessing memories in burst mode.
emilmont	77:869cf507173a	106	This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm	85:024bf7f99721	107
emilmont	77:869cf507173a	108	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
emilmont	77:869cf507173a	109	This parameter can be a value of @ref FMC_Write_Operation */
bogdanm	85:024bf7f99721	110
emilmont	77:869cf507173a	111	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
emilmont	77:869cf507173a	112	signal, valid for Flash memory access in burst mode.
emilmont	77:869cf507173a	113	This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm	85:024bf7f99721	114
emilmont	77:869cf507173a	115	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
emilmont	77:869cf507173a	116	This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm	85:024bf7f99721	117
emilmont	77:869cf507173a	118	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
emilmont	77:869cf507173a	119	valid only with asynchronous Flash memories.
emilmont	77:869cf507173a	120	This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm	85:024bf7f99721	121
emilmont	77:869cf507173a	122	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	85:024bf7f99721	123	This parameter can be a value of @ref FMC_Write_Burst */
bogdanm	85:024bf7f99721	124
emilmont	77:869cf507173a	125	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
emilmont	77:869cf507173a	126	This parameter is only enabled through the FMC_BCR1 register, and don't care
emilmont	77:869cf507173a	127	through FMC_BCR2..4 registers.
bogdanm	85:024bf7f99721	128	This parameter can be a value of @ref FMC_Continous_Clock */
emilmont	77:869cf507173a	129
emilmont	77:869cf507173a	130	}FMC_NORSRAM_InitTypeDef;
emilmont	77:869cf507173a	131
emilmont	77:869cf507173a	132	/**
emilmont	77:869cf507173a	133	* @brief FMC_NORSRAM Timing parameters structure definition
emilmont	77:869cf507173a	134	*/
emilmont	77:869cf507173a	135	typedef struct
emilmont	77:869cf507173a	136	{
emilmont	77:869cf507173a	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	138	the duration of the address setup time.
emilmont	77:869cf507173a	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont	77:869cf507173a	140	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	85:024bf7f99721	141
emilmont	77:869cf507173a	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	143	the duration of the address hold time.
emilmont	77:869cf507173a	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
emilmont	77:869cf507173a	145	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	85:024bf7f99721	146
emilmont	77:869cf507173a	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	148	the duration of the data setup time.
emilmont	77:869cf507173a	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
emilmont	77:869cf507173a	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
emilmont	77:869cf507173a	151	NOR Flash memories. */
bogdanm	85:024bf7f99721	152
emilmont	77:869cf507173a	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	154	the duration of the bus turnaround.
emilmont	77:869cf507173a	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont	77:869cf507173a	156	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	85:024bf7f99721	157
emilmont	77:869cf507173a	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
emilmont	77:869cf507173a	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
emilmont	77:869cf507173a	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
emilmont	77:869cf507173a	161	accesses. */
bogdanm	85:024bf7f99721	162
emilmont	77:869cf507173a	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
emilmont	77:869cf507173a	164	to the memory before getting the first data.
emilmont	77:869cf507173a	165	The parameter value depends on the memory type as shown below:
emilmont	77:869cf507173a	166	- It must be set to 0 in case of a CRAM
emilmont	77:869cf507173a	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
emilmont	77:869cf507173a	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
emilmont	77:869cf507173a	169	with synchronous burst mode enable */
bogdanm	85:024bf7f99721	170
emilmont	77:869cf507173a	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
emilmont	77:869cf507173a	172	This parameter can be a value of @ref FMC_Access_Mode */
emilmont	77:869cf507173a	173	}FMC_NORSRAM_TimingTypeDef;
emilmont	77:869cf507173a	174
emilmont	77:869cf507173a	175	/**
emilmont	77:869cf507173a	176	* @brief FMC_NAND Configuration Structure definition
emilmont	77:869cf507173a	177	*/
emilmont	77:869cf507173a	178	typedef struct
emilmont	77:869cf507173a	179	{
emilmont	77:869cf507173a	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	85:024bf7f99721	181	This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm	85:024bf7f99721	182
emilmont	77:869cf507173a	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
emilmont	77:869cf507173a	184	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	85:024bf7f99721	185
emilmont	77:869cf507173a	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont	77:869cf507173a	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm	85:024bf7f99721	188
emilmont	77:869cf507173a	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
emilmont	77:869cf507173a	190	This parameter can be any value of @ref FMC_ECC */
bogdanm	85:024bf7f99721	191
emilmont	77:869cf507173a	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
emilmont	77:869cf507173a	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm	85:024bf7f99721	194
emilmont	77:869cf507173a	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	196	delay between CLE low and RE low.
emilmont	77:869cf507173a	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	198
emilmont	77:869cf507173a	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	200	delay between ALE low and RE low.
emilmont	77:869cf507173a	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	202	}FMC_NAND_InitTypeDef;
emilmont	77:869cf507173a	203
emilmont	77:869cf507173a	204	/**
emilmont	77:869cf507173a	205	* @brief FMC_NAND_PCCARD Timing parameters structure definition
emilmont	77:869cf507173a	206	*/
emilmont	77:869cf507173a	207	typedef struct
emilmont	77:869cf507173a	208	{
emilmont	77:869cf507173a	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
emilmont	77:869cf507173a	210	the command assertion for NAND-Flash read or write access
emilmont	77:869cf507173a	211	to common/Attribute or I/O memory space (depending on
emilmont	77:869cf507173a	212	the memory space timing to be configured).
emilmont	77:869cf507173a	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	214
emilmont	77:869cf507173a	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
emilmont	77:869cf507173a	216	command for NAND-Flash read or write access to
emilmont	77:869cf507173a	217	common/Attribute or I/O memory space (depending on the
emilmont	77:869cf507173a	218	memory space timing to be configured).
emilmont	77:869cf507173a	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	220
emilmont	77:869cf507173a	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
emilmont	77:869cf507173a	222	(and data for write access) after the command de-assertion
emilmont	77:869cf507173a	223	for NAND-Flash read or write access to common/Attribute
emilmont	77:869cf507173a	224	or I/O memory space (depending on the memory space timing
emilmont	77:869cf507173a	225	to be configured).
emilmont	77:869cf507173a	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	227
emilmont	77:869cf507173a	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
emilmont	77:869cf507173a	229	data bus is kept in HiZ after the start of a NAND-Flash
emilmont	77:869cf507173a	230	write access to common/Attribute or I/O memory space (depending
emilmont	77:869cf507173a	231	on the memory space timing to be configured).
emilmont	77:869cf507173a	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
emilmont	77:869cf507173a	233	}FMC_NAND_PCC_TimingTypeDef;
emilmont	77:869cf507173a	234
emilmont	77:869cf507173a	235	/**
bogdanm	85:024bf7f99721	236	* @brief FMC_NAND Configuration Structure definition
emilmont	77:869cf507173a	237	*/
emilmont	77:869cf507173a	238	typedef struct
emilmont	77:869cf507173a	239	{
emilmont	77:869cf507173a	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
emilmont	77:869cf507173a	241	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	85:024bf7f99721	242
emilmont	77:869cf507173a	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	244	delay between CLE low and RE low.
emilmont	77:869cf507173a	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	246
emilmont	77:869cf507173a	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	248	delay between ALE low and RE low.
emilmont	77:869cf507173a	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	250	}FMC_PCCARD_InitTypeDef;
emilmont	77:869cf507173a	251
emilmont	77:869cf507173a	252	/**
emilmont	77:869cf507173a	253	* @brief FMC_SDRAM Configuration Structure definition
emilmont	77:869cf507173a	254	*/
emilmont	77:869cf507173a	255	typedef struct
emilmont	77:869cf507173a	256	{
emilmont	77:869cf507173a	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
bogdanm	85:024bf7f99721	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
bogdanm	85:024bf7f99721	259
emilmont	77:869cf507173a	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
emilmont	77:869cf507173a	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
bogdanm	85:024bf7f99721	262
emilmont	77:869cf507173a	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
emilmont	77:869cf507173a	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
bogdanm	85:024bf7f99721	265
emilmont	77:869cf507173a	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
emilmont	77:869cf507173a	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
bogdanm	85:024bf7f99721	268
emilmont	77:869cf507173a	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
emilmont	77:869cf507173a	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
bogdanm	85:024bf7f99721	271
emilmont	77:869cf507173a	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
emilmont	77:869cf507173a	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
bogdanm	85:024bf7f99721	274
emilmont	77:869cf507173a	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
emilmont	77:869cf507173a	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
bogdanm	85:024bf7f99721	277
emilmont	77:869cf507173a	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
emilmont	77:869cf507173a	279	to disable the clock before changing frequency.
emilmont	77:869cf507173a	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
bogdanm	85:024bf7f99721	281
emilmont	77:869cf507173a	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
emilmont	77:869cf507173a	283	commands during the CAS latency and stores data in the Read FIFO.
emilmont	77:869cf507173a	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
bogdanm	85:024bf7f99721	285
emilmont	77:869cf507173a	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
emilmont	77:869cf507173a	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
emilmont	77:869cf507173a	288	}FMC_SDRAM_InitTypeDef;
emilmont	77:869cf507173a	289
emilmont	77:869cf507173a	290	/**
emilmont	77:869cf507173a	291	* @brief FMC_SDRAM Timing parameters structure definition
emilmont	77:869cf507173a	292	*/
emilmont	77:869cf507173a	293	typedef struct
emilmont	77:869cf507173a	294	{
emilmont	77:869cf507173a	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
emilmont	77:869cf507173a	296	an active or Refresh command in number of memory clock cycles.
emilmont	77:869cf507173a	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	298
emilmont	77:869cf507173a	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
emilmont	77:869cf507173a	300	issuing the Activate command in number of memory clock cycles.
emilmont	77:869cf507173a	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	302
emilmont	77:869cf507173a	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
emilmont	77:869cf507173a	304	cycles.
emilmont	77:869cf507173a	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	306
emilmont	77:869cf507173a	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
emilmont	77:869cf507173a	308	and the delay between two consecutive Refresh commands in number of
emilmont	77:869cf507173a	309	memory clock cycles.
emilmont	77:869cf507173a	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	311
emilmont	77:869cf507173a	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
emilmont	77:869cf507173a	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	314
emilmont	77:869cf507173a	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
emilmont	77:869cf507173a	316	in number of memory clock cycles.
emilmont	77:869cf507173a	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	318
emilmont	77:869cf507173a	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
emilmont	77:869cf507173a	320	command in number of memory clock cycles.
emilmont	77:869cf507173a	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	322	}FMC_SDRAM_TimingTypeDef;
emilmont	77:869cf507173a	323
emilmont	77:869cf507173a	324	/**
emilmont	77:869cf507173a	325	* @brief SDRAM command parameters structure definition
emilmont	77:869cf507173a	326	*/
emilmont	77:869cf507173a	327	typedef struct
emilmont	77:869cf507173a	328	{
emilmont	77:869cf507173a	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
bogdanm	85:024bf7f99721	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
bogdanm	85:024bf7f99721	331
emilmont	77:869cf507173a	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
bogdanm	85:024bf7f99721	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
bogdanm	85:024bf7f99721	334
emilmont	77:869cf507173a	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
emilmont	77:869cf507173a	336	in auto refresh mode.
bogdanm	85:024bf7f99721	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
emilmont	77:869cf507173a	339	}FMC_SDRAM_CommandTypeDef;
emilmont	77:869cf507173a	340
emilmont	77:869cf507173a	341	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	342
emilmont	77:869cf507173a	343	/** @defgroup FMC_NOR_SRAM_Controller
emilmont	77:869cf507173a	344	* @{
bogdanm	85:024bf7f99721	345	*/
bogdanm	85:024bf7f99721	346
emilmont	77:869cf507173a	347	/** @defgroup FMC_NORSRAM_Bank
emilmont	77:869cf507173a	348	* @{
emilmont	77:869cf507173a	349	*/
emilmont	77:869cf507173a	350	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	351	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	352	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	353	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006)
emilmont	77:869cf507173a	354
emilmont	77:869cf507173a	355	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
emilmont	77:869cf507173a	356	((BANK) == FMC_NORSRAM_BANK2) \|\| \
emilmont	77:869cf507173a	357	((BANK) == FMC_NORSRAM_BANK3) \|\| \
emilmont	77:869cf507173a	358	((BANK) == FMC_NORSRAM_BANK4))
emilmont	77:869cf507173a	359	/**
emilmont	77:869cf507173a	360	* @}
emilmont	77:869cf507173a	361	*/
emilmont	77:869cf507173a	362
emilmont	77:869cf507173a	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing
emilmont	77:869cf507173a	364	* @{
emilmont	77:869cf507173a	365	*/
emilmont	77:869cf507173a	366	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	367	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002)
emilmont	77:869cf507173a	368
emilmont	77:869cf507173a	369	#define IS_FMC_MUX(MUX) (((MUX) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
emilmont	77:869cf507173a	370	((MUX) == FMC_DATA_ADDRESS_MUX_ENABLE))
emilmont	77:869cf507173a	371	/**
emilmont	77:869cf507173a	372	* @}
emilmont	77:869cf507173a	373	*/
emilmont	77:869cf507173a	374
emilmont	77:869cf507173a	375	/** @defgroup FMC_Memory_Type
emilmont	77:869cf507173a	376	* @{
emilmont	77:869cf507173a	377	*/
emilmont	77:869cf507173a	378	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000)
emilmont	77:869cf507173a	379	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004)
emilmont	77:869cf507173a	380	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008)
emilmont	77:869cf507173a	381
emilmont	77:869cf507173a	382	#define IS_FMC_MEMORY(MEMORY) (((MEMORY) == FMC_MEMORY_TYPE_SRAM) \|\| \
emilmont	77:869cf507173a	383	((MEMORY) == FMC_MEMORY_TYPE_PSRAM)\|\| \
emilmont	77:869cf507173a	384	((MEMORY) == FMC_MEMORY_TYPE_NOR))
emilmont	77:869cf507173a	385	/**
emilmont	77:869cf507173a	386	* @}
emilmont	77:869cf507173a	387	*/
emilmont	77:869cf507173a	388
emilmont	77:869cf507173a	389	/** @defgroup FMC_NORSRAM_Data_Width
emilmont	77:869cf507173a	390	* @{
emilmont	77:869cf507173a	391	*/
emilmont	77:869cf507173a	392	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	393	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	394	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	395
emilmont	77:869cf507173a	396	#define IS_FMC_NORSRAM_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
emilmont	77:869cf507173a	397	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
emilmont	77:869cf507173a	398	((WIDTH) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
emilmont	77:869cf507173a	399	/**
emilmont	77:869cf507173a	400	* @}
emilmont	77:869cf507173a	401	*/
emilmont	77:869cf507173a	402
emilmont	77:869cf507173a	403	/** @defgroup FMC_NORSRAM_Flash_Access
emilmont	77:869cf507173a	404	* @{
emilmont	77:869cf507173a	405	*/
emilmont	77:869cf507173a	406	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040)
emilmont	77:869cf507173a	407	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	408	/**
emilmont	77:869cf507173a	409	* @}
emilmont	77:869cf507173a	410	*/
emilmont	77:869cf507173a	411
emilmont	77:869cf507173a	412	/** @defgroup FMC_Burst_Access_Mode
emilmont	77:869cf507173a	413	* @{
emilmont	77:869cf507173a	414	*/
emilmont	77:869cf507173a	415	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	416	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100)
emilmont	77:869cf507173a	417
emilmont	77:869cf507173a	418	#define IS_FMC_BURSTMODE(STATE) (((STATE) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
emilmont	77:869cf507173a	419	((STATE) == FMC_BURST_ACCESS_MODE_ENABLE))
emilmont	77:869cf507173a	420	/**
emilmont	77:869cf507173a	421	* @}
emilmont	77:869cf507173a	422	*/
emilmont	77:869cf507173a	423
emilmont	77:869cf507173a	424
emilmont	77:869cf507173a	425	/** @defgroup FMC_Wait_Signal_Polarity
emilmont	77:869cf507173a	426	* @{
emilmont	77:869cf507173a	427	*/
emilmont	77:869cf507173a	428	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000)
emilmont	77:869cf507173a	429	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200)
emilmont	77:869cf507173a	430
emilmont	77:869cf507173a	431	#define IS_FMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
emilmont	77:869cf507173a	432	((POLARITY) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
emilmont	77:869cf507173a	433	/**
emilmont	77:869cf507173a	434	* @}
emilmont	77:869cf507173a	435	*/
emilmont	77:869cf507173a	436
emilmont	77:869cf507173a	437	/** @defgroup FMC_Wrap_Mode
emilmont	77:869cf507173a	438	* @{
emilmont	77:869cf507173a	439	*/
emilmont	77:869cf507173a	440	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	441	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400)
emilmont	77:869cf507173a	442
emilmont	77:869cf507173a	443	#define IS_FMC_WRAP_MODE(MODE) (((MODE) == FMC_WRAP_MODE_DISABLE) \|\| \
emilmont	77:869cf507173a	444	((MODE) == FMC_WRAP_MODE_ENABLE))
emilmont	77:869cf507173a	445	/**
emilmont	77:869cf507173a	446	* @}
emilmont	77:869cf507173a	447	*/
emilmont	77:869cf507173a	448
emilmont	77:869cf507173a	449	/** @defgroup FMC_Wait_Timing
emilmont	77:869cf507173a	450	* @{
emilmont	77:869cf507173a	451	*/
emilmont	77:869cf507173a	452	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000)
emilmont	77:869cf507173a	453	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800)
emilmont	77:869cf507173a	454
emilmont	77:869cf507173a	455	#define IS_FMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
emilmont	77:869cf507173a	456	((ACTIVE) == FMC_WAIT_TIMING_DURING_WS))
emilmont	77:869cf507173a	457	/**
emilmont	77:869cf507173a	458	* @}
emilmont	77:869cf507173a	459	*/
emilmont	77:869cf507173a	460
emilmont	77:869cf507173a	461	/** @defgroup FMC_Write_Operation
emilmont	77:869cf507173a	462	* @{
emilmont	77:869cf507173a	463	*/
emilmont	77:869cf507173a	464	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	465	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000)
emilmont	77:869cf507173a	466
emilmont	77:869cf507173a	467	#define IS_FMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FMC_WRITE_OPERATION_DISABLE) \|\| \
bogdanm	85:024bf7f99721	468	((OPERATION) == FMC_WRITE_OPERATION_ENABLE))
emilmont	77:869cf507173a	469	/**
emilmont	77:869cf507173a	470	* @}
emilmont	77:869cf507173a	471	*/
emilmont	77:869cf507173a	472
emilmont	77:869cf507173a	473	/** @defgroup FMC_Wait_Signal
emilmont	77:869cf507173a	474	* @{
emilmont	77:869cf507173a	475	*/
emilmont	77:869cf507173a	476	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	477	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000)
emilmont	77:869cf507173a	478
emilmont	77:869cf507173a	479	#define IS_FMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
emilmont	77:869cf507173a	480	((SIGNAL) == FMC_WAIT_SIGNAL_ENABLE))
emilmont	77:869cf507173a	481	/**
emilmont	77:869cf507173a	482	* @}
emilmont	77:869cf507173a	483	*/
emilmont	77:869cf507173a	484
emilmont	77:869cf507173a	485	/** @defgroup FMC_Extended_Mode
emilmont	77:869cf507173a	486	* @{
emilmont	77:869cf507173a	487	*/
emilmont	77:869cf507173a	488	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	489	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000)
emilmont	77:869cf507173a	490
emilmont	77:869cf507173a	491	#define IS_FMC_EXTENDED_MODE(MODE) (((MODE) == FMC_EXTENDED_MODE_DISABLE) \|\| \
emilmont	77:869cf507173a	492	((MODE) == FMC_EXTENDED_MODE_ENABLE))
emilmont	77:869cf507173a	493	/**
emilmont	77:869cf507173a	494	* @}
emilmont	77:869cf507173a	495	*/
emilmont	77:869cf507173a	496
emilmont	77:869cf507173a	497	/** @defgroup FMC_AsynchronousWait
emilmont	77:869cf507173a	498	* @{
emilmont	77:869cf507173a	499	*/
emilmont	77:869cf507173a	500	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	501	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000)
emilmont	77:869cf507173a	502
emilmont	77:869cf507173a	503	#define IS_FMC_ASYNWAIT(STATE) (((STATE) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
emilmont	77:869cf507173a	504	((STATE) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
emilmont	77:869cf507173a	505	/**
emilmont	77:869cf507173a	506	* @}
emilmont	77:869cf507173a	507	*/
emilmont	77:869cf507173a	508
emilmont	77:869cf507173a	509	/** @defgroup FMC_Write_Burst
emilmont	77:869cf507173a	510	* @{
emilmont	77:869cf507173a	511	*/
emilmont	77:869cf507173a	512	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	513	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	514
emilmont	77:869cf507173a	515	#define IS_FMC_WRITE_BURST(BURST) (((BURST) == FMC_WRITE_BURST_DISABLE) \|\| \
emilmont	77:869cf507173a	516	((BURST) == FMC_WRITE_BURST_ENABLE))
emilmont	77:869cf507173a	517	/**
emilmont	77:869cf507173a	518	* @}
emilmont	77:869cf507173a	519	*/
emilmont	77:869cf507173a	520
emilmont	77:869cf507173a	521	/** @defgroup FMC_Continous_Clock
emilmont	77:869cf507173a	522	* @{
emilmont	77:869cf507173a	523	*/
emilmont	77:869cf507173a	524	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000)
emilmont	77:869cf507173a	525	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000)
emilmont	77:869cf507173a	526
emilmont	77:869cf507173a	527	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
emilmont	77:869cf507173a	528	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
emilmont	77:869cf507173a	529	/**
emilmont	77:869cf507173a	530	* @}
emilmont	77:869cf507173a	531	*/
emilmont	77:869cf507173a	532
emilmont	77:869cf507173a	533	/** @defgroup FMC_Address_Setup_Time
emilmont	77:869cf507173a	534	* @{
emilmont	77:869cf507173a	535	*/
emilmont	77:869cf507173a	536	#define IS_FMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 15)
emilmont	77:869cf507173a	537	/**
emilmont	77:869cf507173a	538	* @}
emilmont	77:869cf507173a	539	*/
emilmont	77:869cf507173a	540
emilmont	77:869cf507173a	541	/** @defgroup FMC_Address_Hold_Time
emilmont	77:869cf507173a	542	* @{
emilmont	77:869cf507173a	543	*/
emilmont	77:869cf507173a	544	#define IS_FMC_ADDRESS_HOLD_TIME(TIME) (((TIME) > 0) && ((TIME) <= 15))
emilmont	77:869cf507173a	545	/**
emilmont	77:869cf507173a	546	* @}
emilmont	77:869cf507173a	547	*/
emilmont	77:869cf507173a	548
emilmont	77:869cf507173a	549	/** @defgroup FMC_Data_Setup_Time
emilmont	77:869cf507173a	550	* @{
emilmont	77:869cf507173a	551	*/
emilmont	77:869cf507173a	552	#define IS_FMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 255))
emilmont	77:869cf507173a	553	/**
emilmont	77:869cf507173a	554	* @}
emilmont	77:869cf507173a	555	*/
emilmont	77:869cf507173a	556
emilmont	77:869cf507173a	557	/** @defgroup FMC_Bus_Turn_around_Duration
emilmont	77:869cf507173a	558	* @{
emilmont	77:869cf507173a	559	*/
emilmont	77:869cf507173a	560	#define IS_FMC_TURNAROUND_TIME(TIME) ((TIME) <= 15)
emilmont	77:869cf507173a	561	/**
emilmont	77:869cf507173a	562	* @}
emilmont	77:869cf507173a	563	*/
emilmont	77:869cf507173a	564
emilmont	77:869cf507173a	565	/** @defgroup FMC_CLK_Division
emilmont	77:869cf507173a	566	* @{
emilmont	77:869cf507173a	567	*/
emilmont	77:869cf507173a	568	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
emilmont	77:869cf507173a	569	/**
emilmont	77:869cf507173a	570	* @}
emilmont	77:869cf507173a	571	*/
emilmont	77:869cf507173a	572
emilmont	77:869cf507173a	573	/** @defgroup FMC_Data_Latency
emilmont	77:869cf507173a	574	* @{
emilmont	77:869cf507173a	575	*/
emilmont	77:869cf507173a	576	#define IS_FMC_DATA_LATENCY(LATENCY) (((LATENCY) > 1) && ((LATENCY) <= 17))
emilmont	77:869cf507173a	577	/**
emilmont	77:869cf507173a	578	* @}
emilmont	77:869cf507173a	579	*/
emilmont	77:869cf507173a	580
emilmont	77:869cf507173a	581	/** @defgroup FMC_Access_Mode
emilmont	77:869cf507173a	582	* @{
emilmont	77:869cf507173a	583	*/
emilmont	77:869cf507173a	584	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000)
emilmont	77:869cf507173a	585	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000)
emilmont	77:869cf507173a	586	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000)
emilmont	77:869cf507173a	587	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
emilmont	77:869cf507173a	588
emilmont	77:869cf507173a	589	#define IS_FMC_ACCESS_MODE(MODE) (((MODE) == FMC_ACCESS_MODE_A) \|\| \
emilmont	77:869cf507173a	590	((MODE) == FMC_ACCESS_MODE_B) \|\| \
emilmont	77:869cf507173a	591	((MODE) == FMC_ACCESS_MODE_C) \|\| \
emilmont	77:869cf507173a	592	((MODE) == FMC_ACCESS_MODE_D))
emilmont	77:869cf507173a	593	/**
emilmont	77:869cf507173a	594	* @}
emilmont	77:869cf507173a	595	*/
emilmont	77:869cf507173a	596
emilmont	77:869cf507173a	597	/**
emilmont	77:869cf507173a	598	* @}
emilmont	77:869cf507173a	599	*/
emilmont	77:869cf507173a	600
emilmont	77:869cf507173a	601	/** @defgroup FMC_NAND_Controller
emilmont	77:869cf507173a	602	* @{
emilmont	77:869cf507173a	603	*/
emilmont	77:869cf507173a	604
emilmont	77:869cf507173a	605	/** @defgroup FMC_NAND_Bank
emilmont	77:869cf507173a	606	* @{
emilmont	77:869cf507173a	607	*/
emilmont	77:869cf507173a	608	#define FMC_NAND_BANK2 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	609	#define FMC_NAND_BANK3 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	610
emilmont	77:869cf507173a	611	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
emilmont	77:869cf507173a	612	((BANK) == FMC_NAND_BANK3))
emilmont	77:869cf507173a	613	/**
emilmont	77:869cf507173a	614	* @}
emilmont	77:869cf507173a	615	*/
emilmont	77:869cf507173a	616
emilmont	77:869cf507173a	617	/** @defgroup FMC_Wait_feature
emilmont	77:869cf507173a	618	* @{
emilmont	77:869cf507173a	619	*/
emilmont	77:869cf507173a	620	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	621	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002)
emilmont	77:869cf507173a	622
emilmont	77:869cf507173a	623	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
bogdanm	85:024bf7f99721	624	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
emilmont	77:869cf507173a	625	/**
emilmont	77:869cf507173a	626	* @}
emilmont	77:869cf507173a	627	*/
emilmont	77:869cf507173a	628
emilmont	77:869cf507173a	629	/** @defgroup FMC_PCR_Memory_Type
emilmont	77:869cf507173a	630	* @{
emilmont	77:869cf507173a	631	*/
emilmont	77:869cf507173a	632	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000)
emilmont	77:869cf507173a	633	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008)
emilmont	77:869cf507173a	634	/**
emilmont	77:869cf507173a	635	* @}
emilmont	77:869cf507173a	636	*/
emilmont	77:869cf507173a	637
emilmont	77:869cf507173a	638	/** @defgroup FMC_NAND_Data_Width
emilmont	77:869cf507173a	639	* @{
emilmont	77:869cf507173a	640	*/
emilmont	77:869cf507173a	641	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	642	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	643
emilmont	77:869cf507173a	644	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
emilmont	77:869cf507173a	645	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
emilmont	77:869cf507173a	646	/**
emilmont	77:869cf507173a	647	* @}
emilmont	77:869cf507173a	648	*/
emilmont	77:869cf507173a	649
emilmont	77:869cf507173a	650	/** @defgroup FMC_ECC
emilmont	77:869cf507173a	651	* @{
emilmont	77:869cf507173a	652	*/
emilmont	77:869cf507173a	653	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	654	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040)
emilmont	77:869cf507173a	655
emilmont	77:869cf507173a	656	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
emilmont	77:869cf507173a	657	((STATE) == FMC_NAND_ECC_ENABLE))
emilmont	77:869cf507173a	658	/**
emilmont	77:869cf507173a	659	* @}
emilmont	77:869cf507173a	660	*/
emilmont	77:869cf507173a	661
emilmont	77:869cf507173a	662	/** @defgroup FMC_ECC_Page_Size
emilmont	77:869cf507173a	663	* @{
emilmont	77:869cf507173a	664	*/
emilmont	77:869cf507173a	665	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	666	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000)
emilmont	77:869cf507173a	667	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000)
emilmont	77:869cf507173a	668	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000)
emilmont	77:869cf507173a	669	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000)
emilmont	77:869cf507173a	670	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000)
emilmont	77:869cf507173a	671
emilmont	77:869cf507173a	672	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
emilmont	77:869cf507173a	673	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
emilmont	77:869cf507173a	674	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
emilmont	77:869cf507173a	675	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
emilmont	77:869cf507173a	676	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
emilmont	77:869cf507173a	677	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
emilmont	77:869cf507173a	678	/**
emilmont	77:869cf507173a	679	* @}
emilmont	77:869cf507173a	680	*/
emilmont	77:869cf507173a	681
emilmont	77:869cf507173a	682	/** @defgroup FMC_TCLR_Setup_Time
emilmont	77:869cf507173a	683	* @{
emilmont	77:869cf507173a	684	*/
emilmont	77:869cf507173a	685	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	686	/**
emilmont	77:869cf507173a	687	* @}
emilmont	77:869cf507173a	688	*/
emilmont	77:869cf507173a	689
emilmont	77:869cf507173a	690	/** @defgroup FMC_TAR_Setup_Time
emilmont	77:869cf507173a	691	* @{
emilmont	77:869cf507173a	692	*/
emilmont	77:869cf507173a	693	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	694	/**
emilmont	77:869cf507173a	695	* @}
emilmont	77:869cf507173a	696	*/
emilmont	77:869cf507173a	697
emilmont	77:869cf507173a	698	/** @defgroup FMC_Setup_Time
emilmont	77:869cf507173a	699	* @{
emilmont	77:869cf507173a	700	*/
emilmont	77:869cf507173a	701	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	702	/**
emilmont	77:869cf507173a	703	* @}
emilmont	77:869cf507173a	704	*/
emilmont	77:869cf507173a	705
emilmont	77:869cf507173a	706	/** @defgroup FMC_Wait_Setup_Time
emilmont	77:869cf507173a	707	* @{
emilmont	77:869cf507173a	708	*/
emilmont	77:869cf507173a	709	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	710	/**
emilmont	77:869cf507173a	711	* @}
emilmont	77:869cf507173a	712	*/
emilmont	77:869cf507173a	713
emilmont	77:869cf507173a	714	/** @defgroup FMC_Hold_Setup_Time
emilmont	77:869cf507173a	715	* @{
emilmont	77:869cf507173a	716	*/
emilmont	77:869cf507173a	717	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	718	/**
emilmont	77:869cf507173a	719	* @}
emilmont	77:869cf507173a	720	*/
emilmont	77:869cf507173a	721
emilmont	77:869cf507173a	722	/** @defgroup FMC_HiZ_Setup_Time
emilmont	77:869cf507173a	723	* @{
emilmont	77:869cf507173a	724	*/
emilmont	77:869cf507173a	725	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255)
emilmont	77:869cf507173a	726	/**
emilmont	77:869cf507173a	727	* @}
emilmont	77:869cf507173a	728	*/
emilmont	77:869cf507173a	729
emilmont	77:869cf507173a	730	/**
emilmont	77:869cf507173a	731	* @}
emilmont	77:869cf507173a	732	*/
emilmont	77:869cf507173a	733
emilmont	77:869cf507173a	734	/** @defgroup FMC_SDRAM_Controller
emilmont	77:869cf507173a	735	* @{
emilmont	77:869cf507173a	736	*/
emilmont	77:869cf507173a	737
emilmont	77:869cf507173a	738	/** @defgroup FMC_SDRAM_Bank
emilmont	77:869cf507173a	739	* @{
emilmont	77:869cf507173a	740	*/
emilmont	77:869cf507173a	741	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	742	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	743
emilmont	77:869cf507173a	744	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
emilmont	77:869cf507173a	745	((BANK) == FMC_SDRAM_BANK2))
emilmont	77:869cf507173a	746	/**
emilmont	77:869cf507173a	747	* @}
emilmont	77:869cf507173a	748	*/
emilmont	77:869cf507173a	749
emilmont	77:869cf507173a	750	/** @defgroup FMC_SDRAM_Column_Bits_number
emilmont	77:869cf507173a	751	* @{
emilmont	77:869cf507173a	752	*/
emilmont	77:869cf507173a	753	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	754	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	755	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	756	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003)
emilmont	77:869cf507173a	757
emilmont	77:869cf507173a	758	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
emilmont	77:869cf507173a	759	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
emilmont	77:869cf507173a	760	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
emilmont	77:869cf507173a	761	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
emilmont	77:869cf507173a	762	/**
emilmont	77:869cf507173a	763	* @}
emilmont	77:869cf507173a	764	*/
emilmont	77:869cf507173a	765
emilmont	77:869cf507173a	766	/** @defgroup FMC_SDRAM_Row_Bits_number
emilmont	77:869cf507173a	767	* @{
emilmont	77:869cf507173a	768	*/
emilmont	77:869cf507173a	769	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	770	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	771	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	772
emilmont	77:869cf507173a	773	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
emilmont	77:869cf507173a	774	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
emilmont	77:869cf507173a	775	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
emilmont	77:869cf507173a	776	/**
emilmont	77:869cf507173a	777	* @}
emilmont	77:869cf507173a	778	*/
emilmont	77:869cf507173a	779
emilmont	77:869cf507173a	780	/** @defgroup FMC_SDRAM_Memory_Bus_Width
emilmont	77:869cf507173a	781	* @{
emilmont	77:869cf507173a	782	*/
emilmont	77:869cf507173a	783	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	784	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010)
emilmont	77:869cf507173a	785	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020)
emilmont	77:869cf507173a	786
emilmont	77:869cf507173a	787	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
emilmont	77:869cf507173a	788	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
emilmont	77:869cf507173a	789	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
emilmont	77:869cf507173a	790	/**
emilmont	77:869cf507173a	791	* @}
emilmont	77:869cf507173a	792	*/
emilmont	77:869cf507173a	793
emilmont	77:869cf507173a	794	/** @defgroup FMC_SDRAM_Internal_Banks_Number
emilmont	77:869cf507173a	795	* @{
emilmont	77:869cf507173a	796	*/
emilmont	77:869cf507173a	797	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	798	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040)
emilmont	77:869cf507173a	799
emilmont	77:869cf507173a	800	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
emilmont	77:869cf507173a	801	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
emilmont	77:869cf507173a	802	/**
emilmont	77:869cf507173a	803	* @}
emilmont	77:869cf507173a	804	*/
emilmont	77:869cf507173a	805
emilmont	77:869cf507173a	806	/** @defgroup FMC_SDRAM_CAS_Latency
emilmont	77:869cf507173a	807	* @{
emilmont	77:869cf507173a	808	*/
emilmont	77:869cf507173a	809	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080)
emilmont	77:869cf507173a	810	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100)
emilmont	77:869cf507173a	811	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
emilmont	77:869cf507173a	812
emilmont	77:869cf507173a	813	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
emilmont	77:869cf507173a	814	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
emilmont	77:869cf507173a	815	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
emilmont	77:869cf507173a	816	/**
emilmont	77:869cf507173a	817	* @}
emilmont	77:869cf507173a	818	*/
emilmont	77:869cf507173a	819
emilmont	77:869cf507173a	820	/** @defgroup FMC_SDRAM_Write_Protection
emilmont	77:869cf507173a	821	* @{
emilmont	77:869cf507173a	822	*/
emilmont	77:869cf507173a	823	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	824	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200)
emilmont	77:869cf507173a	825
emilmont	77:869cf507173a	826	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
emilmont	77:869cf507173a	827	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
emilmont	77:869cf507173a	828	/**
emilmont	77:869cf507173a	829	* @}
emilmont	77:869cf507173a	830	*/
emilmont	77:869cf507173a	831
emilmont	77:869cf507173a	832	/** @defgroup FMC_SDRAM_Clock_Period
emilmont	77:869cf507173a	833	* @{
emilmont	77:869cf507173a	834	*/
emilmont	77:869cf507173a	835	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	836	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800)
emilmont	77:869cf507173a	837	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
emilmont	77:869cf507173a	838
emilmont	77:869cf507173a	839	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
emilmont	77:869cf507173a	840	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
emilmont	77:869cf507173a	841	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
emilmont	77:869cf507173a	842	/**
emilmont	77:869cf507173a	843	* @}
emilmont	77:869cf507173a	844	*/
emilmont	77:869cf507173a	845
emilmont	77:869cf507173a	846	/** @defgroup FMC_SDRAM_Read_Burst
emilmont	77:869cf507173a	847	* @{
emilmont	77:869cf507173a	848	*/
emilmont	77:869cf507173a	849	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	850	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000)
emilmont	77:869cf507173a	851
emilmont	77:869cf507173a	852	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
emilmont	77:869cf507173a	853	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
emilmont	77:869cf507173a	854	/**
emilmont	77:869cf507173a	855	* @}
emilmont	77:869cf507173a	856	*/
emilmont	77:869cf507173a	857
emilmont	77:869cf507173a	858	/** @defgroup FMC_SDRAM_Read_Pipe_Delay
emilmont	77:869cf507173a	859	* @{
emilmont	77:869cf507173a	860	*/
emilmont	77:869cf507173a	861	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	862	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000)
emilmont	77:869cf507173a	863	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000)
emilmont	77:869cf507173a	864
emilmont	77:869cf507173a	865	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
emilmont	77:869cf507173a	866	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
emilmont	77:869cf507173a	867	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
emilmont	77:869cf507173a	868	/**
emilmont	77:869cf507173a	869	* @}
emilmont	77:869cf507173a	870	*/
emilmont	77:869cf507173a	871
emilmont	77:869cf507173a	872	/** @defgroup FMC_SDRAM_LoadToActive_Delay
emilmont	77:869cf507173a	873	* @{
emilmont	77:869cf507173a	874	*/
emilmont	77:869cf507173a	875	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
emilmont	77:869cf507173a	876	/**
emilmont	77:869cf507173a	877	* @}
emilmont	77:869cf507173a	878	*/
emilmont	77:869cf507173a	879
emilmont	77:869cf507173a	880	/** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay
emilmont	77:869cf507173a	881	* @{
emilmont	77:869cf507173a	882	*/
emilmont	77:869cf507173a	883	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
emilmont	77:869cf507173a	884	/**
emilmont	77:869cf507173a	885	* @}
emilmont	77:869cf507173a	886	*/
emilmont	77:869cf507173a	887
emilmont	77:869cf507173a	888	/** @defgroup FMC_SDRAM_SelfRefresh_Time
emilmont	77:869cf507173a	889	* @{
emilmont	77:869cf507173a	890	*/
emilmont	77:869cf507173a	891	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
emilmont	77:869cf507173a	892	/**
emilmont	77:869cf507173a	893	* @}
emilmont	77:869cf507173a	894	*/
emilmont	77:869cf507173a	895
emilmont	77:869cf507173a	896	/** @defgroup FMC_SDRAM_RowCycle_Delay
emilmont	77:869cf507173a	897	* @{
emilmont	77:869cf507173a	898	*/
emilmont	77:869cf507173a	899	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
emilmont	77:869cf507173a	900	/**
emilmont	77:869cf507173a	901	* @}
emilmont	77:869cf507173a	902	*/
emilmont	77:869cf507173a	903
emilmont	77:869cf507173a	904	/** @defgroup FMC_SDRAM_Write_Recovery_Time
emilmont	77:869cf507173a	905	* @{
emilmont	77:869cf507173a	906	*/
emilmont	77:869cf507173a	907	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0) && ((TIME) <= 16))
emilmont	77:869cf507173a	908	/**
emilmont	77:869cf507173a	909	* @}
emilmont	77:869cf507173a	910	*/
emilmont	77:869cf507173a	911
emilmont	77:869cf507173a	912	/** @defgroup FMC_SDRAM_RP_Delay
emilmont	77:869cf507173a	913	* @{
emilmont	77:869cf507173a	914	*/
emilmont	77:869cf507173a	915	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
emilmont	77:869cf507173a	916	/**
emilmont	77:869cf507173a	917	* @}
emilmont	77:869cf507173a	918	*/
emilmont	77:869cf507173a	919
emilmont	77:869cf507173a	920	/** @defgroup FMC_SDRAM_RCD_Delay
emilmont	77:869cf507173a	921	* @{
emilmont	77:869cf507173a	922	*/
emilmont	77:869cf507173a	923	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0) && ((DELAY) <= 16))
emilmont	77:869cf507173a	924
emilmont	77:869cf507173a	925	/**
emilmont	77:869cf507173a	926	* @}
emilmont	77:869cf507173a	927	*/
emilmont	77:869cf507173a	928
emilmont	77:869cf507173a	929	/** @defgroup FMC_SDRAM_Command_Mode
emilmont	77:869cf507173a	930	* @{
emilmont	77:869cf507173a	931	*/
emilmont	77:869cf507173a	932	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	933	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	934	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002)
emilmont	77:869cf507173a	935	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003)
emilmont	77:869cf507173a	936	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	937	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005)
emilmont	77:869cf507173a	938	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006)
emilmont	77:869cf507173a	939
emilmont	77:869cf507173a	940	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
emilmont	77:869cf507173a	941	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
emilmont	77:869cf507173a	942	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
emilmont	77:869cf507173a	943	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
emilmont	77:869cf507173a	944	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
emilmont	77:869cf507173a	945	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
emilmont	77:869cf507173a	946	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
emilmont	77:869cf507173a	947	/**
emilmont	77:869cf507173a	948	* @}
emilmont	77:869cf507173a	949	*/
emilmont	77:869cf507173a	950
emilmont	77:869cf507173a	951	/** @defgroup FMC_SDRAM_Command_Target
emilmont	77:869cf507173a	952	* @{
emilmont	77:869cf507173a	953	*/
emilmont	77:869cf507173a	954	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
emilmont	77:869cf507173a	955	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
emilmont	77:869cf507173a	956	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018)
emilmont	77:869cf507173a	957
emilmont	77:869cf507173a	958	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
emilmont	77:869cf507173a	959	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
emilmont	77:869cf507173a	960	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
emilmont	77:869cf507173a	961	/**
emilmont	77:869cf507173a	962	* @}
emilmont	77:869cf507173a	963	*/
emilmont	77:869cf507173a	964
emilmont	77:869cf507173a	965	/** @defgroup FMC_SDRAM_AutoRefresh_Number
emilmont	77:869cf507173a	966	* @{
emilmont	77:869cf507173a	967	*/
emilmont	77:869cf507173a	968	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0) && ((NUMBER) <= 16))
emilmont	77:869cf507173a	969	/**
emilmont	77:869cf507173a	970	* @}
emilmont	77:869cf507173a	971	*/
emilmont	77:869cf507173a	972
emilmont	77:869cf507173a	973	/** @defgroup FMC_SDRAM_ModeRegister_Definition
emilmont	77:869cf507173a	974	* @{
emilmont	77:869cf507173a	975	*/
emilmont	77:869cf507173a	976	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191)
emilmont	77:869cf507173a	977	/**
emilmont	77:869cf507173a	978	* @}
emilmont	77:869cf507173a	979	*/
emilmont	77:869cf507173a	980
emilmont	77:869cf507173a	981	/** @defgroup FMC_SDRAM_Refresh_rate
emilmont	77:869cf507173a	982	* @{
emilmont	77:869cf507173a	983	*/
emilmont	77:869cf507173a	984	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191)
emilmont	77:869cf507173a	985	/**
emilmont	77:869cf507173a	986	* @}
emilmont	77:869cf507173a	987	*/
emilmont	77:869cf507173a	988
emilmont	77:869cf507173a	989	/** @defgroup FMC_SDRAM_Mode_Status
emilmont	77:869cf507173a	990	* @{
emilmont	77:869cf507173a	991	*/
emilmont	77:869cf507173a	992	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	993	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
emilmont	77:869cf507173a	994	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
emilmont	77:869cf507173a	995	/**
emilmont	77:869cf507173a	996	* @}
emilmont	77:869cf507173a	997	*/
emilmont	77:869cf507173a	998
emilmont	77:869cf507173a	999	/** @defgroup FMC_NORSRAM_Device_Instance
emilmont	77:869cf507173a	1000	* @{
emilmont	77:869cf507173a	1001	*/
emilmont	77:869cf507173a	1002	#define IS_FMC_NORSRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_DEVICE)
emilmont	77:869cf507173a	1003	/**
emilmont	77:869cf507173a	1004	* @}
emilmont	77:869cf507173a	1005	*/
emilmont	77:869cf507173a	1006
emilmont	77:869cf507173a	1007	/** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance
emilmont	77:869cf507173a	1008	* @{
emilmont	77:869cf507173a	1009	*/
emilmont	77:869cf507173a	1010	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(INSTANCE) ((INSTANCE) == FMC_NORSRAM_EXTENDED_DEVICE)
emilmont	77:869cf507173a	1011	/**
emilmont	77:869cf507173a	1012	* @}
emilmont	77:869cf507173a	1013	*/
emilmont	77:869cf507173a	1014
emilmont	77:869cf507173a	1015	/** @defgroup FMC_NAND_Device_Instance
emilmont	77:869cf507173a	1016	* @{
emilmont	77:869cf507173a	1017	*/
emilmont	77:869cf507173a	1018	#define IS_FMC_NAND_DEVICE(INSTANCE) ((INSTANCE) == FMC_NAND_DEVICE)
emilmont	77:869cf507173a	1019	/**
emilmont	77:869cf507173a	1020	* @}
emilmont	77:869cf507173a	1021	*/
emilmont	77:869cf507173a	1022
emilmont	77:869cf507173a	1023	/** @defgroup FMC_PCCARD_Device_Instance
emilmont	77:869cf507173a	1024	* @{
emilmont	77:869cf507173a	1025	*/
emilmont	77:869cf507173a	1026	#define IS_FMC_PCCARD_DEVICE(INSTANCE) ((INSTANCE) == FMC_PCCARD_DEVICE)
emilmont	77:869cf507173a	1027	/**
emilmont	77:869cf507173a	1028	* @}
emilmont	77:869cf507173a	1029	*/
emilmont	77:869cf507173a	1030
emilmont	77:869cf507173a	1031	/** @defgroup FMC_SDRAM_Device_Instance
emilmont	77:869cf507173a	1032	* @{
emilmont	77:869cf507173a	1033	*/
emilmont	77:869cf507173a	1034	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
emilmont	77:869cf507173a	1035	/**
emilmont	77:869cf507173a	1036	* @}
emilmont	77:869cf507173a	1037	*/
emilmont	77:869cf507173a	1038
emilmont	77:869cf507173a	1039	/**
emilmont	77:869cf507173a	1040	* @}
emilmont	77:869cf507173a	1041	*/
emilmont	77:869cf507173a	1042
emilmont	77:869cf507173a	1043	/** @defgroup FMC_Interrupt_definition
emilmont	77:869cf507173a	1044	* @brief FMC Interrupt definition
emilmont	77:869cf507173a	1045	* @{
emilmont	77:869cf507173a	1046	*/
emilmont	77:869cf507173a	1047	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008)
emilmont	77:869cf507173a	1048	#define FMC_IT_LEVEL ((uint32_t)0x00000010)
emilmont	77:869cf507173a	1049	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020)
emilmont	77:869cf507173a	1050	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000)
emilmont	77:869cf507173a	1051
emilmont	77:869cf507173a	1052	#define IS_FMC_IT(IT) ((((IT) & (uint32_t)0xFFFFBFC7) == 0x00000000) && ((IT) != 0x00000000))
emilmont	77:869cf507173a	1053
emilmont	77:869cf507173a	1054	#define IS_FMC_GET_IT(IT) (((IT) == FMC_IT_RISING_EDGE) \|\| \
emilmont	77:869cf507173a	1055	((IT) == FMC_IT_LEVEL) \|\| \
emilmont	77:869cf507173a	1056	((IT) == FMC_IT_FALLING_EDGE) \|\| \
emilmont	77:869cf507173a	1057	((IT) == FMC_IT_REFRESH_ERROR))
emilmont	77:869cf507173a	1058	/**
emilmont	77:869cf507173a	1059	* @}
emilmont	77:869cf507173a	1060	*/
emilmont	77:869cf507173a	1061
emilmont	77:869cf507173a	1062	/** @defgroup FMC_Flag_definition
emilmont	77:869cf507173a	1063	* @brief FMC Flag definition
emilmont	77:869cf507173a	1064	* @{
emilmont	77:869cf507173a	1065	*/
emilmont	77:869cf507173a	1066	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	1067	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002)
emilmont	77:869cf507173a	1068	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	1069	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040)
emilmont	77:869cf507173a	1070	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
emilmont	77:869cf507173a	1071	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
emilmont	77:869cf507173a	1072	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
emilmont	77:869cf507173a	1073
emilmont	77:869cf507173a	1074	#define IS_FMC_GET_FLAG(FLAG) (((FLAG) == FMC_FLAG_RISING_EDGE) \|\| \
emilmont	77:869cf507173a	1075	((FLAG) == FMC_FLAG_LEVEL) \|\| \
emilmont	77:869cf507173a	1076	((FLAG) == FMC_FLAG_FALLING_EDGE) \|\| \
emilmont	77:869cf507173a	1077	((FLAG) == FMC_FLAG_FEMPT) \|\| \
emilmont	77:869cf507173a	1078	((FLAG) == FMC_SDRAM_FLAG_REFRESH_IT) \|\| \
emilmont	77:869cf507173a	1079	((FLAG) == FMC_SDRAM_FLAG_BUSY))
emilmont	77:869cf507173a	1080
emilmont	77:869cf507173a	1081	#define IS_FMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
emilmont	77:869cf507173a	1082	/**
emilmont	77:869cf507173a	1083	* @}
emilmont	77:869cf507173a	1084	*/
emilmont	77:869cf507173a	1085
emilmont	77:869cf507173a	1086	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	1087
emilmont	77:869cf507173a	1088	/** @defgroup FMC_NOR_Macros
emilmont	77:869cf507173a	1089	* @brief macros to handle NOR device enable/disable and read/write operations
emilmont	77:869cf507173a	1090	* @{
emilmont	77:869cf507173a	1091	*/
emilmont	77:869cf507173a	1092
emilmont	77:869cf507173a	1093	/**
emilmont	77:869cf507173a	1094	* @brief Enable the NORSRAM device access.
emilmont	77:869cf507173a	1095	* @param __INSTANCE__: FMC_NORSRAM Instance
emilmont	77:869cf507173a	1096	* @param __BANK__: FMC_NORSRAM Bank
emilmont	77:869cf507173a	1097	* @retval None
emilmont	77:869cf507173a	1098	*/
emilmont	77:869cf507173a	1099	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
emilmont	77:869cf507173a	1100
emilmont	77:869cf507173a	1101	/**
emilmont	77:869cf507173a	1102	* @brief Disable the NORSRAM device access.
emilmont	77:869cf507173a	1103	* @param __INSTANCE__: FMC_NORSRAM Instance
emilmont	77:869cf507173a	1104	* @param __BANK__: FMC_NORSRAM Bank
emilmont	77:869cf507173a	1105	* @retval None
emilmont	77:869cf507173a	1106	*/
emilmont	77:869cf507173a	1107	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
emilmont	77:869cf507173a	1108
emilmont	77:869cf507173a	1109	/**
emilmont	77:869cf507173a	1110	* @}
emilmont	77:869cf507173a	1111	*/
emilmont	77:869cf507173a	1112
emilmont	77:869cf507173a	1113	/** @defgroup FMC_NAND_Macros
emilmont	77:869cf507173a	1114	* @brief macros to handle NAND device enable/disable
emilmont	77:869cf507173a	1115	* @{
emilmont	77:869cf507173a	1116	*/
emilmont	77:869cf507173a	1117
emilmont	77:869cf507173a	1118	/**
emilmont	77:869cf507173a	1119	* @brief Enable the NAND device access.
emilmont	77:869cf507173a	1120	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	1121	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	1122	* @retval None
emilmont	77:869cf507173a	1123	*/
emilmont	77:869cf507173a	1124	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
bogdanm	85:024bf7f99721	1125	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
emilmont	77:869cf507173a	1126
emilmont	77:869cf507173a	1127	/**
emilmont	77:869cf507173a	1128	* @brief Disable the NAND device access.
emilmont	77:869cf507173a	1129	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	1130	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	1131	* @retval None
bogdanm	85:024bf7f99721	1132	*/
emilmont	77:869cf507173a	1133	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
bogdanm	85:024bf7f99721	1134	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
emilmont	77:869cf507173a	1135	/**
emilmont	77:869cf507173a	1136	* @}
emilmont	77:869cf507173a	1137	*/
emilmont	77:869cf507173a	1138
emilmont	77:869cf507173a	1139	/** @defgroup FMC_PCCARD_Macros
emilmont	77:869cf507173a	1140	* @brief macros to handle SRAM read/write operations
emilmont	77:869cf507173a	1141	* @{
emilmont	77:869cf507173a	1142	*/
emilmont	77:869cf507173a	1143
emilmont	77:869cf507173a	1144	/**
emilmont	77:869cf507173a	1145	* @brief Enable the PCCARD device access.
emilmont	77:869cf507173a	1146	* @param __INSTANCE__: FMC_PCCARD Instance
emilmont	77:869cf507173a	1147	* @retval None
emilmont	77:869cf507173a	1148	*/
emilmont	77:869cf507173a	1149	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
emilmont	77:869cf507173a	1150
emilmont	77:869cf507173a	1151	/**
emilmont	77:869cf507173a	1152	* @brief Disable the PCCARD device access.
emilmont	77:869cf507173a	1153	* @param __INSTANCE__: FMC_PCCARD Instance
emilmont	77:869cf507173a	1154	* @retval None
emilmont	77:869cf507173a	1155	*/
emilmont	77:869cf507173a	1156	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
emilmont	77:869cf507173a	1157	/**
emilmont	77:869cf507173a	1158	* @}
emilmont	77:869cf507173a	1159	*/
emilmont	77:869cf507173a	1160
emilmont	77:869cf507173a	1161	/** @defgroup FMC_Interrupt
emilmont	77:869cf507173a	1162	* @brief macros to handle FMC interrupts
emilmont	77:869cf507173a	1163	* @{
emilmont	77:869cf507173a	1164	*/
emilmont	77:869cf507173a	1165
emilmont	77:869cf507173a	1166	/**
emilmont	77:869cf507173a	1167	* @brief Enable the NAND device interrupt.
emilmont	77:869cf507173a	1168	* @param __INSTANCE__: FMC_NAND instance
emilmont	77:869cf507173a	1169	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	1170	* @param __INTERRUPT__: FMC_NAND interrupt
emilmont	77:869cf507173a	1171	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1172	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	1173	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	1174	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	1175	* @retval None
emilmont	77:869cf507173a	1176	*/
emilmont	77:869cf507173a	1177	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
emilmont	77:869cf507173a	1178	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
emilmont	77:869cf507173a	1179
emilmont	77:869cf507173a	1180	/**
emilmont	77:869cf507173a	1181	* @brief Disable the NAND device interrupt.
emilmont	77:869cf507173a	1182	* @param __INSTANCE__: FMC_NAND handle
emilmont	77:869cf507173a	1183	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	1184	* @param __INTERRUPT__: FMC_NAND interrupt
emilmont	77:869cf507173a	1185	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1186	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	1187	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	1188	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	1189	* @retval None
emilmont	77:869cf507173a	1190	*/
emilmont	77:869cf507173a	1191	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
emilmont	77:869cf507173a	1192	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
emilmont	77:869cf507173a	1193
emilmont	77:869cf507173a	1194	/**
emilmont	77:869cf507173a	1195	* @brief Get flag status of the NAND device.
emilmont	77:869cf507173a	1196	* @param __INSTANCE__: FMC_NAND handle
emilmont	77:869cf507173a	1197	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	1198	* @param __FLAG__: FMC_NAND flag
emilmont	77:869cf507173a	1199	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1200	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	1201	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	1202	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	1203	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	1204	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	1205	*/
emilmont	77:869cf507173a	1206	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
emilmont	77:869cf507173a	1207	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
emilmont	77:869cf507173a	1208	/**
emilmont	77:869cf507173a	1209	* @brief Clear flag status of the NAND device.
emilmont	77:869cf507173a	1210	* @param __INSTANCE__: FMC_NAND handle
emilmont	77:869cf507173a	1211	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	1212	* @param __FLAG__: FMC_NAND flag
emilmont	77:869cf507173a	1213	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1214	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	1215	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	1216	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	1217	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	1218	* @retval None
emilmont	77:869cf507173a	1219	*/
emilmont	77:869cf507173a	1220	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
emilmont	77:869cf507173a	1221	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
emilmont	77:869cf507173a	1222	/**
emilmont	77:869cf507173a	1223	* @brief Enable the PCCARD device interrupt.
emilmont	77:869cf507173a	1224	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1225	* @param __INTERRUPT__: FMC_PCCARD interrupt
emilmont	77:869cf507173a	1226	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1227	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	1228	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	1229	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	1230	* @retval None
emilmont	77:869cf507173a	1231	*/
emilmont	77:869cf507173a	1232	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1233
emilmont	77:869cf507173a	1234	/**
emilmont	77:869cf507173a	1235	* @brief Disable the PCCARD device interrupt.
emilmont	77:869cf507173a	1236	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1237	* @param __INTERRUPT__: FMC_PCCARD interrupt
emilmont	77:869cf507173a	1238	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1239	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	1240	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	1241	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	1242	* @retval None
emilmont	77:869cf507173a	1243	*/
emilmont	77:869cf507173a	1244	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1245
emilmont	77:869cf507173a	1246	/**
emilmont	77:869cf507173a	1247	* @brief Get flag status of the PCCARD device.
emilmont	77:869cf507173a	1248	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1249	* @param __FLAG__: FMC_PCCARD flag
emilmont	77:869cf507173a	1250	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1251	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	1252	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	1253	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	1254	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	1255	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	1256	*/
emilmont	77:869cf507173a	1257	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	1258
emilmont	77:869cf507173a	1259	/**
emilmont	77:869cf507173a	1260	* @brief Clear flag status of the PCCARD device.
emilmont	77:869cf507173a	1261	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1262	* @param __FLAG__: FMC_PCCARD flag
emilmont	77:869cf507173a	1263	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1264	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	1265	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	1266	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	1267	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	1268	* @retval None
emilmont	77:869cf507173a	1269	*/
emilmont	77:869cf507173a	1270	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
emilmont	77:869cf507173a	1271
emilmont	77:869cf507173a	1272	/**
emilmont	77:869cf507173a	1273	* @brief Enable the SDRAM device interrupt.
emilmont	77:869cf507173a	1274	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1275	* @param __INTERRUPT__: FMC_SDRAM interrupt
emilmont	77:869cf507173a	1276	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1277	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
emilmont	77:869cf507173a	1278	* @retval None
emilmont	77:869cf507173a	1279	*/
emilmont	77:869cf507173a	1280	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1281
emilmont	77:869cf507173a	1282	/**
emilmont	77:869cf507173a	1283	* @brief Disable the SDRAM device interrupt.
emilmont	77:869cf507173a	1284	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1285	* @param __INTERRUPT__: FMC_SDRAM interrupt
emilmont	77:869cf507173a	1286	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1287	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
emilmont	77:869cf507173a	1288	* @retval None
emilmont	77:869cf507173a	1289	*/
emilmont	77:869cf507173a	1290	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1291
emilmont	77:869cf507173a	1292	/**
emilmont	77:869cf507173a	1293	* @brief Get flag status of the SDRAM device.
emilmont	77:869cf507173a	1294	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1295	* @param __FLAG__: FMC_SDRAM flag
emilmont	77:869cf507173a	1296	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1297	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
emilmont	77:869cf507173a	1298	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
emilmont	77:869cf507173a	1299	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
emilmont	77:869cf507173a	1300	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	1301	*/
emilmont	77:869cf507173a	1302	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	1303
emilmont	77:869cf507173a	1304	/**
emilmont	77:869cf507173a	1305	* @brief Clear flag status of the SDRAM device.
emilmont	77:869cf507173a	1306	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1307	* @param __FLAG__: FMC_SDRAM flag
emilmont	77:869cf507173a	1308	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1309	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
emilmont	77:869cf507173a	1310	* @retval None
emilmont	77:869cf507173a	1311	*/
emilmont	77:869cf507173a	1312	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
emilmont	77:869cf507173a	1313	/**
emilmont	77:869cf507173a	1314	* @}
emilmont	77:869cf507173a	1315	*/
emilmont	77:869cf507173a	1316
emilmont	77:869cf507173a	1317	/* Exported functions --------------------------------------------------------*/
emilmont	77:869cf507173a	1318
emilmont	77:869cf507173a	1319	/* FMC_NORSRAM Controller functions *******************************************/
emilmont	77:869cf507173a	1320	/* Initialization/de-initialization functions */
emilmont	77:869cf507173a	1321	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
emilmont	77:869cf507173a	1322	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1323	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
emilmont	77:869cf507173a	1324	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
emilmont	77:869cf507173a	1325
emilmont	77:869cf507173a	1326	/* FMC_NORSRAM Control functions */
emilmont	77:869cf507173a	1327	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1328	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1329
emilmont	77:869cf507173a	1330	/* FMC_NAND Controller functions **********************************************/
emilmont	77:869cf507173a	1331	/* Initialization/de-initialization functions */
emilmont	77:869cf507173a	1332	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
emilmont	77:869cf507173a	1333	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1334	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1335	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1336
emilmont	77:869cf507173a	1337	/* FMC_NAND Control functions */
emilmont	77:869cf507173a	1338	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1339	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1340	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
emilmont	77:869cf507173a	1341
emilmont	77:869cf507173a	1342	/* FMC_PCCARD Controller functions ********************************************/
emilmont	77:869cf507173a	1343	/* Initialization/de-initialization functions */
emilmont	77:869cf507173a	1344	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
emilmont	77:869cf507173a	1345	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1346	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1347	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1348	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
emilmont	77:869cf507173a	1349
emilmont	77:869cf507173a	1350	/* FMC_SDRAM Controller functions *********************************************/
emilmont	77:869cf507173a	1351	/* Initialization/de-initialization functions */
emilmont	77:869cf507173a	1352	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
emilmont	77:869cf507173a	1353	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1354	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1355
emilmont	77:869cf507173a	1356	/* FMC_SDRAM Control functions */
emilmont	77:869cf507173a	1357	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1358	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1359	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
emilmont	77:869cf507173a	1360	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
emilmont	77:869cf507173a	1361	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
emilmont	77:869cf507173a	1362	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1363
emilmont	77:869cf507173a	1364	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
emilmont	77:869cf507173a	1365	/**
emilmont	77:869cf507173a	1366	* @}
emilmont	77:869cf507173a	1367	*/
emilmont	77:869cf507173a	1368
emilmont	77:869cf507173a	1369	/**
emilmont	77:869cf507173a	1370	* @}
emilmont	77:869cf507173a	1371	*/
emilmont	77:869cf507173a	1372
emilmont	77:869cf507173a	1373	#ifdef __cplusplus
emilmont	77:869cf507173a	1374	}
emilmont	77:869cf507173a	1375	#endif
emilmont	77:869cf507173a	1376
emilmont	77:869cf507173a	1377	#endif /* __STM32F4xx_LL_FMC_H */
emilmont	77:869cf507173a	1378
emilmont	77:869cf507173a	1379	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
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TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h@90:cb3d968589d8, 2014-10-28 (annotated)

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