Filippo Casamassima / mbed

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Dependents:   Nucleo_blueNRG

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f4xx_hal.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Parent:
85:024bf7f99721 
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.1.0
Kojto 90:cb3d968589d8 6 * @date 19-June-2014
emilmont 77:869cf507173a 7 * @brief This file contains all the functions prototypes for the HAL
emilmont 77:869cf507173a 8 * module driver.
emilmont 77:869cf507173a 9 ******************************************************************************
emilmont 77:869cf507173a 10 * @attention
emilmont 77:869cf507173a 11 *
emilmont 77:869cf507173a 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 13 *
emilmont 77:869cf507173a 14 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 15 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 16 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 17 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 19 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 20 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 22 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 23 * without specific prior written permission.
emilmont 77:869cf507173a 24 *
emilmont 77:869cf507173a 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 35 *
emilmont 77:869cf507173a 36 ******************************************************************************
emilmont 77:869cf507173a 37 */
emilmont 77:869cf507173a 38
emilmont 77:869cf507173a 39 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 40 #ifndef __STM32F4xx_HAL_H
emilmont 77:869cf507173a 41 #define __STM32F4xx_HAL_H
emilmont 77:869cf507173a 42
emilmont 77:869cf507173a 43 #ifdef __cplusplus
emilmont 77:869cf507173a 44 extern "C" {
emilmont 77:869cf507173a 45 #endif
emilmont 77:869cf507173a 46
emilmont 77:869cf507173a 47 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 48 #include "stm32f4xx_hal_conf.h"
emilmont 77:869cf507173a 49
emilmont 77:869cf507173a 50 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 51 * @{
emilmont 77:869cf507173a 52 */
emilmont 77:869cf507173a 53
emilmont 77:869cf507173a 54 /** @addtogroup HAL
emilmont 77:869cf507173a 55 * @{
emilmont 77:869cf507173a 56 */
emilmont 77:869cf507173a 57
emilmont 77:869cf507173a 58 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 59 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 60 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 61
emilmont 77:869cf507173a 62 /** @brief Freeze/Unfreeze Peripherals in Debug mode
emilmont 77:869cf507173a 63 */
emilmont 77:869cf507173a 64 #define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
emilmont 77:869cf507173a 65 #define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
emilmont 77:869cf507173a 66 #define __HAL_FREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM4_STOP))
emilmont 77:869cf507173a 67 #define __HAL_FREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM5_STOP))
emilmont 77:869cf507173a 68 #define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
emilmont 77:869cf507173a 69 #define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
emilmont 77:869cf507173a 70 #define __HAL_FREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM12_STOP))
emilmont 77:869cf507173a 71 #define __HAL_FREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM13_STOP))
emilmont 77:869cf507173a 72 #define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
emilmont 77:869cf507173a 73 #define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
emilmont 77:869cf507173a 74 #define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
emilmont 77:869cf507173a 75 #define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
emilmont 77:869cf507173a 76 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
emilmont 77:869cf507173a 77 #define __HAL_FREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
emilmont 77:869cf507173a 78 #define __HAL_FREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
emilmont 77:869cf507173a 79 #define __HAL_FREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP))
emilmont 77:869cf507173a 80 #define __HAL_FREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN2_STOP))
emilmont 77:869cf507173a 81 #define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
emilmont 77:869cf507173a 82 #define __HAL_FREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM8_STOP))
emilmont 77:869cf507173a 83 #define __HAL_FREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM9_STOP))
emilmont 77:869cf507173a 84 #define __HAL_FREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM10_STOP))
emilmont 77:869cf507173a 85 #define __HAL_FREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM11_STOP))
emilmont 77:869cf507173a 86
emilmont 77:869cf507173a 87 #define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
emilmont 77:869cf507173a 88 #define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
emilmont 77:869cf507173a 89 #define __HAL_UNFREEZE_TIM4_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM4_STOP))
emilmont 77:869cf507173a 90 #define __HAL_UNFREEZE_TIM5_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM5_STOP))
emilmont 77:869cf507173a 91 #define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
emilmont 77:869cf507173a 92 #define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
emilmont 77:869cf507173a 93 #define __HAL_UNFREEZE_TIM12_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM12_STOP))
emilmont 77:869cf507173a 94 #define __HAL_UNFREEZE_TIM13_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM13_STOP))
emilmont 77:869cf507173a 95 #define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
emilmont 77:869cf507173a 96 #define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
emilmont 77:869cf507173a 97 #define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
emilmont 77:869cf507173a 98 #define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
emilmont 77:869cf507173a 99 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
emilmont 77:869cf507173a 100 #define __HAL_UNFREEZE_I2C2_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT))
emilmont 77:869cf507173a 101 #define __HAL_UNFREEZE_I2C3_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT))
emilmont 77:869cf507173a 102 #define __HAL_UNFREEZE_CAN1_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP))
emilmont 77:869cf507173a 103 #define __HAL_UNFREEZE_CAN2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN2_STOP))
emilmont 77:869cf507173a 104 #define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
emilmont 77:869cf507173a 105 #define __HAL_UNFREEZE_TIM8_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM8_STOP))
emilmont 77:869cf507173a 106 #define __HAL_UNFREEZE_TIM9_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM9_STOP))
emilmont 77:869cf507173a 107 #define __HAL_UNFREEZE_TIM10_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM10_STOP))
emilmont 77:869cf507173a 108 #define __HAL_UNFREEZE_TIM11_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM11_STOP))
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 /** @brief Main Flash memory mapped at 0x00000000
emilmont 77:869cf507173a 111 */
bogdanm 81:7d30d6019079 112 #define __HAL_REMAPMEMORY_FLASH() (SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE))
emilmont 77:869cf507173a 113
emilmont 77:869cf507173a 114 /** @brief System Flash memory mapped at 0x00000000
emilmont 77:869cf507173a 115 */
bogdanm 81:7d30d6019079 116 #define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
bogdanm 81:7d30d6019079 117 SYSCFG->MEMRMP |= SYSCFG_MEMRMP_MEM_MODE_0;\
bogdanm 81:7d30d6019079 118 }while(0);
emilmont 77:869cf507173a 119
emilmont 77:869cf507173a 120 /** @brief Embedded SRAM mapped at 0x00000000
emilmont 77:869cf507173a 121 */
bogdanm 81:7d30d6019079 122 #define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
bogdanm 81:7d30d6019079 123 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_0 | SYSCFG_MEMRMP_MEM_MODE_1);\
bogdanm 81:7d30d6019079 124 }while(0);
emilmont 77:869cf507173a 125
emilmont 77:869cf507173a 126 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 127 /** @brief FSMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
emilmont 77:869cf507173a 128 */
bogdanm 81:7d30d6019079 129 #define __HAL_REMAPMEMORY_FSMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
bogdanm 81:7d30d6019079 130 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
bogdanm 81:7d30d6019079 131 }while(0);
emilmont 77:869cf507173a 132 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 133
emilmont 77:869cf507173a 134 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 135 /** @brief FMC Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
emilmont 77:869cf507173a 136 */
bogdanm 81:7d30d6019079 137 #define __HAL_REMAPMEMORY_FMC() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
bogdanm 81:7d30d6019079 138 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_1);\
bogdanm 81:7d30d6019079 139 }while(0);
emilmont 77:869cf507173a 140
emilmont 77:869cf507173a 141 /** @brief FMC/SDRAM Bank 1 and 2 mapped at 0x00000000
emilmont 77:869cf507173a 142 */
bogdanm 81:7d30d6019079 143 #define __HAL_REMAPMEMORY_FMC_SDRAM() do {SYSCFG->MEMRMP &= ~(SYSCFG_MEMRMP_MEM_MODE);\
bogdanm 81:7d30d6019079 144 SYSCFG->MEMRMP |= (SYSCFG_MEMRMP_MEM_MODE_2);\
bogdanm 81:7d30d6019079 145 }while(0);
emilmont 77:869cf507173a 146 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 147
emilmont 77:869cf507173a 148 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 149
emilmont 77:869cf507173a 150 /* Initialization and de-initialization functions ******************************/
emilmont 77:869cf507173a 151 HAL_StatusTypeDef HAL_Init(void);
emilmont 77:869cf507173a 152 HAL_StatusTypeDef HAL_DeInit(void);
bogdanm 81:7d30d6019079 153 void HAL_MspInit(void);
bogdanm 81:7d30d6019079 154 void HAL_MspDeInit(void);
bogdanm 85:024bf7f99721 155 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
emilmont 77:869cf507173a 156
emilmont 77:869cf507173a 157 /* Peripheral Control functions ************************************************/
bogdanm 85:024bf7f99721 158 void HAL_IncTick(void);
bogdanm 85:024bf7f99721 159 void HAL_Delay(__IO uint32_t Delay);
emilmont 77:869cf507173a 160 uint32_t HAL_GetTick(void);
bogdanm 85:024bf7f99721 161 void HAL_SuspendTick(void);
bogdanm 85:024bf7f99721 162 void HAL_ResumeTick(void);
emilmont 77:869cf507173a 163 uint32_t HAL_GetHalVersion(void);
emilmont 77:869cf507173a 164 uint32_t HAL_GetREVID(void);
emilmont 77:869cf507173a 165 uint32_t HAL_GetDEVID(void);
emilmont 77:869cf507173a 166 void HAL_EnableDBGSleepMode(void);
emilmont 77:869cf507173a 167 void HAL_DisableDBGSleepMode(void);
emilmont 77:869cf507173a 168 void HAL_EnableDBGStopMode(void);
emilmont 77:869cf507173a 169 void HAL_DisableDBGStopMode(void);
emilmont 77:869cf507173a 170 void HAL_EnableDBGStandbyMode(void);
emilmont 77:869cf507173a 171 void HAL_DisableDBGStandbyMode(void);
emilmont 77:869cf507173a 172 void HAL_EnableCompensationCell(void);
emilmont 77:869cf507173a 173 void HAL_DisableCompensationCell(void);
emilmont 77:869cf507173a 174 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 175 void HAL_EnableMemorySwappingBank(void);
emilmont 77:869cf507173a 176 void HAL_DisableMemorySwappingBank(void);
emilmont 77:869cf507173a 177 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 178
emilmont 77:869cf507173a 179
emilmont 77:869cf507173a 180 /**
emilmont 77:869cf507173a 181 * @}
emilmont 77:869cf507173a 182 */
emilmont 77:869cf507173a 183
emilmont 77:869cf507173a 184 /**
emilmont 77:869cf507173a 185 * @}
emilmont 77:869cf507173a 186 */
emilmont 77:869cf507173a 187
emilmont 77:869cf507173a 188 #ifdef __cplusplus
emilmont 77:869cf507173a 189 }
emilmont 77:869cf507173a 190 #endif
emilmont 77:869cf507173a 191
emilmont 77:869cf507173a 192 #endif /* __STM32F4xx_HAL_H */
emilmont 77:869cf507173a 193
emilmont 77:869cf507173a 194 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/