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TARGET_NUCLEO_F302R8/stm32f3xx_hal_rcc_ex.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:: Kojto
Date:: Tue Oct 28 16:40:41 2014 +0000
Revision:: 90:cb3d968589d8

Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/**
Kojto	90:cb3d968589d8	2	******************************************************************************
Kojto	90:cb3d968589d8	3	* @file stm32f3xx_hal_rcc_ex.h
Kojto	90:cb3d968589d8	4	* @author MCD Application Team
Kojto	90:cb3d968589d8	5	* @version V1.1.0
Kojto	90:cb3d968589d8	6	* @date 12-Sept-2014
Kojto	90:cb3d968589d8	7	* @brief Header file of RCC HAL Extended module.
Kojto	90:cb3d968589d8	8	******************************************************************************
Kojto	90:cb3d968589d8	9	* @attention
Kojto	90:cb3d968589d8	10	*
Kojto	90:cb3d968589d8	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	90:cb3d968589d8	12	*
Kojto	90:cb3d968589d8	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	14	* are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	90:cb3d968589d8	16	* this list of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	90:cb3d968589d8	18	* this list of conditions and the following disclaimer in the documentation
Kojto	90:cb3d968589d8	19	* and/or other materials provided with the distribution.
Kojto	90:cb3d968589d8	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	90:cb3d968589d8	21	* may be used to endorse or promote products derived from this software
Kojto	90:cb3d968589d8	22	* without specific prior written permission.
Kojto	90:cb3d968589d8	23	*
Kojto	90:cb3d968589d8	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	90:cb3d968589d8	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	90:cb3d968589d8	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	90:cb3d968589d8	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	90:cb3d968589d8	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	90:cb3d968589d8	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	90:cb3d968589d8	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	90:cb3d968589d8	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	90:cb3d968589d8	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	34	*
Kojto	90:cb3d968589d8	35	******************************************************************************
Kojto	90:cb3d968589d8	36	*/
Kojto	90:cb3d968589d8	37
Kojto	90:cb3d968589d8	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	90:cb3d968589d8	39	#ifndef __STM32F3xx_HAL_RCC_EX_H
Kojto	90:cb3d968589d8	40	#define __STM32F3xx_HAL_RCC_EX_H
Kojto	90:cb3d968589d8	41
Kojto	90:cb3d968589d8	42	#ifdef __cplusplus
Kojto	90:cb3d968589d8	43	extern "C" {
Kojto	90:cb3d968589d8	44	#endif
Kojto	90:cb3d968589d8	45
Kojto	90:cb3d968589d8	46	/* Includes ------------------------------------------------------------------*/
Kojto	90:cb3d968589d8	47	#include "stm32f3xx_hal_def.h"
Kojto	90:cb3d968589d8	48
Kojto	90:cb3d968589d8	49	/** @addtogroup STM32F3xx_HAL_Driver
Kojto	90:cb3d968589d8	50	* @{
Kojto	90:cb3d968589d8	51	*/
Kojto	90:cb3d968589d8	52
Kojto	90:cb3d968589d8	53	/** @addtogroup RCCEx
Kojto	90:cb3d968589d8	54	* @{
Kojto	90:cb3d968589d8	55	*/
Kojto	90:cb3d968589d8	56
Kojto	90:cb3d968589d8	57	/* Exported types ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	58
Kojto	90:cb3d968589d8	59	/** @defgroup RCCEx_Exported_Types RCC Extended Exported Types
Kojto	90:cb3d968589d8	60	* @{
Kojto	90:cb3d968589d8	61	*/
Kojto	90:cb3d968589d8	62	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	63	/**
Kojto	90:cb3d968589d8	64	* @brief RCC PLL configuration structure definition
Kojto	90:cb3d968589d8	65	*/
Kojto	90:cb3d968589d8	66	typedef struct
Kojto	90:cb3d968589d8	67	{
Kojto	90:cb3d968589d8	68	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto	90:cb3d968589d8	69	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	90:cb3d968589d8	70
Kojto	90:cb3d968589d8	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	90:cb3d968589d8	72	This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
Kojto	90:cb3d968589d8	73
Kojto	90:cb3d968589d8	74	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	90:cb3d968589d8	75	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto	90:cb3d968589d8	76
Kojto	90:cb3d968589d8	77	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto	90:cb3d968589d8	78	This parameter must be a value of @ref RCCEx_PLL_Prediv_Factor */
Kojto	90:cb3d968589d8	79
Kojto	90:cb3d968589d8	80	}RCC_PLLInitTypeDef;
Kojto	90:cb3d968589d8	81
Kojto	90:cb3d968589d8	82	/**
Kojto	90:cb3d968589d8	83	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	90:cb3d968589d8	84	*/
Kojto	90:cb3d968589d8	85	typedef struct
Kojto	90:cb3d968589d8	86	{
Kojto	90:cb3d968589d8	87	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	90:cb3d968589d8	88	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	90:cb3d968589d8	89
Kojto	90:cb3d968589d8	90	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	90:cb3d968589d8	91	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	90:cb3d968589d8	92
Kojto	90:cb3d968589d8	93	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	90:cb3d968589d8	94	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	90:cb3d968589d8	95
Kojto	90:cb3d968589d8	96	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	90:cb3d968589d8	97	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	90:cb3d968589d8	98
Kojto	90:cb3d968589d8	99	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto	90:cb3d968589d8	100	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	90:cb3d968589d8	101
Kojto	90:cb3d968589d8	102	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	90:cb3d968589d8	103	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	90:cb3d968589d8	104
Kojto	90:cb3d968589d8	105	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	90:cb3d968589d8	106
Kojto	90:cb3d968589d8	107	}RCC_OscInitTypeDef;
Kojto	90:cb3d968589d8	108
Kojto	90:cb3d968589d8	109	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	110
Kojto	90:cb3d968589d8	111	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	112	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	113	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
Kojto	90:cb3d968589d8	114	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	115	/**
Kojto	90:cb3d968589d8	116	* @brief RCC PLL configuration structure definition
Kojto	90:cb3d968589d8	117	*/
Kojto	90:cb3d968589d8	118	typedef struct
Kojto	90:cb3d968589d8	119	{
Kojto	90:cb3d968589d8	120	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto	90:cb3d968589d8	121	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	90:cb3d968589d8	122
Kojto	90:cb3d968589d8	123	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	90:cb3d968589d8	124	This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
Kojto	90:cb3d968589d8	125
Kojto	90:cb3d968589d8	126	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	90:cb3d968589d8	127	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto	90:cb3d968589d8	128
Kojto	90:cb3d968589d8	129	}RCC_PLLInitTypeDef;
Kojto	90:cb3d968589d8	130
Kojto	90:cb3d968589d8	131	/**
Kojto	90:cb3d968589d8	132	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	90:cb3d968589d8	133	*/
Kojto	90:cb3d968589d8	134	typedef struct
Kojto	90:cb3d968589d8	135	{
Kojto	90:cb3d968589d8	136	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	90:cb3d968589d8	137	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	90:cb3d968589d8	138
Kojto	90:cb3d968589d8	139	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	90:cb3d968589d8	140	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	90:cb3d968589d8	141
Kojto	90:cb3d968589d8	142	uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
Kojto	90:cb3d968589d8	143	This parameter can be a value of @ref RCCEx_HSE_Predivision_Factor */
Kojto	90:cb3d968589d8	144
Kojto	90:cb3d968589d8	145	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	90:cb3d968589d8	146	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	90:cb3d968589d8	147
Kojto	90:cb3d968589d8	148	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	90:cb3d968589d8	149	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	90:cb3d968589d8	150
Kojto	90:cb3d968589d8	151	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
Kojto	90:cb3d968589d8	152	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	90:cb3d968589d8	153
Kojto	90:cb3d968589d8	154	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	90:cb3d968589d8	155	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	90:cb3d968589d8	156
Kojto	90:cb3d968589d8	157	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	90:cb3d968589d8	158
Kojto	90:cb3d968589d8	159	}RCC_OscInitTypeDef;
Kojto	90:cb3d968589d8	160	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	161	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	162	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	163	/* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	164
Kojto	90:cb3d968589d8	165	/**
Kojto	90:cb3d968589d8	166	* @brief RCC extended clocks structure definition
Kojto	90:cb3d968589d8	167	*/
Kojto	90:cb3d968589d8	168	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	169	typedef struct
Kojto	90:cb3d968589d8	170	{
Kojto	90:cb3d968589d8	171	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	172	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	173
Kojto	90:cb3d968589d8	174	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	175	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	176
Kojto	90:cb3d968589d8	177	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	178	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	179
Kojto	90:cb3d968589d8	180	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	181	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	182
Kojto	90:cb3d968589d8	183	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	184	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	185
Kojto	90:cb3d968589d8	186	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	187	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	188
Kojto	90:cb3d968589d8	189	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	190	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	191
Kojto	90:cb3d968589d8	192	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	90:cb3d968589d8	193	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	90:cb3d968589d8	194
Kojto	90:cb3d968589d8	195	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto	90:cb3d968589d8	196	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto	90:cb3d968589d8	197
Kojto	90:cb3d968589d8	198	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	90:cb3d968589d8	199	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	90:cb3d968589d8	200
Kojto	90:cb3d968589d8	201	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	202	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	203
Kojto	90:cb3d968589d8	204	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	90:cb3d968589d8	205	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	90:cb3d968589d8	206
Kojto	90:cb3d968589d8	207	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	90:cb3d968589d8	208	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	90:cb3d968589d8	209
Kojto	90:cb3d968589d8	210	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	90:cb3d968589d8	211	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	90:cb3d968589d8	212	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	213	#endif /* STM32F301x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	214
Kojto	90:cb3d968589d8	215	#if defined(STM32F302x8)
Kojto	90:cb3d968589d8	216	typedef struct
Kojto	90:cb3d968589d8	217	{
Kojto	90:cb3d968589d8	218	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	219	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	220
Kojto	90:cb3d968589d8	221	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	222	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	223
Kojto	90:cb3d968589d8	224	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	225	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	226
Kojto	90:cb3d968589d8	227	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	228	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	229
Kojto	90:cb3d968589d8	230	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	231	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	232
Kojto	90:cb3d968589d8	233	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	234	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	235
Kojto	90:cb3d968589d8	236	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	237	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	238
Kojto	90:cb3d968589d8	239	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	90:cb3d968589d8	240	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	90:cb3d968589d8	241
Kojto	90:cb3d968589d8	242	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto	90:cb3d968589d8	243	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto	90:cb3d968589d8	244
Kojto	90:cb3d968589d8	245	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	90:cb3d968589d8	246	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	90:cb3d968589d8	247
Kojto	90:cb3d968589d8	248	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	249	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	250
Kojto	90:cb3d968589d8	251	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	90:cb3d968589d8	252	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	90:cb3d968589d8	253
Kojto	90:cb3d968589d8	254	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	90:cb3d968589d8	255	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	90:cb3d968589d8	256
Kojto	90:cb3d968589d8	257	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	90:cb3d968589d8	258	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	90:cb3d968589d8	259
Kojto	90:cb3d968589d8	260	uint32_t USBClockSelection; /*!< USB clock source
Kojto	90:cb3d968589d8	261	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	90:cb3d968589d8	262
Kojto	90:cb3d968589d8	263	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	264	#endif /* STM32F302x8 */
Kojto	90:cb3d968589d8	265
Kojto	90:cb3d968589d8	266	#if defined(STM32F302xC)
Kojto	90:cb3d968589d8	267	typedef struct
Kojto	90:cb3d968589d8	268	{
Kojto	90:cb3d968589d8	269	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	270	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	271
Kojto	90:cb3d968589d8	272	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	273	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	274
Kojto	90:cb3d968589d8	275	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	276	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	277
Kojto	90:cb3d968589d8	278	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	279	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	280
Kojto	90:cb3d968589d8	281	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	282	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	283
Kojto	90:cb3d968589d8	284	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	90:cb3d968589d8	285	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	90:cb3d968589d8	286
Kojto	90:cb3d968589d8	287	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	90:cb3d968589d8	288	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	90:cb3d968589d8	289
Kojto	90:cb3d968589d8	290	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	291	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	292
Kojto	90:cb3d968589d8	293	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	294	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	295
Kojto	90:cb3d968589d8	296	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	297	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	298
Kojto	90:cb3d968589d8	299	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	90:cb3d968589d8	300	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	90:cb3d968589d8	301
Kojto	90:cb3d968589d8	302	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	303	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	304
Kojto	90:cb3d968589d8	305	uint32_t USBClockSelection; /*!< USB clock source
Kojto	90:cb3d968589d8	306	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	90:cb3d968589d8	307
Kojto	90:cb3d968589d8	308	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	309	#endif /* STM32F302xC */
Kojto	90:cb3d968589d8	310
Kojto	90:cb3d968589d8	311	#if defined(STM32F303xC)
Kojto	90:cb3d968589d8	312	typedef struct
Kojto	90:cb3d968589d8	313	{
Kojto	90:cb3d968589d8	314	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	315	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	316
Kojto	90:cb3d968589d8	317	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	318	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	319
Kojto	90:cb3d968589d8	320	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	321	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	322
Kojto	90:cb3d968589d8	323	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	324	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	325
Kojto	90:cb3d968589d8	326	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	327	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	328
Kojto	90:cb3d968589d8	329	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	90:cb3d968589d8	330	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	90:cb3d968589d8	331
Kojto	90:cb3d968589d8	332	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	90:cb3d968589d8	333	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	90:cb3d968589d8	334
Kojto	90:cb3d968589d8	335	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	336	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	337
Kojto	90:cb3d968589d8	338	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	339	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	340
Kojto	90:cb3d968589d8	341	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	342	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	343
Kojto	90:cb3d968589d8	344	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto	90:cb3d968589d8	345	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto	90:cb3d968589d8	346
Kojto	90:cb3d968589d8	347	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	90:cb3d968589d8	348	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	90:cb3d968589d8	349
Kojto	90:cb3d968589d8	350	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	351	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	352
Kojto	90:cb3d968589d8	353	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto	90:cb3d968589d8	354	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto	90:cb3d968589d8	355
Kojto	90:cb3d968589d8	356	uint32_t USBClockSelection; /*!< USB clock source
Kojto	90:cb3d968589d8	357	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	90:cb3d968589d8	358
Kojto	90:cb3d968589d8	359	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	360	#endif /* STM32F303xC */
Kojto	90:cb3d968589d8	361
Kojto	90:cb3d968589d8	362	#if defined(STM32F302xE)
Kojto	90:cb3d968589d8	363	typedef struct
Kojto	90:cb3d968589d8	364	{
Kojto	90:cb3d968589d8	365	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	366	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	367
Kojto	90:cb3d968589d8	368	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	369	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	370
Kojto	90:cb3d968589d8	371	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	372	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	373
Kojto	90:cb3d968589d8	374	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	375	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	376
Kojto	90:cb3d968589d8	377	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	378	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	379
Kojto	90:cb3d968589d8	380	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	90:cb3d968589d8	381	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	90:cb3d968589d8	382
Kojto	90:cb3d968589d8	383	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	90:cb3d968589d8	384	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	90:cb3d968589d8	385
Kojto	90:cb3d968589d8	386	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	387	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	388
Kojto	90:cb3d968589d8	389	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	390	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	391
Kojto	90:cb3d968589d8	392	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	90:cb3d968589d8	393	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	90:cb3d968589d8	394
Kojto	90:cb3d968589d8	395	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	396	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	397
Kojto	90:cb3d968589d8	398	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	90:cb3d968589d8	399	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	90:cb3d968589d8	400
Kojto	90:cb3d968589d8	401	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	402	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	403
Kojto	90:cb3d968589d8	404	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto	90:cb3d968589d8	405	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto	90:cb3d968589d8	406
Kojto	90:cb3d968589d8	407	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto	90:cb3d968589d8	408	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto	90:cb3d968589d8	409
Kojto	90:cb3d968589d8	410	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	90:cb3d968589d8	411	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	90:cb3d968589d8	412
Kojto	90:cb3d968589d8	413	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	90:cb3d968589d8	414	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	90:cb3d968589d8	415
Kojto	90:cb3d968589d8	416	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	90:cb3d968589d8	417	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	90:cb3d968589d8	418
Kojto	90:cb3d968589d8	419	uint32_t USBClockSelection; /*!< USB clock source
Kojto	90:cb3d968589d8	420	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	90:cb3d968589d8	421
Kojto	90:cb3d968589d8	422	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	423	#endif /* STM32F302xE */
Kojto	90:cb3d968589d8	424
Kojto	90:cb3d968589d8	425	#if defined(STM32F303xE)
Kojto	90:cb3d968589d8	426	typedef struct
Kojto	90:cb3d968589d8	427	{
Kojto	90:cb3d968589d8	428	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	429	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	430
Kojto	90:cb3d968589d8	431	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	432	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	433
Kojto	90:cb3d968589d8	434	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	435	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	436
Kojto	90:cb3d968589d8	437	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	438	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	439
Kojto	90:cb3d968589d8	440	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	441	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	442
Kojto	90:cb3d968589d8	443	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	90:cb3d968589d8	444	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	90:cb3d968589d8	445
Kojto	90:cb3d968589d8	446	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	90:cb3d968589d8	447	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	90:cb3d968589d8	448
Kojto	90:cb3d968589d8	449	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	450	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	451
Kojto	90:cb3d968589d8	452	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	453	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	454
Kojto	90:cb3d968589d8	455	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	90:cb3d968589d8	456	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	90:cb3d968589d8	457
Kojto	90:cb3d968589d8	458	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	459	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	460
Kojto	90:cb3d968589d8	461	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto	90:cb3d968589d8	462	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto	90:cb3d968589d8	463
Kojto	90:cb3d968589d8	464	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	90:cb3d968589d8	465	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	90:cb3d968589d8	466
Kojto	90:cb3d968589d8	467	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	468	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	469
Kojto	90:cb3d968589d8	470	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto	90:cb3d968589d8	471	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto	90:cb3d968589d8	472
Kojto	90:cb3d968589d8	473	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto	90:cb3d968589d8	474	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto	90:cb3d968589d8	475
Kojto	90:cb3d968589d8	476	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto	90:cb3d968589d8	477	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto	90:cb3d968589d8	478
Kojto	90:cb3d968589d8	479	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	90:cb3d968589d8	480	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	90:cb3d968589d8	481
Kojto	90:cb3d968589d8	482	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	90:cb3d968589d8	483	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	90:cb3d968589d8	484
Kojto	90:cb3d968589d8	485	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	90:cb3d968589d8	486	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	90:cb3d968589d8	487
Kojto	90:cb3d968589d8	488	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
Kojto	90:cb3d968589d8	489	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
Kojto	90:cb3d968589d8	490
Kojto	90:cb3d968589d8	491	uint32_t USBClockSelection; /*!< USB clock source
Kojto	90:cb3d968589d8	492	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	90:cb3d968589d8	493
Kojto	90:cb3d968589d8	494	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	495	#endif /* STM32F303xE */
Kojto	90:cb3d968589d8	496
Kojto	90:cb3d968589d8	497	#if defined(STM32F398xx)
Kojto	90:cb3d968589d8	498	typedef struct
Kojto	90:cb3d968589d8	499	{
Kojto	90:cb3d968589d8	500	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	501	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	502
Kojto	90:cb3d968589d8	503	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	504	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	505
Kojto	90:cb3d968589d8	506	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	507	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	508
Kojto	90:cb3d968589d8	509	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	510	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	511
Kojto	90:cb3d968589d8	512	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	513	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	514
Kojto	90:cb3d968589d8	515	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	90:cb3d968589d8	516	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	90:cb3d968589d8	517
Kojto	90:cb3d968589d8	518	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	90:cb3d968589d8	519	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	90:cb3d968589d8	520
Kojto	90:cb3d968589d8	521	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	522	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	523
Kojto	90:cb3d968589d8	524	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	525	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	526
Kojto	90:cb3d968589d8	527	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	90:cb3d968589d8	528	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	90:cb3d968589d8	529
Kojto	90:cb3d968589d8	530	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	531	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	532
Kojto	90:cb3d968589d8	533	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto	90:cb3d968589d8	534	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto	90:cb3d968589d8	535
Kojto	90:cb3d968589d8	536	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	90:cb3d968589d8	537	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	90:cb3d968589d8	538
Kojto	90:cb3d968589d8	539	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	540	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	541
Kojto	90:cb3d968589d8	542	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
Kojto	90:cb3d968589d8	543	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
Kojto	90:cb3d968589d8	544
Kojto	90:cb3d968589d8	545	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
Kojto	90:cb3d968589d8	546	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
Kojto	90:cb3d968589d8	547
Kojto	90:cb3d968589d8	548	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto	90:cb3d968589d8	549	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto	90:cb3d968589d8	550
Kojto	90:cb3d968589d8	551	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
Kojto	90:cb3d968589d8	552	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
Kojto	90:cb3d968589d8	553
Kojto	90:cb3d968589d8	554	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
Kojto	90:cb3d968589d8	555	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
Kojto	90:cb3d968589d8	556
Kojto	90:cb3d968589d8	557	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
Kojto	90:cb3d968589d8	558	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
Kojto	90:cb3d968589d8	559
Kojto	90:cb3d968589d8	560	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
Kojto	90:cb3d968589d8	561	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
Kojto	90:cb3d968589d8	562
Kojto	90:cb3d968589d8	563	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	564	#endif /* STM32F398xx */
Kojto	90:cb3d968589d8	565
Kojto	90:cb3d968589d8	566	#if defined(STM32F358xx)
Kojto	90:cb3d968589d8	567	typedef struct
Kojto	90:cb3d968589d8	568	{
Kojto	90:cb3d968589d8	569	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	570	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	571
Kojto	90:cb3d968589d8	572	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	573	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	574
Kojto	90:cb3d968589d8	575	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	576	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	577
Kojto	90:cb3d968589d8	578	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	579	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	580
Kojto	90:cb3d968589d8	581	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	582	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	583
Kojto	90:cb3d968589d8	584	uint32_t Uart4ClockSelection; /*!< UART4 clock source
Kojto	90:cb3d968589d8	585	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
Kojto	90:cb3d968589d8	586
Kojto	90:cb3d968589d8	587	uint32_t Uart5ClockSelection; /*!< UART5 clock source
Kojto	90:cb3d968589d8	588	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
Kojto	90:cb3d968589d8	589
Kojto	90:cb3d968589d8	590	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	591	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	592
Kojto	90:cb3d968589d8	593	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	594	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	595
Kojto	90:cb3d968589d8	596	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	597	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	598
Kojto	90:cb3d968589d8	599	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
Kojto	90:cb3d968589d8	600	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
Kojto	90:cb3d968589d8	601
Kojto	90:cb3d968589d8	602	uint32_t I2sClockSelection; /*!< I2S clock source
Kojto	90:cb3d968589d8	603	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
Kojto	90:cb3d968589d8	604
Kojto	90:cb3d968589d8	605	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	606	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	607
Kojto	90:cb3d968589d8	608	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
Kojto	90:cb3d968589d8	609	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
Kojto	90:cb3d968589d8	610
Kojto	90:cb3d968589d8	611	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	612	#endif /* STM32F358xx */
Kojto	90:cb3d968589d8	613
Kojto	90:cb3d968589d8	614	#if defined(STM32F303x8)
Kojto	90:cb3d968589d8	615	typedef struct
Kojto	90:cb3d968589d8	616	{
Kojto	90:cb3d968589d8	617	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	618	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	619
Kojto	90:cb3d968589d8	620	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	621	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	622
Kojto	90:cb3d968589d8	623	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	624	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	625
Kojto	90:cb3d968589d8	626	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	627	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	628
Kojto	90:cb3d968589d8	629	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	630	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	631
Kojto	90:cb3d968589d8	632	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	633	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	634
Kojto	90:cb3d968589d8	635	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	636	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	637
Kojto	90:cb3d968589d8	638	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	639	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	640
Kojto	90:cb3d968589d8	641	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	642	#endif /* STM32F303x8 */
Kojto	90:cb3d968589d8	643
Kojto	90:cb3d968589d8	644	#if defined(STM32F334x8)
Kojto	90:cb3d968589d8	645	typedef struct
Kojto	90:cb3d968589d8	646	{
Kojto	90:cb3d968589d8	647	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	648	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	649
Kojto	90:cb3d968589d8	650	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	651	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	652
Kojto	90:cb3d968589d8	653	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	654	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	655
Kojto	90:cb3d968589d8	656	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	657	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	658
Kojto	90:cb3d968589d8	659	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	660	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	661
Kojto	90:cb3d968589d8	662	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	663	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	664
Kojto	90:cb3d968589d8	665	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	666	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	667
Kojto	90:cb3d968589d8	668	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	669	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	670
Kojto	90:cb3d968589d8	671	uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
Kojto	90:cb3d968589d8	672	This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
Kojto	90:cb3d968589d8	673
Kojto	90:cb3d968589d8	674	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	675	#endif /* STM32F334x8 */
Kojto	90:cb3d968589d8	676
Kojto	90:cb3d968589d8	677	#if defined(STM32F328xx)
Kojto	90:cb3d968589d8	678	typedef struct
Kojto	90:cb3d968589d8	679	{
Kojto	90:cb3d968589d8	680	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	681	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	682
Kojto	90:cb3d968589d8	683	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	684	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	685
Kojto	90:cb3d968589d8	686	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	687	This parameter can be a value of @ref RCC_USART1_Clock_Source */
Kojto	90:cb3d968589d8	688
Kojto	90:cb3d968589d8	689	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	690	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	691
Kojto	90:cb3d968589d8	692	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	693	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	694
Kojto	90:cb3d968589d8	695	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	696	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	697
Kojto	90:cb3d968589d8	698	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
Kojto	90:cb3d968589d8	699	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
Kojto	90:cb3d968589d8	700
Kojto	90:cb3d968589d8	701	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
Kojto	90:cb3d968589d8	702	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
Kojto	90:cb3d968589d8	703
Kojto	90:cb3d968589d8	704	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	705	#endif /* STM32F328xx */
Kojto	90:cb3d968589d8	706
Kojto	90:cb3d968589d8	707	#if defined(STM32F373xC)
Kojto	90:cb3d968589d8	708	typedef struct
Kojto	90:cb3d968589d8	709	{
Kojto	90:cb3d968589d8	710	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	711	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	712
Kojto	90:cb3d968589d8	713	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	714	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	715
Kojto	90:cb3d968589d8	716	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	717	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	718
Kojto	90:cb3d968589d8	719	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	720	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	721
Kojto	90:cb3d968589d8	722	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	723	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	724
Kojto	90:cb3d968589d8	725	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	726	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	727
Kojto	90:cb3d968589d8	728	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	729	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	730
Kojto	90:cb3d968589d8	731	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto	90:cb3d968589d8	732	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto	90:cb3d968589d8	733
Kojto	90:cb3d968589d8	734	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
Kojto	90:cb3d968589d8	735	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
Kojto	90:cb3d968589d8	736
Kojto	90:cb3d968589d8	737	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	90:cb3d968589d8	738	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	90:cb3d968589d8	739
Kojto	90:cb3d968589d8	740	uint32_t USBClockSelection; /*!< USB clock source
Kojto	90:cb3d968589d8	741	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
Kojto	90:cb3d968589d8	742
Kojto	90:cb3d968589d8	743	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	744	#endif /* STM32F373xC */
Kojto	90:cb3d968589d8	745
Kojto	90:cb3d968589d8	746	#if defined(STM32F378xx)
Kojto	90:cb3d968589d8	747	typedef struct
Kojto	90:cb3d968589d8	748	{
Kojto	90:cb3d968589d8	749	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
Kojto	90:cb3d968589d8	750	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	90:cb3d968589d8	751
Kojto	90:cb3d968589d8	752	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	90:cb3d968589d8	753	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	90:cb3d968589d8	754
Kojto	90:cb3d968589d8	755	uint32_t Usart1ClockSelection; /*!< USART1 clock source
Kojto	90:cb3d968589d8	756	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	90:cb3d968589d8	757
Kojto	90:cb3d968589d8	758	uint32_t Usart2ClockSelection; /*!< USART2 clock source
Kojto	90:cb3d968589d8	759	This parameter can be a value of @ref RCC_USART2_Clock_Source */
Kojto	90:cb3d968589d8	760
Kojto	90:cb3d968589d8	761	uint32_t Usart3ClockSelection; /*!< USART3 clock source
Kojto	90:cb3d968589d8	762	This parameter can be a value of @ref RCC_USART3_Clock_Source */
Kojto	90:cb3d968589d8	763
Kojto	90:cb3d968589d8	764	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
Kojto	90:cb3d968589d8	765	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
Kojto	90:cb3d968589d8	766
Kojto	90:cb3d968589d8	767	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
Kojto	90:cb3d968589d8	768	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
Kojto	90:cb3d968589d8	769
Kojto	90:cb3d968589d8	770	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
Kojto	90:cb3d968589d8	771	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
Kojto	90:cb3d968589d8	772
Kojto	90:cb3d968589d8	773	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
Kojto	90:cb3d968589d8	774	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
Kojto	90:cb3d968589d8	775
Kojto	90:cb3d968589d8	776	uint32_t CecClockSelection; /*!< HDMI CEC clock source
Kojto	90:cb3d968589d8	777	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
Kojto	90:cb3d968589d8	778
Kojto	90:cb3d968589d8	779	}RCC_PeriphCLKInitTypeDef;
Kojto	90:cb3d968589d8	780	#endif /* STM32F378xx */
Kojto	90:cb3d968589d8	781
Kojto	90:cb3d968589d8	782	/**
Kojto	90:cb3d968589d8	783	* @}
Kojto	90:cb3d968589d8	784	*/
Kojto	90:cb3d968589d8	785
Kojto	90:cb3d968589d8	786	/* Exported constants --------------------------------------------------------*/
Kojto	90:cb3d968589d8	787	/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
Kojto	90:cb3d968589d8	788	* @{
Kojto	90:cb3d968589d8	789	*/
Kojto	90:cb3d968589d8	790	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	791	defined(STM32F334x8) \|\| \
Kojto	90:cb3d968589d8	792	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	793	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
Kojto	90:cb3d968589d8	794	* @{
Kojto	90:cb3d968589d8	795	*/
Kojto	90:cb3d968589d8	796	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto	90:cb3d968589d8	797	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto	90:cb3d968589d8	798	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto	90:cb3d968589d8	799	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto	90:cb3d968589d8	800	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto	90:cb3d968589d8	801	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto	90:cb3d968589d8	802	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto	90:cb3d968589d8	803
Kojto	90:cb3d968589d8	804	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	90:cb3d968589d8	805	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	90:cb3d968589d8	806	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	807	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	808	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	809	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	810	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
Kojto	90:cb3d968589d8	811	/**
Kojto	90:cb3d968589d8	812	* @}
Kojto	90:cb3d968589d8	813	*/
Kojto	90:cb3d968589d8	814	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	815	/* STM32F334x8 */
Kojto	90:cb3d968589d8	816	/* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	817
Kojto	90:cb3d968589d8	818	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	819	defined(STM32F303x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	820	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	821	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
Kojto	90:cb3d968589d8	822	* @{
Kojto	90:cb3d968589d8	823	*/
Kojto	90:cb3d968589d8	824	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto	90:cb3d968589d8	825	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto	90:cb3d968589d8	826	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto	90:cb3d968589d8	827	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto	90:cb3d968589d8	828	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto	90:cb3d968589d8	829	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto	90:cb3d968589d8	830	#define RCC_MCOSOURCE_PLLCLK_DIV1 (RCC_CFGR_PLLNODIV \| RCC_CFGR_MCO_PLL)
Kojto	90:cb3d968589d8	831	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto	90:cb3d968589d8	832
Kojto	90:cb3d968589d8	833	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
Kojto	90:cb3d968589d8	834	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
Kojto	90:cb3d968589d8	835	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	836	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	837	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	838	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	839	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV1) \|\| \
Kojto	90:cb3d968589d8	840	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
Kojto	90:cb3d968589d8	841	/**
Kojto	90:cb3d968589d8	842	* @}
Kojto	90:cb3d968589d8	843	*/
Kojto	90:cb3d968589d8	844	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	845	/* STM32F303x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	846	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	847
Kojto	90:cb3d968589d8	848	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	849	/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
Kojto	90:cb3d968589d8	850	* @{
Kojto	90:cb3d968589d8	851	*/
Kojto	90:cb3d968589d8	852	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
Kojto	90:cb3d968589d8	853	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
Kojto	90:cb3d968589d8	854
Kojto	90:cb3d968589d8	855	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	856	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	90:cb3d968589d8	857	/**
Kojto	90:cb3d968589d8	858	* @}
Kojto	90:cb3d968589d8	859	*/
Kojto	90:cb3d968589d8	860
Kojto	90:cb3d968589d8	861	/** @defgroup RCCEx_PLL_Prediv_Factor RCC Extended PLL Prediv Factor
Kojto	90:cb3d968589d8	862	* @{
Kojto	90:cb3d968589d8	863	*/
Kojto	90:cb3d968589d8	864	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto	90:cb3d968589d8	865	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto	90:cb3d968589d8	866	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto	90:cb3d968589d8	867	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto	90:cb3d968589d8	868	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto	90:cb3d968589d8	869	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto	90:cb3d968589d8	870	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto	90:cb3d968589d8	871	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto	90:cb3d968589d8	872	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto	90:cb3d968589d8	873	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto	90:cb3d968589d8	874	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto	90:cb3d968589d8	875	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto	90:cb3d968589d8	876	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto	90:cb3d968589d8	877	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto	90:cb3d968589d8	878	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto	90:cb3d968589d8	879	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto	90:cb3d968589d8	880
Kojto	90:cb3d968589d8	881	#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) \|\| ((PREDIV) == RCC_PREDIV_DIV2) \|\| \
Kojto	90:cb3d968589d8	882	((PREDIV) == RCC_PREDIV_DIV3) \|\| ((PREDIV) == RCC_PREDIV_DIV4) \|\| \
Kojto	90:cb3d968589d8	883	((PREDIV) == RCC_PREDIV_DIV5) \|\| ((PREDIV) == RCC_PREDIV_DIV6) \|\| \
Kojto	90:cb3d968589d8	884	((PREDIV) == RCC_PREDIV_DIV7) \|\| ((PREDIV) == RCC_PREDIV_DIV8) \|\| \
Kojto	90:cb3d968589d8	885	((PREDIV) == RCC_PREDIV_DIV9) \|\| ((PREDIV) == RCC_PREDIV_DIV10) \|\| \
Kojto	90:cb3d968589d8	886	((PREDIV) == RCC_PREDIV_DIV11) \|\| ((PREDIV) == RCC_PREDIV_DIV12) \|\| \
Kojto	90:cb3d968589d8	887	((PREDIV) == RCC_PREDIV_DIV13) \|\| ((PREDIV) == RCC_PREDIV_DIV14) \|\| \
Kojto	90:cb3d968589d8	888	((PREDIV) == RCC_PREDIV_DIV15) \|\| ((PREDIV) == RCC_PREDIV_DIV16))
Kojto	90:cb3d968589d8	889	/**
Kojto	90:cb3d968589d8	890	* @}
Kojto	90:cb3d968589d8	891	*/
Kojto	90:cb3d968589d8	892	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	893
Kojto	90:cb3d968589d8	894	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	895	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	896	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
Kojto	90:cb3d968589d8	897	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	898	/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
Kojto	90:cb3d968589d8	899	* @{
Kojto	90:cb3d968589d8	900	*/
Kojto	90:cb3d968589d8	901	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
Kojto	90:cb3d968589d8	902	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
Kojto	90:cb3d968589d8	903
Kojto	90:cb3d968589d8	904	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	905	((SOURCE) == RCC_PLLSOURCE_HSE))
Kojto	90:cb3d968589d8	906	/**
Kojto	90:cb3d968589d8	907	* @}
Kojto	90:cb3d968589d8	908	*/
Kojto	90:cb3d968589d8	909
Kojto	90:cb3d968589d8	910	/** @defgroup RCCEx_HSE_Predivision_Factor RCC Extended HSE Predivision Factor
Kojto	90:cb3d968589d8	911	* @{
Kojto	90:cb3d968589d8	912	*/
Kojto	90:cb3d968589d8	913
Kojto	90:cb3d968589d8	914	#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto	90:cb3d968589d8	915	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto	90:cb3d968589d8	916	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto	90:cb3d968589d8	917	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto	90:cb3d968589d8	918	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto	90:cb3d968589d8	919	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto	90:cb3d968589d8	920	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto	90:cb3d968589d8	921	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto	90:cb3d968589d8	922	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto	90:cb3d968589d8	923	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto	90:cb3d968589d8	924	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto	90:cb3d968589d8	925	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto	90:cb3d968589d8	926	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto	90:cb3d968589d8	927	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto	90:cb3d968589d8	928	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto	90:cb3d968589d8	929	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto	90:cb3d968589d8	930
Kojto	90:cb3d968589d8	931	#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) \|\| ((DIV) == RCC_HSE_PREDIV_DIV2) \|\| \
Kojto	90:cb3d968589d8	932	((DIV) == RCC_HSE_PREDIV_DIV3) \|\| ((DIV) == RCC_HSE_PREDIV_DIV4) \|\| \
Kojto	90:cb3d968589d8	933	((DIV) == RCC_HSE_PREDIV_DIV5) \|\| ((DIV) == RCC_HSE_PREDIV_DIV6) \|\| \
Kojto	90:cb3d968589d8	934	((DIV) == RCC_HSE_PREDIV_DIV7) \|\| ((DIV) == RCC_HSE_PREDIV_DIV8) \|\| \
Kojto	90:cb3d968589d8	935	((DIV) == RCC_HSE_PREDIV_DIV9) \|\| ((DIV) == RCC_HSE_PREDIV_DIV10) \|\| \
Kojto	90:cb3d968589d8	936	((DIV) == RCC_HSE_PREDIV_DIV11) \|\| ((DIV) == RCC_HSE_PREDIV_DIV12) \|\| \
Kojto	90:cb3d968589d8	937	((DIV) == RCC_HSE_PREDIV_DIV13) \|\| ((DIV) == RCC_HSE_PREDIV_DIV14) \|\| \
Kojto	90:cb3d968589d8	938	((DIV) == RCC_HSE_PREDIV_DIV15) \|\| ((DIV) == RCC_HSE_PREDIV_DIV16))
Kojto	90:cb3d968589d8	939	/**
Kojto	90:cb3d968589d8	940	* @}
Kojto	90:cb3d968589d8	941	*/
Kojto	90:cb3d968589d8	942	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	943	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	944	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	945	/* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	946
Kojto	90:cb3d968589d8	947	/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
Kojto	90:cb3d968589d8	948	* @{
Kojto	90:cb3d968589d8	949	*/
Kojto	90:cb3d968589d8	950	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	951	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	952	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	953	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	954	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	955	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	956	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	957	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	958	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	959	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	960	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	961	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	962	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	963	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	964
Kojto	90:cb3d968589d8	965	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	966	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	967	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
Kojto	90:cb3d968589d8	968	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
Kojto	90:cb3d968589d8	969	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
Kojto	90:cb3d968589d8	970	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	971	#endif /* STM32F301x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	972
Kojto	90:cb3d968589d8	973	#if defined(STM32F302x8)
Kojto	90:cb3d968589d8	974	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	975	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	976	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	977	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	978	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	979	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	980	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	981	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	982	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
Kojto	90:cb3d968589d8	983	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	984	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	985	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	986	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
Kojto	90:cb3d968589d8	987	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	988
Kojto	90:cb3d968589d8	989	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	990	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	991	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
Kojto	90:cb3d968589d8	992	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
Kojto	90:cb3d968589d8	993	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB \| \
Kojto	90:cb3d968589d8	994	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
Kojto	90:cb3d968589d8	995	RCC_PERIPHCLK_TIM17))
Kojto	90:cb3d968589d8	996	#endif /* STM32F302x8 */
Kojto	90:cb3d968589d8	997
Kojto	90:cb3d968589d8	998	#if defined(STM32F302xC)
Kojto	90:cb3d968589d8	999	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1000	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1001	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1002	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1003	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1004	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1005	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1006	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1007	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1008	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1009	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1010	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1011
Kojto	90:cb3d968589d8	1012	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1013	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	90:cb3d968589d8	1014	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	1015	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
Kojto	90:cb3d968589d8	1016	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
Kojto	90:cb3d968589d8	1017	RCC_PERIPHCLK_USB))
Kojto	90:cb3d968589d8	1018	#endif /* STM32F302xC */
Kojto	90:cb3d968589d8	1019
Kojto	90:cb3d968589d8	1020	#if defined(STM32F303xC)
Kojto	90:cb3d968589d8	1021	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1022	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1023	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1024	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1025	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1026	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1027	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1028	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1029	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1030	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1031	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1032	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1033	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1034	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1035
Kojto	90:cb3d968589d8	1036	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1037	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	90:cb3d968589d8	1038	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	1039	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
Kojto	90:cb3d968589d8	1040	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
Kojto	90:cb3d968589d8	1041	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
Kojto	90:cb3d968589d8	1042	RCC_PERIPHCLK_USB))
Kojto	90:cb3d968589d8	1043	#endif /* STM32F303xC */
Kojto	90:cb3d968589d8	1044
Kojto	90:cb3d968589d8	1045	#if defined(STM32F302xE)
Kojto	90:cb3d968589d8	1046	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1047	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1048	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1049	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1050	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1051	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1052	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1053	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1054	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1055	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1056	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1057	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1058	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1059	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1060	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1061	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1062	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1063	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	1064
Kojto	90:cb3d968589d8	1065	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1066	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	90:cb3d968589d8	1067	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	1068	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
Kojto	90:cb3d968589d8	1069	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
Kojto	90:cb3d968589d8	1070	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
Kojto	90:cb3d968589d8	1071	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
Kojto	90:cb3d968589d8	1072	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
Kojto	90:cb3d968589d8	1073	RCC_PERIPHCLK_TIM17))
Kojto	90:cb3d968589d8	1074	#endif /* STM32F302xE */
Kojto	90:cb3d968589d8	1075
Kojto	90:cb3d968589d8	1076	#if defined(STM32F303xE)
Kojto	90:cb3d968589d8	1077	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1078	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1079	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1080	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1081	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1082	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1083	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1084	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1085	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1086	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1087	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1088	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1089	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1090	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1091	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1092	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1093	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1094	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1095	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1096	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	1097	#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
Kojto	90:cb3d968589d8	1098
Kojto	90:cb3d968589d8	1099	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1100	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	90:cb3d968589d8	1101	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	1102	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
Kojto	90:cb3d968589d8	1103	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
Kojto	90:cb3d968589d8	1104	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
Kojto	90:cb3d968589d8	1105	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
Kojto	90:cb3d968589d8	1106	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
Kojto	90:cb3d968589d8	1107	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
Kojto	90:cb3d968589d8	1108	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_TIM20))
Kojto	90:cb3d968589d8	1109	#endif /* STM32F303xE */
Kojto	90:cb3d968589d8	1110
Kojto	90:cb3d968589d8	1111	#if defined(STM32F398xx)
Kojto	90:cb3d968589d8	1112	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1113	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1114	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1115	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1116	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1117	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1118	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1119	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1120	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1121	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1122	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1123	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1124	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1125	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
Kojto	90:cb3d968589d8	1126	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
Kojto	90:cb3d968589d8	1127	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
Kojto	90:cb3d968589d8	1128	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
Kojto	90:cb3d968589d8	1129	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
Kojto	90:cb3d968589d8	1130	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
Kojto	90:cb3d968589d8	1131	#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
Kojto	90:cb3d968589d8	1132
Kojto	90:cb3d968589d8	1133	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1134	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	90:cb3d968589d8	1135	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	1136	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
Kojto	90:cb3d968589d8	1137	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
Kojto	90:cb3d968589d8	1138	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
Kojto	90:cb3d968589d8	1139	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM2 \| \
Kojto	90:cb3d968589d8	1140	RCC_PERIPHCLK_TIM34 \| RCC_PERIPHCLK_TIM15 \| \
Kojto	90:cb3d968589d8	1141	RCC_PERIPHCLK_TIM16 \| RCC_PERIPHCLK_TIM17 \| \
Kojto	90:cb3d968589d8	1142	RCC_PERIPHCLK_TIM20))
Kojto	90:cb3d968589d8	1143	#endif /* STM32F398xx */
Kojto	90:cb3d968589d8	1144
Kojto	90:cb3d968589d8	1145	#if defined(STM32F358xx)
Kojto	90:cb3d968589d8	1146	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1147	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1148	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1149	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	1150	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	1151	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1152	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1153	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1154	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
Kojto	90:cb3d968589d8	1155	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
Kojto	90:cb3d968589d8	1156	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1157	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
Kojto	90:cb3d968589d8	1158	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1159
Kojto	90:cb3d968589d8	1160	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1161	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
Kojto	90:cb3d968589d8	1162	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	1163	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
Kojto	90:cb3d968589d8	1164	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
Kojto	90:cb3d968589d8	1165	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	1166	#endif /* STM32F358xx */
Kojto	90:cb3d968589d8	1167
Kojto	90:cb3d968589d8	1168	#if defined(STM32F303x8)
Kojto	90:cb3d968589d8	1169	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1170	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1171	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1172	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1173	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1174	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1175	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1176
Kojto	90:cb3d968589d8	1177	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1178	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
Kojto	90:cb3d968589d8	1179	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	1180	#endif /* STM32F303x8 */
Kojto	90:cb3d968589d8	1181
Kojto	90:cb3d968589d8	1182	#if defined(STM32F334x8)
Kojto	90:cb3d968589d8	1183	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1184	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1185	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1186	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1187	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1188	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1189	#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
Kojto	90:cb3d968589d8	1190	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1191
Kojto	90:cb3d968589d8	1192	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1193	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
Kojto	90:cb3d968589d8	1194	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_HRTIM1 \| \
Kojto	90:cb3d968589d8	1195	RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	1196	#endif /* STM32F334x8 */
Kojto	90:cb3d968589d8	1197
Kojto	90:cb3d968589d8	1198	#if defined(STM32F328xx)
Kojto	90:cb3d968589d8	1199	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1200	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1201	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1202	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1203	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1204	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
Kojto	90:cb3d968589d8	1205	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1206
Kojto	90:cb3d968589d8	1207	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1208	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
Kojto	90:cb3d968589d8	1209	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	1210	#endif /* STM32F328xx */
Kojto	90:cb3d968589d8	1211
Kojto	90:cb3d968589d8	1212	#if defined(STM32F373xC)
Kojto	90:cb3d968589d8	1213	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1214	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1215	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1216	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1217	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1218	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1219	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1220	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1221	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1222	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
Kojto	90:cb3d968589d8	1223
Kojto	90:cb3d968589d8	1224	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1225	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	1226	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
Kojto	90:cb3d968589d8	1227	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
Kojto	90:cb3d968589d8	1228	RCC_PERIPHCLK_USB))
Kojto	90:cb3d968589d8	1229	#endif /* STM32F373xC */
Kojto	90:cb3d968589d8	1230
Kojto	90:cb3d968589d8	1231	#if defined(STM32F378xx)
Kojto	90:cb3d968589d8	1232	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	1233	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	1234	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	1235	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	1236	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
Kojto	90:cb3d968589d8	1237	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
Kojto	90:cb3d968589d8	1238	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
Kojto	90:cb3d968589d8	1239	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
Kojto	90:cb3d968589d8	1240	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
Kojto	90:cb3d968589d8	1241
Kojto	90:cb3d968589d8	1242	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
Kojto	90:cb3d968589d8	1243	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
Kojto	90:cb3d968589d8	1244	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
Kojto	90:cb3d968589d8	1245	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
Kojto	90:cb3d968589d8	1246	#endif /* STM32F378xx */
Kojto	90:cb3d968589d8	1247	/**
Kojto	90:cb3d968589d8	1248	* @}
Kojto	90:cb3d968589d8	1249	*/
Kojto	90:cb3d968589d8	1250
Kojto	90:cb3d968589d8	1251	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	1252
Kojto	90:cb3d968589d8	1253	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	90:cb3d968589d8	1254	* @{
Kojto	90:cb3d968589d8	1255	*/
Kojto	90:cb3d968589d8	1256	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto	90:cb3d968589d8	1257	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	90:cb3d968589d8	1258	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	90:cb3d968589d8	1259	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	90:cb3d968589d8	1260
Kojto	90:cb3d968589d8	1261	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	90:cb3d968589d8	1262	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1263	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1264	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1265	/**
Kojto	90:cb3d968589d8	1266	* @}
Kojto	90:cb3d968589d8	1267	*/
Kojto	90:cb3d968589d8	1268
Kojto	90:cb3d968589d8	1269	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto	90:cb3d968589d8	1270	* @{
Kojto	90:cb3d968589d8	1271	*/
Kojto	90:cb3d968589d8	1272	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto	90:cb3d968589d8	1273	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto	90:cb3d968589d8	1274
Kojto	90:cb3d968589d8	1275	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	1276	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto	90:cb3d968589d8	1277	/**
Kojto	90:cb3d968589d8	1278	* @}
Kojto	90:cb3d968589d8	1279	*/
Kojto	90:cb3d968589d8	1280
Kojto	90:cb3d968589d8	1281	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
Kojto	90:cb3d968589d8	1282	* @{
Kojto	90:cb3d968589d8	1283	*/
Kojto	90:cb3d968589d8	1284	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
Kojto	90:cb3d968589d8	1285	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
Kojto	90:cb3d968589d8	1286
Kojto	90:cb3d968589d8	1287	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	1288	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
Kojto	90:cb3d968589d8	1289	/**
Kojto	90:cb3d968589d8	1290	* @}
Kojto	90:cb3d968589d8	1291	*/
Kojto	90:cb3d968589d8	1292
Kojto	90:cb3d968589d8	1293	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
Kojto	90:cb3d968589d8	1294	* @{
Kojto	90:cb3d968589d8	1295	*/
Kojto	90:cb3d968589d8	1296	#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
Kojto	90:cb3d968589d8	1297	#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
Kojto	90:cb3d968589d8	1298	#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
Kojto	90:cb3d968589d8	1299	#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
Kojto	90:cb3d968589d8	1300	#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
Kojto	90:cb3d968589d8	1301	#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
Kojto	90:cb3d968589d8	1302	#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
Kojto	90:cb3d968589d8	1303	#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
Kojto	90:cb3d968589d8	1304	#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
Kojto	90:cb3d968589d8	1305	#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
Kojto	90:cb3d968589d8	1306	#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
Kojto	90:cb3d968589d8	1307	#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
Kojto	90:cb3d968589d8	1308	#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
Kojto	90:cb3d968589d8	1309
Kojto	90:cb3d968589d8	1310	#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) \|\| \
Kojto	90:cb3d968589d8	1311	((ADCCLK) == RCC_ADC1PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) \|\| \
Kojto	90:cb3d968589d8	1312	((ADCCLK) == RCC_ADC1PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	1313	((ADCCLK) == RCC_ADC1PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) \|\| \
Kojto	90:cb3d968589d8	1314	((ADCCLK) == RCC_ADC1PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) \|\| \
Kojto	90:cb3d968589d8	1315	((ADCCLK) == RCC_ADC1PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) \|\| \
Kojto	90:cb3d968589d8	1316	((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
Kojto	90:cb3d968589d8	1317	/**
Kojto	90:cb3d968589d8	1318	* @}
Kojto	90:cb3d968589d8	1319	*/
Kojto	90:cb3d968589d8	1320
Kojto	90:cb3d968589d8	1321	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto	90:cb3d968589d8	1322	* @{
Kojto	90:cb3d968589d8	1323	*/
Kojto	90:cb3d968589d8	1324	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto	90:cb3d968589d8	1325	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto	90:cb3d968589d8	1326
Kojto	90:cb3d968589d8	1327	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1328	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto	90:cb3d968589d8	1329	/**
Kojto	90:cb3d968589d8	1330	* @}
Kojto	90:cb3d968589d8	1331	*/
Kojto	90:cb3d968589d8	1332
Kojto	90:cb3d968589d8	1333	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto	90:cb3d968589d8	1334	* @{
Kojto	90:cb3d968589d8	1335	*/
Kojto	90:cb3d968589d8	1336	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto	90:cb3d968589d8	1337	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto	90:cb3d968589d8	1338
Kojto	90:cb3d968589d8	1339	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1340	((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto	90:cb3d968589d8	1341	/**
Kojto	90:cb3d968589d8	1342	* @}
Kojto	90:cb3d968589d8	1343	*/
Kojto	90:cb3d968589d8	1344
Kojto	90:cb3d968589d8	1345	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
Kojto	90:cb3d968589d8	1346	* @{
Kojto	90:cb3d968589d8	1347	*/
Kojto	90:cb3d968589d8	1348	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
Kojto	90:cb3d968589d8	1349	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
Kojto	90:cb3d968589d8	1350
Kojto	90:cb3d968589d8	1351	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1352	((SOURCE) == RCC_TIM15CLK_PLLCLK))
Kojto	90:cb3d968589d8	1353	/**
Kojto	90:cb3d968589d8	1354	* @}
Kojto	90:cb3d968589d8	1355	*/
Kojto	90:cb3d968589d8	1356
Kojto	90:cb3d968589d8	1357	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
Kojto	90:cb3d968589d8	1358	* @{
Kojto	90:cb3d968589d8	1359	*/
Kojto	90:cb3d968589d8	1360	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
Kojto	90:cb3d968589d8	1361	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
Kojto	90:cb3d968589d8	1362
Kojto	90:cb3d968589d8	1363	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1364	((SOURCE) == RCC_TIM16CLK_PLLCLK))
Kojto	90:cb3d968589d8	1365	/**
Kojto	90:cb3d968589d8	1366	* @}
Kojto	90:cb3d968589d8	1367	*/
Kojto	90:cb3d968589d8	1368
Kojto	90:cb3d968589d8	1369	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
Kojto	90:cb3d968589d8	1370	* @{
Kojto	90:cb3d968589d8	1371	*/
Kojto	90:cb3d968589d8	1372	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
Kojto	90:cb3d968589d8	1373	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
Kojto	90:cb3d968589d8	1374
Kojto	90:cb3d968589d8	1375	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1376	((SOURCE) == RCC_TIM17CLK_PLLCLK))
Kojto	90:cb3d968589d8	1377	/**
Kojto	90:cb3d968589d8	1378	* @}
Kojto	90:cb3d968589d8	1379	*/
Kojto	90:cb3d968589d8	1380
Kojto	90:cb3d968589d8	1381	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	1382
Kojto	90:cb3d968589d8	1383	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	1384
Kojto	90:cb3d968589d8	1385	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	90:cb3d968589d8	1386	* @{
Kojto	90:cb3d968589d8	1387	*/
Kojto	90:cb3d968589d8	1388	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto	90:cb3d968589d8	1389	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	90:cb3d968589d8	1390	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	90:cb3d968589d8	1391	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	90:cb3d968589d8	1392
Kojto	90:cb3d968589d8	1393	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	90:cb3d968589d8	1394	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1395	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1396	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1397	/**
Kojto	90:cb3d968589d8	1398	* @}
Kojto	90:cb3d968589d8	1399	*/
Kojto	90:cb3d968589d8	1400
Kojto	90:cb3d968589d8	1401	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto	90:cb3d968589d8	1402	* @{
Kojto	90:cb3d968589d8	1403	*/
Kojto	90:cb3d968589d8	1404	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto	90:cb3d968589d8	1405	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto	90:cb3d968589d8	1406
Kojto	90:cb3d968589d8	1407	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	1408	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto	90:cb3d968589d8	1409	/**
Kojto	90:cb3d968589d8	1410	* @}
Kojto	90:cb3d968589d8	1411	*/
Kojto	90:cb3d968589d8	1412
Kojto	90:cb3d968589d8	1413	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto	90:cb3d968589d8	1414	* @{
Kojto	90:cb3d968589d8	1415	*/
Kojto	90:cb3d968589d8	1416
Kojto	90:cb3d968589d8	1417	/* ADC1 & ADC2 */
Kojto	90:cb3d968589d8	1418	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto	90:cb3d968589d8	1419	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto	90:cb3d968589d8	1420	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto	90:cb3d968589d8	1421	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto	90:cb3d968589d8	1422	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto	90:cb3d968589d8	1423	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto	90:cb3d968589d8	1424	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto	90:cb3d968589d8	1425	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto	90:cb3d968589d8	1426	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto	90:cb3d968589d8	1427	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto	90:cb3d968589d8	1428	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto	90:cb3d968589d8	1429	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto	90:cb3d968589d8	1430	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto	90:cb3d968589d8	1431
Kojto	90:cb3d968589d8	1432	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
Kojto	90:cb3d968589d8	1433	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
Kojto	90:cb3d968589d8	1434	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	1435	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
Kojto	90:cb3d968589d8	1436	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
Kojto	90:cb3d968589d8	1437	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
Kojto	90:cb3d968589d8	1438	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto	90:cb3d968589d8	1439	/**
Kojto	90:cb3d968589d8	1440	* @}
Kojto	90:cb3d968589d8	1441	*/
Kojto	90:cb3d968589d8	1442
Kojto	90:cb3d968589d8	1443	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto	90:cb3d968589d8	1444	* @{
Kojto	90:cb3d968589d8	1445	*/
Kojto	90:cb3d968589d8	1446	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto	90:cb3d968589d8	1447	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto	90:cb3d968589d8	1448
Kojto	90:cb3d968589d8	1449	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1450	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto	90:cb3d968589d8	1451	/**
Kojto	90:cb3d968589d8	1452	* @}
Kojto	90:cb3d968589d8	1453	*/
Kojto	90:cb3d968589d8	1454	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto	90:cb3d968589d8	1455	* @{
Kojto	90:cb3d968589d8	1456	*/
Kojto	90:cb3d968589d8	1457	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto	90:cb3d968589d8	1458	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto	90:cb3d968589d8	1459
Kojto	90:cb3d968589d8	1460	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1461	((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto	90:cb3d968589d8	1462	/**
Kojto	90:cb3d968589d8	1463	* @}
Kojto	90:cb3d968589d8	1464	*/
Kojto	90:cb3d968589d8	1465
Kojto	90:cb3d968589d8	1466	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
Kojto	90:cb3d968589d8	1467	* @{
Kojto	90:cb3d968589d8	1468	*/
Kojto	90:cb3d968589d8	1469	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
Kojto	90:cb3d968589d8	1470	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
Kojto	90:cb3d968589d8	1471	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
Kojto	90:cb3d968589d8	1472	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
Kojto	90:cb3d968589d8	1473
Kojto	90:cb3d968589d8	1474	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	1475	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1476	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1477	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1478	/**
Kojto	90:cb3d968589d8	1479	* @}
Kojto	90:cb3d968589d8	1480	*/
Kojto	90:cb3d968589d8	1481
Kojto	90:cb3d968589d8	1482	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
Kojto	90:cb3d968589d8	1483	* @{
Kojto	90:cb3d968589d8	1484	*/
Kojto	90:cb3d968589d8	1485	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
Kojto	90:cb3d968589d8	1486	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
Kojto	90:cb3d968589d8	1487	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
Kojto	90:cb3d968589d8	1488	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
Kojto	90:cb3d968589d8	1489
Kojto	90:cb3d968589d8	1490	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	1491	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1492	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1493	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1494	/**
Kojto	90:cb3d968589d8	1495	* @}
Kojto	90:cb3d968589d8	1496	*/
Kojto	90:cb3d968589d8	1497
Kojto	90:cb3d968589d8	1498	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	1499
Kojto	90:cb3d968589d8	1500	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	1501
Kojto	90:cb3d968589d8	1502	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	90:cb3d968589d8	1503	* @{
Kojto	90:cb3d968589d8	1504	*/
Kojto	90:cb3d968589d8	1505	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto	90:cb3d968589d8	1506	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	90:cb3d968589d8	1507	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	90:cb3d968589d8	1508	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	90:cb3d968589d8	1509
Kojto	90:cb3d968589d8	1510	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	90:cb3d968589d8	1511	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1512	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1513	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1514	/**
Kojto	90:cb3d968589d8	1515	* @}
Kojto	90:cb3d968589d8	1516	*/
Kojto	90:cb3d968589d8	1517
Kojto	90:cb3d968589d8	1518	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto	90:cb3d968589d8	1519	* @{
Kojto	90:cb3d968589d8	1520	*/
Kojto	90:cb3d968589d8	1521	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto	90:cb3d968589d8	1522	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto	90:cb3d968589d8	1523
Kojto	90:cb3d968589d8	1524	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	1525	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto	90:cb3d968589d8	1526	/**
Kojto	90:cb3d968589d8	1527	* @}
Kojto	90:cb3d968589d8	1528	*/
Kojto	90:cb3d968589d8	1529
Kojto	90:cb3d968589d8	1530	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
Kojto	90:cb3d968589d8	1531	* @{
Kojto	90:cb3d968589d8	1532	*/
Kojto	90:cb3d968589d8	1533	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
Kojto	90:cb3d968589d8	1534	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
Kojto	90:cb3d968589d8	1535
Kojto	90:cb3d968589d8	1536	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	1537	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
Kojto	90:cb3d968589d8	1538	/**
Kojto	90:cb3d968589d8	1539	* @}
Kojto	90:cb3d968589d8	1540	*/
Kojto	90:cb3d968589d8	1541
Kojto	90:cb3d968589d8	1542	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto	90:cb3d968589d8	1543	* @{
Kojto	90:cb3d968589d8	1544	*/
Kojto	90:cb3d968589d8	1545
Kojto	90:cb3d968589d8	1546	/* ADC1 & ADC2 */
Kojto	90:cb3d968589d8	1547	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto	90:cb3d968589d8	1548	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto	90:cb3d968589d8	1549	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto	90:cb3d968589d8	1550	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto	90:cb3d968589d8	1551	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto	90:cb3d968589d8	1552	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto	90:cb3d968589d8	1553	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto	90:cb3d968589d8	1554	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto	90:cb3d968589d8	1555	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto	90:cb3d968589d8	1556	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto	90:cb3d968589d8	1557	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto	90:cb3d968589d8	1558	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto	90:cb3d968589d8	1559	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto	90:cb3d968589d8	1560
Kojto	90:cb3d968589d8	1561	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
Kojto	90:cb3d968589d8	1562	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
Kojto	90:cb3d968589d8	1563	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	1564	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
Kojto	90:cb3d968589d8	1565	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
Kojto	90:cb3d968589d8	1566	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
Kojto	90:cb3d968589d8	1567	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto	90:cb3d968589d8	1568	/**
Kojto	90:cb3d968589d8	1569	* @}
Kojto	90:cb3d968589d8	1570	*/
Kojto	90:cb3d968589d8	1571
Kojto	90:cb3d968589d8	1572	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
Kojto	90:cb3d968589d8	1573	* @{
Kojto	90:cb3d968589d8	1574	*/
Kojto	90:cb3d968589d8	1575	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
Kojto	90:cb3d968589d8	1576	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
Kojto	90:cb3d968589d8	1577
Kojto	90:cb3d968589d8	1578	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1579	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
Kojto	90:cb3d968589d8	1580	/**
Kojto	90:cb3d968589d8	1581	* @}
Kojto	90:cb3d968589d8	1582	*/
Kojto	90:cb3d968589d8	1583
Kojto	90:cb3d968589d8	1584	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto	90:cb3d968589d8	1585	* @{
Kojto	90:cb3d968589d8	1586	*/
Kojto	90:cb3d968589d8	1587	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto	90:cb3d968589d8	1588	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto	90:cb3d968589d8	1589
Kojto	90:cb3d968589d8	1590	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1591	((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto	90:cb3d968589d8	1592	/**
Kojto	90:cb3d968589d8	1593	* @}
Kojto	90:cb3d968589d8	1594	*/
Kojto	90:cb3d968589d8	1595
Kojto	90:cb3d968589d8	1596	/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
Kojto	90:cb3d968589d8	1597	* @{
Kojto	90:cb3d968589d8	1598	*/
Kojto	90:cb3d968589d8	1599	#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
Kojto	90:cb3d968589d8	1600	#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
Kojto	90:cb3d968589d8	1601
Kojto	90:cb3d968589d8	1602	#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1603	((SOURCE) == RCC_TIM2CLK_PLLCLK))
Kojto	90:cb3d968589d8	1604	/**
Kojto	90:cb3d968589d8	1605	* @}
Kojto	90:cb3d968589d8	1606	*/
Kojto	90:cb3d968589d8	1607
Kojto	90:cb3d968589d8	1608	/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
Kojto	90:cb3d968589d8	1609	* @{
Kojto	90:cb3d968589d8	1610	*/
Kojto	90:cb3d968589d8	1611	#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
Kojto	90:cb3d968589d8	1612	#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
Kojto	90:cb3d968589d8	1613
Kojto	90:cb3d968589d8	1614	#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1615	((SOURCE) == RCC_TIM34CLK_PLLCLK))
Kojto	90:cb3d968589d8	1616	/**
Kojto	90:cb3d968589d8	1617	* @}
Kojto	90:cb3d968589d8	1618	*/
Kojto	90:cb3d968589d8	1619
Kojto	90:cb3d968589d8	1620	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
Kojto	90:cb3d968589d8	1621	* @{
Kojto	90:cb3d968589d8	1622	*/
Kojto	90:cb3d968589d8	1623	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
Kojto	90:cb3d968589d8	1624	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
Kojto	90:cb3d968589d8	1625
Kojto	90:cb3d968589d8	1626	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1627	((SOURCE) == RCC_TIM15CLK_PLLCLK))
Kojto	90:cb3d968589d8	1628	/**
Kojto	90:cb3d968589d8	1629	* @}
Kojto	90:cb3d968589d8	1630	*/
Kojto	90:cb3d968589d8	1631
Kojto	90:cb3d968589d8	1632	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
Kojto	90:cb3d968589d8	1633	* @{
Kojto	90:cb3d968589d8	1634	*/
Kojto	90:cb3d968589d8	1635	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
Kojto	90:cb3d968589d8	1636	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
Kojto	90:cb3d968589d8	1637
Kojto	90:cb3d968589d8	1638	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1639	((SOURCE) == RCC_TIM16CLK_PLLCLK))
Kojto	90:cb3d968589d8	1640	/**
Kojto	90:cb3d968589d8	1641	* @}
Kojto	90:cb3d968589d8	1642	*/
Kojto	90:cb3d968589d8	1643
Kojto	90:cb3d968589d8	1644	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
Kojto	90:cb3d968589d8	1645	* @{
Kojto	90:cb3d968589d8	1646	*/
Kojto	90:cb3d968589d8	1647	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
Kojto	90:cb3d968589d8	1648	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
Kojto	90:cb3d968589d8	1649
Kojto	90:cb3d968589d8	1650	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1651	((SOURCE) == RCC_TIM17CLK_PLLCLK))
Kojto	90:cb3d968589d8	1652	/**
Kojto	90:cb3d968589d8	1653	* @}
Kojto	90:cb3d968589d8	1654	*/
Kojto	90:cb3d968589d8	1655
Kojto	90:cb3d968589d8	1656	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
Kojto	90:cb3d968589d8	1657	* @{
Kojto	90:cb3d968589d8	1658	*/
Kojto	90:cb3d968589d8	1659	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
Kojto	90:cb3d968589d8	1660	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
Kojto	90:cb3d968589d8	1661	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
Kojto	90:cb3d968589d8	1662	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
Kojto	90:cb3d968589d8	1663
Kojto	90:cb3d968589d8	1664	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	1665	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1666	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1667	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1668	/**
Kojto	90:cb3d968589d8	1669	* @}
Kojto	90:cb3d968589d8	1670	*/
Kojto	90:cb3d968589d8	1671
Kojto	90:cb3d968589d8	1672	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
Kojto	90:cb3d968589d8	1673	* @{
Kojto	90:cb3d968589d8	1674	*/
Kojto	90:cb3d968589d8	1675	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
Kojto	90:cb3d968589d8	1676	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
Kojto	90:cb3d968589d8	1677	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
Kojto	90:cb3d968589d8	1678	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
Kojto	90:cb3d968589d8	1679
Kojto	90:cb3d968589d8	1680	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	1681	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1682	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1683	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1684	/**
Kojto	90:cb3d968589d8	1685	* @}
Kojto	90:cb3d968589d8	1686	*/
Kojto	90:cb3d968589d8	1687
Kojto	90:cb3d968589d8	1688	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	1689
Kojto	90:cb3d968589d8	1690	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	1691	/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
Kojto	90:cb3d968589d8	1692	* @{
Kojto	90:cb3d968589d8	1693	*/
Kojto	90:cb3d968589d8	1694	#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
Kojto	90:cb3d968589d8	1695	#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
Kojto	90:cb3d968589d8	1696
Kojto	90:cb3d968589d8	1697	#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1698	((SOURCE) == RCC_TIM20CLK_PLLCLK))
Kojto	90:cb3d968589d8	1699	/**
Kojto	90:cb3d968589d8	1700	* @}
Kojto	90:cb3d968589d8	1701	*/
Kojto	90:cb3d968589d8	1702	#endif /* STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	1703
Kojto	90:cb3d968589d8	1704	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	1705	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	1706
Kojto	90:cb3d968589d8	1707	/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
Kojto	90:cb3d968589d8	1708	* @{
Kojto	90:cb3d968589d8	1709	*/
Kojto	90:cb3d968589d8	1710
Kojto	90:cb3d968589d8	1711	/* ADC3 & ADC4 */
Kojto	90:cb3d968589d8	1712	#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
Kojto	90:cb3d968589d8	1713	#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
Kojto	90:cb3d968589d8	1714	#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
Kojto	90:cb3d968589d8	1715	#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
Kojto	90:cb3d968589d8	1716	#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
Kojto	90:cb3d968589d8	1717	#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
Kojto	90:cb3d968589d8	1718	#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
Kojto	90:cb3d968589d8	1719	#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
Kojto	90:cb3d968589d8	1720	#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
Kojto	90:cb3d968589d8	1721	#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
Kojto	90:cb3d968589d8	1722	#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
Kojto	90:cb3d968589d8	1723	#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
Kojto	90:cb3d968589d8	1724	#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
Kojto	90:cb3d968589d8	1725
Kojto	90:cb3d968589d8	1726	#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) \|\| \
Kojto	90:cb3d968589d8	1727	((ADCCLK) == RCC_ADC34PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) \|\| \
Kojto	90:cb3d968589d8	1728	((ADCCLK) == RCC_ADC34PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	1729	((ADCCLK) == RCC_ADC34PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) \|\| \
Kojto	90:cb3d968589d8	1730	((ADCCLK) == RCC_ADC34PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) \|\| \
Kojto	90:cb3d968589d8	1731	((ADCCLK) == RCC_ADC34PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) \|\| \
Kojto	90:cb3d968589d8	1732	((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
Kojto	90:cb3d968589d8	1733	/**
Kojto	90:cb3d968589d8	1734	* @}
Kojto	90:cb3d968589d8	1735	*/
Kojto	90:cb3d968589d8	1736
Kojto	90:cb3d968589d8	1737	/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
Kojto	90:cb3d968589d8	1738	* @{
Kojto	90:cb3d968589d8	1739	*/
Kojto	90:cb3d968589d8	1740	#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
Kojto	90:cb3d968589d8	1741	#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
Kojto	90:cb3d968589d8	1742
Kojto	90:cb3d968589d8	1743	#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1744	((SOURCE) == RCC_TIM8CLK_PLLCLK))
Kojto	90:cb3d968589d8	1745	/**
Kojto	90:cb3d968589d8	1746	* @}
Kojto	90:cb3d968589d8	1747	*/
Kojto	90:cb3d968589d8	1748
Kojto	90:cb3d968589d8	1749	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
Kojto	90:cb3d968589d8	1750
Kojto	90:cb3d968589d8	1751	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	90:cb3d968589d8	1752
Kojto	90:cb3d968589d8	1753	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	90:cb3d968589d8	1754	* @{
Kojto	90:cb3d968589d8	1755	*/
Kojto	90:cb3d968589d8	1756	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
Kojto	90:cb3d968589d8	1757	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	90:cb3d968589d8	1758	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	90:cb3d968589d8	1759	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	90:cb3d968589d8	1760
Kojto	90:cb3d968589d8	1761	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	1762	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1763	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1764	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1765	/**
Kojto	90:cb3d968589d8	1766	* @}
Kojto	90:cb3d968589d8	1767	*/
Kojto	90:cb3d968589d8	1768
Kojto	90:cb3d968589d8	1769	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
Kojto	90:cb3d968589d8	1770	* @{
Kojto	90:cb3d968589d8	1771	*/
Kojto	90:cb3d968589d8	1772	/* ADC1 & ADC2 */
Kojto	90:cb3d968589d8	1773	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
Kojto	90:cb3d968589d8	1774	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
Kojto	90:cb3d968589d8	1775	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
Kojto	90:cb3d968589d8	1776	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
Kojto	90:cb3d968589d8	1777	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
Kojto	90:cb3d968589d8	1778	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
Kojto	90:cb3d968589d8	1779	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
Kojto	90:cb3d968589d8	1780	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
Kojto	90:cb3d968589d8	1781	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
Kojto	90:cb3d968589d8	1782	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
Kojto	90:cb3d968589d8	1783	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
Kojto	90:cb3d968589d8	1784	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
Kojto	90:cb3d968589d8	1785	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
Kojto	90:cb3d968589d8	1786
Kojto	90:cb3d968589d8	1787	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
Kojto	90:cb3d968589d8	1788	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
Kojto	90:cb3d968589d8	1789	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	1790	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
Kojto	90:cb3d968589d8	1791	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
Kojto	90:cb3d968589d8	1792	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
Kojto	90:cb3d968589d8	1793	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
Kojto	90:cb3d968589d8	1794	/**
Kojto	90:cb3d968589d8	1795	* @}
Kojto	90:cb3d968589d8	1796	*/
Kojto	90:cb3d968589d8	1797
Kojto	90:cb3d968589d8	1798	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
Kojto	90:cb3d968589d8	1799	* @{
Kojto	90:cb3d968589d8	1800	*/
Kojto	90:cb3d968589d8	1801	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
Kojto	90:cb3d968589d8	1802	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
Kojto	90:cb3d968589d8	1803
Kojto	90:cb3d968589d8	1804	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1805	((SOURCE) == RCC_TIM1CLK_PLLCLK))
Kojto	90:cb3d968589d8	1806	/**
Kojto	90:cb3d968589d8	1807	* @}
Kojto	90:cb3d968589d8	1808	*/
Kojto	90:cb3d968589d8	1809
Kojto	90:cb3d968589d8	1810	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	90:cb3d968589d8	1811
Kojto	90:cb3d968589d8	1812	#if defined(STM32F334x8)
Kojto	90:cb3d968589d8	1813
Kojto	90:cb3d968589d8	1814	/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
Kojto	90:cb3d968589d8	1815	* @{
Kojto	90:cb3d968589d8	1816	*/
Kojto	90:cb3d968589d8	1817	#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
Kojto	90:cb3d968589d8	1818	#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
Kojto	90:cb3d968589d8	1819
Kojto	90:cb3d968589d8	1820	#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) \|\| \
Kojto	90:cb3d968589d8	1821	((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
Kojto	90:cb3d968589d8	1822	/**
Kojto	90:cb3d968589d8	1823	* @}
Kojto	90:cb3d968589d8	1824	*/
Kojto	90:cb3d968589d8	1825
Kojto	90:cb3d968589d8	1826	#endif /* STM32F334x8 */
Kojto	90:cb3d968589d8	1827
Kojto	90:cb3d968589d8	1828	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	1829
Kojto	90:cb3d968589d8	1830	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
Kojto	90:cb3d968589d8	1831	* @{
Kojto	90:cb3d968589d8	1832	*/
Kojto	90:cb3d968589d8	1833	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
Kojto	90:cb3d968589d8	1834	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	90:cb3d968589d8	1835	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	90:cb3d968589d8	1836	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	90:cb3d968589d8	1837
Kojto	90:cb3d968589d8	1838	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	90:cb3d968589d8	1839	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	1840	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	1841	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	1842	/**
Kojto	90:cb3d968589d8	1843	* @}
Kojto	90:cb3d968589d8	1844	*/
Kojto	90:cb3d968589d8	1845
Kojto	90:cb3d968589d8	1846	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
Kojto	90:cb3d968589d8	1847	* @{
Kojto	90:cb3d968589d8	1848	*/
Kojto	90:cb3d968589d8	1849	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
Kojto	90:cb3d968589d8	1850	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
Kojto	90:cb3d968589d8	1851
Kojto	90:cb3d968589d8	1852	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	1853	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
Kojto	90:cb3d968589d8	1854	/**
Kojto	90:cb3d968589d8	1855	* @}
Kojto	90:cb3d968589d8	1856	*/
Kojto	90:cb3d968589d8	1857
Kojto	90:cb3d968589d8	1858	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
Kojto	90:cb3d968589d8	1859	* @{
Kojto	90:cb3d968589d8	1860	*/
Kojto	90:cb3d968589d8	1861
Kojto	90:cb3d968589d8	1862	/* ADC1 */
Kojto	90:cb3d968589d8	1863	#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
Kojto	90:cb3d968589d8	1864	#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
Kojto	90:cb3d968589d8	1865	#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
Kojto	90:cb3d968589d8	1866	#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
Kojto	90:cb3d968589d8	1867
Kojto	90:cb3d968589d8	1868	#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV4) \|\| \
Kojto	90:cb3d968589d8	1869	((ADCCLK) == RCC_ADC1PCLK2_DIV6) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
Kojto	90:cb3d968589d8	1870	/**
Kojto	90:cb3d968589d8	1871	* @}
Kojto	90:cb3d968589d8	1872	*/
Kojto	90:cb3d968589d8	1873
Kojto	90:cb3d968589d8	1874	/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
Kojto	90:cb3d968589d8	1875	* @{
Kojto	90:cb3d968589d8	1876	*/
Kojto	90:cb3d968589d8	1877	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
Kojto	90:cb3d968589d8	1878	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
Kojto	90:cb3d968589d8	1879
Kojto	90:cb3d968589d8	1880	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	1881	((SOURCE) == RCC_CECCLKSOURCE_LSE))
Kojto	90:cb3d968589d8	1882	/**
Kojto	90:cb3d968589d8	1883	* @}
Kojto	90:cb3d968589d8	1884	*/
Kojto	90:cb3d968589d8	1885
Kojto	90:cb3d968589d8	1886	/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
Kojto	90:cb3d968589d8	1887	* @{
Kojto	90:cb3d968589d8	1888	*/
Kojto	90:cb3d968589d8	1889	#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
Kojto	90:cb3d968589d8	1890	#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
Kojto	90:cb3d968589d8	1891	#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
Kojto	90:cb3d968589d8	1892	#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
Kojto	90:cb3d968589d8	1893	#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
Kojto	90:cb3d968589d8	1894	#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
Kojto	90:cb3d968589d8	1895	#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
Kojto	90:cb3d968589d8	1896	#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
Kojto	90:cb3d968589d8	1897	#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
Kojto	90:cb3d968589d8	1898	#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
Kojto	90:cb3d968589d8	1899	#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
Kojto	90:cb3d968589d8	1900	#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
Kojto	90:cb3d968589d8	1901	#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
Kojto	90:cb3d968589d8	1902	#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
Kojto	90:cb3d968589d8	1903	#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
Kojto	90:cb3d968589d8	1904	#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
Kojto	90:cb3d968589d8	1905	#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
Kojto	90:cb3d968589d8	1906
Kojto	90:cb3d968589d8	1907	#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	1908	((DIV) == RCC_SDADCSYSCLK_DIV4) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV6) \|\| \
Kojto	90:cb3d968589d8	1909	((DIV) == RCC_SDADCSYSCLK_DIV8) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV10) \|\| \
Kojto	90:cb3d968589d8	1910	((DIV) == RCC_SDADCSYSCLK_DIV12) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV14) \|\| \
Kojto	90:cb3d968589d8	1911	((DIV) == RCC_SDADCSYSCLK_DIV16) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV20) \|\| \
Kojto	90:cb3d968589d8	1912	((DIV) == RCC_SDADCSYSCLK_DIV24) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV28) \|\| \
Kojto	90:cb3d968589d8	1913	((DIV) == RCC_SDADCSYSCLK_DIV32) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV36) \|\| \
Kojto	90:cb3d968589d8	1914	((DIV) == RCC_SDADCSYSCLK_DIV40) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV44) \|\| \
Kojto	90:cb3d968589d8	1915	((DIV) == RCC_SDADCSYSCLK_DIV48))
Kojto	90:cb3d968589d8	1916	/**
Kojto	90:cb3d968589d8	1917	* @}
Kojto	90:cb3d968589d8	1918	*/
Kojto	90:cb3d968589d8	1919
Kojto	90:cb3d968589d8	1920	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	1921
Kojto	90:cb3d968589d8	1922	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
Kojto	90:cb3d968589d8	1923	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
Kojto	90:cb3d968589d8	1924	defined(STM32F302x8) \|\| \
Kojto	90:cb3d968589d8	1925	defined(STM32F373xC)
Kojto	90:cb3d968589d8	1926	/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
Kojto	90:cb3d968589d8	1927	* @{
Kojto	90:cb3d968589d8	1928	*/
Kojto	90:cb3d968589d8	1929	#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
Kojto	90:cb3d968589d8	1930	#define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
Kojto	90:cb3d968589d8	1931
Kojto	90:cb3d968589d8	1932	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) \|\| \
Kojto	90:cb3d968589d8	1933	((SOURCE) == RCC_USBPLLCLK_DIV1_5))
Kojto	90:cb3d968589d8	1934	/**
Kojto	90:cb3d968589d8	1935	* @}
Kojto	90:cb3d968589d8	1936	*/
Kojto	90:cb3d968589d8	1937
Kojto	90:cb3d968589d8	1938	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
Kojto	90:cb3d968589d8	1939	/* STM32F302xC \|\| STM32F303xC \|\| */
Kojto	90:cb3d968589d8	1940	/* STM32F302x8 \|\| */
Kojto	90:cb3d968589d8	1941	/* STM32F373xC */
Kojto	90:cb3d968589d8	1942
Kojto	90:cb3d968589d8	1943	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	1944	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	1945	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
Kojto	90:cb3d968589d8	1946	* @{
Kojto	90:cb3d968589d8	1947	*/
Kojto	90:cb3d968589d8	1948	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	1949
Kojto	90:cb3d968589d8	1950	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
Kojto	90:cb3d968589d8	1951	/**
Kojto	90:cb3d968589d8	1952	* @}
Kojto	90:cb3d968589d8	1953	*/
Kojto	90:cb3d968589d8	1954	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	1955	/* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	1956
Kojto	90:cb3d968589d8	1957	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	1958	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	1959	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	1960
Kojto	90:cb3d968589d8	1961	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
Kojto	90:cb3d968589d8	1962	* @{
Kojto	90:cb3d968589d8	1963	*/
Kojto	90:cb3d968589d8	1964	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	1965	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
Kojto	90:cb3d968589d8	1966	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
Kojto	90:cb3d968589d8	1967	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
Kojto	90:cb3d968589d8	1968	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
Kojto	90:cb3d968589d8	1969	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
Kojto	90:cb3d968589d8	1970	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
Kojto	90:cb3d968589d8	1971	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
Kojto	90:cb3d968589d8	1972
Kojto	90:cb3d968589d8	1973	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
Kojto	90:cb3d968589d8	1974	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
Kojto	90:cb3d968589d8	1975	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
Kojto	90:cb3d968589d8	1976	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
Kojto	90:cb3d968589d8	1977	/**
Kojto	90:cb3d968589d8	1978	* @}
Kojto	90:cb3d968589d8	1979	*/
Kojto	90:cb3d968589d8	1980
Kojto	90:cb3d968589d8	1981	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	1982	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	1983	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	1984
Kojto	90:cb3d968589d8	1985	/**
Kojto	90:cb3d968589d8	1986	* @}
Kojto	90:cb3d968589d8	1987	*/
Kojto	90:cb3d968589d8	1988
Kojto	90:cb3d968589d8	1989	/* Exported macro ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	1990	/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
Kojto	90:cb3d968589d8	1991	* @{
Kojto	90:cb3d968589d8	1992	*/
Kojto	90:cb3d968589d8	1993
Kojto	90:cb3d968589d8	1994	/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
Kojto	90:cb3d968589d8	1995	* @{
Kojto	90:cb3d968589d8	1996	*/
Kojto	90:cb3d968589d8	1997	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	1998	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
Kojto	90:cb3d968589d8	1999	* @note This macro must be used only when the PLL is disabled.
Kojto	90:cb3d968589d8	2000	*
Kojto	90:cb3d968589d8	2001	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	90:cb3d968589d8	2002	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2003	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	90:cb3d968589d8	2004	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	90:cb3d968589d8	2005	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
Kojto	90:cb3d968589d8	2006	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto	90:cb3d968589d8	2007	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
Kojto	90:cb3d968589d8	2008	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto	90:cb3d968589d8	2009	*
Kojto	90:cb3d968589d8	2010	*/
Kojto	90:cb3d968589d8	2011	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
Kojto	90:cb3d968589d8	2012	do { \
Kojto	90:cb3d968589d8	2013	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
Kojto	90:cb3d968589d8	2014	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__))); \
Kojto	90:cb3d968589d8	2015	} while(0)
Kojto	90:cb3d968589d8	2016	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2017
Kojto	90:cb3d968589d8	2018	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	2019	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	2020	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
Kojto	90:cb3d968589d8	2021	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2022	/** @brief Macro to configure the PLL clock source and multiplication factor.
Kojto	90:cb3d968589d8	2023	* @note This macro must be used only when the PLL is disabled.
Kojto	90:cb3d968589d8	2024	*
Kojto	90:cb3d968589d8	2025	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	90:cb3d968589d8	2026	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2027	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	90:cb3d968589d8	2028	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	90:cb3d968589d8	2029	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
Kojto	90:cb3d968589d8	2030	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto	90:cb3d968589d8	2031	*
Kojto	90:cb3d968589d8	2032	*/
Kojto	90:cb3d968589d8	2033	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
Kojto	90:cb3d968589d8	2034	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__)))
Kojto	90:cb3d968589d8	2035	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	2036	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	2037	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2038	/* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2039	/**
Kojto	90:cb3d968589d8	2040	* @}
Kojto	90:cb3d968589d8	2041	*/
Kojto	90:cb3d968589d8	2042
Kojto	90:cb3d968589d8	2043	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	2044	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	2045	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
Kojto	90:cb3d968589d8	2046	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2047	/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
Kojto	90:cb3d968589d8	2048	* @{
Kojto	90:cb3d968589d8	2049	*/
Kojto	90:cb3d968589d8	2050
Kojto	90:cb3d968589d8	2051	/**
Kojto	90:cb3d968589d8	2052	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
Kojto	90:cb3d968589d8	2053	* @note Predivision factor can not be changed if PLL is used as system clock
Kojto	90:cb3d968589d8	2054	* In this case, you have to select another source of the system clock, disable the PLL and
Kojto	90:cb3d968589d8	2055	* then change the HSE predivision factor.
Kojto	90:cb3d968589d8	2056	* @param __HSEPredivValue__: specifies the division value applied to HSE.
Kojto	90:cb3d968589d8	2057	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
Kojto	90:cb3d968589d8	2058	*/
Kojto	90:cb3d968589d8	2059	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
Kojto	90:cb3d968589d8	2060	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
Kojto	90:cb3d968589d8	2061	/**
Kojto	90:cb3d968589d8	2062	* @}
Kojto	90:cb3d968589d8	2063	*/
Kojto	90:cb3d968589d8	2064	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	2065	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	2066	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2067	/* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2068
Kojto	90:cb3d968589d8	2069	/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
Kojto	90:cb3d968589d8	2070	* @brief Enable or disable the AHB peripheral clock.
Kojto	90:cb3d968589d8	2071	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	2072	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	2073	* using it.
Kojto	90:cb3d968589d8	2074	* @{
Kojto	90:cb3d968589d8	2075	*/
Kojto	90:cb3d968589d8	2076	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	2077	#define __ADC1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC1EN))
Kojto	90:cb3d968589d8	2078
Kojto	90:cb3d968589d8	2079	#define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
Kojto	90:cb3d968589d8	2080	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2081
Kojto	90:cb3d968589d8	2082	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2083	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2084	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
Kojto	90:cb3d968589d8	2085	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
Kojto	90:cb3d968589d8	2086	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
Kojto	90:cb3d968589d8	2087	/* Aliases for STM32 F3 compatibility */
Kojto	90:cb3d968589d8	2088	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto	90:cb3d968589d8	2089	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto	90:cb3d968589d8	2090
Kojto	90:cb3d968589d8	2091	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto	90:cb3d968589d8	2092	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto	90:cb3d968589d8	2093	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
Kojto	90:cb3d968589d8	2094	/* Aliases for STM32 F3 compatibility */
Kojto	90:cb3d968589d8	2095	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto	90:cb3d968589d8	2096	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto	90:cb3d968589d8	2097	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2098	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2099
Kojto	90:cb3d968589d8	2100	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2101	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2102	#define __ADC34_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC34EN))
Kojto	90:cb3d968589d8	2103
Kojto	90:cb3d968589d8	2104	#define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
Kojto	90:cb3d968589d8	2105	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2106	/* STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2107
Kojto	90:cb3d968589d8	2108	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	90:cb3d968589d8	2109	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
Kojto	90:cb3d968589d8	2110	/* Aliases for STM32 F3 compatibility */
Kojto	90:cb3d968589d8	2111	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto	90:cb3d968589d8	2112	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
Kojto	90:cb3d968589d8	2113
Kojto	90:cb3d968589d8	2114	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
Kojto	90:cb3d968589d8	2115	/* Aliases for STM32 F3 compatibility */
Kojto	90:cb3d968589d8	2116	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto	90:cb3d968589d8	2117	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
Kojto	90:cb3d968589d8	2118	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	90:cb3d968589d8	2119
Kojto	90:cb3d968589d8	2120	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2121	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
Kojto	90:cb3d968589d8	2122	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
Kojto	90:cb3d968589d8	2123
Kojto	90:cb3d968589d8	2124	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
Kojto	90:cb3d968589d8	2125	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
Kojto	90:cb3d968589d8	2126	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2127
Kojto	90:cb3d968589d8	2128	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	2129	#define __FMC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FMCEN))
Kojto	90:cb3d968589d8	2130	#define __GPIOG_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOGEN))
Kojto	90:cb3d968589d8	2131	#define __GPIOH_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOHEN))
Kojto	90:cb3d968589d8	2132
Kojto	90:cb3d968589d8	2133	#define __FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
Kojto	90:cb3d968589d8	2134	#define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
Kojto	90:cb3d968589d8	2135	#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
Kojto	90:cb3d968589d8	2136	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2137	/**
Kojto	90:cb3d968589d8	2138	* @}
Kojto	90:cb3d968589d8	2139	*/
Kojto	90:cb3d968589d8	2140
Kojto	90:cb3d968589d8	2141	/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
Kojto	90:cb3d968589d8	2142	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	90:cb3d968589d8	2143	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	2144	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	2145	* using it.
Kojto	90:cb3d968589d8	2146	* @{
Kojto	90:cb3d968589d8	2147	*/
Kojto	90:cb3d968589d8	2148	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	2149	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	2150	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
Kojto	90:cb3d968589d8	2151	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	2152	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
Kojto	90:cb3d968589d8	2153
Kojto	90:cb3d968589d8	2154	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	2155	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	90:cb3d968589d8	2156	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	2157	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	90:cb3d968589d8	2158	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2159
Kojto	90:cb3d968589d8	2160	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2161	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2162	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	2163	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
Kojto	90:cb3d968589d8	2164	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	2165	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
Kojto	90:cb3d968589d8	2166	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
Kojto	90:cb3d968589d8	2167	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
Kojto	90:cb3d968589d8	2168	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	2169
Kojto	90:cb3d968589d8	2170	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	2171	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	90:cb3d968589d8	2172	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	2173	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	90:cb3d968589d8	2174	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
Kojto	90:cb3d968589d8	2175	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
Kojto	90:cb3d968589d8	2176	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	2177	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2178	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2179
Kojto	90:cb3d968589d8	2180	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	90:cb3d968589d8	2181	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	2182	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
Kojto	90:cb3d968589d8	2183
Kojto	90:cb3d968589d8	2184	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	2185	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
Kojto	90:cb3d968589d8	2186	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	90:cb3d968589d8	2187
Kojto	90:cb3d968589d8	2188	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2189	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	2190	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
Kojto	90:cb3d968589d8	2191	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
Kojto	90:cb3d968589d8	2192	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
Kojto	90:cb3d968589d8	2193	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
Kojto	90:cb3d968589d8	2194	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
Kojto	90:cb3d968589d8	2195	#define __TIM18_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM18EN))
Kojto	90:cb3d968589d8	2196	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	2197	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
Kojto	90:cb3d968589d8	2198	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	2199	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
Kojto	90:cb3d968589d8	2200	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
Kojto	90:cb3d968589d8	2201
Kojto	90:cb3d968589d8	2202	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	2203	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	90:cb3d968589d8	2204	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
Kojto	90:cb3d968589d8	2205	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
Kojto	90:cb3d968589d8	2206	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
Kojto	90:cb3d968589d8	2207	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	90:cb3d968589d8	2208	#define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
Kojto	90:cb3d968589d8	2209	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	2210	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
Kojto	90:cb3d968589d8	2211	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	2212	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
Kojto	90:cb3d968589d8	2213	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
Kojto	90:cb3d968589d8	2214	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2215
Kojto	90:cb3d968589d8	2216	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2217	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	2218	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	2219	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2220	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
Kojto	90:cb3d968589d8	2221
Kojto	90:cb3d968589d8	2222	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	90:cb3d968589d8	2223	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2224	/* STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	2225	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	2226	/* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2227
Kojto	90:cb3d968589d8	2228	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
Kojto	90:cb3d968589d8	2229	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
Kojto	90:cb3d968589d8	2230	defined(STM32F302x8) \|\| \
Kojto	90:cb3d968589d8	2231	defined(STM32F373xC)
Kojto	90:cb3d968589d8	2232	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
Kojto	90:cb3d968589d8	2233
Kojto	90:cb3d968589d8	2234	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto	90:cb3d968589d8	2235	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
Kojto	90:cb3d968589d8	2236	/* STM32F302xC \|\| STM32F303xC \|\| */
Kojto	90:cb3d968589d8	2237	/* STM32F302x8 \|\| */
Kojto	90:cb3d968589d8	2238	/* STM32F373xC */
Kojto	90:cb3d968589d8	2239
Kojto	90:cb3d968589d8	2240	#if !defined(STM32F301x8)
Kojto	90:cb3d968589d8	2241	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
Kojto	90:cb3d968589d8	2242
Kojto	90:cb3d968589d8	2243	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
Kojto	90:cb3d968589d8	2244	#endif /* STM32F301x8*/
Kojto	90:cb3d968589d8	2245
Kojto	90:cb3d968589d8	2246	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	2247	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
Kojto	90:cb3d968589d8	2248
Kojto	90:cb3d968589d8	2249	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
Kojto	90:cb3d968589d8	2250	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2251	/**
Kojto	90:cb3d968589d8	2252	* @}
Kojto	90:cb3d968589d8	2253	*/
Kojto	90:cb3d968589d8	2254
Kojto	90:cb3d968589d8	2255	/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
Kojto	90:cb3d968589d8	2256	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	90:cb3d968589d8	2257	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	2258	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	2259	* using it.
Kojto	90:cb3d968589d8	2260	* @{
Kojto	90:cb3d968589d8	2261	*/
Kojto	90:cb3d968589d8	2262	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2263	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2264	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	2265
Kojto	90:cb3d968589d8	2266	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	2267	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2268	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2269
Kojto	90:cb3d968589d8	2270	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2271	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2272	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
Kojto	90:cb3d968589d8	2273
Kojto	90:cb3d968589d8	2274	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
Kojto	90:cb3d968589d8	2275	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2276	/* STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2277
Kojto	90:cb3d968589d8	2278	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	90:cb3d968589d8	2279	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	2280
Kojto	90:cb3d968589d8	2281	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	2282	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	90:cb3d968589d8	2283
Kojto	90:cb3d968589d8	2284	#if defined(STM32F334x8)
Kojto	90:cb3d968589d8	2285	#define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_HRTIM1EN))
Kojto	90:cb3d968589d8	2286
Kojto	90:cb3d968589d8	2287	#define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
Kojto	90:cb3d968589d8	2288	#endif /* STM32F334x8 */
Kojto	90:cb3d968589d8	2289
Kojto	90:cb3d968589d8	2290	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2291	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
Kojto	90:cb3d968589d8	2292	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	2293	#define __TIM19_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM19EN))
Kojto	90:cb3d968589d8	2294	#define __SDADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC1EN))
Kojto	90:cb3d968589d8	2295	#define __SDADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC2EN))
Kojto	90:cb3d968589d8	2296	#define __SDADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC3EN))
Kojto	90:cb3d968589d8	2297
Kojto	90:cb3d968589d8	2298	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	90:cb3d968589d8	2299	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	2300	#define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
Kojto	90:cb3d968589d8	2301	#define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
Kojto	90:cb3d968589d8	2302	#define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
Kojto	90:cb3d968589d8	2303	#define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
Kojto	90:cb3d968589d8	2304	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2305
Kojto	90:cb3d968589d8	2306	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2307	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	2308	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	2309	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	2310	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
Kojto	90:cb3d968589d8	2311
Kojto	90:cb3d968589d8	2312	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto	90:cb3d968589d8	2313	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2314	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	2315	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	2316	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2317
Kojto	90:cb3d968589d8	2318	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	2319	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
Kojto	90:cb3d968589d8	2320
Kojto	90:cb3d968589d8	2321	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
Kojto	90:cb3d968589d8	2322	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2323
Kojto	90:cb3d968589d8	2324	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	2325	#define __TIM20_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM20EN))
Kojto	90:cb3d968589d8	2326
Kojto	90:cb3d968589d8	2327	#define __TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
Kojto	90:cb3d968589d8	2328	#endif /* STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2329
Kojto	90:cb3d968589d8	2330	/**
Kojto	90:cb3d968589d8	2331	* @}
Kojto	90:cb3d968589d8	2332	*/
Kojto	90:cb3d968589d8	2333
Kojto	90:cb3d968589d8	2334	/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
Kojto	90:cb3d968589d8	2335	* @brief Force or release AHB peripheral reset.
Kojto	90:cb3d968589d8	2336	* @{
Kojto	90:cb3d968589d8	2337	*/
Kojto	90:cb3d968589d8	2338	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	2339	#define __ADC1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC1RST))
Kojto	90:cb3d968589d8	2340
Kojto	90:cb3d968589d8	2341	#define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
Kojto	90:cb3d968589d8	2342	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2343
Kojto	90:cb3d968589d8	2344	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2345	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2346	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
Kojto	90:cb3d968589d8	2347	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
Kojto	90:cb3d968589d8	2348	/* Aliases for STM32 F3 compatibility */
Kojto	90:cb3d968589d8	2349	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto	90:cb3d968589d8	2350	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto	90:cb3d968589d8	2351
Kojto	90:cb3d968589d8	2352	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto	90:cb3d968589d8	2353	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
Kojto	90:cb3d968589d8	2354	/* Aliases for STM32 F3 compatibility */
Kojto	90:cb3d968589d8	2355	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto	90:cb3d968589d8	2356	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto	90:cb3d968589d8	2357	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2358	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2359
Kojto	90:cb3d968589d8	2360	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2361	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2362	#define __ADC34_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC34RST))
Kojto	90:cb3d968589d8	2363
Kojto	90:cb3d968589d8	2364	#define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
Kojto	90:cb3d968589d8	2365	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2366	/* STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2367
Kojto	90:cb3d968589d8	2368	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	90:cb3d968589d8	2369	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
Kojto	90:cb3d968589d8	2370	/* Aliases for STM32 F3 compatibility */
Kojto	90:cb3d968589d8	2371	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto	90:cb3d968589d8	2372	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
Kojto	90:cb3d968589d8	2373
Kojto	90:cb3d968589d8	2374	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
Kojto	90:cb3d968589d8	2375	/* Aliases for STM32 F3 compatibility */
Kojto	90:cb3d968589d8	2376	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto	90:cb3d968589d8	2377	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
Kojto	90:cb3d968589d8	2378	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	90:cb3d968589d8	2379
Kojto	90:cb3d968589d8	2380	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2381	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
Kojto	90:cb3d968589d8	2382
Kojto	90:cb3d968589d8	2383	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
Kojto	90:cb3d968589d8	2384	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2385
Kojto	90:cb3d968589d8	2386	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	2387	#define __FMC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FMCRST))
Kojto	90:cb3d968589d8	2388	#define __GPIOG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOGRST))
Kojto	90:cb3d968589d8	2389	#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
Kojto	90:cb3d968589d8	2390
Kojto	90:cb3d968589d8	2391	#define __FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
Kojto	90:cb3d968589d8	2392	#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
Kojto	90:cb3d968589d8	2393	#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
Kojto	90:cb3d968589d8	2394	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2395	/**
Kojto	90:cb3d968589d8	2396	* @}
Kojto	90:cb3d968589d8	2397	*/
Kojto	90:cb3d968589d8	2398
Kojto	90:cb3d968589d8	2399	/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
Kojto	90:cb3d968589d8	2400	* @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	2401	* @{
Kojto	90:cb3d968589d8	2402	*/
Kojto	90:cb3d968589d8	2403	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	2404	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	2405	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	90:cb3d968589d8	2406	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	2407	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	90:cb3d968589d8	2408
Kojto	90:cb3d968589d8	2409	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	2410	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	90:cb3d968589d8	2411	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	2412	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	90:cb3d968589d8	2413	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2414
Kojto	90:cb3d968589d8	2415	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2416	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2417	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	2418	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	90:cb3d968589d8	2419	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	2420	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	90:cb3d968589d8	2421	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
Kojto	90:cb3d968589d8	2422	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
Kojto	90:cb3d968589d8	2423	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	2424
Kojto	90:cb3d968589d8	2425	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	2426	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	90:cb3d968589d8	2427	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	2428	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	90:cb3d968589d8	2429	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
Kojto	90:cb3d968589d8	2430	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
Kojto	90:cb3d968589d8	2431	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	2432	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2433	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2434
Kojto	90:cb3d968589d8	2435	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	90:cb3d968589d8	2436	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	2437	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
Kojto	90:cb3d968589d8	2438
Kojto	90:cb3d968589d8	2439	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	2440	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
Kojto	90:cb3d968589d8	2441	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	90:cb3d968589d8	2442
Kojto	90:cb3d968589d8	2443	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2444	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	2445	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	90:cb3d968589d8	2446	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
Kojto	90:cb3d968589d8	2447	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
Kojto	90:cb3d968589d8	2448	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
Kojto	90:cb3d968589d8	2449	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	90:cb3d968589d8	2450	#define __TIM18_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM18RST))
Kojto	90:cb3d968589d8	2451	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	2452	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
Kojto	90:cb3d968589d8	2453	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	2454	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
Kojto	90:cb3d968589d8	2455	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
Kojto	90:cb3d968589d8	2456
Kojto	90:cb3d968589d8	2457	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	2458	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	90:cb3d968589d8	2459	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
Kojto	90:cb3d968589d8	2460	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
Kojto	90:cb3d968589d8	2461	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
Kojto	90:cb3d968589d8	2462	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	90:cb3d968589d8	2463	#define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
Kojto	90:cb3d968589d8	2464	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	2465	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
Kojto	90:cb3d968589d8	2466	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	2467	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
Kojto	90:cb3d968589d8	2468	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
Kojto	90:cb3d968589d8	2469	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2470
Kojto	90:cb3d968589d8	2471	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2472	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	2473	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	2474	defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2475	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	90:cb3d968589d8	2476
Kojto	90:cb3d968589d8	2477	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	90:cb3d968589d8	2478	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2479	/* STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	2480	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	2481	/* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2482
Kojto	90:cb3d968589d8	2483	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
Kojto	90:cb3d968589d8	2484	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
Kojto	90:cb3d968589d8	2485	defined(STM32F302x8) \|\| \
Kojto	90:cb3d968589d8	2486	defined(STM32F373xC)
Kojto	90:cb3d968589d8	2487	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
Kojto	90:cb3d968589d8	2488
Kojto	90:cb3d968589d8	2489	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto	90:cb3d968589d8	2490	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
Kojto	90:cb3d968589d8	2491	/* STM32F302xC \|\| STM32F303xC \|\| */
Kojto	90:cb3d968589d8	2492	/* STM32F302x8 \|\| */
Kojto	90:cb3d968589d8	2493	/* STM32F373xC */
Kojto	90:cb3d968589d8	2494
Kojto	90:cb3d968589d8	2495	#if !defined(STM32F301x8)
Kojto	90:cb3d968589d8	2496	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
Kojto	90:cb3d968589d8	2497
Kojto	90:cb3d968589d8	2498	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
Kojto	90:cb3d968589d8	2499	#endif /* STM32F301x8*/
Kojto	90:cb3d968589d8	2500
Kojto	90:cb3d968589d8	2501	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	2502	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	90:cb3d968589d8	2503
Kojto	90:cb3d968589d8	2504	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
Kojto	90:cb3d968589d8	2505	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2506	/**
Kojto	90:cb3d968589d8	2507	* @}
Kojto	90:cb3d968589d8	2508	*/
Kojto	90:cb3d968589d8	2509
Kojto	90:cb3d968589d8	2510	/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
Kojto	90:cb3d968589d8	2511	* @brief Force or release APB2 peripheral reset.
Kojto	90:cb3d968589d8	2512	* @{
Kojto	90:cb3d968589d8	2513	*/
Kojto	90:cb3d968589d8	2514	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2515	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2516	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	2517
Kojto	90:cb3d968589d8	2518	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	2519	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2520	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2521
Kojto	90:cb3d968589d8	2522	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2523	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2524	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
Kojto	90:cb3d968589d8	2525
Kojto	90:cb3d968589d8	2526	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
Kojto	90:cb3d968589d8	2527	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2528	/* STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2529
Kojto	90:cb3d968589d8	2530	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	90:cb3d968589d8	2531	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	2532
Kojto	90:cb3d968589d8	2533	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	2534	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	90:cb3d968589d8	2535
Kojto	90:cb3d968589d8	2536	#if defined(STM32F334x8)
Kojto	90:cb3d968589d8	2537	#define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_HRTIM1RST))
Kojto	90:cb3d968589d8	2538
Kojto	90:cb3d968589d8	2539	#define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
Kojto	90:cb3d968589d8	2540	#endif /* STM32F334x8 */
Kojto	90:cb3d968589d8	2541
Kojto	90:cb3d968589d8	2542	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	2543	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
Kojto	90:cb3d968589d8	2544	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	2545	#define __TIM19_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM19RST))
Kojto	90:cb3d968589d8	2546	#define __SDADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC1RST))
Kojto	90:cb3d968589d8	2547	#define __SDADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC2RST))
Kojto	90:cb3d968589d8	2548	#define __SDADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC3RST))
Kojto	90:cb3d968589d8	2549
Kojto	90:cb3d968589d8	2550	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto	90:cb3d968589d8	2551	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	2552	#define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
Kojto	90:cb3d968589d8	2553	#define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
Kojto	90:cb3d968589d8	2554	#define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
Kojto	90:cb3d968589d8	2555	#define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
Kojto	90:cb3d968589d8	2556	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	2557
Kojto	90:cb3d968589d8	2558	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2559	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
Kojto	90:cb3d968589d8	2560	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	2561	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	2562	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
Kojto	90:cb3d968589d8	2563
Kojto	90:cb3d968589d8	2564	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto	90:cb3d968589d8	2565	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2566	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
Kojto	90:cb3d968589d8	2567	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	2568	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2569
Kojto	90:cb3d968589d8	2570	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	2571	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
Kojto	90:cb3d968589d8	2572
Kojto	90:cb3d968589d8	2573	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
Kojto	90:cb3d968589d8	2574	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2575
Kojto	90:cb3d968589d8	2576	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	2577	#define __TIM20_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM20RST))
Kojto	90:cb3d968589d8	2578
Kojto	90:cb3d968589d8	2579	#define __TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
Kojto	90:cb3d968589d8	2580	#endif /* STM32F303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	2581
Kojto	90:cb3d968589d8	2582	/**
Kojto	90:cb3d968589d8	2583	* @}
Kojto	90:cb3d968589d8	2584	*/
Kojto	90:cb3d968589d8	2585
Kojto	90:cb3d968589d8	2586	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	2587	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto	90:cb3d968589d8	2588	* @{
Kojto	90:cb3d968589d8	2589	*/
Kojto	90:cb3d968589d8	2590
Kojto	90:cb3d968589d8	2591	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto	90:cb3d968589d8	2592	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto	90:cb3d968589d8	2593	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2594	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	90:cb3d968589d8	2595	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	90:cb3d968589d8	2596	*/
Kojto	90:cb3d968589d8	2597	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto	90:cb3d968589d8	2598	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto	90:cb3d968589d8	2599
Kojto	90:cb3d968589d8	2600	/** @brief Macro to get the I2C2 clock source.
Kojto	90:cb3d968589d8	2601	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2602	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	90:cb3d968589d8	2603	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	90:cb3d968589d8	2604	*/
Kojto	90:cb3d968589d8	2605	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto	90:cb3d968589d8	2606
Kojto	90:cb3d968589d8	2607	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto	90:cb3d968589d8	2608	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
Kojto	90:cb3d968589d8	2609	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2610	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	90:cb3d968589d8	2611	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	90:cb3d968589d8	2612	*/
Kojto	90:cb3d968589d8	2613	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
Kojto	90:cb3d968589d8	2614	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
Kojto	90:cb3d968589d8	2615
Kojto	90:cb3d968589d8	2616	/** @brief Macro to get the I2C3 clock source.
Kojto	90:cb3d968589d8	2617	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2618	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	90:cb3d968589d8	2619	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	90:cb3d968589d8	2620	*/
Kojto	90:cb3d968589d8	2621	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
Kojto	90:cb3d968589d8	2622
Kojto	90:cb3d968589d8	2623	/**
Kojto	90:cb3d968589d8	2624	* @}
Kojto	90:cb3d968589d8	2625	*/
Kojto	90:cb3d968589d8	2626
Kojto	90:cb3d968589d8	2627	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	90:cb3d968589d8	2628	* @{
Kojto	90:cb3d968589d8	2629	*/
Kojto	90:cb3d968589d8	2630	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto	90:cb3d968589d8	2631	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto	90:cb3d968589d8	2632	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2633	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	90:cb3d968589d8	2634	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	90:cb3d968589d8	2635	*/
Kojto	90:cb3d968589d8	2636	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto	90:cb3d968589d8	2637	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto	90:cb3d968589d8	2638
Kojto	90:cb3d968589d8	2639	/** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto	90:cb3d968589d8	2640	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2641	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2642	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	90:cb3d968589d8	2643	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	90:cb3d968589d8	2644	*/
Kojto	90:cb3d968589d8	2645	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto	90:cb3d968589d8	2646
Kojto	90:cb3d968589d8	2647	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
Kojto	90:cb3d968589d8	2648	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
Kojto	90:cb3d968589d8	2649	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2650	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
Kojto	90:cb3d968589d8	2651	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
Kojto	90:cb3d968589d8	2652	*/
Kojto	90:cb3d968589d8	2653	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
Kojto	90:cb3d968589d8	2654	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
Kojto	90:cb3d968589d8	2655
Kojto	90:cb3d968589d8	2656	/** @brief Macro to get the TIM15 clock (TIM15CLK).
Kojto	90:cb3d968589d8	2657	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2658	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2659	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
Kojto	90:cb3d968589d8	2660	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
Kojto	90:cb3d968589d8	2661	*/
Kojto	90:cb3d968589d8	2662	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
Kojto	90:cb3d968589d8	2663
Kojto	90:cb3d968589d8	2664	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
Kojto	90:cb3d968589d8	2665	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
Kojto	90:cb3d968589d8	2666	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2667	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
Kojto	90:cb3d968589d8	2668	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
Kojto	90:cb3d968589d8	2669	*/
Kojto	90:cb3d968589d8	2670	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
Kojto	90:cb3d968589d8	2671	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
Kojto	90:cb3d968589d8	2672
Kojto	90:cb3d968589d8	2673	/** @brief Macro to get the TIM16 clock (TIM16CLK).
Kojto	90:cb3d968589d8	2674	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2675	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2676	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
Kojto	90:cb3d968589d8	2677	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
Kojto	90:cb3d968589d8	2678	*/
Kojto	90:cb3d968589d8	2679	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
Kojto	90:cb3d968589d8	2680
Kojto	90:cb3d968589d8	2681	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
Kojto	90:cb3d968589d8	2682	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
Kojto	90:cb3d968589d8	2683	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2684	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
Kojto	90:cb3d968589d8	2685	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
Kojto	90:cb3d968589d8	2686	*/
Kojto	90:cb3d968589d8	2687	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
Kojto	90:cb3d968589d8	2688	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
Kojto	90:cb3d968589d8	2689
Kojto	90:cb3d968589d8	2690	/** @brief Macro to get the TIM17 clock (TIM17CLK).
Kojto	90:cb3d968589d8	2691	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2692	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2693	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
Kojto	90:cb3d968589d8	2694	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
Kojto	90:cb3d968589d8	2695	*/
Kojto	90:cb3d968589d8	2696	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
Kojto	90:cb3d968589d8	2697
Kojto	90:cb3d968589d8	2698	/**
Kojto	90:cb3d968589d8	2699	* @}
Kojto	90:cb3d968589d8	2700	*/
Kojto	90:cb3d968589d8	2701
Kojto	90:cb3d968589d8	2702	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
Kojto	90:cb3d968589d8	2703	* @{
Kojto	90:cb3d968589d8	2704	*/
Kojto	90:cb3d968589d8	2705	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	90:cb3d968589d8	2706	* @note This function must be called before enabling the I2S APB clock.
Kojto	90:cb3d968589d8	2707	* @param __I2SCLKSource__: specifies the I2S clock source.
Kojto	90:cb3d968589d8	2708	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2709	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto	90:cb3d968589d8	2710	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	90:cb3d968589d8	2711	* used as I2S clock source
Kojto	90:cb3d968589d8	2712	*/
Kojto	90:cb3d968589d8	2713	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
Kojto	90:cb3d968589d8	2714	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
Kojto	90:cb3d968589d8	2715
Kojto	90:cb3d968589d8	2716	/** @brief Macro to get the I2S clock source (I2SCLK).
Kojto	90:cb3d968589d8	2717	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2718	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto	90:cb3d968589d8	2719	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	90:cb3d968589d8	2720	* used as I2S clock source
Kojto	90:cb3d968589d8	2721	*/
Kojto	90:cb3d968589d8	2722	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
Kojto	90:cb3d968589d8	2723	/**
Kojto	90:cb3d968589d8	2724	* @}
Kojto	90:cb3d968589d8	2725	*/
Kojto	90:cb3d968589d8	2726
Kojto	90:cb3d968589d8	2727	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	90:cb3d968589d8	2728	* @{
Kojto	90:cb3d968589d8	2729	*/
Kojto	90:cb3d968589d8	2730
Kojto	90:cb3d968589d8	2731	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
Kojto	90:cb3d968589d8	2732	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
Kojto	90:cb3d968589d8	2733	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2734	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
Kojto	90:cb3d968589d8	2735	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
Kojto	90:cb3d968589d8	2736	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
Kojto	90:cb3d968589d8	2737	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
Kojto	90:cb3d968589d8	2738	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
Kojto	90:cb3d968589d8	2739	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
Kojto	90:cb3d968589d8	2740	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
Kojto	90:cb3d968589d8	2741	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
Kojto	90:cb3d968589d8	2742	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
Kojto	90:cb3d968589d8	2743	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
Kojto	90:cb3d968589d8	2744	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
Kojto	90:cb3d968589d8	2745	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
Kojto	90:cb3d968589d8	2746	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
Kojto	90:cb3d968589d8	2747	*/
Kojto	90:cb3d968589d8	2748	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
Kojto	90:cb3d968589d8	2749	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
Kojto	90:cb3d968589d8	2750
Kojto	90:cb3d968589d8	2751	/** @brief Macro to get the ADC1 clock
Kojto	90:cb3d968589d8	2752	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2753	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
Kojto	90:cb3d968589d8	2754	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
Kojto	90:cb3d968589d8	2755	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
Kojto	90:cb3d968589d8	2756	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
Kojto	90:cb3d968589d8	2757	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
Kojto	90:cb3d968589d8	2758	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
Kojto	90:cb3d968589d8	2759	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
Kojto	90:cb3d968589d8	2760	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
Kojto	90:cb3d968589d8	2761	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
Kojto	90:cb3d968589d8	2762	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
Kojto	90:cb3d968589d8	2763	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
Kojto	90:cb3d968589d8	2764	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
Kojto	90:cb3d968589d8	2765	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
Kojto	90:cb3d968589d8	2766	*/
Kojto	90:cb3d968589d8	2767	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
Kojto	90:cb3d968589d8	2768	/**
Kojto	90:cb3d968589d8	2769	* @}
Kojto	90:cb3d968589d8	2770	*/
Kojto	90:cb3d968589d8	2771
Kojto	90:cb3d968589d8	2772	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	2773
Kojto	90:cb3d968589d8	2774	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2775	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2776	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto	90:cb3d968589d8	2777	* @{
Kojto	90:cb3d968589d8	2778	*/
Kojto	90:cb3d968589d8	2779
Kojto	90:cb3d968589d8	2780	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto	90:cb3d968589d8	2781	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto	90:cb3d968589d8	2782	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2783	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	90:cb3d968589d8	2784	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	90:cb3d968589d8	2785	*/
Kojto	90:cb3d968589d8	2786	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto	90:cb3d968589d8	2787	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto	90:cb3d968589d8	2788
Kojto	90:cb3d968589d8	2789	/** @brief Macro to get the I2C2 clock source.
Kojto	90:cb3d968589d8	2790	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2791	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	90:cb3d968589d8	2792	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	90:cb3d968589d8	2793	*/
Kojto	90:cb3d968589d8	2794	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto	90:cb3d968589d8	2795	/**
Kojto	90:cb3d968589d8	2796	* @}
Kojto	90:cb3d968589d8	2797	*/
Kojto	90:cb3d968589d8	2798
Kojto	90:cb3d968589d8	2799	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	90:cb3d968589d8	2800	* @{
Kojto	90:cb3d968589d8	2801	*/
Kojto	90:cb3d968589d8	2802
Kojto	90:cb3d968589d8	2803	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
Kojto	90:cb3d968589d8	2804	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
Kojto	90:cb3d968589d8	2805	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2806	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto	90:cb3d968589d8	2807	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2808	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2809	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2810	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2811	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2812	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2813	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2814	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2815	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2816	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2817	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2818	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2819	*/
Kojto	90:cb3d968589d8	2820	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
Kojto	90:cb3d968589d8	2821	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
Kojto	90:cb3d968589d8	2822
Kojto	90:cb3d968589d8	2823	/** @brief Macro to get the ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2824	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2825	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto	90:cb3d968589d8	2826	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2827	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2828	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2829	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2830	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2831	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2832	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2833	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2834	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2835	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2836	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2837	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	2838	*/
Kojto	90:cb3d968589d8	2839	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
Kojto	90:cb3d968589d8	2840	/**
Kojto	90:cb3d968589d8	2841	* @}
Kojto	90:cb3d968589d8	2842	*/
Kojto	90:cb3d968589d8	2843
Kojto	90:cb3d968589d8	2844	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	90:cb3d968589d8	2845	* @{
Kojto	90:cb3d968589d8	2846	*/
Kojto	90:cb3d968589d8	2847
Kojto	90:cb3d968589d8	2848	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto	90:cb3d968589d8	2849	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto	90:cb3d968589d8	2850	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2851	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	90:cb3d968589d8	2852	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	90:cb3d968589d8	2853	*/
Kojto	90:cb3d968589d8	2854	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto	90:cb3d968589d8	2855	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto	90:cb3d968589d8	2856
Kojto	90:cb3d968589d8	2857	/** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto	90:cb3d968589d8	2858	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2859	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2860	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	90:cb3d968589d8	2861	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	90:cb3d968589d8	2862	*/
Kojto	90:cb3d968589d8	2863	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto	90:cb3d968589d8	2864	/**
Kojto	90:cb3d968589d8	2865	* @}
Kojto	90:cb3d968589d8	2866	*/
Kojto	90:cb3d968589d8	2867
Kojto	90:cb3d968589d8	2868	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
Kojto	90:cb3d968589d8	2869	* @{
Kojto	90:cb3d968589d8	2870	*/
Kojto	90:cb3d968589d8	2871
Kojto	90:cb3d968589d8	2872	/** @brief Macro to configure the I2S clock source (I2SCLK).
Kojto	90:cb3d968589d8	2873	* @note This function must be called before enabling the I2S APB clock.
Kojto	90:cb3d968589d8	2874	* @param __I2SCLKSource__: specifies the I2S clock source.
Kojto	90:cb3d968589d8	2875	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2876	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto	90:cb3d968589d8	2877	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	90:cb3d968589d8	2878	* used as I2S clock source
Kojto	90:cb3d968589d8	2879	*/
Kojto	90:cb3d968589d8	2880	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
Kojto	90:cb3d968589d8	2881	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
Kojto	90:cb3d968589d8	2882
Kojto	90:cb3d968589d8	2883	/** @brief Macro to get the I2S clock source (I2SCLK).
Kojto	90:cb3d968589d8	2884	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2885	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
Kojto	90:cb3d968589d8	2886	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
Kojto	90:cb3d968589d8	2887	* used as I2S clock source
Kojto	90:cb3d968589d8	2888	*/
Kojto	90:cb3d968589d8	2889	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
Kojto	90:cb3d968589d8	2890	/**
Kojto	90:cb3d968589d8	2891	* @}
Kojto	90:cb3d968589d8	2892	*/
Kojto	90:cb3d968589d8	2893
Kojto	90:cb3d968589d8	2894	/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
Kojto	90:cb3d968589d8	2895	* @{
Kojto	90:cb3d968589d8	2896	*/
Kojto	90:cb3d968589d8	2897
Kojto	90:cb3d968589d8	2898	/** @brief Macro to configure the UART4 clock (UART4CLK).
Kojto	90:cb3d968589d8	2899	* @param __UART4CLKSource__: specifies the UART4 clock source.
Kojto	90:cb3d968589d8	2900	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2901	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto	90:cb3d968589d8	2902	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto	90:cb3d968589d8	2903	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto	90:cb3d968589d8	2904	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto	90:cb3d968589d8	2905	*/
Kojto	90:cb3d968589d8	2906	#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
Kojto	90:cb3d968589d8	2907	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
Kojto	90:cb3d968589d8	2908
Kojto	90:cb3d968589d8	2909	/** @brief Macro to get the UART4 clock source.
Kojto	90:cb3d968589d8	2910	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2911	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
Kojto	90:cb3d968589d8	2912	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
Kojto	90:cb3d968589d8	2913	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
Kojto	90:cb3d968589d8	2914	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
Kojto	90:cb3d968589d8	2915	*/
Kojto	90:cb3d968589d8	2916	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
Kojto	90:cb3d968589d8	2917
Kojto	90:cb3d968589d8	2918	/** @brief Macro to configure the UART5 clock (UART5CLK).
Kojto	90:cb3d968589d8	2919	* @param __UART5CLKSource__: specifies the UART5 clock source.
Kojto	90:cb3d968589d8	2920	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2921	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto	90:cb3d968589d8	2922	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto	90:cb3d968589d8	2923	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto	90:cb3d968589d8	2924	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto	90:cb3d968589d8	2925	*/
Kojto	90:cb3d968589d8	2926	#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
Kojto	90:cb3d968589d8	2927	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
Kojto	90:cb3d968589d8	2928
Kojto	90:cb3d968589d8	2929	/** @brief Macro to get the UART5 clock source.
Kojto	90:cb3d968589d8	2930	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2931	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
Kojto	90:cb3d968589d8	2932	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
Kojto	90:cb3d968589d8	2933	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
Kojto	90:cb3d968589d8	2934	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
Kojto	90:cb3d968589d8	2935	*/
Kojto	90:cb3d968589d8	2936	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
Kojto	90:cb3d968589d8	2937	/**
Kojto	90:cb3d968589d8	2938	* @}
Kojto	90:cb3d968589d8	2939	*/
Kojto	90:cb3d968589d8	2940	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	2941	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	2942
Kojto	90:cb3d968589d8	2943	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	2944	defined(STM32F303xC) \|\| defined(STM32F358xx)
Kojto	90:cb3d968589d8	2945	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	90:cb3d968589d8	2946	* @{
Kojto	90:cb3d968589d8	2947	*/
Kojto	90:cb3d968589d8	2948
Kojto	90:cb3d968589d8	2949	/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
Kojto	90:cb3d968589d8	2950	* @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
Kojto	90:cb3d968589d8	2951	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2952	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
Kojto	90:cb3d968589d8	2953	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2954	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2955	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2956	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2957	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2958	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2959	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2960	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2961	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2962	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2963	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2964	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2965	*/
Kojto	90:cb3d968589d8	2966	#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
Kojto	90:cb3d968589d8	2967	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
Kojto	90:cb3d968589d8	2968
Kojto	90:cb3d968589d8	2969	/** @brief Macro to get the ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2970	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	2971	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
Kojto	90:cb3d968589d8	2972	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2973	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2974	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2975	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2976	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2977	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2978	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2979	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2980	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2981	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2982	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2983	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
Kojto	90:cb3d968589d8	2984	*/
Kojto	90:cb3d968589d8	2985	#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
Kojto	90:cb3d968589d8	2986	/**
Kojto	90:cb3d968589d8	2987	* @}
Kojto	90:cb3d968589d8	2988	*/
Kojto	90:cb3d968589d8	2989
Kojto	90:cb3d968589d8	2990	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	90:cb3d968589d8	2991	* @{
Kojto	90:cb3d968589d8	2992	*/
Kojto	90:cb3d968589d8	2993
Kojto	90:cb3d968589d8	2994	/** @brief Macro to configure the TIM8 clock (TIM8CLK).
Kojto	90:cb3d968589d8	2995	* @param __TIM8CLKSource__: specifies the TIM8 clock source.
Kojto	90:cb3d968589d8	2996	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	2997	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
Kojto	90:cb3d968589d8	2998	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
Kojto	90:cb3d968589d8	2999	*/
Kojto	90:cb3d968589d8	3000	#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
Kojto	90:cb3d968589d8	3001	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
Kojto	90:cb3d968589d8	3002
Kojto	90:cb3d968589d8	3003	/** @brief Macro to get the TIM8 clock (TIM8CLK).
Kojto	90:cb3d968589d8	3004	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3005	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3006	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
Kojto	90:cb3d968589d8	3007	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
Kojto	90:cb3d968589d8	3008	*/
Kojto	90:cb3d968589d8	3009	#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
Kojto	90:cb3d968589d8	3010
Kojto	90:cb3d968589d8	3011	/**
Kojto	90:cb3d968589d8	3012	* @}
Kojto	90:cb3d968589d8	3013	*/
Kojto	90:cb3d968589d8	3014	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	3015	/* STM32F303xC \|\| STM32F358xx */
Kojto	90:cb3d968589d8	3016
Kojto	90:cb3d968589d8	3017	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
Kojto	90:cb3d968589d8	3018	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	90:cb3d968589d8	3019	* @{
Kojto	90:cb3d968589d8	3020	*/
Kojto	90:cb3d968589d8	3021
Kojto	90:cb3d968589d8	3022	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
Kojto	90:cb3d968589d8	3023	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
Kojto	90:cb3d968589d8	3024	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3025	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto	90:cb3d968589d8	3026	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3027	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3028	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3029	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3030	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3031	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3032	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3033	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3034	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3035	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3036	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3037	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3038	*/
Kojto	90:cb3d968589d8	3039	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
Kojto	90:cb3d968589d8	3040	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
Kojto	90:cb3d968589d8	3041
Kojto	90:cb3d968589d8	3042	/** @brief Macro to get the ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3043	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3044	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
Kojto	90:cb3d968589d8	3045	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3046	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3047	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3048	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3049	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3050	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3051	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3052	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3053	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3054	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3055	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3056	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
Kojto	90:cb3d968589d8	3057	*/
Kojto	90:cb3d968589d8	3058	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
Kojto	90:cb3d968589d8	3059	/**
Kojto	90:cb3d968589d8	3060	* @}
Kojto	90:cb3d968589d8	3061	*/
Kojto	90:cb3d968589d8	3062
Kojto	90:cb3d968589d8	3063	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	90:cb3d968589d8	3064	* @{
Kojto	90:cb3d968589d8	3065	*/
Kojto	90:cb3d968589d8	3066	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
Kojto	90:cb3d968589d8	3067	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
Kojto	90:cb3d968589d8	3068	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3069	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	90:cb3d968589d8	3070	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	90:cb3d968589d8	3071	*/
Kojto	90:cb3d968589d8	3072	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
Kojto	90:cb3d968589d8	3073	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
Kojto	90:cb3d968589d8	3074
Kojto	90:cb3d968589d8	3075	/** @brief Macro to get the TIM1 clock (TIM1CLK).
Kojto	90:cb3d968589d8	3076	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3077	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3078	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
Kojto	90:cb3d968589d8	3079	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
Kojto	90:cb3d968589d8	3080	*/
Kojto	90:cb3d968589d8	3081	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
Kojto	90:cb3d968589d8	3082	/**
Kojto	90:cb3d968589d8	3083	* @}
Kojto	90:cb3d968589d8	3084	*/
Kojto	90:cb3d968589d8	3085	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
Kojto	90:cb3d968589d8	3086
Kojto	90:cb3d968589d8	3087	#if defined(STM32F334x8)
Kojto	90:cb3d968589d8	3088	/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
Kojto	90:cb3d968589d8	3089	* @{
Kojto	90:cb3d968589d8	3090	*/
Kojto	90:cb3d968589d8	3091	/** @brief Macro to configure the HRTIM1 clock.
Kojto	90:cb3d968589d8	3092	* @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
Kojto	90:cb3d968589d8	3093	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3094	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
Kojto	90:cb3d968589d8	3095	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
Kojto	90:cb3d968589d8	3096	*/
Kojto	90:cb3d968589d8	3097	#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
Kojto	90:cb3d968589d8	3098	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
Kojto	90:cb3d968589d8	3099
Kojto	90:cb3d968589d8	3100	/** @brief Macro to get the HRTIM1 clock source.
Kojto	90:cb3d968589d8	3101	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3102	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
Kojto	90:cb3d968589d8	3103	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
Kojto	90:cb3d968589d8	3104	*/
Kojto	90:cb3d968589d8	3105	#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
Kojto	90:cb3d968589d8	3106	/**
Kojto	90:cb3d968589d8	3107	* @}
Kojto	90:cb3d968589d8	3108	*/
Kojto	90:cb3d968589d8	3109	#endif /* STM32F334x8 */
Kojto	90:cb3d968589d8	3110
Kojto	90:cb3d968589d8	3111	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
Kojto	90:cb3d968589d8	3112	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto	90:cb3d968589d8	3113	* @{
Kojto	90:cb3d968589d8	3114	*/
Kojto	90:cb3d968589d8	3115	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
Kojto	90:cb3d968589d8	3116	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
Kojto	90:cb3d968589d8	3117	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3118	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	90:cb3d968589d8	3119	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	90:cb3d968589d8	3120	*/
Kojto	90:cb3d968589d8	3121	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
Kojto	90:cb3d968589d8	3122	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
Kojto	90:cb3d968589d8	3123
Kojto	90:cb3d968589d8	3124	/** @brief Macro to get the I2C2 clock source.
Kojto	90:cb3d968589d8	3125	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3126	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
Kojto	90:cb3d968589d8	3127	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
Kojto	90:cb3d968589d8	3128	*/
Kojto	90:cb3d968589d8	3129	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
Kojto	90:cb3d968589d8	3130	/**
Kojto	90:cb3d968589d8	3131	* @}
Kojto	90:cb3d968589d8	3132	*/
Kojto	90:cb3d968589d8	3133
Kojto	90:cb3d968589d8	3134	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
Kojto	90:cb3d968589d8	3135	* @{
Kojto	90:cb3d968589d8	3136	*/
Kojto	90:cb3d968589d8	3137	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
Kojto	90:cb3d968589d8	3138	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
Kojto	90:cb3d968589d8	3139	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3140	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
Kojto	90:cb3d968589d8	3141	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
Kojto	90:cb3d968589d8	3142	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
Kojto	90:cb3d968589d8	3143	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
Kojto	90:cb3d968589d8	3144	*/
Kojto	90:cb3d968589d8	3145	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
Kojto	90:cb3d968589d8	3146	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
Kojto	90:cb3d968589d8	3147
Kojto	90:cb3d968589d8	3148	/** @brief Macro to get the ADC1 clock (ADC1CLK).
Kojto	90:cb3d968589d8	3149	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3150	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
Kojto	90:cb3d968589d8	3151	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
Kojto	90:cb3d968589d8	3152	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
Kojto	90:cb3d968589d8	3153	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
Kojto	90:cb3d968589d8	3154	*/
Kojto	90:cb3d968589d8	3155	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
Kojto	90:cb3d968589d8	3156	/**
Kojto	90:cb3d968589d8	3157	* @}
Kojto	90:cb3d968589d8	3158	*/
Kojto	90:cb3d968589d8	3159
Kojto	90:cb3d968589d8	3160	/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
Kojto	90:cb3d968589d8	3161	* @{
Kojto	90:cb3d968589d8	3162	*/
Kojto	90:cb3d968589d8	3163	/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
Kojto	90:cb3d968589d8	3164	* @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
Kojto	90:cb3d968589d8	3165	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3166	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
Kojto	90:cb3d968589d8	3167	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
Kojto	90:cb3d968589d8	3168	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
Kojto	90:cb3d968589d8	3169	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
Kojto	90:cb3d968589d8	3170	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
Kojto	90:cb3d968589d8	3171	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
Kojto	90:cb3d968589d8	3172	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
Kojto	90:cb3d968589d8	3173	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
Kojto	90:cb3d968589d8	3174	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
Kojto	90:cb3d968589d8	3175	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
Kojto	90:cb3d968589d8	3176	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
Kojto	90:cb3d968589d8	3177	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
Kojto	90:cb3d968589d8	3178	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
Kojto	90:cb3d968589d8	3179	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
Kojto	90:cb3d968589d8	3180	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
Kojto	90:cb3d968589d8	3181	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
Kojto	90:cb3d968589d8	3182	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
Kojto	90:cb3d968589d8	3183	*/
Kojto	90:cb3d968589d8	3184	#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
Kojto	90:cb3d968589d8	3185	MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
Kojto	90:cb3d968589d8	3186
Kojto	90:cb3d968589d8	3187	/** @brief Macro to get the SDADCx clock prescaler.
Kojto	90:cb3d968589d8	3188	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3189	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
Kojto	90:cb3d968589d8	3190	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
Kojto	90:cb3d968589d8	3191	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
Kojto	90:cb3d968589d8	3192	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
Kojto	90:cb3d968589d8	3193	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
Kojto	90:cb3d968589d8	3194	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
Kojto	90:cb3d968589d8	3195	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
Kojto	90:cb3d968589d8	3196	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
Kojto	90:cb3d968589d8	3197	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
Kojto	90:cb3d968589d8	3198	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
Kojto	90:cb3d968589d8	3199	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
Kojto	90:cb3d968589d8	3200	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
Kojto	90:cb3d968589d8	3201	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
Kojto	90:cb3d968589d8	3202	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
Kojto	90:cb3d968589d8	3203	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
Kojto	90:cb3d968589d8	3204	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
Kojto	90:cb3d968589d8	3205	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
Kojto	90:cb3d968589d8	3206	*/
Kojto	90:cb3d968589d8	3207	#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
Kojto	90:cb3d968589d8	3208	/**
Kojto	90:cb3d968589d8	3209	* @}
Kojto	90:cb3d968589d8	3210	*/
Kojto	90:cb3d968589d8	3211
Kojto	90:cb3d968589d8	3212	/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
Kojto	90:cb3d968589d8	3213	* @{
Kojto	90:cb3d968589d8	3214	*/
Kojto	90:cb3d968589d8	3215	/** @brief Macro to configure the CEC clock.
Kojto	90:cb3d968589d8	3216	* @param __CECCLKSource__: specifies the CEC clock source.
Kojto	90:cb3d968589d8	3217	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3218	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	90:cb3d968589d8	3219	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	90:cb3d968589d8	3220	*/
Kojto	90:cb3d968589d8	3221	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
Kojto	90:cb3d968589d8	3222	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
Kojto	90:cb3d968589d8	3223
Kojto	90:cb3d968589d8	3224	/** @brief Macro to get the HDMI CEC clock source.
Kojto	90:cb3d968589d8	3225	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3226	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
Kojto	90:cb3d968589d8	3227	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
Kojto	90:cb3d968589d8	3228	*/
Kojto	90:cb3d968589d8	3229	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
Kojto	90:cb3d968589d8	3230	/**
Kojto	90:cb3d968589d8	3231	* @}
Kojto	90:cb3d968589d8	3232	*/
Kojto	90:cb3d968589d8	3233
Kojto	90:cb3d968589d8	3234	#endif /* STM32F373xC \|\| STM32F378xx */
Kojto	90:cb3d968589d8	3235
Kojto	90:cb3d968589d8	3236	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
Kojto	90:cb3d968589d8	3237	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
Kojto	90:cb3d968589d8	3238	defined(STM32F302x8) \|\| \
Kojto	90:cb3d968589d8	3239	defined(STM32F373xC)
Kojto	90:cb3d968589d8	3240
Kojto	90:cb3d968589d8	3241	/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
Kojto	90:cb3d968589d8	3242	* @{
Kojto	90:cb3d968589d8	3243	*/
Kojto	90:cb3d968589d8	3244	/** @brief Macro to configure the USB clock (USBCLK).
Kojto	90:cb3d968589d8	3245	* @param __USBCLKSource__: specifies the USB clock source.
Kojto	90:cb3d968589d8	3246	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3247	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
Kojto	90:cb3d968589d8	3248	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
Kojto	90:cb3d968589d8	3249	*/
Kojto	90:cb3d968589d8	3250	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
Kojto	90:cb3d968589d8	3251	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
Kojto	90:cb3d968589d8	3252
Kojto	90:cb3d968589d8	3253	/** @brief Macro to get the USB clock source.
Kojto	90:cb3d968589d8	3254	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3255	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
Kojto	90:cb3d968589d8	3256	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
Kojto	90:cb3d968589d8	3257	*/
Kojto	90:cb3d968589d8	3258	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
Kojto	90:cb3d968589d8	3259	/**
Kojto	90:cb3d968589d8	3260	* @}
Kojto	90:cb3d968589d8	3261	*/
Kojto	90:cb3d968589d8	3262
Kojto	90:cb3d968589d8	3263	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
Kojto	90:cb3d968589d8	3264	/* STM32F302xC \|\| STM32F303xC \|\| */
Kojto	90:cb3d968589d8	3265	/* STM32F302x8 \|\| */
Kojto	90:cb3d968589d8	3266	/* STM32F373xC */
Kojto	90:cb3d968589d8	3267
Kojto	90:cb3d968589d8	3268	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
Kojto	90:cb3d968589d8	3269	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
Kojto	90:cb3d968589d8	3270	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
Kojto	90:cb3d968589d8	3271
Kojto	90:cb3d968589d8	3272	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto	90:cb3d968589d8	3273	* @{
Kojto	90:cb3d968589d8	3274	*/
Kojto	90:cb3d968589d8	3275	/** @brief macro to configure the MCO clock.
Kojto	90:cb3d968589d8	3276	* @param __MCOCLKSource__: specifies the MCO clock source.
Kojto	90:cb3d968589d8	3277	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3278	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
Kojto	90:cb3d968589d8	3279	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
Kojto	90:cb3d968589d8	3280	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
Kojto	90:cb3d968589d8	3281	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
Kojto	90:cb3d968589d8	3282	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
Kojto	90:cb3d968589d8	3283	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
Kojto	90:cb3d968589d8	3284	* @param __MCODiv__: specifies the MCO clock prescaler.
Kojto	90:cb3d968589d8	3285	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3286	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
Kojto	90:cb3d968589d8	3287	*/
Kojto	90:cb3d968589d8	3288	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto	90:cb3d968589d8	3289	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
Kojto	90:cb3d968589d8	3290	/**
Kojto	90:cb3d968589d8	3291	* @}
Kojto	90:cb3d968589d8	3292	*/
Kojto	90:cb3d968589d8	3293	#else
Kojto	90:cb3d968589d8	3294	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
Kojto	90:cb3d968589d8	3295	* @{
Kojto	90:cb3d968589d8	3296	*/
Kojto	90:cb3d968589d8	3297
Kojto	90:cb3d968589d8	3298	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
Kojto	90:cb3d968589d8	3299	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
Kojto	90:cb3d968589d8	3300	/**
Kojto	90:cb3d968589d8	3301	* @}
Kojto	90:cb3d968589d8	3302	*/
Kojto	90:cb3d968589d8	3303
Kojto	90:cb3d968589d8	3304	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
Kojto	90:cb3d968589d8	3305	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
Kojto	90:cb3d968589d8	3306	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
Kojto	90:cb3d968589d8	3307
Kojto	90:cb3d968589d8	3308	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	3309
Kojto	90:cb3d968589d8	3310	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
Kojto	90:cb3d968589d8	3311	* @{
Kojto	90:cb3d968589d8	3312	*/
Kojto	90:cb3d968589d8	3313	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
Kojto	90:cb3d968589d8	3314	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
Kojto	90:cb3d968589d8	3315	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3316	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	90:cb3d968589d8	3317	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	90:cb3d968589d8	3318	*/
Kojto	90:cb3d968589d8	3319	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
Kojto	90:cb3d968589d8	3320	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
Kojto	90:cb3d968589d8	3321
Kojto	90:cb3d968589d8	3322	/** @brief Macro to get the I2C3 clock source.
Kojto	90:cb3d968589d8	3323	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3324	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	90:cb3d968589d8	3325	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	90:cb3d968589d8	3326	*/
Kojto	90:cb3d968589d8	3327	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
Kojto	90:cb3d968589d8	3328	/**
Kojto	90:cb3d968589d8	3329	* @}
Kojto	90:cb3d968589d8	3330	*/
Kojto	90:cb3d968589d8	3331
Kojto	90:cb3d968589d8	3332	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	90:cb3d968589d8	3333	* @{
Kojto	90:cb3d968589d8	3334	*/
Kojto	90:cb3d968589d8	3335	/** @brief Macro to configure the TIM2 clock (TIM2CLK).
Kojto	90:cb3d968589d8	3336	* @param __TIM2CLKSource__: specifies the TIM2 clock source.
Kojto	90:cb3d968589d8	3337	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3338	* @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
Kojto	90:cb3d968589d8	3339	* @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
Kojto	90:cb3d968589d8	3340	*/
Kojto	90:cb3d968589d8	3341	#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
Kojto	90:cb3d968589d8	3342	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
Kojto	90:cb3d968589d8	3343
Kojto	90:cb3d968589d8	3344	/** @brief Macro to get the TIM2 clock (TIM2CLK).
Kojto	90:cb3d968589d8	3345	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3346	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3347	* @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
Kojto	90:cb3d968589d8	3348	* @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
Kojto	90:cb3d968589d8	3349	*/
Kojto	90:cb3d968589d8	3350	#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
Kojto	90:cb3d968589d8	3351
Kojto	90:cb3d968589d8	3352	/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
Kojto	90:cb3d968589d8	3353	* @param __TIM3CLKSource__: specifies the TIM3 & TIM4 clock source.
Kojto	90:cb3d968589d8	3354	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3355	* @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
Kojto	90:cb3d968589d8	3356	* @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
Kojto	90:cb3d968589d8	3357	*/
Kojto	90:cb3d968589d8	3358	#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
Kojto	90:cb3d968589d8	3359	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
Kojto	90:cb3d968589d8	3360
Kojto	90:cb3d968589d8	3361	/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
Kojto	90:cb3d968589d8	3362	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3363	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3364	* @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
Kojto	90:cb3d968589d8	3365	* @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
Kojto	90:cb3d968589d8	3366	*/
Kojto	90:cb3d968589d8	3367	#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
Kojto	90:cb3d968589d8	3368
Kojto	90:cb3d968589d8	3369	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
Kojto	90:cb3d968589d8	3370	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
Kojto	90:cb3d968589d8	3371	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3372	* @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
Kojto	90:cb3d968589d8	3373	* @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
Kojto	90:cb3d968589d8	3374	*/
Kojto	90:cb3d968589d8	3375	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
Kojto	90:cb3d968589d8	3376	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
Kojto	90:cb3d968589d8	3377
Kojto	90:cb3d968589d8	3378	/** @brief Macro to get the TIM15 clock (TIM15CLK).
Kojto	90:cb3d968589d8	3379	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3380	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3381	* @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
Kojto	90:cb3d968589d8	3382	* @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
Kojto	90:cb3d968589d8	3383	*/
Kojto	90:cb3d968589d8	3384	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
Kojto	90:cb3d968589d8	3385
Kojto	90:cb3d968589d8	3386	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
Kojto	90:cb3d968589d8	3387	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
Kojto	90:cb3d968589d8	3388	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3389	* @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
Kojto	90:cb3d968589d8	3390	* @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
Kojto	90:cb3d968589d8	3391	*/
Kojto	90:cb3d968589d8	3392	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
Kojto	90:cb3d968589d8	3393	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
Kojto	90:cb3d968589d8	3394
Kojto	90:cb3d968589d8	3395	/** @brief Macro to get the TIM16 clock (TIM16CLK).
Kojto	90:cb3d968589d8	3396	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3397	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3398	* @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
Kojto	90:cb3d968589d8	3399	* @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
Kojto	90:cb3d968589d8	3400	*/
Kojto	90:cb3d968589d8	3401	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
Kojto	90:cb3d968589d8	3402
Kojto	90:cb3d968589d8	3403	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
Kojto	90:cb3d968589d8	3404	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
Kojto	90:cb3d968589d8	3405	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3406	* @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
Kojto	90:cb3d968589d8	3407	* @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
Kojto	90:cb3d968589d8	3408	*/
Kojto	90:cb3d968589d8	3409	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
Kojto	90:cb3d968589d8	3410	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
Kojto	90:cb3d968589d8	3411
Kojto	90:cb3d968589d8	3412	/** @brief Macro to get the TIM17 clock (TIM17CLK).
Kojto	90:cb3d968589d8	3413	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3414	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3415	* @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
Kojto	90:cb3d968589d8	3416	* @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
Kojto	90:cb3d968589d8	3417	*/
Kojto	90:cb3d968589d8	3418	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
Kojto	90:cb3d968589d8	3419
Kojto	90:cb3d968589d8	3420	/**
Kojto	90:cb3d968589d8	3421	* @}
Kojto	90:cb3d968589d8	3422	*/
Kojto	90:cb3d968589d8	3423
Kojto	90:cb3d968589d8	3424	#endif /* STM32f302xE \|\| STM32f303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	3425
Kojto	90:cb3d968589d8	3426	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
Kojto	90:cb3d968589d8	3427	/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
Kojto	90:cb3d968589d8	3428	* @{
Kojto	90:cb3d968589d8	3429	*/
Kojto	90:cb3d968589d8	3430	/** @brief Macro to configure the TIM20 clock (TIM20CLK).
Kojto	90:cb3d968589d8	3431	* @param __TIM20CLKSource__: specifies the TIM20 clock source.
Kojto	90:cb3d968589d8	3432	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3433	* @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
Kojto	90:cb3d968589d8	3434	* @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
Kojto	90:cb3d968589d8	3435	*/
Kojto	90:cb3d968589d8	3436	#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
Kojto	90:cb3d968589d8	3437	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
Kojto	90:cb3d968589d8	3438
Kojto	90:cb3d968589d8	3439	/** @brief Macro to get the TIM20 clock (TIM20CLK).
Kojto	90:cb3d968589d8	3440	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	3441	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	3442	* @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
Kojto	90:cb3d968589d8	3443	* @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
Kojto	90:cb3d968589d8	3444	*/
Kojto	90:cb3d968589d8	3445	#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
Kojto	90:cb3d968589d8	3446
Kojto	90:cb3d968589d8	3447	/**
Kojto	90:cb3d968589d8	3448	* @}
Kojto	90:cb3d968589d8	3449	*/
Kojto	90:cb3d968589d8	3450	#endif /* STM32f303xE \|\| STM32F398xx */
Kojto	90:cb3d968589d8	3451
Kojto	90:cb3d968589d8	3452
Kojto	90:cb3d968589d8	3453	/**
Kojto	90:cb3d968589d8	3454	* @}
Kojto	90:cb3d968589d8	3455	*/
Kojto	90:cb3d968589d8	3456
Kojto	90:cb3d968589d8	3457	/* Exported functions --------------------------------------------------------*/
Kojto	90:cb3d968589d8	3458	/** @addtogroup RCCEx_Exported_Functions RCC Extended Exported Functions
Kojto	90:cb3d968589d8	3459	* @{
Kojto	90:cb3d968589d8	3460	*/
Kojto	90:cb3d968589d8	3461
Kojto	90:cb3d968589d8	3462	/** @addtogroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
Kojto	90:cb3d968589d8	3463	* @{
Kojto	90:cb3d968589d8	3464	*/
Kojto	90:cb3d968589d8	3465	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	90:cb3d968589d8	3466	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	90:cb3d968589d8	3467	/**
Kojto	90:cb3d968589d8	3468	* @}
Kojto	90:cb3d968589d8	3469	*/
Kojto	90:cb3d968589d8	3470
Kojto	90:cb3d968589d8	3471	/**
Kojto	90:cb3d968589d8	3472	* @}
Kojto	90:cb3d968589d8	3473	*/
Kojto	90:cb3d968589d8	3474
Kojto	90:cb3d968589d8	3475	/**
Kojto	90:cb3d968589d8	3476	* @}
Kojto	90:cb3d968589d8	3477	*/
Kojto	90:cb3d968589d8	3478
Kojto	90:cb3d968589d8	3479	/**
Kojto	90:cb3d968589d8	3480	* @}
Kojto	90:cb3d968589d8	3481	*/
Kojto	90:cb3d968589d8	3482	#ifdef __cplusplus
Kojto	90:cb3d968589d8	3483	}
Kojto	90:cb3d968589d8	3484	#endif
Kojto	90:cb3d968589d8	3485
Kojto	90:cb3d968589d8	3486	#endif /* __STM32F3xx_HAL_RCC_EX_H */
Kojto	90:cb3d968589d8	3487
Kojto	90:cb3d968589d8	3488	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F302R8/stm32f3xx_hal_rcc_ex.h@90:cb3d968589d8, 2014-10-28 (annotated)

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