Filippo Casamassima / mbed

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Dependents:   Nucleo_blueNRG

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f4xx_hal_nand.h@77:869cf507173a, 2014-02-14 (annotated)

Committer:
emilmont
Date:
Fri Feb 14 14:36:43 2014 +0000
Revision:
77:869cf507173a
Child:
81:7d30d6019079
Release 77 of the mbed library



Main changes:

* Add target NUCLEO_F030R8

* Add target NUCLEO_F401RE

* Add target NUCLEO_F103RB

* Add target NUCLEO_L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_nand.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.0.0RC2
emilmont 77:869cf507173a 6 * @date 04-February-2014
emilmont 77:869cf507173a 7 * @brief Header file of NAND HAL module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_NAND_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_NAND_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
emilmont 77:869cf507173a 48 #include "stm32f4xx_ll_fsmc.h"
emilmont 77:869cf507173a 49 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
emilmont 77:869cf507173a 50
emilmont 77:869cf507173a 51 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
emilmont 77:869cf507173a 52 #include "stm32f4xx_ll_fmc.h"
emilmont 77:869cf507173a 53 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 54
emilmont 77:869cf507173a 55 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 56 * @{
emilmont 77:869cf507173a 57 */
emilmont 77:869cf507173a 58
emilmont 77:869cf507173a 59 /** @addtogroup NAND
emilmont 77:869cf507173a 60 * @{
emilmont 77:869cf507173a 61 */
emilmont 77:869cf507173a 62
emilmont 77:869cf507173a 63 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
emilmont 77:869cf507173a 64
emilmont 77:869cf507173a 65 /* Exported typedef ----------------------------------------------------------*/
emilmont 77:869cf507173a 66 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 67
emilmont 77:869cf507173a 68 /**
emilmont 77:869cf507173a 69 * @brief HAL NAND State structures definition
emilmont 77:869cf507173a 70 */
emilmont 77:869cf507173a 71 typedef enum
emilmont 77:869cf507173a 72 {
emilmont 77:869cf507173a 73 HAL_NAND_STATE_RESET = 0x00, /*!< NAND not yet initialized or disabled */
emilmont 77:869cf507173a 74 HAL_NAND_STATE_READY = 0x01, /*!< NAND initialized and ready for use */
emilmont 77:869cf507173a 75 HAL_NAND_STATE_BUSY = 0x02, /*!< NAND internal process is ongoing */
emilmont 77:869cf507173a 76 HAL_NAND_STATE_ERROR = 0x03 /*!< NAND error state */
emilmont 77:869cf507173a 77
emilmont 77:869cf507173a 78 }HAL_NAND_StateTypeDef;
emilmont 77:869cf507173a 79
emilmont 77:869cf507173a 80 /**
emilmont 77:869cf507173a 81 * @brief NAND Memory electronic signature Structure definition
emilmont 77:869cf507173a 82 */
emilmont 77:869cf507173a 83 typedef struct
emilmont 77:869cf507173a 84 {
emilmont 77:869cf507173a 85 /*<! NAND memory electronic signature maker and device IDs */
emilmont 77:869cf507173a 86
emilmont 77:869cf507173a 87 uint8_t Maker_Id;
emilmont 77:869cf507173a 88
emilmont 77:869cf507173a 89 uint8_t Device_Id;
emilmont 77:869cf507173a 90
emilmont 77:869cf507173a 91 uint8_t Third_Id;
emilmont 77:869cf507173a 92
emilmont 77:869cf507173a 93 uint8_t Fourth_Id;
emilmont 77:869cf507173a 94
emilmont 77:869cf507173a 95 }NAND_IDTypeDef;
emilmont 77:869cf507173a 96
emilmont 77:869cf507173a 97 /**
emilmont 77:869cf507173a 98 * @brief NAND Memory address Structure definition
emilmont 77:869cf507173a 99 */
emilmont 77:869cf507173a 100 typedef struct
emilmont 77:869cf507173a 101 {
emilmont 77:869cf507173a 102 uint16_t Page; /*!< NAND memory Page address */
emilmont 77:869cf507173a 103
emilmont 77:869cf507173a 104 uint16_t Zone; /*!< NAND memory Zone address */
emilmont 77:869cf507173a 105
emilmont 77:869cf507173a 106 uint16_t Block; /*!< NAND memory Block address */
emilmont 77:869cf507173a 107
emilmont 77:869cf507173a 108 }NAND_AddressTypedef;
emilmont 77:869cf507173a 109
emilmont 77:869cf507173a 110 /**
emilmont 77:869cf507173a 111 * @brief NAND Memory info Structure definition
emilmont 77:869cf507173a 112 */
emilmont 77:869cf507173a 113 typedef struct
emilmont 77:869cf507173a 114 {
emilmont 77:869cf507173a 115 uint32_t PageSize; /*!< NAND memory page (without spare area) size measured in K. bytes */
emilmont 77:869cf507173a 116
emilmont 77:869cf507173a 117 uint32_t SpareAreaSize; /*!< NAND memory spare area size measured in K. bytes */
emilmont 77:869cf507173a 118
emilmont 77:869cf507173a 119 uint32_t BlockSize; /*!< NAND memory block size number of pages */
emilmont 77:869cf507173a 120
emilmont 77:869cf507173a 121 uint32_t BlockNbr; /*!< NAND memory number of blocks */
emilmont 77:869cf507173a 122
emilmont 77:869cf507173a 123 uint32_t ZoneSize; /*!< NAND memory zone size measured in number of blocks */
emilmont 77:869cf507173a 124
emilmont 77:869cf507173a 125 }NAND_InfoTypeDef;
emilmont 77:869cf507173a 126
emilmont 77:869cf507173a 127 /**
emilmont 77:869cf507173a 128 * @brief NAND handle Structure definition
emilmont 77:869cf507173a 129 */
emilmont 77:869cf507173a 130 typedef struct
emilmont 77:869cf507173a 131 {
emilmont 77:869cf507173a 132 FMC_NAND_TypeDef *Instance; /*!< Register base address */
emilmont 77:869cf507173a 133
emilmont 77:869cf507173a 134 FMC_NAND_InitTypeDef Init; /*!< NAND device control configuration parameters */
emilmont 77:869cf507173a 135
emilmont 77:869cf507173a 136 HAL_LockTypeDef Lock; /*!< NAND locking object */
emilmont 77:869cf507173a 137
emilmont 77:869cf507173a 138 __IO HAL_NAND_StateTypeDef State; /*!< NAND device access state */
emilmont 77:869cf507173a 139
emilmont 77:869cf507173a 140 NAND_InfoTypeDef Info; /*!< NAND characteristic information structure */
emilmont 77:869cf507173a 141
emilmont 77:869cf507173a 142 }NAND_HandleTypeDef;
emilmont 77:869cf507173a 143
emilmont 77:869cf507173a 144
emilmont 77:869cf507173a 145 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 146 /** @defgroup NAND_Exported_Constants
emilmont 77:869cf507173a 147 * @{
emilmont 77:869cf507173a 148 */
emilmont 77:869cf507173a 149 #define NAND_DEVICE1 ((uint32_t)0x70000000)
emilmont 77:869cf507173a 150 #define NAND_DEVICE2 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 151 #define NAND_WRITE_TIMEOUT ((uint32_t)0x01000000)
emilmont 77:869cf507173a 152
emilmont 77:869cf507173a 153 #define CMD_AREA ((uint32_t)(1<<16)) /* A16 = CLE high */
emilmont 77:869cf507173a 154 #define ADDR_AREA ((uint32_t)(1<<17)) /* A17 = ALE high */
emilmont 77:869cf507173a 155
emilmont 77:869cf507173a 156 #define NAND_CMD_AREA_A ((uint8_t)0x00)
emilmont 77:869cf507173a 157 #define NAND_CMD_AREA_B ((uint8_t)0x01)
emilmont 77:869cf507173a 158 #define NAND_CMD_AREA_C ((uint8_t)0x50)
emilmont 77:869cf507173a 159
emilmont 77:869cf507173a 160 /* NAND memory status */
emilmont 77:869cf507173a 161 #define NAND_VALID_ADDRESS ((uint32_t)0x00000100)
emilmont 77:869cf507173a 162 #define NAND_INVALID_ADDRESS ((uint32_t)0x00000200)
emilmont 77:869cf507173a 163 #define NAND_TIMEOUT_ERROR ((uint32_t)0x00000400)
emilmont 77:869cf507173a 164 #define NAND_BUSY ((uint32_t)0x00000000)
emilmont 77:869cf507173a 165 #define NAND_ERROR ((uint32_t)0x00000001)
emilmont 77:869cf507173a 166 #define NAND_READY ((uint32_t)0x00000040)
emilmont 77:869cf507173a 167
emilmont 77:869cf507173a 168 /**
emilmont 77:869cf507173a 169 * @}
emilmont 77:869cf507173a 170 */
emilmont 77:869cf507173a 171
emilmont 77:869cf507173a 172 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 173 /**
emilmont 77:869cf507173a 174 * @brief NAND memory address computation.
emilmont 77:869cf507173a 175 * @param __ADDRESS__: NAND memory address.
emilmont 77:869cf507173a 176 * @param __HANDLE__ : NAND handle.
emilmont 77:869cf507173a 177 * @retval NAND Raw address value
emilmont 77:869cf507173a 178 */
emilmont 77:869cf507173a 179 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + (((__ADDRESS__)->Block + (((__ADDRESS__)->Zone) * ((__HANDLE__)->Info.BlockSize)))* ((__HANDLE__)->Info.ZoneSize)))
emilmont 77:869cf507173a 180
emilmont 77:869cf507173a 181 /**
emilmont 77:869cf507173a 182 * @brief NAND memory address cycling.
emilmont 77:869cf507173a 183 * @param __ADDRESS__: NAND memory address.
emilmont 77:869cf507173a 184 * @retval NAND address cycling value.
emilmont 77:869cf507173a 185 */
emilmont 77:869cf507173a 186 #define ADDR_1st_CYCLE(__ADDRESS__) (uint8_t)((__ADDRESS__)& 0xFF) /* 1st addressing cycle */
emilmont 77:869cf507173a 187 #define ADDR_2nd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF00) >> 8) /* 2nd addressing cycle */
emilmont 77:869cf507173a 188 #define ADDR_3rd_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF0000) >> 16) /* 3rd addressing cycle */
emilmont 77:869cf507173a 189 #define ADDR_4th_CYCLE(__ADDRESS__) (uint8_t)(((__ADDRESS__)& 0xFF000000) >> 24) /* 4th addressing cycle */
emilmont 77:869cf507173a 190
emilmont 77:869cf507173a 191 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 192
emilmont 77:869cf507173a 193 /* Initialization/de-initialization functions **********************************/
emilmont 77:869cf507173a 194 HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
emilmont 77:869cf507173a 195 HAL_StatusTypeDef HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 196 __weak void HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 197 __weak void HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 198 void HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 199 __weak void HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 200
emilmont 77:869cf507173a 201 /* IO operation functions *****************************************************/
emilmont 77:869cf507173a 202 HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
emilmont 77:869cf507173a 203 HAL_StatusTypeDef HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 204 HAL_StatusTypeDef HAL_NAND_Read_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
emilmont 77:869cf507173a 205 HAL_StatusTypeDef HAL_NAND_Write_Page(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
emilmont 77:869cf507173a 206 HAL_StatusTypeDef HAL_NAND_Read_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
emilmont 77:869cf507173a 207 HAL_StatusTypeDef HAL_NAND_Write_SpareArea(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
emilmont 77:869cf507173a 208 HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
emilmont 77:869cf507173a 209 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 210 uint32_t HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypedef *pAddress);
emilmont 77:869cf507173a 211
emilmont 77:869cf507173a 212 /* NAND Control functions ******************************************************/
emilmont 77:869cf507173a 213 HAL_StatusTypeDef HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 214 HAL_StatusTypeDef HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 215 HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
emilmont 77:869cf507173a 216
emilmont 77:869cf507173a 217 /* NAND State functions *********************************************************/
emilmont 77:869cf507173a 218 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 219 uint32_t HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
emilmont 77:869cf507173a 220
emilmont 77:869cf507173a 221 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 222 /**
emilmont 77:869cf507173a 223 * @}
emilmont 77:869cf507173a 224 */
emilmont 77:869cf507173a 225
emilmont 77:869cf507173a 226 /**
emilmont 77:869cf507173a 227 * @}
emilmont 77:869cf507173a 228 */
emilmont 77:869cf507173a 229
emilmont 77:869cf507173a 230 #ifdef __cplusplus
emilmont 77:869cf507173a 231 }
emilmont 77:869cf507173a 232 #endif
emilmont 77:869cf507173a 233
emilmont 77:869cf507173a 234 #endif /* __STM32F4xx_HAL_NAND_H */
emilmont 77:869cf507173a 235
emilmont 77:869cf507173a 236 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/