Filippo Casamassima / mbed

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TARGET_NUCLEO_L152RE/stm32l1xx.h@81:7d30d6019079, 2014-03-19 (annotated)

Committer:
bogdanm
Date:
Wed Mar 19 18:28:32 2014 +0000
Revision:
81:7d30d6019079
Parent:
77:869cf507173a
Child:
90:cb3d968589d8
Release 81 of the mbed library



Main changes:



- Updates and fixes for many targets

- LPC1768: serial interface code fixes

- nRF51822 targets now output a .hex file

- More exporters

- More flexible GPIO API

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32l1xx.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
emilmont 77:869cf507173a 5 * @version V1.3.0
emilmont 77:869cf507173a 6 * @date 31-January-2014
emilmont 77:869cf507173a 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer Header File.
emilmont 77:869cf507173a 8 * This file contains all the peripheral register's definitions, bits
emilmont 77:869cf507173a 9 * definitions and memory mapping for STM32L1xx High-density, Medium-density,
emilmont 77:869cf507173a 10 * Medium-density and XL-density Plus devices.
emilmont 77:869cf507173a 11 *
emilmont 77:869cf507173a 12 * The file is the unique include file that the application programmer
emilmont 77:869cf507173a 13 * is using in the C source code, usually in main.c. This file contains:
emilmont 77:869cf507173a 14 * - Configuration section that allows to select:
emilmont 77:869cf507173a 15 * - The device used in the target application
emilmont 77:869cf507173a 16 * - To use or not the peripheral’s drivers in application code(i.e.
emilmont 77:869cf507173a 17 * code will be based on direct access to peripheral’s registers
emilmont 77:869cf507173a 18 * rather than drivers API), this option is controlled by
emilmont 77:869cf507173a 19 * "#define USE_STDPERIPH_DRIVER"
emilmont 77:869cf507173a 20 * - To change few application-specific parameters such as the HSE
emilmont 77:869cf507173a 21 * crystal frequency
emilmont 77:869cf507173a 22 * - Data structures and the address mapping for all peripherals
emilmont 77:869cf507173a 23 * - Peripheral's registers declarations and bits definition
emilmont 77:869cf507173a 24 * - Macros to access peripheral’s registers hardware
emilmont 77:869cf507173a 25 *
emilmont 77:869cf507173a 26 ******************************************************************************
emilmont 77:869cf507173a 27 * @attention
emilmont 77:869cf507173a 28 *
bogdanm 81:7d30d6019079 29 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 30 *
bogdanm 81:7d30d6019079 31 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 81:7d30d6019079 32 * are permitted provided that the following conditions are met:
bogdanm 81:7d30d6019079 33 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 81:7d30d6019079 34 * this list of conditions and the following disclaimer.
bogdanm 81:7d30d6019079 35 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 81:7d30d6019079 36 * this list of conditions and the following disclaimer in the documentation
bogdanm 81:7d30d6019079 37 * and/or other materials provided with the distribution.
bogdanm 81:7d30d6019079 38 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 81:7d30d6019079 39 * may be used to endorse or promote products derived from this software
bogdanm 81:7d30d6019079 40 * without specific prior written permission.
emilmont 77:869cf507173a 41 *
bogdanm 81:7d30d6019079 42 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 81:7d30d6019079 43 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 81:7d30d6019079 44 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 81:7d30d6019079 45 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 81:7d30d6019079 46 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 81:7d30d6019079 47 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 81:7d30d6019079 48 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 81:7d30d6019079 49 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 81:7d30d6019079 50 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 81:7d30d6019079 51 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 52 *
emilmont 77:869cf507173a 53 ******************************************************************************
emilmont 77:869cf507173a 54 */
emilmont 77:869cf507173a 55
emilmont 77:869cf507173a 56 /** @addtogroup CMSIS
emilmont 77:869cf507173a 57 * @{
emilmont 77:869cf507173a 58 */
emilmont 77:869cf507173a 59
emilmont 77:869cf507173a 60 /** @addtogroup stm32l1xx
emilmont 77:869cf507173a 61 * @{
emilmont 77:869cf507173a 62 */
emilmont 77:869cf507173a 63
emilmont 77:869cf507173a 64 #ifndef __STM32L1XX_H
emilmont 77:869cf507173a 65 #define __STM32L1XX_H
emilmont 77:869cf507173a 66
emilmont 77:869cf507173a 67 #ifdef __cplusplus
emilmont 77:869cf507173a 68 extern "C" {
emilmont 77:869cf507173a 69 #endif
emilmont 77:869cf507173a 70
emilmont 77:869cf507173a 71 /** @addtogroup Library_configuration_section
emilmont 77:869cf507173a 72 * @{
emilmont 77:869cf507173a 73 */
emilmont 77:869cf507173a 74
emilmont 77:869cf507173a 75 /* Uncomment the line below according to the target STM32L device used in your
emilmont 77:869cf507173a 76 application
emilmont 77:869cf507173a 77 */
emilmont 77:869cf507173a 78
emilmont 77:869cf507173a 79 #if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
emilmont 77:869cf507173a 80
emilmont 77:869cf507173a 81 /* #define STM32L1XX_MD */ /*!< - Ultra Low Power Medium-density devices: STM32L151x6xx, STM32L151x8xx,
emilmont 77:869cf507173a 82 STM32L151xBxx, STM32L152x6xx, STM32L152x8xx, STM32L152xBxx,
emilmont 77:869cf507173a 83 STM32L151x6xxA, STM32L151x8xxA, STM32L151xBxxA, STM32L152x6xxA,
emilmont 77:869cf507173a 84 STM32L152x8xxA and STM32L152xBxxA.
emilmont 77:869cf507173a 85 - Ultra Low Power Medium-density Value Line devices: STM32L100x6xx,
emilmont 77:869cf507173a 86 STM32L100x8xx and STM32L100xBxx. */
emilmont 77:869cf507173a 87
emilmont 77:869cf507173a 88 /* #define STM32L1XX_MDP */ /*!< - Ultra Low Power Medium-density Plus devices: STM32L151xCxx, STM32L152xCxx and STM32L162xCxx
emilmont 77:869cf507173a 89 - Ultra Low Power Medium-density Plus Value Line devices: STM32L100xCxx */
emilmont 77:869cf507173a 90
emilmont 77:869cf507173a 91 /* #define STM32L1XX_HD */ /*!< Ultra Low Power High-density devices: STM32L151xDxx, STM32L152xDxx and STM32L162xDxx */
emilmont 77:869cf507173a 92
emilmont 77:869cf507173a 93 #define STM32L1XX_XL /*!< Ultra Low Power XL-density devices: STM32L151xExx, STM32L152xExx and STM32L162xExx */
emilmont 77:869cf507173a 94 #endif
emilmont 77:869cf507173a 95 /* Tip: To avoid modifying this file each time you need to switch between these
emilmont 77:869cf507173a 96 devices, you can define the device in your toolchain compiler preprocessor.
emilmont 77:869cf507173a 97 */
emilmont 77:869cf507173a 98
emilmont 77:869cf507173a 99 #if !defined (STM32L1XX_MD) && !defined (STM32L1XX_MDP) && !defined (STM32L1XX_HD) && !defined (STM32L1XX_XL)
emilmont 77:869cf507173a 100 #error "Please select first the target STM32L1xx device used in your application (in stm32l1xx.h file)"
emilmont 77:869cf507173a 101 #endif
emilmont 77:869cf507173a 102
emilmont 77:869cf507173a 103 #if !defined USE_STDPERIPH_DRIVER
emilmont 77:869cf507173a 104 /**
emilmont 77:869cf507173a 105 * @brief Comment the line below if you will not use the peripherals drivers.
emilmont 77:869cf507173a 106 In this case, these drivers will not be included and the application code will
emilmont 77:869cf507173a 107 be based on direct access to peripherals registers
emilmont 77:869cf507173a 108 */
emilmont 77:869cf507173a 109 #define USE_STDPERIPH_DRIVER
emilmont 77:869cf507173a 110 #endif
emilmont 77:869cf507173a 111
emilmont 77:869cf507173a 112 /**
emilmont 77:869cf507173a 113 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
emilmont 77:869cf507173a 114 used in your application
emilmont 77:869cf507173a 115
emilmont 77:869cf507173a 116 Tip: To avoid modifying this file each time you need to use different HSE, you
emilmont 77:869cf507173a 117 can define the HSE value in your toolchain compiler preprocessor.
emilmont 77:869cf507173a 118 */
emilmont 77:869cf507173a 119 #if !defined (HSE_VALUE)
emilmont 77:869cf507173a 120 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */
emilmont 77:869cf507173a 121 #endif
emilmont 77:869cf507173a 122
emilmont 77:869cf507173a 123 /**
emilmont 77:869cf507173a 124 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
emilmont 77:869cf507173a 125 Timeout value
emilmont 77:869cf507173a 126 */
emilmont 77:869cf507173a 127 #if !defined (HSE_STARTUP_TIMEOUT)
emilmont 77:869cf507173a 128 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
emilmont 77:869cf507173a 129 #endif
emilmont 77:869cf507173a 130
emilmont 77:869cf507173a 131 /**
emilmont 77:869cf507173a 132 * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
emilmont 77:869cf507173a 133 Timeout value
emilmont 77:869cf507173a 134 */
emilmont 77:869cf507173a 135 #if !defined (HSI_STARTUP_TIMEOUT)
emilmont 77:869cf507173a 136 #define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
emilmont 77:869cf507173a 137 #endif
emilmont 77:869cf507173a 138
emilmont 77:869cf507173a 139 #if !defined (HSI_VALUE)
emilmont 77:869cf507173a 140 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal High Speed oscillator in Hz.
emilmont 77:869cf507173a 141 The real value may vary depending on the variations
emilmont 77:869cf507173a 142 in voltage and temperature. */
emilmont 77:869cf507173a 143 #endif
emilmont 77:869cf507173a 144
emilmont 77:869cf507173a 145 #if !defined (LSI_VALUE)
emilmont 77:869cf507173a 146 #define LSI_VALUE ((uint32_t)37000) /*!< Value of the Internal Low Speed oscillator in Hz
emilmont 77:869cf507173a 147 The real value may vary depending on the variations
emilmont 77:869cf507173a 148 in voltage and temperature. */
emilmont 77:869cf507173a 149 #endif
emilmont 77:869cf507173a 150
emilmont 77:869cf507173a 151 #if !defined (LSE_VALUE)
emilmont 77:869cf507173a 152 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
emilmont 77:869cf507173a 153 #endif
emilmont 77:869cf507173a 154
emilmont 77:869cf507173a 155 /**
emilmont 77:869cf507173a 156 * @brief STM32L1xx Standard Peripheral Library version number V1.3.0
emilmont 77:869cf507173a 157 */
emilmont 77:869cf507173a 158 #define __STM32L1XX_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
emilmont 77:869cf507173a 159 #define __STM32L1XX_STDPERIPH_VERSION_SUB1 (0x03) /*!< [23:16] sub1 version */
emilmont 77:869cf507173a 160 #define __STM32L1XX_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
emilmont 77:869cf507173a 161 #define __STM32L1XX_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
emilmont 77:869cf507173a 162 #define __STM32L1XX_STDPERIPH_VERSION ( (__STM32L1XX_STDPERIPH_VERSION_MAIN << 24)\
emilmont 77:869cf507173a 163 |(__STM32L1XX_STDPERIPH_VERSION_SUB1 << 16)\
emilmont 77:869cf507173a 164 |(__STM32L1XX_STDPERIPH_VERSION_SUB2 << 8)\
emilmont 77:869cf507173a 165 |(__STM32L1XX_STDPERIPH_VERSION_RC))
emilmont 77:869cf507173a 166
emilmont 77:869cf507173a 167 /**
emilmont 77:869cf507173a 168 * @}
emilmont 77:869cf507173a 169 */
emilmont 77:869cf507173a 170
emilmont 77:869cf507173a 171 /** @addtogroup Configuration_section_for_CMSIS
emilmont 77:869cf507173a 172 * @{
emilmont 77:869cf507173a 173 */
emilmont 77:869cf507173a 174
emilmont 77:869cf507173a 175 /**
emilmont 77:869cf507173a 176 * @brief STM32L1xx Interrupt Number Definition, according to the selected device
emilmont 77:869cf507173a 177 * in @ref Library_configuration_section
emilmont 77:869cf507173a 178 */
emilmont 77:869cf507173a 179 #define __CM3_REV 0x200 /*!< Cortex-M3 Revision r2p0 */
emilmont 77:869cf507173a 180 #define __MPU_PRESENT 1 /*!< STM32L1 provides MPU */
emilmont 77:869cf507173a 181 #define __NVIC_PRIO_BITS 4 /*!< STM32L1 uses 4 Bits for the Priority Levels */
emilmont 77:869cf507173a 182 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 77:869cf507173a 183
emilmont 77:869cf507173a 184 /*!< Interrupt Number Definition */
emilmont 77:869cf507173a 185 typedef enum IRQn
emilmont 77:869cf507173a 186 {
emilmont 77:869cf507173a 187 /****** Cortex-M3 Processor Exceptions Numbers ******************************************************/
emilmont 77:869cf507173a 188 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
emilmont 77:869cf507173a 189 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
emilmont 77:869cf507173a 190 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
emilmont 77:869cf507173a 191 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
emilmont 77:869cf507173a 192 SVC_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
emilmont 77:869cf507173a 193 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
emilmont 77:869cf507173a 194 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
emilmont 77:869cf507173a 195 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
emilmont 77:869cf507173a 196
emilmont 77:869cf507173a 197 /****** STM32L specific Interrupt Numbers ***********************************************************/
emilmont 77:869cf507173a 198 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
emilmont 77:869cf507173a 199 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
emilmont 77:869cf507173a 200 TAMPER_STAMP_IRQn = 2, /*!< Tamper and Time Stamp through EXTI Line Interrupts */
emilmont 77:869cf507173a 201 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup Timer through EXTI Line Interrupt */
emilmont 77:869cf507173a 202 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
emilmont 77:869cf507173a 203 RCC_IRQn = 5, /*!< RCC global Interrupt */
emilmont 77:869cf507173a 204 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
emilmont 77:869cf507173a 205 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
emilmont 77:869cf507173a 206 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
emilmont 77:869cf507173a 207 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
emilmont 77:869cf507173a 208 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
emilmont 77:869cf507173a 209 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 global Interrupt */
emilmont 77:869cf507173a 210 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 global Interrupt */
emilmont 77:869cf507173a 211 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 global Interrupt */
emilmont 77:869cf507173a 212 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 global Interrupt */
emilmont 77:869cf507173a 213 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 global Interrupt */
emilmont 77:869cf507173a 214 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 global Interrupt */
emilmont 77:869cf507173a 215 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 global Interrupt */
emilmont 77:869cf507173a 216 ADC1_IRQn = 18, /*!< ADC1 global Interrupt */
emilmont 77:869cf507173a 217 USB_HP_IRQn = 19, /*!< USB High Priority Interrupt */
emilmont 77:869cf507173a 218 USB_LP_IRQn = 20, /*!< USB Low Priority Interrupt */
emilmont 77:869cf507173a 219 DAC_IRQn = 21, /*!< DAC Interrupt */
emilmont 77:869cf507173a 220 COMP_IRQn = 22, /*!< Comparator through EXTI Line Interrupt */
emilmont 77:869cf507173a 221 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
emilmont 77:869cf507173a 222 LCD_IRQn = 24, /*!< LCD Interrupt */
emilmont 77:869cf507173a 223 TIM9_IRQn = 25, /*!< TIM9 global Interrupt */
emilmont 77:869cf507173a 224 TIM10_IRQn = 26, /*!< TIM10 global Interrupt */
emilmont 77:869cf507173a 225 TIM11_IRQn = 27, /*!< TIM11 global Interrupt */
emilmont 77:869cf507173a 226 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
emilmont 77:869cf507173a 227 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
emilmont 77:869cf507173a 228 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
emilmont 77:869cf507173a 229 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
emilmont 77:869cf507173a 230 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
emilmont 77:869cf507173a 231 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
emilmont 77:869cf507173a 232 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
emilmont 77:869cf507173a 233 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
emilmont 77:869cf507173a 234 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
emilmont 77:869cf507173a 235 USART1_IRQn = 37, /*!< USART1 global Interrupt */
emilmont 77:869cf507173a 236 USART2_IRQn = 38, /*!< USART2 global Interrupt */
emilmont 77:869cf507173a 237 USART3_IRQn = 39, /*!< USART3 global Interrupt */
emilmont 77:869cf507173a 238 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
emilmont 77:869cf507173a 239 RTC_Alarm_IRQn = 41, /*!< RTC Alarm through EXTI Line Interrupt */
emilmont 77:869cf507173a 240 USB_FS_WKUP_IRQn = 42, /*!< USB FS WakeUp from suspend through EXTI Line Interrupt */
emilmont 77:869cf507173a 241 TIM6_IRQn = 43, /*!< TIM6 global Interrupt */
emilmont 77:869cf507173a 242
emilmont 77:869cf507173a 243 #ifdef STM32L1XX_MD
emilmont 77:869cf507173a 244 TIM7_IRQn = 44 /*!< TIM7 global Interrupt */
emilmont 77:869cf507173a 245 #endif /* STM32L1XX_MD */
emilmont 77:869cf507173a 246
emilmont 77:869cf507173a 247 #ifdef STM32L1XX_MDP
emilmont 77:869cf507173a 248 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
emilmont 77:869cf507173a 249 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
emilmont 77:869cf507173a 250 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
emilmont 77:869cf507173a 251 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
emilmont 77:869cf507173a 252 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
emilmont 77:869cf507173a 253 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
emilmont 77:869cf507173a 254 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
emilmont 77:869cf507173a 255 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
emilmont 77:869cf507173a 256 AES_IRQn = 55, /*!< AES global Interrupt */
emilmont 77:869cf507173a 257 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
emilmont 77:869cf507173a 258 #endif /* STM32L1XX_MDP */
emilmont 77:869cf507173a 259
emilmont 77:869cf507173a 260 #ifdef STM32L1XX_HD
emilmont 77:869cf507173a 261 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
emilmont 77:869cf507173a 262 SDIO_IRQn = 45, /*!< SDIO global Interrupt */
emilmont 77:869cf507173a 263 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
emilmont 77:869cf507173a 264 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
emilmont 77:869cf507173a 265 UART4_IRQn = 48, /*!< UART4 global Interrupt */
emilmont 77:869cf507173a 266 UART5_IRQn = 49, /*!< UART5 global Interrupt */
emilmont 77:869cf507173a 267 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
emilmont 77:869cf507173a 268 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
emilmont 77:869cf507173a 269 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
emilmont 77:869cf507173a 270 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
emilmont 77:869cf507173a 271 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
emilmont 77:869cf507173a 272 AES_IRQn = 55, /*!< AES global Interrupt */
emilmont 77:869cf507173a 273 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
emilmont 77:869cf507173a 274 #endif /* STM32L1XX_HD */
emilmont 77:869cf507173a 275
emilmont 77:869cf507173a 276 #ifdef STM32L1XX_XL
emilmont 77:869cf507173a 277 TIM7_IRQn = 44, /*!< TIM7 global Interrupt */
emilmont 77:869cf507173a 278 TIM5_IRQn = 46, /*!< TIM5 global Interrupt */
emilmont 77:869cf507173a 279 SPI3_IRQn = 47, /*!< SPI3 global Interrupt */
emilmont 77:869cf507173a 280 UART4_IRQn = 48, /*!< UART4 global Interrupt */
emilmont 77:869cf507173a 281 UART5_IRQn = 49, /*!< UART5 global Interrupt */
emilmont 77:869cf507173a 282 DMA2_Channel1_IRQn = 50, /*!< DMA2 Channel 1 global Interrupt */
emilmont 77:869cf507173a 283 DMA2_Channel2_IRQn = 51, /*!< DMA2 Channel 2 global Interrupt */
emilmont 77:869cf507173a 284 DMA2_Channel3_IRQn = 52, /*!< DMA2 Channel 3 global Interrupt */
emilmont 77:869cf507173a 285 DMA2_Channel4_IRQn = 53, /*!< DMA2 Channel 4 global Interrupt */
emilmont 77:869cf507173a 286 DMA2_Channel5_IRQn = 54, /*!< DMA2 Channel 5 global Interrupt */
emilmont 77:869cf507173a 287 AES_IRQn = 55, /*!< AES global Interrupt */
emilmont 77:869cf507173a 288 COMP_ACQ_IRQn = 56 /*!< Comparator Channel Acquisition global Interrupt */
emilmont 77:869cf507173a 289 #endif /* STM32L1XX_XL */
emilmont 77:869cf507173a 290 } IRQn_Type;
emilmont 77:869cf507173a 291
emilmont 77:869cf507173a 292 /**
emilmont 77:869cf507173a 293 * @}
emilmont 77:869cf507173a 294 */
emilmont 77:869cf507173a 295
emilmont 77:869cf507173a 296 #include "core_cm3.h"
emilmont 77:869cf507173a 297 #include "system_stm32l1xx.h"
emilmont 77:869cf507173a 298 #include <stdint.h>
emilmont 77:869cf507173a 299
emilmont 77:869cf507173a 300 /** @addtogroup Exported_types
emilmont 77:869cf507173a 301 * @{
emilmont 77:869cf507173a 302 */
emilmont 77:869cf507173a 303
emilmont 77:869cf507173a 304 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
emilmont 77:869cf507173a 305
emilmont 77:869cf507173a 306 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
emilmont 77:869cf507173a 307 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
emilmont 77:869cf507173a 308
emilmont 77:869cf507173a 309 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
emilmont 77:869cf507173a 310
emilmont 77:869cf507173a 311 /**
emilmont 77:869cf507173a 312 * @brief __RAM_FUNC definition
emilmont 77:869cf507173a 313 */
emilmont 77:869cf507173a 314 #if defined ( __CC_ARM )
emilmont 77:869cf507173a 315 /* ARM Compiler
emilmont 77:869cf507173a 316 ------------
emilmont 77:869cf507173a 317 RAM functions are defined using the toolchain options.
emilmont 77:869cf507173a 318 Functions that are executed in RAM should reside in a separate source module.
emilmont 77:869cf507173a 319 Using the 'Options for File' dialog you can simply change the 'Code / Const'
emilmont 77:869cf507173a 320 area of a module to a memory space in physical RAM.
emilmont 77:869cf507173a 321 Available memory areas are declared in the 'Target' tab of the 'Options for Target'
emilmont 77:869cf507173a 322 dialog.
emilmont 77:869cf507173a 323 */
emilmont 77:869cf507173a 324 #define __RAM_FUNC FLASH_Status
emilmont 77:869cf507173a 325
emilmont 77:869cf507173a 326 #elif defined ( __ICCARM__ )
emilmont 77:869cf507173a 327 /* ICCARM Compiler
emilmont 77:869cf507173a 328 ---------------
emilmont 77:869cf507173a 329 RAM functions are defined using a specific toolchain keyword "__ramfunc".
emilmont 77:869cf507173a 330 */
emilmont 77:869cf507173a 331 #define __RAM_FUNC __ramfunc FLASH_Status
emilmont 77:869cf507173a 332
emilmont 77:869cf507173a 333 #elif defined ( __GNUC__ )
emilmont 77:869cf507173a 334 /* GNU Compiler
emilmont 77:869cf507173a 335 ------------
emilmont 77:869cf507173a 336 RAM functions are defined using a specific toolchain attribute
emilmont 77:869cf507173a 337 "__attribute__((section(".data")))".
emilmont 77:869cf507173a 338 */
emilmont 77:869cf507173a 339 #define __RAM_FUNC FLASH_Status __attribute__((section(".data")))
emilmont 77:869cf507173a 340
emilmont 77:869cf507173a 341 #elif defined ( __TASKING__ )
emilmont 77:869cf507173a 342 /* TASKING Compiler
emilmont 77:869cf507173a 343 ----------------
emilmont 77:869cf507173a 344 RAM functions are defined using a specific toolchain pragma. This pragma is
emilmont 77:869cf507173a 345 defined in the stm32l1xx_flash_ramfunc.c
emilmont 77:869cf507173a 346 */
emilmont 77:869cf507173a 347 #define __RAM_FUNC FLASH_Status
emilmont 77:869cf507173a 348
emilmont 77:869cf507173a 349 #endif
emilmont 77:869cf507173a 350
emilmont 77:869cf507173a 351 /**
emilmont 77:869cf507173a 352 * @}
emilmont 77:869cf507173a 353 */
emilmont 77:869cf507173a 354
emilmont 77:869cf507173a 355 /** @addtogroup Peripheral_registers_structures
emilmont 77:869cf507173a 356 * @{
emilmont 77:869cf507173a 357 */
emilmont 77:869cf507173a 358
emilmont 77:869cf507173a 359 /**
emilmont 77:869cf507173a 360 * @brief Analog to Digital Converter
emilmont 77:869cf507173a 361 */
emilmont 77:869cf507173a 362
emilmont 77:869cf507173a 363 typedef struct
emilmont 77:869cf507173a 364 {
emilmont 77:869cf507173a 365 __IO uint32_t SR; /*!< ADC status register, Address offset: 0x00 */
emilmont 77:869cf507173a 366 __IO uint32_t CR1; /*!< ADC control register 1, Address offset: 0x04 */
emilmont 77:869cf507173a 367 __IO uint32_t CR2; /*!< ADC control register 2, Address offset: 0x08 */
emilmont 77:869cf507173a 368 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x0C */
emilmont 77:869cf507173a 369 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x10 */
emilmont 77:869cf507173a 370 __IO uint32_t SMPR3; /*!< ADC sample time register 3, Address offset: 0x14 */
emilmont 77:869cf507173a 371 __IO uint32_t JOFR1; /*!< ADC injected channel data offset register 1, Address offset: 0x18 */
emilmont 77:869cf507173a 372 __IO uint32_t JOFR2; /*!< ADC injected channel data offset register 2, Address offset: 0x1C */
emilmont 77:869cf507173a 373 __IO uint32_t JOFR3; /*!< ADC injected channel data offset register 3, Address offset: 0x20 */
emilmont 77:869cf507173a 374 __IO uint32_t JOFR4; /*!< ADC injected channel data offset register 4, Address offset: 0x24 */
emilmont 77:869cf507173a 375 __IO uint32_t HTR; /*!< ADC watchdog higher threshold register, Address offset: 0x28 */
emilmont 77:869cf507173a 376 __IO uint32_t LTR; /*!< ADC watchdog lower threshold register, Address offset: 0x2C */
emilmont 77:869cf507173a 377 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
emilmont 77:869cf507173a 378 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
emilmont 77:869cf507173a 379 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
emilmont 77:869cf507173a 380 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
emilmont 77:869cf507173a 381 __IO uint32_t SQR5; /*!< ADC regular sequence register 5, Address offset: 0x40 */
emilmont 77:869cf507173a 382 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x44 */
emilmont 77:869cf507173a 383 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x48 */
emilmont 77:869cf507173a 384 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x4C */
emilmont 77:869cf507173a 385 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x50 */
emilmont 77:869cf507173a 386 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x54 */
emilmont 77:869cf507173a 387 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x58 */
emilmont 77:869cf507173a 388 __IO uint32_t SMPR0; /*!< ADC sample time register 0, Address offset: 0x5C */
emilmont 77:869cf507173a 389 } ADC_TypeDef;
emilmont 77:869cf507173a 390
emilmont 77:869cf507173a 391 typedef struct
emilmont 77:869cf507173a 392 {
emilmont 77:869cf507173a 393 __IO uint32_t CSR; /*!< ADC common status register, Address offset: ADC1 base address + 0x300 */
emilmont 77:869cf507173a 394 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1 base address + 0x304 */
emilmont 77:869cf507173a 395 } ADC_Common_TypeDef;
emilmont 77:869cf507173a 396
emilmont 77:869cf507173a 397
emilmont 77:869cf507173a 398 /**
emilmont 77:869cf507173a 399 * @brief AES hardware accelerator
emilmont 77:869cf507173a 400 */
emilmont 77:869cf507173a 401
emilmont 77:869cf507173a 402 typedef struct
emilmont 77:869cf507173a 403 {
emilmont 77:869cf507173a 404 __IO uint32_t CR; /*!< AES control register, Address offset: 0x00 */
emilmont 77:869cf507173a 405 __IO uint32_t SR; /*!< AES status register, Address offset: 0x04 */
emilmont 77:869cf507173a 406 __IO uint32_t DINR; /*!< AES data input register, Address offset: 0x08 */
emilmont 77:869cf507173a 407 __IO uint32_t DOUTR; /*!< AES data output register, Address offset: 0x0C */
emilmont 77:869cf507173a 408 __IO uint32_t KEYR0; /*!< AES key register 0, Address offset: 0x10 */
emilmont 77:869cf507173a 409 __IO uint32_t KEYR1; /*!< AES key register 1, Address offset: 0x14 */
emilmont 77:869cf507173a 410 __IO uint32_t KEYR2; /*!< AES key register 2, Address offset: 0x18 */
emilmont 77:869cf507173a 411 __IO uint32_t KEYR3; /*!< AES key register 3, Address offset: 0x1C */
emilmont 77:869cf507173a 412 __IO uint32_t IVR0; /*!< AES initialization vector register 0, Address offset: 0x20 */
emilmont 77:869cf507173a 413 __IO uint32_t IVR1; /*!< AES initialization vector register 1, Address offset: 0x24 */
emilmont 77:869cf507173a 414 __IO uint32_t IVR2; /*!< AES initialization vector register 2, Address offset: 0x28 */
emilmont 77:869cf507173a 415 __IO uint32_t IVR3; /*!< AES initialization vector register 3, Address offset: 0x2C */
emilmont 77:869cf507173a 416 } AES_TypeDef;
emilmont 77:869cf507173a 417
emilmont 77:869cf507173a 418 /**
emilmont 77:869cf507173a 419 * @brief Comparator
emilmont 77:869cf507173a 420 */
emilmont 77:869cf507173a 421
emilmont 77:869cf507173a 422 typedef struct
emilmont 77:869cf507173a 423 {
emilmont 77:869cf507173a 424 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x00 */
emilmont 77:869cf507173a 425 } COMP_TypeDef;
emilmont 77:869cf507173a 426
emilmont 77:869cf507173a 427 /**
emilmont 77:869cf507173a 428 * @brief CRC calculation unit
emilmont 77:869cf507173a 429 */
emilmont 77:869cf507173a 430
emilmont 77:869cf507173a 431 typedef struct
emilmont 77:869cf507173a 432 {
emilmont 77:869cf507173a 433 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
emilmont 77:869cf507173a 434 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
emilmont 77:869cf507173a 435 uint8_t RESERVED0; /*!< Reserved, 0x05 */
emilmont 77:869cf507173a 436 uint16_t RESERVED1; /*!< Reserved, 0x06 */
emilmont 77:869cf507173a 437 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
emilmont 77:869cf507173a 438 } CRC_TypeDef;
emilmont 77:869cf507173a 439
emilmont 77:869cf507173a 440 /**
emilmont 77:869cf507173a 441 * @brief Digital to Analog Converter
emilmont 77:869cf507173a 442 */
emilmont 77:869cf507173a 443
emilmont 77:869cf507173a 444 typedef struct
emilmont 77:869cf507173a 445 {
emilmont 77:869cf507173a 446 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
emilmont 77:869cf507173a 447 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
emilmont 77:869cf507173a 448 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
emilmont 77:869cf507173a 449 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
emilmont 77:869cf507173a 450 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
emilmont 77:869cf507173a 451 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
emilmont 77:869cf507173a 452 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
emilmont 77:869cf507173a 453 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
emilmont 77:869cf507173a 454 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
emilmont 77:869cf507173a 455 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
emilmont 77:869cf507173a 456 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
emilmont 77:869cf507173a 457 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
emilmont 77:869cf507173a 458 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
emilmont 77:869cf507173a 459 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
emilmont 77:869cf507173a 460 } DAC_TypeDef;
emilmont 77:869cf507173a 461
emilmont 77:869cf507173a 462 /**
emilmont 77:869cf507173a 463 * @brief Debug MCU
emilmont 77:869cf507173a 464 */
emilmont 77:869cf507173a 465
emilmont 77:869cf507173a 466 typedef struct
emilmont 77:869cf507173a 467 {
emilmont 77:869cf507173a 468 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
emilmont 77:869cf507173a 469 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
emilmont 77:869cf507173a 470 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
emilmont 77:869cf507173a 471 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
emilmont 77:869cf507173a 472 }DBGMCU_TypeDef;
emilmont 77:869cf507173a 473
emilmont 77:869cf507173a 474 /**
emilmont 77:869cf507173a 475 * @brief DMA Controller
emilmont 77:869cf507173a 476 */
emilmont 77:869cf507173a 477
emilmont 77:869cf507173a 478 typedef struct
emilmont 77:869cf507173a 479 {
emilmont 77:869cf507173a 480 __IO uint32_t CCR; /*!< DMA channel x configuration register */
emilmont 77:869cf507173a 481 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
emilmont 77:869cf507173a 482 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
emilmont 77:869cf507173a 483 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
emilmont 77:869cf507173a 484 } DMA_Channel_TypeDef;
emilmont 77:869cf507173a 485
emilmont 77:869cf507173a 486 typedef struct
emilmont 77:869cf507173a 487 {
emilmont 77:869cf507173a 488 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
emilmont 77:869cf507173a 489 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
emilmont 77:869cf507173a 490 } DMA_TypeDef;
emilmont 77:869cf507173a 491
emilmont 77:869cf507173a 492 /**
emilmont 77:869cf507173a 493 * @brief External Interrupt/Event Controller
emilmont 77:869cf507173a 494 */
emilmont 77:869cf507173a 495
emilmont 77:869cf507173a 496 typedef struct
emilmont 77:869cf507173a 497 {
emilmont 77:869cf507173a 498 __IO uint32_t IMR; /*!< EXTI interrupt mask register, Address offset: 0x00 */
emilmont 77:869cf507173a 499 __IO uint32_t EMR; /*!< EXTI event mask register, Address offset: 0x04 */
emilmont 77:869cf507173a 500 __IO uint32_t RTSR; /*!< EXTI rising edge trigger selection register, Address offset: 0x08 */
emilmont 77:869cf507173a 501 __IO uint32_t FTSR; /*!< EXTI Falling edge trigger selection register, Address offset: 0x0C */
emilmont 77:869cf507173a 502 __IO uint32_t SWIER; /*!< EXTI software interrupt event register, Address offset: 0x10 */
emilmont 77:869cf507173a 503 __IO uint32_t PR; /*!< EXTI pending register, Address offset: 0x14 */
emilmont 77:869cf507173a 504 } EXTI_TypeDef;
emilmont 77:869cf507173a 505
emilmont 77:869cf507173a 506 /**
emilmont 77:869cf507173a 507 * @brief FLASH Registers
emilmont 77:869cf507173a 508 */
emilmont 77:869cf507173a 509
emilmont 77:869cf507173a 510 typedef struct
emilmont 77:869cf507173a 511 {
emilmont 77:869cf507173a 512 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
emilmont 77:869cf507173a 513 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
emilmont 77:869cf507173a 514 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
emilmont 77:869cf507173a 515 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
emilmont 77:869cf507173a 516 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
emilmont 77:869cf507173a 517 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
emilmont 77:869cf507173a 518 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
emilmont 77:869cf507173a 519 __IO uint32_t OBR; /*!< Option byte register, Address offset: 0x1c */
emilmont 77:869cf507173a 520 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
emilmont 77:869cf507173a 521 uint32_t RESERVED[23]; /*!< Reserved, 0x24 */
emilmont 77:869cf507173a 522 __IO uint32_t WRPR1; /*!< Write protection register 1, Address offset: 0x28 */
emilmont 77:869cf507173a 523 __IO uint32_t WRPR2; /*!< Write protection register 2, Address offset: 0x2C */
emilmont 77:869cf507173a 524 } FLASH_TypeDef;
emilmont 77:869cf507173a 525
emilmont 77:869cf507173a 526 /**
emilmont 77:869cf507173a 527 * @brief Option Bytes Registers
emilmont 77:869cf507173a 528 */
emilmont 77:869cf507173a 529
emilmont 77:869cf507173a 530 typedef struct
emilmont 77:869cf507173a 531 {
emilmont 77:869cf507173a 532 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
emilmont 77:869cf507173a 533 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
emilmont 77:869cf507173a 534 __IO uint32_t WRP01; /*!< write protection register 0 1, Address offset: 0x08 */
emilmont 77:869cf507173a 535 __IO uint32_t WRP23; /*!< write protection register 2 3, Address offset: 0x0C */
emilmont 77:869cf507173a 536 __IO uint32_t WRP45; /*!< write protection register 4 5, Address offset: 0x10 */
emilmont 77:869cf507173a 537 __IO uint32_t WRP67; /*!< write protection register 6 7, Address offset: 0x14 */
emilmont 77:869cf507173a 538 __IO uint32_t WRP89; /*!< write protection register 8 9, Address offset: 0x18 */
emilmont 77:869cf507173a 539 __IO uint32_t WRP1011; /*!< write protection register 10 11, Address offset: 0x1C */
emilmont 77:869cf507173a 540 } OB_TypeDef;
emilmont 77:869cf507173a 541
emilmont 77:869cf507173a 542 /**
emilmont 77:869cf507173a 543 * @brief Operational Amplifier (OPAMP)
emilmont 77:869cf507173a 544 */
emilmont 77:869cf507173a 545
emilmont 77:869cf507173a 546 typedef struct
emilmont 77:869cf507173a 547 {
emilmont 77:869cf507173a 548 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
emilmont 77:869cf507173a 549 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
emilmont 77:869cf507173a 550 __IO uint32_t LPOTR; /*!< OPAMP offset trimming register for low power mode, Address offset: 0x08 */
emilmont 77:869cf507173a 551 } OPAMP_TypeDef;
emilmont 77:869cf507173a 552
emilmont 77:869cf507173a 553 /**
emilmont 77:869cf507173a 554 * @brief Flexible Static Memory Controller
emilmont 77:869cf507173a 555 */
emilmont 77:869cf507173a 556
emilmont 77:869cf507173a 557 typedef struct
emilmont 77:869cf507173a 558 {
emilmont 77:869cf507173a 559 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
emilmont 77:869cf507173a 560 } FSMC_Bank1_TypeDef;
emilmont 77:869cf507173a 561
emilmont 77:869cf507173a 562 /**
emilmont 77:869cf507173a 563 * @brief Flexible Static Memory Controller Bank1E
emilmont 77:869cf507173a 564 */
emilmont 77:869cf507173a 565
emilmont 77:869cf507173a 566 typedef struct
emilmont 77:869cf507173a 567 {
emilmont 77:869cf507173a 568 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
emilmont 77:869cf507173a 569 } FSMC_Bank1E_TypeDef;
emilmont 77:869cf507173a 570
emilmont 77:869cf507173a 571 /**
emilmont 77:869cf507173a 572 * @brief General Purpose IO
emilmont 77:869cf507173a 573 */
emilmont 77:869cf507173a 574
emilmont 77:869cf507173a 575 typedef struct
emilmont 77:869cf507173a 576 {
emilmont 77:869cf507173a 577 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
emilmont 77:869cf507173a 578 __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
emilmont 77:869cf507173a 579 uint16_t RESERVED0; /*!< Reserved, 0x06 */
emilmont 77:869cf507173a 580 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
emilmont 77:869cf507173a 581 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
emilmont 77:869cf507173a 582 __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
emilmont 77:869cf507173a 583 uint16_t RESERVED1; /*!< Reserved, 0x12 */
emilmont 77:869cf507173a 584 __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
emilmont 77:869cf507173a 585 uint16_t RESERVED2; /*!< Reserved, 0x16 */
emilmont 77:869cf507173a 586 __IO uint16_t BSRRL; /*!< GPIO port bit set/reset low registerBSRR, Address offset: 0x18 */
emilmont 77:869cf507173a 587 __IO uint16_t BSRRH; /*!< GPIO port bit set/reset high registerBSRR, Address offset: 0x1A */
emilmont 77:869cf507173a 588 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
emilmont 77:869cf507173a 589 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
emilmont 77:869cf507173a 590 #if defined (STM32L1XX_HD) || defined (STM32L1XX_XL)
emilmont 77:869cf507173a 591 __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
emilmont 77:869cf507173a 592 uint16_t RESERVED3; /*!< Reserved, 0x2A */
emilmont 77:869cf507173a 593 #endif
emilmont 77:869cf507173a 594 } GPIO_TypeDef;
emilmont 77:869cf507173a 595
emilmont 77:869cf507173a 596 /**
emilmont 77:869cf507173a 597 * @brief SysTem Configuration
emilmont 77:869cf507173a 598 */
emilmont 77:869cf507173a 599
emilmont 77:869cf507173a 600 typedef struct
emilmont 77:869cf507173a 601 {
emilmont 77:869cf507173a 602 __IO uint32_t MEMRMP; /*!< SYSCFG memory remap register, Address offset: 0x00 */
emilmont 77:869cf507173a 603 __IO uint32_t PMC; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
emilmont 77:869cf507173a 604 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
emilmont 77:869cf507173a 605 } SYSCFG_TypeDef;
emilmont 77:869cf507173a 606
emilmont 77:869cf507173a 607 /**
emilmont 77:869cf507173a 608 * @brief Inter-integrated Circuit Interface
emilmont 77:869cf507173a 609 */
emilmont 77:869cf507173a 610
emilmont 77:869cf507173a 611 typedef struct
emilmont 77:869cf507173a 612 {
emilmont 77:869cf507173a 613 __IO uint16_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
emilmont 77:869cf507173a 614 uint16_t RESERVED0; /*!< Reserved, 0x02 */
emilmont 77:869cf507173a 615 __IO uint16_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
emilmont 77:869cf507173a 616 uint16_t RESERVED1; /*!< Reserved, 0x06 */
emilmont 77:869cf507173a 617 __IO uint16_t OAR1; /*!< I2C Own address register 1, Address offset: 0x08 */
emilmont 77:869cf507173a 618 uint16_t RESERVED2; /*!< Reserved, 0x0A */
emilmont 77:869cf507173a 619 __IO uint16_t OAR2; /*!< I2C Own address register 2, Address offset: 0x0C */
emilmont 77:869cf507173a 620 uint16_t RESERVED3; /*!< Reserved, 0x0E */
emilmont 77:869cf507173a 621 __IO uint16_t DR; /*!< I2C Data register, Address offset: 0x10 */
emilmont 77:869cf507173a 622 uint16_t RESERVED4; /*!< Reserved, 0x12 */
emilmont 77:869cf507173a 623 __IO uint16_t SR1; /*!< I2C Status register 1, Address offset: 0x14 */
emilmont 77:869cf507173a 624 uint16_t RESERVED5; /*!< Reserved, 0x16 */
emilmont 77:869cf507173a 625 __IO uint16_t SR2; /*!< I2C Status register 2, Address offset: 0x18 */
emilmont 77:869cf507173a 626 uint16_t RESERVED6; /*!< Reserved, 0x1A */
emilmont 77:869cf507173a 627 __IO uint16_t CCR; /*!< I2C Clock control register, Address offset: 0x1C */
emilmont 77:869cf507173a 628 uint16_t RESERVED7; /*!< Reserved, 0x1E */
emilmont 77:869cf507173a 629 __IO uint16_t TRISE; /*!< I2C TRISE register, Address offset: 0x20 */
emilmont 77:869cf507173a 630 uint16_t RESERVED8; /*!< Reserved, 0x22 */
emilmont 77:869cf507173a 631 } I2C_TypeDef;
emilmont 77:869cf507173a 632
emilmont 77:869cf507173a 633 /**
emilmont 77:869cf507173a 634 * @brief Independent WATCHDOG
emilmont 77:869cf507173a 635 */
emilmont 77:869cf507173a 636
emilmont 77:869cf507173a 637 typedef struct
emilmont 77:869cf507173a 638 {
emilmont 77:869cf507173a 639 __IO uint32_t KR; /*!< Key register, Address offset: 0x00 */
emilmont 77:869cf507173a 640 __IO uint32_t PR; /*!< Prescaler register, Address offset: 0x04 */
emilmont 77:869cf507173a 641 __IO uint32_t RLR; /*!< Reload register, Address offset: 0x08 */
emilmont 77:869cf507173a 642 __IO uint32_t SR; /*!< Status register, Address offset: 0x0C */
emilmont 77:869cf507173a 643 } IWDG_TypeDef;
emilmont 77:869cf507173a 644
emilmont 77:869cf507173a 645
emilmont 77:869cf507173a 646 /**
emilmont 77:869cf507173a 647 * @brief LCD
emilmont 77:869cf507173a 648 */
emilmont 77:869cf507173a 649
emilmont 77:869cf507173a 650 typedef struct
emilmont 77:869cf507173a 651 {
emilmont 77:869cf507173a 652 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
emilmont 77:869cf507173a 653 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
emilmont 77:869cf507173a 654 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
emilmont 77:869cf507173a 655 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
emilmont 77:869cf507173a 656 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
emilmont 77:869cf507173a 657 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
emilmont 77:869cf507173a 658 } LCD_TypeDef;
emilmont 77:869cf507173a 659
emilmont 77:869cf507173a 660 /**
emilmont 77:869cf507173a 661 * @brief Power Control
emilmont 77:869cf507173a 662 */
emilmont 77:869cf507173a 663
emilmont 77:869cf507173a 664 typedef struct
emilmont 77:869cf507173a 665 {
emilmont 77:869cf507173a 666 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
emilmont 77:869cf507173a 667 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
emilmont 77:869cf507173a 668 } PWR_TypeDef;
emilmont 77:869cf507173a 669
emilmont 77:869cf507173a 670 /**
emilmont 77:869cf507173a 671 * @brief Reset and Clock Control
emilmont 77:869cf507173a 672 */
emilmont 77:869cf507173a 673
emilmont 77:869cf507173a 674 typedef struct
emilmont 77:869cf507173a 675 {
emilmont 77:869cf507173a 676 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
emilmont 77:869cf507173a 677 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
emilmont 77:869cf507173a 678 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x08 */
emilmont 77:869cf507173a 679 __IO uint32_t CIR; /*!< RCC Clock interrupt register, Address offset: 0x0C */
emilmont 77:869cf507173a 680 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x10 */
emilmont 77:869cf507173a 681 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x14 */
emilmont 77:869cf507173a 682 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x18 */
emilmont 77:869cf507173a 683 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x1C */
emilmont 77:869cf507173a 684 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x20 */
emilmont 77:869cf507173a 685 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x24 */
emilmont 77:869cf507173a 686 __IO uint32_t AHBLPENR; /*!< RCC AHB peripheral clock enable in low power mode register, Address offset: 0x28 */
emilmont 77:869cf507173a 687 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x2C */
emilmont 77:869cf507173a 688 __IO uint32_t APB1LPENR; /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x30 */
emilmont 77:869cf507173a 689 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x34 */
emilmont 77:869cf507173a 690 } RCC_TypeDef;
emilmont 77:869cf507173a 691
emilmont 77:869cf507173a 692 /**
emilmont 77:869cf507173a 693 * @brief Routing Interface
emilmont 77:869cf507173a 694 */
emilmont 77:869cf507173a 695
emilmont 77:869cf507173a 696 typedef struct
emilmont 77:869cf507173a 697 {
emilmont 77:869cf507173a 698 __IO uint32_t ICR; /*!< RI input capture register, Address offset: 0x04 */
emilmont 77:869cf507173a 699 __IO uint32_t ASCR1; /*!< RI analog switches control register, Address offset: 0x08 */
emilmont 77:869cf507173a 700 __IO uint32_t ASCR2; /*!< RI analog switch control register 2, Address offset: 0x0C */
emilmont 77:869cf507173a 701 __IO uint32_t HYSCR1; /*!< RI hysteresis control register 1, Address offset: 0x10 */
emilmont 77:869cf507173a 702 __IO uint32_t HYSCR2; /*!< RI Hysteresis control register 2, Address offset: 0x14 */
emilmont 77:869cf507173a 703 __IO uint32_t HYSCR3; /*!< RI Hysteresis control register 3, Address offset: 0x18 */
emilmont 77:869cf507173a 704 __IO uint32_t HYSCR4; /*!< RI Hysteresis control register 4, Address offset: 0x1C */
emilmont 77:869cf507173a 705 __IO uint32_t ASMR1; /*!< RI Analog switch mode register 1, Address offset: 0x20 */
emilmont 77:869cf507173a 706 __IO uint32_t CMR1; /*!< RI Channel mask register 1, Address offset: 0x24 */
emilmont 77:869cf507173a 707 __IO uint32_t CICR1; /*!< RI Channel identification for capture register 1, Address offset: 0x28 */
emilmont 77:869cf507173a 708 __IO uint32_t ASMR2; /*!< RI Analog switch mode register 2, Address offset: 0x2C */
emilmont 77:869cf507173a 709 __IO uint32_t CMR2; /*!< RI Channel mask register 2, Address offset: 0x30 */
emilmont 77:869cf507173a 710 __IO uint32_t CICR2; /*!< RI Channel identification for capture register 2, Address offset: 0x34 */
emilmont 77:869cf507173a 711 __IO uint32_t ASMR3; /*!< RI Analog switch mode register 3, Address offset: 0x38 */
emilmont 77:869cf507173a 712 __IO uint32_t CMR3; /*!< RI Channel mask register 3, Address offset: 0x3C */
emilmont 77:869cf507173a 713 __IO uint32_t CICR3; /*!< RI Channel identification for capture register3 , Address offset: 0x40 */
emilmont 77:869cf507173a 714 __IO uint32_t ASMR4; /*!< RI Analog switch mode register 4, Address offset: 0x44 */
emilmont 77:869cf507173a 715 __IO uint32_t CMR4; /*!< RI Channel mask register 4, Address offset: 0x48 */
emilmont 77:869cf507173a 716 __IO uint32_t CICR4; /*!< RI Channel identification for capture register 4, Address offset: 0x4C */
emilmont 77:869cf507173a 717 __IO uint32_t ASMR5; /*!< RI Analog switch mode register 5, Address offset: 0x50 */
emilmont 77:869cf507173a 718 __IO uint32_t CMR5; /*!< RI Channel mask register 5, Address offset: 0x54 */
emilmont 77:869cf507173a 719 __IO uint32_t CICR5; /*!< RI Channel identification for capture register 5, Address offset: 0x58 */
emilmont 77:869cf507173a 720 } RI_TypeDef;
emilmont 77:869cf507173a 721
emilmont 77:869cf507173a 722 /**
emilmont 77:869cf507173a 723 * @brief Real-Time Clock
emilmont 77:869cf507173a 724 */
emilmont 77:869cf507173a 725
emilmont 77:869cf507173a 726 typedef struct
emilmont 77:869cf507173a 727 {
emilmont 77:869cf507173a 728 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
emilmont 77:869cf507173a 729 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
emilmont 77:869cf507173a 730 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
emilmont 77:869cf507173a 731 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
emilmont 77:869cf507173a 732 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
emilmont 77:869cf507173a 733 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
emilmont 77:869cf507173a 734 __IO uint32_t CALIBR; /*!< RTC calibration register, Address offset: 0x18 */
emilmont 77:869cf507173a 735 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
emilmont 77:869cf507173a 736 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
emilmont 77:869cf507173a 737 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
emilmont 77:869cf507173a 738 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
emilmont 77:869cf507173a 739 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
emilmont 77:869cf507173a 740 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
emilmont 77:869cf507173a 741 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
emilmont 77:869cf507173a 742 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
emilmont 77:869cf507173a 743 __IO uint32_t CALR; /*!< RRTC calibration register, Address offset: 0x3C */
emilmont 77:869cf507173a 744 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
emilmont 77:869cf507173a 745 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
emilmont 77:869cf507173a 746 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
emilmont 77:869cf507173a 747 uint32_t RESERVED7; /*!< Reserved, 0x4C */
emilmont 77:869cf507173a 748 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
emilmont 77:869cf507173a 749 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
emilmont 77:869cf507173a 750 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
emilmont 77:869cf507173a 751 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
emilmont 77:869cf507173a 752 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
emilmont 77:869cf507173a 753 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
emilmont 77:869cf507173a 754 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
emilmont 77:869cf507173a 755 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
emilmont 77:869cf507173a 756 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
emilmont 77:869cf507173a 757 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
emilmont 77:869cf507173a 758 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
emilmont 77:869cf507173a 759 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
emilmont 77:869cf507173a 760 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
emilmont 77:869cf507173a 761 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
emilmont 77:869cf507173a 762 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
emilmont 77:869cf507173a 763 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
emilmont 77:869cf507173a 764 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
emilmont 77:869cf507173a 765 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
emilmont 77:869cf507173a 766 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
emilmont 77:869cf507173a 767 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
emilmont 77:869cf507173a 768 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
emilmont 77:869cf507173a 769 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
emilmont 77:869cf507173a 770 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
emilmont 77:869cf507173a 771 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
emilmont 77:869cf507173a 772 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
emilmont 77:869cf507173a 773 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
emilmont 77:869cf507173a 774 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
emilmont 77:869cf507173a 775 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
emilmont 77:869cf507173a 776 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
emilmont 77:869cf507173a 777 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
emilmont 77:869cf507173a 778 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
emilmont 77:869cf507173a 779 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
emilmont 77:869cf507173a 780 } RTC_TypeDef;
emilmont 77:869cf507173a 781
emilmont 77:869cf507173a 782 /**
emilmont 77:869cf507173a 783 * @brief SD host Interface
emilmont 77:869cf507173a 784 */
emilmont 77:869cf507173a 785
emilmont 77:869cf507173a 786 typedef struct
emilmont 77:869cf507173a 787 {
emilmont 77:869cf507173a 788 __IO uint32_t POWER; /*!< SDIO power control register, Address offset: 0x00 */
emilmont 77:869cf507173a 789 __IO uint32_t CLKCR; /*!< SDI clock control register, Address offset: 0x04 */
emilmont 77:869cf507173a 790 __IO uint32_t ARG; /*!< SDIO argument register, Address offset: 0x08 */
emilmont 77:869cf507173a 791 __IO uint32_t CMD; /*!< SDIO command register, Address offset: 0x0C */
emilmont 77:869cf507173a 792 __I uint32_t RESPCMD; /*!< SDIO command response register, Address offset: 0x10 */
emilmont 77:869cf507173a 793 __I uint32_t RESP1; /*!< SDIO response 1 register, Address offset: 0x14 */
emilmont 77:869cf507173a 794 __I uint32_t RESP2; /*!< SDIO response 2 register, Address offset: 0x18 */
emilmont 77:869cf507173a 795 __I uint32_t RESP3; /*!< SDIO response 3 register, Address offset: 0x1C */
emilmont 77:869cf507173a 796 __I uint32_t RESP4; /*!< SDIO response 4 register, Address offset: 0x20 */
emilmont 77:869cf507173a 797 __IO uint32_t DTIMER; /*!< SDIO data timer register, Address offset: 0x24 */
emilmont 77:869cf507173a 798 __IO uint32_t DLEN; /*!< SDIO data length register, Address offset: 0x28 */
emilmont 77:869cf507173a 799 __IO uint32_t DCTRL; /*!< SDIO data control register, Address offset: 0x2C */
emilmont 77:869cf507173a 800 __I uint32_t DCOUNT; /*!< SDIO data counter register, Address offset: 0x30 */
emilmont 77:869cf507173a 801 __I uint32_t STA; /*!< SDIO status register, Address offset: 0x34 */
emilmont 77:869cf507173a 802 __IO uint32_t ICR; /*!< SDIO interrupt clear register, Address offset: 0x38 */
emilmont 77:869cf507173a 803 __IO uint32_t MASK; /*!< SDIO mask register, Address offset: 0x3C */
emilmont 77:869cf507173a 804 uint32_t RESERVED0[2]; /*!< Reserved, 0x40-0x44 */
emilmont 77:869cf507173a 805 __I uint32_t FIFOCNT; /*!< SDIO FIFO counter register, Address offset: 0x48 */
emilmont 77:869cf507173a 806 uint32_t RESERVED1[13]; /*!< Reserved, 0x4C-0x7C */
emilmont 77:869cf507173a 807 __IO uint32_t FIFO; /*!< SDIO data FIFO register, Address offset: 0x80 */
emilmont 77:869cf507173a 808 } SDIO_TypeDef;
emilmont 77:869cf507173a 809
emilmont 77:869cf507173a 810 /**
emilmont 77:869cf507173a 811 * @brief Serial Peripheral Interface
emilmont 77:869cf507173a 812 */
emilmont 77:869cf507173a 813
emilmont 77:869cf507173a 814 typedef struct
emilmont 77:869cf507173a 815 {
emilmont 77:869cf507173a 816 __IO uint16_t CR1; /*!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 */
emilmont 77:869cf507173a 817 uint16_t RESERVED0; /*!< Reserved, 0x02 */
emilmont 77:869cf507173a 818 __IO uint16_t CR2; /*!< SPI control register 2, Address offset: 0x04 */
emilmont 77:869cf507173a 819 uint16_t RESERVED1; /*!< Reserved, 0x06 */
emilmont 77:869cf507173a 820 __IO uint16_t SR; /*!< SPI status register, Address offset: 0x08 */
emilmont 77:869cf507173a 821 uint16_t RESERVED2; /*!< Reserved, 0x0A */
emilmont 77:869cf507173a 822 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
emilmont 77:869cf507173a 823 uint16_t RESERVED3; /*!< Reserved, 0x0E */
emilmont 77:869cf507173a 824 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
emilmont 77:869cf507173a 825 uint16_t RESERVED4; /*!< Reserved, 0x12 */
emilmont 77:869cf507173a 826 __IO uint16_t RXCRCR; /*!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 */
emilmont 77:869cf507173a 827 uint16_t RESERVED5; /*!< Reserved, 0x16 */
emilmont 77:869cf507173a 828 __IO uint16_t TXCRCR; /*!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 */
emilmont 77:869cf507173a 829 uint16_t RESERVED6; /*!< Reserved, 0x1A */
emilmont 77:869cf507173a 830 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
emilmont 77:869cf507173a 831 uint16_t RESERVED7; /*!< Reserved, 0x1E */
emilmont 77:869cf507173a 832 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
emilmont 77:869cf507173a 833 uint16_t RESERVED8; /*!< Reserved, 0x22 */
emilmont 77:869cf507173a 834 } SPI_TypeDef;
emilmont 77:869cf507173a 835
emilmont 77:869cf507173a 836 /**
emilmont 77:869cf507173a 837 * @brief TIM
emilmont 77:869cf507173a 838 */
emilmont 77:869cf507173a 839
emilmont 77:869cf507173a 840 typedef struct
emilmont 77:869cf507173a 841 {
emilmont 77:869cf507173a 842 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
emilmont 77:869cf507173a 843 uint16_t RESERVED0; /*!< Reserved, 0x02 */
emilmont 77:869cf507173a 844 __IO uint16_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
emilmont 77:869cf507173a 845 uint16_t RESERVED1; /*!< Reserved, 0x06 */
emilmont 77:869cf507173a 846 __IO uint16_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
emilmont 77:869cf507173a 847 uint16_t RESERVED2; /*!< Reserved, 0x0A */
emilmont 77:869cf507173a 848 __IO uint16_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
emilmont 77:869cf507173a 849 uint16_t RESERVED3; /*!< Reserved, 0x0E */
emilmont 77:869cf507173a 850 __IO uint16_t SR; /*!< TIM status register, Address offset: 0x10 */
emilmont 77:869cf507173a 851 uint16_t RESERVED4; /*!< Reserved, 0x12 */
emilmont 77:869cf507173a 852 __IO uint16_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
emilmont 77:869cf507173a 853 uint16_t RESERVED5; /*!< Reserved, 0x16 */
emilmont 77:869cf507173a 854 __IO uint16_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
emilmont 77:869cf507173a 855 uint16_t RESERVED6; /*!< Reserved, 0x1A */
emilmont 77:869cf507173a 856 __IO uint16_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
emilmont 77:869cf507173a 857 uint16_t RESERVED7; /*!< Reserved, 0x1E */
emilmont 77:869cf507173a 858 __IO uint16_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
emilmont 77:869cf507173a 859 uint16_t RESERVED8; /*!< Reserved, 0x22 */
emilmont 77:869cf507173a 860 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
emilmont 77:869cf507173a 861 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
emilmont 77:869cf507173a 862 uint16_t RESERVED10; /*!< Reserved, 0x2A */
emilmont 77:869cf507173a 863 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
emilmont 77:869cf507173a 864 uint32_t RESERVED12; /*!< Reserved, 0x30 */
emilmont 77:869cf507173a 865 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
emilmont 77:869cf507173a 866 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
emilmont 77:869cf507173a 867 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
emilmont 77:869cf507173a 868 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
emilmont 77:869cf507173a 869 uint32_t RESERVED17; /*!< Reserved, 0x44 */
emilmont 77:869cf507173a 870 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
emilmont 77:869cf507173a 871 uint16_t RESERVED18; /*!< Reserved, 0x4A */
emilmont 77:869cf507173a 872 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
emilmont 77:869cf507173a 873 uint16_t RESERVED19; /*!< Reserved, 0x4E */
emilmont 77:869cf507173a 874 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
emilmont 77:869cf507173a 875 uint16_t RESERVED20; /*!< Reserved, 0x52 */
emilmont 77:869cf507173a 876 } TIM_TypeDef;
emilmont 77:869cf507173a 877
emilmont 77:869cf507173a 878 /**
emilmont 77:869cf507173a 879 * @brief Universal Synchronous Asynchronous Receiver Transmitter
emilmont 77:869cf507173a 880 */
emilmont 77:869cf507173a 881
emilmont 77:869cf507173a 882 typedef struct
emilmont 77:869cf507173a 883 {
emilmont 77:869cf507173a 884 __IO uint16_t SR; /*!< USART Status register, Address offset: 0x00 */
emilmont 77:869cf507173a 885 uint16_t RESERVED0; /*!< Reserved, 0x02 */
emilmont 77:869cf507173a 886 __IO uint16_t DR; /*!< USART Data register, Address offset: 0x04 */
emilmont 77:869cf507173a 887 uint16_t RESERVED1; /*!< Reserved, 0x06 */
emilmont 77:869cf507173a 888 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x08 */
emilmont 77:869cf507173a 889 uint16_t RESERVED2; /*!< Reserved, 0x0A */
emilmont 77:869cf507173a 890 __IO uint16_t CR1; /*!< USART Control register 1, Address offset: 0x0C */
emilmont 77:869cf507173a 891 uint16_t RESERVED3; /*!< Reserved, 0x0E */
emilmont 77:869cf507173a 892 __IO uint16_t CR2; /*!< USART Control register 2, Address offset: 0x10 */
emilmont 77:869cf507173a 893 uint16_t RESERVED4; /*!< Reserved, 0x12 */
emilmont 77:869cf507173a 894 __IO uint16_t CR3; /*!< USART Control register 3, Address offset: 0x14 */
emilmont 77:869cf507173a 895 uint16_t RESERVED5; /*!< Reserved, 0x16 */
emilmont 77:869cf507173a 896 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x18 */
emilmont 77:869cf507173a 897 uint16_t RESERVED6; /*!< Reserved, 0x1A */
emilmont 77:869cf507173a 898 } USART_TypeDef;
emilmont 77:869cf507173a 899
emilmont 77:869cf507173a 900 /**
emilmont 77:869cf507173a 901 * @brief Window WATCHDOG
emilmont 77:869cf507173a 902 */
emilmont 77:869cf507173a 903
emilmont 77:869cf507173a 904 typedef struct
emilmont 77:869cf507173a 905 {
emilmont 77:869cf507173a 906 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
emilmont 77:869cf507173a 907 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
emilmont 77:869cf507173a 908 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
emilmont 77:869cf507173a 909 } WWDG_TypeDef;
emilmont 77:869cf507173a 910
emilmont 77:869cf507173a 911 /**
emilmont 77:869cf507173a 912 * @}
emilmont 77:869cf507173a 913 */
emilmont 77:869cf507173a 914
emilmont 77:869cf507173a 915 /** @addtogroup Peripheral_memory_map
emilmont 77:869cf507173a 916 * @{
emilmont 77:869cf507173a 917 */
emilmont 77:869cf507173a 918
emilmont 77:869cf507173a 919 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
emilmont 77:869cf507173a 920 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
emilmont 77:869cf507173a 921 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
emilmont 77:869cf507173a 922
emilmont 77:869cf507173a 923 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
emilmont 77:869cf507173a 924 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
emilmont 77:869cf507173a 925
emilmont 77:869cf507173a 926 #define FSMC_R_BASE ((uint32_t)0xA0000000) /*!< FSMC registers base address */
emilmont 77:869cf507173a 927
emilmont 77:869cf507173a 928 /*!< Peripheral memory map */
emilmont 77:869cf507173a 929 #define APB1PERIPH_BASE PERIPH_BASE
emilmont 77:869cf507173a 930 #define APB2PERIPH_BASE (PERIPH_BASE + 0x10000)
emilmont 77:869cf507173a 931 #define AHBPERIPH_BASE (PERIPH_BASE + 0x20000)
emilmont 77:869cf507173a 932
emilmont 77:869cf507173a 933 #define TIM2_BASE (APB1PERIPH_BASE + 0x0000)
emilmont 77:869cf507173a 934 #define TIM3_BASE (APB1PERIPH_BASE + 0x0400)
emilmont 77:869cf507173a 935 #define TIM4_BASE (APB1PERIPH_BASE + 0x0800)
emilmont 77:869cf507173a 936 #define TIM5_BASE (APB1PERIPH_BASE + 0x0C00)
emilmont 77:869cf507173a 937 #define TIM6_BASE (APB1PERIPH_BASE + 0x1000)
emilmont 77:869cf507173a 938 #define TIM7_BASE (APB1PERIPH_BASE + 0x1400)
emilmont 77:869cf507173a 939 #define LCD_BASE (APB1PERIPH_BASE + 0x2400)
emilmont 77:869cf507173a 940 #define RTC_BASE (APB1PERIPH_BASE + 0x2800)
emilmont 77:869cf507173a 941 #define WWDG_BASE (APB1PERIPH_BASE + 0x2C00)
emilmont 77:869cf507173a 942 #define IWDG_BASE (APB1PERIPH_BASE + 0x3000)
emilmont 77:869cf507173a 943 #define SPI2_BASE (APB1PERIPH_BASE + 0x3800)
emilmont 77:869cf507173a 944 #define SPI3_BASE (APB1PERIPH_BASE + 0x3C00)
emilmont 77:869cf507173a 945 #define USART2_BASE (APB1PERIPH_BASE + 0x4400)
emilmont 77:869cf507173a 946 #define USART3_BASE (APB1PERIPH_BASE + 0x4800)
emilmont 77:869cf507173a 947 #define UART4_BASE (APB1PERIPH_BASE + 0x4C00)
emilmont 77:869cf507173a 948 #define UART5_BASE (APB1PERIPH_BASE + 0x5000)
emilmont 77:869cf507173a 949 #define I2C1_BASE (APB1PERIPH_BASE + 0x5400)
emilmont 77:869cf507173a 950 #define I2C2_BASE (APB1PERIPH_BASE + 0x5800)
emilmont 77:869cf507173a 951 #define PWR_BASE (APB1PERIPH_BASE + 0x7000)
emilmont 77:869cf507173a 952 #define DAC_BASE (APB1PERIPH_BASE + 0x7400)
emilmont 77:869cf507173a 953 #define COMP_BASE (APB1PERIPH_BASE + 0x7C00)
emilmont 77:869cf507173a 954 #define RI_BASE (APB1PERIPH_BASE + 0x7C04)
emilmont 77:869cf507173a 955 #define OPAMP_BASE (APB1PERIPH_BASE + 0x7C5C)
emilmont 77:869cf507173a 956
emilmont 77:869cf507173a 957 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x0000)
emilmont 77:869cf507173a 958 #define EXTI_BASE (APB2PERIPH_BASE + 0x0400)
emilmont 77:869cf507173a 959 #define TIM9_BASE (APB2PERIPH_BASE + 0x0800)
emilmont 77:869cf507173a 960 #define TIM10_BASE (APB2PERIPH_BASE + 0x0C00)
emilmont 77:869cf507173a 961 #define TIM11_BASE (APB2PERIPH_BASE + 0x1000)
emilmont 77:869cf507173a 962 #define ADC1_BASE (APB2PERIPH_BASE + 0x2400)
emilmont 77:869cf507173a 963 #define ADC_BASE (APB2PERIPH_BASE + 0x2700)
emilmont 77:869cf507173a 964 #define SDIO_BASE (APB2PERIPH_BASE + 0x2C00)
emilmont 77:869cf507173a 965 #define SPI1_BASE (APB2PERIPH_BASE + 0x3000)
emilmont 77:869cf507173a 966 #define USART1_BASE (APB2PERIPH_BASE + 0x3800)
emilmont 77:869cf507173a 967
emilmont 77:869cf507173a 968 #define GPIOA_BASE (AHBPERIPH_BASE + 0x0000)
emilmont 77:869cf507173a 969 #define GPIOB_BASE (AHBPERIPH_BASE + 0x0400)
emilmont 77:869cf507173a 970 #define GPIOC_BASE (AHBPERIPH_BASE + 0x0800)
emilmont 77:869cf507173a 971 #define GPIOD_BASE (AHBPERIPH_BASE + 0x0C00)
emilmont 77:869cf507173a 972 #define GPIOE_BASE (AHBPERIPH_BASE + 0x1000)
emilmont 77:869cf507173a 973 #define GPIOH_BASE (AHBPERIPH_BASE + 0x1400)
emilmont 77:869cf507173a 974 #define GPIOF_BASE (AHBPERIPH_BASE + 0x1800)
emilmont 77:869cf507173a 975 #define GPIOG_BASE (AHBPERIPH_BASE + 0x1C00)
emilmont 77:869cf507173a 976 #define CRC_BASE (AHBPERIPH_BASE + 0x3000)
emilmont 77:869cf507173a 977 #define RCC_BASE (AHBPERIPH_BASE + 0x3800)
emilmont 77:869cf507173a 978
emilmont 77:869cf507173a 979
emilmont 77:869cf507173a 980 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x3C00) /*!< FLASH registers base address */
emilmont 77:869cf507173a 981 #define OB_BASE ((uint32_t)0x1FF80000) /*!< FLASH Option Bytes base address */
emilmont 77:869cf507173a 982
emilmont 77:869cf507173a 983 #define DMA1_BASE (AHBPERIPH_BASE + 0x6000)
emilmont 77:869cf507173a 984 #define DMA1_Channel1_BASE (DMA1_BASE + 0x0008)
emilmont 77:869cf507173a 985 #define DMA1_Channel2_BASE (DMA1_BASE + 0x001C)
emilmont 77:869cf507173a 986 #define DMA1_Channel3_BASE (DMA1_BASE + 0x0030)
emilmont 77:869cf507173a 987 #define DMA1_Channel4_BASE (DMA1_BASE + 0x0044)
emilmont 77:869cf507173a 988 #define DMA1_Channel5_BASE (DMA1_BASE + 0x0058)
emilmont 77:869cf507173a 989 #define DMA1_Channel6_BASE (DMA1_BASE + 0x006C)
emilmont 77:869cf507173a 990 #define DMA1_Channel7_BASE (DMA1_BASE + 0x0080)
emilmont 77:869cf507173a 991
emilmont 77:869cf507173a 992 #define DMA2_BASE (AHBPERIPH_BASE + 0x6400)
emilmont 77:869cf507173a 993 #define DMA2_Channel1_BASE (DMA2_BASE + 0x0008)
emilmont 77:869cf507173a 994 #define DMA2_Channel2_BASE (DMA2_BASE + 0x001C)
emilmont 77:869cf507173a 995 #define DMA2_Channel3_BASE (DMA2_BASE + 0x0030)
emilmont 77:869cf507173a 996 #define DMA2_Channel4_BASE (DMA2_BASE + 0x0044)
emilmont 77:869cf507173a 997 #define DMA2_Channel5_BASE (DMA2_BASE + 0x0058)
emilmont 77:869cf507173a 998
emilmont 77:869cf507173a 999 #define AES_BASE ((uint32_t)0x50060000)
emilmont 77:869cf507173a 1000
emilmont 77:869cf507173a 1001 #define FSMC_Bank1_R_BASE (FSMC_R_BASE + 0x0000) /*!< FSMC Bank1 registers base address */
emilmont 77:869cf507173a 1002 #define FSMC_Bank1E_R_BASE (FSMC_R_BASE + 0x0104) /*!< FSMC Bank1E registers base address */
emilmont 77:869cf507173a 1003
emilmont 77:869cf507173a 1004 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
emilmont 77:869cf507173a 1005
emilmont 77:869cf507173a 1006 /**
emilmont 77:869cf507173a 1007 * @}
emilmont 77:869cf507173a 1008 */
emilmont 77:869cf507173a 1009
emilmont 77:869cf507173a 1010 /** @addtogroup Peripheral_declaration
emilmont 77:869cf507173a 1011 * @{
emilmont 77:869cf507173a 1012 */
emilmont 77:869cf507173a 1013
emilmont 77:869cf507173a 1014 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
emilmont 77:869cf507173a 1015 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
emilmont 77:869cf507173a 1016 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
emilmont 77:869cf507173a 1017 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
emilmont 77:869cf507173a 1018 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
emilmont 77:869cf507173a 1019 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
emilmont 77:869cf507173a 1020 #define LCD ((LCD_TypeDef *) LCD_BASE)
emilmont 77:869cf507173a 1021 #define RTC ((RTC_TypeDef *) RTC_BASE)
emilmont 77:869cf507173a 1022 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
emilmont 77:869cf507173a 1023 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
emilmont 77:869cf507173a 1024 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
emilmont 77:869cf507173a 1025 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
emilmont 77:869cf507173a 1026 #define USART2 ((USART_TypeDef *) USART2_BASE)
emilmont 77:869cf507173a 1027 #define USART3 ((USART_TypeDef *) USART3_BASE)
emilmont 77:869cf507173a 1028 #define UART4 ((USART_TypeDef *) UART4_BASE)
emilmont 77:869cf507173a 1029 #define UART5 ((USART_TypeDef *) UART5_BASE)
emilmont 77:869cf507173a 1030 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
emilmont 77:869cf507173a 1031 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
emilmont 77:869cf507173a 1032 #define PWR ((PWR_TypeDef *) PWR_BASE)
emilmont 77:869cf507173a 1033 #define DAC ((DAC_TypeDef *) DAC_BASE)
emilmont 77:869cf507173a 1034 #define COMP ((COMP_TypeDef *) COMP_BASE)
emilmont 77:869cf507173a 1035 #define RI ((RI_TypeDef *) RI_BASE)
emilmont 77:869cf507173a 1036 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
emilmont 77:869cf507173a 1037 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
emilmont 77:869cf507173a 1038 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
emilmont 77:869cf507173a 1039
emilmont 77:869cf507173a 1040 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
emilmont 77:869cf507173a 1041 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
emilmont 77:869cf507173a 1042 #define SDIO ((SDIO_TypeDef *) SDIO_BASE)
emilmont 77:869cf507173a 1043 #define TIM9 ((TIM_TypeDef *) TIM9_BASE)
emilmont 77:869cf507173a 1044 #define TIM10 ((TIM_TypeDef *) TIM10_BASE)
emilmont 77:869cf507173a 1045 #define TIM11 ((TIM_TypeDef *) TIM11_BASE)
emilmont 77:869cf507173a 1046 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
emilmont 77:869cf507173a 1047 #define USART1 ((USART_TypeDef *) USART1_BASE)
emilmont 77:869cf507173a 1048 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
emilmont 77:869cf507173a 1049 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
emilmont 77:869cf507173a 1050 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
emilmont 77:869cf507173a 1051 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
emilmont 77:869cf507173a 1052 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
emilmont 77:869cf507173a 1053 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
emilmont 77:869cf507173a 1054 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
emilmont 77:869cf507173a 1055 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
emilmont 77:869cf507173a 1056
emilmont 77:869cf507173a 1057 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
emilmont 77:869cf507173a 1058 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
emilmont 77:869cf507173a 1059 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
emilmont 77:869cf507173a 1060 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
emilmont 77:869cf507173a 1061 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
emilmont 77:869cf507173a 1062 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
emilmont 77:869cf507173a 1063
emilmont 77:869cf507173a 1064 #define RCC ((RCC_TypeDef *) RCC_BASE)
emilmont 77:869cf507173a 1065 #define CRC ((CRC_TypeDef *) CRC_BASE)
emilmont 77:869cf507173a 1066
emilmont 77:869cf507173a 1067 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
emilmont 77:869cf507173a 1068 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
emilmont 77:869cf507173a 1069 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
emilmont 77:869cf507173a 1070 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
emilmont 77:869cf507173a 1071 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
emilmont 77:869cf507173a 1072 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
emilmont 77:869cf507173a 1073 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
emilmont 77:869cf507173a 1074 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
emilmont 77:869cf507173a 1075
emilmont 77:869cf507173a 1076 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
emilmont 77:869cf507173a 1077 #define OB ((OB_TypeDef *) OB_BASE)
emilmont 77:869cf507173a 1078
emilmont 77:869cf507173a 1079 #define AES ((AES_TypeDef *) AES_BASE)
emilmont 77:869cf507173a 1080
emilmont 77:869cf507173a 1081 #define FSMC_Bank1 ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
emilmont 77:869cf507173a 1082 #define FSMC_Bank1E ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
emilmont 77:869cf507173a 1083
emilmont 77:869cf507173a 1084 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
emilmont 77:869cf507173a 1085
emilmont 77:869cf507173a 1086 /**
emilmont 77:869cf507173a 1087 * @}
emilmont 77:869cf507173a 1088 */
emilmont 77:869cf507173a 1089
emilmont 77:869cf507173a 1090 /** @addtogroup Exported_constants
emilmont 77:869cf507173a 1091 * @{
emilmont 77:869cf507173a 1092 */
emilmont 77:869cf507173a 1093
emilmont 77:869cf507173a 1094 /** @addtogroup Peripheral_Registers_Bits_Definition
emilmont 77:869cf507173a 1095 * @{
emilmont 77:869cf507173a 1096 */
emilmont 77:869cf507173a 1097
emilmont 77:869cf507173a 1098 /******************************************************************************/
emilmont 77:869cf507173a 1099 /* Peripheral Registers Bits Definition */
emilmont 77:869cf507173a 1100 /******************************************************************************/
emilmont 77:869cf507173a 1101 /******************************************************************************/
emilmont 77:869cf507173a 1102 /* */
emilmont 77:869cf507173a 1103 /* Analog to Digital Converter (ADC) */
emilmont 77:869cf507173a 1104 /* */
emilmont 77:869cf507173a 1105 /******************************************************************************/
emilmont 77:869cf507173a 1106
emilmont 77:869cf507173a 1107 /******************** Bit definition for ADC_SR register ********************/
emilmont 77:869cf507173a 1108 #define ADC_SR_AWD ((uint32_t)0x00000001) /*!< Analog watchdog flag */
emilmont 77:869cf507173a 1109 #define ADC_SR_EOC ((uint32_t)0x00000002) /*!< End of conversion */
emilmont 77:869cf507173a 1110 #define ADC_SR_JEOC ((uint32_t)0x00000004) /*!< Injected channel end of conversion */
emilmont 77:869cf507173a 1111 #define ADC_SR_JSTRT ((uint32_t)0x00000008) /*!< Injected channel Start flag */
emilmont 77:869cf507173a 1112 #define ADC_SR_STRT ((uint32_t)0x00000010) /*!< Regular channel Start flag */
emilmont 77:869cf507173a 1113 #define ADC_SR_OVR ((uint32_t)0x00000020) /*!< Overrun flag */
emilmont 77:869cf507173a 1114 #define ADC_SR_ADONS ((uint32_t)0x00000040) /*!< ADC ON status */
emilmont 77:869cf507173a 1115 #define ADC_SR_RCNR ((uint32_t)0x00000100) /*!< Regular channel not ready flag */
emilmont 77:869cf507173a 1116 #define ADC_SR_JCNR ((uint32_t)0x00000200) /*!< Injected channel not ready flag */
emilmont 77:869cf507173a 1117
emilmont 77:869cf507173a 1118 /******************* Bit definition for ADC_CR1 register ********************/
emilmont 77:869cf507173a 1119 #define ADC_CR1_AWDCH ((uint32_t)0x0000001F) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
emilmont 77:869cf507173a 1120 #define ADC_CR1_AWDCH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1121 #define ADC_CR1_AWDCH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1122 #define ADC_CR1_AWDCH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1123 #define ADC_CR1_AWDCH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 1124 #define ADC_CR1_AWDCH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 1125
emilmont 77:869cf507173a 1126 #define ADC_CR1_EOCIE ((uint32_t)0x00000020) /*!< Interrupt enable for EOC */
emilmont 77:869cf507173a 1127 #define ADC_CR1_AWDIE ((uint32_t)0x00000040) /*!< Analog Watchdog interrupt enable */
emilmont 77:869cf507173a 1128 #define ADC_CR1_JEOCIE ((uint32_t)0x00000080) /*!< Interrupt enable for injected channels */
emilmont 77:869cf507173a 1129 #define ADC_CR1_SCAN ((uint32_t)0x00000100) /*!< Scan mode */
emilmont 77:869cf507173a 1130 #define ADC_CR1_AWDSGL ((uint32_t)0x00000200) /*!< Enable the watchdog on a single channel in scan mode */
emilmont 77:869cf507173a 1131 #define ADC_CR1_JAUTO ((uint32_t)0x00000400) /*!< Automatic injected group conversion */
emilmont 77:869cf507173a 1132 #define ADC_CR1_DISCEN ((uint32_t)0x00000800) /*!< Discontinuous mode on regular channels */
emilmont 77:869cf507173a 1133 #define ADC_CR1_JDISCEN ((uint32_t)0x00001000) /*!< Discontinuous mode on injected channels */
emilmont 77:869cf507173a 1134
emilmont 77:869cf507173a 1135 #define ADC_CR1_DISCNUM ((uint32_t)0x0000E000) /*!< DISCNUM[2:0] bits (Discontinuous mode channel count) */
emilmont 77:869cf507173a 1136 #define ADC_CR1_DISCNUM_0 ((uint32_t)0x00002000) /*!< Bit 0 */
emilmont 77:869cf507173a 1137 #define ADC_CR1_DISCNUM_1 ((uint32_t)0x00004000) /*!< Bit 1 */
emilmont 77:869cf507173a 1138 #define ADC_CR1_DISCNUM_2 ((uint32_t)0x00008000) /*!< Bit 2 */
emilmont 77:869cf507173a 1139
emilmont 77:869cf507173a 1140 #define ADC_CR1_PDD ((uint32_t)0x00010000) /*!< Power Down during Delay phase */
emilmont 77:869cf507173a 1141 #define ADC_CR1_PDI ((uint32_t)0x00020000) /*!< Power Down during Idle phase */
emilmont 77:869cf507173a 1142
emilmont 77:869cf507173a 1143 #define ADC_CR1_JAWDEN ((uint32_t)0x00400000) /*!< Analog watchdog enable on injected channels */
emilmont 77:869cf507173a 1144 #define ADC_CR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
emilmont 77:869cf507173a 1145
emilmont 77:869cf507173a 1146 #define ADC_CR1_RES ((uint32_t)0x03000000) /*!< RES[1:0] bits (Resolution) */
emilmont 77:869cf507173a 1147 #define ADC_CR1_RES_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1148 #define ADC_CR1_RES_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1149
emilmont 77:869cf507173a 1150 #define ADC_CR1_OVRIE ((uint32_t)0x04000000) /*!< Overrun interrupt enable */
emilmont 77:869cf507173a 1151
emilmont 77:869cf507173a 1152 /******************* Bit definition for ADC_CR2 register ********************/
emilmont 77:869cf507173a 1153 #define ADC_CR2_ADON ((uint32_t)0x00000001) /*!< A/D Converter ON / OFF */
emilmont 77:869cf507173a 1154 #define ADC_CR2_CONT ((uint32_t)0x00000002) /*!< Continuous Conversion */
emilmont 77:869cf507173a 1155 #define ADC_CR2_CFG ((uint32_t)0x00000004) /*!< ADC Configuration */
emilmont 77:869cf507173a 1156
emilmont 77:869cf507173a 1157 #define ADC_CR2_DELS ((uint32_t)0x00000070) /*!< DELS[2:0] bits (Delay selection) */
emilmont 77:869cf507173a 1158 #define ADC_CR2_DELS_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 1159 #define ADC_CR2_DELS_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 1160 #define ADC_CR2_DELS_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 1161
emilmont 77:869cf507173a 1162 #define ADC_CR2_DMA ((uint32_t)0x00000100) /*!< Direct Memory access mode */
emilmont 77:869cf507173a 1163 #define ADC_CR2_DDS ((uint32_t)0x00000200) /*!< DMA disable selection (Single ADC) */
emilmont 77:869cf507173a 1164 #define ADC_CR2_EOCS ((uint32_t)0x00000400) /*!< End of conversion selection */
emilmont 77:869cf507173a 1165 #define ADC_CR2_ALIGN ((uint32_t)0x00000800) /*!< Data Alignment */
emilmont 77:869cf507173a 1166
emilmont 77:869cf507173a 1167 #define ADC_CR2_JEXTSEL ((uint32_t)0x000F0000) /*!< JEXTSEL[3:0] bits (External event select for injected group) */
emilmont 77:869cf507173a 1168 #define ADC_CR2_JEXTSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 1169 #define ADC_CR2_JEXTSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 1170 #define ADC_CR2_JEXTSEL_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 1171 #define ADC_CR2_JEXTSEL_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 1172
emilmont 77:869cf507173a 1173 #define ADC_CR2_JEXTEN ((uint32_t)0x00300000) /*!< JEXTEN[1:0] bits (External Trigger Conversion mode for injected channels) */
emilmont 77:869cf507173a 1174 #define ADC_CR2_JEXTEN_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 1175 #define ADC_CR2_JEXTEN_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 1176
emilmont 77:869cf507173a 1177 #define ADC_CR2_JSWSTART ((uint32_t)0x00400000) /*!< Start Conversion of injected channels */
emilmont 77:869cf507173a 1178
emilmont 77:869cf507173a 1179 #define ADC_CR2_EXTSEL ((uint32_t)0x0F000000) /*!< EXTSEL[3:0] bits (External Event Select for regular group) */
emilmont 77:869cf507173a 1180 #define ADC_CR2_EXTSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1181 #define ADC_CR2_EXTSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1182 #define ADC_CR2_EXTSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1183 #define ADC_CR2_EXTSEL_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 1184
emilmont 77:869cf507173a 1185 #define ADC_CR2_EXTEN ((uint32_t)0x30000000) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
emilmont 77:869cf507173a 1186 #define ADC_CR2_EXTEN_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1187 #define ADC_CR2_EXTEN_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1188
emilmont 77:869cf507173a 1189 #define ADC_CR2_SWSTART ((uint32_t)0x40000000) /*!< Start Conversion of regular channels */
emilmont 77:869cf507173a 1190
emilmont 77:869cf507173a 1191 /****************** Bit definition for ADC_SMPR1 register *******************/
emilmont 77:869cf507173a 1192 #define ADC_SMPR1_SMP20 ((uint32_t)0x00000007) /*!< SMP20[2:0] bits (Channel 20 Sample time selection) */
emilmont 77:869cf507173a 1193 #define ADC_SMPR1_SMP20_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1194 #define ADC_SMPR1_SMP20_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1195 #define ADC_SMPR1_SMP20_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1196
emilmont 77:869cf507173a 1197 #define ADC_SMPR1_SMP21 ((uint32_t)0x00000038) /*!< SMP21[2:0] bits (Channel 21 Sample time selection) */
emilmont 77:869cf507173a 1198 #define ADC_SMPR1_SMP21_0 ((uint32_t)0x00000008) /*!< Bit 0 */
emilmont 77:869cf507173a 1199 #define ADC_SMPR1_SMP21_1 ((uint32_t)0x00000010) /*!< Bit 1 */
emilmont 77:869cf507173a 1200 #define ADC_SMPR1_SMP21_2 ((uint32_t)0x00000020) /*!< Bit 2 */
emilmont 77:869cf507173a 1201
emilmont 77:869cf507173a 1202 #define ADC_SMPR1_SMP22 ((uint32_t)0x000001C0) /*!< SMP22[2:0] bits (Channel 22 Sample time selection) */
emilmont 77:869cf507173a 1203 #define ADC_SMPR1_SMP22_0 ((uint32_t)0x00000040) /*!< Bit 0 */
emilmont 77:869cf507173a 1204 #define ADC_SMPR1_SMP22_1 ((uint32_t)0x00000080) /*!< Bit 1 */
emilmont 77:869cf507173a 1205 #define ADC_SMPR1_SMP22_2 ((uint32_t)0x00000100) /*!< Bit 2 */
emilmont 77:869cf507173a 1206
emilmont 77:869cf507173a 1207 #define ADC_SMPR1_SMP23 ((uint32_t)0x00000E00) /*!< SMP23[2:0] bits (Channel 23 Sample time selection) */
emilmont 77:869cf507173a 1208 #define ADC_SMPR1_SMP23_0 ((uint32_t)0x00000200) /*!< Bit 0 */
emilmont 77:869cf507173a 1209 #define ADC_SMPR1_SMP23_1 ((uint32_t)0x00000400) /*!< Bit 1 */
emilmont 77:869cf507173a 1210 #define ADC_SMPR1_SMP23_2 ((uint32_t)0x00000800) /*!< Bit 2 */
emilmont 77:869cf507173a 1211
emilmont 77:869cf507173a 1212 #define ADC_SMPR1_SMP24 ((uint32_t)0x00007000) /*!< SMP24[2:0] bits (Channel 24 Sample time selection) */
emilmont 77:869cf507173a 1213 #define ADC_SMPR1_SMP24_0 ((uint32_t)0x00001000) /*!< Bit 0 */
emilmont 77:869cf507173a 1214 #define ADC_SMPR1_SMP24_1 ((uint32_t)0x00002000) /*!< Bit 1 */
emilmont 77:869cf507173a 1215 #define ADC_SMPR1_SMP24_2 ((uint32_t)0x00004000) /*!< Bit 2 */
emilmont 77:869cf507173a 1216
emilmont 77:869cf507173a 1217 #define ADC_SMPR1_SMP25 ((uint32_t)0x00038000) /*!< SMP25[2:0] bits (Channel 25 Sample time selection) */
emilmont 77:869cf507173a 1218 #define ADC_SMPR1_SMP25_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1219 #define ADC_SMPR1_SMP25_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1220 #define ADC_SMPR1_SMP25_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1221
emilmont 77:869cf507173a 1222 #define ADC_SMPR1_SMP26 ((uint32_t)0x001C0000) /*!< SMP26[2:0] bits (Channel 26 Sample time selection) */
emilmont 77:869cf507173a 1223 #define ADC_SMPR1_SMP26_0 ((uint32_t)0x00040000) /*!< Bit 0 */
emilmont 77:869cf507173a 1224 #define ADC_SMPR1_SMP26_1 ((uint32_t)0x00080000) /*!< Bit 1 */
emilmont 77:869cf507173a 1225 #define ADC_SMPR1_SMP26_2 ((uint32_t)0x00100000) /*!< Bit 2 */
emilmont 77:869cf507173a 1226
emilmont 77:869cf507173a 1227 #define ADC_SMPR1_SMP27 ((uint32_t)0x00E00000) /*!< SMP27[2:0] bits (Channel 27 Sample time selection) */
emilmont 77:869cf507173a 1228 #define ADC_SMPR1_SMP27_0 ((uint32_t)0x00200000) /*!< Bit 0 */
emilmont 77:869cf507173a 1229 #define ADC_SMPR1_SMP27_1 ((uint32_t)0x00400000) /*!< Bit 1 */
emilmont 77:869cf507173a 1230 #define ADC_SMPR1_SMP27_2 ((uint32_t)0x00800000) /*!< Bit 2 */
emilmont 77:869cf507173a 1231
emilmont 77:869cf507173a 1232 #define ADC_SMPR1_SMP28 ((uint32_t)0x07000000) /*!< SMP28[2:0] bits (Channel 28 Sample time selection) */
emilmont 77:869cf507173a 1233 #define ADC_SMPR1_SMP28_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1234 #define ADC_SMPR1_SMP28_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1235 #define ADC_SMPR1_SMP28_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1236
emilmont 77:869cf507173a 1237 #define ADC_SMPR1_SMP29 ((uint32_t)0x38000000) /*!< SMP29[2:0] bits (Channel 29 Sample time selection) */
emilmont 77:869cf507173a 1238 #define ADC_SMPR1_SMP29_0 ((uint32_t)0x08000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1239 #define ADC_SMPR1_SMP29_1 ((uint32_t)0x10000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1240 #define ADC_SMPR1_SMP29_2 ((uint32_t)0x20000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1241
emilmont 77:869cf507173a 1242 /****************** Bit definition for ADC_SMPR2 register *******************/
emilmont 77:869cf507173a 1243 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< SMP10[2:0] bits (Channel 10 Sample time selection) */
emilmont 77:869cf507173a 1244 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1245 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1246 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1247
emilmont 77:869cf507173a 1248 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< SMP11[2:0] bits (Channel 11 Sample time selection) */
emilmont 77:869cf507173a 1249 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< Bit 0 */
emilmont 77:869cf507173a 1250 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< Bit 1 */
emilmont 77:869cf507173a 1251 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< Bit 2 */
emilmont 77:869cf507173a 1252
emilmont 77:869cf507173a 1253 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< SMP12[2:0] bits (Channel 12 Sample time selection) */
emilmont 77:869cf507173a 1254 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< Bit 0 */
emilmont 77:869cf507173a 1255 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< Bit 1 */
emilmont 77:869cf507173a 1256 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< Bit 2 */
emilmont 77:869cf507173a 1257
emilmont 77:869cf507173a 1258 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< SMP13[2:0] bits (Channel 13 Sample time selection) */
emilmont 77:869cf507173a 1259 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< Bit 0 */
emilmont 77:869cf507173a 1260 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< Bit 1 */
emilmont 77:869cf507173a 1261 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< Bit 2 */
emilmont 77:869cf507173a 1262
emilmont 77:869cf507173a 1263 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< SMP14[2:0] bits (Channel 14 Sample time selection) */
emilmont 77:869cf507173a 1264 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< Bit 0 */
emilmont 77:869cf507173a 1265 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< Bit 1 */
emilmont 77:869cf507173a 1266 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< Bit 2 */
emilmont 77:869cf507173a 1267
emilmont 77:869cf507173a 1268 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< SMP15[2:0] bits (Channel 5 Sample time selection) */
emilmont 77:869cf507173a 1269 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1270 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1271 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1272
emilmont 77:869cf507173a 1273 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< SMP16[2:0] bits (Channel 16 Sample time selection) */
emilmont 77:869cf507173a 1274 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< Bit 0 */
emilmont 77:869cf507173a 1275 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< Bit 1 */
emilmont 77:869cf507173a 1276 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< Bit 2 */
emilmont 77:869cf507173a 1277
emilmont 77:869cf507173a 1278 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< SMP17[2:0] bits (Channel 17 Sample time selection) */
emilmont 77:869cf507173a 1279 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< Bit 0 */
emilmont 77:869cf507173a 1280 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< Bit 1 */
emilmont 77:869cf507173a 1281 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< Bit 2 */
emilmont 77:869cf507173a 1282
emilmont 77:869cf507173a 1283 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< SMP18[2:0] bits (Channel 18 Sample time selection) */
emilmont 77:869cf507173a 1284 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1285 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1286 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1287
emilmont 77:869cf507173a 1288 #define ADC_SMPR2_SMP19 ((uint32_t)0x38000000) /*!< SMP19[2:0] bits (Channel 19 Sample time selection) */
emilmont 77:869cf507173a 1289 #define ADC_SMPR2_SMP19_0 ((uint32_t)0x08000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1290 #define ADC_SMPR2_SMP19_1 ((uint32_t)0x10000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1291 #define ADC_SMPR2_SMP19_2 ((uint32_t)0x20000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1292
emilmont 77:869cf507173a 1293 /****************** Bit definition for ADC_SMPR3 register *******************/
emilmont 77:869cf507173a 1294 #define ADC_SMPR3_SMP0 ((uint32_t)0x00000007) /*!< SMP0[2:0] bits (Channel 0 Sample time selection) */
emilmont 77:869cf507173a 1295 #define ADC_SMPR3_SMP0_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1296 #define ADC_SMPR3_SMP0_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1297 #define ADC_SMPR3_SMP0_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1298
emilmont 77:869cf507173a 1299 #define ADC_SMPR3_SMP1 ((uint32_t)0x00000038) /*!< SMP1[2:0] bits (Channel 1 Sample time selection) */
emilmont 77:869cf507173a 1300 #define ADC_SMPR3_SMP1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
emilmont 77:869cf507173a 1301 #define ADC_SMPR3_SMP1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
emilmont 77:869cf507173a 1302 #define ADC_SMPR3_SMP1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
emilmont 77:869cf507173a 1303
emilmont 77:869cf507173a 1304 #define ADC_SMPR3_SMP2 ((uint32_t)0x000001C0) /*!< SMP2[2:0] bits (Channel 2 Sample time selection) */
emilmont 77:869cf507173a 1305 #define ADC_SMPR3_SMP2_0 ((uint32_t)0x00000040) /*!< Bit 0 */
emilmont 77:869cf507173a 1306 #define ADC_SMPR3_SMP2_1 ((uint32_t)0x00000080) /*!< Bit 1 */
emilmont 77:869cf507173a 1307 #define ADC_SMPR3_SMP2_2 ((uint32_t)0x00000100) /*!< Bit 2 */
emilmont 77:869cf507173a 1308
emilmont 77:869cf507173a 1309 #define ADC_SMPR3_SMP3 ((uint32_t)0x00000E00) /*!< SMP3[2:0] bits (Channel 3 Sample time selection) */
emilmont 77:869cf507173a 1310 #define ADC_SMPR3_SMP3_0 ((uint32_t)0x00000200) /*!< Bit 0 */
emilmont 77:869cf507173a 1311 #define ADC_SMPR3_SMP3_1 ((uint32_t)0x00000400) /*!< Bit 1 */
emilmont 77:869cf507173a 1312 #define ADC_SMPR3_SMP3_2 ((uint32_t)0x00000800) /*!< Bit 2 */
emilmont 77:869cf507173a 1313
emilmont 77:869cf507173a 1314 #define ADC_SMPR3_SMP4 ((uint32_t)0x00007000) /*!< SMP4[2:0] bits (Channel 4 Sample time selection) */
emilmont 77:869cf507173a 1315 #define ADC_SMPR3_SMP4_0 ((uint32_t)0x00001000) /*!< Bit 0 */
emilmont 77:869cf507173a 1316 #define ADC_SMPR3_SMP4_1 ((uint32_t)0x00002000) /*!< Bit 1 */
emilmont 77:869cf507173a 1317 #define ADC_SMPR3_SMP4_2 ((uint32_t)0x00004000) /*!< Bit 2 */
emilmont 77:869cf507173a 1318
emilmont 77:869cf507173a 1319 #define ADC_SMPR3_SMP5 ((uint32_t)0x00038000) /*!< SMP5[2:0] bits (Channel 5 Sample time selection) */
emilmont 77:869cf507173a 1320 #define ADC_SMPR3_SMP5_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1321 #define ADC_SMPR3_SMP5_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1322 #define ADC_SMPR3_SMP5_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1323
emilmont 77:869cf507173a 1324 #define ADC_SMPR3_SMP6 ((uint32_t)0x001C0000) /*!< SMP6[2:0] bits (Channel 6 Sample time selection) */
emilmont 77:869cf507173a 1325 #define ADC_SMPR3_SMP6_0 ((uint32_t)0x00040000) /*!< Bit 0 */
emilmont 77:869cf507173a 1326 #define ADC_SMPR3_SMP6_1 ((uint32_t)0x00080000) /*!< Bit 1 */
emilmont 77:869cf507173a 1327 #define ADC_SMPR3_SMP6_2 ((uint32_t)0x00100000) /*!< Bit 2 */
emilmont 77:869cf507173a 1328
emilmont 77:869cf507173a 1329 #define ADC_SMPR3_SMP7 ((uint32_t)0x00E00000) /*!< SMP7[2:0] bits (Channel 7 Sample time selection) */
emilmont 77:869cf507173a 1330 #define ADC_SMPR3_SMP7_0 ((uint32_t)0x00200000) /*!< Bit 0 */
emilmont 77:869cf507173a 1331 #define ADC_SMPR3_SMP7_1 ((uint32_t)0x00400000) /*!< Bit 1 */
emilmont 77:869cf507173a 1332 #define ADC_SMPR3_SMP7_2 ((uint32_t)0x00800000) /*!< Bit 2 */
emilmont 77:869cf507173a 1333
emilmont 77:869cf507173a 1334 #define ADC_SMPR3_SMP8 ((uint32_t)0x07000000) /*!< SMP8[2:0] bits (Channel 8 Sample time selection) */
emilmont 77:869cf507173a 1335 #define ADC_SMPR3_SMP8_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1336 #define ADC_SMPR3_SMP8_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1337 #define ADC_SMPR3_SMP8_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1338
emilmont 77:869cf507173a 1339 #define ADC_SMPR3_SMP9 ((uint32_t)0x38000000) /*!< SMP9[2:0] bits (Channel 9 Sample time selection) */
emilmont 77:869cf507173a 1340 #define ADC_SMPR3_SMP9_0 ((uint32_t)0x08000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1341 #define ADC_SMPR3_SMP9_1 ((uint32_t)0x10000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1342 #define ADC_SMPR3_SMP9_2 ((uint32_t)0x20000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1343
emilmont 77:869cf507173a 1344 /****************** Bit definition for ADC_JOFR1 register *******************/
emilmont 77:869cf507173a 1345 #define ADC_JOFR1_JOFFSET1 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 1 */
emilmont 77:869cf507173a 1346
emilmont 77:869cf507173a 1347 /****************** Bit definition for ADC_JOFR2 register *******************/
emilmont 77:869cf507173a 1348 #define ADC_JOFR2_JOFFSET2 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 2 */
emilmont 77:869cf507173a 1349
emilmont 77:869cf507173a 1350 /****************** Bit definition for ADC_JOFR3 register *******************/
emilmont 77:869cf507173a 1351 #define ADC_JOFR3_JOFFSET3 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 3 */
emilmont 77:869cf507173a 1352
emilmont 77:869cf507173a 1353 /****************** Bit definition for ADC_JOFR4 register *******************/
emilmont 77:869cf507173a 1354 #define ADC_JOFR4_JOFFSET4 ((uint32_t)0x00000FFF) /*!< Data offset for injected channel 4 */
emilmont 77:869cf507173a 1355
emilmont 77:869cf507173a 1356 /******************* Bit definition for ADC_HTR register ********************/
emilmont 77:869cf507173a 1357 #define ADC_HTR_HT ((uint32_t)0x00000FFF) /*!< Analog watchdog high threshold */
emilmont 77:869cf507173a 1358
emilmont 77:869cf507173a 1359 /******************* Bit definition for ADC_LTR register ********************/
emilmont 77:869cf507173a 1360 #define ADC_LTR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
emilmont 77:869cf507173a 1361
emilmont 77:869cf507173a 1362 /******************* Bit definition for ADC_SQR1 register *******************/
emilmont 77:869cf507173a 1363 #define ADC_SQR1_L ((uint32_t)0x00F00000) /*!< L[3:0] bits (Regular channel sequence length) */
emilmont 77:869cf507173a 1364 #define ADC_SQR1_L_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 1365 #define ADC_SQR1_L_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 1366 #define ADC_SQR1_L_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 1367 #define ADC_SQR1_L_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 1368
emilmont 77:869cf507173a 1369 #define ADC_SQR1_SQ28 ((uint32_t)0x000F8000) /*!< SQ28[4:0] bits (25th conversion in regular sequence) */
emilmont 77:869cf507173a 1370 #define ADC_SQR1_SQ28_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1371 #define ADC_SQR1_SQ28_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1372 #define ADC_SQR1_SQ28_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1373 #define ADC_SQR1_SQ28_3 ((uint32_t)0x00040000) /*!< Bit 3 */
emilmont 77:869cf507173a 1374 #define ADC_SQR1_SQ28_4 ((uint32_t)0x00080000) /*!< Bit 4 */
emilmont 77:869cf507173a 1375
emilmont 77:869cf507173a 1376 #define ADC_SQR1_SQ27 ((uint32_t)0x00007C00) /*!< SQ27[4:0] bits (27th conversion in regular sequence) */
emilmont 77:869cf507173a 1377 #define ADC_SQR1_SQ27_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 1378 #define ADC_SQR1_SQ27_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 1379 #define ADC_SQR1_SQ27_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 1380 #define ADC_SQR1_SQ27_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 1381 #define ADC_SQR1_SQ27_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 1382
emilmont 77:869cf507173a 1383 #define ADC_SQR1_SQ26 ((uint32_t)0x000003E0) /*!< SQ26[4:0] bits (26th conversion in regular sequence) */
emilmont 77:869cf507173a 1384 #define ADC_SQR1_SQ26_0 ((uint32_t)0x00000020) /*!< Bit 0 */
emilmont 77:869cf507173a 1385 #define ADC_SQR1_SQ26_1 ((uint32_t)0x00000040) /*!< Bit 1 */
emilmont 77:869cf507173a 1386 #define ADC_SQR1_SQ26_2 ((uint32_t)0x00000080) /*!< Bit 2 */
emilmont 77:869cf507173a 1387 #define ADC_SQR1_SQ26_3 ((uint32_t)0x00000100) /*!< Bit 3 */
emilmont 77:869cf507173a 1388 #define ADC_SQR1_SQ26_4 ((uint32_t)0x00000200) /*!< Bit 4 */
emilmont 77:869cf507173a 1389
emilmont 77:869cf507173a 1390 #define ADC_SQR1_SQ25 ((uint32_t)0x0000001F) /*!< SQ25[4:0] bits (25th conversion in regular sequence) */
emilmont 77:869cf507173a 1391 #define ADC_SQR1_SQ25_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1392 #define ADC_SQR1_SQ25_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1393 #define ADC_SQR1_SQ25_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1394 #define ADC_SQR1_SQ25_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 1395 #define ADC_SQR1_SQ25_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 1396
emilmont 77:869cf507173a 1397 /******************* Bit definition for ADC_SQR2 register *******************/
emilmont 77:869cf507173a 1398 #define ADC_SQR2_SQ19 ((uint32_t)0x0000001F) /*!< SQ19[4:0] bits (19th conversion in regular sequence) */
emilmont 77:869cf507173a 1399 #define ADC_SQR2_SQ19_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1400 #define ADC_SQR2_SQ19_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1401 #define ADC_SQR2_SQ19_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1402 #define ADC_SQR2_SQ19_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 1403 #define ADC_SQR2_SQ19_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 1404
emilmont 77:869cf507173a 1405 #define ADC_SQR2_SQ20 ((uint32_t)0x000003E0) /*!< SQ20[4:0] bits (20th conversion in regular sequence) */
emilmont 77:869cf507173a 1406 #define ADC_SQR2_SQ20_0 ((uint32_t)0x00000020) /*!< Bit 0 */
emilmont 77:869cf507173a 1407 #define ADC_SQR2_SQ20_1 ((uint32_t)0x00000040) /*!< Bit 1 */
emilmont 77:869cf507173a 1408 #define ADC_SQR2_SQ20_2 ((uint32_t)0x00000080) /*!< Bit 2 */
emilmont 77:869cf507173a 1409 #define ADC_SQR2_SQ20_3 ((uint32_t)0x00000100) /*!< Bit 3 */
emilmont 77:869cf507173a 1410 #define ADC_SQR2_SQ20_4 ((uint32_t)0x00000200) /*!< Bit 4 */
emilmont 77:869cf507173a 1411
emilmont 77:869cf507173a 1412 #define ADC_SQR2_SQ21 ((uint32_t)0x00007C00) /*!< SQ21[4:0] bits (21th conversion in regular sequence) */
emilmont 77:869cf507173a 1413 #define ADC_SQR2_SQ21_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 1414 #define ADC_SQR2_SQ21_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 1415 #define ADC_SQR2_SQ21_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 1416 #define ADC_SQR2_SQ21_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 1417 #define ADC_SQR2_SQ21_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 1418
emilmont 77:869cf507173a 1419 #define ADC_SQR2_SQ22 ((uint32_t)0x000F8000) /*!< SQ22[4:0] bits (22th conversion in regular sequence) */
emilmont 77:869cf507173a 1420 #define ADC_SQR2_SQ22_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1421 #define ADC_SQR2_SQ22_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1422 #define ADC_SQR2_SQ22_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1423 #define ADC_SQR2_SQ22_3 ((uint32_t)0x00040000) /*!< Bit 3 */
emilmont 77:869cf507173a 1424 #define ADC_SQR2_SQ22_4 ((uint32_t)0x00080000) /*!< Bit 4 */
emilmont 77:869cf507173a 1425
emilmont 77:869cf507173a 1426 #define ADC_SQR2_SQ23 ((uint32_t)0x01F00000) /*!< SQ23[4:0] bits (23th conversion in regular sequence) */
emilmont 77:869cf507173a 1427 #define ADC_SQR2_SQ23_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 1428 #define ADC_SQR2_SQ23_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 1429 #define ADC_SQR2_SQ23_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 1430 #define ADC_SQR2_SQ23_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 1431 #define ADC_SQR2_SQ23_4 ((uint32_t)0x01000000) /*!< Bit 4 */
emilmont 77:869cf507173a 1432
emilmont 77:869cf507173a 1433 #define ADC_SQR2_SQ24 ((uint32_t)0x3E000000) /*!< SQ24[4:0] bits (24th conversion in regular sequence) */
emilmont 77:869cf507173a 1434 #define ADC_SQR2_SQ24_0 ((uint32_t)0x02000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1435 #define ADC_SQR2_SQ24_1 ((uint32_t)0x04000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1436 #define ADC_SQR2_SQ24_2 ((uint32_t)0x08000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1437 #define ADC_SQR2_SQ24_3 ((uint32_t)0x10000000) /*!< Bit 3 */
emilmont 77:869cf507173a 1438 #define ADC_SQR2_SQ24_4 ((uint32_t)0x20000000) /*!< Bit 4 */
emilmont 77:869cf507173a 1439
emilmont 77:869cf507173a 1440 /******************* Bit definition for ADC_SQR3 register *******************/
emilmont 77:869cf507173a 1441 #define ADC_SQR3_SQ13 ((uint32_t)0x0000001F) /*!< SQ13[4:0] bits (13th conversion in regular sequence) */
emilmont 77:869cf507173a 1442 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1443 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1444 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1445 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 1446 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 1447
emilmont 77:869cf507173a 1448 #define ADC_SQR3_SQ14 ((uint32_t)0x000003E0) /*!< SQ14[4:0] bits (14th conversion in regular sequence) */
emilmont 77:869cf507173a 1449 #define ADC_SQR3_SQ14_0 ((uint32_t)0x00000020) /*!< Bit 0 */
emilmont 77:869cf507173a 1450 #define ADC_SQR3_SQ14_1 ((uint32_t)0x00000040) /*!< Bit 1 */
emilmont 77:869cf507173a 1451 #define ADC_SQR3_SQ14_2 ((uint32_t)0x00000080) /*!< Bit 2 */
emilmont 77:869cf507173a 1452 #define ADC_SQR3_SQ14_3 ((uint32_t)0x00000100) /*!< Bit 3 */
emilmont 77:869cf507173a 1453 #define ADC_SQR3_SQ14_4 ((uint32_t)0x00000200) /*!< Bit 4 */
emilmont 77:869cf507173a 1454
emilmont 77:869cf507173a 1455 #define ADC_SQR3_SQ15 ((uint32_t)0x00007C00) /*!< SQ15[4:0] bits (15th conversion in regular sequence) */
emilmont 77:869cf507173a 1456 #define ADC_SQR3_SQ15_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 1457 #define ADC_SQR3_SQ15_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 1458 #define ADC_SQR3_SQ15_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 1459 #define ADC_SQR3_SQ15_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 1460 #define ADC_SQR3_SQ15_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 1461
emilmont 77:869cf507173a 1462 #define ADC_SQR3_SQ16 ((uint32_t)0x000F8000) /*!< SQ16[4:0] bits (16th conversion in regular sequence) */
emilmont 77:869cf507173a 1463 #define ADC_SQR3_SQ16_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1464 #define ADC_SQR3_SQ16_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1465 #define ADC_SQR3_SQ16_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1466 #define ADC_SQR3_SQ16_3 ((uint32_t)0x00040000) /*!< Bit 3 */
emilmont 77:869cf507173a 1467 #define ADC_SQR3_SQ16_4 ((uint32_t)0x00080000) /*!< Bit 4 */
emilmont 77:869cf507173a 1468
emilmont 77:869cf507173a 1469 #define ADC_SQR3_SQ17 ((uint32_t)0x01F00000) /*!< SQ17[4:0] bits (17th conversion in regular sequence) */
emilmont 77:869cf507173a 1470 #define ADC_SQR3_SQ17_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 1471 #define ADC_SQR3_SQ17_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 1472 #define ADC_SQR3_SQ17_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 1473 #define ADC_SQR3_SQ17_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 1474 #define ADC_SQR3_SQ17_4 ((uint32_t)0x01000000) /*!< Bit 4 */
emilmont 77:869cf507173a 1475
emilmont 77:869cf507173a 1476 #define ADC_SQR3_SQ18 ((uint32_t)0x3E000000) /*!< SQ18[4:0] bits (18th conversion in regular sequence) */
emilmont 77:869cf507173a 1477 #define ADC_SQR3_SQ18_0 ((uint32_t)0x02000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1478 #define ADC_SQR3_SQ18_1 ((uint32_t)0x04000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1479 #define ADC_SQR3_SQ18_2 ((uint32_t)0x08000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1480 #define ADC_SQR3_SQ18_3 ((uint32_t)0x10000000) /*!< Bit 3 */
emilmont 77:869cf507173a 1481 #define ADC_SQR3_SQ18_4 ((uint32_t)0x20000000) /*!< Bit 4 */
emilmont 77:869cf507173a 1482
emilmont 77:869cf507173a 1483 /******************* Bit definition for ADC_SQR4 register *******************/
emilmont 77:869cf507173a 1484 #define ADC_SQR4_SQ7 ((uint32_t)0x0000001F) /*!< SQ7[4:0] bits (7th conversion in regular sequence) */
emilmont 77:869cf507173a 1485 #define ADC_SQR4_SQ7_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1486 #define ADC_SQR4_SQ7_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1487 #define ADC_SQR4_SQ7_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1488 #define ADC_SQR4_SQ7_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 1489 #define ADC_SQR4_SQ7_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 1490
emilmont 77:869cf507173a 1491 #define ADC_SQR4_SQ8 ((uint32_t)0x000003E0) /*!< SQ8[4:0] bits (8th conversion in regular sequence) */
emilmont 77:869cf507173a 1492 #define ADC_SQR4_SQ8_0 ((uint32_t)0x00000020) /*!< Bit 0 */
emilmont 77:869cf507173a 1493 #define ADC_SQR4_SQ8_1 ((uint32_t)0x00000040) /*!< Bit 1 */
emilmont 77:869cf507173a 1494 #define ADC_SQR4_SQ8_2 ((uint32_t)0x00000080) /*!< Bit 2 */
emilmont 77:869cf507173a 1495 #define ADC_SQR4_SQ8_3 ((uint32_t)0x00000100) /*!< Bit 3 */
emilmont 77:869cf507173a 1496 #define ADC_SQR4_SQ8_4 ((uint32_t)0x00000200) /*!< Bit 4 */
emilmont 77:869cf507173a 1497
emilmont 77:869cf507173a 1498 #define ADC_SQR4_SQ9 ((uint32_t)0x00007C00) /*!< SQ9[4:0] bits (9th conversion in regular sequence) */
emilmont 77:869cf507173a 1499 #define ADC_SQR4_SQ9_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 1500 #define ADC_SQR4_SQ9_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 1501 #define ADC_SQR4_SQ9_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 1502 #define ADC_SQR4_SQ9_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 1503 #define ADC_SQR4_SQ9_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 1504
emilmont 77:869cf507173a 1505 #define ADC_SQR4_SQ10 ((uint32_t)0x000F8000) /*!< SQ10[4:0] bits (10th conversion in regular sequence) */
emilmont 77:869cf507173a 1506 #define ADC_SQR4_SQ10_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1507 #define ADC_SQR4_SQ10_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1508 #define ADC_SQR4_SQ10_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1509 #define ADC_SQR4_SQ10_3 ((uint32_t)0x00040000) /*!< Bit 3 */
emilmont 77:869cf507173a 1510 #define ADC_SQR4_SQ10_4 ((uint32_t)0x00080000) /*!< Bit 4 */
emilmont 77:869cf507173a 1511
emilmont 77:869cf507173a 1512 #define ADC_SQR4_SQ11 ((uint32_t)0x01F00000) /*!< SQ11[4:0] bits (11th conversion in regular sequence) */
emilmont 77:869cf507173a 1513 #define ADC_SQR4_SQ11_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 1514 #define ADC_SQR4_SQ11_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 1515 #define ADC_SQR4_SQ11_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 1516 #define ADC_SQR4_SQ11_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 1517 #define ADC_SQR4_SQ11_4 ((uint32_t)0x01000000) /*!< Bit 4 */
emilmont 77:869cf507173a 1518
emilmont 77:869cf507173a 1519 #define ADC_SQR4_SQ12 ((uint32_t)0x3E000000) /*!< SQ12[4:0] bits (12th conversion in regular sequence) */
emilmont 77:869cf507173a 1520 #define ADC_SQR4_SQ12_0 ((uint32_t)0x02000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1521 #define ADC_SQR4_SQ12_1 ((uint32_t)0x04000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1522 #define ADC_SQR4_SQ12_2 ((uint32_t)0x08000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1523 #define ADC_SQR4_SQ12_3 ((uint32_t)0x10000000) /*!< Bit 3 */
emilmont 77:869cf507173a 1524 #define ADC_SQR4_SQ12_4 ((uint32_t)0x20000000) /*!< Bit 4 */
emilmont 77:869cf507173a 1525
emilmont 77:869cf507173a 1526 /******************* Bit definition for ADC_SQR5 register *******************/
emilmont 77:869cf507173a 1527 #define ADC_SQR5_SQ1 ((uint32_t)0x0000001F) /*!< SQ1[4:0] bits (1st conversion in regular sequence) */
emilmont 77:869cf507173a 1528 #define ADC_SQR5_SQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1529 #define ADC_SQR5_SQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1530 #define ADC_SQR5_SQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1531 #define ADC_SQR5_SQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 1532 #define ADC_SQR5_SQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 1533
emilmont 77:869cf507173a 1534 #define ADC_SQR5_SQ2 ((uint32_t)0x000003E0) /*!< SQ2[4:0] bits (2nd conversion in regular sequence) */
emilmont 77:869cf507173a 1535 #define ADC_SQR5_SQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
emilmont 77:869cf507173a 1536 #define ADC_SQR5_SQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
emilmont 77:869cf507173a 1537 #define ADC_SQR5_SQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
emilmont 77:869cf507173a 1538 #define ADC_SQR5_SQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
emilmont 77:869cf507173a 1539 #define ADC_SQR5_SQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
emilmont 77:869cf507173a 1540
emilmont 77:869cf507173a 1541 #define ADC_SQR5_SQ3 ((uint32_t)0x00007C00) /*!< SQ3[4:0] bits (3rd conversion in regular sequence) */
emilmont 77:869cf507173a 1542 #define ADC_SQR5_SQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 1543 #define ADC_SQR5_SQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 1544 #define ADC_SQR5_SQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 1545 #define ADC_SQR5_SQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 1546 #define ADC_SQR5_SQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 1547
emilmont 77:869cf507173a 1548 #define ADC_SQR5_SQ4 ((uint32_t)0x000F8000) /*!< SQ4[4:0] bits (4th conversion in regular sequence) */
emilmont 77:869cf507173a 1549 #define ADC_SQR5_SQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1550 #define ADC_SQR5_SQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1551 #define ADC_SQR5_SQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1552 #define ADC_SQR5_SQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
emilmont 77:869cf507173a 1553 #define ADC_SQR5_SQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
emilmont 77:869cf507173a 1554
emilmont 77:869cf507173a 1555 #define ADC_SQR5_SQ5 ((uint32_t)0x01F00000) /*!< SQ5[4:0] bits (5th conversion in regular sequence) */
emilmont 77:869cf507173a 1556 #define ADC_SQR5_SQ5_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 1557 #define ADC_SQR5_SQ5_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 1558 #define ADC_SQR5_SQ5_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 1559 #define ADC_SQR5_SQ5_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 1560 #define ADC_SQR5_SQ5_4 ((uint32_t)0x01000000) /*!< Bit 4 */
emilmont 77:869cf507173a 1561
emilmont 77:869cf507173a 1562 #define ADC_SQR5_SQ6 ((uint32_t)0x3E000000) /*!< SQ6[4:0] bits (6th conversion in regular sequence) */
emilmont 77:869cf507173a 1563 #define ADC_SQR5_SQ6_0 ((uint32_t)0x02000000) /*!< Bit 0 */
emilmont 77:869cf507173a 1564 #define ADC_SQR5_SQ6_1 ((uint32_t)0x04000000) /*!< Bit 1 */
emilmont 77:869cf507173a 1565 #define ADC_SQR5_SQ6_2 ((uint32_t)0x08000000) /*!< Bit 2 */
emilmont 77:869cf507173a 1566 #define ADC_SQR5_SQ6_3 ((uint32_t)0x10000000) /*!< Bit 3 */
emilmont 77:869cf507173a 1567 #define ADC_SQR5_SQ6_4 ((uint32_t)0x20000000) /*!< Bit 4 */
emilmont 77:869cf507173a 1568
emilmont 77:869cf507173a 1569
emilmont 77:869cf507173a 1570 /******************* Bit definition for ADC_JSQR register *******************/
emilmont 77:869cf507173a 1571 #define ADC_JSQR_JSQ1 ((uint32_t)0x0000001F) /*!< JSQ1[4:0] bits (1st conversion in injected sequence) */
emilmont 77:869cf507173a 1572 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1573 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1574 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1575 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 1576 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 1577
emilmont 77:869cf507173a 1578 #define ADC_JSQR_JSQ2 ((uint32_t)0x000003E0) /*!< JSQ2[4:0] bits (2nd conversion in injected sequence) */
emilmont 77:869cf507173a 1579 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00000020) /*!< Bit 0 */
emilmont 77:869cf507173a 1580 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00000040) /*!< Bit 1 */
emilmont 77:869cf507173a 1581 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00000080) /*!< Bit 2 */
emilmont 77:869cf507173a 1582 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00000100) /*!< Bit 3 */
emilmont 77:869cf507173a 1583 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00000200) /*!< Bit 4 */
emilmont 77:869cf507173a 1584
emilmont 77:869cf507173a 1585 #define ADC_JSQR_JSQ3 ((uint32_t)0x00007C00) /*!< JSQ3[4:0] bits (3rd conversion in injected sequence) */
emilmont 77:869cf507173a 1586 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 1587 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 1588 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 1589 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 1590 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 1591
emilmont 77:869cf507173a 1592 #define ADC_JSQR_JSQ4 ((uint32_t)0x000F8000) /*!< JSQ4[4:0] bits (4th conversion in injected sequence) */
emilmont 77:869cf507173a 1593 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x00008000) /*!< Bit 0 */
emilmont 77:869cf507173a 1594 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x00010000) /*!< Bit 1 */
emilmont 77:869cf507173a 1595 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x00020000) /*!< Bit 2 */
emilmont 77:869cf507173a 1596 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x00040000) /*!< Bit 3 */
emilmont 77:869cf507173a 1597 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x00080000) /*!< Bit 4 */
emilmont 77:869cf507173a 1598
emilmont 77:869cf507173a 1599 #define ADC_JSQR_JL ((uint32_t)0x00300000) /*!< JL[1:0] bits (Injected Sequence length) */
emilmont 77:869cf507173a 1600 #define ADC_JSQR_JL_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 1601 #define ADC_JSQR_JL_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 1602
emilmont 77:869cf507173a 1603 /******************* Bit definition for ADC_JDR1 register *******************/
emilmont 77:869cf507173a 1604 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
emilmont 77:869cf507173a 1605
emilmont 77:869cf507173a 1606 /******************* Bit definition for ADC_JDR2 register *******************/
emilmont 77:869cf507173a 1607 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
emilmont 77:869cf507173a 1608
emilmont 77:869cf507173a 1609 /******************* Bit definition for ADC_JDR3 register *******************/
emilmont 77:869cf507173a 1610 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
emilmont 77:869cf507173a 1611
emilmont 77:869cf507173a 1612 /******************* Bit definition for ADC_JDR4 register *******************/
emilmont 77:869cf507173a 1613 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< Injected data */
emilmont 77:869cf507173a 1614
emilmont 77:869cf507173a 1615 /******************** Bit definition for ADC_DR register ********************/
emilmont 77:869cf507173a 1616 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
emilmont 77:869cf507173a 1617
emilmont 77:869cf507173a 1618 /****************** Bit definition for ADC_SMPR0 register *******************/
emilmont 77:869cf507173a 1619 #define ADC_SMPR3_SMP30 ((uint32_t)0x00000007) /*!< SMP30[2:0] bits (Channel 30 Sample time selection) */
emilmont 77:869cf507173a 1620 #define ADC_SMPR3_SMP30_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 1621 #define ADC_SMPR3_SMP30_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 1622 #define ADC_SMPR3_SMP30_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 1623
emilmont 77:869cf507173a 1624 #define ADC_SMPR3_SMP31 ((uint32_t)0x00000038) /*!< SMP31[2:0] bits (Channel 31 Sample time selection) */
emilmont 77:869cf507173a 1625 #define ADC_SMPR3_SMP31_0 ((uint32_t)0x00000008) /*!< Bit 0 */
emilmont 77:869cf507173a 1626 #define ADC_SMPR3_SMP31_1 ((uint32_t)0x00000010) /*!< Bit 1 */
emilmont 77:869cf507173a 1627 #define ADC_SMPR3_SMP31_2 ((uint32_t)0x00000020) /*!< Bit 2 */
emilmont 77:869cf507173a 1628
emilmont 77:869cf507173a 1629 /******************* Bit definition for ADC_CSR register ********************/
emilmont 77:869cf507173a 1630 #define ADC_CSR_AWD1 ((uint32_t)0x00000001) /*!< ADC1 Analog watchdog flag */
emilmont 77:869cf507173a 1631 #define ADC_CSR_EOC1 ((uint32_t)0x00000002) /*!< ADC1 End of conversion */
emilmont 77:869cf507173a 1632 #define ADC_CSR_JEOC1 ((uint32_t)0x00000004) /*!< ADC1 Injected channel end of conversion */
emilmont 77:869cf507173a 1633 #define ADC_CSR_JSTRT1 ((uint32_t)0x00000008) /*!< ADC1 Injected channel Start flag */
emilmont 77:869cf507173a 1634 #define ADC_CSR_STRT1 ((uint32_t)0x00000010) /*!< ADC1 Regular channel Start flag */
emilmont 77:869cf507173a 1635 #define ADC_CSR_OVR1 ((uint32_t)0x00000020) /*!< ADC1 overrun flag */
emilmont 77:869cf507173a 1636 #define ADC_CSR_ADONS1 ((uint32_t)0x00000040) /*!< ADON status of ADC1 */
emilmont 77:869cf507173a 1637
emilmont 77:869cf507173a 1638 /******************* Bit definition for ADC_CCR register ********************/
emilmont 77:869cf507173a 1639 #define ADC_CCR_ADCPRE ((uint32_t)0x00030000) /*!< ADC prescaler*/
emilmont 77:869cf507173a 1640 #define ADC_CCR_ADCPRE_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 1641 #define ADC_CCR_ADCPRE_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 1642 #define ADC_CCR_TSVREFE ((uint32_t)0x00800000) /*!< Temperature Sensor and VREFINT Enable */
emilmont 77:869cf507173a 1643
emilmont 77:869cf507173a 1644 /******************************************************************************/
emilmont 77:869cf507173a 1645 /* */
emilmont 77:869cf507173a 1646 /* Advanced Encryption Standard (AES) */
emilmont 77:869cf507173a 1647 /* */
emilmont 77:869cf507173a 1648 /******************************************************************************/
emilmont 77:869cf507173a 1649 /******************* Bit definition for AES_CR register *********************/
emilmont 77:869cf507173a 1650 #define AES_CR_EN ((uint32_t)0x00000001) /*!< AES Enable */
emilmont 77:869cf507173a 1651 #define AES_CR_DATATYPE ((uint32_t)0x00000006) /*!< Data type selection */
emilmont 77:869cf507173a 1652 #define AES_CR_DATATYPE_0 ((uint32_t)0x00000002) /*!< Bit 0 */
emilmont 77:869cf507173a 1653 #define AES_CR_DATATYPE_1 ((uint32_t)0x00000004) /*!< Bit 1 */
emilmont 77:869cf507173a 1654
emilmont 77:869cf507173a 1655 #define AES_CR_MODE ((uint32_t)0x00000018) /*!< AES Mode Of Operation */
emilmont 77:869cf507173a 1656 #define AES_CR_MODE_0 ((uint32_t)0x00000008) /*!< Bit 0 */
emilmont 77:869cf507173a 1657 #define AES_CR_MODE_1 ((uint32_t)0x00000010) /*!< Bit 1 */
emilmont 77:869cf507173a 1658
emilmont 77:869cf507173a 1659 #define AES_CR_CHMOD ((uint32_t)0x00000060) /*!< AES Chaining Mode */
emilmont 77:869cf507173a 1660 #define AES_CR_CHMOD_0 ((uint32_t)0x00000020) /*!< Bit 0 */
emilmont 77:869cf507173a 1661 #define AES_CR_CHMOD_1 ((uint32_t)0x00000040) /*!< Bit 1 */
emilmont 77:869cf507173a 1662
emilmont 77:869cf507173a 1663 #define AES_CR_CCFC ((uint32_t)0x00000080) /*!< Computation Complete Flag Clear */
emilmont 77:869cf507173a 1664 #define AES_CR_ERRC ((uint32_t)0x00000100) /*!< Error Clear */
emilmont 77:869cf507173a 1665 #define AES_CR_CCIE ((uint32_t)0x00000200) /*!< Computation Complete Interrupt Enable */
emilmont 77:869cf507173a 1666 #define AES_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
emilmont 77:869cf507173a 1667 #define AES_CR_DMAINEN ((uint32_t)0x00000800) /*!< DMA ENable managing the data input phase */
emilmont 77:869cf507173a 1668 #define AES_CR_DMAOUTEN ((uint32_t)0x00001000) /*!< DMA Enable managing the data output phase */
emilmont 77:869cf507173a 1669
emilmont 77:869cf507173a 1670 /******************* Bit definition for AES_SR register *********************/
emilmont 77:869cf507173a 1671 #define AES_SR_CCF ((uint32_t)0x00000001) /*!< Computation Complete Flag */
emilmont 77:869cf507173a 1672 #define AES_SR_RDERR ((uint32_t)0x00000002) /*!< Read Error Flag */
emilmont 77:869cf507173a 1673 #define AES_SR_WRERR ((uint32_t)0x00000004) /*!< Write Error Flag */
emilmont 77:869cf507173a 1674
emilmont 77:869cf507173a 1675 /******************* Bit definition for AES_DINR register *******************/
emilmont 77:869cf507173a 1676 #define AES_DINR ((uint32_t)0x0000FFFF) /*!< AES Data Input Register */
emilmont 77:869cf507173a 1677
emilmont 77:869cf507173a 1678 /******************* Bit definition for AES_DOUTR register ******************/
emilmont 77:869cf507173a 1679 #define AES_DOUTR ((uint32_t)0x0000FFFF) /*!< AES Data Output Register */
emilmont 77:869cf507173a 1680
emilmont 77:869cf507173a 1681 /******************* Bit definition for AES_KEYR0 register ******************/
emilmont 77:869cf507173a 1682 #define AES_KEYR0 ((uint32_t)0x0000FFFF) /*!< AES Key Register 0 */
emilmont 77:869cf507173a 1683
emilmont 77:869cf507173a 1684 /******************* Bit definition for AES_KEYR1 register ******************/
emilmont 77:869cf507173a 1685 #define AES_KEYR1 ((uint32_t)0x0000FFFF) /*!< AES Key Register 1 */
emilmont 77:869cf507173a 1686
emilmont 77:869cf507173a 1687 /******************* Bit definition for AES_KEYR2 register ******************/
emilmont 77:869cf507173a 1688 #define AES_KEYR2 ((uint32_t)0x0000FFFF) /*!< AES Key Register 2 */
emilmont 77:869cf507173a 1689
emilmont 77:869cf507173a 1690 /******************* Bit definition for AES_KEYR3 register ******************/
emilmont 77:869cf507173a 1691 #define AES_KEYR3 ((uint32_t)0x0000FFFF) /*!< AES Key Register 3 */
emilmont 77:869cf507173a 1692
emilmont 77:869cf507173a 1693 /******************* Bit definition for AES_IVR0 register *******************/
emilmont 77:869cf507173a 1694 #define AES_IVR0 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 0 */
emilmont 77:869cf507173a 1695
emilmont 77:869cf507173a 1696 /******************* Bit definition for AES_IVR1 register *******************/
emilmont 77:869cf507173a 1697 #define AES_IVR1 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 1 */
emilmont 77:869cf507173a 1698
emilmont 77:869cf507173a 1699 /******************* Bit definition for AES_IVR2 register *******************/
emilmont 77:869cf507173a 1700 #define AES_IVR2 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 2 */
emilmont 77:869cf507173a 1701
emilmont 77:869cf507173a 1702 /******************* Bit definition for AES_IVR3 register *******************/
emilmont 77:869cf507173a 1703 #define AES_IVR3 ((uint32_t)0x0000FFFF) /*!< AES Initialization Vector Register 3 */
emilmont 77:869cf507173a 1704
emilmont 77:869cf507173a 1705 /******************************************************************************/
emilmont 77:869cf507173a 1706 /* */
emilmont 77:869cf507173a 1707 /* Analog Comparators (COMP) */
emilmont 77:869cf507173a 1708 /* */
emilmont 77:869cf507173a 1709 /******************************************************************************/
emilmont 77:869cf507173a 1710
emilmont 77:869cf507173a 1711 /****************** Bit definition for COMP_CSR register ********************/
emilmont 77:869cf507173a 1712 #define COMP_CSR_10KPU ((uint32_t)0x00000001) /*!< 10K pull-up resistor */
emilmont 77:869cf507173a 1713 #define COMP_CSR_400KPU ((uint32_t)0x00000002) /*!< 400K pull-up resistor */
emilmont 77:869cf507173a 1714 #define COMP_CSR_10KPD ((uint32_t)0x00000004) /*!< 10K pull-down resistor */
emilmont 77:869cf507173a 1715 #define COMP_CSR_400KPD ((uint32_t)0x00000008) /*!< 400K pull-down resistor */
emilmont 77:869cf507173a 1716
emilmont 77:869cf507173a 1717 #define COMP_CSR_CMP1EN ((uint32_t)0x00000010) /*!< Comparator 1 enable */
emilmont 77:869cf507173a 1718 #define COMP_CSR_SW1 ((uint32_t)0x00000020) /*!< SW1 analog switch enable */
emilmont 77:869cf507173a 1719 #define COMP_CSR_CMP1OUT ((uint32_t)0x00000080) /*!< Comparator 1 output */
emilmont 77:869cf507173a 1720
emilmont 77:869cf507173a 1721 #define COMP_CSR_SPEED ((uint32_t)0x00001000) /*!< Comparator 2 speed */
emilmont 77:869cf507173a 1722 #define COMP_CSR_CMP2OUT ((uint32_t)0x00002000) /*!< Comparator 2 ouput */
emilmont 77:869cf507173a 1723
emilmont 77:869cf507173a 1724 #define COMP_CSR_VREFOUTEN ((uint32_t)0x00010000) /*!< Comparator Vref Enable */
emilmont 77:869cf507173a 1725 #define COMP_CSR_WNDWE ((uint32_t)0x00020000) /*!< Window mode enable */
emilmont 77:869cf507173a 1726
emilmont 77:869cf507173a 1727 #define COMP_CSR_INSEL ((uint32_t)0x001C0000) /*!< INSEL[2:0] Inversion input Selection */
emilmont 77:869cf507173a 1728 #define COMP_CSR_INSEL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
emilmont 77:869cf507173a 1729 #define COMP_CSR_INSEL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
emilmont 77:869cf507173a 1730 #define COMP_CSR_INSEL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
emilmont 77:869cf507173a 1731
emilmont 77:869cf507173a 1732 #define COMP_CSR_OUTSEL ((uint32_t)0x00E00000) /*!< OUTSEL[2:0] comparator 2 output redirection */
emilmont 77:869cf507173a 1733 #define COMP_CSR_OUTSEL_0 ((uint32_t)0x00200000) /*!< Bit 0 */
emilmont 77:869cf507173a 1734 #define COMP_CSR_OUTSEL_1 ((uint32_t)0x00400000) /*!< Bit 1 */
emilmont 77:869cf507173a 1735 #define COMP_CSR_OUTSEL_2 ((uint32_t)0x00800000) /*!< Bit 2 */
emilmont 77:869cf507173a 1736
emilmont 77:869cf507173a 1737 #define COMP_CSR_FCH3 ((uint32_t)0x04000000) /*!< Bit 26 */
emilmont 77:869cf507173a 1738 #define COMP_CSR_FCH8 ((uint32_t)0x08000000) /*!< Bit 27 */
emilmont 77:869cf507173a 1739 #define COMP_CSR_RCH13 ((uint32_t)0x10000000) /*!< Bit 28 */
emilmont 77:869cf507173a 1740
emilmont 77:869cf507173a 1741 #define COMP_CSR_CAIE ((uint32_t)0x20000000) /*!< Bit 29 */
emilmont 77:869cf507173a 1742 #define COMP_CSR_CAIF ((uint32_t)0x40000000) /*!< Bit 30 */
emilmont 77:869cf507173a 1743 #define COMP_CSR_TSUSP ((uint32_t)0x80000000) /*!< Bit 31 */
emilmont 77:869cf507173a 1744
emilmont 77:869cf507173a 1745 /******************************************************************************/
emilmont 77:869cf507173a 1746 /* */
emilmont 77:869cf507173a 1747 /* Operational Amplifier (OPAMP) */
emilmont 77:869cf507173a 1748 /* */
emilmont 77:869cf507173a 1749 /******************************************************************************/
emilmont 77:869cf507173a 1750 /******************* Bit definition for OPAMP_CSR register ******************/
emilmont 77:869cf507173a 1751 #define OPAMP_CSR_OPA1PD ((uint32_t)0x00000001) /*!< OPAMP1 disable */
emilmont 77:869cf507173a 1752 #define OPAMP_CSR_S3SEL1 ((uint32_t)0x00000002) /*!< Switch 3 for OPAMP1 Enable */
emilmont 77:869cf507173a 1753 #define OPAMP_CSR_S4SEL1 ((uint32_t)0x00000004) /*!< Switch 4 for OPAMP1 Enable */
emilmont 77:869cf507173a 1754 #define OPAMP_CSR_S5SEL1 ((uint32_t)0x00000008) /*!< Switch 5 for OPAMP1 Enable */
emilmont 77:869cf507173a 1755 #define OPAMP_CSR_S6SEL1 ((uint32_t)0x00000010) /*!< Switch 6 for OPAMP1 Enable */
emilmont 77:869cf507173a 1756 #define OPAMP_CSR_OPA1CAL_L ((uint32_t)0x00000020) /*!< OPAMP1 Offset calibration for P differential pair */
emilmont 77:869cf507173a 1757 #define OPAMP_CSR_OPA1CAL_H ((uint32_t)0x00000040) /*!< OPAMP1 Offset calibration for N differential pair */
emilmont 77:869cf507173a 1758 #define OPAMP_CSR_OPA1LPM ((uint32_t)0x00000080) /*!< OPAMP1 Low power enable */
emilmont 77:869cf507173a 1759 #define OPAMP_CSR_OPA2PD ((uint32_t)0x00000100) /*!< OPAMP2 disable */
emilmont 77:869cf507173a 1760 #define OPAMP_CSR_S3SEL2 ((uint32_t)0x00000200) /*!< Switch 3 for OPAMP2 Enable */
emilmont 77:869cf507173a 1761 #define OPAMP_CSR_S4SEL2 ((uint32_t)0x00000400) /*!< Switch 4 for OPAMP2 Enable */
emilmont 77:869cf507173a 1762 #define OPAMP_CSR_S5SEL2 ((uint32_t)0x00000800) /*!< Switch 5 for OPAMP2 Enable */
emilmont 77:869cf507173a 1763 #define OPAMP_CSR_S6SEL2 ((uint32_t)0x00001000) /*!< Switch 6 for OPAMP2 Enable */
emilmont 77:869cf507173a 1764 #define OPAMP_CSR_OPA2CAL_L ((uint32_t)0x00002000) /*!< OPAMP2 Offset calibration for P differential pair */
emilmont 77:869cf507173a 1765 #define OPAMP_CSR_OPA2CAL_H ((uint32_t)0x00004000) /*!< OPAMP2 Offset calibration for N differential pair */
emilmont 77:869cf507173a 1766 #define OPAMP_CSR_OPA2LPM ((uint32_t)0x00008000) /*!< OPAMP2 Low power enable */
emilmont 77:869cf507173a 1767 #define OPAMP_CSR_OPA3PD ((uint32_t)0x00010000) /*!< OPAMP3 disable */
emilmont 77:869cf507173a 1768 #define OPAMP_CSR_S3SEL3 ((uint32_t)0x00020000) /*!< Switch 3 for OPAMP3 Enable */
emilmont 77:869cf507173a 1769 #define OPAMP_CSR_S4SEL3 ((uint32_t)0x00040000) /*!< Switch 4 for OPAMP3 Enable */
emilmont 77:869cf507173a 1770 #define OPAMP_CSR_S5SEL3 ((uint32_t)0x00080000) /*!< Switch 5 for OPAMP3 Enable */
emilmont 77:869cf507173a 1771 #define OPAMP_CSR_S6SEL3 ((uint32_t)0x00100000) /*!< Switch 6 for OPAMP3 Enable */
emilmont 77:869cf507173a 1772 #define OPAMP_CSR_OPA3CAL_L ((uint32_t)0x00200000) /*!< OPAMP3 Offset calibration for P differential pair */
emilmont 77:869cf507173a 1773 #define OPAMP_CSR_OPA3CAL_H ((uint32_t)0x00400000) /*!< OPAMP3 Offset calibration for N differential pair */
emilmont 77:869cf507173a 1774 #define OPAMP_CSR_OPA3LPM ((uint32_t)0x00800000) /*!< OPAMP3 Low power enable */
emilmont 77:869cf507173a 1775 #define OPAMP_CSR_ANAWSEL1 ((uint32_t)0x01000000) /*!< Switch ANA Enable for OPAMP1 */
emilmont 77:869cf507173a 1776 #define OPAMP_CSR_ANAWSEL2 ((uint32_t)0x02000000) /*!< Switch ANA Enable for OPAMP2 */
emilmont 77:869cf507173a 1777 #define OPAMP_CSR_ANAWSEL3 ((uint32_t)0x04000000) /*!< Switch ANA Enable for OPAMP3 */
emilmont 77:869cf507173a 1778 #define OPAMP_CSR_S7SEL2 ((uint32_t)0x08000000) /*!< Switch 7 for OPAMP2 Enable */
emilmont 77:869cf507173a 1779 #define OPAMP_CSR_AOP_RANGE ((uint32_t)0x10000000) /*!< Power range selection */
emilmont 77:869cf507173a 1780 #define OPAMP_CSR_OPA1CALOUT ((uint32_t)0x20000000) /*!< OPAMP1 calibration output */
emilmont 77:869cf507173a 1781 #define OPAMP_CSR_OPA2CALOUT ((uint32_t)0x40000000) /*!< OPAMP2 calibration output */
emilmont 77:869cf507173a 1782 #define OPAMP_CSR_OPA3CALOUT ((uint32_t)0x80000000) /*!< OPAMP3 calibration output */
emilmont 77:869cf507173a 1783
emilmont 77:869cf507173a 1784 /******************* Bit definition for OPAMP_OTR register ******************/
emilmont 77:869cf507173a 1785 #define OPAMP_OTR_AO1_OPT_OFFSET_TRIM ((uint32_t)0x000003FF) /*!< Offset trim for OPAMP1 */
emilmont 77:869cf507173a 1786 #define OPAMP_OTR_AO2_OPT_OFFSET_TRIM ((uint32_t)0x000FFC00) /*!< Offset trim for OPAMP2 */
emilmont 77:869cf507173a 1787 #define OPAMP_OTR_AO3_OPT_OFFSET_TRIM ((uint32_t)0x3FF00000) /*!< Offset trim for OPAMP2 */
emilmont 77:869cf507173a 1788 #define OPAMP_OTR_OT_USER ((uint32_t)0x80000000) /*!< Switch to OPAMP offset user trimmed values */
emilmont 77:869cf507173a 1789
emilmont 77:869cf507173a 1790 /******************* Bit definition for OPAMP_LPOTR register ****************/
emilmont 77:869cf507173a 1791 #define OPAMP_LP_OTR_AO1_OPT_OFFSET_TRIM_LP ((uint32_t)0x000003FF) /*!< Offset trim in low power for OPAMP1 */
emilmont 77:869cf507173a 1792 #define OPAMP_LP_OTR_AO2_OPT_OFFSET_TRIM_LP ((uint32_t)0x000FFC00) /*!< Offset trim in low power for OPAMP2 */
emilmont 77:869cf507173a 1793 #define OPAMP_LP_OTR_AO3_OPT_OFFSET_TRIM_LP ((uint32_t)0x3FF00000) /*!< Offset trim in low power for OPAMP3 */
emilmont 77:869cf507173a 1794
emilmont 77:869cf507173a 1795 /******************************************************************************/
emilmont 77:869cf507173a 1796 /* */
emilmont 77:869cf507173a 1797 /* CRC calculation unit (CRC) */
emilmont 77:869cf507173a 1798 /* */
emilmont 77:869cf507173a 1799 /******************************************************************************/
emilmont 77:869cf507173a 1800
emilmont 77:869cf507173a 1801 /******************* Bit definition for CRC_DR register *********************/
emilmont 77:869cf507173a 1802 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
emilmont 77:869cf507173a 1803
emilmont 77:869cf507173a 1804 /******************* Bit definition for CRC_IDR register ********************/
emilmont 77:869cf507173a 1805 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
emilmont 77:869cf507173a 1806
emilmont 77:869cf507173a 1807 /******************** Bit definition for CRC_CR register ********************/
emilmont 77:869cf507173a 1808 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET bit */
emilmont 77:869cf507173a 1809
emilmont 77:869cf507173a 1810 /******************************************************************************/
emilmont 77:869cf507173a 1811 /* */
emilmont 77:869cf507173a 1812 /* Digital to Analog Converter (DAC) */
emilmont 77:869cf507173a 1813 /* */
emilmont 77:869cf507173a 1814 /******************************************************************************/
emilmont 77:869cf507173a 1815
emilmont 77:869cf507173a 1816 /******************** Bit definition for DAC_CR register ********************/
emilmont 77:869cf507173a 1817 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!<DAC channel1 enable */
emilmont 77:869cf507173a 1818 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!<DAC channel1 output buffer disable */
emilmont 77:869cf507173a 1819 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!<DAC channel1 Trigger enable */
emilmont 77:869cf507173a 1820
emilmont 77:869cf507173a 1821 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
emilmont 77:869cf507173a 1822 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!<Bit 0 */
emilmont 77:869cf507173a 1823 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!<Bit 1 */
emilmont 77:869cf507173a 1824 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!<Bit 2 */
emilmont 77:869cf507173a 1825
emilmont 77:869cf507173a 1826 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
emilmont 77:869cf507173a 1827 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!<Bit 0 */
emilmont 77:869cf507173a 1828 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!<Bit 1 */
emilmont 77:869cf507173a 1829
emilmont 77:869cf507173a 1830 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
emilmont 77:869cf507173a 1831 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!<Bit 0 */
emilmont 77:869cf507173a 1832 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!<Bit 1 */
emilmont 77:869cf507173a 1833 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!<Bit 2 */
emilmont 77:869cf507173a 1834 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!<Bit 3 */
emilmont 77:869cf507173a 1835
emilmont 77:869cf507173a 1836 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!<DAC channel1 DMA enable */
emilmont 77:869cf507173a 1837 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun interrupt enable */
emilmont 77:869cf507173a 1838 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!<DAC channel2 enable */
emilmont 77:869cf507173a 1839 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!<DAC channel2 output buffer disable */
emilmont 77:869cf507173a 1840 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!<DAC channel2 Trigger enable */
emilmont 77:869cf507173a 1841
emilmont 77:869cf507173a 1842 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
emilmont 77:869cf507173a 1843 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!<Bit 0 */
emilmont 77:869cf507173a 1844 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!<Bit 1 */
emilmont 77:869cf507173a 1845 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!<Bit 2 */
emilmont 77:869cf507173a 1846
emilmont 77:869cf507173a 1847 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
emilmont 77:869cf507173a 1848 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!<Bit 0 */
emilmont 77:869cf507173a 1849 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!<Bit 1 */
emilmont 77:869cf507173a 1850
emilmont 77:869cf507173a 1851 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
emilmont 77:869cf507173a 1852 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!<Bit 0 */
emilmont 77:869cf507173a 1853 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!<Bit 1 */
emilmont 77:869cf507173a 1854 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!<Bit 2 */
emilmont 77:869cf507173a 1855 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!<Bit 3 */
emilmont 77:869cf507173a 1856
emilmont 77:869cf507173a 1857 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!<DAC channel2 DMA enabled */
emilmont 77:869cf507173a 1858 #define DAC_CR_DMAUDRIE2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun interrupt enable */
emilmont 77:869cf507173a 1859 /***************** Bit definition for DAC_SWTRIGR register ******************/
emilmont 77:869cf507173a 1860 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!<DAC channel1 software trigger */
emilmont 77:869cf507173a 1861 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!<DAC channel2 software trigger */
emilmont 77:869cf507173a 1862
emilmont 77:869cf507173a 1863 /***************** Bit definition for DAC_DHR12R1 register ******************/
emilmont 77:869cf507173a 1864 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!<DAC channel1 12-bit Right aligned data */
emilmont 77:869cf507173a 1865
emilmont 77:869cf507173a 1866 /***************** Bit definition for DAC_DHR12L1 register ******************/
emilmont 77:869cf507173a 1867 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!<DAC channel1 12-bit Left aligned data */
emilmont 77:869cf507173a 1868
emilmont 77:869cf507173a 1869 /****************** Bit definition for DAC_DHR8R1 register ******************/
emilmont 77:869cf507173a 1870 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!<DAC channel1 8-bit Right aligned data */
emilmont 77:869cf507173a 1871
emilmont 77:869cf507173a 1872 /***************** Bit definition for DAC_DHR12R2 register ******************/
emilmont 77:869cf507173a 1873 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!<DAC channel2 12-bit Right aligned data */
emilmont 77:869cf507173a 1874
emilmont 77:869cf507173a 1875 /***************** Bit definition for DAC_DHR12L2 register ******************/
emilmont 77:869cf507173a 1876 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!<DAC channel2 12-bit Left aligned data */
emilmont 77:869cf507173a 1877
emilmont 77:869cf507173a 1878 /****************** Bit definition for DAC_DHR8R2 register ******************/
emilmont 77:869cf507173a 1879 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!<DAC channel2 8-bit Right aligned data */
emilmont 77:869cf507173a 1880
emilmont 77:869cf507173a 1881 /***************** Bit definition for DAC_DHR12RD register ******************/
emilmont 77:869cf507173a 1882 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!<DAC channel1 12-bit Right aligned data */
emilmont 77:869cf507173a 1883 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!<DAC channel2 12-bit Right aligned data */
emilmont 77:869cf507173a 1884
emilmont 77:869cf507173a 1885 /***************** Bit definition for DAC_DHR12LD register ******************/
emilmont 77:869cf507173a 1886 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!<DAC channel1 12-bit Left aligned data */
emilmont 77:869cf507173a 1887 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!<DAC channel2 12-bit Left aligned data */
emilmont 77:869cf507173a 1888
emilmont 77:869cf507173a 1889 /****************** Bit definition for DAC_DHR8RD register ******************/
emilmont 77:869cf507173a 1890 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!<DAC channel1 8-bit Right aligned data */
emilmont 77:869cf507173a 1891 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!<DAC channel2 8-bit Right aligned data */
emilmont 77:869cf507173a 1892
emilmont 77:869cf507173a 1893 /******************* Bit definition for DAC_DOR1 register *******************/
emilmont 77:869cf507173a 1894 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!<DAC channel1 data output */
emilmont 77:869cf507173a 1895
emilmont 77:869cf507173a 1896 /******************* Bit definition for DAC_DOR2 register *******************/
emilmont 77:869cf507173a 1897 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!<DAC channel2 data output */
emilmont 77:869cf507173a 1898
emilmont 77:869cf507173a 1899 /******************** Bit definition for DAC_SR register ********************/
emilmont 77:869cf507173a 1900 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!<DAC channel1 DMA underrun flag */
emilmont 77:869cf507173a 1901 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!<DAC channel2 DMA underrun flag */
emilmont 77:869cf507173a 1902
emilmont 77:869cf507173a 1903 /******************************************************************************/
emilmont 77:869cf507173a 1904 /* */
emilmont 77:869cf507173a 1905 /* Debug MCU (DBGMCU) */
emilmont 77:869cf507173a 1906 /* */
emilmont 77:869cf507173a 1907 /******************************************************************************/
emilmont 77:869cf507173a 1908
emilmont 77:869cf507173a 1909 /**************** Bit definition for DBGMCU_IDCODE register *****************/
emilmont 77:869cf507173a 1910 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
emilmont 77:869cf507173a 1911
emilmont 77:869cf507173a 1912 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
emilmont 77:869cf507173a 1913 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 1914 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 1915 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 1916 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 1917 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
emilmont 77:869cf507173a 1918 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
emilmont 77:869cf507173a 1919 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
emilmont 77:869cf507173a 1920 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
emilmont 77:869cf507173a 1921 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
emilmont 77:869cf507173a 1922 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
emilmont 77:869cf507173a 1923 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
emilmont 77:869cf507173a 1924 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
emilmont 77:869cf507173a 1925 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
emilmont 77:869cf507173a 1926 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
emilmont 77:869cf507173a 1927 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
emilmont 77:869cf507173a 1928 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
emilmont 77:869cf507173a 1929
emilmont 77:869cf507173a 1930 /****************** Bit definition for DBGMCU_CR register *******************/
emilmont 77:869cf507173a 1931 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001) /*!< Debug Sleep Mode */
emilmont 77:869cf507173a 1932 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
emilmont 77:869cf507173a 1933 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
emilmont 77:869cf507173a 1934 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020) /*!< Trace Pin Assignment Control */
emilmont 77:869cf507173a 1935
emilmont 77:869cf507173a 1936 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0) /*!< TRACE_MODE[1:0] bits (Trace Pin Assignment Control) */
emilmont 77:869cf507173a 1937 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040) /*!< Bit 0 */
emilmont 77:869cf507173a 1938 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080) /*!< Bit 1 */
emilmont 77:869cf507173a 1939
emilmont 77:869cf507173a 1940 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
emilmont 77:869cf507173a 1941
emilmont 77:869cf507173a 1942 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001) /*!< TIM2 counter stopped when core is halted */
emilmont 77:869cf507173a 1943 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
emilmont 77:869cf507173a 1944 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004) /*!< TIM4 counter stopped when core is halted */
emilmont 77:869cf507173a 1945 #define DBGMCU_APB1_FZ_DBG_TIM5_STOP ((uint32_t)0x00000008) /*!< TIM5 counter stopped when core is halted */
emilmont 77:869cf507173a 1946 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
emilmont 77:869cf507173a 1947 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020) /*!< TIM7 counter stopped when core is halted */
emilmont 77:869cf507173a 1948 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Counter stopped when Core is halted */
emilmont 77:869cf507173a 1949 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
emilmont 77:869cf507173a 1950 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
emilmont 77:869cf507173a 1951 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< SMBUS timeout mode stopped when Core is halted */
emilmont 77:869cf507173a 1952 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000) /*!< SMBUS timeout mode stopped when Core is halted */
emilmont 77:869cf507173a 1953
emilmont 77:869cf507173a 1954 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
emilmont 77:869cf507173a 1955
emilmont 77:869cf507173a 1956 #define DBGMCU_APB2_FZ_DBG_TIM9_STOP ((uint32_t)0x00000004) /*!< TIM9 counter stopped when core is halted */
emilmont 77:869cf507173a 1957 #define DBGMCU_APB2_FZ_DBG_TIM10_STOP ((uint32_t)0x00000008) /*!< TIM10 counter stopped when core is halted */
emilmont 77:869cf507173a 1958 #define DBGMCU_APB2_FZ_DBG_TIM11_STOP ((uint32_t)0x00000010) /*!< TIM11 counter stopped when core is halted */
emilmont 77:869cf507173a 1959
emilmont 77:869cf507173a 1960 /******************************************************************************/
emilmont 77:869cf507173a 1961 /* */
emilmont 77:869cf507173a 1962 /* DMA Controller (DMA) */
emilmont 77:869cf507173a 1963 /* */
emilmont 77:869cf507173a 1964 /******************************************************************************/
emilmont 77:869cf507173a 1965
emilmont 77:869cf507173a 1966 /******************* Bit definition for DMA_ISR register ********************/
emilmont 77:869cf507173a 1967 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
emilmont 77:869cf507173a 1968 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
emilmont 77:869cf507173a 1969 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
emilmont 77:869cf507173a 1970 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
emilmont 77:869cf507173a 1971 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
emilmont 77:869cf507173a 1972 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
emilmont 77:869cf507173a 1973 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
emilmont 77:869cf507173a 1974 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
emilmont 77:869cf507173a 1975 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
emilmont 77:869cf507173a 1976 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
emilmont 77:869cf507173a 1977 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
emilmont 77:869cf507173a 1978 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
emilmont 77:869cf507173a 1979 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
emilmont 77:869cf507173a 1980 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
emilmont 77:869cf507173a 1981 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
emilmont 77:869cf507173a 1982 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
emilmont 77:869cf507173a 1983 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
emilmont 77:869cf507173a 1984 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
emilmont 77:869cf507173a 1985 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
emilmont 77:869cf507173a 1986 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
emilmont 77:869cf507173a 1987 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
emilmont 77:869cf507173a 1988 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
emilmont 77:869cf507173a 1989 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
emilmont 77:869cf507173a 1990 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
emilmont 77:869cf507173a 1991 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
emilmont 77:869cf507173a 1992 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
emilmont 77:869cf507173a 1993 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
emilmont 77:869cf507173a 1994 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
emilmont 77:869cf507173a 1995
emilmont 77:869cf507173a 1996 /******************* Bit definition for DMA_IFCR register *******************/
emilmont 77:869cf507173a 1997 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clearr */
emilmont 77:869cf507173a 1998 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
emilmont 77:869cf507173a 1999 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
emilmont 77:869cf507173a 2000 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
emilmont 77:869cf507173a 2001 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
emilmont 77:869cf507173a 2002 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
emilmont 77:869cf507173a 2003 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
emilmont 77:869cf507173a 2004 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
emilmont 77:869cf507173a 2005 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
emilmont 77:869cf507173a 2006 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
emilmont 77:869cf507173a 2007 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
emilmont 77:869cf507173a 2008 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
emilmont 77:869cf507173a 2009 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
emilmont 77:869cf507173a 2010 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
emilmont 77:869cf507173a 2011 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
emilmont 77:869cf507173a 2012 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
emilmont 77:869cf507173a 2013 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
emilmont 77:869cf507173a 2014 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
emilmont 77:869cf507173a 2015 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
emilmont 77:869cf507173a 2016 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
emilmont 77:869cf507173a 2017 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
emilmont 77:869cf507173a 2018 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
emilmont 77:869cf507173a 2019 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
emilmont 77:869cf507173a 2020 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
emilmont 77:869cf507173a 2021 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
emilmont 77:869cf507173a 2022 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
emilmont 77:869cf507173a 2023 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
emilmont 77:869cf507173a 2024 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
emilmont 77:869cf507173a 2025
emilmont 77:869cf507173a 2026 /******************* Bit definition for DMA_CCR1 register *******************/
emilmont 77:869cf507173a 2027 #define DMA_CCR1_EN ((uint16_t)0x0001) /*!< Channel enable*/
emilmont 77:869cf507173a 2028 #define DMA_CCR1_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
emilmont 77:869cf507173a 2029 #define DMA_CCR1_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
emilmont 77:869cf507173a 2030 #define DMA_CCR1_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
emilmont 77:869cf507173a 2031 #define DMA_CCR1_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
emilmont 77:869cf507173a 2032 #define DMA_CCR1_CIRC ((uint16_t)0x0020) /*!< Circular mode */
emilmont 77:869cf507173a 2033 #define DMA_CCR1_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
emilmont 77:869cf507173a 2034 #define DMA_CCR1_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
emilmont 77:869cf507173a 2035
emilmont 77:869cf507173a 2036 #define DMA_CCR1_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
emilmont 77:869cf507173a 2037 #define DMA_CCR1_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
emilmont 77:869cf507173a 2038 #define DMA_CCR1_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
emilmont 77:869cf507173a 2039
emilmont 77:869cf507173a 2040 #define DMA_CCR1_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
emilmont 77:869cf507173a 2041 #define DMA_CCR1_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 2042 #define DMA_CCR1_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 2043
emilmont 77:869cf507173a 2044 #define DMA_CCR1_PL ((uint16_t)0x3000) /*!< PL[1:0] bits(Channel Priority level) */
emilmont 77:869cf507173a 2045 #define DMA_CCR1_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
emilmont 77:869cf507173a 2046 #define DMA_CCR1_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
emilmont 77:869cf507173a 2047
emilmont 77:869cf507173a 2048 #define DMA_CCR1_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
emilmont 77:869cf507173a 2049
emilmont 77:869cf507173a 2050 /******************* Bit definition for DMA_CCR2 register *******************/
emilmont 77:869cf507173a 2051 #define DMA_CCR2_EN ((uint16_t)0x0001) /*!< Channel enable */
emilmont 77:869cf507173a 2052 #define DMA_CCR2_TCIE ((uint16_t)0x0002) /*!< ransfer complete interrupt enable */
emilmont 77:869cf507173a 2053 #define DMA_CCR2_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
emilmont 77:869cf507173a 2054 #define DMA_CCR2_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
emilmont 77:869cf507173a 2055 #define DMA_CCR2_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
emilmont 77:869cf507173a 2056 #define DMA_CCR2_CIRC ((uint16_t)0x0020) /*!< Circular mode */
emilmont 77:869cf507173a 2057 #define DMA_CCR2_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
emilmont 77:869cf507173a 2058 #define DMA_CCR2_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
emilmont 77:869cf507173a 2059
emilmont 77:869cf507173a 2060 #define DMA_CCR2_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
emilmont 77:869cf507173a 2061 #define DMA_CCR2_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
emilmont 77:869cf507173a 2062 #define DMA_CCR2_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
emilmont 77:869cf507173a 2063
emilmont 77:869cf507173a 2064 #define DMA_CCR2_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
emilmont 77:869cf507173a 2065 #define DMA_CCR2_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 2066 #define DMA_CCR2_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 2067
emilmont 77:869cf507173a 2068 #define DMA_CCR2_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
emilmont 77:869cf507173a 2069 #define DMA_CCR2_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
emilmont 77:869cf507173a 2070 #define DMA_CCR2_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
emilmont 77:869cf507173a 2071
emilmont 77:869cf507173a 2072 #define DMA_CCR2_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
emilmont 77:869cf507173a 2073
emilmont 77:869cf507173a 2074 /******************* Bit definition for DMA_CCR3 register *******************/
emilmont 77:869cf507173a 2075 #define DMA_CCR3_EN ((uint16_t)0x0001) /*!< Channel enable */
emilmont 77:869cf507173a 2076 #define DMA_CCR3_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
emilmont 77:869cf507173a 2077 #define DMA_CCR3_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
emilmont 77:869cf507173a 2078 #define DMA_CCR3_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
emilmont 77:869cf507173a 2079 #define DMA_CCR3_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
emilmont 77:869cf507173a 2080 #define DMA_CCR3_CIRC ((uint16_t)0x0020) /*!< Circular mode */
emilmont 77:869cf507173a 2081 #define DMA_CCR3_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
emilmont 77:869cf507173a 2082 #define DMA_CCR3_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
emilmont 77:869cf507173a 2083
emilmont 77:869cf507173a 2084 #define DMA_CCR3_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
emilmont 77:869cf507173a 2085 #define DMA_CCR3_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
emilmont 77:869cf507173a 2086 #define DMA_CCR3_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
emilmont 77:869cf507173a 2087
emilmont 77:869cf507173a 2088 #define DMA_CCR3_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
emilmont 77:869cf507173a 2089 #define DMA_CCR3_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 2090 #define DMA_CCR3_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 2091
emilmont 77:869cf507173a 2092 #define DMA_CCR3_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
emilmont 77:869cf507173a 2093 #define DMA_CCR3_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
emilmont 77:869cf507173a 2094 #define DMA_CCR3_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
emilmont 77:869cf507173a 2095
emilmont 77:869cf507173a 2096 #define DMA_CCR3_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
emilmont 77:869cf507173a 2097
emilmont 77:869cf507173a 2098 /*!<****************** Bit definition for DMA_CCR4 register *******************/
emilmont 77:869cf507173a 2099 #define DMA_CCR4_EN ((uint16_t)0x0001) /*!< Channel enable */
emilmont 77:869cf507173a 2100 #define DMA_CCR4_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
emilmont 77:869cf507173a 2101 #define DMA_CCR4_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
emilmont 77:869cf507173a 2102 #define DMA_CCR4_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
emilmont 77:869cf507173a 2103 #define DMA_CCR4_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
emilmont 77:869cf507173a 2104 #define DMA_CCR4_CIRC ((uint16_t)0x0020) /*!< Circular mode */
emilmont 77:869cf507173a 2105 #define DMA_CCR4_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
emilmont 77:869cf507173a 2106 #define DMA_CCR4_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
emilmont 77:869cf507173a 2107
emilmont 77:869cf507173a 2108 #define DMA_CCR4_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
emilmont 77:869cf507173a 2109 #define DMA_CCR4_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
emilmont 77:869cf507173a 2110 #define DMA_CCR4_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
emilmont 77:869cf507173a 2111
emilmont 77:869cf507173a 2112 #define DMA_CCR4_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
emilmont 77:869cf507173a 2113 #define DMA_CCR4_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 2114 #define DMA_CCR4_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 2115
emilmont 77:869cf507173a 2116 #define DMA_CCR4_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
emilmont 77:869cf507173a 2117 #define DMA_CCR4_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
emilmont 77:869cf507173a 2118 #define DMA_CCR4_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
emilmont 77:869cf507173a 2119
emilmont 77:869cf507173a 2120 #define DMA_CCR4_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
emilmont 77:869cf507173a 2121
emilmont 77:869cf507173a 2122 /****************** Bit definition for DMA_CCR5 register *******************/
emilmont 77:869cf507173a 2123 #define DMA_CCR5_EN ((uint16_t)0x0001) /*!< Channel enable */
emilmont 77:869cf507173a 2124 #define DMA_CCR5_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
emilmont 77:869cf507173a 2125 #define DMA_CCR5_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
emilmont 77:869cf507173a 2126 #define DMA_CCR5_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
emilmont 77:869cf507173a 2127 #define DMA_CCR5_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
emilmont 77:869cf507173a 2128 #define DMA_CCR5_CIRC ((uint16_t)0x0020) /*!< Circular mode */
emilmont 77:869cf507173a 2129 #define DMA_CCR5_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
emilmont 77:869cf507173a 2130 #define DMA_CCR5_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
emilmont 77:869cf507173a 2131
emilmont 77:869cf507173a 2132 #define DMA_CCR5_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
emilmont 77:869cf507173a 2133 #define DMA_CCR5_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
emilmont 77:869cf507173a 2134 #define DMA_CCR5_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
emilmont 77:869cf507173a 2135
emilmont 77:869cf507173a 2136 #define DMA_CCR5_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
emilmont 77:869cf507173a 2137 #define DMA_CCR5_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 2138 #define DMA_CCR5_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 2139
emilmont 77:869cf507173a 2140 #define DMA_CCR5_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
emilmont 77:869cf507173a 2141 #define DMA_CCR5_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
emilmont 77:869cf507173a 2142 #define DMA_CCR5_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
emilmont 77:869cf507173a 2143
emilmont 77:869cf507173a 2144 #define DMA_CCR5_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
emilmont 77:869cf507173a 2145
emilmont 77:869cf507173a 2146 /******************* Bit definition for DMA_CCR6 register *******************/
emilmont 77:869cf507173a 2147 #define DMA_CCR6_EN ((uint16_t)0x0001) /*!< Channel enable */
emilmont 77:869cf507173a 2148 #define DMA_CCR6_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
emilmont 77:869cf507173a 2149 #define DMA_CCR6_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
emilmont 77:869cf507173a 2150 #define DMA_CCR6_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
emilmont 77:869cf507173a 2151 #define DMA_CCR6_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
emilmont 77:869cf507173a 2152 #define DMA_CCR6_CIRC ((uint16_t)0x0020) /*!< Circular mode */
emilmont 77:869cf507173a 2153 #define DMA_CCR6_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
emilmont 77:869cf507173a 2154 #define DMA_CCR6_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
emilmont 77:869cf507173a 2155
emilmont 77:869cf507173a 2156 #define DMA_CCR6_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
emilmont 77:869cf507173a 2157 #define DMA_CCR6_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
emilmont 77:869cf507173a 2158 #define DMA_CCR6_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
emilmont 77:869cf507173a 2159
emilmont 77:869cf507173a 2160 #define DMA_CCR6_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
emilmont 77:869cf507173a 2161 #define DMA_CCR6_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 2162 #define DMA_CCR6_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 2163
emilmont 77:869cf507173a 2164 #define DMA_CCR6_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
emilmont 77:869cf507173a 2165 #define DMA_CCR6_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
emilmont 77:869cf507173a 2166 #define DMA_CCR6_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
emilmont 77:869cf507173a 2167
emilmont 77:869cf507173a 2168 #define DMA_CCR6_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode */
emilmont 77:869cf507173a 2169
emilmont 77:869cf507173a 2170 /******************* Bit definition for DMA_CCR7 register *******************/
emilmont 77:869cf507173a 2171 #define DMA_CCR7_EN ((uint16_t)0x0001) /*!< Channel enable */
emilmont 77:869cf507173a 2172 #define DMA_CCR7_TCIE ((uint16_t)0x0002) /*!< Transfer complete interrupt enable */
emilmont 77:869cf507173a 2173 #define DMA_CCR7_HTIE ((uint16_t)0x0004) /*!< Half Transfer interrupt enable */
emilmont 77:869cf507173a 2174 #define DMA_CCR7_TEIE ((uint16_t)0x0008) /*!< Transfer error interrupt enable */
emilmont 77:869cf507173a 2175 #define DMA_CCR7_DIR ((uint16_t)0x0010) /*!< Data transfer direction */
emilmont 77:869cf507173a 2176 #define DMA_CCR7_CIRC ((uint16_t)0x0020) /*!< Circular mode */
emilmont 77:869cf507173a 2177 #define DMA_CCR7_PINC ((uint16_t)0x0040) /*!< Peripheral increment mode */
emilmont 77:869cf507173a 2178 #define DMA_CCR7_MINC ((uint16_t)0x0080) /*!< Memory increment mode */
emilmont 77:869cf507173a 2179
emilmont 77:869cf507173a 2180 #define DMA_CCR7_PSIZE ((uint16_t)0x0300) /*!< PSIZE[1:0] bits (Peripheral size) */
emilmont 77:869cf507173a 2181 #define DMA_CCR7_PSIZE_0 ((uint16_t)0x0100) /*!< Bit 0 */
emilmont 77:869cf507173a 2182 #define DMA_CCR7_PSIZE_1 ((uint16_t)0x0200) /*!< Bit 1 */
emilmont 77:869cf507173a 2183
emilmont 77:869cf507173a 2184 #define DMA_CCR7_MSIZE ((uint16_t)0x0C00) /*!< MSIZE[1:0] bits (Memory size) */
emilmont 77:869cf507173a 2185 #define DMA_CCR7_MSIZE_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 2186 #define DMA_CCR7_MSIZE_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 2187
emilmont 77:869cf507173a 2188 #define DMA_CCR7_PL ((uint16_t)0x3000) /*!< PL[1:0] bits (Channel Priority level) */
emilmont 77:869cf507173a 2189 #define DMA_CCR7_PL_0 ((uint16_t)0x1000) /*!< Bit 0 */
emilmont 77:869cf507173a 2190 #define DMA_CCR7_PL_1 ((uint16_t)0x2000) /*!< Bit 1 */
emilmont 77:869cf507173a 2191
emilmont 77:869cf507173a 2192 #define DMA_CCR7_MEM2MEM ((uint16_t)0x4000) /*!< Memory to memory mode enable */
emilmont 77:869cf507173a 2193
emilmont 77:869cf507173a 2194 /****************** Bit definition for DMA_CNDTR1 register ******************/
emilmont 77:869cf507173a 2195 #define DMA_CNDTR1_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
emilmont 77:869cf507173a 2196
emilmont 77:869cf507173a 2197 /****************** Bit definition for DMA_CNDTR2 register ******************/
emilmont 77:869cf507173a 2198 #define DMA_CNDTR2_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
emilmont 77:869cf507173a 2199
emilmont 77:869cf507173a 2200 /****************** Bit definition for DMA_CNDTR3 register ******************/
emilmont 77:869cf507173a 2201 #define DMA_CNDTR3_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
emilmont 77:869cf507173a 2202
emilmont 77:869cf507173a 2203 /****************** Bit definition for DMA_CNDTR4 register ******************/
emilmont 77:869cf507173a 2204 #define DMA_CNDTR4_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
emilmont 77:869cf507173a 2205
emilmont 77:869cf507173a 2206 /****************** Bit definition for DMA_CNDTR5 register ******************/
emilmont 77:869cf507173a 2207 #define DMA_CNDTR5_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
emilmont 77:869cf507173a 2208
emilmont 77:869cf507173a 2209 /****************** Bit definition for DMA_CNDTR6 register ******************/
emilmont 77:869cf507173a 2210 #define DMA_CNDTR6_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
emilmont 77:869cf507173a 2211
emilmont 77:869cf507173a 2212 /****************** Bit definition for DMA_CNDTR7 register ******************/
emilmont 77:869cf507173a 2213 #define DMA_CNDTR7_NDT ((uint16_t)0xFFFF) /*!< Number of data to Transfer */
emilmont 77:869cf507173a 2214
emilmont 77:869cf507173a 2215 /****************** Bit definition for DMA_CPAR1 register *******************/
emilmont 77:869cf507173a 2216 #define DMA_CPAR1_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
emilmont 77:869cf507173a 2217
emilmont 77:869cf507173a 2218 /****************** Bit definition for DMA_CPAR2 register *******************/
emilmont 77:869cf507173a 2219 #define DMA_CPAR2_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
emilmont 77:869cf507173a 2220
emilmont 77:869cf507173a 2221 /****************** Bit definition for DMA_CPAR3 register *******************/
emilmont 77:869cf507173a 2222 #define DMA_CPAR3_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
emilmont 77:869cf507173a 2223
emilmont 77:869cf507173a 2224
emilmont 77:869cf507173a 2225 /****************** Bit definition for DMA_CPAR4 register *******************/
emilmont 77:869cf507173a 2226 #define DMA_CPAR4_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
emilmont 77:869cf507173a 2227
emilmont 77:869cf507173a 2228 /****************** Bit definition for DMA_CPAR5 register *******************/
emilmont 77:869cf507173a 2229 #define DMA_CPAR5_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
emilmont 77:869cf507173a 2230
emilmont 77:869cf507173a 2231 /****************** Bit definition for DMA_CPAR6 register *******************/
emilmont 77:869cf507173a 2232 #define DMA_CPAR6_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
emilmont 77:869cf507173a 2233
emilmont 77:869cf507173a 2234
emilmont 77:869cf507173a 2235 /****************** Bit definition for DMA_CPAR7 register *******************/
emilmont 77:869cf507173a 2236 #define DMA_CPAR7_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
emilmont 77:869cf507173a 2237
emilmont 77:869cf507173a 2238 /****************** Bit definition for DMA_CMAR1 register *******************/
emilmont 77:869cf507173a 2239 #define DMA_CMAR1_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
emilmont 77:869cf507173a 2240
emilmont 77:869cf507173a 2241 /****************** Bit definition for DMA_CMAR2 register *******************/
emilmont 77:869cf507173a 2242 #define DMA_CMAR2_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
emilmont 77:869cf507173a 2243
emilmont 77:869cf507173a 2244 /****************** Bit definition for DMA_CMAR3 register *******************/
emilmont 77:869cf507173a 2245 #define DMA_CMAR3_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
emilmont 77:869cf507173a 2246
emilmont 77:869cf507173a 2247
emilmont 77:869cf507173a 2248 /****************** Bit definition for DMA_CMAR4 register *******************/
emilmont 77:869cf507173a 2249 #define DMA_CMAR4_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
emilmont 77:869cf507173a 2250
emilmont 77:869cf507173a 2251 /****************** Bit definition for DMA_CMAR5 register *******************/
emilmont 77:869cf507173a 2252 #define DMA_CMAR5_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
emilmont 77:869cf507173a 2253
emilmont 77:869cf507173a 2254 /****************** Bit definition for DMA_CMAR6 register *******************/
emilmont 77:869cf507173a 2255 #define DMA_CMAR6_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
emilmont 77:869cf507173a 2256
emilmont 77:869cf507173a 2257 /****************** Bit definition for DMA_CMAR7 register *******************/
emilmont 77:869cf507173a 2258 #define DMA_CMAR7_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
emilmont 77:869cf507173a 2259
emilmont 77:869cf507173a 2260 /******************************************************************************/
emilmont 77:869cf507173a 2261 /* */
emilmont 77:869cf507173a 2262 /* External Interrupt/Event Controller (EXTI) */
emilmont 77:869cf507173a 2263 /* */
emilmont 77:869cf507173a 2264 /******************************************************************************/
emilmont 77:869cf507173a 2265
emilmont 77:869cf507173a 2266 /******************* Bit definition for EXTI_IMR register *******************/
emilmont 77:869cf507173a 2267 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
emilmont 77:869cf507173a 2268 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
emilmont 77:869cf507173a 2269 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
emilmont 77:869cf507173a 2270 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
emilmont 77:869cf507173a 2271 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
emilmont 77:869cf507173a 2272 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
emilmont 77:869cf507173a 2273 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
emilmont 77:869cf507173a 2274 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
emilmont 77:869cf507173a 2275 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
emilmont 77:869cf507173a 2276 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
emilmont 77:869cf507173a 2277 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
emilmont 77:869cf507173a 2278 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
emilmont 77:869cf507173a 2279 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
emilmont 77:869cf507173a 2280 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
emilmont 77:869cf507173a 2281 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
emilmont 77:869cf507173a 2282 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
emilmont 77:869cf507173a 2283 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
emilmont 77:869cf507173a 2284 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
emilmont 77:869cf507173a 2285 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
emilmont 77:869cf507173a 2286 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
emilmont 77:869cf507173a 2287 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
emilmont 77:869cf507173a 2288 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
emilmont 77:869cf507173a 2289 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
emilmont 77:869cf507173a 2290 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
emilmont 77:869cf507173a 2291
emilmont 77:869cf507173a 2292 /******************* Bit definition for EXTI_EMR register *******************/
emilmont 77:869cf507173a 2293 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
emilmont 77:869cf507173a 2294 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
emilmont 77:869cf507173a 2295 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
emilmont 77:869cf507173a 2296 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
emilmont 77:869cf507173a 2297 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
emilmont 77:869cf507173a 2298 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
emilmont 77:869cf507173a 2299 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
emilmont 77:869cf507173a 2300 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
emilmont 77:869cf507173a 2301 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
emilmont 77:869cf507173a 2302 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
emilmont 77:869cf507173a 2303 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
emilmont 77:869cf507173a 2304 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
emilmont 77:869cf507173a 2305 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
emilmont 77:869cf507173a 2306 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
emilmont 77:869cf507173a 2307 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
emilmont 77:869cf507173a 2308 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
emilmont 77:869cf507173a 2309 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
emilmont 77:869cf507173a 2310 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
emilmont 77:869cf507173a 2311 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
emilmont 77:869cf507173a 2312 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
emilmont 77:869cf507173a 2313 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
emilmont 77:869cf507173a 2314 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
emilmont 77:869cf507173a 2315 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
emilmont 77:869cf507173a 2316 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
emilmont 77:869cf507173a 2317
emilmont 77:869cf507173a 2318 /****************** Bit definition for EXTI_RTSR register *******************/
emilmont 77:869cf507173a 2319 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
emilmont 77:869cf507173a 2320 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
emilmont 77:869cf507173a 2321 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
emilmont 77:869cf507173a 2322 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
emilmont 77:869cf507173a 2323 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
emilmont 77:869cf507173a 2324 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
emilmont 77:869cf507173a 2325 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
emilmont 77:869cf507173a 2326 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
emilmont 77:869cf507173a 2327 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
emilmont 77:869cf507173a 2328 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
emilmont 77:869cf507173a 2329 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
emilmont 77:869cf507173a 2330 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
emilmont 77:869cf507173a 2331 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
emilmont 77:869cf507173a 2332 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
emilmont 77:869cf507173a 2333 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
emilmont 77:869cf507173a 2334 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
emilmont 77:869cf507173a 2335 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
emilmont 77:869cf507173a 2336 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
emilmont 77:869cf507173a 2337 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
emilmont 77:869cf507173a 2338 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
emilmont 77:869cf507173a 2339 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
emilmont 77:869cf507173a 2340 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
emilmont 77:869cf507173a 2341 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
emilmont 77:869cf507173a 2342 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
emilmont 77:869cf507173a 2343
emilmont 77:869cf507173a 2344 /****************** Bit definition for EXTI_FTSR register *******************/
emilmont 77:869cf507173a 2345 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
emilmont 77:869cf507173a 2346 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
emilmont 77:869cf507173a 2347 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
emilmont 77:869cf507173a 2348 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
emilmont 77:869cf507173a 2349 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
emilmont 77:869cf507173a 2350 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
emilmont 77:869cf507173a 2351 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
emilmont 77:869cf507173a 2352 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
emilmont 77:869cf507173a 2353 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
emilmont 77:869cf507173a 2354 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
emilmont 77:869cf507173a 2355 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
emilmont 77:869cf507173a 2356 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
emilmont 77:869cf507173a 2357 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
emilmont 77:869cf507173a 2358 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
emilmont 77:869cf507173a 2359 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
emilmont 77:869cf507173a 2360 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
emilmont 77:869cf507173a 2361 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
emilmont 77:869cf507173a 2362 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
emilmont 77:869cf507173a 2363 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
emilmont 77:869cf507173a 2364 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
emilmont 77:869cf507173a 2365 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
emilmont 77:869cf507173a 2366 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
emilmont 77:869cf507173a 2367 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
emilmont 77:869cf507173a 2368 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
emilmont 77:869cf507173a 2369
emilmont 77:869cf507173a 2370 /****************** Bit definition for EXTI_SWIER register ******************/
emilmont 77:869cf507173a 2371 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
emilmont 77:869cf507173a 2372 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
emilmont 77:869cf507173a 2373 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
emilmont 77:869cf507173a 2374 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
emilmont 77:869cf507173a 2375 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
emilmont 77:869cf507173a 2376 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
emilmont 77:869cf507173a 2377 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
emilmont 77:869cf507173a 2378 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
emilmont 77:869cf507173a 2379 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
emilmont 77:869cf507173a 2380 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
emilmont 77:869cf507173a 2381 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
emilmont 77:869cf507173a 2382 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
emilmont 77:869cf507173a 2383 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
emilmont 77:869cf507173a 2384 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
emilmont 77:869cf507173a 2385 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
emilmont 77:869cf507173a 2386 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
emilmont 77:869cf507173a 2387 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
emilmont 77:869cf507173a 2388 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
emilmont 77:869cf507173a 2389 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
emilmont 77:869cf507173a 2390 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
emilmont 77:869cf507173a 2391 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
emilmont 77:869cf507173a 2392 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
emilmont 77:869cf507173a 2393 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
emilmont 77:869cf507173a 2394 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
emilmont 77:869cf507173a 2395
emilmont 77:869cf507173a 2396 /******************* Bit definition for EXTI_PR register ********************/
emilmont 77:869cf507173a 2397 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
emilmont 77:869cf507173a 2398 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
emilmont 77:869cf507173a 2399 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
emilmont 77:869cf507173a 2400 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
emilmont 77:869cf507173a 2401 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
emilmont 77:869cf507173a 2402 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
emilmont 77:869cf507173a 2403 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
emilmont 77:869cf507173a 2404 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
emilmont 77:869cf507173a 2405 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
emilmont 77:869cf507173a 2406 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
emilmont 77:869cf507173a 2407 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
emilmont 77:869cf507173a 2408 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
emilmont 77:869cf507173a 2409 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
emilmont 77:869cf507173a 2410 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
emilmont 77:869cf507173a 2411 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
emilmont 77:869cf507173a 2412 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
emilmont 77:869cf507173a 2413 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
emilmont 77:869cf507173a 2414 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
emilmont 77:869cf507173a 2415 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit 18 */
emilmont 77:869cf507173a 2416 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
emilmont 77:869cf507173a 2417 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit 20 */
emilmont 77:869cf507173a 2418 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit 21 */
emilmont 77:869cf507173a 2419 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit 22 */
emilmont 77:869cf507173a 2420 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit 23 */
emilmont 77:869cf507173a 2421
emilmont 77:869cf507173a 2422 /******************************************************************************/
emilmont 77:869cf507173a 2423 /* */
emilmont 77:869cf507173a 2424 /* FLASH, DATA EEPROM and Option Bytes Registers */
emilmont 77:869cf507173a 2425 /* (FLASH, DATA_EEPROM, OB) */
emilmont 77:869cf507173a 2426 /* */
emilmont 77:869cf507173a 2427 /******************************************************************************/
emilmont 77:869cf507173a 2428
emilmont 77:869cf507173a 2429 /******************* Bit definition for FLASH_ACR register ******************/
emilmont 77:869cf507173a 2430 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< Latency */
emilmont 77:869cf507173a 2431 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002) /*!< Prefetch Buffer Enable */
emilmont 77:869cf507173a 2432 #define FLASH_ACR_ACC64 ((uint32_t)0x00000004) /*!< Access 64 bits */
emilmont 77:869cf507173a 2433 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008) /*!< Flash mode during sleep mode */
emilmont 77:869cf507173a 2434 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010) /*!< Flash mode during RUN mode */
emilmont 77:869cf507173a 2435
emilmont 77:869cf507173a 2436 /******************* Bit definition for FLASH_PECR register ******************/
emilmont 77:869cf507173a 2437 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001) /*!< FLASH_PECR and Flash data Lock */
emilmont 77:869cf507173a 2438 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002) /*!< Program matrix Lock */
emilmont 77:869cf507173a 2439 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004) /*!< Option byte matrix Lock */
emilmont 77:869cf507173a 2440 #define FLASH_PECR_PROG ((uint32_t)0x00000008) /*!< Program matrix selection */
emilmont 77:869cf507173a 2441 #define FLASH_PECR_DATA ((uint32_t)0x00000010) /*!< Data matrix selection */
emilmont 77:869cf507173a 2442 #define FLASH_PECR_FTDW ((uint32_t)0x00000100) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
emilmont 77:869cf507173a 2443 #define FLASH_PECR_ERASE ((uint32_t)0x00000200) /*!< Page erasing mode */
emilmont 77:869cf507173a 2444 #define FLASH_PECR_FPRG ((uint32_t)0x00000400) /*!< Fast Page/Half Page programming mode */
emilmont 77:869cf507173a 2445 #define FLASH_PECR_PARALLBANK ((uint32_t)0x00008000) /*!< Parallel Bank mode */
emilmont 77:869cf507173a 2446 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000) /*!< End of programming interrupt */
emilmont 77:869cf507173a 2447 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000) /*!< Error interrupt */
emilmont 77:869cf507173a 2448 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000) /*!< Launch the option byte loading */
emilmont 77:869cf507173a 2449
emilmont 77:869cf507173a 2450 /****************** Bit definition for FLASH_PDKEYR register ******************/
emilmont 77:869cf507173a 2451 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
emilmont 77:869cf507173a 2452
emilmont 77:869cf507173a 2453 /****************** Bit definition for FLASH_PEKEYR register ******************/
emilmont 77:869cf507173a 2454 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFF) /*!< FLASH_PEC and data matrix Key */
emilmont 77:869cf507173a 2455
emilmont 77:869cf507173a 2456 /****************** Bit definition for FLASH_PRGKEYR register ******************/
emilmont 77:869cf507173a 2457 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFF) /*!< Program matrix Key */
emilmont 77:869cf507173a 2458
emilmont 77:869cf507173a 2459 /****************** Bit definition for FLASH_OPTKEYR register ******************/
emilmont 77:869cf507173a 2460 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option bytes matrix Key */
emilmont 77:869cf507173a 2461
emilmont 77:869cf507173a 2462 /****************** Bit definition for FLASH_SR register *******************/
emilmont 77:869cf507173a 2463 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
emilmont 77:869cf507173a 2464 #define FLASH_SR_EOP ((uint32_t)0x00000002) /*!< End Of Programming*/
emilmont 77:869cf507173a 2465 #define FLASH_SR_ENHV ((uint32_t)0x00000004) /*!< End of high voltage */
emilmont 77:869cf507173a 2466 #define FLASH_SR_READY ((uint32_t)0x00000008) /*!< Flash ready after low power mode */
emilmont 77:869cf507173a 2467
emilmont 77:869cf507173a 2468 #define FLASH_SR_WRPERR ((uint32_t)0x00000100) /*!< Write protected error */
emilmont 77:869cf507173a 2469 #define FLASH_SR_PGAERR ((uint32_t)0x00000200) /*!< Programming Alignment Error */
emilmont 77:869cf507173a 2470 #define FLASH_SR_SIZERR ((uint32_t)0x00000400) /*!< Size error */
emilmont 77:869cf507173a 2471 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800) /*!< Option validity error */
emilmont 77:869cf507173a 2472 #define FLASH_SR_OPTVERRUSR ((uint32_t)0x00001000) /*!< Option User validity error */
emilmont 77:869cf507173a 2473 #define FLASH_SR_RDERR ((uint32_t)0x00002000) /*!< Read protected error */
emilmont 77:869cf507173a 2474
emilmont 77:869cf507173a 2475 /****************** Bit definition for FLASH_OBR register *******************/
emilmont 77:869cf507173a 2476 #define FLASH_OBR_RDPRT ((uint32_t)0x000000AA) /*!< Read Protection */
emilmont 77:869cf507173a 2477 #define FLASH_OBR_SPRMOD ((uint32_t)0x00000100) /*!< Selection of protection mode of WPRi bits
emilmont 77:869cf507173a 2478 (available only in STM32L1xx Medium-density Plus devices) */
emilmont 77:869cf507173a 2479 #define FLASH_OBR_BOR_LEV ((uint32_t)0x000F0000) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
emilmont 77:869cf507173a 2480 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00100000) /*!< IWDG_SW */
emilmont 77:869cf507173a 2481 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00200000) /*!< nRST_STOP */
emilmont 77:869cf507173a 2482 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00400000) /*!< nRST_STDBY */
emilmont 77:869cf507173a 2483 #define FLASH_OBR_BFB2 ((uint32_t)0x00800000) /*!< BFB2(available only in STM32L1xx High-density devices) */
emilmont 77:869cf507173a 2484
emilmont 77:869cf507173a 2485 /****************** Bit definition for FLASH_WRPR register ******************/
emilmont 77:869cf507173a 2486 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits */
emilmont 77:869cf507173a 2487
emilmont 77:869cf507173a 2488 /****************** Bit definition for FLASH_WRPR1 register *****************/
emilmont 77:869cf507173a 2489 #define FLASH_WRPR1_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits (available only in STM32L1xx
emilmont 77:869cf507173a 2490 Medium-density Plus and High-density devices) */
emilmont 77:869cf507173a 2491
emilmont 77:869cf507173a 2492 /****************** Bit definition for FLASH_WRPR2 register *****************/
emilmont 77:869cf507173a 2493 #define FLASH_WRPR2_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protection bits (available only in STM32L1xx
emilmont 77:869cf507173a 2494 High-density devices) */
emilmont 77:869cf507173a 2495 /******************************************************************************/
emilmont 77:869cf507173a 2496 /* */
emilmont 77:869cf507173a 2497 /* Flexible Static Memory Controller */
emilmont 77:869cf507173a 2498 /* */
emilmont 77:869cf507173a 2499 /******************************************************************************/
emilmont 77:869cf507173a 2500 /****************** Bit definition for FSMC_BCR1 register *******************/
emilmont 77:869cf507173a 2501 #define FSMC_BCR1_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
emilmont 77:869cf507173a 2502 #define FSMC_BCR1_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
emilmont 77:869cf507173a 2503
emilmont 77:869cf507173a 2504 #define FSMC_BCR1_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
emilmont 77:869cf507173a 2505 #define FSMC_BCR1_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
emilmont 77:869cf507173a 2506 #define FSMC_BCR1_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
emilmont 77:869cf507173a 2507
emilmont 77:869cf507173a 2508 #define FSMC_BCR1_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
emilmont 77:869cf507173a 2509 #define FSMC_BCR1_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2510 #define FSMC_BCR1_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2511
emilmont 77:869cf507173a 2512 #define FSMC_BCR1_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
emilmont 77:869cf507173a 2513 #define FSMC_BCR1_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
emilmont 77:869cf507173a 2514 #define FSMC_BCR1_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
emilmont 77:869cf507173a 2515 #define FSMC_BCR1_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
emilmont 77:869cf507173a 2516 #define FSMC_BCR1_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
emilmont 77:869cf507173a 2517 #define FSMC_BCR1_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
emilmont 77:869cf507173a 2518 #define FSMC_BCR1_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
emilmont 77:869cf507173a 2519 #define FSMC_BCR1_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
emilmont 77:869cf507173a 2520 #define FSMC_BCR1_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
emilmont 77:869cf507173a 2521 #define FSMC_BCR1_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
emilmont 77:869cf507173a 2522
emilmont 77:869cf507173a 2523 /****************** Bit definition for FSMC_BCR2 register *******************/
emilmont 77:869cf507173a 2524 #define FSMC_BCR2_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
emilmont 77:869cf507173a 2525 #define FSMC_BCR2_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
emilmont 77:869cf507173a 2526
emilmont 77:869cf507173a 2527 #define FSMC_BCR2_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
emilmont 77:869cf507173a 2528 #define FSMC_BCR2_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
emilmont 77:869cf507173a 2529 #define FSMC_BCR2_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
emilmont 77:869cf507173a 2530
emilmont 77:869cf507173a 2531 #define FSMC_BCR2_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
emilmont 77:869cf507173a 2532 #define FSMC_BCR2_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2533 #define FSMC_BCR2_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2534
emilmont 77:869cf507173a 2535 #define FSMC_BCR2_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
emilmont 77:869cf507173a 2536 #define FSMC_BCR2_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
emilmont 77:869cf507173a 2537 #define FSMC_BCR2_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
emilmont 77:869cf507173a 2538 #define FSMC_BCR2_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
emilmont 77:869cf507173a 2539 #define FSMC_BCR2_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
emilmont 77:869cf507173a 2540 #define FSMC_BCR2_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
emilmont 77:869cf507173a 2541 #define FSMC_BCR2_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
emilmont 77:869cf507173a 2542 #define FSMC_BCR2_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
emilmont 77:869cf507173a 2543 #define FSMC_BCR2_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
emilmont 77:869cf507173a 2544 #define FSMC_BCR2_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
emilmont 77:869cf507173a 2545
emilmont 77:869cf507173a 2546 /****************** Bit definition for FSMC_BCR3 register *******************/
emilmont 77:869cf507173a 2547 #define FSMC_BCR3_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
emilmont 77:869cf507173a 2548 #define FSMC_BCR3_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
emilmont 77:869cf507173a 2549
emilmont 77:869cf507173a 2550 #define FSMC_BCR3_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
emilmont 77:869cf507173a 2551 #define FSMC_BCR3_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
emilmont 77:869cf507173a 2552 #define FSMC_BCR3_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
emilmont 77:869cf507173a 2553
emilmont 77:869cf507173a 2554 #define FSMC_BCR3_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
emilmont 77:869cf507173a 2555 #define FSMC_BCR3_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2556 #define FSMC_BCR3_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2557
emilmont 77:869cf507173a 2558 #define FSMC_BCR3_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
emilmont 77:869cf507173a 2559 #define FSMC_BCR3_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
emilmont 77:869cf507173a 2560 #define FSMC_BCR3_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit. */
emilmont 77:869cf507173a 2561 #define FSMC_BCR3_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
emilmont 77:869cf507173a 2562 #define FSMC_BCR3_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
emilmont 77:869cf507173a 2563 #define FSMC_BCR3_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
emilmont 77:869cf507173a 2564 #define FSMC_BCR3_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
emilmont 77:869cf507173a 2565 #define FSMC_BCR3_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
emilmont 77:869cf507173a 2566 #define FSMC_BCR3_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
emilmont 77:869cf507173a 2567 #define FSMC_BCR3_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
emilmont 77:869cf507173a 2568
emilmont 77:869cf507173a 2569 /****************** Bit definition for FSMC_BCR4 register *******************/
emilmont 77:869cf507173a 2570 #define FSMC_BCR4_MBKEN ((uint32_t)0x00000001) /*!< Memory bank enable bit */
emilmont 77:869cf507173a 2571 #define FSMC_BCR4_MUXEN ((uint32_t)0x00000002) /*!< Address/data multiplexing enable bit */
emilmont 77:869cf507173a 2572
emilmont 77:869cf507173a 2573 #define FSMC_BCR4_MTYP ((uint32_t)0x0000000C) /*!< MTYP[1:0] bits (Memory type) */
emilmont 77:869cf507173a 2574 #define FSMC_BCR4_MTYP_0 ((uint32_t)0x00000004) /*!< Bit 0 */
emilmont 77:869cf507173a 2575 #define FSMC_BCR4_MTYP_1 ((uint32_t)0x00000008) /*!< Bit 1 */
emilmont 77:869cf507173a 2576
emilmont 77:869cf507173a 2577 #define FSMC_BCR4_MWID ((uint32_t)0x00000030) /*!< MWID[1:0] bits (Memory data bus width) */
emilmont 77:869cf507173a 2578 #define FSMC_BCR4_MWID_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2579 #define FSMC_BCR4_MWID_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2580
emilmont 77:869cf507173a 2581 #define FSMC_BCR4_FACCEN ((uint32_t)0x00000040) /*!< Flash access enable */
emilmont 77:869cf507173a 2582 #define FSMC_BCR4_BURSTEN ((uint32_t)0x00000100) /*!< Burst enable bit */
emilmont 77:869cf507173a 2583 #define FSMC_BCR4_WAITPOL ((uint32_t)0x00000200) /*!< Wait signal polarity bit */
emilmont 77:869cf507173a 2584 #define FSMC_BCR4_WRAPMOD ((uint32_t)0x00000400) /*!< Wrapped burst mode support */
emilmont 77:869cf507173a 2585 #define FSMC_BCR4_WAITCFG ((uint32_t)0x00000800) /*!< Wait timing configuration */
emilmont 77:869cf507173a 2586 #define FSMC_BCR4_WREN ((uint32_t)0x00001000) /*!< Write enable bit */
emilmont 77:869cf507173a 2587 #define FSMC_BCR4_WAITEN ((uint32_t)0x00002000) /*!< Wait enable bit */
emilmont 77:869cf507173a 2588 #define FSMC_BCR4_EXTMOD ((uint32_t)0x00004000) /*!< Extended mode enable */
emilmont 77:869cf507173a 2589 #define FSMC_BCR4_ASYNCWAIT ((uint32_t)0x00008000) /*!< Asynchronous wait */
emilmont 77:869cf507173a 2590 #define FSMC_BCR4_CBURSTRW ((uint32_t)0x00080000) /*!< Write burst enable */
emilmont 77:869cf507173a 2591
emilmont 77:869cf507173a 2592 /****************** Bit definition for FSMC_BTR1 register ******************/
emilmont 77:869cf507173a 2593 #define FSMC_BTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
emilmont 77:869cf507173a 2594 #define FSMC_BTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2595 #define FSMC_BTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2596 #define FSMC_BTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 2597 #define FSMC_BTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 2598
emilmont 77:869cf507173a 2599 #define FSMC_BTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
emilmont 77:869cf507173a 2600 #define FSMC_BTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2601 #define FSMC_BTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2602 #define FSMC_BTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2603 #define FSMC_BTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2604
emilmont 77:869cf507173a 2605 #define FSMC_BTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
emilmont 77:869cf507173a 2606 #define FSMC_BTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 2607 #define FSMC_BTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 2608 #define FSMC_BTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 2609 #define FSMC_BTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 2610
emilmont 77:869cf507173a 2611 #define FSMC_BTR1_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
emilmont 77:869cf507173a 2612 #define FSMC_BTR1_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 2613 #define FSMC_BTR1_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 2614 #define FSMC_BTR1_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 2615 #define FSMC_BTR1_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 2616
emilmont 77:869cf507173a 2617 #define FSMC_BTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
emilmont 77:869cf507173a 2618 #define FSMC_BTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 2619 #define FSMC_BTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 2620 #define FSMC_BTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 2621 #define FSMC_BTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 2622
emilmont 77:869cf507173a 2623 #define FSMC_BTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
emilmont 77:869cf507173a 2624 #define FSMC_BTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2625 #define FSMC_BTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2626 #define FSMC_BTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 2627 #define FSMC_BTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 2628
emilmont 77:869cf507173a 2629 #define FSMC_BTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
emilmont 77:869cf507173a 2630 #define FSMC_BTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2631 #define FSMC_BTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2632
emilmont 77:869cf507173a 2633 /****************** Bit definition for FSMC_BTR2 register *******************/
emilmont 77:869cf507173a 2634 #define FSMC_BTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
emilmont 77:869cf507173a 2635 #define FSMC_BTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2636 #define FSMC_BTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2637 #define FSMC_BTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 2638 #define FSMC_BTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 2639
emilmont 77:869cf507173a 2640 #define FSMC_BTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
emilmont 77:869cf507173a 2641 #define FSMC_BTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2642 #define FSMC_BTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2643 #define FSMC_BTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2644 #define FSMC_BTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2645
emilmont 77:869cf507173a 2646 #define FSMC_BTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
emilmont 77:869cf507173a 2647 #define FSMC_BTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 2648 #define FSMC_BTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 2649 #define FSMC_BTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 2650 #define FSMC_BTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 2651
emilmont 77:869cf507173a 2652 #define FSMC_BTR2_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
emilmont 77:869cf507173a 2653 #define FSMC_BTR2_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 2654 #define FSMC_BTR2_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 2655 #define FSMC_BTR2_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 2656 #define FSMC_BTR2_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 2657
emilmont 77:869cf507173a 2658 #define FSMC_BTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
emilmont 77:869cf507173a 2659 #define FSMC_BTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 2660 #define FSMC_BTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 2661 #define FSMC_BTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 2662 #define FSMC_BTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 2663
emilmont 77:869cf507173a 2664 #define FSMC_BTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
emilmont 77:869cf507173a 2665 #define FSMC_BTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2666 #define FSMC_BTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2667 #define FSMC_BTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 2668 #define FSMC_BTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 2669
emilmont 77:869cf507173a 2670 #define FSMC_BTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
emilmont 77:869cf507173a 2671 #define FSMC_BTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2672 #define FSMC_BTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2673
emilmont 77:869cf507173a 2674 /******************* Bit definition for FSMC_BTR3 register *******************/
emilmont 77:869cf507173a 2675 #define FSMC_BTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
emilmont 77:869cf507173a 2676 #define FSMC_BTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2677 #define FSMC_BTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2678 #define FSMC_BTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 2679 #define FSMC_BTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 2680
emilmont 77:869cf507173a 2681 #define FSMC_BTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
emilmont 77:869cf507173a 2682 #define FSMC_BTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2683 #define FSMC_BTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2684 #define FSMC_BTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2685 #define FSMC_BTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2686
emilmont 77:869cf507173a 2687 #define FSMC_BTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
emilmont 77:869cf507173a 2688 #define FSMC_BTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 2689 #define FSMC_BTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 2690 #define FSMC_BTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 2691 #define FSMC_BTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 2692
emilmont 77:869cf507173a 2693 #define FSMC_BTR3_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
emilmont 77:869cf507173a 2694 #define FSMC_BTR3_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 2695 #define FSMC_BTR3_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 2696 #define FSMC_BTR3_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 2697 #define FSMC_BTR3_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 2698
emilmont 77:869cf507173a 2699 #define FSMC_BTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
emilmont 77:869cf507173a 2700 #define FSMC_BTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 2701 #define FSMC_BTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 2702 #define FSMC_BTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 2703 #define FSMC_BTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 2704
emilmont 77:869cf507173a 2705 #define FSMC_BTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
emilmont 77:869cf507173a 2706 #define FSMC_BTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2707 #define FSMC_BTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2708 #define FSMC_BTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 2709 #define FSMC_BTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 2710
emilmont 77:869cf507173a 2711 #define FSMC_BTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
emilmont 77:869cf507173a 2712 #define FSMC_BTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2713 #define FSMC_BTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2714
emilmont 77:869cf507173a 2715 /****************** Bit definition for FSMC_BTR4 register *******************/
emilmont 77:869cf507173a 2716 #define FSMC_BTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
emilmont 77:869cf507173a 2717 #define FSMC_BTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2718 #define FSMC_BTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2719 #define FSMC_BTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 2720 #define FSMC_BTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 2721
emilmont 77:869cf507173a 2722 #define FSMC_BTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
emilmont 77:869cf507173a 2723 #define FSMC_BTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2724 #define FSMC_BTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2725 #define FSMC_BTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2726 #define FSMC_BTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2727
emilmont 77:869cf507173a 2728 #define FSMC_BTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
emilmont 77:869cf507173a 2729 #define FSMC_BTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 2730 #define FSMC_BTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 2731 #define FSMC_BTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 2732 #define FSMC_BTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 2733
emilmont 77:869cf507173a 2734 #define FSMC_BTR4_BUSTURN ((uint32_t)0x000F0000) /*!< BUSTURN[3:0] bits (Bus turnaround phase duration) */
emilmont 77:869cf507173a 2735 #define FSMC_BTR4_BUSTURN_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 2736 #define FSMC_BTR4_BUSTURN_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 2737 #define FSMC_BTR4_BUSTURN_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 2738 #define FSMC_BTR4_BUSTURN_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 2739
emilmont 77:869cf507173a 2740 #define FSMC_BTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
emilmont 77:869cf507173a 2741 #define FSMC_BTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 2742 #define FSMC_BTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 2743 #define FSMC_BTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 2744 #define FSMC_BTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 2745
emilmont 77:869cf507173a 2746 #define FSMC_BTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
emilmont 77:869cf507173a 2747 #define FSMC_BTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2748 #define FSMC_BTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2749 #define FSMC_BTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 2750 #define FSMC_BTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 2751
emilmont 77:869cf507173a 2752 #define FSMC_BTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
emilmont 77:869cf507173a 2753 #define FSMC_BTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2754 #define FSMC_BTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2755
emilmont 77:869cf507173a 2756 /****************** Bit definition for FSMC_BWTR1 register ******************/
emilmont 77:869cf507173a 2757 #define FSMC_BWTR1_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
emilmont 77:869cf507173a 2758 #define FSMC_BWTR1_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2759 #define FSMC_BWTR1_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2760 #define FSMC_BWTR1_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 2761 #define FSMC_BWTR1_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 2762
emilmont 77:869cf507173a 2763 #define FSMC_BWTR1_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
emilmont 77:869cf507173a 2764 #define FSMC_BWTR1_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2765 #define FSMC_BWTR1_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2766 #define FSMC_BWTR1_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2767 #define FSMC_BWTR1_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2768
emilmont 77:869cf507173a 2769 #define FSMC_BWTR1_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
emilmont 77:869cf507173a 2770 #define FSMC_BWTR1_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 2771 #define FSMC_BWTR1_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 2772 #define FSMC_BWTR1_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 2773 #define FSMC_BWTR1_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 2774
emilmont 77:869cf507173a 2775 #define FSMC_BWTR1_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
emilmont 77:869cf507173a 2776 #define FSMC_BWTR1_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 2777 #define FSMC_BWTR1_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 2778 #define FSMC_BWTR1_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 2779 #define FSMC_BWTR1_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 2780
emilmont 77:869cf507173a 2781 #define FSMC_BWTR1_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
emilmont 77:869cf507173a 2782 #define FSMC_BWTR1_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2783 #define FSMC_BWTR1_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2784 #define FSMC_BWTR1_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 2785 #define FSMC_BWTR1_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 2786
emilmont 77:869cf507173a 2787 #define FSMC_BWTR1_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
emilmont 77:869cf507173a 2788 #define FSMC_BWTR1_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2789 #define FSMC_BWTR1_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2790
emilmont 77:869cf507173a 2791 /****************** Bit definition for FSMC_BWTR2 register ******************/
emilmont 77:869cf507173a 2792 #define FSMC_BWTR2_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
emilmont 77:869cf507173a 2793 #define FSMC_BWTR2_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2794 #define FSMC_BWTR2_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2795 #define FSMC_BWTR2_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 2796 #define FSMC_BWTR2_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 2797
emilmont 77:869cf507173a 2798 #define FSMC_BWTR2_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
emilmont 77:869cf507173a 2799 #define FSMC_BWTR2_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2800 #define FSMC_BWTR2_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2801 #define FSMC_BWTR2_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2802 #define FSMC_BWTR2_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2803
emilmont 77:869cf507173a 2804 #define FSMC_BWTR2_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
emilmont 77:869cf507173a 2805 #define FSMC_BWTR2_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 2806 #define FSMC_BWTR2_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 2807 #define FSMC_BWTR2_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 2808 #define FSMC_BWTR2_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 2809
emilmont 77:869cf507173a 2810 #define FSMC_BWTR2_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
emilmont 77:869cf507173a 2811 #define FSMC_BWTR2_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 2812 #define FSMC_BWTR2_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1*/
emilmont 77:869cf507173a 2813 #define FSMC_BWTR2_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 2814 #define FSMC_BWTR2_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 2815
emilmont 77:869cf507173a 2816 #define FSMC_BWTR2_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
emilmont 77:869cf507173a 2817 #define FSMC_BWTR2_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2818 #define FSMC_BWTR2_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2819 #define FSMC_BWTR2_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 2820 #define FSMC_BWTR2_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 2821
emilmont 77:869cf507173a 2822 #define FSMC_BWTR2_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
emilmont 77:869cf507173a 2823 #define FSMC_BWTR2_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2824 #define FSMC_BWTR2_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2825
emilmont 77:869cf507173a 2826 /****************** Bit definition for FSMC_BWTR3 register ******************/
emilmont 77:869cf507173a 2827 #define FSMC_BWTR3_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
emilmont 77:869cf507173a 2828 #define FSMC_BWTR3_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2829 #define FSMC_BWTR3_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2830 #define FSMC_BWTR3_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 2831 #define FSMC_BWTR3_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 2832
emilmont 77:869cf507173a 2833 #define FSMC_BWTR3_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
emilmont 77:869cf507173a 2834 #define FSMC_BWTR3_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2835 #define FSMC_BWTR3_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2836 #define FSMC_BWTR3_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2837 #define FSMC_BWTR3_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2838
emilmont 77:869cf507173a 2839 #define FSMC_BWTR3_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
emilmont 77:869cf507173a 2840 #define FSMC_BWTR3_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 2841 #define FSMC_BWTR3_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 2842 #define FSMC_BWTR3_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 2843 #define FSMC_BWTR3_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 2844
emilmont 77:869cf507173a 2845 #define FSMC_BWTR3_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
emilmont 77:869cf507173a 2846 #define FSMC_BWTR3_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 2847 #define FSMC_BWTR3_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 2848 #define FSMC_BWTR3_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 2849 #define FSMC_BWTR3_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 2850
emilmont 77:869cf507173a 2851 #define FSMC_BWTR3_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
emilmont 77:869cf507173a 2852 #define FSMC_BWTR3_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2853 #define FSMC_BWTR3_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2854 #define FSMC_BWTR3_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 2855 #define FSMC_BWTR3_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 2856
emilmont 77:869cf507173a 2857 #define FSMC_BWTR3_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
emilmont 77:869cf507173a 2858 #define FSMC_BWTR3_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2859 #define FSMC_BWTR3_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2860
emilmont 77:869cf507173a 2861 /****************** Bit definition for FSMC_BWTR4 register ******************/
emilmont 77:869cf507173a 2862 #define FSMC_BWTR4_ADDSET ((uint32_t)0x0000000F) /*!< ADDSET[3:0] bits (Address setup phase duration) */
emilmont 77:869cf507173a 2863 #define FSMC_BWTR4_ADDSET_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 2864 #define FSMC_BWTR4_ADDSET_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 2865 #define FSMC_BWTR4_ADDSET_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 2866 #define FSMC_BWTR4_ADDSET_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 2867
emilmont 77:869cf507173a 2868 #define FSMC_BWTR4_ADDHLD ((uint32_t)0x000000F0) /*!< ADDHLD[3:0] bits (Address-hold phase duration) */
emilmont 77:869cf507173a 2869 #define FSMC_BWTR4_ADDHLD_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 2870 #define FSMC_BWTR4_ADDHLD_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 2871 #define FSMC_BWTR4_ADDHLD_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 2872 #define FSMC_BWTR4_ADDHLD_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 2873
emilmont 77:869cf507173a 2874 #define FSMC_BWTR4_DATAST ((uint32_t)0x0000FF00) /*!< DATAST [3:0] bits (Data-phase duration) */
emilmont 77:869cf507173a 2875 #define FSMC_BWTR4_DATAST_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 2876 #define FSMC_BWTR4_DATAST_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 2877 #define FSMC_BWTR4_DATAST_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 2878 #define FSMC_BWTR4_DATAST_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 2879
emilmont 77:869cf507173a 2880 #define FSMC_BWTR4_CLKDIV ((uint32_t)0x00F00000) /*!< CLKDIV[3:0] bits (Clock divide ratio) */
emilmont 77:869cf507173a 2881 #define FSMC_BWTR4_CLKDIV_0 ((uint32_t)0x00100000) /*!< Bit 0 */
emilmont 77:869cf507173a 2882 #define FSMC_BWTR4_CLKDIV_1 ((uint32_t)0x00200000) /*!< Bit 1 */
emilmont 77:869cf507173a 2883 #define FSMC_BWTR4_CLKDIV_2 ((uint32_t)0x00400000) /*!< Bit 2 */
emilmont 77:869cf507173a 2884 #define FSMC_BWTR4_CLKDIV_3 ((uint32_t)0x00800000) /*!< Bit 3 */
emilmont 77:869cf507173a 2885
emilmont 77:869cf507173a 2886 #define FSMC_BWTR4_DATLAT ((uint32_t)0x0F000000) /*!< DATLA[3:0] bits (Data latency) */
emilmont 77:869cf507173a 2887 #define FSMC_BWTR4_DATLAT_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2888 #define FSMC_BWTR4_DATLAT_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2889 #define FSMC_BWTR4_DATLAT_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 2890 #define FSMC_BWTR4_DATLAT_3 ((uint32_t)0x08000000) /*!< Bit 3 */
emilmont 77:869cf507173a 2891
emilmont 77:869cf507173a 2892 #define FSMC_BWTR4_ACCMOD ((uint32_t)0x30000000) /*!< ACCMOD[1:0] bits (Access mode) */
emilmont 77:869cf507173a 2893 #define FSMC_BWTR4_ACCMOD_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 2894 #define FSMC_BWTR4_ACCMOD_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 2895
emilmont 77:869cf507173a 2896 /******************************************************************************/
emilmont 77:869cf507173a 2897 /* */
emilmont 77:869cf507173a 2898 /* General Purpose IOs (GPIO) */
emilmont 77:869cf507173a 2899 /* */
emilmont 77:869cf507173a 2900 /******************************************************************************/
emilmont 77:869cf507173a 2901 /******************* Bit definition for GPIO_MODER register *****************/
emilmont 77:869cf507173a 2902 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
emilmont 77:869cf507173a 2903 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2904 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2905 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
emilmont 77:869cf507173a 2906 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2907 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2908 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
emilmont 77:869cf507173a 2909 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2910 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2911 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
emilmont 77:869cf507173a 2912 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2913 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2914 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
emilmont 77:869cf507173a 2915 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2916 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2917 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
emilmont 77:869cf507173a 2918 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2919 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2920 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
emilmont 77:869cf507173a 2921 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2922 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2923 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
emilmont 77:869cf507173a 2924 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2925 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2926 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
emilmont 77:869cf507173a 2927 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2928 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2929 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
emilmont 77:869cf507173a 2930 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2931 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 2932 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
emilmont 77:869cf507173a 2933 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 2934 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 2935 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
emilmont 77:869cf507173a 2936 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 2937 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 2938 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
emilmont 77:869cf507173a 2939 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 2940 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 2941 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
emilmont 77:869cf507173a 2942 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 2943 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 2944 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
emilmont 77:869cf507173a 2945 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 2946 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 2947 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
emilmont 77:869cf507173a 2948 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 2949 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 2950
emilmont 77:869cf507173a 2951 /******************* Bit definition for GPIO_OTYPER register ****************/
emilmont 77:869cf507173a 2952 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2953 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2954 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2955 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2956 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2957 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2958 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2959 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2960 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2961 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2962 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2963 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2964 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2965 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2966 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2967 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2968
emilmont 77:869cf507173a 2969 /******************* Bit definition for GPIO_OSPEEDR register ***************/
emilmont 77:869cf507173a 2970 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
emilmont 77:869cf507173a 2971 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 2972 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 2973 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
emilmont 77:869cf507173a 2974 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 2975 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 2976 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
emilmont 77:869cf507173a 2977 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 2978 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 2979 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
emilmont 77:869cf507173a 2980 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 2981 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 2982 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
emilmont 77:869cf507173a 2983 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 2984 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 2985 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
emilmont 77:869cf507173a 2986 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 2987 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 2988 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
emilmont 77:869cf507173a 2989 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 2990 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 2991 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
emilmont 77:869cf507173a 2992 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 2993 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 2994 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
emilmont 77:869cf507173a 2995 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 2996 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 2997 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
emilmont 77:869cf507173a 2998 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 2999 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 3000 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
emilmont 77:869cf507173a 3001 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 3002 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 3003 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
emilmont 77:869cf507173a 3004 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3005 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 3006 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
emilmont 77:869cf507173a 3007 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 3008 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 3009 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
emilmont 77:869cf507173a 3010 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 3011 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 3012 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
emilmont 77:869cf507173a 3013 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 3014 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 3015 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
emilmont 77:869cf507173a 3016 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 3017 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 3018
emilmont 77:869cf507173a 3019 /******************* Bit definition for GPIO_PUPDR register *****************/
emilmont 77:869cf507173a 3020 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
emilmont 77:869cf507173a 3021 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3022 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3023 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
emilmont 77:869cf507173a 3024 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3025 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3026 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
emilmont 77:869cf507173a 3027 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3028 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3029 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
emilmont 77:869cf507173a 3030 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3031 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3032 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
emilmont 77:869cf507173a 3033 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3034 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3035 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
emilmont 77:869cf507173a 3036 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3037 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3038 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
emilmont 77:869cf507173a 3039 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3040 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3041 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
emilmont 77:869cf507173a 3042 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3043 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3044 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
emilmont 77:869cf507173a 3045 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3046 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 3047 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
emilmont 77:869cf507173a 3048 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 3049 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 3050 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
emilmont 77:869cf507173a 3051 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 3052 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 3053 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
emilmont 77:869cf507173a 3054 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3055 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 3056 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
emilmont 77:869cf507173a 3057 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 3058 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 3059 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
emilmont 77:869cf507173a 3060 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 3061 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 3062 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
emilmont 77:869cf507173a 3063 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 3064 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 3065 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
emilmont 77:869cf507173a 3066 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 3067 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 3068
emilmont 77:869cf507173a 3069 /****************** Bits definition for GPIO_IDR register *******************/
emilmont 77:869cf507173a 3070 #define GPIO_IDR_IDR_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3071 #define GPIO_IDR_IDR_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3072 #define GPIO_IDR_IDR_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3073 #define GPIO_IDR_IDR_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3074 #define GPIO_IDR_IDR_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3075 #define GPIO_IDR_IDR_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3076 #define GPIO_IDR_IDR_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3077 #define GPIO_IDR_IDR_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3078 #define GPIO_IDR_IDR_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3079 #define GPIO_IDR_IDR_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3080 #define GPIO_IDR_IDR_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3081 #define GPIO_IDR_IDR_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3082 #define GPIO_IDR_IDR_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3083 #define GPIO_IDR_IDR_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3084 #define GPIO_IDR_IDR_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3085 #define GPIO_IDR_IDR_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3086 /* Old GPIO_IDR register bits definition, maintained for legacy purpose */
emilmont 77:869cf507173a 3087 #define GPIO_OTYPER_IDR_0 GPIO_IDR_IDR_0
emilmont 77:869cf507173a 3088 #define GPIO_OTYPER_IDR_1 GPIO_IDR_IDR_1
emilmont 77:869cf507173a 3089 #define GPIO_OTYPER_IDR_2 GPIO_IDR_IDR_2
emilmont 77:869cf507173a 3090 #define GPIO_OTYPER_IDR_3 GPIO_IDR_IDR_3
emilmont 77:869cf507173a 3091 #define GPIO_OTYPER_IDR_4 GPIO_IDR_IDR_4
emilmont 77:869cf507173a 3092 #define GPIO_OTYPER_IDR_5 GPIO_IDR_IDR_5
emilmont 77:869cf507173a 3093 #define GPIO_OTYPER_IDR_6 GPIO_IDR_IDR_6
emilmont 77:869cf507173a 3094 #define GPIO_OTYPER_IDR_7 GPIO_IDR_IDR_7
emilmont 77:869cf507173a 3095 #define GPIO_OTYPER_IDR_8 GPIO_IDR_IDR_8
emilmont 77:869cf507173a 3096 #define GPIO_OTYPER_IDR_9 GPIO_IDR_IDR_9
emilmont 77:869cf507173a 3097 #define GPIO_OTYPER_IDR_10 GPIO_IDR_IDR_10
emilmont 77:869cf507173a 3098 #define GPIO_OTYPER_IDR_11 GPIO_IDR_IDR_11
emilmont 77:869cf507173a 3099 #define GPIO_OTYPER_IDR_12 GPIO_IDR_IDR_12
emilmont 77:869cf507173a 3100 #define GPIO_OTYPER_IDR_13 GPIO_IDR_IDR_13
emilmont 77:869cf507173a 3101 #define GPIO_OTYPER_IDR_14 GPIO_IDR_IDR_14
emilmont 77:869cf507173a 3102 #define GPIO_OTYPER_IDR_15 GPIO_IDR_IDR_15
emilmont 77:869cf507173a 3103
emilmont 77:869cf507173a 3104 /****************** Bits definition for GPIO_ODR register *******************/
emilmont 77:869cf507173a 3105 #define GPIO_ODR_ODR_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3106 #define GPIO_ODR_ODR_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3107 #define GPIO_ODR_ODR_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3108 #define GPIO_ODR_ODR_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3109 #define GPIO_ODR_ODR_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3110 #define GPIO_ODR_ODR_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3111 #define GPIO_ODR_ODR_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3112 #define GPIO_ODR_ODR_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3113 #define GPIO_ODR_ODR_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3114 #define GPIO_ODR_ODR_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3115 #define GPIO_ODR_ODR_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3116 #define GPIO_ODR_ODR_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3117 #define GPIO_ODR_ODR_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3118 #define GPIO_ODR_ODR_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3119 #define GPIO_ODR_ODR_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3120 #define GPIO_ODR_ODR_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3121 /* Old GPIO_ODR register bits definition, maintained for legacy purpose */
emilmont 77:869cf507173a 3122 #define GPIO_OTYPER_ODR_0 GPIO_ODR_ODR_0
emilmont 77:869cf507173a 3123 #define GPIO_OTYPER_ODR_1 GPIO_ODR_ODR_1
emilmont 77:869cf507173a 3124 #define GPIO_OTYPER_ODR_2 GPIO_ODR_ODR_2
emilmont 77:869cf507173a 3125 #define GPIO_OTYPER_ODR_3 GPIO_ODR_ODR_3
emilmont 77:869cf507173a 3126 #define GPIO_OTYPER_ODR_4 GPIO_ODR_ODR_4
emilmont 77:869cf507173a 3127 #define GPIO_OTYPER_ODR_5 GPIO_ODR_ODR_5
emilmont 77:869cf507173a 3128 #define GPIO_OTYPER_ODR_6 GPIO_ODR_ODR_6
emilmont 77:869cf507173a 3129 #define GPIO_OTYPER_ODR_7 GPIO_ODR_ODR_7
emilmont 77:869cf507173a 3130 #define GPIO_OTYPER_ODR_8 GPIO_ODR_ODR_8
emilmont 77:869cf507173a 3131 #define GPIO_OTYPER_ODR_9 GPIO_ODR_ODR_9
emilmont 77:869cf507173a 3132 #define GPIO_OTYPER_ODR_10 GPIO_ODR_ODR_10
emilmont 77:869cf507173a 3133 #define GPIO_OTYPER_ODR_11 GPIO_ODR_ODR_11
emilmont 77:869cf507173a 3134 #define GPIO_OTYPER_ODR_12 GPIO_ODR_ODR_12
emilmont 77:869cf507173a 3135 #define GPIO_OTYPER_ODR_13 GPIO_ODR_ODR_13
emilmont 77:869cf507173a 3136 #define GPIO_OTYPER_ODR_14 GPIO_ODR_ODR_14
emilmont 77:869cf507173a 3137 #define GPIO_OTYPER_ODR_15 GPIO_ODR_ODR_15
emilmont 77:869cf507173a 3138
emilmont 77:869cf507173a 3139 /******************* Bit definition for GPIO_BSRR register ******************/
emilmont 77:869cf507173a 3140 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3141 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3142 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3143 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3144 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3145 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3146 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3147 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3148 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3149 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3150 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3151 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3152 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3153 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3154 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3155 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3156 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3157 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 3158 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 3159 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 3160 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 3161 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 3162 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3163 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 3164 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 3165 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 3166 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 3167 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 3168 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 3169 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 3170 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
emilmont 77:869cf507173a 3171 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 3172
emilmont 77:869cf507173a 3173 /******************* Bit definition for GPIO_LCKR register ******************/
emilmont 77:869cf507173a 3174 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3175 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3176 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3177 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3178 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3179 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3180 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3181 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3182 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3183 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3184 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3185 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3186 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3187 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3188 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3189 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3190 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3191
emilmont 77:869cf507173a 3192 /******************* Bit definition for GPIO_AFRL register ******************/
emilmont 77:869cf507173a 3193 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 3194 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
emilmont 77:869cf507173a 3195 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 3196 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
emilmont 77:869cf507173a 3197 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 3198 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
emilmont 77:869cf507173a 3199 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 3200 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
emilmont 77:869cf507173a 3201
emilmont 77:869cf507173a 3202 /******************* Bit definition for GPIO_AFRH register ******************/
emilmont 77:869cf507173a 3203 #define GPIO_AFRH_AFRH8 ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 3204 #define GPIO_AFRH_AFRH9 ((uint32_t)0x000000F0)
emilmont 77:869cf507173a 3205 #define GPIO_AFRH_AFRH10 ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 3206 #define GPIO_AFRH_AFRH11 ((uint32_t)0x0000F000)
emilmont 77:869cf507173a 3207 #define GPIO_AFRH_AFRH12 ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 3208 #define GPIO_AFRH_AFRH13 ((uint32_t)0x00F00000)
emilmont 77:869cf507173a 3209 #define GPIO_AFRH_AFRH14 ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 3210 #define GPIO_AFRH_AFRH15 ((uint32_t)0xF0000000)
emilmont 77:869cf507173a 3211
emilmont 77:869cf507173a 3212 /******************************************************************************/
emilmont 77:869cf507173a 3213 /* */
emilmont 77:869cf507173a 3214 /* Inter-integrated Circuit Interface (I2C) */
emilmont 77:869cf507173a 3215 /* */
emilmont 77:869cf507173a 3216 /******************************************************************************/
emilmont 77:869cf507173a 3217
emilmont 77:869cf507173a 3218 /******************* Bit definition for I2C_CR1 register ********************/
emilmont 77:869cf507173a 3219 #define I2C_CR1_PE ((uint16_t)0x0001) /*!< Peripheral Enable */
emilmont 77:869cf507173a 3220 #define I2C_CR1_SMBUS ((uint16_t)0x0002) /*!< SMBus Mode */
emilmont 77:869cf507173a 3221 #define I2C_CR1_SMBTYPE ((uint16_t)0x0008) /*!< SMBus Type */
emilmont 77:869cf507173a 3222 #define I2C_CR1_ENARP ((uint16_t)0x0010) /*!< ARP Enable */
emilmont 77:869cf507173a 3223 #define I2C_CR1_ENPEC ((uint16_t)0x0020) /*!< PEC Enable */
emilmont 77:869cf507173a 3224 #define I2C_CR1_ENGC ((uint16_t)0x0040) /*!< General Call Enable */
emilmont 77:869cf507173a 3225 #define I2C_CR1_NOSTRETCH ((uint16_t)0x0080) /*!< Clock Stretching Disable (Slave mode) */
emilmont 77:869cf507173a 3226 #define I2C_CR1_START ((uint16_t)0x0100) /*!< Start Generation */
emilmont 77:869cf507173a 3227 #define I2C_CR1_STOP ((uint16_t)0x0200) /*!< Stop Generation */
emilmont 77:869cf507173a 3228 #define I2C_CR1_ACK ((uint16_t)0x0400) /*!< Acknowledge Enable */
emilmont 77:869cf507173a 3229 #define I2C_CR1_POS ((uint16_t)0x0800) /*!< Acknowledge/PEC Position (for data reception) */
emilmont 77:869cf507173a 3230 #define I2C_CR1_PEC ((uint16_t)0x1000) /*!< Packet Error Checking */
emilmont 77:869cf507173a 3231 #define I2C_CR1_ALERT ((uint16_t)0x2000) /*!< SMBus Alert */
emilmont 77:869cf507173a 3232 #define I2C_CR1_SWRST ((uint16_t)0x8000) /*!< Software Reset */
emilmont 77:869cf507173a 3233
emilmont 77:869cf507173a 3234 /******************* Bit definition for I2C_CR2 register ********************/
emilmont 77:869cf507173a 3235 #define I2C_CR2_FREQ ((uint16_t)0x003F) /*!< FREQ[5:0] bits (Peripheral Clock Frequency) */
emilmont 77:869cf507173a 3236 #define I2C_CR2_FREQ_0 ((uint16_t)0x0001) /*!< Bit 0 */
emilmont 77:869cf507173a 3237 #define I2C_CR2_FREQ_1 ((uint16_t)0x0002) /*!< Bit 1 */
emilmont 77:869cf507173a 3238 #define I2C_CR2_FREQ_2 ((uint16_t)0x0004) /*!< Bit 2 */
emilmont 77:869cf507173a 3239 #define I2C_CR2_FREQ_3 ((uint16_t)0x0008) /*!< Bit 3 */
emilmont 77:869cf507173a 3240 #define I2C_CR2_FREQ_4 ((uint16_t)0x0010) /*!< Bit 4 */
emilmont 77:869cf507173a 3241 #define I2C_CR2_FREQ_5 ((uint16_t)0x0020) /*!< Bit 5 */
emilmont 77:869cf507173a 3242
emilmont 77:869cf507173a 3243 #define I2C_CR2_ITERREN ((uint16_t)0x0100) /*!< Error Interrupt Enable */
emilmont 77:869cf507173a 3244 #define I2C_CR2_ITEVTEN ((uint16_t)0x0200) /*!< Event Interrupt Enable */
emilmont 77:869cf507173a 3245 #define I2C_CR2_ITBUFEN ((uint16_t)0x0400) /*!< Buffer Interrupt Enable */
emilmont 77:869cf507173a 3246 #define I2C_CR2_DMAEN ((uint16_t)0x0800) /*!< DMA Requests Enable */
emilmont 77:869cf507173a 3247 #define I2C_CR2_LAST ((uint16_t)0x1000) /*!< DMA Last Transfer */
emilmont 77:869cf507173a 3248
emilmont 77:869cf507173a 3249 /******************* Bit definition for I2C_OAR1 register *******************/
emilmont 77:869cf507173a 3250 #define I2C_OAR1_ADD1_7 ((uint16_t)0x00FE) /*!< Interface Address */
emilmont 77:869cf507173a 3251 #define I2C_OAR1_ADD8_9 ((uint16_t)0x0300) /*!< Interface Address */
emilmont 77:869cf507173a 3252
emilmont 77:869cf507173a 3253 #define I2C_OAR1_ADD0 ((uint16_t)0x0001) /*!< Bit 0 */
emilmont 77:869cf507173a 3254 #define I2C_OAR1_ADD1 ((uint16_t)0x0002) /*!< Bit 1 */
emilmont 77:869cf507173a 3255 #define I2C_OAR1_ADD2 ((uint16_t)0x0004) /*!< Bit 2 */
emilmont 77:869cf507173a 3256 #define I2C_OAR1_ADD3 ((uint16_t)0x0008) /*!< Bit 3 */
emilmont 77:869cf507173a 3257 #define I2C_OAR1_ADD4 ((uint16_t)0x0010) /*!< Bit 4 */
emilmont 77:869cf507173a 3258 #define I2C_OAR1_ADD5 ((uint16_t)0x0020) /*!< Bit 5 */
emilmont 77:869cf507173a 3259 #define I2C_OAR1_ADD6 ((uint16_t)0x0040) /*!< Bit 6 */
emilmont 77:869cf507173a 3260 #define I2C_OAR1_ADD7 ((uint16_t)0x0080) /*!< Bit 7 */
emilmont 77:869cf507173a 3261 #define I2C_OAR1_ADD8 ((uint16_t)0x0100) /*!< Bit 8 */
emilmont 77:869cf507173a 3262 #define I2C_OAR1_ADD9 ((uint16_t)0x0200) /*!< Bit 9 */
emilmont 77:869cf507173a 3263
emilmont 77:869cf507173a 3264 #define I2C_OAR1_ADDMODE ((uint16_t)0x8000) /*!< Addressing Mode (Slave mode) */
emilmont 77:869cf507173a 3265
emilmont 77:869cf507173a 3266 /******************* Bit definition for I2C_OAR2 register *******************/
emilmont 77:869cf507173a 3267 #define I2C_OAR2_ENDUAL ((uint8_t)0x01) /*!< Dual addressing mode enable */
emilmont 77:869cf507173a 3268 #define I2C_OAR2_ADD2 ((uint8_t)0xFE) /*!< Interface address */
emilmont 77:869cf507173a 3269
emilmont 77:869cf507173a 3270 /******************** Bit definition for I2C_DR register ********************/
emilmont 77:869cf507173a 3271 #define I2C_DR_DR ((uint8_t)0xFF) /*!< 8-bit Data Register */
emilmont 77:869cf507173a 3272
emilmont 77:869cf507173a 3273 /******************* Bit definition for I2C_SR1 register ********************/
emilmont 77:869cf507173a 3274 #define I2C_SR1_SB ((uint16_t)0x0001) /*!< Start Bit (Master mode) */
emilmont 77:869cf507173a 3275 #define I2C_SR1_ADDR ((uint16_t)0x0002) /*!< Address sent (master mode)/matched (slave mode) */
emilmont 77:869cf507173a 3276 #define I2C_SR1_BTF ((uint16_t)0x0004) /*!< Byte Transfer Finished */
emilmont 77:869cf507173a 3277 #define I2C_SR1_ADD10 ((uint16_t)0x0008) /*!< 10-bit header sent (Master mode) */
emilmont 77:869cf507173a 3278 #define I2C_SR1_STOPF ((uint16_t)0x0010) /*!< Stop detection (Slave mode) */
emilmont 77:869cf507173a 3279 #define I2C_SR1_RXNE ((uint16_t)0x0040) /*!< Data Register not Empty (receivers) */
emilmont 77:869cf507173a 3280 #define I2C_SR1_TXE ((uint16_t)0x0080) /*!< Data Register Empty (transmitters) */
emilmont 77:869cf507173a 3281 #define I2C_SR1_BERR ((uint16_t)0x0100) /*!< Bus Error */
emilmont 77:869cf507173a 3282 #define I2C_SR1_ARLO ((uint16_t)0x0200) /*!< Arbitration Lost (master mode) */
emilmont 77:869cf507173a 3283 #define I2C_SR1_AF ((uint16_t)0x0400) /*!< Acknowledge Failure */
emilmont 77:869cf507173a 3284 #define I2C_SR1_OVR ((uint16_t)0x0800) /*!< Overrun/Underrun */
emilmont 77:869cf507173a 3285 #define I2C_SR1_PECERR ((uint16_t)0x1000) /*!< PEC Error in reception */
emilmont 77:869cf507173a 3286 #define I2C_SR1_TIMEOUT ((uint16_t)0x4000) /*!< Timeout or Tlow Error */
emilmont 77:869cf507173a 3287 #define I2C_SR1_SMBALERT ((uint16_t)0x8000) /*!< SMBus Alert */
emilmont 77:869cf507173a 3288
emilmont 77:869cf507173a 3289 /******************* Bit definition for I2C_SR2 register ********************/
emilmont 77:869cf507173a 3290 #define I2C_SR2_MSL ((uint16_t)0x0001) /*!< Master/Slave */
emilmont 77:869cf507173a 3291 #define I2C_SR2_BUSY ((uint16_t)0x0002) /*!< Bus Busy */
emilmont 77:869cf507173a 3292 #define I2C_SR2_TRA ((uint16_t)0x0004) /*!< Transmitter/Receiver */
emilmont 77:869cf507173a 3293 #define I2C_SR2_GENCALL ((uint16_t)0x0010) /*!< General Call Address (Slave mode) */
emilmont 77:869cf507173a 3294 #define I2C_SR2_SMBDEFAULT ((uint16_t)0x0020) /*!< SMBus Device Default Address (Slave mode) */
emilmont 77:869cf507173a 3295 #define I2C_SR2_SMBHOST ((uint16_t)0x0040) /*!< SMBus Host Header (Slave mode) */
emilmont 77:869cf507173a 3296 #define I2C_SR2_DUALF ((uint16_t)0x0080) /*!< Dual Flag (Slave mode) */
emilmont 77:869cf507173a 3297 #define I2C_SR2_PEC ((uint16_t)0xFF00) /*!< Packet Error Checking Register */
emilmont 77:869cf507173a 3298
emilmont 77:869cf507173a 3299 /******************* Bit definition for I2C_CCR register ********************/
emilmont 77:869cf507173a 3300 #define I2C_CCR_CCR ((uint16_t)0x0FFF) /*!< Clock Control Register in Fast/Standard mode (Master mode) */
emilmont 77:869cf507173a 3301 #define I2C_CCR_DUTY ((uint16_t)0x4000) /*!< Fast Mode Duty Cycle */
emilmont 77:869cf507173a 3302 #define I2C_CCR_FS ((uint16_t)0x8000) /*!< I2C Master Mode Selection */
emilmont 77:869cf507173a 3303
emilmont 77:869cf507173a 3304 /****************** Bit definition for I2C_TRISE register *******************/
emilmont 77:869cf507173a 3305 #define I2C_TRISE_TRISE ((uint8_t)0x3F) /*!< Maximum Rise Time in Fast/Standard mode (Master mode) */
emilmont 77:869cf507173a 3306
emilmont 77:869cf507173a 3307 /******************************************************************************/
emilmont 77:869cf507173a 3308 /* */
emilmont 77:869cf507173a 3309 /* Independent WATCHDOG (IWDG) */
emilmont 77:869cf507173a 3310 /* */
emilmont 77:869cf507173a 3311 /******************************************************************************/
emilmont 77:869cf507173a 3312
emilmont 77:869cf507173a 3313 /******************* Bit definition for IWDG_KR register ********************/
emilmont 77:869cf507173a 3314 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
emilmont 77:869cf507173a 3315
emilmont 77:869cf507173a 3316 /******************* Bit definition for IWDG_PR register ********************/
emilmont 77:869cf507173a 3317 #define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
emilmont 77:869cf507173a 3318 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
emilmont 77:869cf507173a 3319 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
emilmont 77:869cf507173a 3320 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
emilmont 77:869cf507173a 3321
emilmont 77:869cf507173a 3322 /******************* Bit definition for IWDG_RLR register *******************/
emilmont 77:869cf507173a 3323 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
emilmont 77:869cf507173a 3324
emilmont 77:869cf507173a 3325 /******************* Bit definition for IWDG_SR register ********************/
emilmont 77:869cf507173a 3326 #define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
emilmont 77:869cf507173a 3327 #define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
emilmont 77:869cf507173a 3328
emilmont 77:869cf507173a 3329 /******************************************************************************/
emilmont 77:869cf507173a 3330 /* */
emilmont 77:869cf507173a 3331 /* LCD Controller (LCD) */
emilmont 77:869cf507173a 3332 /* */
emilmont 77:869cf507173a 3333 /******************************************************************************/
emilmont 77:869cf507173a 3334
emilmont 77:869cf507173a 3335 /******************* Bit definition for LCD_CR register *********************/
emilmont 77:869cf507173a 3336 #define LCD_CR_LCDEN ((uint32_t)0x00000001) /*!< LCD Enable Bit */
emilmont 77:869cf507173a 3337 #define LCD_CR_VSEL ((uint32_t)0x00000002) /*!< Voltage source selector Bit */
emilmont 77:869cf507173a 3338
emilmont 77:869cf507173a 3339 #define LCD_CR_DUTY ((uint32_t)0x0000001C) /*!< DUTY[2:0] bits (Duty selector) */
emilmont 77:869cf507173a 3340 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004) /*!< Duty selector Bit 0 */
emilmont 77:869cf507173a 3341 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008) /*!< Duty selector Bit 1 */
emilmont 77:869cf507173a 3342 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010) /*!< Duty selector Bit 2 */
emilmont 77:869cf507173a 3343
emilmont 77:869cf507173a 3344 #define LCD_CR_BIAS ((uint32_t)0x00000060) /*!< BIAS[1:0] bits (Bias selector) */
emilmont 77:869cf507173a 3345 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020) /*!< Bias selector Bit 0 */
emilmont 77:869cf507173a 3346 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040) /*!< Bias selector Bit 1 */
emilmont 77:869cf507173a 3347
emilmont 77:869cf507173a 3348 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080) /*!< Mux Segment Enable Bit */
emilmont 77:869cf507173a 3349
emilmont 77:869cf507173a 3350 /******************* Bit definition for LCD_FCR register ********************/
emilmont 77:869cf507173a 3351 #define LCD_FCR_HD ((uint32_t)0x00000001) /*!< High Drive Enable Bit */
emilmont 77:869cf507173a 3352 #define LCD_FCR_SOFIE ((uint32_t)0x00000002) /*!< Start of Frame Interrupt Enable Bit */
emilmont 77:869cf507173a 3353 #define LCD_FCR_UDDIE ((uint32_t)0x00000008) /*!< Update Display Done Interrupt Enable Bit */
emilmont 77:869cf507173a 3354
emilmont 77:869cf507173a 3355 #define LCD_FCR_PON ((uint32_t)0x00000070) /*!< PON[2:0] bits (Puls ON Duration) */
emilmont 77:869cf507173a 3356 #define LCD_FCR_PON_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 3357 #define LCD_FCR_PON_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 3358 #define LCD_FCR_PON_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 3359
emilmont 77:869cf507173a 3360 #define LCD_FCR_DEAD ((uint32_t)0x00000380) /*!< DEAD[2:0] bits (DEAD Time) */
emilmont 77:869cf507173a 3361 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080) /*!< Bit 0 */
emilmont 77:869cf507173a 3362 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100) /*!< Bit 1 */
emilmont 77:869cf507173a 3363 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200) /*!< Bit 2 */
emilmont 77:869cf507173a 3364
emilmont 77:869cf507173a 3365 #define LCD_FCR_CC ((uint32_t)0x00001C00) /*!< CC[2:0] bits (Contrast Control) */
emilmont 77:869cf507173a 3366 #define LCD_FCR_CC_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 3367 #define LCD_FCR_CC_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 3368 #define LCD_FCR_CC_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 3369
emilmont 77:869cf507173a 3370 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000) /*!< BLINKF[2:0] bits (Blink Frequency) */
emilmont 77:869cf507173a 3371 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000) /*!< Bit 0 */
emilmont 77:869cf507173a 3372 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000) /*!< Bit 1 */
emilmont 77:869cf507173a 3373 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000) /*!< Bit 2 */
emilmont 77:869cf507173a 3374
emilmont 77:869cf507173a 3375 #define LCD_FCR_BLINK ((uint32_t)0x00030000) /*!< BLINK[1:0] bits (Blink Enable) */
emilmont 77:869cf507173a 3376 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 3377 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 3378
emilmont 77:869cf507173a 3379 #define LCD_FCR_DIV ((uint32_t)0x003C0000) /*!< DIV[3:0] bits (Divider) */
emilmont 77:869cf507173a 3380 #define LCD_FCR_PS ((uint32_t)0x03C00000) /*!< PS[3:0] bits (Prescaler) */
emilmont 77:869cf507173a 3381
emilmont 77:869cf507173a 3382 /******************* Bit definition for LCD_SR register *********************/
emilmont 77:869cf507173a 3383 #define LCD_SR_ENS ((uint32_t)0x00000001) /*!< LCD Enabled Bit */
emilmont 77:869cf507173a 3384 #define LCD_SR_SOF ((uint32_t)0x00000002) /*!< Start Of Frame Flag Bit */
emilmont 77:869cf507173a 3385 #define LCD_SR_UDR ((uint32_t)0x00000004) /*!< Update Display Request Bit */
emilmont 77:869cf507173a 3386 #define LCD_SR_UDD ((uint32_t)0x00000008) /*!< Update Display Done Flag Bit */
emilmont 77:869cf507173a 3387 #define LCD_SR_RDY ((uint32_t)0x00000010) /*!< Ready Flag Bit */
emilmont 77:869cf507173a 3388 #define LCD_SR_FCRSR ((uint32_t)0x00000020) /*!< LCD FCR Register Synchronization Flag Bit */
emilmont 77:869cf507173a 3389
emilmont 77:869cf507173a 3390 /******************* Bit definition for LCD_CLR register ********************/
emilmont 77:869cf507173a 3391 #define LCD_CLR_SOFC ((uint32_t)0x00000002) /*!< Start Of Frame Flag Clear Bit */
emilmont 77:869cf507173a 3392 #define LCD_CLR_UDDC ((uint32_t)0x00000008) /*!< Update Display Done Flag Clear Bit */
emilmont 77:869cf507173a 3393
emilmont 77:869cf507173a 3394 /******************* Bit definition for LCD_RAM register ********************/
emilmont 77:869cf507173a 3395 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFF) /*!< Segment Data Bits */
emilmont 77:869cf507173a 3396
emilmont 77:869cf507173a 3397 /******************************************************************************/
emilmont 77:869cf507173a 3398 /* */
emilmont 77:869cf507173a 3399 /* Power Control (PWR) */
emilmont 77:869cf507173a 3400 /* */
emilmont 77:869cf507173a 3401 /******************************************************************************/
emilmont 77:869cf507173a 3402
emilmont 77:869cf507173a 3403 /******************** Bit definition for PWR_CR register ********************/
emilmont 77:869cf507173a 3404 #define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */
emilmont 77:869cf507173a 3405 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
emilmont 77:869cf507173a 3406 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
emilmont 77:869cf507173a 3407 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
emilmont 77:869cf507173a 3408 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
emilmont 77:869cf507173a 3409
emilmont 77:869cf507173a 3410 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
emilmont 77:869cf507173a 3411 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
emilmont 77:869cf507173a 3412 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
emilmont 77:869cf507173a 3413 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
emilmont 77:869cf507173a 3414
emilmont 77:869cf507173a 3415 /*!< PVD level configuration */
emilmont 77:869cf507173a 3416 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
emilmont 77:869cf507173a 3417 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
emilmont 77:869cf507173a 3418 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
emilmont 77:869cf507173a 3419 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
emilmont 77:869cf507173a 3420 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
emilmont 77:869cf507173a 3421 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
emilmont 77:869cf507173a 3422 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
emilmont 77:869cf507173a 3423 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
emilmont 77:869cf507173a 3424
emilmont 77:869cf507173a 3425 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
emilmont 77:869cf507173a 3426 #define PWR_CR_ULP ((uint16_t)0x0200) /*!< Ultra Low Power mode */
emilmont 77:869cf507173a 3427 #define PWR_CR_FWU ((uint16_t)0x0400) /*!< Fast wakeup */
emilmont 77:869cf507173a 3428
emilmont 77:869cf507173a 3429 #define PWR_CR_VOS ((uint16_t)0x1800) /*!< VOS[1:0] bits (Voltage scaling range selection) */
emilmont 77:869cf507173a 3430 #define PWR_CR_VOS_0 ((uint16_t)0x0800) /*!< Bit 0 */
emilmont 77:869cf507173a 3431 #define PWR_CR_VOS_1 ((uint16_t)0x1000) /*!< Bit 1 */
emilmont 77:869cf507173a 3432 #define PWR_CR_LPRUN ((uint16_t)0x4000) /*!< Low power run mode */
emilmont 77:869cf507173a 3433
emilmont 77:869cf507173a 3434 /******************* Bit definition for PWR_CSR register ********************/
emilmont 77:869cf507173a 3435 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
emilmont 77:869cf507173a 3436 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
emilmont 77:869cf507173a 3437 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
emilmont 77:869cf507173a 3438 #define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */
emilmont 77:869cf507173a 3439 #define PWR_CSR_VOSF ((uint16_t)0x0010) /*!< Voltage Scaling select flag */
emilmont 77:869cf507173a 3440 #define PWR_CSR_REGLPF ((uint16_t)0x0020) /*!< Regulator LP flag */
emilmont 77:869cf507173a 3441
emilmont 77:869cf507173a 3442 #define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
emilmont 77:869cf507173a 3443 #define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
emilmont 77:869cf507173a 3444 #define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
emilmont 77:869cf507173a 3445
emilmont 77:869cf507173a 3446 /******************************************************************************/
emilmont 77:869cf507173a 3447 /* */
emilmont 77:869cf507173a 3448 /* Reset and Clock Control (RCC) */
emilmont 77:869cf507173a 3449 /* */
emilmont 77:869cf507173a 3450 /******************************************************************************/
emilmont 77:869cf507173a 3451 /******************** Bit definition for RCC_CR register ********************/
emilmont 77:869cf507173a 3452 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
emilmont 77:869cf507173a 3453 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
emilmont 77:869cf507173a 3454
emilmont 77:869cf507173a 3455 #define RCC_CR_MSION ((uint32_t)0x00000100) /*!< Internal Multi Speed clock enable */
emilmont 77:869cf507173a 3456 #define RCC_CR_MSIRDY ((uint32_t)0x00000200) /*!< Internal Multi Speed clock ready flag */
emilmont 77:869cf507173a 3457
emilmont 77:869cf507173a 3458 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
emilmont 77:869cf507173a 3459 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
emilmont 77:869cf507173a 3460 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
emilmont 77:869cf507173a 3461
emilmont 77:869cf507173a 3462 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
emilmont 77:869cf507173a 3463 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
emilmont 77:869cf507173a 3464 #define RCC_CR_CSSON ((uint32_t)0x10000000) /*!< Clock Security System enable */
emilmont 77:869cf507173a 3465
emilmont 77:869cf507173a 3466 #define RCC_CR_RTCPRE ((uint32_t)0x60000000) /*!< RTC/LCD Prescaler */
emilmont 77:869cf507173a 3467 #define RCC_CR_RTCPRE_0 ((uint32_t)0x20000000) /*!< Bit0 */
emilmont 77:869cf507173a 3468 #define RCC_CR_RTCPRE_1 ((uint32_t)0x40000000) /*!< Bit1 */
emilmont 77:869cf507173a 3469
emilmont 77:869cf507173a 3470 /******************** Bit definition for RCC_ICSCR register *****************/
emilmont 77:869cf507173a 3471 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FF) /*!< Internal High Speed clock Calibration */
emilmont 77:869cf507173a 3472 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00) /*!< Internal High Speed clock trimming */
emilmont 77:869cf507173a 3473
emilmont 77:869cf507173a 3474 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000) /*!< Internal Multi Speed clock Range */
emilmont 77:869cf507173a 3475 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000) /*!< Internal Multi Speed clock Range 65.536 KHz */
emilmont 77:869cf507173a 3476 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000) /*!< Internal Multi Speed clock Range 131.072 KHz */
emilmont 77:869cf507173a 3477 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000) /*!< Internal Multi Speed clock Range 262.144 KHz */
emilmont 77:869cf507173a 3478 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000) /*!< Internal Multi Speed clock Range 524.288 KHz */
emilmont 77:869cf507173a 3479 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000) /*!< Internal Multi Speed clock Range 1.048 MHz */
emilmont 77:869cf507173a 3480 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000) /*!< Internal Multi Speed clock Range 2.097 MHz */
emilmont 77:869cf507173a 3481 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000) /*!< Internal Multi Speed clock Range 4.194 MHz */
emilmont 77:869cf507173a 3482 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000) /*!< Internal Multi Speed clock Calibration */
emilmont 77:869cf507173a 3483 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000) /*!< Internal Multi Speed clock trimming */
emilmont 77:869cf507173a 3484
emilmont 77:869cf507173a 3485 /******************** Bit definition for RCC_CFGR register ******************/
emilmont 77:869cf507173a 3486 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
emilmont 77:869cf507173a 3487 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 3488 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 3489
emilmont 77:869cf507173a 3490 /*!< SW configuration */
emilmont 77:869cf507173a 3491 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000) /*!< MSI selected as system clock */
emilmont 77:869cf507173a 3492 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001) /*!< HSI selected as system clock */
emilmont 77:869cf507173a 3493 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /*!< HSE selected as system clock */
emilmont 77:869cf507173a 3494 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003) /*!< PLL selected as system clock */
emilmont 77:869cf507173a 3495
emilmont 77:869cf507173a 3496 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
emilmont 77:869cf507173a 3497 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
emilmont 77:869cf507173a 3498 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
emilmont 77:869cf507173a 3499
emilmont 77:869cf507173a 3500 /*!< SWS configuration */
emilmont 77:869cf507173a 3501 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000) /*!< MSI oscillator used as system clock */
emilmont 77:869cf507173a 3502 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004) /*!< HSI oscillator used as system clock */
emilmont 77:869cf507173a 3503 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008) /*!< HSE oscillator used as system clock */
emilmont 77:869cf507173a 3504 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000C) /*!< PLL used as system clock */
emilmont 77:869cf507173a 3505
emilmont 77:869cf507173a 3506 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
emilmont 77:869cf507173a 3507 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 3508 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 3509 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 3510 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 3511
emilmont 77:869cf507173a 3512 /*!< HPRE configuration */
emilmont 77:869cf507173a 3513 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
emilmont 77:869cf507173a 3514 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
emilmont 77:869cf507173a 3515 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
emilmont 77:869cf507173a 3516 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
emilmont 77:869cf507173a 3517 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
emilmont 77:869cf507173a 3518 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
emilmont 77:869cf507173a 3519 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
emilmont 77:869cf507173a 3520 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
emilmont 77:869cf507173a 3521 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
emilmont 77:869cf507173a 3522
emilmont 77:869cf507173a 3523 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
emilmont 77:869cf507173a 3524 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 3525 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 3526 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 3527
emilmont 77:869cf507173a 3528 /*!< PPRE1 configuration */
emilmont 77:869cf507173a 3529 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
emilmont 77:869cf507173a 3530 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
emilmont 77:869cf507173a 3531 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
emilmont 77:869cf507173a 3532 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
emilmont 77:869cf507173a 3533 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
emilmont 77:869cf507173a 3534
emilmont 77:869cf507173a 3535 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
emilmont 77:869cf507173a 3536 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
emilmont 77:869cf507173a 3537 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
emilmont 77:869cf507173a 3538 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
emilmont 77:869cf507173a 3539
emilmont 77:869cf507173a 3540 /*!< PPRE2 configuration */
emilmont 77:869cf507173a 3541 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
emilmont 77:869cf507173a 3542 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
emilmont 77:869cf507173a 3543 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
emilmont 77:869cf507173a 3544 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
emilmont 77:869cf507173a 3545 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
emilmont 77:869cf507173a 3546
emilmont 77:869cf507173a 3547 /*!< PLL entry clock source*/
emilmont 77:869cf507173a 3548 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
emilmont 77:869cf507173a 3549
emilmont 77:869cf507173a 3550 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI as PLL entry clock source */
emilmont 77:869cf507173a 3551 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000) /*!< HSE as PLL entry clock source */
emilmont 77:869cf507173a 3552
emilmont 77:869cf507173a 3553
emilmont 77:869cf507173a 3554 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
emilmont 77:869cf507173a 3555 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
emilmont 77:869cf507173a 3556 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
emilmont 77:869cf507173a 3557 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
emilmont 77:869cf507173a 3558 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
emilmont 77:869cf507173a 3559
emilmont 77:869cf507173a 3560 /*!< PLLMUL configuration */
emilmont 77:869cf507173a 3561 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000) /*!< PLL input clock * 3 */
emilmont 77:869cf507173a 3562 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000) /*!< PLL input clock * 4 */
emilmont 77:869cf507173a 3563 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000) /*!< PLL input clock * 6 */
emilmont 77:869cf507173a 3564 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000) /*!< PLL input clock * 8 */
emilmont 77:869cf507173a 3565 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000) /*!< PLL input clock * 12 */
emilmont 77:869cf507173a 3566 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000) /*!< PLL input clock * 16 */
emilmont 77:869cf507173a 3567 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000) /*!< PLL input clock * 24 */
emilmont 77:869cf507173a 3568 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000) /*!< PLL input clock * 32 */
emilmont 77:869cf507173a 3569 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000) /*!< PLL input clock * 48 */
emilmont 77:869cf507173a 3570
emilmont 77:869cf507173a 3571 /*!< PLLDIV configuration */
emilmont 77:869cf507173a 3572 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000) /*!< PLLDIV[1:0] bits (PLL Output Division) */
emilmont 77:869cf507173a 3573 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000) /*!< Bit0 */
emilmont 77:869cf507173a 3574 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000) /*!< Bit1 */
emilmont 77:869cf507173a 3575
emilmont 77:869cf507173a 3576
emilmont 77:869cf507173a 3577 /*!< PLLDIV configuration */
emilmont 77:869cf507173a 3578 #define RCC_CFGR_PLLDIV1 ((uint32_t)0x00000000) /*!< PLL clock output = CKVCO / 1 */
emilmont 77:869cf507173a 3579 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000) /*!< PLL clock output = CKVCO / 2 */
emilmont 77:869cf507173a 3580 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000) /*!< PLL clock output = CKVCO / 3 */
emilmont 77:869cf507173a 3581 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000) /*!< PLL clock output = CKVCO / 4 */
emilmont 77:869cf507173a 3582
emilmont 77:869cf507173a 3583
emilmont 77:869cf507173a 3584 #define RCC_CFGR_MCOSEL ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
emilmont 77:869cf507173a 3585 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000) /*!< Bit 0 */
emilmont 77:869cf507173a 3586 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000) /*!< Bit 1 */
emilmont 77:869cf507173a 3587 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000) /*!< Bit 2 */
emilmont 77:869cf507173a 3588
emilmont 77:869cf507173a 3589 /*!< MCO configuration */
emilmont 77:869cf507173a 3590 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
emilmont 77:869cf507173a 3591 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000) /*!< System clock selected */
emilmont 77:869cf507173a 3592 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000) /*!< Internal 16 MHz RC oscillator clock selected */
emilmont 77:869cf507173a 3593 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000) /*!< Internal Medium Speed RC oscillator clock selected */
emilmont 77:869cf507173a 3594 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000) /*!< External 1-25 MHz oscillator clock selected */
emilmont 77:869cf507173a 3595 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000) /*!< PLL clock divided */
emilmont 77:869cf507173a 3596 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000) /*!< LSI selected */
emilmont 77:869cf507173a 3597 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000) /*!< LSE selected */
emilmont 77:869cf507173a 3598
emilmont 77:869cf507173a 3599 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000) /*!< MCOPRE[2:0] bits (Microcontroller Clock Output Prescaler) */
emilmont 77:869cf507173a 3600 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000) /*!< Bit 0 */
emilmont 77:869cf507173a 3601 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000) /*!< Bit 1 */
emilmont 77:869cf507173a 3602 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000) /*!< Bit 2 */
emilmont 77:869cf507173a 3603
emilmont 77:869cf507173a 3604 /*!< MCO Prescaler configuration */
emilmont 77:869cf507173a 3605 #define RCC_CFGR_MCO_DIV1 ((uint32_t)0x00000000) /*!< MCO Clock divided by 1 */
emilmont 77:869cf507173a 3606 #define RCC_CFGR_MCO_DIV2 ((uint32_t)0x10000000) /*!< MCO Clock divided by 2 */
emilmont 77:869cf507173a 3607 #define RCC_CFGR_MCO_DIV4 ((uint32_t)0x20000000) /*!< MCO Clock divided by 4 */
emilmont 77:869cf507173a 3608 #define RCC_CFGR_MCO_DIV8 ((uint32_t)0x30000000) /*!< MCO Clock divided by 8 */
emilmont 77:869cf507173a 3609 #define RCC_CFGR_MCO_DIV16 ((uint32_t)0x40000000) /*!< MCO Clock divided by 16 */
emilmont 77:869cf507173a 3610
emilmont 77:869cf507173a 3611 /*!<****************** Bit definition for RCC_CIR register ********************/
emilmont 77:869cf507173a 3612 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
emilmont 77:869cf507173a 3613 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
emilmont 77:869cf507173a 3614 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
emilmont 77:869cf507173a 3615 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
emilmont 77:869cf507173a 3616 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
emilmont 77:869cf507173a 3617 #define RCC_CIR_MSIRDYF ((uint32_t)0x00000020) /*!< MSI Ready Interrupt flag */
emilmont 77:869cf507173a 3618 #define RCC_CIR_LSECSS ((uint32_t)0x00000040) /*!< LSE CSS Interrupt flag */
emilmont 77:869cf507173a 3619 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
emilmont 77:869cf507173a 3620
emilmont 77:869cf507173a 3621 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
emilmont 77:869cf507173a 3622 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
emilmont 77:869cf507173a 3623 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
emilmont 77:869cf507173a 3624 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
emilmont 77:869cf507173a 3625 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
emilmont 77:869cf507173a 3626 #define RCC_CIR_MSIRDYIE ((uint32_t)0x00002000) /*!< MSI Ready Interrupt Enable */
emilmont 77:869cf507173a 3627 #define RCC_CIR_LSECSSIE ((uint32_t)0x00004000) /*!< LSE CSS Interrupt Enable */
emilmont 77:869cf507173a 3628
emilmont 77:869cf507173a 3629 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
emilmont 77:869cf507173a 3630 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
emilmont 77:869cf507173a 3631 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
emilmont 77:869cf507173a 3632 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
emilmont 77:869cf507173a 3633 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
emilmont 77:869cf507173a 3634 #define RCC_CIR_MSIRDYC ((uint32_t)0x00200000) /*!< MSI Ready Interrupt Clear */
emilmont 77:869cf507173a 3635 #define RCC_CIR_LSECSSC ((uint32_t)0x00400000) /*!< LSE CSS Interrupt Clear */
emilmont 77:869cf507173a 3636 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
emilmont 77:869cf507173a 3637
emilmont 77:869cf507173a 3638
emilmont 77:869cf507173a 3639 /***************** Bit definition for RCC_AHBRSTR register ******************/
emilmont 77:869cf507173a 3640 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00000001) /*!< GPIO port A reset */
emilmont 77:869cf507173a 3641 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00000002) /*!< GPIO port B reset */
emilmont 77:869cf507173a 3642 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00000004) /*!< GPIO port C reset */
emilmont 77:869cf507173a 3643 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00000008) /*!< GPIO port D reset */
emilmont 77:869cf507173a 3644 #define RCC_AHBRSTR_GPIOERST ((uint32_t)0x00000010) /*!< GPIO port E reset */
emilmont 77:869cf507173a 3645 #define RCC_AHBRSTR_GPIOHRST ((uint32_t)0x00000020) /*!< GPIO port H reset */
emilmont 77:869cf507173a 3646 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00000040) /*!< GPIO port F reset */
emilmont 77:869cf507173a 3647 #define RCC_AHBRSTR_GPIOGRST ((uint32_t)0x00000080) /*!< GPIO port G reset */
emilmont 77:869cf507173a 3648 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000) /*!< CRC reset */
emilmont 77:869cf507173a 3649 #define RCC_AHBRSTR_FLITFRST ((uint32_t)0x00008000) /*!< FLITF reset */
emilmont 77:869cf507173a 3650 #define RCC_AHBRSTR_DMA1RST ((uint32_t)0x01000000) /*!< DMA1 reset */
emilmont 77:869cf507173a 3651 #define RCC_AHBRSTR_DMA2RST ((uint32_t)0x02000000) /*!< DMA2 reset */
emilmont 77:869cf507173a 3652 #define RCC_AHBRSTR_AESRST ((uint32_t)0x08000000) /*!< AES reset */
emilmont 77:869cf507173a 3653 #define RCC_AHBRSTR_FSMCRST ((uint32_t)0x40000000) /*!< FSMC reset */
emilmont 77:869cf507173a 3654
emilmont 77:869cf507173a 3655 /***************** Bit definition for RCC_APB2RSTR register *****************/
emilmont 77:869cf507173a 3656 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< System Configuration SYSCFG reset */
emilmont 77:869cf507173a 3657 #define RCC_APB2RSTR_TIM9RST ((uint32_t)0x00000004) /*!< TIM9 reset */
emilmont 77:869cf507173a 3658 #define RCC_APB2RSTR_TIM10RST ((uint32_t)0x00000008) /*!< TIM10 reset */
emilmont 77:869cf507173a 3659 #define RCC_APB2RSTR_TIM11RST ((uint32_t)0x00000010) /*!< TIM11 reset */
emilmont 77:869cf507173a 3660 #define RCC_APB2RSTR_ADC1RST ((uint32_t)0x00000200) /*!< ADC1 reset */
emilmont 77:869cf507173a 3661 #define RCC_APB2RSTR_SDIORST ((uint32_t)0x00000800) /*!< SDIO reset */
emilmont 77:869cf507173a 3662 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
emilmont 77:869cf507173a 3663 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
emilmont 77:869cf507173a 3664
emilmont 77:869cf507173a 3665 /***************** Bit definition for RCC_APB1RSTR register *****************/
emilmont 77:869cf507173a 3666 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
emilmont 77:869cf507173a 3667 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
emilmont 77:869cf507173a 3668 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
emilmont 77:869cf507173a 3669 #define RCC_APB1RSTR_TIM5RST ((uint32_t)0x00000008) /*!< Timer 5 reset */
emilmont 77:869cf507173a 3670 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
emilmont 77:869cf507173a 3671 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
emilmont 77:869cf507173a 3672 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200) /*!< LCD reset */
emilmont 77:869cf507173a 3673 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
emilmont 77:869cf507173a 3674 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI 2 reset */
emilmont 77:869cf507173a 3675 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI 3 reset */
emilmont 77:869cf507173a 3676 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
emilmont 77:869cf507173a 3677 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
emilmont 77:869cf507173a 3678 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
emilmont 77:869cf507173a 3679 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
emilmont 77:869cf507173a 3680 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
emilmont 77:869cf507173a 3681 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
emilmont 77:869cf507173a 3682 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
emilmont 77:869cf507173a 3683 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< Power interface reset */
emilmont 77:869cf507173a 3684 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000) /*!< DAC interface reset */
emilmont 77:869cf507173a 3685 #define RCC_APB1RSTR_COMPRST ((uint32_t)0x80000000) /*!< Comparator interface reset */
emilmont 77:869cf507173a 3686
emilmont 77:869cf507173a 3687 /****************** Bit definition for RCC_AHBENR register ******************/
emilmont 77:869cf507173a 3688 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00000001) /*!< GPIO port A clock enable */
emilmont 77:869cf507173a 3689 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00000002) /*!< GPIO port B clock enable */
emilmont 77:869cf507173a 3690 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00000004) /*!< GPIO port C clock enable */
emilmont 77:869cf507173a 3691 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00000008) /*!< GPIO port D clock enable */
emilmont 77:869cf507173a 3692 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00000010) /*!< GPIO port E clock enable */
emilmont 77:869cf507173a 3693 #define RCC_AHBENR_GPIOHEN ((uint32_t)0x00000020) /*!< GPIO port H clock enable */
emilmont 77:869cf507173a 3694 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00000040) /*!< GPIO port F clock enable */
emilmont 77:869cf507173a 3695 #define RCC_AHBENR_GPIOGEN ((uint32_t)0x00000080) /*!< GPIO port G clock enable */
emilmont 77:869cf507173a 3696 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000) /*!< CRC clock enable */
emilmont 77:869cf507173a 3697 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00008000) /*!< FLITF clock enable (has effect only when
emilmont 77:869cf507173a 3698 the Flash memory is in power down mode) */
emilmont 77:869cf507173a 3699 #define RCC_AHBENR_DMA1EN ((uint32_t)0x01000000) /*!< DMA1 clock enable */
emilmont 77:869cf507173a 3700 #define RCC_AHBENR_DMA2EN ((uint32_t)0x02000000) /*!< DMA2 clock enable */
emilmont 77:869cf507173a 3701 #define RCC_AHBENR_AESEN ((uint32_t)0x08000000) /*!< AES clock enable */
emilmont 77:869cf507173a 3702 #define RCC_AHBENR_FSMCEN ((uint32_t)0x40000000) /*!< FSMC clock enable */
emilmont 77:869cf507173a 3703
emilmont 77:869cf507173a 3704
emilmont 77:869cf507173a 3705 /****************** Bit definition for RCC_APB2ENR register *****************/
emilmont 77:869cf507173a 3706 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enable */
emilmont 77:869cf507173a 3707 #define RCC_APB2ENR_TIM9EN ((uint32_t)0x00000004) /*!< TIM9 interface clock enable */
emilmont 77:869cf507173a 3708 #define RCC_APB2ENR_TIM10EN ((uint32_t)0x00000008) /*!< TIM10 interface clock enable */
emilmont 77:869cf507173a 3709 #define RCC_APB2ENR_TIM11EN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enable */
emilmont 77:869cf507173a 3710 #define RCC_APB2ENR_ADC1EN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
emilmont 77:869cf507173a 3711 #define RCC_APB2ENR_SDIOEN ((uint32_t)0x00000800) /*!< SDIO clock enable */
emilmont 77:869cf507173a 3712 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
emilmont 77:869cf507173a 3713 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
emilmont 77:869cf507173a 3714
emilmont 77:869cf507173a 3715
emilmont 77:869cf507173a 3716 /***************** Bit definition for RCC_APB1ENR register ******************/
emilmont 77:869cf507173a 3717 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled*/
emilmont 77:869cf507173a 3718 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
emilmont 77:869cf507173a 3719 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
emilmont 77:869cf507173a 3720 #define RCC_APB1ENR_TIM5EN ((uint32_t)0x00000008) /*!< Timer 5 clock enable */
emilmont 77:869cf507173a 3721 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
emilmont 77:869cf507173a 3722 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
emilmont 77:869cf507173a 3723 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200) /*!< LCD clock enable */
emilmont 77:869cf507173a 3724 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
emilmont 77:869cf507173a 3725 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI 2 clock enable */
emilmont 77:869cf507173a 3726 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI 3 clock enable */
emilmont 77:869cf507173a 3727 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
emilmont 77:869cf507173a 3728 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
emilmont 77:869cf507173a 3729 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
emilmont 77:869cf507173a 3730 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
emilmont 77:869cf507173a 3731 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
emilmont 77:869cf507173a 3732 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
emilmont 77:869cf507173a 3733 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
emilmont 77:869cf507173a 3734 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< Power interface clock enable */
emilmont 77:869cf507173a 3735 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000) /*!< DAC interface clock enable */
emilmont 77:869cf507173a 3736 #define RCC_APB1ENR_COMPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enable */
emilmont 77:869cf507173a 3737
emilmont 77:869cf507173a 3738 /****************** Bit definition for RCC_AHBLPENR register ****************/
emilmont 77:869cf507173a 3739 #define RCC_AHBLPENR_GPIOALPEN ((uint32_t)0x00000001) /*!< GPIO port A clock enabled in sleep mode */
emilmont 77:869cf507173a 3740 #define RCC_AHBLPENR_GPIOBLPEN ((uint32_t)0x00000002) /*!< GPIO port B clock enabled in sleep mode */
emilmont 77:869cf507173a 3741 #define RCC_AHBLPENR_GPIOCLPEN ((uint32_t)0x00000004) /*!< GPIO port C clock enabled in sleep mode */
emilmont 77:869cf507173a 3742 #define RCC_AHBLPENR_GPIODLPEN ((uint32_t)0x00000008) /*!< GPIO port D clock enabled in sleep mode */
emilmont 77:869cf507173a 3743 #define RCC_AHBLPENR_GPIOELPEN ((uint32_t)0x00000010) /*!< GPIO port E clock enabled in sleep mode */
emilmont 77:869cf507173a 3744 #define RCC_AHBLPENR_GPIOHLPEN ((uint32_t)0x00000020) /*!< GPIO port H clock enabled in sleep mode */
emilmont 77:869cf507173a 3745 #define RCC_AHBLPENR_GPIOFLPEN ((uint32_t)0x00000040) /*!< GPIO port F clock enabled in sleep mode */
emilmont 77:869cf507173a 3746 #define RCC_AHBLPENR_GPIOGLPEN ((uint32_t)0x00000080) /*!< GPIO port G clock enabled in sleep mode */
emilmont 77:869cf507173a 3747 #define RCC_AHBLPENR_CRCLPEN ((uint32_t)0x00001000) /*!< CRC clock enabled in sleep mode */
emilmont 77:869cf507173a 3748 #define RCC_AHBLPENR_FLITFLPEN ((uint32_t)0x00008000) /*!< Flash Interface clock enabled in sleep mode
emilmont 77:869cf507173a 3749 (has effect only when the Flash memory is
emilmont 77:869cf507173a 3750 in power down mode) */
emilmont 77:869cf507173a 3751 #define RCC_AHBLPENR_SRAMLPEN ((uint32_t)0x00010000) /*!< SRAM clock enabled in sleep mode */
emilmont 77:869cf507173a 3752 #define RCC_AHBLPENR_DMA1LPEN ((uint32_t)0x01000000) /*!< DMA1 clock enabled in sleep mode */
emilmont 77:869cf507173a 3753 #define RCC_AHBLPENR_DMA2LPEN ((uint32_t)0x02000000) /*!< DMA2 clock enabled in sleep mode */
emilmont 77:869cf507173a 3754 #define RCC_AHBLPENR_AESLPEN ((uint32_t)0x08000000) /*!< AES clock enabled in sleep mode */
emilmont 77:869cf507173a 3755 #define RCC_AHBLPENR_FSMCLPEN ((uint32_t)0x40000000) /*!< FSMC clock enabled in sleep mode */
emilmont 77:869cf507173a 3756
emilmont 77:869cf507173a 3757 /****************** Bit definition for RCC_APB2LPENR register ***************/
emilmont 77:869cf507173a 3758 #define RCC_APB2LPENR_SYSCFGLPEN ((uint32_t)0x00000001) /*!< System Configuration SYSCFG clock enabled in sleep mode */
emilmont 77:869cf507173a 3759 #define RCC_APB2LPENR_TIM9LPEN ((uint32_t)0x00000004) /*!< TIM9 interface clock enabled in sleep mode */
emilmont 77:869cf507173a 3760 #define RCC_APB2LPENR_TIM10LPEN ((uint32_t)0x00000008) /*!< TIM10 interface clock enabled in sleep mode */
emilmont 77:869cf507173a 3761 #define RCC_APB2LPENR_TIM11LPEN ((uint32_t)0x00000010) /*!< TIM11 Timer clock enabled in sleep mode */
emilmont 77:869cf507173a 3762 #define RCC_APB2LPENR_ADC1LPEN ((uint32_t)0x00000200) /*!< ADC1 clock enabled in sleep mode */
emilmont 77:869cf507173a 3763 #define RCC_APB2LPENR_SDIOLPEN ((uint32_t)0x00000800) /*!< SDIO clock enabled in sleep mode */
emilmont 77:869cf507173a 3764 #define RCC_APB2LPENR_SPI1LPEN ((uint32_t)0x00001000) /*!< SPI1 clock enabled in sleep mode */
emilmont 77:869cf507173a 3765 #define RCC_APB2LPENR_USART1LPEN ((uint32_t)0x00004000) /*!< USART1 clock enabled in sleep mode */
emilmont 77:869cf507173a 3766
emilmont 77:869cf507173a 3767 /***************** Bit definition for RCC_APB1LPENR register ****************/
emilmont 77:869cf507173a 3768 #define RCC_APB1LPENR_TIM2LPEN ((uint32_t)0x00000001) /*!< Timer 2 clock enabled in sleep mode */
emilmont 77:869cf507173a 3769 #define RCC_APB1LPENR_TIM3LPEN ((uint32_t)0x00000002) /*!< Timer 3 clock enabled in sleep mode */
emilmont 77:869cf507173a 3770 #define RCC_APB1LPENR_TIM4LPEN ((uint32_t)0x00000004) /*!< Timer 4 clock enabled in sleep mode */
emilmont 77:869cf507173a 3771 #define RCC_APB1LPENR_TIM5LPEN ((uint32_t)0x00000008) /*!< Timer 5 clock enabled in sleep mode */
emilmont 77:869cf507173a 3772 #define RCC_APB1LPENR_TIM6LPEN ((uint32_t)0x00000010) /*!< Timer 6 clock enabled in sleep mode */
emilmont 77:869cf507173a 3773 #define RCC_APB1LPENR_TIM7LPEN ((uint32_t)0x00000020) /*!< Timer 7 clock enabled in sleep mode */
emilmont 77:869cf507173a 3774 #define RCC_APB1LPENR_LCDLPEN ((uint32_t)0x00000200) /*!< LCD clock enabled in sleep mode */
emilmont 77:869cf507173a 3775 #define RCC_APB1LPENR_WWDGLPEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enabled in sleep mode */
emilmont 77:869cf507173a 3776 #define RCC_APB1LPENR_SPI2LPEN ((uint32_t)0x00004000) /*!< SPI 2 clock enabled in sleep mode */
emilmont 77:869cf507173a 3777 #define RCC_APB1LPENR_SPI3LPEN ((uint32_t)0x00008000) /*!< SPI 3 clock enabled in sleep mode */
emilmont 77:869cf507173a 3778 #define RCC_APB1LPENR_USART2LPEN ((uint32_t)0x00020000) /*!< USART 2 clock enabled in sleep mode */
emilmont 77:869cf507173a 3779 #define RCC_APB1LPENR_USART3LPEN ((uint32_t)0x00040000) /*!< USART 3 clock enabled in sleep mode */
emilmont 77:869cf507173a 3780 #define RCC_APB1LPENR_UART4LPEN ((uint32_t)0x00080000) /*!< UART 4 clock enabled in sleep mode */
emilmont 77:869cf507173a 3781 #define RCC_APB1LPENR_UART5LPEN ((uint32_t)0x00100000) /*!< UART 5 clock enabled in sleep mode */
emilmont 77:869cf507173a 3782 #define RCC_APB1LPENR_I2C1LPEN ((uint32_t)0x00200000) /*!< I2C 1 clock enabled in sleep mode */
emilmont 77:869cf507173a 3783 #define RCC_APB1LPENR_I2C2LPEN ((uint32_t)0x00400000) /*!< I2C 2 clock enabled in sleep mode */
emilmont 77:869cf507173a 3784 #define RCC_APB1LPENR_USBLPEN ((uint32_t)0x00800000) /*!< USB clock enabled in sleep mode */
emilmont 77:869cf507173a 3785 #define RCC_APB1LPENR_PWRLPEN ((uint32_t)0x10000000) /*!< Power interface clock enabled in sleep mode */
emilmont 77:869cf507173a 3786 #define RCC_APB1LPENR_DACLPEN ((uint32_t)0x20000000) /*!< DAC interface clock enabled in sleep mode */
emilmont 77:869cf507173a 3787 #define RCC_APB1LPENR_COMPLPEN ((uint32_t)0x80000000) /*!< Comparator interface clock enabled in sleep mode*/
emilmont 77:869cf507173a 3788
emilmont 77:869cf507173a 3789 /******************* Bit definition for RCC_CSR register ********************/
emilmont 77:869cf507173a 3790 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
emilmont 77:869cf507173a 3791 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
emilmont 77:869cf507173a 3792
emilmont 77:869cf507173a 3793 #define RCC_CSR_LSEON ((uint32_t)0x00000100) /*!< External Low Speed oscillator enable */
emilmont 77:869cf507173a 3794 #define RCC_CSR_LSERDY ((uint32_t)0x00000200) /*!< External Low Speed oscillator Ready */
emilmont 77:869cf507173a 3795 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400) /*!< External Low Speed oscillator Bypass */
emilmont 77:869cf507173a 3796 #define RCC_CSR_LSECSSON ((uint32_t)0x00000800) /*!< External Low Speed oscillator CSS Enable */
emilmont 77:869cf507173a 3797 #define RCC_CSR_LSECSSD ((uint32_t)0x00001000) /*!< External Low Speed oscillator CSS Detected */
emilmont 77:869cf507173a 3798
emilmont 77:869cf507173a 3799 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
emilmont 77:869cf507173a 3800 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 3801 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 3802
emilmont 77:869cf507173a 3803 /*!< RTC congiguration */
emilmont 77:869cf507173a 3804 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
emilmont 77:869cf507173a 3805 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000) /*!< LSE oscillator clock used as RTC clock */
emilmont 77:869cf507173a 3806 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000) /*!< LSI oscillator clock used as RTC clock */
emilmont 77:869cf507173a 3807 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000) /*!< HSE oscillator clock divided by 2, 4, 8 or 16 by RTCPRE used as RTC clock */
emilmont 77:869cf507173a 3808
emilmont 77:869cf507173a 3809 #define RCC_CSR_RTCEN ((uint32_t)0x00400000) /*!< RTC clock enable */
emilmont 77:869cf507173a 3810 #define RCC_CSR_RTCRST ((uint32_t)0x00800000) /*!< RTC reset */
emilmont 77:869cf507173a 3811
emilmont 77:869cf507173a 3812 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
emilmont 77:869cf507173a 3813 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< Option Bytes Loader reset flag */
emilmont 77:869cf507173a 3814 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
emilmont 77:869cf507173a 3815 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
emilmont 77:869cf507173a 3816 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
emilmont 77:869cf507173a 3817 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
emilmont 77:869cf507173a 3818 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
emilmont 77:869cf507173a 3819 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
emilmont 77:869cf507173a 3820
emilmont 77:869cf507173a 3821
emilmont 77:869cf507173a 3822 /******************************************************************************/
emilmont 77:869cf507173a 3823 /* */
emilmont 77:869cf507173a 3824 /* Real-Time Clock (RTC) */
emilmont 77:869cf507173a 3825 /* */
emilmont 77:869cf507173a 3826 /******************************************************************************/
emilmont 77:869cf507173a 3827 /******************** Bits definition for RTC_TR register *******************/
emilmont 77:869cf507173a 3828 #define RTC_TR_PM ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3829 #define RTC_TR_HT ((uint32_t)0x00300000)
emilmont 77:869cf507173a 3830 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 3831 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 3832 #define RTC_TR_HU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 3833 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3834 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 3835 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 3836 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 3837 #define RTC_TR_MNT ((uint32_t)0x00007000)
emilmont 77:869cf507173a 3838 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3839 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3840 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3841 #define RTC_TR_MNU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 3842 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3843 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3844 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3845 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3846 #define RTC_TR_ST ((uint32_t)0x00000070)
emilmont 77:869cf507173a 3847 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3848 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3849 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3850 #define RTC_TR_SU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 3851 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3852 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3853 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3854 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3855
emilmont 77:869cf507173a 3856 /******************** Bits definition for RTC_DR register *******************/
emilmont 77:869cf507173a 3857 #define RTC_DR_YT ((uint32_t)0x00F00000)
emilmont 77:869cf507173a 3858 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 3859 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 3860 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3861 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 3862 #define RTC_DR_YU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 3863 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3864 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 3865 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 3866 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 3867 #define RTC_DR_WDU ((uint32_t)0x0000E000)
emilmont 77:869cf507173a 3868 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3869 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3870 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3871 #define RTC_DR_MT ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3872 #define RTC_DR_MU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 3873 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3874 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3875 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3876 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3877 #define RTC_DR_DT ((uint32_t)0x00000030)
emilmont 77:869cf507173a 3878 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3879 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3880 #define RTC_DR_DU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 3881 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3882 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3883 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3884 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3885
emilmont 77:869cf507173a 3886 /******************** Bits definition for RTC_CR register *******************/
emilmont 77:869cf507173a 3887 #define RTC_CR_COE ((uint32_t)0x00800000)
emilmont 77:869cf507173a 3888 #define RTC_CR_OSEL ((uint32_t)0x00600000)
emilmont 77:869cf507173a 3889 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 3890 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3891 #define RTC_CR_POL ((uint32_t)0x00100000)
emilmont 77:869cf507173a 3892 #define RTC_CR_COSEL ((uint32_t)0x00080000)
emilmont 77:869cf507173a 3893 #define RTC_CR_BCK ((uint32_t)0x00040000)
emilmont 77:869cf507173a 3894 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
emilmont 77:869cf507173a 3895 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3896 #define RTC_CR_TSIE ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3897 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3898 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3899 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3900 #define RTC_CR_TSE ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3901 #define RTC_CR_WUTE ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3902 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3903 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3904 #define RTC_CR_DCE ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3905 #define RTC_CR_FMT ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3906 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3907 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3908 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3909 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
emilmont 77:869cf507173a 3910 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3911 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3912 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3913
emilmont 77:869cf507173a 3914 /******************** Bits definition for RTC_ISR register ******************/
emilmont 77:869cf507173a 3915 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3916 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3917 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3918 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3919 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3920 #define RTC_ISR_TSF ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3921 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3922 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3923 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3924 #define RTC_ISR_INIT ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3925 #define RTC_ISR_INITF ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3926 #define RTC_ISR_RSF ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3927 #define RTC_ISR_INITS ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3928 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3929 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3930 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3931 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3932
emilmont 77:869cf507173a 3933 /******************** Bits definition for RTC_PRER register *****************/
emilmont 77:869cf507173a 3934 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
emilmont 77:869cf507173a 3935 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
emilmont 77:869cf507173a 3936
emilmont 77:869cf507173a 3937 /******************** Bits definition for RTC_WUTR register *****************/
emilmont 77:869cf507173a 3938 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
emilmont 77:869cf507173a 3939
emilmont 77:869cf507173a 3940 /******************** Bits definition for RTC_CALIBR register ***************/
emilmont 77:869cf507173a 3941 #define RTC_CALIBR_DCS ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3942 #define RTC_CALIBR_DC ((uint32_t)0x0000001F)
emilmont 77:869cf507173a 3943
emilmont 77:869cf507173a 3944 /******************** Bits definition for RTC_ALRMAR register ***************/
emilmont 77:869cf507173a 3945 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 3946 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
emilmont 77:869cf507173a 3947 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
emilmont 77:869cf507173a 3948 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 3949 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 3950 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 3951 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 3952 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 3953 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 3954 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 3955 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 3956 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3957 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
emilmont 77:869cf507173a 3958 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 3959 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 3960 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 3961 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 3962 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 3963 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 3964 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 3965 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 3966 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
emilmont 77:869cf507173a 3967 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 3968 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 3969 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 3970 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 3971 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 3972 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 3973 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 3974 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 3975 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 3976 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
emilmont 77:869cf507173a 3977 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 3978 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 3979 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 3980 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 3981 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 3982 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 3983 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 3984 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 3985
emilmont 77:869cf507173a 3986 /******************** Bits definition for RTC_ALRMBR register ***************/
emilmont 77:869cf507173a 3987 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
emilmont 77:869cf507173a 3988 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
emilmont 77:869cf507173a 3989 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
emilmont 77:869cf507173a 3990 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
emilmont 77:869cf507173a 3991 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
emilmont 77:869cf507173a 3992 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 3993 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 3994 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 3995 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 3996 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 3997 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
emilmont 77:869cf507173a 3998 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
emilmont 77:869cf507173a 3999 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
emilmont 77:869cf507173a 4000 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 4001 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 4002 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 4003 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 4004 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 4005 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 4006 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 4007 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 4008 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
emilmont 77:869cf507173a 4009 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 4010 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 4011 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 4012 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 4013 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 4014 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 4015 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 4016 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 4017 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 4018 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
emilmont 77:869cf507173a 4019 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 4020 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 4021 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 4022 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 4023 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 4024 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 4025 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 4026 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 4027
emilmont 77:869cf507173a 4028 /******************** Bits definition for RTC_WPR register ******************/
emilmont 77:869cf507173a 4029 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
emilmont 77:869cf507173a 4030
emilmont 77:869cf507173a 4031 /******************** Bits definition for RTC_SSR register ******************/
emilmont 77:869cf507173a 4032 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
emilmont 77:869cf507173a 4033
emilmont 77:869cf507173a 4034 /******************** Bits definition for RTC_SHIFTR register ***************/
emilmont 77:869cf507173a 4035 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
emilmont 77:869cf507173a 4036 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
emilmont 77:869cf507173a 4037
emilmont 77:869cf507173a 4038 /******************** Bits definition for RTC_TSTR register *****************/
emilmont 77:869cf507173a 4039 #define RTC_TSTR_PM ((uint32_t)0x00400000)
emilmont 77:869cf507173a 4040 #define RTC_TSTR_HT ((uint32_t)0x00300000)
emilmont 77:869cf507173a 4041 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
emilmont 77:869cf507173a 4042 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
emilmont 77:869cf507173a 4043 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
emilmont 77:869cf507173a 4044 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
emilmont 77:869cf507173a 4045 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
emilmont 77:869cf507173a 4046 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
emilmont 77:869cf507173a 4047 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
emilmont 77:869cf507173a 4048 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
emilmont 77:869cf507173a 4049 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 4050 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 4051 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 4052 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 4053 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 4054 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 4055 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 4056 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 4057 #define RTC_TSTR_ST ((uint32_t)0x00000070)
emilmont 77:869cf507173a 4058 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 4059 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 4060 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 4061 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 4062 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 4063 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 4064 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 4065 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 4066
emilmont 77:869cf507173a 4067 /******************** Bits definition for RTC_TSDR register *****************/
emilmont 77:869cf507173a 4068 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
emilmont 77:869cf507173a 4069 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 4070 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 4071 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
emilmont 77:869cf507173a 4072 #define RTC_TSDR_MT ((uint32_t)0x00001000)
emilmont 77:869cf507173a 4073 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
emilmont 77:869cf507173a 4074 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 4075 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 4076 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 4077 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 4078 #define RTC_TSDR_DT ((uint32_t)0x00000030)
emilmont 77:869cf507173a 4079 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 4080 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 4081 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
emilmont 77:869cf507173a 4082 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 4083 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 4084 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 4085 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 4086
emilmont 77:869cf507173a 4087 /******************** Bits definition for RTC_TSSSR register ****************/
emilmont 77:869cf507173a 4088 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
emilmont 77:869cf507173a 4089
emilmont 77:869cf507173a 4090 /******************** Bits definition for RTC_CAL register *****************/
emilmont 77:869cf507173a 4091 #define RTC_CALR_CALP ((uint32_t)0x00008000)
emilmont 77:869cf507173a 4092 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 4093 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 4094 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
emilmont 77:869cf507173a 4095 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
emilmont 77:869cf507173a 4096 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
emilmont 77:869cf507173a 4097 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
emilmont 77:869cf507173a 4098 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
emilmont 77:869cf507173a 4099 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
emilmont 77:869cf507173a 4100 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
emilmont 77:869cf507173a 4101 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
emilmont 77:869cf507173a 4102 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
emilmont 77:869cf507173a 4103 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 4104
emilmont 77:869cf507173a 4105 /******************** Bits definition for RTC_TAFCR register ****************/
emilmont 77:869cf507173a 4106 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
emilmont 77:869cf507173a 4107 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
emilmont 77:869cf507173a 4108 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
emilmont 77:869cf507173a 4109 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
emilmont 77:869cf507173a 4110 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
emilmont 77:869cf507173a 4111 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
emilmont 77:869cf507173a 4112 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
emilmont 77:869cf507173a 4113 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
emilmont 77:869cf507173a 4114 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
emilmont 77:869cf507173a 4115 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
emilmont 77:869cf507173a 4116 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
emilmont 77:869cf507173a 4117 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
emilmont 77:869cf507173a 4118 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
emilmont 77:869cf507173a 4119 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
emilmont 77:869cf507173a 4120 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
emilmont 77:869cf507173a 4121 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
emilmont 77:869cf507173a 4122 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
emilmont 77:869cf507173a 4123 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
emilmont 77:869cf507173a 4124 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
emilmont 77:869cf507173a 4125 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
emilmont 77:869cf507173a 4126
emilmont 77:869cf507173a 4127 /******************** Bits definition for RTC_ALRMASSR register *************/
emilmont 77:869cf507173a 4128 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 4129 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 4130 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 4131 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 4132 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 4133 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
emilmont 77:869cf507173a 4134
emilmont 77:869cf507173a 4135 /******************** Bits definition for RTC_ALRMBSSR register *************/
emilmont 77:869cf507173a 4136 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
emilmont 77:869cf507173a 4137 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
emilmont 77:869cf507173a 4138 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
emilmont 77:869cf507173a 4139 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
emilmont 77:869cf507173a 4140 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
emilmont 77:869cf507173a 4141 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
emilmont 77:869cf507173a 4142
emilmont 77:869cf507173a 4143 /******************** Bits definition for RTC_BKP0R register ****************/
emilmont 77:869cf507173a 4144 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4145
emilmont 77:869cf507173a 4146 /******************** Bits definition for RTC_BKP1R register ****************/
emilmont 77:869cf507173a 4147 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4148
emilmont 77:869cf507173a 4149 /******************** Bits definition for RTC_BKP2R register ****************/
emilmont 77:869cf507173a 4150 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4151
emilmont 77:869cf507173a 4152 /******************** Bits definition for RTC_BKP3R register ****************/
emilmont 77:869cf507173a 4153 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4154
emilmont 77:869cf507173a 4155 /******************** Bits definition for RTC_BKP4R register ****************/
emilmont 77:869cf507173a 4156 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4157
emilmont 77:869cf507173a 4158 /******************** Bits definition for RTC_BKP5R register ****************/
emilmont 77:869cf507173a 4159 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4160
emilmont 77:869cf507173a 4161 /******************** Bits definition for RTC_BKP6R register ****************/
emilmont 77:869cf507173a 4162 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4163
emilmont 77:869cf507173a 4164 /******************** Bits definition for RTC_BKP7R register ****************/
emilmont 77:869cf507173a 4165 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4166
emilmont 77:869cf507173a 4167 /******************** Bits definition for RTC_BKP8R register ****************/
emilmont 77:869cf507173a 4168 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4169
emilmont 77:869cf507173a 4170 /******************** Bits definition for RTC_BKP9R register ****************/
emilmont 77:869cf507173a 4171 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4172
emilmont 77:869cf507173a 4173 /******************** Bits definition for RTC_BKP10R register ***************/
emilmont 77:869cf507173a 4174 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4175
emilmont 77:869cf507173a 4176 /******************** Bits definition for RTC_BKP11R register ***************/
emilmont 77:869cf507173a 4177 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4178
emilmont 77:869cf507173a 4179 /******************** Bits definition for RTC_BKP12R register ***************/
emilmont 77:869cf507173a 4180 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4181
emilmont 77:869cf507173a 4182 /******************** Bits definition for RTC_BKP13R register ***************/
emilmont 77:869cf507173a 4183 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4184
emilmont 77:869cf507173a 4185 /******************** Bits definition for RTC_BKP14R register ***************/
emilmont 77:869cf507173a 4186 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4187
emilmont 77:869cf507173a 4188 /******************** Bits definition for RTC_BKP15R register ***************/
emilmont 77:869cf507173a 4189 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4190
emilmont 77:869cf507173a 4191 /******************** Bits definition for RTC_BKP16R register ***************/
emilmont 77:869cf507173a 4192 #define RTC_BKP16R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4193
emilmont 77:869cf507173a 4194 /******************** Bits definition for RTC_BKP17R register ***************/
emilmont 77:869cf507173a 4195 #define RTC_BKP17R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4196
emilmont 77:869cf507173a 4197 /******************** Bits definition for RTC_BKP18R register ***************/
emilmont 77:869cf507173a 4198 #define RTC_BKP18R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4199
emilmont 77:869cf507173a 4200 /******************** Bits definition for RTC_BKP19R register ***************/
emilmont 77:869cf507173a 4201 #define RTC_BKP19R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4202
emilmont 77:869cf507173a 4203 /******************** Bits definition for RTC_BKP20R register ***************/
emilmont 77:869cf507173a 4204 #define RTC_BKP20R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4205
emilmont 77:869cf507173a 4206 /******************** Bits definition for RTC_BKP21R register ***************/
emilmont 77:869cf507173a 4207 #define RTC_BKP21R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4208
emilmont 77:869cf507173a 4209 /******************** Bits definition for RTC_BKP22R register ***************/
emilmont 77:869cf507173a 4210 #define RTC_BKP22R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4211
emilmont 77:869cf507173a 4212 /******************** Bits definition for RTC_BKP23R register ***************/
emilmont 77:869cf507173a 4213 #define RTC_BKP23R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4214
emilmont 77:869cf507173a 4215 /******************** Bits definition for RTC_BKP24R register ***************/
emilmont 77:869cf507173a 4216 #define RTC_BKP24R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4217
emilmont 77:869cf507173a 4218 /******************** Bits definition for RTC_BKP25R register ***************/
emilmont 77:869cf507173a 4219 #define RTC_BKP25R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4220
emilmont 77:869cf507173a 4221 /******************** Bits definition for RTC_BKP26R register ***************/
emilmont 77:869cf507173a 4222 #define RTC_BKP26R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4223
emilmont 77:869cf507173a 4224 /******************** Bits definition for RTC_BKP27R register ***************/
emilmont 77:869cf507173a 4225 #define RTC_BKP27R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4226
emilmont 77:869cf507173a 4227 /******************** Bits definition for RTC_BKP28R register ***************/
emilmont 77:869cf507173a 4228 #define RTC_BKP28R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4229
emilmont 77:869cf507173a 4230 /******************** Bits definition for RTC_BKP29R register ***************/
emilmont 77:869cf507173a 4231 #define RTC_BKP29R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4232
emilmont 77:869cf507173a 4233 /******************** Bits definition for RTC_BKP30R register ***************/
emilmont 77:869cf507173a 4234 #define RTC_BKP30R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4235
emilmont 77:869cf507173a 4236 /******************** Bits definition for RTC_BKP31R register ***************/
emilmont 77:869cf507173a 4237 #define RTC_BKP31R ((uint32_t)0xFFFFFFFF)
emilmont 77:869cf507173a 4238
emilmont 77:869cf507173a 4239 /******************************************************************************/
emilmont 77:869cf507173a 4240 /* */
emilmont 77:869cf507173a 4241 /* SD host Interface */
emilmont 77:869cf507173a 4242 /* */
emilmont 77:869cf507173a 4243 /******************************************************************************/
emilmont 77:869cf507173a 4244
emilmont 77:869cf507173a 4245 /****************** Bit definition for SDIO_POWER register ******************/
emilmont 77:869cf507173a 4246 #define SDIO_POWER_PWRCTRL ((uint8_t)0x03) /*!< PWRCTRL[1:0] bits (Power supply control bits) */
emilmont 77:869cf507173a 4247 #define SDIO_POWER_PWRCTRL_0 ((uint8_t)0x01) /*!< Bit 0 */
emilmont 77:869cf507173a 4248 #define SDIO_POWER_PWRCTRL_1 ((uint8_t)0x02) /*!< Bit 1 */
emilmont 77:869cf507173a 4249
emilmont 77:869cf507173a 4250 /****************** Bit definition for SDIO_CLKCR register ******************/
emilmont 77:869cf507173a 4251 #define SDIO_CLKCR_CLKDIV ((uint16_t)0x00FF) /*!< Clock divide factor */
emilmont 77:869cf507173a 4252 #define SDIO_CLKCR_CLKEN ((uint16_t)0x0100) /*!< Clock enable bit */
emilmont 77:869cf507173a 4253 #define SDIO_CLKCR_PWRSAV ((uint16_t)0x0200) /*!< Power saving configuration bit */
emilmont 77:869cf507173a 4254 #define SDIO_CLKCR_BYPASS ((uint16_t)0x0400) /*!< Clock divider bypass enable bit */
emilmont 77:869cf507173a 4255
emilmont 77:869cf507173a 4256 #define SDIO_CLKCR_WIDBUS ((uint16_t)0x1800) /*!< WIDBUS[1:0] bits (Wide bus mode enable bit) */
emilmont 77:869cf507173a 4257 #define SDIO_CLKCR_WIDBUS_0 ((uint16_t)0x0800) /*!< Bit 0 */
emilmont 77:869cf507173a 4258 #define SDIO_CLKCR_WIDBUS_1 ((uint16_t)0x1000) /*!< Bit 1 */
emilmont 77:869cf507173a 4259
emilmont 77:869cf507173a 4260 #define SDIO_CLKCR_NEGEDGE ((uint16_t)0x2000) /*!< SDIO_CK dephasing selection bit */
emilmont 77:869cf507173a 4261 #define SDIO_CLKCR_HWFC_EN ((uint16_t)0x4000) /*!< HW Flow Control enable */
emilmont 77:869cf507173a 4262
emilmont 77:869cf507173a 4263 /******************* Bit definition for SDIO_ARG register *******************/
emilmont 77:869cf507173a 4264 #define SDIO_ARG_CMDARG ((uint32_t)0xFFFFFFFF) /*!< Command argument */
emilmont 77:869cf507173a 4265
emilmont 77:869cf507173a 4266 /******************* Bit definition for SDIO_CMD register *******************/
emilmont 77:869cf507173a 4267 #define SDIO_CMD_CMDINDEX ((uint16_t)0x003F) /*!< Command Index */
emilmont 77:869cf507173a 4268
emilmont 77:869cf507173a 4269 #define SDIO_CMD_WAITRESP ((uint16_t)0x00C0) /*!< WAITRESP[1:0] bits (Wait for response bits) */
emilmont 77:869cf507173a 4270 #define SDIO_CMD_WAITRESP_0 ((uint16_t)0x0040) /*!< Bit 0 */
emilmont 77:869cf507173a 4271 #define SDIO_CMD_WAITRESP_1 ((uint16_t)0x0080) /*!< Bit 1 */
emilmont 77:869cf507173a 4272
emilmont 77:869cf507173a 4273 #define SDIO_CMD_WAITINT ((uint16_t)0x0100) /*!< CPSM Waits for Interrupt Request */
emilmont 77:869cf507173a 4274 #define SDIO_CMD_WAITPEND ((uint16_t)0x0200) /*!< CPSM Waits for ends of data transfer (CmdPend internal signal) */
emilmont 77:869cf507173a 4275 #define SDIO_CMD_CPSMEN ((uint16_t)0x0400) /*!< Command path state machine (CPSM) Enable bit */
emilmont 77:869cf507173a 4276 #define SDIO_CMD_SDIOSUSPEND ((uint16_t)0x0800) /*!< SD I/O suspend command */
emilmont 77:869cf507173a 4277 #define SDIO_CMD_ENCMDCOMPL ((uint16_t)0x1000) /*!< Enable CMD completion */
emilmont 77:869cf507173a 4278 #define SDIO_CMD_NIEN ((uint16_t)0x2000) /*!< Not Interrupt Enable */
emilmont 77:869cf507173a 4279 #define SDIO_CMD_CEATACMD ((uint16_t)0x4000) /*!< CE-ATA command */
emilmont 77:869cf507173a 4280
emilmont 77:869cf507173a 4281 /***************** Bit definition for SDIO_RESPCMD register *****************/
emilmont 77:869cf507173a 4282 #define SDIO_RESPCMD_RESPCMD ((uint8_t)0x3F) /*!< Response command index */
emilmont 77:869cf507173a 4283
emilmont 77:869cf507173a 4284 /****************** Bit definition for SDIO_RESP0 register ******************/
emilmont 77:869cf507173a 4285 #define SDIO_RESP0_CARDSTATUS0 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
emilmont 77:869cf507173a 4286
emilmont 77:869cf507173a 4287 /****************** Bit definition for SDIO_RESP1 register ******************/
emilmont 77:869cf507173a 4288 #define SDIO_RESP1_CARDSTATUS1 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
emilmont 77:869cf507173a 4289
emilmont 77:869cf507173a 4290 /****************** Bit definition for SDIO_RESP2 register ******************/
emilmont 77:869cf507173a 4291 #define SDIO_RESP2_CARDSTATUS2 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
emilmont 77:869cf507173a 4292
emilmont 77:869cf507173a 4293 /****************** Bit definition for SDIO_RESP3 register ******************/
emilmont 77:869cf507173a 4294 #define SDIO_RESP3_CARDSTATUS3 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
emilmont 77:869cf507173a 4295
emilmont 77:869cf507173a 4296 /****************** Bit definition for SDIO_RESP4 register ******************/
emilmont 77:869cf507173a 4297 #define SDIO_RESP4_CARDSTATUS4 ((uint32_t)0xFFFFFFFF) /*!< Card Status */
emilmont 77:869cf507173a 4298
emilmont 77:869cf507173a 4299 /****************** Bit definition for SDIO_DTIMER register *****************/
emilmont 77:869cf507173a 4300 #define SDIO_DTIMER_DATATIME ((uint32_t)0xFFFFFFFF) /*!< Data timeout period. */
emilmont 77:869cf507173a 4301
emilmont 77:869cf507173a 4302 /****************** Bit definition for SDIO_DLEN register *******************/
emilmont 77:869cf507173a 4303 #define SDIO_DLEN_DATALENGTH ((uint32_t)0x01FFFFFF) /*!< Data length value */
emilmont 77:869cf507173a 4304
emilmont 77:869cf507173a 4305 /****************** Bit definition for SDIO_DCTRL register ******************/
emilmont 77:869cf507173a 4306 #define SDIO_DCTRL_DTEN ((uint16_t)0x0001) /*!< Data transfer enabled bit */
emilmont 77:869cf507173a 4307 #define SDIO_DCTRL_DTDIR ((uint16_t)0x0002) /*!< Data transfer direction selection */
emilmont 77:869cf507173a 4308 #define SDIO_DCTRL_DTMODE ((uint16_t)0x0004) /*!< Data transfer mode selection */
emilmont 77:869cf507173a 4309 #define SDIO_DCTRL_DMAEN ((uint16_t)0x0008) /*!< DMA enabled bit */
emilmont 77:869cf507173a 4310
emilmont 77:869cf507173a 4311 #define SDIO_DCTRL_DBLOCKSIZE ((uint16_t)0x00F0) /*!< DBLOCKSIZE[3:0] bits (Data block size) */
emilmont 77:869cf507173a 4312 #define SDIO_DCTRL_DBLOCKSIZE_0 ((uint16_t)0x0010) /*!< Bit 0 */
emilmont 77:869cf507173a 4313 #define SDIO_DCTRL_DBLOCKSIZE_1 ((uint16_t)0x0020) /*!< Bit 1 */
emilmont 77:869cf507173a 4314 #define SDIO_DCTRL_DBLOCKSIZE_2 ((uint16_t)0x0040) /*!< Bit 2 */
emilmont 77:869cf507173a 4315 #define SDIO_DCTRL_DBLOCKSIZE_3 ((uint16_t)0x0080) /*!< Bit 3 */
emilmont 77:869cf507173a 4316
emilmont 77:869cf507173a 4317 #define SDIO_DCTRL_RWSTART ((uint16_t)0x0100) /*!< Read wait start */
emilmont 77:869cf507173a 4318 #define SDIO_DCTRL_RWSTOP ((uint16_t)0x0200) /*!< Read wait stop */
emilmont 77:869cf507173a 4319 #define SDIO_DCTRL_RWMOD ((uint16_t)0x0400) /*!< Read wait mode */
emilmont 77:869cf507173a 4320 #define SDIO_DCTRL_SDIOEN ((uint16_t)0x0800) /*!< SD I/O enable functions */
emilmont 77:869cf507173a 4321
emilmont 77:869cf507173a 4322 /****************** Bit definition for SDIO_DCOUNT register *****************/
emilmont 77:869cf507173a 4323 #define SDIO_DCOUNT_DATACOUNT ((uint32_t)0x01FFFFFF) /*!< Data count value */
emilmont 77:869cf507173a 4324
emilmont 77:869cf507173a 4325 /****************** Bit definition for SDIO_STA register ********************/
emilmont 77:869cf507173a 4326 #define SDIO_STA_CCRCFAIL ((uint32_t)0x00000001) /*!< Command response received (CRC check failed) */
emilmont 77:869cf507173a 4327 #define SDIO_STA_DCRCFAIL ((uint32_t)0x00000002) /*!< Data block sent/received (CRC check failed) */
emilmont 77:869cf507173a 4328 #define SDIO_STA_CTIMEOUT ((uint32_t)0x00000004) /*!< Command response timeout */
emilmont 77:869cf507173a 4329 #define SDIO_STA_DTIMEOUT ((uint32_t)0x00000008) /*!< Data timeout */
emilmont 77:869cf507173a 4330 #define SDIO_STA_TXUNDERR ((uint32_t)0x00000010) /*!< Transmit FIFO underrun error */
emilmont 77:869cf507173a 4331 #define SDIO_STA_RXOVERR ((uint32_t)0x00000020) /*!< Received FIFO overrun error */
emilmont 77:869cf507173a 4332 #define SDIO_STA_CMDREND ((uint32_t)0x00000040) /*!< Command response received (CRC check passed) */
emilmont 77:869cf507173a 4333 #define SDIO_STA_CMDSENT ((uint32_t)0x00000080) /*!< Command sent (no response required) */
emilmont 77:869cf507173a 4334 #define SDIO_STA_DATAEND ((uint32_t)0x00000100) /*!< Data end (data counter, SDIDCOUNT, is zero) */
emilmont 77:869cf507173a 4335 #define SDIO_STA_STBITERR ((uint32_t)0x00000200) /*!< Start bit not detected on all data signals in wide bus mode */
emilmont 77:869cf507173a 4336 #define SDIO_STA_DBCKEND ((uint32_t)0x00000400) /*!< Data block sent/received (CRC check passed) */
emilmont 77:869cf507173a 4337 #define SDIO_STA_CMDACT ((uint32_t)0x00000800) /*!< Command transfer in progress */
emilmont 77:869cf507173a 4338 #define SDIO_STA_TXACT ((uint32_t)0x00001000) /*!< Data transmit in progress */
emilmont 77:869cf507173a 4339 #define SDIO_STA_RXACT ((uint32_t)0x00002000) /*!< Data receive in progress */
emilmont 77:869cf507173a 4340 #define SDIO_STA_TXFIFOHE ((uint32_t)0x00004000) /*!< Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
emilmont 77:869cf507173a 4341 #define SDIO_STA_RXFIFOHF ((uint32_t)0x00008000) /*!< Receive FIFO Half Full: there are at least 8 words in the FIFO */
emilmont 77:869cf507173a 4342 #define SDIO_STA_TXFIFOF ((uint32_t)0x00010000) /*!< Transmit FIFO full */
emilmont 77:869cf507173a 4343 #define SDIO_STA_RXFIFOF ((uint32_t)0x00020000) /*!< Receive FIFO full */
emilmont 77:869cf507173a 4344 #define SDIO_STA_TXFIFOE ((uint32_t)0x00040000) /*!< Transmit FIFO empty */
emilmont 77:869cf507173a 4345 #define SDIO_STA_RXFIFOE ((uint32_t)0x00080000) /*!< Receive FIFO empty */
emilmont 77:869cf507173a 4346 #define SDIO_STA_TXDAVL ((uint32_t)0x00100000) /*!< Data available in transmit FIFO */
emilmont 77:869cf507173a 4347 #define SDIO_STA_RXDAVL ((uint32_t)0x00200000) /*!< Data available in receive FIFO */
emilmont 77:869cf507173a 4348 #define SDIO_STA_SDIOIT ((uint32_t)0x00400000) /*!< SDIO interrupt received */
emilmont 77:869cf507173a 4349 #define SDIO_STA_CEATAEND ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received for CMD61 */
emilmont 77:869cf507173a 4350
emilmont 77:869cf507173a 4351 /******************* Bit definition for SDIO_ICR register *******************/
emilmont 77:869cf507173a 4352 #define SDIO_ICR_CCRCFAILC ((uint32_t)0x00000001) /*!< CCRCFAIL flag clear bit */
emilmont 77:869cf507173a 4353 #define SDIO_ICR_DCRCFAILC ((uint32_t)0x00000002) /*!< DCRCFAIL flag clear bit */
emilmont 77:869cf507173a 4354 #define SDIO_ICR_CTIMEOUTC ((uint32_t)0x00000004) /*!< CTIMEOUT flag clear bit */
emilmont 77:869cf507173a 4355 #define SDIO_ICR_DTIMEOUTC ((uint32_t)0x00000008) /*!< DTIMEOUT flag clear bit */
emilmont 77:869cf507173a 4356 #define SDIO_ICR_TXUNDERRC ((uint32_t)0x00000010) /*!< TXUNDERR flag clear bit */
emilmont 77:869cf507173a 4357 #define SDIO_ICR_RXOVERRC ((uint32_t)0x00000020) /*!< RXOVERR flag clear bit */
emilmont 77:869cf507173a 4358 #define SDIO_ICR_CMDRENDC ((uint32_t)0x00000040) /*!< CMDREND flag clear bit */
emilmont 77:869cf507173a 4359 #define SDIO_ICR_CMDSENTC ((uint32_t)0x00000080) /*!< CMDSENT flag clear bit */
emilmont 77:869cf507173a 4360 #define SDIO_ICR_DATAENDC ((uint32_t)0x00000100) /*!< DATAEND flag clear bit */
emilmont 77:869cf507173a 4361 #define SDIO_ICR_STBITERRC ((uint32_t)0x00000200) /*!< STBITERR flag clear bit */
emilmont 77:869cf507173a 4362 #define SDIO_ICR_DBCKENDC ((uint32_t)0x00000400) /*!< DBCKEND flag clear bit */
emilmont 77:869cf507173a 4363 #define SDIO_ICR_SDIOITC ((uint32_t)0x00400000) /*!< SDIOIT flag clear bit */
emilmont 77:869cf507173a 4364 #define SDIO_ICR_CEATAENDC ((uint32_t)0x00800000) /*!< CEATAEND flag clear bit */
emilmont 77:869cf507173a 4365
emilmont 77:869cf507173a 4366 /****************** Bit definition for SDIO_MASK register *******************/
emilmont 77:869cf507173a 4367 #define SDIO_MASK_CCRCFAILIE ((uint32_t)0x00000001) /*!< Command CRC Fail Interrupt Enable */
emilmont 77:869cf507173a 4368 #define SDIO_MASK_DCRCFAILIE ((uint32_t)0x00000002) /*!< Data CRC Fail Interrupt Enable */
emilmont 77:869cf507173a 4369 #define SDIO_MASK_CTIMEOUTIE ((uint32_t)0x00000004) /*!< Command TimeOut Interrupt Enable */
emilmont 77:869cf507173a 4370 #define SDIO_MASK_DTIMEOUTIE ((uint32_t)0x00000008) /*!< Data TimeOut Interrupt Enable */
emilmont 77:869cf507173a 4371 #define SDIO_MASK_TXUNDERRIE ((uint32_t)0x00000010) /*!< Tx FIFO UnderRun Error Interrupt Enable */
emilmont 77:869cf507173a 4372 #define SDIO_MASK_RXOVERRIE ((uint32_t)0x00000020) /*!< Rx FIFO OverRun Error Interrupt Enable */
emilmont 77:869cf507173a 4373 #define SDIO_MASK_CMDRENDIE ((uint32_t)0x00000040) /*!< Command Response Received Interrupt Enable */
emilmont 77:869cf507173a 4374 #define SDIO_MASK_CMDSENTIE ((uint32_t)0x00000080) /*!< Command Sent Interrupt Enable */
emilmont 77:869cf507173a 4375 #define SDIO_MASK_DATAENDIE ((uint32_t)0x00000100) /*!< Data End Interrupt Enable */
emilmont 77:869cf507173a 4376 #define SDIO_MASK_STBITERRIE ((uint32_t)0x00000200) /*!< Start Bit Error Interrupt Enable */
emilmont 77:869cf507173a 4377 #define SDIO_MASK_DBCKENDIE ((uint32_t)0x00000400) /*!< Data Block End Interrupt Enable */
emilmont 77:869cf507173a 4378 #define SDIO_MASK_CMDACTIE ((uint32_t)0x00000800) /*!< Command Acting Interrupt Enable */
emilmont 77:869cf507173a 4379 #define SDIO_MASK_TXACTIE ((uint32_t)0x00001000) /*!< Data Transmit Acting Interrupt Enable */
emilmont 77:869cf507173a 4380 #define SDIO_MASK_RXACTIE ((uint32_t)0x00002000) /*!< Data receive acting interrupt enabled */
emilmont 77:869cf507173a 4381 #define SDIO_MASK_TXFIFOHEIE ((uint32_t)0x00004000) /*!< Tx FIFO Half Empty interrupt Enable */
emilmont 77:869cf507173a 4382 #define SDIO_MASK_RXFIFOHFIE ((uint32_t)0x00008000) /*!< Rx FIFO Half Full interrupt Enable */
emilmont 77:869cf507173a 4383 #define SDIO_MASK_TXFIFOFIE ((uint32_t)0x00010000) /*!< Tx FIFO Full interrupt Enable */
emilmont 77:869cf507173a 4384 #define SDIO_MASK_RXFIFOFIE ((uint32_t)0x00020000) /*!< Rx FIFO Full interrupt Enable */
emilmont 77:869cf507173a 4385 #define SDIO_MASK_TXFIFOEIE ((uint32_t)0x00040000) /*!< Tx FIFO Empty interrupt Enable */
emilmont 77:869cf507173a 4386 #define SDIO_MASK_RXFIFOEIE ((uint32_t)0x00080000) /*!< Rx FIFO Empty interrupt Enable */
emilmont 77:869cf507173a 4387 #define SDIO_MASK_TXDAVLIE ((uint32_t)0x00100000) /*!< Data available in Tx FIFO interrupt Enable */
emilmont 77:869cf507173a 4388 #define SDIO_MASK_RXDAVLIE ((uint32_t)0x00200000) /*!< Data available in Rx FIFO interrupt Enable */
emilmont 77:869cf507173a 4389 #define SDIO_MASK_SDIOITIE ((uint32_t)0x00400000) /*!< SDIO Mode Interrupt Received interrupt Enable */
emilmont 77:869cf507173a 4390 #define SDIO_MASK_CEATAENDIE ((uint32_t)0x00800000) /*!< CE-ATA command completion signal received Interrupt Enable */
emilmont 77:869cf507173a 4391
emilmont 77:869cf507173a 4392 /***************** Bit definition for SDIO_FIFOCNT register *****************/
emilmont 77:869cf507173a 4393 #define SDIO_FIFOCNT_FIFOCOUNT ((uint32_t)0x00FFFFFF) /*!< Remaining number of words to be written to or read from the FIFO */
emilmont 77:869cf507173a 4394
emilmont 77:869cf507173a 4395 /****************** Bit definition for SDIO_FIFO register *******************/
emilmont 77:869cf507173a 4396 #define SDIO_FIFO_FIFODATA ((uint32_t)0xFFFFFFFF) /*!< Receive and transmit FIFO data */
emilmont 77:869cf507173a 4397
emilmont 77:869cf507173a 4398 /******************************************************************************/
emilmont 77:869cf507173a 4399 /* */
emilmont 77:869cf507173a 4400 /* Serial Peripheral Interface (SPI) */
emilmont 77:869cf507173a 4401 /* */
emilmont 77:869cf507173a 4402 /******************************************************************************/
emilmont 77:869cf507173a 4403
emilmont 77:869cf507173a 4404 /******************* Bit definition for SPI_CR1 register ********************/
emilmont 77:869cf507173a 4405 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
emilmont 77:869cf507173a 4406 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
emilmont 77:869cf507173a 4407 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
emilmont 77:869cf507173a 4408
emilmont 77:869cf507173a 4409 #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
emilmont 77:869cf507173a 4410 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
emilmont 77:869cf507173a 4411 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
emilmont 77:869cf507173a 4412 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
emilmont 77:869cf507173a 4413
emilmont 77:869cf507173a 4414 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
emilmont 77:869cf507173a 4415 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
emilmont 77:869cf507173a 4416 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
emilmont 77:869cf507173a 4417 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
emilmont 77:869cf507173a 4418 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
emilmont 77:869cf507173a 4419 #define SPI_CR1_DFF ((uint16_t)0x0800) /*!< Data Frame Format */
emilmont 77:869cf507173a 4420 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
emilmont 77:869cf507173a 4421 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
emilmont 77:869cf507173a 4422 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
emilmont 77:869cf507173a 4423 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
emilmont 77:869cf507173a 4424
emilmont 77:869cf507173a 4425 /******************* Bit definition for SPI_CR2 register ********************/
emilmont 77:869cf507173a 4426 #define SPI_CR2_RXDMAEN ((uint8_t)0x01) /*!< Rx Buffer DMA Enable */
emilmont 77:869cf507173a 4427 #define SPI_CR2_TXDMAEN ((uint8_t)0x02) /*!< Tx Buffer DMA Enable */
emilmont 77:869cf507173a 4428 #define SPI_CR2_SSOE ((uint8_t)0x04) /*!< SS Output Enable */
emilmont 77:869cf507173a 4429 #define SPI_CR2_FRF ((uint8_t)0x08) /*!< Frame format */
emilmont 77:869cf507173a 4430 #define SPI_CR2_ERRIE ((uint8_t)0x20) /*!< Error Interrupt Enable */
emilmont 77:869cf507173a 4431 #define SPI_CR2_RXNEIE ((uint8_t)0x40) /*!< RX buffer Not Empty Interrupt Enable */
emilmont 77:869cf507173a 4432 #define SPI_CR2_TXEIE ((uint8_t)0x80) /*!< Tx buffer Empty Interrupt Enable */
emilmont 77:869cf507173a 4433
emilmont 77:869cf507173a 4434 /******************** Bit definition for SPI_SR register ********************/
emilmont 77:869cf507173a 4435 #define SPI_SR_RXNE ((uint8_t)0x01) /*!< Receive buffer Not Empty */
emilmont 77:869cf507173a 4436 #define SPI_SR_TXE ((uint8_t)0x02) /*!< Transmit buffer Empty */
emilmont 77:869cf507173a 4437 #define SPI_SR_CHSIDE ((uint8_t)0x04) /*!< Channel side */
emilmont 77:869cf507173a 4438 #define SPI_SR_UDR ((uint8_t)0x08) /*!< Underrun flag */
emilmont 77:869cf507173a 4439 #define SPI_SR_CRCERR ((uint8_t)0x10) /*!< CRC Error flag */
emilmont 77:869cf507173a 4440 #define SPI_SR_MODF ((uint8_t)0x20) /*!< Mode fault */
emilmont 77:869cf507173a 4441 #define SPI_SR_OVR ((uint8_t)0x40) /*!< Overrun flag */
emilmont 77:869cf507173a 4442 #define SPI_SR_BSY ((uint8_t)0x80) /*!< Busy flag */
emilmont 77:869cf507173a 4443
emilmont 77:869cf507173a 4444 /******************** Bit definition for SPI_DR register ********************/
emilmont 77:869cf507173a 4445 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
emilmont 77:869cf507173a 4446
emilmont 77:869cf507173a 4447 /******************* Bit definition for SPI_CRCPR register ******************/
emilmont 77:869cf507173a 4448 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
emilmont 77:869cf507173a 4449
emilmont 77:869cf507173a 4450 /****************** Bit definition for SPI_RXCRCR register ******************/
emilmont 77:869cf507173a 4451 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
emilmont 77:869cf507173a 4452
emilmont 77:869cf507173a 4453 /****************** Bit definition for SPI_TXCRCR register ******************/
emilmont 77:869cf507173a 4454 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
emilmont 77:869cf507173a 4455
emilmont 77:869cf507173a 4456 /****************** Bit definition for SPI_I2SCFGR register *****************/
emilmont 77:869cf507173a 4457 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
emilmont 77:869cf507173a 4458
emilmont 77:869cf507173a 4459 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
emilmont 77:869cf507173a 4460 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
emilmont 77:869cf507173a 4461 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
emilmont 77:869cf507173a 4462
emilmont 77:869cf507173a 4463 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
emilmont 77:869cf507173a 4464
emilmont 77:869cf507173a 4465 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
emilmont 77:869cf507173a 4466 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 4467 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 4468
emilmont 77:869cf507173a 4469 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
emilmont 77:869cf507173a 4470
emilmont 77:869cf507173a 4471 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
emilmont 77:869cf507173a 4472 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 4473 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 4474
emilmont 77:869cf507173a 4475 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
emilmont 77:869cf507173a 4476 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
emilmont 77:869cf507173a 4477
emilmont 77:869cf507173a 4478 /****************** Bit definition for SPI_I2SPR register *******************/
emilmont 77:869cf507173a 4479 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
emilmont 77:869cf507173a 4480 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
emilmont 77:869cf507173a 4481 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
emilmont 77:869cf507173a 4482
emilmont 77:869cf507173a 4483 /******************************************************************************/
emilmont 77:869cf507173a 4484 /* */
emilmont 77:869cf507173a 4485 /* System Configuration (SYSCFG) */
emilmont 77:869cf507173a 4486 /* */
emilmont 77:869cf507173a 4487 /******************************************************************************/
emilmont 77:869cf507173a 4488 /***************** Bit definition for SYSCFG_MEMRMP register ****************/
emilmont 77:869cf507173a 4489 #define SYSCFG_MEMRMP_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
emilmont 77:869cf507173a 4490 #define SYSCFG_MEMRMP_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4491 #define SYSCFG_MEMRMP_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4492 #define SYSCFG_MEMRMP_BOOT_MODE ((uint32_t)0x00000300) /*!< Boot mode Config */
emilmont 77:869cf507173a 4493 #define SYSCFG_MEMRMP_BOOT_MODE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 4494 #define SYSCFG_MEMRMP_BOOT_MODE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 4495
emilmont 77:869cf507173a 4496 /***************** Bit definition for SYSCFG_PMC register *******************/
emilmont 77:869cf507173a 4497 #define SYSCFG_PMC_USB_PU ((uint32_t)0x00000001) /*!< SYSCFG PMC */
emilmont 77:869cf507173a 4498
emilmont 77:869cf507173a 4499 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
emilmont 77:869cf507173a 4500 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
emilmont 77:869cf507173a 4501 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
emilmont 77:869cf507173a 4502 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
emilmont 77:869cf507173a 4503 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
emilmont 77:869cf507173a 4504
emilmont 77:869cf507173a 4505 /**
emilmont 77:869cf507173a 4506 * @brief EXTI0 configuration
emilmont 77:869cf507173a 4507 */
emilmont 77:869cf507173a 4508 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
emilmont 77:869cf507173a 4509 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
emilmont 77:869cf507173a 4510 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
emilmont 77:869cf507173a 4511 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
emilmont 77:869cf507173a 4512 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
emilmont 77:869cf507173a 4513 #define SYSCFG_EXTICR1_EXTI0_PH ((uint16_t)0x0005) /*!< PH[0] pin */
emilmont 77:869cf507173a 4514 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0006) /*!< PF[0] pin */
emilmont 77:869cf507173a 4515 #define SYSCFG_EXTICR1_EXTI0_PG ((uint16_t)0x0007) /*!< PG[0] pin */
emilmont 77:869cf507173a 4516
emilmont 77:869cf507173a 4517 /**
emilmont 77:869cf507173a 4518 * @brief EXTI1 configuration
emilmont 77:869cf507173a 4519 */
emilmont 77:869cf507173a 4520 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
emilmont 77:869cf507173a 4521 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
emilmont 77:869cf507173a 4522 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
emilmont 77:869cf507173a 4523 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
emilmont 77:869cf507173a 4524 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
emilmont 77:869cf507173a 4525 #define SYSCFG_EXTICR1_EXTI1_PH ((uint16_t)0x0050) /*!< PH[1] pin */
emilmont 77:869cf507173a 4526 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0060) /*!< PF[1] pin */
emilmont 77:869cf507173a 4527 #define SYSCFG_EXTICR1_EXTI1_PG ((uint16_t)0x0070) /*!< PG[1] pin */
emilmont 77:869cf507173a 4528
emilmont 77:869cf507173a 4529 /**
emilmont 77:869cf507173a 4530 * @brief EXTI2 configuration
emilmont 77:869cf507173a 4531 */
emilmont 77:869cf507173a 4532 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
emilmont 77:869cf507173a 4533 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
emilmont 77:869cf507173a 4534 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
emilmont 77:869cf507173a 4535 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
emilmont 77:869cf507173a 4536 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
emilmont 77:869cf507173a 4537 #define SYSCFG_EXTICR1_EXTI2_PH ((uint16_t)0x0500) /*!< PH[2] pin */
emilmont 77:869cf507173a 4538 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0600) /*!< PF[2] pin */
emilmont 77:869cf507173a 4539 #define SYSCFG_EXTICR1_EXTI2_PG ((uint16_t)0x0700) /*!< PG[2] pin */
emilmont 77:869cf507173a 4540
emilmont 77:869cf507173a 4541 /**
emilmont 77:869cf507173a 4542 * @brief EXTI3 configuration
emilmont 77:869cf507173a 4543 */
emilmont 77:869cf507173a 4544 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
emilmont 77:869cf507173a 4545 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
emilmont 77:869cf507173a 4546 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
emilmont 77:869cf507173a 4547 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
emilmont 77:869cf507173a 4548 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
emilmont 77:869cf507173a 4549 #define SYSCFG_EXTICR1_EXTI3_PF ((uint16_t)0x3000) /*!< PF[3] pin */
emilmont 77:869cf507173a 4550 #define SYSCFG_EXTICR1_EXTI3_PG ((uint16_t)0x4000) /*!< PG[3] pin */
emilmont 77:869cf507173a 4551
emilmont 77:869cf507173a 4552 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
emilmont 77:869cf507173a 4553 #define SYSCFG_EXTICR2_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
emilmont 77:869cf507173a 4554 #define SYSCFG_EXTICR2_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
emilmont 77:869cf507173a 4555 #define SYSCFG_EXTICR2_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
emilmont 77:869cf507173a 4556 #define SYSCFG_EXTICR2_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
emilmont 77:869cf507173a 4557
emilmont 77:869cf507173a 4558 /**
emilmont 77:869cf507173a 4559 * @brief EXTI4 configuration
emilmont 77:869cf507173a 4560 */
emilmont 77:869cf507173a 4561 #define SYSCFG_EXTICR2_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
emilmont 77:869cf507173a 4562 #define SYSCFG_EXTICR2_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
emilmont 77:869cf507173a 4563 #define SYSCFG_EXTICR2_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
emilmont 77:869cf507173a 4564 #define SYSCFG_EXTICR2_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
emilmont 77:869cf507173a 4565 #define SYSCFG_EXTICR2_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
emilmont 77:869cf507173a 4566 #define SYSCFG_EXTICR2_EXTI4_PF ((uint16_t)0x0006) /*!< PF[4] pin */
emilmont 77:869cf507173a 4567 #define SYSCFG_EXTICR2_EXTI4_PG ((uint16_t)0x0007) /*!< PG[4] pin */
emilmont 77:869cf507173a 4568
emilmont 77:869cf507173a 4569 /**
emilmont 77:869cf507173a 4570 * @brief EXTI5 configuration
emilmont 77:869cf507173a 4571 */
emilmont 77:869cf507173a 4572 #define SYSCFG_EXTICR2_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
emilmont 77:869cf507173a 4573 #define SYSCFG_EXTICR2_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
emilmont 77:869cf507173a 4574 #define SYSCFG_EXTICR2_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
emilmont 77:869cf507173a 4575 #define SYSCFG_EXTICR2_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
emilmont 77:869cf507173a 4576 #define SYSCFG_EXTICR2_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
emilmont 77:869cf507173a 4577 #define SYSCFG_EXTICR2_EXTI5_PF ((uint16_t)0x0060) /*!< PF[5] pin */
emilmont 77:869cf507173a 4578 #define SYSCFG_EXTICR2_EXTI5_PG ((uint16_t)0x0070) /*!< PG[5] pin */
emilmont 77:869cf507173a 4579
emilmont 77:869cf507173a 4580 /**
emilmont 77:869cf507173a 4581 * @brief EXTI6 configuration
emilmont 77:869cf507173a 4582 */
emilmont 77:869cf507173a 4583 #define SYSCFG_EXTICR2_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
emilmont 77:869cf507173a 4584 #define SYSCFG_EXTICR2_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
emilmont 77:869cf507173a 4585 #define SYSCFG_EXTICR2_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
emilmont 77:869cf507173a 4586 #define SYSCFG_EXTICR2_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
emilmont 77:869cf507173a 4587 #define SYSCFG_EXTICR2_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
emilmont 77:869cf507173a 4588 #define SYSCFG_EXTICR2_EXTI6_PF ((uint16_t)0x0600) /*!< PF[6] pin */
emilmont 77:869cf507173a 4589 #define SYSCFG_EXTICR2_EXTI6_PG ((uint16_t)0x0700) /*!< PG[6] pin */
emilmont 77:869cf507173a 4590
emilmont 77:869cf507173a 4591 /**
emilmont 77:869cf507173a 4592 * @brief EXTI7 configuration
emilmont 77:869cf507173a 4593 */
emilmont 77:869cf507173a 4594 #define SYSCFG_EXTICR2_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
emilmont 77:869cf507173a 4595 #define SYSCFG_EXTICR2_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
emilmont 77:869cf507173a 4596 #define SYSCFG_EXTICR2_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
emilmont 77:869cf507173a 4597 #define SYSCFG_EXTICR2_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
emilmont 77:869cf507173a 4598 #define SYSCFG_EXTICR2_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
emilmont 77:869cf507173a 4599 #define SYSCFG_EXTICR2_EXTI7_PF ((uint16_t)0x6000) /*!< PF[7] pin */
emilmont 77:869cf507173a 4600 #define SYSCFG_EXTICR2_EXTI7_PG ((uint16_t)0x7000) /*!< PG[7] pin */
emilmont 77:869cf507173a 4601
emilmont 77:869cf507173a 4602 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
emilmont 77:869cf507173a 4603 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
emilmont 77:869cf507173a 4604 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
emilmont 77:869cf507173a 4605 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
emilmont 77:869cf507173a 4606 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
emilmont 77:869cf507173a 4607
emilmont 77:869cf507173a 4608 /**
emilmont 77:869cf507173a 4609 * @brief EXTI8 configuration
emilmont 77:869cf507173a 4610 */
emilmont 77:869cf507173a 4611 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
emilmont 77:869cf507173a 4612 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
emilmont 77:869cf507173a 4613 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
emilmont 77:869cf507173a 4614 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
emilmont 77:869cf507173a 4615 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
emilmont 77:869cf507173a 4616 #define SYSCFG_EXTICR3_EXTI8_PF ((uint16_t)0x0006) /*!< PF[8] pin */
emilmont 77:869cf507173a 4617 #define SYSCFG_EXTICR3_EXTI8_PG ((uint16_t)0x0007) /*!< PG[8] pin */
emilmont 77:869cf507173a 4618
emilmont 77:869cf507173a 4619 /**
emilmont 77:869cf507173a 4620 * @brief EXTI9 configuration
emilmont 77:869cf507173a 4621 */
emilmont 77:869cf507173a 4622 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
emilmont 77:869cf507173a 4623 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
emilmont 77:869cf507173a 4624 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
emilmont 77:869cf507173a 4625 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
emilmont 77:869cf507173a 4626 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
emilmont 77:869cf507173a 4627 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0060) /*!< PF[9] pin */
emilmont 77:869cf507173a 4628 #define SYSCFG_EXTICR3_EXTI9_PG ((uint16_t)0x0070) /*!< PG[9] pin */
emilmont 77:869cf507173a 4629
emilmont 77:869cf507173a 4630 /**
emilmont 77:869cf507173a 4631 * @brief EXTI10 configuration
emilmont 77:869cf507173a 4632 */
emilmont 77:869cf507173a 4633 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
emilmont 77:869cf507173a 4634 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
emilmont 77:869cf507173a 4635 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
emilmont 77:869cf507173a 4636 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
emilmont 77:869cf507173a 4637 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
emilmont 77:869cf507173a 4638 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0600) /*!< PF[10] pin */
emilmont 77:869cf507173a 4639 #define SYSCFG_EXTICR3_EXTI10_PG ((uint16_t)0x0700) /*!< PG[10] pin */
emilmont 77:869cf507173a 4640
emilmont 77:869cf507173a 4641 /**
emilmont 77:869cf507173a 4642 * @brief EXTI11 configuration
emilmont 77:869cf507173a 4643 */
emilmont 77:869cf507173a 4644 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
emilmont 77:869cf507173a 4645 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
emilmont 77:869cf507173a 4646 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
emilmont 77:869cf507173a 4647 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
emilmont 77:869cf507173a 4648 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
emilmont 77:869cf507173a 4649 #define SYSCFG_EXTICR3_EXTI11_PF ((uint16_t)0x6000) /*!< PF[11] pin */
emilmont 77:869cf507173a 4650 #define SYSCFG_EXTICR3_EXTI11_PG ((uint16_t)0x7000) /*!< PG[11] pin */
emilmont 77:869cf507173a 4651
emilmont 77:869cf507173a 4652 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
emilmont 77:869cf507173a 4653 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
emilmont 77:869cf507173a 4654 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
emilmont 77:869cf507173a 4655 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
emilmont 77:869cf507173a 4656 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
emilmont 77:869cf507173a 4657
emilmont 77:869cf507173a 4658 /**
emilmont 77:869cf507173a 4659 * @brief EXTI12 configuration
emilmont 77:869cf507173a 4660 */
emilmont 77:869cf507173a 4661 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
emilmont 77:869cf507173a 4662 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
emilmont 77:869cf507173a 4663 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
emilmont 77:869cf507173a 4664 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
emilmont 77:869cf507173a 4665 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
emilmont 77:869cf507173a 4666 #define SYSCFG_EXTICR4_EXTI12_PF ((uint16_t)0x0006) /*!< PF[12] pin */
emilmont 77:869cf507173a 4667 #define SYSCFG_EXTICR4_EXTI12_PG ((uint16_t)0x0007) /*!< PG[12] pin */
emilmont 77:869cf507173a 4668
emilmont 77:869cf507173a 4669 /**
emilmont 77:869cf507173a 4670 * @brief EXTI13 configuration
emilmont 77:869cf507173a 4671 */
emilmont 77:869cf507173a 4672 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
emilmont 77:869cf507173a 4673 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
emilmont 77:869cf507173a 4674 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
emilmont 77:869cf507173a 4675 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
emilmont 77:869cf507173a 4676 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
emilmont 77:869cf507173a 4677 #define SYSCFG_EXTICR4_EXTI13_PF ((uint16_t)0x0060) /*!< PF[13] pin */
emilmont 77:869cf507173a 4678 #define SYSCFG_EXTICR4_EXTI13_PG ((uint16_t)0x0070) /*!< PG[13] pin */
emilmont 77:869cf507173a 4679
emilmont 77:869cf507173a 4680 /**
emilmont 77:869cf507173a 4681 * @brief EXTI14 configuration
emilmont 77:869cf507173a 4682 */
emilmont 77:869cf507173a 4683 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
emilmont 77:869cf507173a 4684 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
emilmont 77:869cf507173a 4685 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
emilmont 77:869cf507173a 4686 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
emilmont 77:869cf507173a 4687 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
emilmont 77:869cf507173a 4688 #define SYSCFG_EXTICR4_EXTI14_PF ((uint16_t)0x0600) /*!< PF[14] pin */
emilmont 77:869cf507173a 4689 #define SYSCFG_EXTICR4_EXTI14_PG ((uint16_t)0x0700) /*!< PG[14] pin */
emilmont 77:869cf507173a 4690
emilmont 77:869cf507173a 4691 /**
emilmont 77:869cf507173a 4692 * @brief EXTI15 configuration
emilmont 77:869cf507173a 4693 */
emilmont 77:869cf507173a 4694 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
emilmont 77:869cf507173a 4695 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
emilmont 77:869cf507173a 4696 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
emilmont 77:869cf507173a 4697 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
emilmont 77:869cf507173a 4698 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
emilmont 77:869cf507173a 4699 #define SYSCFG_EXTICR4_EXTI15_PF ((uint16_t)0x6000) /*!< PF[15] pin */
emilmont 77:869cf507173a 4700 #define SYSCFG_EXTICR4_EXTI15_PG ((uint16_t)0x7000) /*!< PG[15] pin */
emilmont 77:869cf507173a 4701
emilmont 77:869cf507173a 4702 /******************************************************************************/
emilmont 77:869cf507173a 4703 /* */
emilmont 77:869cf507173a 4704 /* Routing Interface (RI) */
emilmont 77:869cf507173a 4705 /* */
emilmont 77:869cf507173a 4706 /******************************************************************************/
emilmont 77:869cf507173a 4707
emilmont 77:869cf507173a 4708 /******************** Bit definition for RI_ICR register ********************/
emilmont 77:869cf507173a 4709 #define RI_ICR_IC1Z ((uint32_t)0x0000000F) /*!< IC1Z[3:0] bits (Input Capture 1 select bits) */
emilmont 77:869cf507173a 4710 #define RI_ICR_IC1Z_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4711 #define RI_ICR_IC1Z_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4712 #define RI_ICR_IC1Z_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4713 #define RI_ICR_IC1Z_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4714
emilmont 77:869cf507173a 4715 #define RI_ICR_IC2Z ((uint32_t)0x000000F0) /*!< IC2Z[3:0] bits (Input Capture 2 select bits) */
emilmont 77:869cf507173a 4716 #define RI_ICR_IC2Z_0 ((uint32_t)0x00000010) /*!< Bit 0 */
emilmont 77:869cf507173a 4717 #define RI_ICR_IC2Z_1 ((uint32_t)0x00000020) /*!< Bit 1 */
emilmont 77:869cf507173a 4718 #define RI_ICR_IC2Z_2 ((uint32_t)0x00000040) /*!< Bit 2 */
emilmont 77:869cf507173a 4719 #define RI_ICR_IC2Z_3 ((uint32_t)0x00000080) /*!< Bit 3 */
emilmont 77:869cf507173a 4720
emilmont 77:869cf507173a 4721 #define RI_ICR_IC3Z ((uint32_t)0x00000F00) /*!< IC3Z[3:0] bits (Input Capture 3 select bits) */
emilmont 77:869cf507173a 4722 #define RI_ICR_IC3Z_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 4723 #define RI_ICR_IC3Z_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 4724 #define RI_ICR_IC3Z_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 4725 #define RI_ICR_IC3Z_3 ((uint32_t)0x00000800) /*!< Bit 3 */
emilmont 77:869cf507173a 4726
emilmont 77:869cf507173a 4727 #define RI_ICR_IC4Z ((uint32_t)0x0000F000) /*!< IC4Z[3:0] bits (Input Capture 4 select bits) */
emilmont 77:869cf507173a 4728 #define RI_ICR_IC4Z_0 ((uint32_t)0x00001000) /*!< Bit 0 */
emilmont 77:869cf507173a 4729 #define RI_ICR_IC4Z_1 ((uint32_t)0x00002000) /*!< Bit 1 */
emilmont 77:869cf507173a 4730 #define RI_ICR_IC4Z_2 ((uint32_t)0x00004000) /*!< Bit 2 */
emilmont 77:869cf507173a 4731 #define RI_ICR_IC4Z_3 ((uint32_t)0x00008000) /*!< Bit 3 */
emilmont 77:869cf507173a 4732
emilmont 77:869cf507173a 4733 #define RI_ICR_TIM ((uint32_t)0x00030000) /*!< TIM[3:0] bits (Timers select bits) */
emilmont 77:869cf507173a 4734 #define RI_ICR_TIM_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 4735 #define RI_ICR_TIM_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 4736
emilmont 77:869cf507173a 4737 #define RI_ICR_IC1 ((uint32_t)0x00040000) /*!< Input capture 1 */
emilmont 77:869cf507173a 4738 #define RI_ICR_IC2 ((uint32_t)0x00080000) /*!< Input capture 2 */
emilmont 77:869cf507173a 4739 #define RI_ICR_IC3 ((uint32_t)0x00100000) /*!< Input capture 3 */
emilmont 77:869cf507173a 4740 #define RI_ICR_IC4 ((uint32_t)0x00200000) /*!< Input capture 4 */
emilmont 77:869cf507173a 4741
emilmont 77:869cf507173a 4742 /******************** Bit definition for RI_ASCR1 register ********************/
emilmont 77:869cf507173a 4743 #define RI_ASCR1_CH ((uint32_t)0x03FCFFFF) /*!< AS_CH[25:18] & AS_CH[15:0] bits ( Analog switches selection bits) */
emilmont 77:869cf507173a 4744 #define RI_ASCR1_CH_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4745 #define RI_ASCR1_CH_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4746 #define RI_ASCR1_CH_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4747 #define RI_ASCR1_CH_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4748 #define RI_ASCR1_CH_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4749 #define RI_ASCR1_CH_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 4750 #define RI_ASCR1_CH_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 4751 #define RI_ASCR1_CH_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 4752 #define RI_ASCR1_CH_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 4753 #define RI_ASCR1_CH_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 4754 #define RI_ASCR1_CH_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 4755 #define RI_ASCR1_CH_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 4756 #define RI_ASCR1_CH_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 4757 #define RI_ASCR1_CH_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 4758 #define RI_ASCR1_CH_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 4759 #define RI_ASCR1_CH_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 4760 #define RI_ASCR1_CH_31 ((uint32_t)0x00010000) /*!< Bit 16 */
emilmont 77:869cf507173a 4761 #define RI_ASCR1_CH_18 ((uint32_t)0x00040000) /*!< Bit 18 */
emilmont 77:869cf507173a 4762 #define RI_ASCR1_CH_19 ((uint32_t)0x00080000) /*!< Bit 19 */
emilmont 77:869cf507173a 4763 #define RI_ASCR1_CH_20 ((uint32_t)0x00100000) /*!< Bit 20 */
emilmont 77:869cf507173a 4764 #define RI_ASCR1_CH_21 ((uint32_t)0x00200000) /*!< Bit 21 */
emilmont 77:869cf507173a 4765 #define RI_ASCR1_CH_22 ((uint32_t)0x00400000) /*!< Bit 22 */
emilmont 77:869cf507173a 4766 #define RI_ASCR1_CH_23 ((uint32_t)0x00800000) /*!< Bit 23 */
emilmont 77:869cf507173a 4767 #define RI_ASCR1_CH_24 ((uint32_t)0x01000000) /*!< Bit 24 */
emilmont 77:869cf507173a 4768 #define RI_ASCR1_CH_25 ((uint32_t)0x02000000) /*!< Bit 25 */
emilmont 77:869cf507173a 4769 #define RI_ASCR1_VCOMP ((uint32_t)0x04000000) /*!< ADC analog switch selection for internal node to COMP1 */
emilmont 77:869cf507173a 4770 #define RI_ASCR1_CH_27 ((uint32_t)0x00400000) /*!< Bit 27 */
emilmont 77:869cf507173a 4771 #define RI_ASCR1_CH_28 ((uint32_t)0x00800000) /*!< Bit 28 */
emilmont 77:869cf507173a 4772 #define RI_ASCR1_CH_29 ((uint32_t)0x01000000) /*!< Bit 29 */
emilmont 77:869cf507173a 4773 #define RI_ASCR1_CH_30 ((uint32_t)0x02000000) /*!< Bit 30 */
emilmont 77:869cf507173a 4774 #define RI_ASCR1_SCM ((uint32_t)0x80000000) /*!< I/O Switch control mode */
emilmont 77:869cf507173a 4775
emilmont 77:869cf507173a 4776 /******************** Bit definition for RI_ASCR2 register ********************/
emilmont 77:869cf507173a 4777 #define RI_ASCR2_GR10_1 ((uint32_t)0x00000001) /*!< GR10-1 selection bit */
emilmont 77:869cf507173a 4778 #define RI_ASCR2_GR10_2 ((uint32_t)0x00000002) /*!< GR10-2 selection bit */
emilmont 77:869cf507173a 4779 #define RI_ASCR2_GR10_3 ((uint32_t)0x00000004) /*!< GR10-3 selection bit */
emilmont 77:869cf507173a 4780 #define RI_ASCR2_GR10_4 ((uint32_t)0x00000008) /*!< GR10-4 selection bit */
emilmont 77:869cf507173a 4781 #define RI_ASCR2_GR6_1 ((uint32_t)0x00000010) /*!< GR6-1 selection bit */
emilmont 77:869cf507173a 4782 #define RI_ASCR2_GR6_2 ((uint32_t)0x00000020) /*!< GR6-2 selection bit */
emilmont 77:869cf507173a 4783 #define RI_ASCR2_GR5_1 ((uint32_t)0x00000040) /*!< GR5-1 selection bit */
emilmont 77:869cf507173a 4784 #define RI_ASCR2_GR5_2 ((uint32_t)0x00000080) /*!< GR5-2 selection bit */
emilmont 77:869cf507173a 4785 #define RI_ASCR2_GR5_3 ((uint32_t)0x00000100) /*!< GR5-3 selection bit */
emilmont 77:869cf507173a 4786 #define RI_ASCR2_GR4_1 ((uint32_t)0x00000200) /*!< GR4-1 selection bit */
emilmont 77:869cf507173a 4787 #define RI_ASCR2_GR4_2 ((uint32_t)0x00000400) /*!< GR4-2 selection bit */
emilmont 77:869cf507173a 4788 #define RI_ASCR2_GR4_3 ((uint32_t)0x00000800) /*!< GR4-3 selection bit */
emilmont 77:869cf507173a 4789 #define RI_ASCR2_GR4_4 ((uint32_t)0x00008000) /*!< GR4-4 selection bit */
emilmont 77:869cf507173a 4790 #define RI_ASCR2_CH0b ((uint32_t)0x00010000) /*!< CH0b selection bit */
emilmont 77:869cf507173a 4791 #define RI_ASCR2_CH1b ((uint32_t)0x00020000) /*!< CH1b selection bit */
emilmont 77:869cf507173a 4792 #define RI_ASCR2_CH2b ((uint32_t)0x00040000) /*!< CH2b selection bit */
emilmont 77:869cf507173a 4793 #define RI_ASCR2_CH3b ((uint32_t)0x00080000) /*!< CH3b selection bit */
emilmont 77:869cf507173a 4794 #define RI_ASCR2_CH6b ((uint32_t)0x00100000) /*!< CH6b selection bit */
emilmont 77:869cf507173a 4795 #define RI_ASCR2_CH7b ((uint32_t)0x00200000) /*!< CH7b selection bit */
emilmont 77:869cf507173a 4796 #define RI_ASCR2_CH8b ((uint32_t)0x00400000) /*!< CH8b selection bit */
emilmont 77:869cf507173a 4797 #define RI_ASCR2_CH9b ((uint32_t)0x00800000) /*!< CH9b selection bit */
emilmont 77:869cf507173a 4798 #define RI_ASCR2_CH10b ((uint32_t)0x01000000) /*!< CH10b selection bit */
emilmont 77:869cf507173a 4799 #define RI_ASCR2_CH11b ((uint32_t)0x02000000) /*!< CH11b selection bit */
emilmont 77:869cf507173a 4800 #define RI_ASCR2_CH12b ((uint32_t)0x04000000) /*!< CH12b selection bit */
emilmont 77:869cf507173a 4801 #define RI_ASCR2_GR6_3 ((uint32_t)0x08000000) /*!< GR6-3 selection bit */
emilmont 77:869cf507173a 4802 #define RI_ASCR2_GR6_4 ((uint32_t)0x10000000) /*!< GR6-4 selection bit */
emilmont 77:869cf507173a 4803 #define RI_ASCR2_GR5_4 ((uint32_t)0x20000000) /*!< GR5-4 selection bit */
emilmont 77:869cf507173a 4804
emilmont 77:869cf507173a 4805 /******************** Bit definition for RI_HYSCR1 register ********************/
emilmont 77:869cf507173a 4806 #define RI_HYSCR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A Hysteresis selection */
emilmont 77:869cf507173a 4807 #define RI_HYSCR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4808 #define RI_HYSCR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4809 #define RI_HYSCR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4810 #define RI_HYSCR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4811 #define RI_HYSCR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4812 #define RI_HYSCR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 4813 #define RI_HYSCR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 4814 #define RI_HYSCR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 4815 #define RI_HYSCR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 4816 #define RI_HYSCR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 4817 #define RI_HYSCR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 4818 #define RI_HYSCR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 4819 #define RI_HYSCR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 4820 #define RI_HYSCR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 4821 #define RI_HYSCR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 4822 #define RI_HYSCR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 4823
emilmont 77:869cf507173a 4824 #define RI_HYSCR1_PB ((uint32_t)0xFFFF0000) /*!< PB[15:0] Port B Hysteresis selection */
emilmont 77:869cf507173a 4825 #define RI_HYSCR1_PB_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 4826 #define RI_HYSCR1_PB_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 4827 #define RI_HYSCR1_PB_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 4828 #define RI_HYSCR1_PB_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 4829 #define RI_HYSCR1_PB_4 ((uint32_t)0x00100000) /*!< Bit 4 */
emilmont 77:869cf507173a 4830 #define RI_HYSCR1_PB_5 ((uint32_t)0x00200000) /*!< Bit 5 */
emilmont 77:869cf507173a 4831 #define RI_HYSCR1_PB_6 ((uint32_t)0x00400000) /*!< Bit 6 */
emilmont 77:869cf507173a 4832 #define RI_HYSCR1_PB_7 ((uint32_t)0x00800000) /*!< Bit 7 */
emilmont 77:869cf507173a 4833 #define RI_HYSCR1_PB_8 ((uint32_t)0x01000000) /*!< Bit 8 */
emilmont 77:869cf507173a 4834 #define RI_HYSCR1_PB_9 ((uint32_t)0x02000000) /*!< Bit 9 */
emilmont 77:869cf507173a 4835 #define RI_HYSCR1_PB_10 ((uint32_t)0x04000000) /*!< Bit 10 */
emilmont 77:869cf507173a 4836 #define RI_HYSCR1_PB_11 ((uint32_t)0x08000000) /*!< Bit 11 */
emilmont 77:869cf507173a 4837 #define RI_HYSCR1_PB_12 ((uint32_t)0x10000000) /*!< Bit 12 */
emilmont 77:869cf507173a 4838 #define RI_HYSCR1_PB_13 ((uint32_t)0x20000000) /*!< Bit 13 */
emilmont 77:869cf507173a 4839 #define RI_HYSCR1_PB_14 ((uint32_t)0x40000000) /*!< Bit 14 */
emilmont 77:869cf507173a 4840 #define RI_HYSCR1_PB_15 ((uint32_t)0x80000000) /*!< Bit 15 */
emilmont 77:869cf507173a 4841
emilmont 77:869cf507173a 4842 /******************** Bit definition for RI_HYSCR2 register ********************/
emilmont 77:869cf507173a 4843 #define RI_HYSCR2_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C Hysteresis selection */
emilmont 77:869cf507173a 4844 #define RI_HYSCR2_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4845 #define RI_HYSCR2_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4846 #define RI_HYSCR2_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4847 #define RI_HYSCR2_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4848 #define RI_HYSCR2_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4849 #define RI_HYSCR2_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 4850 #define RI_HYSCR2_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 4851 #define RI_HYSCR2_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 4852 #define RI_HYSCR2_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 4853 #define RI_HYSCR2_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 4854 #define RI_HYSCR2_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 4855 #define RI_HYSCR2_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 4856 #define RI_HYSCR2_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 4857 #define RI_HYSCR2_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 4858 #define RI_HYSCR2_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 4859 #define RI_HYSCR2_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 4860
emilmont 77:869cf507173a 4861 #define RI_HYSCR2_PD ((uint32_t)0xFFFF0000) /*!< PD[15:0] Port D Hysteresis selection */
emilmont 77:869cf507173a 4862 #define RI_HYSCR2_PD_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 4863 #define RI_HYSCR2_PD_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 4864 #define RI_HYSCR2_PD_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 4865 #define RI_HYSCR2_PD_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 4866 #define RI_HYSCR2_PD_4 ((uint32_t)0x00100000) /*!< Bit 4 */
emilmont 77:869cf507173a 4867 #define RI_HYSCR2_PD_5 ((uint32_t)0x00200000) /*!< Bit 5 */
emilmont 77:869cf507173a 4868 #define RI_HYSCR2_PD_6 ((uint32_t)0x00400000) /*!< Bit 6 */
emilmont 77:869cf507173a 4869 #define RI_HYSCR2_PD_7 ((uint32_t)0x00800000) /*!< Bit 7 */
emilmont 77:869cf507173a 4870 #define RI_HYSCR2_PD_8 ((uint32_t)0x01000000) /*!< Bit 8 */
emilmont 77:869cf507173a 4871 #define RI_HYSCR2_PD_9 ((uint32_t)0x02000000) /*!< Bit 9 */
emilmont 77:869cf507173a 4872 #define RI_HYSCR2_PD_10 ((uint32_t)0x04000000) /*!< Bit 10 */
emilmont 77:869cf507173a 4873 #define RI_HYSCR2_PD_11 ((uint32_t)0x08000000) /*!< Bit 11 */
emilmont 77:869cf507173a 4874 #define RI_HYSCR2_PD_12 ((uint32_t)0x10000000) /*!< Bit 12 */
emilmont 77:869cf507173a 4875 #define RI_HYSCR2_PD_13 ((uint32_t)0x20000000) /*!< Bit 13 */
emilmont 77:869cf507173a 4876 #define RI_HYSCR2_PD_14 ((uint32_t)0x40000000) /*!< Bit 14 */
emilmont 77:869cf507173a 4877 #define RI_HYSCR2_PD_15 ((uint32_t)0x80000000) /*!< Bit 15 */
emilmont 77:869cf507173a 4878
emilmont 77:869cf507173a 4879 /******************** Bit definition for RI_HYSCR3 register ********************/
emilmont 77:869cf507173a 4880 #define RI_HYSCR2_PE ((uint32_t)0x0000FFFF) /*!< PE[15:0] Port E Hysteresis selection */
emilmont 77:869cf507173a 4881 #define RI_HYSCR2_PE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4882 #define RI_HYSCR2_PE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4883 #define RI_HYSCR2_PE_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4884 #define RI_HYSCR2_PE_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4885 #define RI_HYSCR2_PE_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4886 #define RI_HYSCR2_PE_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 4887 #define RI_HYSCR2_PE_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 4888 #define RI_HYSCR2_PE_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 4889 #define RI_HYSCR2_PE_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 4890 #define RI_HYSCR2_PE_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 4891 #define RI_HYSCR2_PE_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 4892 #define RI_HYSCR2_PE_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 4893 #define RI_HYSCR2_PE_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 4894 #define RI_HYSCR2_PE_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 4895 #define RI_HYSCR2_PE_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 4896 #define RI_HYSCR2_PE_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 4897
emilmont 77:869cf507173a 4898 #define RI_HYSCR3_PF ((uint32_t)0xFFFF0000) /*!< PF[15:0] Port F Hysteresis selection */
emilmont 77:869cf507173a 4899 #define RI_HYSCR3_PF_0 ((uint32_t)0x00010000) /*!< Bit 0 */
emilmont 77:869cf507173a 4900 #define RI_HYSCR3_PF_1 ((uint32_t)0x00020000) /*!< Bit 1 */
emilmont 77:869cf507173a 4901 #define RI_HYSCR3_PF_2 ((uint32_t)0x00040000) /*!< Bit 2 */
emilmont 77:869cf507173a 4902 #define RI_HYSCR3_PF_3 ((uint32_t)0x00080000) /*!< Bit 3 */
emilmont 77:869cf507173a 4903 #define RI_HYSCR3_PF_4 ((uint32_t)0x00100000) /*!< Bit 4 */
emilmont 77:869cf507173a 4904 #define RI_HYSCR3_PF_5 ((uint32_t)0x00200000) /*!< Bit 5 */
emilmont 77:869cf507173a 4905 #define RI_HYSCR3_PF_6 ((uint32_t)0x00400000) /*!< Bit 6 */
emilmont 77:869cf507173a 4906 #define RI_HYSCR3_PF_7 ((uint32_t)0x00800000) /*!< Bit 7 */
emilmont 77:869cf507173a 4907 #define RI_HYSCR3_PF_8 ((uint32_t)0x01000000) /*!< Bit 8 */
emilmont 77:869cf507173a 4908 #define RI_HYSCR3_PF_9 ((uint32_t)0x02000000) /*!< Bit 9 */
emilmont 77:869cf507173a 4909 #define RI_HYSCR3_PF_10 ((uint32_t)0x04000000) /*!< Bit 10 */
emilmont 77:869cf507173a 4910 #define RI_HYSCR3_PF_11 ((uint32_t)0x08000000) /*!< Bit 11 */
emilmont 77:869cf507173a 4911 #define RI_HYSCR3_PF_12 ((uint32_t)0x10000000) /*!< Bit 12 */
emilmont 77:869cf507173a 4912 #define RI_HYSCR3_PF_13 ((uint32_t)0x20000000) /*!< Bit 13 */
emilmont 77:869cf507173a 4913 #define RI_HYSCR3_PF_14 ((uint32_t)0x40000000) /*!< Bit 14 */
emilmont 77:869cf507173a 4914 #define RI_HYSCR3_PF_15 ((uint32_t)0x80000000) /*!< Bit 15 */
emilmont 77:869cf507173a 4915
emilmont 77:869cf507173a 4916 /******************** Bit definition for RI_HYSCR4 register ********************/
emilmont 77:869cf507173a 4917 #define RI_HYSCR4_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G Hysteresis selection */
emilmont 77:869cf507173a 4918 #define RI_HYSCR4_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4919 #define RI_HYSCR4_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4920 #define RI_HYSCR4_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4921 #define RI_HYSCR4_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4922 #define RI_HYSCR4_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4923 #define RI_HYSCR4_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 4924 #define RI_HYSCR4_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 4925 #define RI_HYSCR4_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 4926 #define RI_HYSCR4_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 4927 #define RI_HYSCR4_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 4928 #define RI_HYSCR4_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 4929 #define RI_HYSCR4_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 4930 #define RI_HYSCR4_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 4931 #define RI_HYSCR4_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 4932 #define RI_HYSCR4_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 4933 #define RI_HYSCR4_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 4934
emilmont 77:869cf507173a 4935 /******************** Bit definition for RI_ASMR1 register ********************/
emilmont 77:869cf507173a 4936 #define RI_ASMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A analog switch mode selection */
emilmont 77:869cf507173a 4937 #define RI_ASMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4938 #define RI_ASMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4939 #define RI_ASMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4940 #define RI_ASMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4941 #define RI_ASMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4942 #define RI_ASMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 4943 #define RI_ASMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 4944 #define RI_ASMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 4945 #define RI_ASMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 4946 #define RI_ASMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 4947 #define RI_ASMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 4948 #define RI_ASMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 4949 #define RI_ASMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 4950 #define RI_ASMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 4951 #define RI_ASMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 4952 #define RI_ASMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 4953
emilmont 77:869cf507173a 4954 /******************** Bit definition for RI_CMR1 register ********************/
emilmont 77:869cf507173a 4955 #define RI_CMR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A channel masking */
emilmont 77:869cf507173a 4956 #define RI_CMR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4957 #define RI_CMR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4958 #define RI_CMR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4959 #define RI_CMR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4960 #define RI_CMR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4961 #define RI_CMR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 4962 #define RI_CMR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 4963 #define RI_CMR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 4964 #define RI_CMR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 4965 #define RI_CMR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 4966 #define RI_CMR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 4967 #define RI_CMR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 4968 #define RI_CMR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 4969 #define RI_CMR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 4970 #define RI_CMR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 4971 #define RI_CMR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 4972
emilmont 77:869cf507173a 4973 /******************** Bit definition for RI_CICR1 register ********************/
emilmont 77:869cf507173a 4974 #define RI_CICR1_PA ((uint32_t)0x0000FFFF) /*!< PA[15:0] Port A channel identification for capture */
emilmont 77:869cf507173a 4975 #define RI_CICR1_PA_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4976 #define RI_CICR1_PA_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4977 #define RI_CICR1_PA_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4978 #define RI_CICR1_PA_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4979 #define RI_CICR1_PA_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4980 #define RI_CICR1_PA_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 4981 #define RI_CICR1_PA_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 4982 #define RI_CICR1_PA_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 4983 #define RI_CICR1_PA_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 4984 #define RI_CICR1_PA_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 4985 #define RI_CICR1_PA_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 4986 #define RI_CICR1_PA_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 4987 #define RI_CICR1_PA_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 4988 #define RI_CICR1_PA_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 4989 #define RI_CICR1_PA_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 4990 #define RI_CICR1_PA_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 4991
emilmont 77:869cf507173a 4992 /******************** Bit definition for RI_ASMR2 register ********************/
emilmont 77:869cf507173a 4993 #define RI_ASMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B analog switch mode selection */
emilmont 77:869cf507173a 4994 #define RI_ASMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 4995 #define RI_ASMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 4996 #define RI_ASMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 4997 #define RI_ASMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 4998 #define RI_ASMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 4999 #define RI_ASMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5000 #define RI_ASMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5001 #define RI_ASMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5002 #define RI_ASMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5003 #define RI_ASMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5004 #define RI_ASMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5005 #define RI_ASMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5006 #define RI_ASMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5007 #define RI_ASMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5008 #define RI_ASMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5009 #define RI_ASMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5010
emilmont 77:869cf507173a 5011 /******************** Bit definition for RI_CMR2 register ********************/
emilmont 77:869cf507173a 5012 #define RI_CMR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B channel masking */
emilmont 77:869cf507173a 5013 #define RI_CMR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5014 #define RI_CMR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5015 #define RI_CMR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5016 #define RI_CMR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5017 #define RI_CMR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5018 #define RI_CMR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5019 #define RI_CMR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5020 #define RI_CMR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5021 #define RI_CMR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5022 #define RI_CMR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5023 #define RI_CMR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5024 #define RI_CMR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5025 #define RI_CMR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5026 #define RI_CMR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5027 #define RI_CMR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5028 #define RI_CMR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5029
emilmont 77:869cf507173a 5030 /******************** Bit definition for RI_CICR2 register ********************/
emilmont 77:869cf507173a 5031 #define RI_CICR2_PB ((uint32_t)0x0000FFFF) /*!< PB[15:0] Port B channel identification for capture */
emilmont 77:869cf507173a 5032 #define RI_CICR2_PB_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5033 #define RI_CICR2_PB_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5034 #define RI_CICR2_PB_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5035 #define RI_CICR2_PB_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5036 #define RI_CICR2_PB_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5037 #define RI_CICR2_PB_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5038 #define RI_CICR2_PB_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5039 #define RI_CICR2_PB_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5040 #define RI_CICR2_PB_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5041 #define RI_CICR2_PB_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5042 #define RI_CICR2_PB_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5043 #define RI_CICR2_PB_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5044 #define RI_CICR2_PB_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5045 #define RI_CICR2_PB_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5046 #define RI_CICR2_PB_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5047 #define RI_CICR2_PB_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5048
emilmont 77:869cf507173a 5049 /******************** Bit definition for RI_ASMR3 register ********************/
emilmont 77:869cf507173a 5050 #define RI_ASMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C analog switch mode selection */
emilmont 77:869cf507173a 5051 #define RI_ASMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5052 #define RI_ASMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5053 #define RI_ASMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5054 #define RI_ASMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5055 #define RI_ASMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5056 #define RI_ASMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5057 #define RI_ASMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5058 #define RI_ASMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5059 #define RI_ASMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5060 #define RI_ASMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5061 #define RI_ASMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5062 #define RI_ASMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5063 #define RI_ASMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5064 #define RI_ASMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5065 #define RI_ASMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5066 #define RI_ASMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5067
emilmont 77:869cf507173a 5068 /******************** Bit definition for RI_CMR3 register ********************/
emilmont 77:869cf507173a 5069 #define RI_CMR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C channel masking */
emilmont 77:869cf507173a 5070 #define RI_CMR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5071 #define RI_CMR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5072 #define RI_CMR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5073 #define RI_CMR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5074 #define RI_CMR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5075 #define RI_CMR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5076 #define RI_CMR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5077 #define RI_CMR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5078 #define RI_CMR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5079 #define RI_CMR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5080 #define RI_CMR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5081 #define RI_CMR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5082 #define RI_CMR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5083 #define RI_CMR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5084 #define RI_CMR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5085 #define RI_CMR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5086
emilmont 77:869cf507173a 5087 /******************** Bit definition for RI_CICR3 register ********************/
emilmont 77:869cf507173a 5088 #define RI_CICR3_PC ((uint32_t)0x0000FFFF) /*!< PC[15:0] Port C channel identification for capture */
emilmont 77:869cf507173a 5089 #define RI_CICR3_PC_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5090 #define RI_CICR3_PC_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5091 #define RI_CICR3_PC_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5092 #define RI_CICR3_PC_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5093 #define RI_CICR3_PC_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5094 #define RI_CICR3_PC_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5095 #define RI_CICR3_PC_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5096 #define RI_CICR3_PC_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5097 #define RI_CICR3_PC_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5098 #define RI_CICR3_PC_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5099 #define RI_CICR3_PC_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5100 #define RI_CICR3_PC_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5101 #define RI_CICR3_PC_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5102 #define RI_CICR3_PC_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5103 #define RI_CICR3_PC_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5104 #define RI_CICR3_PC_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5105
emilmont 77:869cf507173a 5106 /******************** Bit definition for RI_ASMR4 register ********************/
emilmont 77:869cf507173a 5107 #define RI_ASMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F analog switch mode selection */
emilmont 77:869cf507173a 5108 #define RI_ASMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5109 #define RI_ASMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5110 #define RI_ASMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5111 #define RI_ASMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5112 #define RI_ASMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5113 #define RI_ASMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5114 #define RI_ASMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5115 #define RI_ASMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5116 #define RI_ASMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5117 #define RI_ASMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5118 #define RI_ASMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5119 #define RI_ASMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5120 #define RI_ASMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5121 #define RI_ASMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5122 #define RI_ASMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5123 #define RI_ASMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5124
emilmont 77:869cf507173a 5125 /******************** Bit definition for RI_CMR4 register ********************/
emilmont 77:869cf507173a 5126 #define RI_CMR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F channel masking */
emilmont 77:869cf507173a 5127 #define RI_CMR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5128 #define RI_CMR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5129 #define RI_CMR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5130 #define RI_CMR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5131 #define RI_CMR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5132 #define RI_CMR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5133 #define RI_CMR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5134 #define RI_CMR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5135 #define RI_CMR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5136 #define RI_CMR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5137 #define RI_CMR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5138 #define RI_CMR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5139 #define RI_CMR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5140 #define RI_CMR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5141 #define RI_CMR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5142 #define RI_CMR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5143
emilmont 77:869cf507173a 5144 /******************** Bit definition for RI_CICR4 register ********************/
emilmont 77:869cf507173a 5145 #define RI_CICR4_PF ((uint32_t)0x0000FFFF) /*!< PF[15:0] Port F channel identification for capture */
emilmont 77:869cf507173a 5146 #define RI_CICR4_PF_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5147 #define RI_CICR4_PF_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5148 #define RI_CICR4_PF_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5149 #define RI_CICR4_PF_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5150 #define RI_CICR4_PF_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5151 #define RI_CICR4_PF_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5152 #define RI_CICR4_PF_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5153 #define RI_CICR4_PF_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5154 #define RI_CICR4_PF_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5155 #define RI_CICR4_PF_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5156 #define RI_CICR4_PF_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5157 #define RI_CICR4_PF_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5158 #define RI_CICR4_PF_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5159 #define RI_CICR4_PF_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5160 #define RI_CICR4_PF_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5161 #define RI_CICR4_PF_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5162
emilmont 77:869cf507173a 5163 /******************** Bit definition for RI_ASMR5 register ********************/
emilmont 77:869cf507173a 5164 #define RI_ASMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G analog switch mode selection */
emilmont 77:869cf507173a 5165 #define RI_ASMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5166 #define RI_ASMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5167 #define RI_ASMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5168 #define RI_ASMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5169 #define RI_ASMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5170 #define RI_ASMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5171 #define RI_ASMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5172 #define RI_ASMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5173 #define RI_ASMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5174 #define RI_ASMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5175 #define RI_ASMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5176 #define RI_ASMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5177 #define RI_ASMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5178 #define RI_ASMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5179 #define RI_ASMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5180 #define RI_ASMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5181
emilmont 77:869cf507173a 5182 /******************** Bit definition for RI_CMR5 register ********************/
emilmont 77:869cf507173a 5183 #define RI_CMR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G channel masking */
emilmont 77:869cf507173a 5184 #define RI_CMR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5185 #define RI_CMR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5186 #define RI_CMR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5187 #define RI_CMR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5188 #define RI_CMR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5189 #define RI_CMR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5190 #define RI_CMR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5191 #define RI_CMR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5192 #define RI_CMR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5193 #define RI_CMR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5194 #define RI_CMR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5195 #define RI_CMR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5196 #define RI_CMR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5197 #define RI_CMR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5198 #define RI_CMR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5199 #define RI_CMR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5200
emilmont 77:869cf507173a 5201 /******************** Bit definition for RI_CICR5 register ********************/
emilmont 77:869cf507173a 5202 #define RI_CICR5_PG ((uint32_t)0x0000FFFF) /*!< PG[15:0] Port G channel identification for capture */
emilmont 77:869cf507173a 5203 #define RI_CICR5_PG_0 ((uint32_t)0x00000001) /*!< Bit 0 */
emilmont 77:869cf507173a 5204 #define RI_CICR5_PG_1 ((uint32_t)0x00000002) /*!< Bit 1 */
emilmont 77:869cf507173a 5205 #define RI_CICR5_PG_2 ((uint32_t)0x00000004) /*!< Bit 2 */
emilmont 77:869cf507173a 5206 #define RI_CICR5_PG_3 ((uint32_t)0x00000008) /*!< Bit 3 */
emilmont 77:869cf507173a 5207 #define RI_CICR5_PG_4 ((uint32_t)0x00000010) /*!< Bit 4 */
emilmont 77:869cf507173a 5208 #define RI_CICR5_PG_5 ((uint32_t)0x00000020) /*!< Bit 5 */
emilmont 77:869cf507173a 5209 #define RI_CICR5_PG_6 ((uint32_t)0x00000040) /*!< Bit 6 */
emilmont 77:869cf507173a 5210 #define RI_CICR5_PG_7 ((uint32_t)0x00000080) /*!< Bit 7 */
emilmont 77:869cf507173a 5211 #define RI_CICR5_PG_8 ((uint32_t)0x00000100) /*!< Bit 8 */
emilmont 77:869cf507173a 5212 #define RI_CICR5_PG_9 ((uint32_t)0x00000200) /*!< Bit 9 */
emilmont 77:869cf507173a 5213 #define RI_CICR5_PG_10 ((uint32_t)0x00000400) /*!< Bit 10 */
emilmont 77:869cf507173a 5214 #define RI_CICR5_PG_11 ((uint32_t)0x00000800) /*!< Bit 11 */
emilmont 77:869cf507173a 5215 #define RI_CICR5_PG_12 ((uint32_t)0x00001000) /*!< Bit 12 */
emilmont 77:869cf507173a 5216 #define RI_CICR5_PG_13 ((uint32_t)0x00002000) /*!< Bit 13 */
emilmont 77:869cf507173a 5217 #define RI_CICR5_PG_14 ((uint32_t)0x00004000) /*!< Bit 14 */
emilmont 77:869cf507173a 5218 #define RI_CICR5_PG_15 ((uint32_t)0x00008000) /*!< Bit 15 */
emilmont 77:869cf507173a 5219
emilmont 77:869cf507173a 5220 /******************************************************************************/
emilmont 77:869cf507173a 5221 /* */
emilmont 77:869cf507173a 5222 /* Timers (TIM) */
emilmont 77:869cf507173a 5223 /* */
emilmont 77:869cf507173a 5224 /******************************************************************************/
emilmont 77:869cf507173a 5225
emilmont 77:869cf507173a 5226 /******************* Bit definition for TIM_CR1 register ********************/
emilmont 77:869cf507173a 5227 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
emilmont 77:869cf507173a 5228 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
emilmont 77:869cf507173a 5229 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
emilmont 77:869cf507173a 5230 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
emilmont 77:869cf507173a 5231 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
emilmont 77:869cf507173a 5232
emilmont 77:869cf507173a 5233 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
emilmont 77:869cf507173a 5234 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
emilmont 77:869cf507173a 5235 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
emilmont 77:869cf507173a 5236
emilmont 77:869cf507173a 5237 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
emilmont 77:869cf507173a 5238
emilmont 77:869cf507173a 5239 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
emilmont 77:869cf507173a 5240 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 5241 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 5242
emilmont 77:869cf507173a 5243 /******************* Bit definition for TIM_CR2 register ********************/
emilmont 77:869cf507173a 5244 #define TIM_CR2_CCDS ((uint16_t)0x0008) /*!<Capture/Compare DMA Selection */
emilmont 77:869cf507173a 5245
emilmont 77:869cf507173a 5246 #define TIM_CR2_MMS ((uint16_t)0x0070) /*!<MMS[2:0] bits (Master Mode Selection) */
emilmont 77:869cf507173a 5247 #define TIM_CR2_MMS_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5248 #define TIM_CR2_MMS_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5249 #define TIM_CR2_MMS_2 ((uint16_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 5250
emilmont 77:869cf507173a 5251 #define TIM_CR2_TI1S ((uint16_t)0x0080) /*!<TI1 Selection */
emilmont 77:869cf507173a 5252
emilmont 77:869cf507173a 5253 /******************* Bit definition for TIM_SMCR register *******************/
emilmont 77:869cf507173a 5254 #define TIM_SMCR_SMS ((uint16_t)0x0007) /*!<SMS[2:0] bits (Slave mode selection) */
emilmont 77:869cf507173a 5255 #define TIM_SMCR_SMS_0 ((uint16_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 5256 #define TIM_SMCR_SMS_1 ((uint16_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 5257 #define TIM_SMCR_SMS_2 ((uint16_t)0x0004) /*!<Bit 2 */
emilmont 77:869cf507173a 5258
emilmont 77:869cf507173a 5259 #define TIM_SMCR_OCCS ((uint16_t)0x0008) /*!<OCCS bits (OCref Clear Selection) */
emilmont 77:869cf507173a 5260
emilmont 77:869cf507173a 5261 #define TIM_SMCR_TS ((uint16_t)0x0070) /*!<TS[2:0] bits (Trigger selection) */
emilmont 77:869cf507173a 5262 #define TIM_SMCR_TS_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5263 #define TIM_SMCR_TS_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5264 #define TIM_SMCR_TS_2 ((uint16_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 5265
emilmont 77:869cf507173a 5266 #define TIM_SMCR_MSM ((uint16_t)0x0080) /*!<Master/slave mode */
emilmont 77:869cf507173a 5267
emilmont 77:869cf507173a 5268 #define TIM_SMCR_ETF ((uint16_t)0x0F00) /*!<ETF[3:0] bits (External trigger filter) */
emilmont 77:869cf507173a 5269 #define TIM_SMCR_ETF_0 ((uint16_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 5270 #define TIM_SMCR_ETF_1 ((uint16_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 5271 #define TIM_SMCR_ETF_2 ((uint16_t)0x0400) /*!<Bit 2 */
emilmont 77:869cf507173a 5272 #define TIM_SMCR_ETF_3 ((uint16_t)0x0800) /*!<Bit 3 */
emilmont 77:869cf507173a 5273
emilmont 77:869cf507173a 5274 #define TIM_SMCR_ETPS ((uint16_t)0x3000) /*!<ETPS[1:0] bits (External trigger prescaler) */
emilmont 77:869cf507173a 5275 #define TIM_SMCR_ETPS_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5276 #define TIM_SMCR_ETPS_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5277
emilmont 77:869cf507173a 5278 #define TIM_SMCR_ECE ((uint16_t)0x4000) /*!<External clock enable */
emilmont 77:869cf507173a 5279 #define TIM_SMCR_ETP ((uint16_t)0x8000) /*!<External trigger polarity */
emilmont 77:869cf507173a 5280
emilmont 77:869cf507173a 5281 /******************* Bit definition for TIM_DIER register *******************/
emilmont 77:869cf507173a 5282 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
emilmont 77:869cf507173a 5283 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
emilmont 77:869cf507173a 5284 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
emilmont 77:869cf507173a 5285 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
emilmont 77:869cf507173a 5286 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
emilmont 77:869cf507173a 5287 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
emilmont 77:869cf507173a 5288 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
emilmont 77:869cf507173a 5289 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
emilmont 77:869cf507173a 5290 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
emilmont 77:869cf507173a 5291 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
emilmont 77:869cf507173a 5292 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
emilmont 77:869cf507173a 5293 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
emilmont 77:869cf507173a 5294
emilmont 77:869cf507173a 5295 /******************** Bit definition for TIM_SR register ********************/
emilmont 77:869cf507173a 5296 #define TIM_SR_UIF ((uint16_t)0x0001) /*!<Update interrupt Flag */
emilmont 77:869cf507173a 5297 #define TIM_SR_CC1IF ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt Flag */
emilmont 77:869cf507173a 5298 #define TIM_SR_CC2IF ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt Flag */
emilmont 77:869cf507173a 5299 #define TIM_SR_CC3IF ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt Flag */
emilmont 77:869cf507173a 5300 #define TIM_SR_CC4IF ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt Flag */
emilmont 77:869cf507173a 5301 #define TIM_SR_TIF ((uint16_t)0x0040) /*!<Trigger interrupt Flag */
emilmont 77:869cf507173a 5302 #define TIM_SR_CC1OF ((uint16_t)0x0200) /*!<Capture/Compare 1 Overcapture Flag */
emilmont 77:869cf507173a 5303 #define TIM_SR_CC2OF ((uint16_t)0x0400) /*!<Capture/Compare 2 Overcapture Flag */
emilmont 77:869cf507173a 5304 #define TIM_SR_CC3OF ((uint16_t)0x0800) /*!<Capture/Compare 3 Overcapture Flag */
emilmont 77:869cf507173a 5305 #define TIM_SR_CC4OF ((uint16_t)0x1000) /*!<Capture/Compare 4 Overcapture Flag */
emilmont 77:869cf507173a 5306
emilmont 77:869cf507173a 5307 /******************* Bit definition for TIM_EGR register ********************/
emilmont 77:869cf507173a 5308 #define TIM_EGR_UG ((uint8_t)0x01) /*!<Update Generation */
emilmont 77:869cf507173a 5309 #define TIM_EGR_CC1G ((uint8_t)0x02) /*!<Capture/Compare 1 Generation */
emilmont 77:869cf507173a 5310 #define TIM_EGR_CC2G ((uint8_t)0x04) /*!<Capture/Compare 2 Generation */
emilmont 77:869cf507173a 5311 #define TIM_EGR_CC3G ((uint8_t)0x08) /*!<Capture/Compare 3 Generation */
emilmont 77:869cf507173a 5312 #define TIM_EGR_CC4G ((uint8_t)0x10) /*!<Capture/Compare 4 Generation */
emilmont 77:869cf507173a 5313 #define TIM_EGR_TG ((uint8_t)0x40) /*!<Trigger Generation */
emilmont 77:869cf507173a 5314
emilmont 77:869cf507173a 5315 /****************** Bit definition for TIM_CCMR1 register *******************/
emilmont 77:869cf507173a 5316 #define TIM_CCMR1_CC1S ((uint16_t)0x0003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
emilmont 77:869cf507173a 5317 #define TIM_CCMR1_CC1S_0 ((uint16_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 5318 #define TIM_CCMR1_CC1S_1 ((uint16_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 5319
emilmont 77:869cf507173a 5320 #define TIM_CCMR1_OC1FE ((uint16_t)0x0004) /*!<Output Compare 1 Fast enable */
emilmont 77:869cf507173a 5321 #define TIM_CCMR1_OC1PE ((uint16_t)0x0008) /*!<Output Compare 1 Preload enable */
emilmont 77:869cf507173a 5322
emilmont 77:869cf507173a 5323 #define TIM_CCMR1_OC1M ((uint16_t)0x0070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
emilmont 77:869cf507173a 5324 #define TIM_CCMR1_OC1M_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5325 #define TIM_CCMR1_OC1M_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5326 #define TIM_CCMR1_OC1M_2 ((uint16_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 5327
emilmont 77:869cf507173a 5328 #define TIM_CCMR1_OC1CE ((uint16_t)0x0080) /*!<Output Compare 1Clear Enable */
emilmont 77:869cf507173a 5329
emilmont 77:869cf507173a 5330 #define TIM_CCMR1_CC2S ((uint16_t)0x0300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
emilmont 77:869cf507173a 5331 #define TIM_CCMR1_CC2S_0 ((uint16_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 5332 #define TIM_CCMR1_CC2S_1 ((uint16_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 5333
emilmont 77:869cf507173a 5334 #define TIM_CCMR1_OC2FE ((uint16_t)0x0400) /*!<Output Compare 2 Fast enable */
emilmont 77:869cf507173a 5335 #define TIM_CCMR1_OC2PE ((uint16_t)0x0800) /*!<Output Compare 2 Preload enable */
emilmont 77:869cf507173a 5336
emilmont 77:869cf507173a 5337 #define TIM_CCMR1_OC2M ((uint16_t)0x7000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
emilmont 77:869cf507173a 5338 #define TIM_CCMR1_OC2M_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5339 #define TIM_CCMR1_OC2M_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5340 #define TIM_CCMR1_OC2M_2 ((uint16_t)0x4000) /*!<Bit 2 */
emilmont 77:869cf507173a 5341
emilmont 77:869cf507173a 5342 #define TIM_CCMR1_OC2CE ((uint16_t)0x8000) /*!<Output Compare 2 Clear Enable */
emilmont 77:869cf507173a 5343
emilmont 77:869cf507173a 5344 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 5345
emilmont 77:869cf507173a 5346 #define TIM_CCMR1_IC1PSC ((uint16_t)0x000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
emilmont 77:869cf507173a 5347 #define TIM_CCMR1_IC1PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
emilmont 77:869cf507173a 5348 #define TIM_CCMR1_IC1PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
emilmont 77:869cf507173a 5349
emilmont 77:869cf507173a 5350 #define TIM_CCMR1_IC1F ((uint16_t)0x00F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
emilmont 77:869cf507173a 5351 #define TIM_CCMR1_IC1F_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5352 #define TIM_CCMR1_IC1F_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5353 #define TIM_CCMR1_IC1F_2 ((uint16_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 5354 #define TIM_CCMR1_IC1F_3 ((uint16_t)0x0080) /*!<Bit 3 */
emilmont 77:869cf507173a 5355
emilmont 77:869cf507173a 5356 #define TIM_CCMR1_IC2PSC ((uint16_t)0x0C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
emilmont 77:869cf507173a 5357 #define TIM_CCMR1_IC2PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
emilmont 77:869cf507173a 5358 #define TIM_CCMR1_IC2PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
emilmont 77:869cf507173a 5359
emilmont 77:869cf507173a 5360 #define TIM_CCMR1_IC2F ((uint16_t)0xF000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
emilmont 77:869cf507173a 5361 #define TIM_CCMR1_IC2F_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5362 #define TIM_CCMR1_IC2F_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5363 #define TIM_CCMR1_IC2F_2 ((uint16_t)0x4000) /*!<Bit 2 */
emilmont 77:869cf507173a 5364 #define TIM_CCMR1_IC2F_3 ((uint16_t)0x8000) /*!<Bit 3 */
emilmont 77:869cf507173a 5365
emilmont 77:869cf507173a 5366 /****************** Bit definition for TIM_CCMR2 register *******************/
emilmont 77:869cf507173a 5367 #define TIM_CCMR2_CC3S ((uint16_t)0x0003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
emilmont 77:869cf507173a 5368 #define TIM_CCMR2_CC3S_0 ((uint16_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 5369 #define TIM_CCMR2_CC3S_1 ((uint16_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 5370
emilmont 77:869cf507173a 5371 #define TIM_CCMR2_OC3FE ((uint16_t)0x0004) /*!<Output Compare 3 Fast enable */
emilmont 77:869cf507173a 5372 #define TIM_CCMR2_OC3PE ((uint16_t)0x0008) /*!<Output Compare 3 Preload enable */
emilmont 77:869cf507173a 5373
emilmont 77:869cf507173a 5374 #define TIM_CCMR2_OC3M ((uint16_t)0x0070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
emilmont 77:869cf507173a 5375 #define TIM_CCMR2_OC3M_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5376 #define TIM_CCMR2_OC3M_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5377 #define TIM_CCMR2_OC3M_2 ((uint16_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 5378
emilmont 77:869cf507173a 5379 #define TIM_CCMR2_OC3CE ((uint16_t)0x0080) /*!<Output Compare 3 Clear Enable */
emilmont 77:869cf507173a 5380
emilmont 77:869cf507173a 5381 #define TIM_CCMR2_CC4S ((uint16_t)0x0300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
emilmont 77:869cf507173a 5382 #define TIM_CCMR2_CC4S_0 ((uint16_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 5383 #define TIM_CCMR2_CC4S_1 ((uint16_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 5384
emilmont 77:869cf507173a 5385 #define TIM_CCMR2_OC4FE ((uint16_t)0x0400) /*!<Output Compare 4 Fast enable */
emilmont 77:869cf507173a 5386 #define TIM_CCMR2_OC4PE ((uint16_t)0x0800) /*!<Output Compare 4 Preload enable */
emilmont 77:869cf507173a 5387
emilmont 77:869cf507173a 5388 #define TIM_CCMR2_OC4M ((uint16_t)0x7000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
emilmont 77:869cf507173a 5389 #define TIM_CCMR2_OC4M_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5390 #define TIM_CCMR2_OC4M_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5391 #define TIM_CCMR2_OC4M_2 ((uint16_t)0x4000) /*!<Bit 2 */
emilmont 77:869cf507173a 5392
emilmont 77:869cf507173a 5393 #define TIM_CCMR2_OC4CE ((uint16_t)0x8000) /*!<Output Compare 4 Clear Enable */
emilmont 77:869cf507173a 5394
emilmont 77:869cf507173a 5395 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 5396
emilmont 77:869cf507173a 5397 #define TIM_CCMR2_IC3PSC ((uint16_t)0x000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
emilmont 77:869cf507173a 5398 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x0004) /*!<Bit 0 */
emilmont 77:869cf507173a 5399 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x0008) /*!<Bit 1 */
emilmont 77:869cf507173a 5400
emilmont 77:869cf507173a 5401 #define TIM_CCMR2_IC3F ((uint16_t)0x00F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
emilmont 77:869cf507173a 5402 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5403 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5404 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x0040) /*!<Bit 2 */
emilmont 77:869cf507173a 5405 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x0080) /*!<Bit 3 */
emilmont 77:869cf507173a 5406
emilmont 77:869cf507173a 5407 #define TIM_CCMR2_IC4PSC ((uint16_t)0x0C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
emilmont 77:869cf507173a 5408 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x0400) /*!<Bit 0 */
emilmont 77:869cf507173a 5409 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x0800) /*!<Bit 1 */
emilmont 77:869cf507173a 5410
emilmont 77:869cf507173a 5411 #define TIM_CCMR2_IC4F ((uint16_t)0xF000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
emilmont 77:869cf507173a 5412 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5413 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5414 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x4000) /*!<Bit 2 */
emilmont 77:869cf507173a 5415 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x8000) /*!<Bit 3 */
emilmont 77:869cf507173a 5416
emilmont 77:869cf507173a 5417 /******************* Bit definition for TIM_CCER register *******************/
emilmont 77:869cf507173a 5418 #define TIM_CCER_CC1E ((uint16_t)0x0001) /*!<Capture/Compare 1 output enable */
emilmont 77:869cf507173a 5419 #define TIM_CCER_CC1P ((uint16_t)0x0002) /*!<Capture/Compare 1 output Polarity */
emilmont 77:869cf507173a 5420 #define TIM_CCER_CC1NP ((uint16_t)0x0008) /*!<Capture/Compare 1 Complementary output Polarity */
emilmont 77:869cf507173a 5421 #define TIM_CCER_CC2E ((uint16_t)0x0010) /*!<Capture/Compare 2 output enable */
emilmont 77:869cf507173a 5422 #define TIM_CCER_CC2P ((uint16_t)0x0020) /*!<Capture/Compare 2 output Polarity */
emilmont 77:869cf507173a 5423 #define TIM_CCER_CC2NP ((uint16_t)0x0080) /*!<Capture/Compare 2 Complementary output Polarity */
emilmont 77:869cf507173a 5424 #define TIM_CCER_CC3E ((uint16_t)0x0100) /*!<Capture/Compare 3 output enable */
emilmont 77:869cf507173a 5425 #define TIM_CCER_CC3P ((uint16_t)0x0200) /*!<Capture/Compare 3 output Polarity */
emilmont 77:869cf507173a 5426 #define TIM_CCER_CC3NP ((uint16_t)0x0800) /*!<Capture/Compare 3 Complementary output Polarity */
emilmont 77:869cf507173a 5427 #define TIM_CCER_CC4E ((uint16_t)0x1000) /*!<Capture/Compare 4 output enable */
emilmont 77:869cf507173a 5428 #define TIM_CCER_CC4P ((uint16_t)0x2000) /*!<Capture/Compare 4 output Polarity */
emilmont 77:869cf507173a 5429 #define TIM_CCER_CC4NP ((uint16_t)0x8000) /*!<Capture/Compare 4 Complementary output Polarity */
emilmont 77:869cf507173a 5430
emilmont 77:869cf507173a 5431 /******************* Bit definition for TIM_CNT register ********************/
emilmont 77:869cf507173a 5432 #define TIM_CNT_CNT ((uint16_t)0xFFFF) /*!<Counter Value */
emilmont 77:869cf507173a 5433
emilmont 77:869cf507173a 5434 /******************* Bit definition for TIM_PSC register ********************/
emilmont 77:869cf507173a 5435 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
emilmont 77:869cf507173a 5436
emilmont 77:869cf507173a 5437 /******************* Bit definition for TIM_ARR register ********************/
emilmont 77:869cf507173a 5438 #define TIM_ARR_ARR ((uint16_t)0xFFFF) /*!<actual auto-reload Value */
emilmont 77:869cf507173a 5439
emilmont 77:869cf507173a 5440 /******************* Bit definition for TIM_CCR1 register *******************/
emilmont 77:869cf507173a 5441 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
emilmont 77:869cf507173a 5442
emilmont 77:869cf507173a 5443 /******************* Bit definition for TIM_CCR2 register *******************/
emilmont 77:869cf507173a 5444 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
emilmont 77:869cf507173a 5445
emilmont 77:869cf507173a 5446 /******************* Bit definition for TIM_CCR3 register *******************/
emilmont 77:869cf507173a 5447 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
emilmont 77:869cf507173a 5448
emilmont 77:869cf507173a 5449 /******************* Bit definition for TIM_CCR4 register *******************/
emilmont 77:869cf507173a 5450 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
emilmont 77:869cf507173a 5451
emilmont 77:869cf507173a 5452 /******************* Bit definition for TIM_DCR register ********************/
emilmont 77:869cf507173a 5453 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
emilmont 77:869cf507173a 5454 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 5455 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 5456 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
emilmont 77:869cf507173a 5457 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
emilmont 77:869cf507173a 5458 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
emilmont 77:869cf507173a 5459
emilmont 77:869cf507173a 5460 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
emilmont 77:869cf507173a 5461 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
emilmont 77:869cf507173a 5462 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
emilmont 77:869cf507173a 5463 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
emilmont 77:869cf507173a 5464 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
emilmont 77:869cf507173a 5465 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
emilmont 77:869cf507173a 5466
emilmont 77:869cf507173a 5467 /******************* Bit definition for TIM_DMAR register *******************/
emilmont 77:869cf507173a 5468 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
emilmont 77:869cf507173a 5469
emilmont 77:869cf507173a 5470 /******************* Bit definition for TIM_OR register *********************/
emilmont 77:869cf507173a 5471 #define TIM_OR_TI1RMP ((uint16_t)0x0003) /*!<Option register for TI1 Remapping */
emilmont 77:869cf507173a 5472 #define TIM_OR_TI1RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
emilmont 77:869cf507173a 5473 #define TIM_OR_TI1RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
emilmont 77:869cf507173a 5474
emilmont 77:869cf507173a 5475 /******************************************************************************/
emilmont 77:869cf507173a 5476 /* */
emilmont 77:869cf507173a 5477 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
emilmont 77:869cf507173a 5478 /* */
emilmont 77:869cf507173a 5479 /******************************************************************************/
emilmont 77:869cf507173a 5480
emilmont 77:869cf507173a 5481 /******************* Bit definition for USART_SR register *******************/
emilmont 77:869cf507173a 5482 #define USART_SR_PE ((uint16_t)0x0001) /*!< Parity Error */
emilmont 77:869cf507173a 5483 #define USART_SR_FE ((uint16_t)0x0002) /*!< Framing Error */
emilmont 77:869cf507173a 5484 #define USART_SR_NE ((uint16_t)0x0004) /*!< Noise Error Flag */
emilmont 77:869cf507173a 5485 #define USART_SR_ORE ((uint16_t)0x0008) /*!< OverRun Error */
emilmont 77:869cf507173a 5486 #define USART_SR_IDLE ((uint16_t)0x0010) /*!< IDLE line detected */
emilmont 77:869cf507173a 5487 #define USART_SR_RXNE ((uint16_t)0x0020) /*!< Read Data Register Not Empty */
emilmont 77:869cf507173a 5488 #define USART_SR_TC ((uint16_t)0x0040) /*!< Transmission Complete */
emilmont 77:869cf507173a 5489 #define USART_SR_TXE ((uint16_t)0x0080) /*!< Transmit Data Register Empty */
emilmont 77:869cf507173a 5490 #define USART_SR_LBD ((uint16_t)0x0100) /*!< LIN Break Detection Flag */
emilmont 77:869cf507173a 5491 #define USART_SR_CTS ((uint16_t)0x0200) /*!< CTS Flag */
emilmont 77:869cf507173a 5492
emilmont 77:869cf507173a 5493 /******************* Bit definition for USART_DR register *******************/
emilmont 77:869cf507173a 5494 #define USART_DR_DR ((uint16_t)0x01FF) /*!< Data value */
emilmont 77:869cf507173a 5495
emilmont 77:869cf507173a 5496 /****************** Bit definition for USART_BRR register *******************/
emilmont 77:869cf507173a 5497 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
emilmont 77:869cf507173a 5498 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
emilmont 77:869cf507173a 5499
emilmont 77:869cf507173a 5500 /****************** Bit definition for USART_CR1 register *******************/
emilmont 77:869cf507173a 5501 #define USART_CR1_SBK ((uint16_t)0x0001) /*!< Send Break */
emilmont 77:869cf507173a 5502 #define USART_CR1_RWU ((uint16_t)0x0002) /*!< Receiver wakeup */
emilmont 77:869cf507173a 5503 #define USART_CR1_RE ((uint16_t)0x0004) /*!< Receiver Enable */
emilmont 77:869cf507173a 5504 #define USART_CR1_TE ((uint16_t)0x0008) /*!< Transmitter Enable */
emilmont 77:869cf507173a 5505 #define USART_CR1_IDLEIE ((uint16_t)0x0010) /*!< IDLE Interrupt Enable */
emilmont 77:869cf507173a 5506 #define USART_CR1_RXNEIE ((uint16_t)0x0020) /*!< RXNE Interrupt Enable */
emilmont 77:869cf507173a 5507 #define USART_CR1_TCIE ((uint16_t)0x0040) /*!< Transmission Complete Interrupt Enable */
emilmont 77:869cf507173a 5508 #define USART_CR1_TXEIE ((uint16_t)0x0080) /*!< PE Interrupt Enable */
emilmont 77:869cf507173a 5509 #define USART_CR1_PEIE ((uint16_t)0x0100) /*!< PE Interrupt Enable */
emilmont 77:869cf507173a 5510 #define USART_CR1_PS ((uint16_t)0x0200) /*!< Parity Selection */
emilmont 77:869cf507173a 5511 #define USART_CR1_PCE ((uint16_t)0x0400) /*!< Parity Control Enable */
emilmont 77:869cf507173a 5512 #define USART_CR1_WAKE ((uint16_t)0x0800) /*!< Wakeup method */
emilmont 77:869cf507173a 5513 #define USART_CR1_M ((uint16_t)0x1000) /*!< Word length */
emilmont 77:869cf507173a 5514 #define USART_CR1_UE ((uint16_t)0x2000) /*!< USART Enable */
emilmont 77:869cf507173a 5515 #define USART_CR1_OVER8 ((uint16_t)0x8000) /*!< Oversampling by 8-bit mode */
emilmont 77:869cf507173a 5516
emilmont 77:869cf507173a 5517 /****************** Bit definition for USART_CR2 register *******************/
emilmont 77:869cf507173a 5518 #define USART_CR2_ADD ((uint16_t)0x000F) /*!< Address of the USART node */
emilmont 77:869cf507173a 5519 #define USART_CR2_LBDL ((uint16_t)0x0020) /*!< LIN Break Detection Length */
emilmont 77:869cf507173a 5520 #define USART_CR2_LBDIE ((uint16_t)0x0040) /*!< LIN Break Detection Interrupt Enable */
emilmont 77:869cf507173a 5521 #define USART_CR2_LBCL ((uint16_t)0x0100) /*!< Last Bit Clock pulse */
emilmont 77:869cf507173a 5522 #define USART_CR2_CPHA ((uint16_t)0x0200) /*!< Clock Phase */
emilmont 77:869cf507173a 5523 #define USART_CR2_CPOL ((uint16_t)0x0400) /*!< Clock Polarity */
emilmont 77:869cf507173a 5524 #define USART_CR2_CLKEN ((uint16_t)0x0800) /*!< Clock Enable */
emilmont 77:869cf507173a 5525
emilmont 77:869cf507173a 5526 #define USART_CR2_STOP ((uint16_t)0x3000) /*!< STOP[1:0] bits (STOP bits) */
emilmont 77:869cf507173a 5527 #define USART_CR2_STOP_0 ((uint16_t)0x1000) /*!< Bit 0 */
emilmont 77:869cf507173a 5528 #define USART_CR2_STOP_1 ((uint16_t)0x2000) /*!< Bit 1 */
emilmont 77:869cf507173a 5529
emilmont 77:869cf507173a 5530 #define USART_CR2_LINEN ((uint16_t)0x4000) /*!< LIN mode enable */
emilmont 77:869cf507173a 5531
emilmont 77:869cf507173a 5532 /****************** Bit definition for USART_CR3 register *******************/
emilmont 77:869cf507173a 5533 #define USART_CR3_EIE ((uint16_t)0x0001) /*!< Error Interrupt Enable */
emilmont 77:869cf507173a 5534 #define USART_CR3_IREN ((uint16_t)0x0002) /*!< IrDA mode Enable */
emilmont 77:869cf507173a 5535 #define USART_CR3_IRLP ((uint16_t)0x0004) /*!< IrDA Low-Power */
emilmont 77:869cf507173a 5536 #define USART_CR3_HDSEL ((uint16_t)0x0008) /*!< Half-Duplex Selection */
emilmont 77:869cf507173a 5537 #define USART_CR3_NACK ((uint16_t)0x0010) /*!< Smartcard NACK enable */
emilmont 77:869cf507173a 5538 #define USART_CR3_SCEN ((uint16_t)0x0020) /*!< Smartcard mode enable */
emilmont 77:869cf507173a 5539 #define USART_CR3_DMAR ((uint16_t)0x0040) /*!< DMA Enable Receiver */
emilmont 77:869cf507173a 5540 #define USART_CR3_DMAT ((uint16_t)0x0080) /*!< DMA Enable Transmitter */
emilmont 77:869cf507173a 5541 #define USART_CR3_RTSE ((uint16_t)0x0100) /*!< RTS Enable */
emilmont 77:869cf507173a 5542 #define USART_CR3_CTSE ((uint16_t)0x0200) /*!< CTS Enable */
emilmont 77:869cf507173a 5543 #define USART_CR3_CTSIE ((uint16_t)0x0400) /*!< CTS Interrupt Enable */
emilmont 77:869cf507173a 5544 #define USART_CR3_ONEBIT ((uint16_t)0x0800) /*!< One sample bit method enable */
emilmont 77:869cf507173a 5545
emilmont 77:869cf507173a 5546 /****************** Bit definition for USART_GTPR register ******************/
emilmont 77:869cf507173a 5547 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
emilmont 77:869cf507173a 5548 #define USART_GTPR_PSC_0 ((uint16_t)0x0001) /*!< Bit 0 */
emilmont 77:869cf507173a 5549 #define USART_GTPR_PSC_1 ((uint16_t)0x0002) /*!< Bit 1 */
emilmont 77:869cf507173a 5550 #define USART_GTPR_PSC_2 ((uint16_t)0x0004) /*!< Bit 2 */
emilmont 77:869cf507173a 5551 #define USART_GTPR_PSC_3 ((uint16_t)0x0008) /*!< Bit 3 */
emilmont 77:869cf507173a 5552 #define USART_GTPR_PSC_4 ((uint16_t)0x0010) /*!< Bit 4 */
emilmont 77:869cf507173a 5553 #define USART_GTPR_PSC_5 ((uint16_t)0x0020) /*!< Bit 5 */
emilmont 77:869cf507173a 5554 #define USART_GTPR_PSC_6 ((uint16_t)0x0040) /*!< Bit 6 */
emilmont 77:869cf507173a 5555 #define USART_GTPR_PSC_7 ((uint16_t)0x0080) /*!< Bit 7 */
emilmont 77:869cf507173a 5556
emilmont 77:869cf507173a 5557 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< Guard time value */
emilmont 77:869cf507173a 5558
emilmont 77:869cf507173a 5559 /******************************************************************************/
emilmont 77:869cf507173a 5560 /* */
emilmont 77:869cf507173a 5561 /* Universal Serial Bus (USB) */
emilmont 77:869cf507173a 5562 /* */
emilmont 77:869cf507173a 5563 /******************************************************************************/
emilmont 77:869cf507173a 5564
emilmont 77:869cf507173a 5565 /*!<Endpoint-specific registers */
emilmont 77:869cf507173a 5566 /******************* Bit definition for USB_EP0R register *******************/
emilmont 77:869cf507173a 5567 #define USB_EP0R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
emilmont 77:869cf507173a 5568
emilmont 77:869cf507173a 5569 #define USB_EP0R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
emilmont 77:869cf507173a 5570 #define USB_EP0R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5571 #define USB_EP0R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5572
emilmont 77:869cf507173a 5573 #define USB_EP0R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
emilmont 77:869cf507173a 5574 #define USB_EP0R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
emilmont 77:869cf507173a 5575 #define USB_EP0R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
emilmont 77:869cf507173a 5576
emilmont 77:869cf507173a 5577 #define USB_EP0R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
emilmont 77:869cf507173a 5578 #define USB_EP0R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
emilmont 77:869cf507173a 5579 #define USB_EP0R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
emilmont 77:869cf507173a 5580
emilmont 77:869cf507173a 5581 #define USB_EP0R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
emilmont 77:869cf507173a 5582
emilmont 77:869cf507173a 5583 #define USB_EP0R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
emilmont 77:869cf507173a 5584 #define USB_EP0R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5585 #define USB_EP0R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5586
emilmont 77:869cf507173a 5587 #define USB_EP0R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
emilmont 77:869cf507173a 5588 #define USB_EP0R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
emilmont 77:869cf507173a 5589
emilmont 77:869cf507173a 5590 /******************* Bit definition for USB_EP1R register *******************/
emilmont 77:869cf507173a 5591 #define USB_EP1R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
emilmont 77:869cf507173a 5592
emilmont 77:869cf507173a 5593 #define USB_EP1R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
emilmont 77:869cf507173a 5594 #define USB_EP1R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5595 #define USB_EP1R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5596
emilmont 77:869cf507173a 5597 #define USB_EP1R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
emilmont 77:869cf507173a 5598 #define USB_EP1R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
emilmont 77:869cf507173a 5599 #define USB_EP1R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
emilmont 77:869cf507173a 5600
emilmont 77:869cf507173a 5601 #define USB_EP1R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
emilmont 77:869cf507173a 5602 #define USB_EP1R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
emilmont 77:869cf507173a 5603 #define USB_EP1R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
emilmont 77:869cf507173a 5604
emilmont 77:869cf507173a 5605 #define USB_EP1R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
emilmont 77:869cf507173a 5606
emilmont 77:869cf507173a 5607 #define USB_EP1R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
emilmont 77:869cf507173a 5608 #define USB_EP1R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5609 #define USB_EP1R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5610
emilmont 77:869cf507173a 5611 #define USB_EP1R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
emilmont 77:869cf507173a 5612 #define USB_EP1R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
emilmont 77:869cf507173a 5613
emilmont 77:869cf507173a 5614 /******************* Bit definition for USB_EP2R register *******************/
emilmont 77:869cf507173a 5615 #define USB_EP2R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
emilmont 77:869cf507173a 5616
emilmont 77:869cf507173a 5617 #define USB_EP2R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
emilmont 77:869cf507173a 5618 #define USB_EP2R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5619 #define USB_EP2R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5620
emilmont 77:869cf507173a 5621 #define USB_EP2R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
emilmont 77:869cf507173a 5622 #define USB_EP2R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
emilmont 77:869cf507173a 5623 #define USB_EP2R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
emilmont 77:869cf507173a 5624
emilmont 77:869cf507173a 5625 #define USB_EP2R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
emilmont 77:869cf507173a 5626 #define USB_EP2R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
emilmont 77:869cf507173a 5627 #define USB_EP2R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
emilmont 77:869cf507173a 5628
emilmont 77:869cf507173a 5629 #define USB_EP2R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
emilmont 77:869cf507173a 5630
emilmont 77:869cf507173a 5631 #define USB_EP2R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
emilmont 77:869cf507173a 5632 #define USB_EP2R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5633 #define USB_EP2R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5634
emilmont 77:869cf507173a 5635 #define USB_EP2R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
emilmont 77:869cf507173a 5636 #define USB_EP2R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
emilmont 77:869cf507173a 5637
emilmont 77:869cf507173a 5638 /******************* Bit definition for USB_EP3R register *******************/
emilmont 77:869cf507173a 5639 #define USB_EP3R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
emilmont 77:869cf507173a 5640
emilmont 77:869cf507173a 5641 #define USB_EP3R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
emilmont 77:869cf507173a 5642 #define USB_EP3R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5643 #define USB_EP3R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5644
emilmont 77:869cf507173a 5645 #define USB_EP3R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
emilmont 77:869cf507173a 5646 #define USB_EP3R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
emilmont 77:869cf507173a 5647 #define USB_EP3R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
emilmont 77:869cf507173a 5648
emilmont 77:869cf507173a 5649 #define USB_EP3R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
emilmont 77:869cf507173a 5650 #define USB_EP3R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
emilmont 77:869cf507173a 5651 #define USB_EP3R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
emilmont 77:869cf507173a 5652
emilmont 77:869cf507173a 5653 #define USB_EP3R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
emilmont 77:869cf507173a 5654
emilmont 77:869cf507173a 5655 #define USB_EP3R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
emilmont 77:869cf507173a 5656 #define USB_EP3R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5657 #define USB_EP3R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5658
emilmont 77:869cf507173a 5659 #define USB_EP3R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
emilmont 77:869cf507173a 5660 #define USB_EP3R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
emilmont 77:869cf507173a 5661
emilmont 77:869cf507173a 5662 /******************* Bit definition for USB_EP4R register *******************/
emilmont 77:869cf507173a 5663 #define USB_EP4R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
emilmont 77:869cf507173a 5664
emilmont 77:869cf507173a 5665 #define USB_EP4R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
emilmont 77:869cf507173a 5666 #define USB_EP4R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5667 #define USB_EP4R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5668
emilmont 77:869cf507173a 5669 #define USB_EP4R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
emilmont 77:869cf507173a 5670 #define USB_EP4R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
emilmont 77:869cf507173a 5671 #define USB_EP4R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
emilmont 77:869cf507173a 5672
emilmont 77:869cf507173a 5673 #define USB_EP4R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
emilmont 77:869cf507173a 5674 #define USB_EP4R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
emilmont 77:869cf507173a 5675 #define USB_EP4R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
emilmont 77:869cf507173a 5676
emilmont 77:869cf507173a 5677 #define USB_EP4R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
emilmont 77:869cf507173a 5678
emilmont 77:869cf507173a 5679 #define USB_EP4R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
emilmont 77:869cf507173a 5680 #define USB_EP4R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5681 #define USB_EP4R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5682
emilmont 77:869cf507173a 5683 #define USB_EP4R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
emilmont 77:869cf507173a 5684 #define USB_EP4R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
emilmont 77:869cf507173a 5685
emilmont 77:869cf507173a 5686 /******************* Bit definition for USB_EP5R register *******************/
emilmont 77:869cf507173a 5687 #define USB_EP5R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
emilmont 77:869cf507173a 5688
emilmont 77:869cf507173a 5689 #define USB_EP5R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
emilmont 77:869cf507173a 5690 #define USB_EP5R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5691 #define USB_EP5R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5692
emilmont 77:869cf507173a 5693 #define USB_EP5R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
emilmont 77:869cf507173a 5694 #define USB_EP5R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
emilmont 77:869cf507173a 5695 #define USB_EP5R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
emilmont 77:869cf507173a 5696
emilmont 77:869cf507173a 5697 #define USB_EP5R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
emilmont 77:869cf507173a 5698 #define USB_EP5R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
emilmont 77:869cf507173a 5699 #define USB_EP5R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
emilmont 77:869cf507173a 5700
emilmont 77:869cf507173a 5701 #define USB_EP5R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
emilmont 77:869cf507173a 5702
emilmont 77:869cf507173a 5703 #define USB_EP5R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
emilmont 77:869cf507173a 5704 #define USB_EP5R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5705 #define USB_EP5R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5706
emilmont 77:869cf507173a 5707 #define USB_EP5R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
emilmont 77:869cf507173a 5708 #define USB_EP5R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
emilmont 77:869cf507173a 5709
emilmont 77:869cf507173a 5710 /******************* Bit definition for USB_EP6R register *******************/
emilmont 77:869cf507173a 5711 #define USB_EP6R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
emilmont 77:869cf507173a 5712
emilmont 77:869cf507173a 5713 #define USB_EP6R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
emilmont 77:869cf507173a 5714 #define USB_EP6R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5715 #define USB_EP6R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5716
emilmont 77:869cf507173a 5717 #define USB_EP6R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
emilmont 77:869cf507173a 5718 #define USB_EP6R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
emilmont 77:869cf507173a 5719 #define USB_EP6R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
emilmont 77:869cf507173a 5720
emilmont 77:869cf507173a 5721 #define USB_EP6R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
emilmont 77:869cf507173a 5722 #define USB_EP6R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
emilmont 77:869cf507173a 5723 #define USB_EP6R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
emilmont 77:869cf507173a 5724
emilmont 77:869cf507173a 5725 #define USB_EP6R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
emilmont 77:869cf507173a 5726
emilmont 77:869cf507173a 5727 #define USB_EP6R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
emilmont 77:869cf507173a 5728 #define USB_EP6R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5729 #define USB_EP6R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5730
emilmont 77:869cf507173a 5731 #define USB_EP6R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
emilmont 77:869cf507173a 5732 #define USB_EP6R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
emilmont 77:869cf507173a 5733
emilmont 77:869cf507173a 5734 /******************* Bit definition for USB_EP7R register *******************/
emilmont 77:869cf507173a 5735 #define USB_EP7R_EA ((uint16_t)0x000F) /*!<Endpoint Address */
emilmont 77:869cf507173a 5736
emilmont 77:869cf507173a 5737 #define USB_EP7R_STAT_TX ((uint16_t)0x0030) /*!<STAT_TX[1:0] bits (Status bits, for transmission transfers) */
emilmont 77:869cf507173a 5738 #define USB_EP7R_STAT_TX_0 ((uint16_t)0x0010) /*!<Bit 0 */
emilmont 77:869cf507173a 5739 #define USB_EP7R_STAT_TX_1 ((uint16_t)0x0020) /*!<Bit 1 */
emilmont 77:869cf507173a 5740
emilmont 77:869cf507173a 5741 #define USB_EP7R_DTOG_TX ((uint16_t)0x0040) /*!<Data Toggle, for transmission transfers */
emilmont 77:869cf507173a 5742 #define USB_EP7R_CTR_TX ((uint16_t)0x0080) /*!<Correct Transfer for transmission */
emilmont 77:869cf507173a 5743 #define USB_EP7R_EP_KIND ((uint16_t)0x0100) /*!<Endpoint Kind */
emilmont 77:869cf507173a 5744
emilmont 77:869cf507173a 5745 #define USB_EP7R_EP_TYPE ((uint16_t)0x0600) /*!<EP_TYPE[1:0] bits (Endpoint type) */
emilmont 77:869cf507173a 5746 #define USB_EP7R_EP_TYPE_0 ((uint16_t)0x0200) /*!<Bit 0 */
emilmont 77:869cf507173a 5747 #define USB_EP7R_EP_TYPE_1 ((uint16_t)0x0400) /*!<Bit 1 */
emilmont 77:869cf507173a 5748
emilmont 77:869cf507173a 5749 #define USB_EP7R_SETUP ((uint16_t)0x0800) /*!<Setup transaction completed */
emilmont 77:869cf507173a 5750
emilmont 77:869cf507173a 5751 #define USB_EP7R_STAT_RX ((uint16_t)0x3000) /*!<STAT_RX[1:0] bits (Status bits, for reception transfers) */
emilmont 77:869cf507173a 5752 #define USB_EP7R_STAT_RX_0 ((uint16_t)0x1000) /*!<Bit 0 */
emilmont 77:869cf507173a 5753 #define USB_EP7R_STAT_RX_1 ((uint16_t)0x2000) /*!<Bit 1 */
emilmont 77:869cf507173a 5754
emilmont 77:869cf507173a 5755 #define USB_EP7R_DTOG_RX ((uint16_t)0x4000) /*!<Data Toggle, for reception transfers */
emilmont 77:869cf507173a 5756 #define USB_EP7R_CTR_RX ((uint16_t)0x8000) /*!<Correct Transfer for reception */
emilmont 77:869cf507173a 5757
emilmont 77:869cf507173a 5758 /*!<Common registers */
emilmont 77:869cf507173a 5759 /******************* Bit definition for USB_CNTR register *******************/
emilmont 77:869cf507173a 5760 #define USB_CNTR_FRES ((uint16_t)0x0001) /*!<Force USB Reset */
emilmont 77:869cf507173a 5761 #define USB_CNTR_PDWN ((uint16_t)0x0002) /*!<Power down */
emilmont 77:869cf507173a 5762 #define USB_CNTR_LP_MODE ((uint16_t)0x0004) /*!<Low-power mode */
emilmont 77:869cf507173a 5763 #define USB_CNTR_FSUSP ((uint16_t)0x0008) /*!<Force suspend */
emilmont 77:869cf507173a 5764 #define USB_CNTR_RESUME ((uint16_t)0x0010) /*!<Resume request */
emilmont 77:869cf507173a 5765 #define USB_CNTR_ESOFM ((uint16_t)0x0100) /*!<Expected Start Of Frame Interrupt Mask */
emilmont 77:869cf507173a 5766 #define USB_CNTR_SOFM ((uint16_t)0x0200) /*!<Start Of Frame Interrupt Mask */
emilmont 77:869cf507173a 5767 #define USB_CNTR_RESETM ((uint16_t)0x0400) /*!<RESET Interrupt Mask */
emilmont 77:869cf507173a 5768 #define USB_CNTR_SUSPM ((uint16_t)0x0800) /*!<Suspend mode Interrupt Mask */
emilmont 77:869cf507173a 5769 #define USB_CNTR_WKUPM ((uint16_t)0x1000) /*!<Wakeup Interrupt Mask */
emilmont 77:869cf507173a 5770 #define USB_CNTR_ERRM ((uint16_t)0x2000) /*!<Error Interrupt Mask */
emilmont 77:869cf507173a 5771 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun Interrupt Mask */
emilmont 77:869cf507173a 5772 #define USB_CNTR_CTRM ((uint16_t)0x8000) /*!<Correct Transfer Interrupt Mask */
emilmont 77:869cf507173a 5773
emilmont 77:869cf507173a 5774 /******************* Bit definition for USB_ISTR register *******************/
emilmont 77:869cf507173a 5775 #define USB_ISTR_EP_ID ((uint16_t)0x000F) /*!<Endpoint Identifier */
emilmont 77:869cf507173a 5776 #define USB_ISTR_DIR ((uint16_t)0x0010) /*!<Direction of transaction */
emilmont 77:869cf507173a 5777 #define USB_ISTR_ESOF ((uint16_t)0x0100) /*!<Expected Start Of Frame */
emilmont 77:869cf507173a 5778 #define USB_ISTR_SOF ((uint16_t)0x0200) /*!<Start Of Frame */
emilmont 77:869cf507173a 5779 #define USB_ISTR_RESET ((uint16_t)0x0400) /*!<USB RESET request */
emilmont 77:869cf507173a 5780 #define USB_ISTR_SUSP ((uint16_t)0x0800) /*!<Suspend mode request */
emilmont 77:869cf507173a 5781 #define USB_ISTR_WKUP ((uint16_t)0x1000) /*!<Wake up */
emilmont 77:869cf507173a 5782 #define USB_ISTR_ERR ((uint16_t)0x2000) /*!<Error */
emilmont 77:869cf507173a 5783 #define USB_ISTR_PMAOVR ((uint16_t)0x4000) /*!<Packet Memory Area Over / Underrun */
emilmont 77:869cf507173a 5784 #define USB_ISTR_CTR ((uint16_t)0x8000) /*!<Correct Transfer */
emilmont 77:869cf507173a 5785
emilmont 77:869cf507173a 5786 /******************* Bit definition for USB_FNR register ********************/
emilmont 77:869cf507173a 5787 #define USB_FNR_FN ((uint16_t)0x07FF) /*!<Frame Number */
emilmont 77:869cf507173a 5788 #define USB_FNR_LSOF ((uint16_t)0x1800) /*!<Lost SOF */
emilmont 77:869cf507173a 5789 #define USB_FNR_LCK ((uint16_t)0x2000) /*!<Locked */
emilmont 77:869cf507173a 5790 #define USB_FNR_RXDM ((uint16_t)0x4000) /*!<Receive Data - Line Status */
emilmont 77:869cf507173a 5791 #define USB_FNR_RXDP ((uint16_t)0x8000) /*!<Receive Data + Line Status */
emilmont 77:869cf507173a 5792
emilmont 77:869cf507173a 5793 /****************** Bit definition for USB_DADDR register *******************/
emilmont 77:869cf507173a 5794 #define USB_DADDR_ADD ((uint8_t)0x7F) /*!<ADD[6:0] bits (Device Address) */
emilmont 77:869cf507173a 5795 #define USB_DADDR_ADD0 ((uint8_t)0x01) /*!<Bit 0 */
emilmont 77:869cf507173a 5796 #define USB_DADDR_ADD1 ((uint8_t)0x02) /*!<Bit 1 */
emilmont 77:869cf507173a 5797 #define USB_DADDR_ADD2 ((uint8_t)0x04) /*!<Bit 2 */
emilmont 77:869cf507173a 5798 #define USB_DADDR_ADD3 ((uint8_t)0x08) /*!<Bit 3 */
emilmont 77:869cf507173a 5799 #define USB_DADDR_ADD4 ((uint8_t)0x10) /*!<Bit 4 */
emilmont 77:869cf507173a 5800 #define USB_DADDR_ADD5 ((uint8_t)0x20) /*!<Bit 5 */
emilmont 77:869cf507173a 5801 #define USB_DADDR_ADD6 ((uint8_t)0x40) /*!<Bit 6 */
emilmont 77:869cf507173a 5802
emilmont 77:869cf507173a 5803 #define USB_DADDR_EF ((uint8_t)0x80) /*!<Enable Function */
emilmont 77:869cf507173a 5804
emilmont 77:869cf507173a 5805 /****************** Bit definition for USB_BTABLE register ******************/
emilmont 77:869cf507173a 5806 #define USB_BTABLE_BTABLE ((uint16_t)0xFFF8) /*!<Buffer Table */
emilmont 77:869cf507173a 5807
emilmont 77:869cf507173a 5808 /*!< Buffer descriptor table */
emilmont 77:869cf507173a 5809 /***************** Bit definition for USB_ADDR0_TX register *****************/
emilmont 77:869cf507173a 5810 #define USB_ADDR0_TX_ADDR0_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 0 */
emilmont 77:869cf507173a 5811
emilmont 77:869cf507173a 5812 /***************** Bit definition for USB_ADDR1_TX register *****************/
emilmont 77:869cf507173a 5813 #define USB_ADDR1_TX_ADDR1_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 1 */
emilmont 77:869cf507173a 5814
emilmont 77:869cf507173a 5815 /***************** Bit definition for USB_ADDR2_TX register *****************/
emilmont 77:869cf507173a 5816 #define USB_ADDR2_TX_ADDR2_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 2 */
emilmont 77:869cf507173a 5817
emilmont 77:869cf507173a 5818 /***************** Bit definition for USB_ADDR3_TX register *****************/
emilmont 77:869cf507173a 5819 #define USB_ADDR3_TX_ADDR3_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 3 */
emilmont 77:869cf507173a 5820
emilmont 77:869cf507173a 5821 /***************** Bit definition for USB_ADDR4_TX register *****************/
emilmont 77:869cf507173a 5822 #define USB_ADDR4_TX_ADDR4_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 4 */
emilmont 77:869cf507173a 5823
emilmont 77:869cf507173a 5824 /***************** Bit definition for USB_ADDR5_TX register *****************/
emilmont 77:869cf507173a 5825 #define USB_ADDR5_TX_ADDR5_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 5 */
emilmont 77:869cf507173a 5826
emilmont 77:869cf507173a 5827 /***************** Bit definition for USB_ADDR6_TX register *****************/
emilmont 77:869cf507173a 5828 #define USB_ADDR6_TX_ADDR6_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 6 */
emilmont 77:869cf507173a 5829
emilmont 77:869cf507173a 5830 /***************** Bit definition for USB_ADDR7_TX register *****************/
emilmont 77:869cf507173a 5831 #define USB_ADDR7_TX_ADDR7_TX ((uint16_t)0xFFFE) /*!< Transmission Buffer Address 7 */
emilmont 77:869cf507173a 5832
emilmont 77:869cf507173a 5833 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 5834
emilmont 77:869cf507173a 5835 /***************** Bit definition for USB_COUNT0_TX register ****************/
emilmont 77:869cf507173a 5836 #define USB_COUNT0_TX_COUNT0_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 0 */
emilmont 77:869cf507173a 5837
emilmont 77:869cf507173a 5838 /***************** Bit definition for USB_COUNT1_TX register ****************/
emilmont 77:869cf507173a 5839 #define USB_COUNT1_TX_COUNT1_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 1 */
emilmont 77:869cf507173a 5840
emilmont 77:869cf507173a 5841 /***************** Bit definition for USB_COUNT2_TX register ****************/
emilmont 77:869cf507173a 5842 #define USB_COUNT2_TX_COUNT2_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 2 */
emilmont 77:869cf507173a 5843
emilmont 77:869cf507173a 5844 /***************** Bit definition for USB_COUNT3_TX register ****************/
emilmont 77:869cf507173a 5845 #define USB_COUNT3_TX_COUNT3_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 3 */
emilmont 77:869cf507173a 5846
emilmont 77:869cf507173a 5847 /***************** Bit definition for USB_COUNT4_TX register ****************/
emilmont 77:869cf507173a 5848 #define USB_COUNT4_TX_COUNT4_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 4 */
emilmont 77:869cf507173a 5849
emilmont 77:869cf507173a 5850 /***************** Bit definition for USB_COUNT5_TX register ****************/
emilmont 77:869cf507173a 5851 #define USB_COUNT5_TX_COUNT5_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 5 */
emilmont 77:869cf507173a 5852
emilmont 77:869cf507173a 5853 /***************** Bit definition for USB_COUNT6_TX register ****************/
emilmont 77:869cf507173a 5854 #define USB_COUNT6_TX_COUNT6_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 6 */
emilmont 77:869cf507173a 5855
emilmont 77:869cf507173a 5856 /***************** Bit definition for USB_COUNT7_TX register ****************/
emilmont 77:869cf507173a 5857 #define USB_COUNT7_TX_COUNT7_TX ((uint16_t)0x03FF) /*!< Transmission Byte Count 7 */
emilmont 77:869cf507173a 5858
emilmont 77:869cf507173a 5859 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 5860
emilmont 77:869cf507173a 5861 /**************** Bit definition for USB_COUNT0_TX_0 register ***************/
emilmont 77:869cf507173a 5862 #define USB_COUNT0_TX_0_COUNT0_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 0 (low) */
emilmont 77:869cf507173a 5863
emilmont 77:869cf507173a 5864 /**************** Bit definition for USB_COUNT0_TX_1 register ***************/
emilmont 77:869cf507173a 5865 #define USB_COUNT0_TX_1_COUNT0_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 0 (high) */
emilmont 77:869cf507173a 5866
emilmont 77:869cf507173a 5867 /**************** Bit definition for USB_COUNT1_TX_0 register ***************/
emilmont 77:869cf507173a 5868 #define USB_COUNT1_TX_0_COUNT1_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 1 (low) */
emilmont 77:869cf507173a 5869
emilmont 77:869cf507173a 5870 /**************** Bit definition for USB_COUNT1_TX_1 register ***************/
emilmont 77:869cf507173a 5871 #define USB_COUNT1_TX_1_COUNT1_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 1 (high) */
emilmont 77:869cf507173a 5872
emilmont 77:869cf507173a 5873 /**************** Bit definition for USB_COUNT2_TX_0 register ***************/
emilmont 77:869cf507173a 5874 #define USB_COUNT2_TX_0_COUNT2_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 2 (low) */
emilmont 77:869cf507173a 5875
emilmont 77:869cf507173a 5876 /**************** Bit definition for USB_COUNT2_TX_1 register ***************/
emilmont 77:869cf507173a 5877 #define USB_COUNT2_TX_1_COUNT2_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 2 (high) */
emilmont 77:869cf507173a 5878
emilmont 77:869cf507173a 5879 /**************** Bit definition for USB_COUNT3_TX_0 register ***************/
emilmont 77:869cf507173a 5880 #define USB_COUNT3_TX_0_COUNT3_TX_0 ((uint16_t)0x000003FF) /*!< Transmission Byte Count 3 (low) */
emilmont 77:869cf507173a 5881
emilmont 77:869cf507173a 5882 /**************** Bit definition for USB_COUNT3_TX_1 register ***************/
emilmont 77:869cf507173a 5883 #define USB_COUNT3_TX_1_COUNT3_TX_1 ((uint16_t)0x03FF0000) /*!< Transmission Byte Count 3 (high) */
emilmont 77:869cf507173a 5884
emilmont 77:869cf507173a 5885 /**************** Bit definition for USB_COUNT4_TX_0 register ***************/
emilmont 77:869cf507173a 5886 #define USB_COUNT4_TX_0_COUNT4_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 4 (low) */
emilmont 77:869cf507173a 5887
emilmont 77:869cf507173a 5888 /**************** Bit definition for USB_COUNT4_TX_1 register ***************/
emilmont 77:869cf507173a 5889 #define USB_COUNT4_TX_1_COUNT4_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 4 (high) */
emilmont 77:869cf507173a 5890
emilmont 77:869cf507173a 5891 /**************** Bit definition for USB_COUNT5_TX_0 register ***************/
emilmont 77:869cf507173a 5892 #define USB_COUNT5_TX_0_COUNT5_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 5 (low) */
emilmont 77:869cf507173a 5893
emilmont 77:869cf507173a 5894 /**************** Bit definition for USB_COUNT5_TX_1 register ***************/
emilmont 77:869cf507173a 5895 #define USB_COUNT5_TX_1_COUNT5_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 5 (high) */
emilmont 77:869cf507173a 5896
emilmont 77:869cf507173a 5897 /**************** Bit definition for USB_COUNT6_TX_0 register ***************/
emilmont 77:869cf507173a 5898 #define USB_COUNT6_TX_0_COUNT6_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 6 (low) */
emilmont 77:869cf507173a 5899
emilmont 77:869cf507173a 5900 /**************** Bit definition for USB_COUNT6_TX_1 register ***************/
emilmont 77:869cf507173a 5901 #define USB_COUNT6_TX_1_COUNT6_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 6 (high) */
emilmont 77:869cf507173a 5902
emilmont 77:869cf507173a 5903 /**************** Bit definition for USB_COUNT7_TX_0 register ***************/
emilmont 77:869cf507173a 5904 #define USB_COUNT7_TX_0_COUNT7_TX_0 ((uint32_t)0x000003FF) /*!< Transmission Byte Count 7 (low) */
emilmont 77:869cf507173a 5905
emilmont 77:869cf507173a 5906 /**************** Bit definition for USB_COUNT7_TX_1 register ***************/
emilmont 77:869cf507173a 5907 #define USB_COUNT7_TX_1_COUNT7_TX_1 ((uint32_t)0x03FF0000) /*!< Transmission Byte Count 7 (high) */
emilmont 77:869cf507173a 5908
emilmont 77:869cf507173a 5909 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 5910
emilmont 77:869cf507173a 5911 /***************** Bit definition for USB_ADDR0_RX register *****************/
emilmont 77:869cf507173a 5912 #define USB_ADDR0_RX_ADDR0_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 0 */
emilmont 77:869cf507173a 5913
emilmont 77:869cf507173a 5914 /***************** Bit definition for USB_ADDR1_RX register *****************/
emilmont 77:869cf507173a 5915 #define USB_ADDR1_RX_ADDR1_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 1 */
emilmont 77:869cf507173a 5916
emilmont 77:869cf507173a 5917 /***************** Bit definition for USB_ADDR2_RX register *****************/
emilmont 77:869cf507173a 5918 #define USB_ADDR2_RX_ADDR2_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 2 */
emilmont 77:869cf507173a 5919
emilmont 77:869cf507173a 5920 /***************** Bit definition for USB_ADDR3_RX register *****************/
emilmont 77:869cf507173a 5921 #define USB_ADDR3_RX_ADDR3_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 3 */
emilmont 77:869cf507173a 5922
emilmont 77:869cf507173a 5923 /***************** Bit definition for USB_ADDR4_RX register *****************/
emilmont 77:869cf507173a 5924 #define USB_ADDR4_RX_ADDR4_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 4 */
emilmont 77:869cf507173a 5925
emilmont 77:869cf507173a 5926 /***************** Bit definition for USB_ADDR5_RX register *****************/
emilmont 77:869cf507173a 5927 #define USB_ADDR5_RX_ADDR5_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 5 */
emilmont 77:869cf507173a 5928
emilmont 77:869cf507173a 5929 /***************** Bit definition for USB_ADDR6_RX register *****************/
emilmont 77:869cf507173a 5930 #define USB_ADDR6_RX_ADDR6_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 6 */
emilmont 77:869cf507173a 5931
emilmont 77:869cf507173a 5932 /***************** Bit definition for USB_ADDR7_RX register *****************/
emilmont 77:869cf507173a 5933 #define USB_ADDR7_RX_ADDR7_RX ((uint16_t)0xFFFE) /*!< Reception Buffer Address 7 */
emilmont 77:869cf507173a 5934
emilmont 77:869cf507173a 5935 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 5936
emilmont 77:869cf507173a 5937 /***************** Bit definition for USB_COUNT0_RX register ****************/
emilmont 77:869cf507173a 5938 #define USB_COUNT0_RX_COUNT0_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
emilmont 77:869cf507173a 5939
emilmont 77:869cf507173a 5940 #define USB_COUNT0_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
emilmont 77:869cf507173a 5941 #define USB_COUNT0_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 5942 #define USB_COUNT0_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 5943 #define USB_COUNT0_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
emilmont 77:869cf507173a 5944 #define USB_COUNT0_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
emilmont 77:869cf507173a 5945 #define USB_COUNT0_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
emilmont 77:869cf507173a 5946
emilmont 77:869cf507173a 5947 #define USB_COUNT0_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
emilmont 77:869cf507173a 5948
emilmont 77:869cf507173a 5949 /***************** Bit definition for USB_COUNT1_RX register ****************/
emilmont 77:869cf507173a 5950 #define USB_COUNT1_RX_COUNT1_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
emilmont 77:869cf507173a 5951
emilmont 77:869cf507173a 5952 #define USB_COUNT1_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
emilmont 77:869cf507173a 5953 #define USB_COUNT1_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 5954 #define USB_COUNT1_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 5955 #define USB_COUNT1_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
emilmont 77:869cf507173a 5956 #define USB_COUNT1_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
emilmont 77:869cf507173a 5957 #define USB_COUNT1_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
emilmont 77:869cf507173a 5958
emilmont 77:869cf507173a 5959 #define USB_COUNT1_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
emilmont 77:869cf507173a 5960
emilmont 77:869cf507173a 5961 /***************** Bit definition for USB_COUNT2_RX register ****************/
emilmont 77:869cf507173a 5962 #define USB_COUNT2_RX_COUNT2_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
emilmont 77:869cf507173a 5963
emilmont 77:869cf507173a 5964 #define USB_COUNT2_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
emilmont 77:869cf507173a 5965 #define USB_COUNT2_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 5966 #define USB_COUNT2_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 5967 #define USB_COUNT2_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
emilmont 77:869cf507173a 5968 #define USB_COUNT2_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
emilmont 77:869cf507173a 5969 #define USB_COUNT2_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
emilmont 77:869cf507173a 5970
emilmont 77:869cf507173a 5971 #define USB_COUNT2_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
emilmont 77:869cf507173a 5972
emilmont 77:869cf507173a 5973 /***************** Bit definition for USB_COUNT3_RX register ****************/
emilmont 77:869cf507173a 5974 #define USB_COUNT3_RX_COUNT3_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
emilmont 77:869cf507173a 5975
emilmont 77:869cf507173a 5976 #define USB_COUNT3_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
emilmont 77:869cf507173a 5977 #define USB_COUNT3_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 5978 #define USB_COUNT3_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 5979 #define USB_COUNT3_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
emilmont 77:869cf507173a 5980 #define USB_COUNT3_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
emilmont 77:869cf507173a 5981 #define USB_COUNT3_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
emilmont 77:869cf507173a 5982
emilmont 77:869cf507173a 5983 #define USB_COUNT3_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
emilmont 77:869cf507173a 5984
emilmont 77:869cf507173a 5985 /***************** Bit definition for USB_COUNT4_RX register ****************/
emilmont 77:869cf507173a 5986 #define USB_COUNT4_RX_COUNT4_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
emilmont 77:869cf507173a 5987
emilmont 77:869cf507173a 5988 #define USB_COUNT4_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
emilmont 77:869cf507173a 5989 #define USB_COUNT4_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 5990 #define USB_COUNT4_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 5991 #define USB_COUNT4_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
emilmont 77:869cf507173a 5992 #define USB_COUNT4_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
emilmont 77:869cf507173a 5993 #define USB_COUNT4_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
emilmont 77:869cf507173a 5994
emilmont 77:869cf507173a 5995 #define USB_COUNT4_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
emilmont 77:869cf507173a 5996
emilmont 77:869cf507173a 5997 /***************** Bit definition for USB_COUNT5_RX register ****************/
emilmont 77:869cf507173a 5998 #define USB_COUNT5_RX_COUNT5_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
emilmont 77:869cf507173a 5999
emilmont 77:869cf507173a 6000 #define USB_COUNT5_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
emilmont 77:869cf507173a 6001 #define USB_COUNT5_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 6002 #define USB_COUNT5_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 6003 #define USB_COUNT5_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
emilmont 77:869cf507173a 6004 #define USB_COUNT5_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
emilmont 77:869cf507173a 6005 #define USB_COUNT5_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
emilmont 77:869cf507173a 6006
emilmont 77:869cf507173a 6007 #define USB_COUNT5_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
emilmont 77:869cf507173a 6008
emilmont 77:869cf507173a 6009 /***************** Bit definition for USB_COUNT6_RX register ****************/
emilmont 77:869cf507173a 6010 #define USB_COUNT6_RX_COUNT6_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
emilmont 77:869cf507173a 6011
emilmont 77:869cf507173a 6012 #define USB_COUNT6_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
emilmont 77:869cf507173a 6013 #define USB_COUNT6_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 6014 #define USB_COUNT6_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 6015 #define USB_COUNT6_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
emilmont 77:869cf507173a 6016 #define USB_COUNT6_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
emilmont 77:869cf507173a 6017 #define USB_COUNT6_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
emilmont 77:869cf507173a 6018
emilmont 77:869cf507173a 6019 #define USB_COUNT6_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
emilmont 77:869cf507173a 6020
emilmont 77:869cf507173a 6021 /***************** Bit definition for USB_COUNT7_RX register ****************/
emilmont 77:869cf507173a 6022 #define USB_COUNT7_RX_COUNT7_RX ((uint16_t)0x03FF) /*!< Reception Byte Count */
emilmont 77:869cf507173a 6023
emilmont 77:869cf507173a 6024 #define USB_COUNT7_RX_NUM_BLOCK ((uint16_t)0x7C00) /*!< NUM_BLOCK[4:0] bits (Number of blocks) */
emilmont 77:869cf507173a 6025 #define USB_COUNT7_RX_NUM_BLOCK_0 ((uint16_t)0x0400) /*!< Bit 0 */
emilmont 77:869cf507173a 6026 #define USB_COUNT7_RX_NUM_BLOCK_1 ((uint16_t)0x0800) /*!< Bit 1 */
emilmont 77:869cf507173a 6027 #define USB_COUNT7_RX_NUM_BLOCK_2 ((uint16_t)0x1000) /*!< Bit 2 */
emilmont 77:869cf507173a 6028 #define USB_COUNT7_RX_NUM_BLOCK_3 ((uint16_t)0x2000) /*!< Bit 3 */
emilmont 77:869cf507173a 6029 #define USB_COUNT7_RX_NUM_BLOCK_4 ((uint16_t)0x4000) /*!< Bit 4 */
emilmont 77:869cf507173a 6030
emilmont 77:869cf507173a 6031 #define USB_COUNT7_RX_BLSIZE ((uint16_t)0x8000) /*!< BLock SIZE */
emilmont 77:869cf507173a 6032
emilmont 77:869cf507173a 6033 /*----------------------------------------------------------------------------*/
emilmont 77:869cf507173a 6034
emilmont 77:869cf507173a 6035 /**************** Bit definition for USB_COUNT0_RX_0 register ***************/
emilmont 77:869cf507173a 6036 #define USB_COUNT0_RX_0_COUNT0_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
emilmont 77:869cf507173a 6037
emilmont 77:869cf507173a 6038 #define USB_COUNT0_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
emilmont 77:869cf507173a 6039 #define USB_COUNT0_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 6040 #define USB_COUNT0_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 6041 #define USB_COUNT0_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 6042 #define USB_COUNT0_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 6043 #define USB_COUNT0_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 6044
emilmont 77:869cf507173a 6045 #define USB_COUNT0_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
emilmont 77:869cf507173a 6046
emilmont 77:869cf507173a 6047 /**************** Bit definition for USB_COUNT0_RX_1 register ***************/
emilmont 77:869cf507173a 6048 #define USB_COUNT0_RX_1_COUNT0_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
emilmont 77:869cf507173a 6049
emilmont 77:869cf507173a 6050 #define USB_COUNT0_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
emilmont 77:869cf507173a 6051 #define USB_COUNT0_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6052 #define USB_COUNT0_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6053 #define USB_COUNT0_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
emilmont 77:869cf507173a 6054 #define USB_COUNT0_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
emilmont 77:869cf507173a 6055 #define USB_COUNT0_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
emilmont 77:869cf507173a 6056
emilmont 77:869cf507173a 6057 #define USB_COUNT0_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
emilmont 77:869cf507173a 6058
emilmont 77:869cf507173a 6059 /**************** Bit definition for USB_COUNT1_RX_0 register ***************/
emilmont 77:869cf507173a 6060 #define USB_COUNT1_RX_0_COUNT1_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
emilmont 77:869cf507173a 6061
emilmont 77:869cf507173a 6062 #define USB_COUNT1_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
emilmont 77:869cf507173a 6063 #define USB_COUNT1_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 6064 #define USB_COUNT1_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 6065 #define USB_COUNT1_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 6066 #define USB_COUNT1_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 6067 #define USB_COUNT1_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 6068
emilmont 77:869cf507173a 6069 #define USB_COUNT1_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
emilmont 77:869cf507173a 6070
emilmont 77:869cf507173a 6071 /**************** Bit definition for USB_COUNT1_RX_1 register ***************/
emilmont 77:869cf507173a 6072 #define USB_COUNT1_RX_1_COUNT1_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
emilmont 77:869cf507173a 6073
emilmont 77:869cf507173a 6074 #define USB_COUNT1_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
emilmont 77:869cf507173a 6075 #define USB_COUNT1_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
emilmont 77:869cf507173a 6076 #define USB_COUNT1_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6077 #define USB_COUNT1_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
emilmont 77:869cf507173a 6078 #define USB_COUNT1_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
emilmont 77:869cf507173a 6079 #define USB_COUNT1_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
emilmont 77:869cf507173a 6080
emilmont 77:869cf507173a 6081 #define USB_COUNT1_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
emilmont 77:869cf507173a 6082
emilmont 77:869cf507173a 6083 /**************** Bit definition for USB_COUNT2_RX_0 register ***************/
emilmont 77:869cf507173a 6084 #define USB_COUNT2_RX_0_COUNT2_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
emilmont 77:869cf507173a 6085
emilmont 77:869cf507173a 6086 #define USB_COUNT2_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
emilmont 77:869cf507173a 6087 #define USB_COUNT2_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 6088 #define USB_COUNT2_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 6089 #define USB_COUNT2_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 6090 #define USB_COUNT2_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 6091 #define USB_COUNT2_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 6092
emilmont 77:869cf507173a 6093 #define USB_COUNT2_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
emilmont 77:869cf507173a 6094
emilmont 77:869cf507173a 6095 /**************** Bit definition for USB_COUNT2_RX_1 register ***************/
emilmont 77:869cf507173a 6096 #define USB_COUNT2_RX_1_COUNT2_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
emilmont 77:869cf507173a 6097
emilmont 77:869cf507173a 6098 #define USB_COUNT2_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
emilmont 77:869cf507173a 6099 #define USB_COUNT2_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
emilmont 77:869cf507173a 6100 #define USB_COUNT2_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6101 #define USB_COUNT2_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
emilmont 77:869cf507173a 6102 #define USB_COUNT2_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
emilmont 77:869cf507173a 6103 #define USB_COUNT2_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
emilmont 77:869cf507173a 6104
emilmont 77:869cf507173a 6105 #define USB_COUNT2_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
emilmont 77:869cf507173a 6106
emilmont 77:869cf507173a 6107 /**************** Bit definition for USB_COUNT3_RX_0 register ***************/
emilmont 77:869cf507173a 6108 #define USB_COUNT3_RX_0_COUNT3_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
emilmont 77:869cf507173a 6109
emilmont 77:869cf507173a 6110 #define USB_COUNT3_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
emilmont 77:869cf507173a 6111 #define USB_COUNT3_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 6112 #define USB_COUNT3_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 6113 #define USB_COUNT3_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 6114 #define USB_COUNT3_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 6115 #define USB_COUNT3_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 6116
emilmont 77:869cf507173a 6117 #define USB_COUNT3_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
emilmont 77:869cf507173a 6118
emilmont 77:869cf507173a 6119 /**************** Bit definition for USB_COUNT3_RX_1 register ***************/
emilmont 77:869cf507173a 6120 #define USB_COUNT3_RX_1_COUNT3_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
emilmont 77:869cf507173a 6121
emilmont 77:869cf507173a 6122 #define USB_COUNT3_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
emilmont 77:869cf507173a 6123 #define USB_COUNT3_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
emilmont 77:869cf507173a 6124 #define USB_COUNT3_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6125 #define USB_COUNT3_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
emilmont 77:869cf507173a 6126 #define USB_COUNT3_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
emilmont 77:869cf507173a 6127 #define USB_COUNT3_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
emilmont 77:869cf507173a 6128
emilmont 77:869cf507173a 6129 #define USB_COUNT3_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
emilmont 77:869cf507173a 6130
emilmont 77:869cf507173a 6131 /**************** Bit definition for USB_COUNT4_RX_0 register ***************/
emilmont 77:869cf507173a 6132 #define USB_COUNT4_RX_0_COUNT4_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
emilmont 77:869cf507173a 6133
emilmont 77:869cf507173a 6134 #define USB_COUNT4_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
emilmont 77:869cf507173a 6135 #define USB_COUNT4_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 6136 #define USB_COUNT4_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 6137 #define USB_COUNT4_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 6138 #define USB_COUNT4_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 6139 #define USB_COUNT4_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 6140
emilmont 77:869cf507173a 6141 #define USB_COUNT4_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
emilmont 77:869cf507173a 6142
emilmont 77:869cf507173a 6143 /**************** Bit definition for USB_COUNT4_RX_1 register ***************/
emilmont 77:869cf507173a 6144 #define USB_COUNT4_RX_1_COUNT4_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
emilmont 77:869cf507173a 6145
emilmont 77:869cf507173a 6146 #define USB_COUNT4_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
emilmont 77:869cf507173a 6147 #define USB_COUNT4_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
emilmont 77:869cf507173a 6148 #define USB_COUNT4_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6149 #define USB_COUNT4_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
emilmont 77:869cf507173a 6150 #define USB_COUNT4_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
emilmont 77:869cf507173a 6151 #define USB_COUNT4_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
emilmont 77:869cf507173a 6152
emilmont 77:869cf507173a 6153 #define USB_COUNT4_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
emilmont 77:869cf507173a 6154
emilmont 77:869cf507173a 6155 /**************** Bit definition for USB_COUNT5_RX_0 register ***************/
emilmont 77:869cf507173a 6156 #define USB_COUNT5_RX_0_COUNT5_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
emilmont 77:869cf507173a 6157
emilmont 77:869cf507173a 6158 #define USB_COUNT5_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
emilmont 77:869cf507173a 6159 #define USB_COUNT5_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 6160 #define USB_COUNT5_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 6161 #define USB_COUNT5_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 6162 #define USB_COUNT5_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 6163 #define USB_COUNT5_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 6164
emilmont 77:869cf507173a 6165 #define USB_COUNT5_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
emilmont 77:869cf507173a 6166
emilmont 77:869cf507173a 6167 /**************** Bit definition for USB_COUNT5_RX_1 register ***************/
emilmont 77:869cf507173a 6168 #define USB_COUNT5_RX_1_COUNT5_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
emilmont 77:869cf507173a 6169
emilmont 77:869cf507173a 6170 #define USB_COUNT5_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
emilmont 77:869cf507173a 6171 #define USB_COUNT5_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
emilmont 77:869cf507173a 6172 #define USB_COUNT5_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6173 #define USB_COUNT5_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
emilmont 77:869cf507173a 6174 #define USB_COUNT5_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
emilmont 77:869cf507173a 6175 #define USB_COUNT5_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
emilmont 77:869cf507173a 6176
emilmont 77:869cf507173a 6177 #define USB_COUNT5_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
emilmont 77:869cf507173a 6178
emilmont 77:869cf507173a 6179 /*************** Bit definition for USB_COUNT6_RX_0 register ***************/
emilmont 77:869cf507173a 6180 #define USB_COUNT6_RX_0_COUNT6_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
emilmont 77:869cf507173a 6181
emilmont 77:869cf507173a 6182 #define USB_COUNT6_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
emilmont 77:869cf507173a 6183 #define USB_COUNT6_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 6184 #define USB_COUNT6_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 6185 #define USB_COUNT6_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 6186 #define USB_COUNT6_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 6187 #define USB_COUNT6_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 6188
emilmont 77:869cf507173a 6189 #define USB_COUNT6_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
emilmont 77:869cf507173a 6190
emilmont 77:869cf507173a 6191 /**************** Bit definition for USB_COUNT6_RX_1 register ***************/
emilmont 77:869cf507173a 6192 #define USB_COUNT6_RX_1_COUNT6_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
emilmont 77:869cf507173a 6193
emilmont 77:869cf507173a 6194 #define USB_COUNT6_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
emilmont 77:869cf507173a 6195 #define USB_COUNT6_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
emilmont 77:869cf507173a 6196 #define USB_COUNT6_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6197 #define USB_COUNT6_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
emilmont 77:869cf507173a 6198 #define USB_COUNT6_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
emilmont 77:869cf507173a 6199 #define USB_COUNT6_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
emilmont 77:869cf507173a 6200
emilmont 77:869cf507173a 6201 #define USB_COUNT6_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
emilmont 77:869cf507173a 6202
emilmont 77:869cf507173a 6203 /*************** Bit definition for USB_COUNT7_RX_0 register ****************/
emilmont 77:869cf507173a 6204 #define USB_COUNT7_RX_0_COUNT7_RX_0 ((uint32_t)0x000003FF) /*!< Reception Byte Count (low) */
emilmont 77:869cf507173a 6205
emilmont 77:869cf507173a 6206 #define USB_COUNT7_RX_0_NUM_BLOCK_0 ((uint32_t)0x00007C00) /*!< NUM_BLOCK_0[4:0] bits (Number of blocks) (low) */
emilmont 77:869cf507173a 6207 #define USB_COUNT7_RX_0_NUM_BLOCK_0_0 ((uint32_t)0x00000400) /*!< Bit 0 */
emilmont 77:869cf507173a 6208 #define USB_COUNT7_RX_0_NUM_BLOCK_0_1 ((uint32_t)0x00000800) /*!< Bit 1 */
emilmont 77:869cf507173a 6209 #define USB_COUNT7_RX_0_NUM_BLOCK_0_2 ((uint32_t)0x00001000) /*!< Bit 2 */
emilmont 77:869cf507173a 6210 #define USB_COUNT7_RX_0_NUM_BLOCK_0_3 ((uint32_t)0x00002000) /*!< Bit 3 */
emilmont 77:869cf507173a 6211 #define USB_COUNT7_RX_0_NUM_BLOCK_0_4 ((uint32_t)0x00004000) /*!< Bit 4 */
emilmont 77:869cf507173a 6212
emilmont 77:869cf507173a 6213 #define USB_COUNT7_RX_0_BLSIZE_0 ((uint32_t)0x00008000) /*!< BLock SIZE (low) */
emilmont 77:869cf507173a 6214
emilmont 77:869cf507173a 6215 /*************** Bit definition for USB_COUNT7_RX_1 register ****************/
emilmont 77:869cf507173a 6216 #define USB_COUNT7_RX_1_COUNT7_RX_1 ((uint32_t)0x03FF0000) /*!< Reception Byte Count (high) */
emilmont 77:869cf507173a 6217
emilmont 77:869cf507173a 6218 #define USB_COUNT7_RX_1_NUM_BLOCK_1 ((uint32_t)0x7C000000) /*!< NUM_BLOCK_1[4:0] bits (Number of blocks) (high) */
emilmont 77:869cf507173a 6219 #define USB_COUNT7_RX_1_NUM_BLOCK_1_0 ((uint32_t)0x04000000) /*!< Bit 0 */
emilmont 77:869cf507173a 6220 #define USB_COUNT7_RX_1_NUM_BLOCK_1_1 ((uint32_t)0x08000000) /*!< Bit 1 */
emilmont 77:869cf507173a 6221 #define USB_COUNT7_RX_1_NUM_BLOCK_1_2 ((uint32_t)0x10000000) /*!< Bit 2 */
emilmont 77:869cf507173a 6222 #define USB_COUNT7_RX_1_NUM_BLOCK_1_3 ((uint32_t)0x20000000) /*!< Bit 3 */
emilmont 77:869cf507173a 6223 #define USB_COUNT7_RX_1_NUM_BLOCK_1_4 ((uint32_t)0x40000000) /*!< Bit 4 */
emilmont 77:869cf507173a 6224
emilmont 77:869cf507173a 6225 #define USB_COUNT7_RX_1_BLSIZE_1 ((uint32_t)0x80000000) /*!< BLock SIZE (high) */
emilmont 77:869cf507173a 6226
emilmont 77:869cf507173a 6227 /******************************************************************************/
emilmont 77:869cf507173a 6228 /* */
emilmont 77:869cf507173a 6229 /* Window WATCHDOG (WWDG) */
emilmont 77:869cf507173a 6230 /* */
emilmont 77:869cf507173a 6231 /******************************************************************************/
emilmont 77:869cf507173a 6232
emilmont 77:869cf507173a 6233 /******************* Bit definition for WWDG_CR register ********************/
emilmont 77:869cf507173a 6234 #define WWDG_CR_T ((uint8_t)0x7F) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
emilmont 77:869cf507173a 6235 #define WWDG_CR_T0 ((uint8_t)0x01) /*!< Bit 0 */
emilmont 77:869cf507173a 6236 #define WWDG_CR_T1 ((uint8_t)0x02) /*!< Bit 1 */
emilmont 77:869cf507173a 6237 #define WWDG_CR_T2 ((uint8_t)0x04) /*!< Bit 2 */
emilmont 77:869cf507173a 6238 #define WWDG_CR_T3 ((uint8_t)0x08) /*!< Bit 3 */
emilmont 77:869cf507173a 6239 #define WWDG_CR_T4 ((uint8_t)0x10) /*!< Bit 4 */
emilmont 77:869cf507173a 6240 #define WWDG_CR_T5 ((uint8_t)0x20) /*!< Bit 5 */
emilmont 77:869cf507173a 6241 #define WWDG_CR_T6 ((uint8_t)0x40) /*!< Bit 6 */
emilmont 77:869cf507173a 6242
emilmont 77:869cf507173a 6243 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!< Activation bit */
emilmont 77:869cf507173a 6244
emilmont 77:869cf507173a 6245 /******************* Bit definition for WWDG_CFR register *******************/
emilmont 77:869cf507173a 6246 #define WWDG_CFR_W ((uint16_t)0x007F) /*!< W[6:0] bits (7-bit window value) */
emilmont 77:869cf507173a 6247 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!< Bit 0 */
emilmont 77:869cf507173a 6248 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!< Bit 1 */
emilmont 77:869cf507173a 6249 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!< Bit 2 */
emilmont 77:869cf507173a 6250 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!< Bit 3 */
emilmont 77:869cf507173a 6251 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!< Bit 4 */
emilmont 77:869cf507173a 6252 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!< Bit 5 */
emilmont 77:869cf507173a 6253 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!< Bit 6 */
emilmont 77:869cf507173a 6254
emilmont 77:869cf507173a 6255 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!< WDGTB[1:0] bits (Timer Base) */
emilmont 77:869cf507173a 6256 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!< Bit 0 */
emilmont 77:869cf507173a 6257 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!< Bit 1 */
emilmont 77:869cf507173a 6258
emilmont 77:869cf507173a 6259 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!< Early Wakeup Interrupt */
emilmont 77:869cf507173a 6260
emilmont 77:869cf507173a 6261 /******************* Bit definition for WWDG_SR register ********************/
emilmont 77:869cf507173a 6262 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!< Early Wakeup Interrupt Flag */
emilmont 77:869cf507173a 6263
emilmont 77:869cf507173a 6264 /******************************************************************************/
emilmont 77:869cf507173a 6265 /* */
emilmont 77:869cf507173a 6266 /* SystemTick (SysTick) */
emilmont 77:869cf507173a 6267 /* */
emilmont 77:869cf507173a 6268 /******************************************************************************/
emilmont 77:869cf507173a 6269
emilmont 77:869cf507173a 6270 /***************** Bit definition for SysTick_CTRL register *****************/
emilmont 77:869cf507173a 6271 #define SysTick_CTRL_ENABLE ((uint32_t)0x00000001) /*!< Counter enable */
emilmont 77:869cf507173a 6272 #define SysTick_CTRL_TICKINT ((uint32_t)0x00000002) /*!< Counting down to 0 pends the SysTick handler */
emilmont 77:869cf507173a 6273 #define SysTick_CTRL_CLKSOURCE ((uint32_t)0x00000004) /*!< Clock source */
emilmont 77:869cf507173a 6274 #define SysTick_CTRL_COUNTFLAG ((uint32_t)0x00010000) /*!< Count Flag */
emilmont 77:869cf507173a 6275
emilmont 77:869cf507173a 6276 /***************** Bit definition for SysTick_LOAD register *****************/
emilmont 77:869cf507173a 6277 #define SysTick_LOAD_RELOAD ((uint32_t)0x00FFFFFF) /*!< Value to load into the SysTick Current Value Register when the counter reaches 0 */
emilmont 77:869cf507173a 6278
emilmont 77:869cf507173a 6279 /***************** Bit definition for SysTick_VAL register ******************/
emilmont 77:869cf507173a 6280 #define SysTick_VAL_CURRENT ((uint32_t)0x00FFFFFF) /*!< Current value at the time the register is accessed */
emilmont 77:869cf507173a 6281
emilmont 77:869cf507173a 6282 /***************** Bit definition for SysTick_CALIB register ****************/
emilmont 77:869cf507173a 6283 #define SysTick_CALIB_TENMS ((uint32_t)0x00FFFFFF) /*!< Reload value to use for 10ms timing */
emilmont 77:869cf507173a 6284 #define SysTick_CALIB_SKEW ((uint32_t)0x40000000) /*!< Calibration value is not exactly 10 ms */
emilmont 77:869cf507173a 6285 #define SysTick_CALIB_NOREF ((uint32_t)0x80000000) /*!< The reference clock is not provided */
emilmont 77:869cf507173a 6286
emilmont 77:869cf507173a 6287 /******************************************************************************/
emilmont 77:869cf507173a 6288 /* */
emilmont 77:869cf507173a 6289 /* Nested Vectored Interrupt Controller (NVIC) */
emilmont 77:869cf507173a 6290 /* */
emilmont 77:869cf507173a 6291 /******************************************************************************/
emilmont 77:869cf507173a 6292
emilmont 77:869cf507173a 6293 /****************** Bit definition for NVIC_ISER register *******************/
emilmont 77:869cf507173a 6294 #define NVIC_ISER_SETENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt set enable bits */
emilmont 77:869cf507173a 6295 #define NVIC_ISER_SETENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
emilmont 77:869cf507173a 6296 #define NVIC_ISER_SETENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
emilmont 77:869cf507173a 6297 #define NVIC_ISER_SETENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
emilmont 77:869cf507173a 6298 #define NVIC_ISER_SETENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
emilmont 77:869cf507173a 6299 #define NVIC_ISER_SETENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
emilmont 77:869cf507173a 6300 #define NVIC_ISER_SETENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
emilmont 77:869cf507173a 6301 #define NVIC_ISER_SETENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
emilmont 77:869cf507173a 6302 #define NVIC_ISER_SETENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
emilmont 77:869cf507173a 6303 #define NVIC_ISER_SETENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
emilmont 77:869cf507173a 6304 #define NVIC_ISER_SETENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
emilmont 77:869cf507173a 6305 #define NVIC_ISER_SETENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
emilmont 77:869cf507173a 6306 #define NVIC_ISER_SETENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
emilmont 77:869cf507173a 6307 #define NVIC_ISER_SETENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
emilmont 77:869cf507173a 6308 #define NVIC_ISER_SETENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
emilmont 77:869cf507173a 6309 #define NVIC_ISER_SETENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
emilmont 77:869cf507173a 6310 #define NVIC_ISER_SETENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
emilmont 77:869cf507173a 6311 #define NVIC_ISER_SETENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
emilmont 77:869cf507173a 6312 #define NVIC_ISER_SETENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
emilmont 77:869cf507173a 6313 #define NVIC_ISER_SETENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
emilmont 77:869cf507173a 6314 #define NVIC_ISER_SETENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
emilmont 77:869cf507173a 6315 #define NVIC_ISER_SETENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
emilmont 77:869cf507173a 6316 #define NVIC_ISER_SETENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
emilmont 77:869cf507173a 6317 #define NVIC_ISER_SETENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
emilmont 77:869cf507173a 6318 #define NVIC_ISER_SETENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
emilmont 77:869cf507173a 6319 #define NVIC_ISER_SETENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
emilmont 77:869cf507173a 6320 #define NVIC_ISER_SETENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
emilmont 77:869cf507173a 6321 #define NVIC_ISER_SETENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
emilmont 77:869cf507173a 6322 #define NVIC_ISER_SETENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
emilmont 77:869cf507173a 6323 #define NVIC_ISER_SETENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
emilmont 77:869cf507173a 6324 #define NVIC_ISER_SETENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
emilmont 77:869cf507173a 6325 #define NVIC_ISER_SETENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
emilmont 77:869cf507173a 6326 #define NVIC_ISER_SETENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
emilmont 77:869cf507173a 6327
emilmont 77:869cf507173a 6328 /****************** Bit definition for NVIC_ICER register *******************/
emilmont 77:869cf507173a 6329 #define NVIC_ICER_CLRENA ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-enable bits */
emilmont 77:869cf507173a 6330 #define NVIC_ICER_CLRENA_0 ((uint32_t)0x00000001) /*!< bit 0 */
emilmont 77:869cf507173a 6331 #define NVIC_ICER_CLRENA_1 ((uint32_t)0x00000002) /*!< bit 1 */
emilmont 77:869cf507173a 6332 #define NVIC_ICER_CLRENA_2 ((uint32_t)0x00000004) /*!< bit 2 */
emilmont 77:869cf507173a 6333 #define NVIC_ICER_CLRENA_3 ((uint32_t)0x00000008) /*!< bit 3 */
emilmont 77:869cf507173a 6334 #define NVIC_ICER_CLRENA_4 ((uint32_t)0x00000010) /*!< bit 4 */
emilmont 77:869cf507173a 6335 #define NVIC_ICER_CLRENA_5 ((uint32_t)0x00000020) /*!< bit 5 */
emilmont 77:869cf507173a 6336 #define NVIC_ICER_CLRENA_6 ((uint32_t)0x00000040) /*!< bit 6 */
emilmont 77:869cf507173a 6337 #define NVIC_ICER_CLRENA_7 ((uint32_t)0x00000080) /*!< bit 7 */
emilmont 77:869cf507173a 6338 #define NVIC_ICER_CLRENA_8 ((uint32_t)0x00000100) /*!< bit 8 */
emilmont 77:869cf507173a 6339 #define NVIC_ICER_CLRENA_9 ((uint32_t)0x00000200) /*!< bit 9 */
emilmont 77:869cf507173a 6340 #define NVIC_ICER_CLRENA_10 ((uint32_t)0x00000400) /*!< bit 10 */
emilmont 77:869cf507173a 6341 #define NVIC_ICER_CLRENA_11 ((uint32_t)0x00000800) /*!< bit 11 */
emilmont 77:869cf507173a 6342 #define NVIC_ICER_CLRENA_12 ((uint32_t)0x00001000) /*!< bit 12 */
emilmont 77:869cf507173a 6343 #define NVIC_ICER_CLRENA_13 ((uint32_t)0x00002000) /*!< bit 13 */
emilmont 77:869cf507173a 6344 #define NVIC_ICER_CLRENA_14 ((uint32_t)0x00004000) /*!< bit 14 */
emilmont 77:869cf507173a 6345 #define NVIC_ICER_CLRENA_15 ((uint32_t)0x00008000) /*!< bit 15 */
emilmont 77:869cf507173a 6346 #define NVIC_ICER_CLRENA_16 ((uint32_t)0x00010000) /*!< bit 16 */
emilmont 77:869cf507173a 6347 #define NVIC_ICER_CLRENA_17 ((uint32_t)0x00020000) /*!< bit 17 */
emilmont 77:869cf507173a 6348 #define NVIC_ICER_CLRENA_18 ((uint32_t)0x00040000) /*!< bit 18 */
emilmont 77:869cf507173a 6349 #define NVIC_ICER_CLRENA_19 ((uint32_t)0x00080000) /*!< bit 19 */
emilmont 77:869cf507173a 6350 #define NVIC_ICER_CLRENA_20 ((uint32_t)0x00100000) /*!< bit 20 */
emilmont 77:869cf507173a 6351 #define NVIC_ICER_CLRENA_21 ((uint32_t)0x00200000) /*!< bit 21 */
emilmont 77:869cf507173a 6352 #define NVIC_ICER_CLRENA_22 ((uint32_t)0x00400000) /*!< bit 22 */
emilmont 77:869cf507173a 6353 #define NVIC_ICER_CLRENA_23 ((uint32_t)0x00800000) /*!< bit 23 */
emilmont 77:869cf507173a 6354 #define NVIC_ICER_CLRENA_24 ((uint32_t)0x01000000) /*!< bit 24 */
emilmont 77:869cf507173a 6355 #define NVIC_ICER_CLRENA_25 ((uint32_t)0x02000000) /*!< bit 25 */
emilmont 77:869cf507173a 6356 #define NVIC_ICER_CLRENA_26 ((uint32_t)0x04000000) /*!< bit 26 */
emilmont 77:869cf507173a 6357 #define NVIC_ICER_CLRENA_27 ((uint32_t)0x08000000) /*!< bit 27 */
emilmont 77:869cf507173a 6358 #define NVIC_ICER_CLRENA_28 ((uint32_t)0x10000000) /*!< bit 28 */
emilmont 77:869cf507173a 6359 #define NVIC_ICER_CLRENA_29 ((uint32_t)0x20000000) /*!< bit 29 */
emilmont 77:869cf507173a 6360 #define NVIC_ICER_CLRENA_30 ((uint32_t)0x40000000) /*!< bit 30 */
emilmont 77:869cf507173a 6361 #define NVIC_ICER_CLRENA_31 ((uint32_t)0x80000000) /*!< bit 31 */
emilmont 77:869cf507173a 6362
emilmont 77:869cf507173a 6363 /****************** Bit definition for NVIC_ISPR register *******************/
emilmont 77:869cf507173a 6364 #define NVIC_ISPR_SETPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt set-pending bits */
emilmont 77:869cf507173a 6365 #define NVIC_ISPR_SETPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
emilmont 77:869cf507173a 6366 #define NVIC_ISPR_SETPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
emilmont 77:869cf507173a 6367 #define NVIC_ISPR_SETPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
emilmont 77:869cf507173a 6368 #define NVIC_ISPR_SETPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
emilmont 77:869cf507173a 6369 #define NVIC_ISPR_SETPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
emilmont 77:869cf507173a 6370 #define NVIC_ISPR_SETPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
emilmont 77:869cf507173a 6371 #define NVIC_ISPR_SETPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
emilmont 77:869cf507173a 6372 #define NVIC_ISPR_SETPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
emilmont 77:869cf507173a 6373 #define NVIC_ISPR_SETPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
emilmont 77:869cf507173a 6374 #define NVIC_ISPR_SETPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
emilmont 77:869cf507173a 6375 #define NVIC_ISPR_SETPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
emilmont 77:869cf507173a 6376 #define NVIC_ISPR_SETPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
emilmont 77:869cf507173a 6377 #define NVIC_ISPR_SETPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
emilmont 77:869cf507173a 6378 #define NVIC_ISPR_SETPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
emilmont 77:869cf507173a 6379 #define NVIC_ISPR_SETPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
emilmont 77:869cf507173a 6380 #define NVIC_ISPR_SETPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
emilmont 77:869cf507173a 6381 #define NVIC_ISPR_SETPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
emilmont 77:869cf507173a 6382 #define NVIC_ISPR_SETPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
emilmont 77:869cf507173a 6383 #define NVIC_ISPR_SETPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
emilmont 77:869cf507173a 6384 #define NVIC_ISPR_SETPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
emilmont 77:869cf507173a 6385 #define NVIC_ISPR_SETPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
emilmont 77:869cf507173a 6386 #define NVIC_ISPR_SETPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
emilmont 77:869cf507173a 6387 #define NVIC_ISPR_SETPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
emilmont 77:869cf507173a 6388 #define NVIC_ISPR_SETPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
emilmont 77:869cf507173a 6389 #define NVIC_ISPR_SETPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
emilmont 77:869cf507173a 6390 #define NVIC_ISPR_SETPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
emilmont 77:869cf507173a 6391 #define NVIC_ISPR_SETPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
emilmont 77:869cf507173a 6392 #define NVIC_ISPR_SETPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
emilmont 77:869cf507173a 6393 #define NVIC_ISPR_SETPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
emilmont 77:869cf507173a 6394 #define NVIC_ISPR_SETPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
emilmont 77:869cf507173a 6395 #define NVIC_ISPR_SETPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
emilmont 77:869cf507173a 6396 #define NVIC_ISPR_SETPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
emilmont 77:869cf507173a 6397
emilmont 77:869cf507173a 6398 /****************** Bit definition for NVIC_ICPR register *******************/
emilmont 77:869cf507173a 6399 #define NVIC_ICPR_CLRPEND ((uint32_t)0xFFFFFFFF) /*!< Interrupt clear-pending bits */
emilmont 77:869cf507173a 6400 #define NVIC_ICPR_CLRPEND_0 ((uint32_t)0x00000001) /*!< bit 0 */
emilmont 77:869cf507173a 6401 #define NVIC_ICPR_CLRPEND_1 ((uint32_t)0x00000002) /*!< bit 1 */
emilmont 77:869cf507173a 6402 #define NVIC_ICPR_CLRPEND_2 ((uint32_t)0x00000004) /*!< bit 2 */
emilmont 77:869cf507173a 6403 #define NVIC_ICPR_CLRPEND_3 ((uint32_t)0x00000008) /*!< bit 3 */
emilmont 77:869cf507173a 6404 #define NVIC_ICPR_CLRPEND_4 ((uint32_t)0x00000010) /*!< bit 4 */
emilmont 77:869cf507173a 6405 #define NVIC_ICPR_CLRPEND_5 ((uint32_t)0x00000020) /*!< bit 5 */
emilmont 77:869cf507173a 6406 #define NVIC_ICPR_CLRPEND_6 ((uint32_t)0x00000040) /*!< bit 6 */
emilmont 77:869cf507173a 6407 #define NVIC_ICPR_CLRPEND_7 ((uint32_t)0x00000080) /*!< bit 7 */
emilmont 77:869cf507173a 6408 #define NVIC_ICPR_CLRPEND_8 ((uint32_t)0x00000100) /*!< bit 8 */
emilmont 77:869cf507173a 6409 #define NVIC_ICPR_CLRPEND_9 ((uint32_t)0x00000200) /*!< bit 9 */
emilmont 77:869cf507173a 6410 #define NVIC_ICPR_CLRPEND_10 ((uint32_t)0x00000400) /*!< bit 10 */
emilmont 77:869cf507173a 6411 #define NVIC_ICPR_CLRPEND_11 ((uint32_t)0x00000800) /*!< bit 11 */
emilmont 77:869cf507173a 6412 #define NVIC_ICPR_CLRPEND_12 ((uint32_t)0x00001000) /*!< bit 12 */
emilmont 77:869cf507173a 6413 #define NVIC_ICPR_CLRPEND_13 ((uint32_t)0x00002000) /*!< bit 13 */
emilmont 77:869cf507173a 6414 #define NVIC_ICPR_CLRPEND_14 ((uint32_t)0x00004000) /*!< bit 14 */
emilmont 77:869cf507173a 6415 #define NVIC_ICPR_CLRPEND_15 ((uint32_t)0x00008000) /*!< bit 15 */
emilmont 77:869cf507173a 6416 #define NVIC_ICPR_CLRPEND_16 ((uint32_t)0x00010000) /*!< bit 16 */
emilmont 77:869cf507173a 6417 #define NVIC_ICPR_CLRPEND_17 ((uint32_t)0x00020000) /*!< bit 17 */
emilmont 77:869cf507173a 6418 #define NVIC_ICPR_CLRPEND_18 ((uint32_t)0x00040000) /*!< bit 18 */
emilmont 77:869cf507173a 6419 #define NVIC_ICPR_CLRPEND_19 ((uint32_t)0x00080000) /*!< bit 19 */
emilmont 77:869cf507173a 6420 #define NVIC_ICPR_CLRPEND_20 ((uint32_t)0x00100000) /*!< bit 20 */
emilmont 77:869cf507173a 6421 #define NVIC_ICPR_CLRPEND_21 ((uint32_t)0x00200000) /*!< bit 21 */
emilmont 77:869cf507173a 6422 #define NVIC_ICPR_CLRPEND_22 ((uint32_t)0x00400000) /*!< bit 22 */
emilmont 77:869cf507173a 6423 #define NVIC_ICPR_CLRPEND_23 ((uint32_t)0x00800000) /*!< bit 23 */
emilmont 77:869cf507173a 6424 #define NVIC_ICPR_CLRPEND_24 ((uint32_t)0x01000000) /*!< bit 24 */
emilmont 77:869cf507173a 6425 #define NVIC_ICPR_CLRPEND_25 ((uint32_t)0x02000000) /*!< bit 25 */
emilmont 77:869cf507173a 6426 #define NVIC_ICPR_CLRPEND_26 ((uint32_t)0x04000000) /*!< bit 26 */
emilmont 77:869cf507173a 6427 #define NVIC_ICPR_CLRPEND_27 ((uint32_t)0x08000000) /*!< bit 27 */
emilmont 77:869cf507173a 6428 #define NVIC_ICPR_CLRPEND_28 ((uint32_t)0x10000000) /*!< bit 28 */
emilmont 77:869cf507173a 6429 #define NVIC_ICPR_CLRPEND_29 ((uint32_t)0x20000000) /*!< bit 29 */
emilmont 77:869cf507173a 6430 #define NVIC_ICPR_CLRPEND_30 ((uint32_t)0x40000000) /*!< bit 30 */
emilmont 77:869cf507173a 6431 #define NVIC_ICPR_CLRPEND_31 ((uint32_t)0x80000000) /*!< bit 31 */
emilmont 77:869cf507173a 6432
emilmont 77:869cf507173a 6433 /****************** Bit definition for NVIC_IABR register *******************/
emilmont 77:869cf507173a 6434 #define NVIC_IABR_ACTIVE ((uint32_t)0xFFFFFFFF) /*!< Interrupt active flags */
emilmont 77:869cf507173a 6435 #define NVIC_IABR_ACTIVE_0 ((uint32_t)0x00000001) /*!< bit 0 */
emilmont 77:869cf507173a 6436 #define NVIC_IABR_ACTIVE_1 ((uint32_t)0x00000002) /*!< bit 1 */
emilmont 77:869cf507173a 6437 #define NVIC_IABR_ACTIVE_2 ((uint32_t)0x00000004) /*!< bit 2 */
emilmont 77:869cf507173a 6438 #define NVIC_IABR_ACTIVE_3 ((uint32_t)0x00000008) /*!< bit 3 */
emilmont 77:869cf507173a 6439 #define NVIC_IABR_ACTIVE_4 ((uint32_t)0x00000010) /*!< bit 4 */
emilmont 77:869cf507173a 6440 #define NVIC_IABR_ACTIVE_5 ((uint32_t)0x00000020) /*!< bit 5 */
emilmont 77:869cf507173a 6441 #define NVIC_IABR_ACTIVE_6 ((uint32_t)0x00000040) /*!< bit 6 */
emilmont 77:869cf507173a 6442 #define NVIC_IABR_ACTIVE_7 ((uint32_t)0x00000080) /*!< bit 7 */
emilmont 77:869cf507173a 6443 #define NVIC_IABR_ACTIVE_8 ((uint32_t)0x00000100) /*!< bit 8 */
emilmont 77:869cf507173a 6444 #define NVIC_IABR_ACTIVE_9 ((uint32_t)0x00000200) /*!< bit 9 */
emilmont 77:869cf507173a 6445 #define NVIC_IABR_ACTIVE_10 ((uint32_t)0x00000400) /*!< bit 10 */
emilmont 77:869cf507173a 6446 #define NVIC_IABR_ACTIVE_11 ((uint32_t)0x00000800) /*!< bit 11 */
emilmont 77:869cf507173a 6447 #define NVIC_IABR_ACTIVE_12 ((uint32_t)0x00001000) /*!< bit 12 */
emilmont 77:869cf507173a 6448 #define NVIC_IABR_ACTIVE_13 ((uint32_t)0x00002000) /*!< bit 13 */
emilmont 77:869cf507173a 6449 #define NVIC_IABR_ACTIVE_14 ((uint32_t)0x00004000) /*!< bit 14 */
emilmont 77:869cf507173a 6450 #define NVIC_IABR_ACTIVE_15 ((uint32_t)0x00008000) /*!< bit 15 */
emilmont 77:869cf507173a 6451 #define NVIC_IABR_ACTIVE_16 ((uint32_t)0x00010000) /*!< bit 16 */
emilmont 77:869cf507173a 6452 #define NVIC_IABR_ACTIVE_17 ((uint32_t)0x00020000) /*!< bit 17 */
emilmont 77:869cf507173a 6453 #define NVIC_IABR_ACTIVE_18 ((uint32_t)0x00040000) /*!< bit 18 */
emilmont 77:869cf507173a 6454 #define NVIC_IABR_ACTIVE_19 ((uint32_t)0x00080000) /*!< bit 19 */
emilmont 77:869cf507173a 6455 #define NVIC_IABR_ACTIVE_20 ((uint32_t)0x00100000) /*!< bit 20 */
emilmont 77:869cf507173a 6456 #define NVIC_IABR_ACTIVE_21 ((uint32_t)0x00200000) /*!< bit 21 */
emilmont 77:869cf507173a 6457 #define NVIC_IABR_ACTIVE_22 ((uint32_t)0x00400000) /*!< bit 22 */
emilmont 77:869cf507173a 6458 #define NVIC_IABR_ACTIVE_23 ((uint32_t)0x00800000) /*!< bit 23 */
emilmont 77:869cf507173a 6459 #define NVIC_IABR_ACTIVE_24 ((uint32_t)0x01000000) /*!< bit 24 */
emilmont 77:869cf507173a 6460 #define NVIC_IABR_ACTIVE_25 ((uint32_t)0x02000000) /*!< bit 25 */
emilmont 77:869cf507173a 6461 #define NVIC_IABR_ACTIVE_26 ((uint32_t)0x04000000) /*!< bit 26 */
emilmont 77:869cf507173a 6462 #define NVIC_IABR_ACTIVE_27 ((uint32_t)0x08000000) /*!< bit 27 */
emilmont 77:869cf507173a 6463 #define NVIC_IABR_ACTIVE_28 ((uint32_t)0x10000000) /*!< bit 28 */
emilmont 77:869cf507173a 6464 #define NVIC_IABR_ACTIVE_29 ((uint32_t)0x20000000) /*!< bit 29 */
emilmont 77:869cf507173a 6465 #define NVIC_IABR_ACTIVE_30 ((uint32_t)0x40000000) /*!< bit 30 */
emilmont 77:869cf507173a 6466 #define NVIC_IABR_ACTIVE_31 ((uint32_t)0x80000000) /*!< bit 31 */
emilmont 77:869cf507173a 6467
emilmont 77:869cf507173a 6468 /****************** Bit definition for NVIC_PRI0 register *******************/
emilmont 77:869cf507173a 6469 #define NVIC_IPR0_PRI_0 ((uint32_t)0x000000FF) /*!< Priority of interrupt 0 */
emilmont 77:869cf507173a 6470 #define NVIC_IPR0_PRI_1 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 1 */
emilmont 77:869cf507173a 6471 #define NVIC_IPR0_PRI_2 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 2 */
emilmont 77:869cf507173a 6472 #define NVIC_IPR0_PRI_3 ((uint32_t)0xFF000000) /*!< Priority of interrupt 3 */
emilmont 77:869cf507173a 6473
emilmont 77:869cf507173a 6474 /****************** Bit definition for NVIC_PRI1 register *******************/
emilmont 77:869cf507173a 6475 #define NVIC_IPR1_PRI_4 ((uint32_t)0x000000FF) /*!< Priority of interrupt 4 */
emilmont 77:869cf507173a 6476 #define NVIC_IPR1_PRI_5 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 5 */
emilmont 77:869cf507173a 6477 #define NVIC_IPR1_PRI_6 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 6 */
emilmont 77:869cf507173a 6478 #define NVIC_IPR1_PRI_7 ((uint32_t)0xFF000000) /*!< Priority of interrupt 7 */
emilmont 77:869cf507173a 6479
emilmont 77:869cf507173a 6480 /****************** Bit definition for NVIC_PRI2 register *******************/
emilmont 77:869cf507173a 6481 #define NVIC_IPR2_PRI_8 ((uint32_t)0x000000FF) /*!< Priority of interrupt 8 */
emilmont 77:869cf507173a 6482 #define NVIC_IPR2_PRI_9 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 9 */
emilmont 77:869cf507173a 6483 #define NVIC_IPR2_PRI_10 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 10 */
emilmont 77:869cf507173a 6484 #define NVIC_IPR2_PRI_11 ((uint32_t)0xFF000000) /*!< Priority of interrupt 11 */
emilmont 77:869cf507173a 6485
emilmont 77:869cf507173a 6486 /****************** Bit definition for NVIC_PRI3 register *******************/
emilmont 77:869cf507173a 6487 #define NVIC_IPR3_PRI_12 ((uint32_t)0x000000FF) /*!< Priority of interrupt 12 */
emilmont 77:869cf507173a 6488 #define NVIC_IPR3_PRI_13 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 13 */
emilmont 77:869cf507173a 6489 #define NVIC_IPR3_PRI_14 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 14 */
emilmont 77:869cf507173a 6490 #define NVIC_IPR3_PRI_15 ((uint32_t)0xFF000000) /*!< Priority of interrupt 15 */
emilmont 77:869cf507173a 6491
emilmont 77:869cf507173a 6492 /****************** Bit definition for NVIC_PRI4 register *******************/
emilmont 77:869cf507173a 6493 #define NVIC_IPR4_PRI_16 ((uint32_t)0x000000FF) /*!< Priority of interrupt 16 */
emilmont 77:869cf507173a 6494 #define NVIC_IPR4_PRI_17 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 17 */
emilmont 77:869cf507173a 6495 #define NVIC_IPR4_PRI_18 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 18 */
emilmont 77:869cf507173a 6496 #define NVIC_IPR4_PRI_19 ((uint32_t)0xFF000000) /*!< Priority of interrupt 19 */
emilmont 77:869cf507173a 6497
emilmont 77:869cf507173a 6498 /****************** Bit definition for NVIC_PRI5 register *******************/
emilmont 77:869cf507173a 6499 #define NVIC_IPR5_PRI_20 ((uint32_t)0x000000FF) /*!< Priority of interrupt 20 */
emilmont 77:869cf507173a 6500 #define NVIC_IPR5_PRI_21 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 21 */
emilmont 77:869cf507173a 6501 #define NVIC_IPR5_PRI_22 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 22 */
emilmont 77:869cf507173a 6502 #define NVIC_IPR5_PRI_23 ((uint32_t)0xFF000000) /*!< Priority of interrupt 23 */
emilmont 77:869cf507173a 6503
emilmont 77:869cf507173a 6504 /****************** Bit definition for NVIC_PRI6 register *******************/
emilmont 77:869cf507173a 6505 #define NVIC_IPR6_PRI_24 ((uint32_t)0x000000FF) /*!< Priority of interrupt 24 */
emilmont 77:869cf507173a 6506 #define NVIC_IPR6_PRI_25 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 25 */
emilmont 77:869cf507173a 6507 #define NVIC_IPR6_PRI_26 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 26 */
emilmont 77:869cf507173a 6508 #define NVIC_IPR6_PRI_27 ((uint32_t)0xFF000000) /*!< Priority of interrupt 27 */
emilmont 77:869cf507173a 6509
emilmont 77:869cf507173a 6510 /****************** Bit definition for NVIC_PRI7 register *******************/
emilmont 77:869cf507173a 6511 #define NVIC_IPR7_PRI_28 ((uint32_t)0x000000FF) /*!< Priority of interrupt 28 */
emilmont 77:869cf507173a 6512 #define NVIC_IPR7_PRI_29 ((uint32_t)0x0000FF00) /*!< Priority of interrupt 29 */
emilmont 77:869cf507173a 6513 #define NVIC_IPR7_PRI_30 ((uint32_t)0x00FF0000) /*!< Priority of interrupt 30 */
emilmont 77:869cf507173a 6514 #define NVIC_IPR7_PRI_31 ((uint32_t)0xFF000000) /*!< Priority of interrupt 31 */
emilmont 77:869cf507173a 6515
emilmont 77:869cf507173a 6516 /****************** Bit definition for SCB_CPUID register *******************/
emilmont 77:869cf507173a 6517 #define SCB_CPUID_REVISION ((uint32_t)0x0000000F) /*!< Implementation defined revision number */
emilmont 77:869cf507173a 6518 #define SCB_CPUID_PARTNO ((uint32_t)0x0000FFF0) /*!< Number of processor within family */
emilmont 77:869cf507173a 6519 #define SCB_CPUID_Constant ((uint32_t)0x000F0000) /*!< Reads as 0x0F */
emilmont 77:869cf507173a 6520 #define SCB_CPUID_VARIANT ((uint32_t)0x00F00000) /*!< Implementation defined variant number */
emilmont 77:869cf507173a 6521 #define SCB_CPUID_IMPLEMENTER ((uint32_t)0xFF000000) /*!< Implementer code. ARM is 0x41 */
emilmont 77:869cf507173a 6522
emilmont 77:869cf507173a 6523 /******************* Bit definition for SCB_ICSR register *******************/
emilmont 77:869cf507173a 6524 #define SCB_ICSR_VECTACTIVE ((uint32_t)0x000001FF) /*!< Active ISR number field */
emilmont 77:869cf507173a 6525 #define SCB_ICSR_RETTOBASE ((uint32_t)0x00000800) /*!< All active exceptions minus the IPSR_current_exception yields the empty set */
emilmont 77:869cf507173a 6526 #define SCB_ICSR_VECTPENDING ((uint32_t)0x003FF000) /*!< Pending ISR number field */
emilmont 77:869cf507173a 6527 #define SCB_ICSR_ISRPENDING ((uint32_t)0x00400000) /*!< Interrupt pending flag */
emilmont 77:869cf507173a 6528 #define SCB_ICSR_ISRPREEMPT ((uint32_t)0x00800000) /*!< It indicates that a pending interrupt becomes active in the next running cycle */
emilmont 77:869cf507173a 6529 #define SCB_ICSR_PENDSTCLR ((uint32_t)0x02000000) /*!< Clear pending SysTick bit */
emilmont 77:869cf507173a 6530 #define SCB_ICSR_PENDSTSET ((uint32_t)0x04000000) /*!< Set pending SysTick bit */
emilmont 77:869cf507173a 6531 #define SCB_ICSR_PENDSVCLR ((uint32_t)0x08000000) /*!< Clear pending pendSV bit */
emilmont 77:869cf507173a 6532 #define SCB_ICSR_PENDSVSET ((uint32_t)0x10000000) /*!< Set pending pendSV bit */
emilmont 77:869cf507173a 6533 #define SCB_ICSR_NMIPENDSET ((uint32_t)0x80000000) /*!< Set pending NMI bit */
emilmont 77:869cf507173a 6534
emilmont 77:869cf507173a 6535 /******************* Bit definition for SCB_VTOR register *******************/
emilmont 77:869cf507173a 6536 #define SCB_VTOR_TBLOFF ((uint32_t)0x1FFFFF80) /*!< Vector table base offset field */
emilmont 77:869cf507173a 6537 #define SCB_VTOR_TBLBASE ((uint32_t)0x20000000) /*!< Table base in code(0) or RAM(1) */
emilmont 77:869cf507173a 6538
emilmont 77:869cf507173a 6539 /*!<***************** Bit definition for SCB_AIRCR register *******************/
emilmont 77:869cf507173a 6540 #define SCB_AIRCR_VECTRESET ((uint32_t)0x00000001) /*!< System Reset bit */
emilmont 77:869cf507173a 6541 #define SCB_AIRCR_VECTCLRACTIVE ((uint32_t)0x00000002) /*!< Clear active vector bit */
emilmont 77:869cf507173a 6542 #define SCB_AIRCR_SYSRESETREQ ((uint32_t)0x00000004) /*!< Requests chip control logic to generate a reset */
emilmont 77:869cf507173a 6543
emilmont 77:869cf507173a 6544 #define SCB_AIRCR_PRIGROUP ((uint32_t)0x00000700) /*!< PRIGROUP[2:0] bits (Priority group) */
emilmont 77:869cf507173a 6545 #define SCB_AIRCR_PRIGROUP_0 ((uint32_t)0x00000100) /*!< Bit 0 */
emilmont 77:869cf507173a 6546 #define SCB_AIRCR_PRIGROUP_1 ((uint32_t)0x00000200) /*!< Bit 1 */
emilmont 77:869cf507173a 6547 #define SCB_AIRCR_PRIGROUP_2 ((uint32_t)0x00000400) /*!< Bit 2 */
emilmont 77:869cf507173a 6548
emilmont 77:869cf507173a 6549 /* prority group configuration */
emilmont 77:869cf507173a 6550 #define SCB_AIRCR_PRIGROUP0 ((uint32_t)0x00000000) /*!< Priority group=0 (7 bits of pre-emption priority, 1 bit of subpriority) */
emilmont 77:869cf507173a 6551 #define SCB_AIRCR_PRIGROUP1 ((uint32_t)0x00000100) /*!< Priority group=1 (6 bits of pre-emption priority, 2 bits of subpriority) */
emilmont 77:869cf507173a 6552 #define SCB_AIRCR_PRIGROUP2 ((uint32_t)0x00000200) /*!< Priority group=2 (5 bits of pre-emption priority, 3 bits of subpriority) */
emilmont 77:869cf507173a 6553 #define SCB_AIRCR_PRIGROUP3 ((uint32_t)0x00000300) /*!< Priority group=3 (4 bits of pre-emption priority, 4 bits of subpriority) */
emilmont 77:869cf507173a 6554 #define SCB_AIRCR_PRIGROUP4 ((uint32_t)0x00000400) /*!< Priority group=4 (3 bits of pre-emption priority, 5 bits of subpriority) */
emilmont 77:869cf507173a 6555 #define SCB_AIRCR_PRIGROUP5 ((uint32_t)0x00000500) /*!< Priority group=5 (2 bits of pre-emption priority, 6 bits of subpriority) */
emilmont 77:869cf507173a 6556 #define SCB_AIRCR_PRIGROUP6 ((uint32_t)0x00000600) /*!< Priority group=6 (1 bit of pre-emption priority, 7 bits of subpriority) */
emilmont 77:869cf507173a 6557 #define SCB_AIRCR_PRIGROUP7 ((uint32_t)0x00000700) /*!< Priority group=7 (no pre-emption priority, 8 bits of subpriority) */
emilmont 77:869cf507173a 6558
emilmont 77:869cf507173a 6559 #define SCB_AIRCR_ENDIANESS ((uint32_t)0x00008000) /*!< Data endianness bit */
emilmont 77:869cf507173a 6560 #define SCB_AIRCR_VECTKEY ((uint32_t)0xFFFF0000) /*!< Register key (VECTKEY) - Reads as 0xFA05 (VECTKEYSTAT) */
emilmont 77:869cf507173a 6561
emilmont 77:869cf507173a 6562 /******************* Bit definition for SCB_SCR register ********************/
emilmont 77:869cf507173a 6563 #define SCB_SCR_SLEEPONEXIT ((uint8_t)0x02) /*!< Sleep on exit bit */
emilmont 77:869cf507173a 6564 #define SCB_SCR_SLEEPDEEP ((uint8_t)0x04) /*!< Sleep deep bit */
emilmont 77:869cf507173a 6565 #define SCB_SCR_SEVONPEND ((uint8_t)0x10) /*!< Wake up from WFE */
emilmont 77:869cf507173a 6566
emilmont 77:869cf507173a 6567 /******************** Bit definition for SCB_CCR register *******************/
emilmont 77:869cf507173a 6568 #define SCB_CCR_NONBASETHRDENA ((uint16_t)0x0001) /*!< Thread mode can be entered from any level in Handler mode by controlled return value */
emilmont 77:869cf507173a 6569 #define SCB_CCR_USERSETMPEND ((uint16_t)0x0002) /*!< Enables user code to write the Software Trigger Interrupt register to trigger (pend) a Main exception */
emilmont 77:869cf507173a 6570 #define SCB_CCR_UNALIGN_TRP ((uint16_t)0x0008) /*!< Trap for unaligned access */
emilmont 77:869cf507173a 6571 #define SCB_CCR_DIV_0_TRP ((uint16_t)0x0010) /*!< Trap on Divide by 0 */
emilmont 77:869cf507173a 6572 #define SCB_CCR_BFHFNMIGN ((uint16_t)0x0100) /*!< Handlers running at priority -1 and -2 */
emilmont 77:869cf507173a 6573 #define SCB_CCR_STKALIGN ((uint16_t)0x0200) /*!< On exception entry, the SP used prior to the exception is adjusted to be 8-byte aligned */
emilmont 77:869cf507173a 6574
emilmont 77:869cf507173a 6575 /******************* Bit definition for SCB_SHPR register ********************/
emilmont 77:869cf507173a 6576 #define SCB_SHPR_PRI_N ((uint32_t)0x000000FF) /*!< Priority of system handler 4,8, and 12. Mem Manage, reserved and Debug Monitor */
emilmont 77:869cf507173a 6577 #define SCB_SHPR_PRI_N1 ((uint32_t)0x0000FF00) /*!< Priority of system handler 5,9, and 13. Bus Fault, reserved and reserved */
emilmont 77:869cf507173a 6578 #define SCB_SHPR_PRI_N2 ((uint32_t)0x00FF0000) /*!< Priority of system handler 6,10, and 14. Usage Fault, reserved and PendSV */
emilmont 77:869cf507173a 6579 #define SCB_SHPR_PRI_N3 ((uint32_t)0xFF000000) /*!< Priority of system handler 7,11, and 15. Reserved, SVCall and SysTick */
emilmont 77:869cf507173a 6580
emilmont 77:869cf507173a 6581 /****************** Bit definition for SCB_SHCSR register *******************/
emilmont 77:869cf507173a 6582 #define SCB_SHCSR_MEMFAULTACT ((uint32_t)0x00000001) /*!< MemManage is active */
emilmont 77:869cf507173a 6583 #define SCB_SHCSR_BUSFAULTACT ((uint32_t)0x00000002) /*!< BusFault is active */
emilmont 77:869cf507173a 6584 #define SCB_SHCSR_USGFAULTACT ((uint32_t)0x00000008) /*!< UsageFault is active */
emilmont 77:869cf507173a 6585 #define SCB_SHCSR_SVCALLACT ((uint32_t)0x00000080) /*!< SVCall is active */
emilmont 77:869cf507173a 6586 #define SCB_SHCSR_MONITORACT ((uint32_t)0x00000100) /*!< Monitor is active */
emilmont 77:869cf507173a 6587 #define SCB_SHCSR_PENDSVACT ((uint32_t)0x00000400) /*!< PendSV is active */
emilmont 77:869cf507173a 6588 #define SCB_SHCSR_SYSTICKACT ((uint32_t)0x00000800) /*!< SysTick is active */
emilmont 77:869cf507173a 6589 #define SCB_SHCSR_USGFAULTPENDED ((uint32_t)0x00001000) /*!< Usage Fault is pended */
emilmont 77:869cf507173a 6590 #define SCB_SHCSR_MEMFAULTPENDED ((uint32_t)0x00002000) /*!< MemManage is pended */
emilmont 77:869cf507173a 6591 #define SCB_SHCSR_BUSFAULTPENDED ((uint32_t)0x00004000) /*!< Bus Fault is pended */
emilmont 77:869cf507173a 6592 #define SCB_SHCSR_SVCALLPENDED ((uint32_t)0x00008000) /*!< SVCall is pended */
emilmont 77:869cf507173a 6593 #define SCB_SHCSR_MEMFAULTENA ((uint32_t)0x00010000) /*!< MemManage enable */
emilmont 77:869cf507173a 6594 #define SCB_SHCSR_BUSFAULTENA ((uint32_t)0x00020000) /*!< Bus Fault enable */
emilmont 77:869cf507173a 6595 #define SCB_SHCSR_USGFAULTENA ((uint32_t)0x00040000) /*!< UsageFault enable */
emilmont 77:869cf507173a 6596
emilmont 77:869cf507173a 6597 /******************* Bit definition for SCB_CFSR register *******************/
emilmont 77:869cf507173a 6598 /*!< MFSR */
emilmont 77:869cf507173a 6599 #define SCB_CFSR_IACCVIOL ((uint32_t)0x00000001) /*!< Instruction access violation */
emilmont 77:869cf507173a 6600 #define SCB_CFSR_DACCVIOL ((uint32_t)0x00000002) /*!< Data access violation */
emilmont 77:869cf507173a 6601 #define SCB_CFSR_MUNSTKERR ((uint32_t)0x00000008) /*!< Unstacking error */
emilmont 77:869cf507173a 6602 #define SCB_CFSR_MSTKERR ((uint32_t)0x00000010) /*!< Stacking error */
emilmont 77:869cf507173a 6603 #define SCB_CFSR_MMARVALID ((uint32_t)0x00000080) /*!< Memory Manage Address Register address valid flag */
emilmont 77:869cf507173a 6604 /*!< BFSR */
emilmont 77:869cf507173a 6605 #define SCB_CFSR_IBUSERR ((uint32_t)0x00000100) /*!< Instruction bus error flag */
emilmont 77:869cf507173a 6606 #define SCB_CFSR_PRECISERR ((uint32_t)0x00000200) /*!< Precise data bus error */
emilmont 77:869cf507173a 6607 #define SCB_CFSR_IMPRECISERR ((uint32_t)0x00000400) /*!< Imprecise data bus error */
emilmont 77:869cf507173a 6608 #define SCB_CFSR_UNSTKERR ((uint32_t)0x00000800) /*!< Unstacking error */
emilmont 77:869cf507173a 6609 #define SCB_CFSR_STKERR ((uint32_t)0x00001000) /*!< Stacking error */
emilmont 77:869cf507173a 6610 #define SCB_CFSR_BFARVALID ((uint32_t)0x00008000) /*!< Bus Fault Address Register address valid flag */
emilmont 77:869cf507173a 6611 /*!< UFSR */
emilmont 77:869cf507173a 6612 #define SCB_CFSR_UNDEFINSTR ((uint32_t)0x00010000) /*!< The processor attempt to excecute an undefined instruction */
emilmont 77:869cf507173a 6613 #define SCB_CFSR_INVSTATE ((uint32_t)0x00020000) /*!< Invalid combination of EPSR and instruction */
emilmont 77:869cf507173a 6614 #define SCB_CFSR_INVPC ((uint32_t)0x00040000) /*!< Attempt to load EXC_RETURN into pc illegally */
emilmont 77:869cf507173a 6615 #define SCB_CFSR_NOCP ((uint32_t)0x00080000) /*!< Attempt to use a coprocessor instruction */
emilmont 77:869cf507173a 6616 #define SCB_CFSR_UNALIGNED ((uint32_t)0x01000000) /*!< Fault occurs when there is an attempt to make an unaligned memory access */
emilmont 77:869cf507173a 6617 #define SCB_CFSR_DIVBYZERO ((uint32_t)0x02000000) /*!< Fault occurs when SDIV or DIV instruction is used with a divisor of 0 */
emilmont 77:869cf507173a 6618
emilmont 77:869cf507173a 6619 /******************* Bit definition for SCB_HFSR register *******************/
emilmont 77:869cf507173a 6620 #define SCB_HFSR_VECTTBL ((uint32_t)0x00000002) /*!< Fault occures because of vector table read on exception processing */
emilmont 77:869cf507173a 6621 #define SCB_HFSR_FORCED ((uint32_t)0x40000000) /*!< Hard Fault activated when a configurable Fault was received and cannot activate */
emilmont 77:869cf507173a 6622 #define SCB_HFSR_DEBUGEVT ((uint32_t)0x80000000) /*!< Fault related to debug */
emilmont 77:869cf507173a 6623
emilmont 77:869cf507173a 6624 /******************* Bit definition for SCB_DFSR register *******************/
emilmont 77:869cf507173a 6625 #define SCB_DFSR_HALTED ((uint8_t)0x01) /*!< Halt request flag */
emilmont 77:869cf507173a 6626 #define SCB_DFSR_BKPT ((uint8_t)0x02) /*!< BKPT flag */
emilmont 77:869cf507173a 6627 #define SCB_DFSR_DWTTRAP ((uint8_t)0x04) /*!< Data Watchpoint and Trace (DWT) flag */
emilmont 77:869cf507173a 6628 #define SCB_DFSR_VCATCH ((uint8_t)0x08) /*!< Vector catch flag */
emilmont 77:869cf507173a 6629 #define SCB_DFSR_EXTERNAL ((uint8_t)0x10) /*!< External debug request flag */
emilmont 77:869cf507173a 6630
emilmont 77:869cf507173a 6631 /******************* Bit definition for SCB_MMFAR register ******************/
emilmont 77:869cf507173a 6632 #define SCB_MMFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Mem Manage fault address field */
emilmont 77:869cf507173a 6633
emilmont 77:869cf507173a 6634 /******************* Bit definition for SCB_BFAR register *******************/
emilmont 77:869cf507173a 6635 #define SCB_BFAR_ADDRESS ((uint32_t)0xFFFFFFFF) /*!< Bus fault address field */
emilmont 77:869cf507173a 6636
emilmont 77:869cf507173a 6637 /******************* Bit definition for SCB_afsr register *******************/
emilmont 77:869cf507173a 6638 #define SCB_AFSR_IMPDEF ((uint32_t)0xFFFFFFFF) /*!< Implementation defined */
emilmont 77:869cf507173a 6639 /**
emilmont 77:869cf507173a 6640 * @}
emilmont 77:869cf507173a 6641 */
emilmont 77:869cf507173a 6642
emilmont 77:869cf507173a 6643 /**
emilmont 77:869cf507173a 6644 * @}
emilmont 77:869cf507173a 6645 */
emilmont 77:869cf507173a 6646
emilmont 77:869cf507173a 6647 #ifdef USE_STDPERIPH_DRIVER
emilmont 77:869cf507173a 6648 #include "stm32l1xx_conf.h"
emilmont 77:869cf507173a 6649 #endif
emilmont 77:869cf507173a 6650
emilmont 77:869cf507173a 6651 /** @addtogroup Exported_macro
emilmont 77:869cf507173a 6652 * @{
emilmont 77:869cf507173a 6653 */
emilmont 77:869cf507173a 6654
emilmont 77:869cf507173a 6655 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
emilmont 77:869cf507173a 6656
emilmont 77:869cf507173a 6657 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
emilmont 77:869cf507173a 6658
emilmont 77:869cf507173a 6659 #define READ_BIT(REG, BIT) ((REG) & (BIT))
emilmont 77:869cf507173a 6660
emilmont 77:869cf507173a 6661 #define CLEAR_REG(REG) ((REG) = (0x0))
emilmont 77:869cf507173a 6662
emilmont 77:869cf507173a 6663 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
emilmont 77:869cf507173a 6664
emilmont 77:869cf507173a 6665 #define READ_REG(REG) ((REG))
emilmont 77:869cf507173a 6666
emilmont 77:869cf507173a 6667 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
emilmont 77:869cf507173a 6668
emilmont 77:869cf507173a 6669 /**
emilmont 77:869cf507173a 6670 * @}
emilmont 77:869cf507173a 6671 */
emilmont 77:869cf507173a 6672
emilmont 77:869cf507173a 6673 #ifdef __cplusplus
emilmont 77:869cf507173a 6674 }
emilmont 77:869cf507173a 6675 #endif
emilmont 77:869cf507173a 6676
emilmont 77:869cf507173a 6677 #endif /* __STM32L1XX_H */
emilmont 77:869cf507173a 6678
emilmont 77:869cf507173a 6679 /**
emilmont 77:869cf507173a 6680 * @}
emilmont 77:869cf507173a 6681 */
emilmont 77:869cf507173a 6682
emilmont 77:869cf507173a 6683 /**
emilmont 77:869cf507173a 6684 * @}
emilmont 77:869cf507173a 6685 */
emilmont 77:869cf507173a 6686
emilmont 77:869cf507173a 6687 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/