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TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h@81:7d30d6019079, 2014-03-19 (annotated)

Committer:: bogdanm
Date:: Wed Mar 19 18:28:32 2014 +0000
Revision:: 81:7d30d6019079
Parent:: 77:869cf507173a
Child:: 83:8a40adfe8776

Release 81 of the mbed library



Main changes:



- Updates and fixes for many targets

- LPC1768: serial interface code fixes

- nRF51822 targets now output a .hex file

- More exporters

- More flexible GPIO API

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_hal_rcc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
bogdanm	81:7d30d6019079	5	* @version V1.0.0
bogdanm	81:7d30d6019079	6	* @date 18-February-2014
emilmont	77:869cf507173a	7	* @brief Header file of RCC HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
emilmont	77:869cf507173a	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_HAL_RCC_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_HAL_RCC_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
emilmont	77:869cf507173a	52
emilmont	77:869cf507173a	53	/** @addtogroup RCC
emilmont	77:869cf507173a	54	* @{
emilmont	77:869cf507173a	55	*/
emilmont	77:869cf507173a	56
emilmont	77:869cf507173a	57	/* Exported types ------------------------------------------------------------*/
emilmont	77:869cf507173a	58
emilmont	77:869cf507173a	59	/**
emilmont	77:869cf507173a	60	* @brief RCC PLL configuration structure definition
emilmont	77:869cf507173a	61	*/
emilmont	77:869cf507173a	62	typedef struct
emilmont	77:869cf507173a	63	{
emilmont	77:869cf507173a	64	uint32_t PLLState; /*!< The new state of the PLL.
emilmont	77:869cf507173a	65	This parameter can be a value of @ref RCC_PLL_Config */
emilmont	77:869cf507173a	66
emilmont	77:869cf507173a	67	uint32_t PLLSource; /*!< RCC_PLLSource: PLL entry clock source.
emilmont	77:869cf507173a	68	This parameter must be a value of @ref RCC_PLL_Clock_Source */
emilmont	77:869cf507173a	69
emilmont	77:869cf507173a	70	uint32_t PLLM; /*!< PLLM: Division factor for PLL VCO input clock
emilmont	77:869cf507173a	71	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
emilmont	77:869cf507173a	72
emilmont	77:869cf507173a	73	uint32_t PLLN; /*!< PLLN: Multiplication factor for PLL VCO output clock
emilmont	77:869cf507173a	74	This parameter must be a number between Min_Data = 192 and Max_Data = 432 */
emilmont	77:869cf507173a	75
emilmont	77:869cf507173a	76	uint32_t PLLP; /*!< PLLP: Division factor for main system clock (SYSCLK)
emilmont	77:869cf507173a	77	This parameter must be a value of @ref RCC_PLLP_Clock_Divider. */
emilmont	77:869cf507173a	78
emilmont	77:869cf507173a	79	uint32_t PLLQ; /*!< PLLQ: Division factor for OTG FS, SDIO and RNG clocks
emilmont	77:869cf507173a	80	This parameter must be a number between Min_Data = 0 and Max_Data = 63 */
emilmont	77:869cf507173a	81
emilmont	77:869cf507173a	82	}RCC_PLLInitTypeDef;
emilmont	77:869cf507173a	83
emilmont	77:869cf507173a	84	/**
emilmont	77:869cf507173a	85	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
emilmont	77:869cf507173a	86	*/
emilmont	77:869cf507173a	87	typedef struct
emilmont	77:869cf507173a	88	{
emilmont	77:869cf507173a	89	uint32_t OscillatorType; /*!< The oscillators to be configured.
emilmont	77:869cf507173a	90	This parameter can be a value of @ref RCC_Oscillator_Type */
emilmont	77:869cf507173a	91
emilmont	77:869cf507173a	92	uint32_t HSEState; /*!< The new state of the HSE.
emilmont	77:869cf507173a	93	This parameter can be a value of @ref RCC_HSE_Config */
emilmont	77:869cf507173a	94
emilmont	77:869cf507173a	95	uint32_t LSEState; /*!< The new state of the LSE.
emilmont	77:869cf507173a	96	This parameter can be a value of @ref RCC_LSE_Config */
emilmont	77:869cf507173a	97
emilmont	77:869cf507173a	98	uint32_t HSIState; /*!< The new state of the HSI.
emilmont	77:869cf507173a	99	This parameter can be a value of @ref RCC_HSI_Config */
emilmont	77:869cf507173a	100
emilmont	77:869cf507173a	101	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
emilmont	77:869cf507173a	102	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
emilmont	77:869cf507173a	103
emilmont	77:869cf507173a	104	uint32_t LSIState; /*!< The new state of the LSI.
emilmont	77:869cf507173a	105	This parameter can be a value of @ref RCC_LSI_Config */
emilmont	77:869cf507173a	106
emilmont	77:869cf507173a	107	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
emilmont	77:869cf507173a	108
emilmont	77:869cf507173a	109	}RCC_OscInitTypeDef;
emilmont	77:869cf507173a	110
emilmont	77:869cf507173a	111	/**
emilmont	77:869cf507173a	112	* @brief RCC System, AHB and APB busses clock configuration structure definition
emilmont	77:869cf507173a	113	*/
emilmont	77:869cf507173a	114	typedef struct
emilmont	77:869cf507173a	115	{
emilmont	77:869cf507173a	116	uint32_t ClockType; /*!< The clock to be configured.
emilmont	77:869cf507173a	117	This parameter can be a value of @ref RCC_System_Clock_Type */
emilmont	77:869cf507173a	118
emilmont	77:869cf507173a	119	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
emilmont	77:869cf507173a	120	This parameter can be a value of @ref RCC_System_Clock_Source */
emilmont	77:869cf507173a	121
emilmont	77:869cf507173a	122	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
emilmont	77:869cf507173a	123	This parameter can be a value of @ref RCC_AHB_Clock_Source */
emilmont	77:869cf507173a	124
emilmont	77:869cf507173a	125	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
emilmont	77:869cf507173a	126	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
emilmont	77:869cf507173a	127
emilmont	77:869cf507173a	128	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
emilmont	77:869cf507173a	129	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
emilmont	77:869cf507173a	130
emilmont	77:869cf507173a	131	}RCC_ClkInitTypeDef;
emilmont	77:869cf507173a	132
emilmont	77:869cf507173a	133	/* Exported constants --------------------------------------------------------*/
emilmont	77:869cf507173a	134	/** @defgroup RCC_Exported_Constants
emilmont	77:869cf507173a	135	* @{
emilmont	77:869cf507173a	136	*/
emilmont	77:869cf507173a	137
emilmont	77:869cf507173a	138	/** @defgroup RCC_BitAddress_AliasRegion
emilmont	77:869cf507173a	139	* @brief RCC registers bit address in the alias region
emilmont	77:869cf507173a	140	* @{
emilmont	77:869cf507173a	141	*/
emilmont	77:869cf507173a	142	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
emilmont	77:869cf507173a	143	/* --- CR Register ---*/
emilmont	77:869cf507173a	144	/* Alias word address of HSION bit */
emilmont	77:869cf507173a	145	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
emilmont	77:869cf507173a	146	#define HSION_BitNumber 0x00
emilmont	77:869cf507173a	147	#define CR_HSION_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (HSION_BitNumber * 4))
emilmont	77:869cf507173a	148	/* Alias word address of CSSON bit */
emilmont	77:869cf507173a	149	#define CSSON_BitNumber 0x13
emilmont	77:869cf507173a	150	#define CR_CSSON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (CSSON_BitNumber * 4))
emilmont	77:869cf507173a	151	/* Alias word address of PLLON bit */
emilmont	77:869cf507173a	152	#define PLLON_BitNumber 0x18
emilmont	77:869cf507173a	153	#define CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLON_BitNumber * 4))
emilmont	77:869cf507173a	154	/* Alias word address of PLLI2SON bit */
emilmont	77:869cf507173a	155	#define PLLI2SON_BitNumber 0x1A
emilmont	77:869cf507173a	156	#define CR_PLLI2SON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
emilmont	77:869cf507173a	157
emilmont	77:869cf507173a	158	/* --- CFGR Register ---*/
emilmont	77:869cf507173a	159	/* Alias word address of I2SSRC bit */
emilmont	77:869cf507173a	160	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x08)
emilmont	77:869cf507173a	161	#define I2SSRC_BitNumber 0x17
emilmont	77:869cf507173a	162	#define CFGR_I2SSRC_BB (PERIPH_BB_BASE + (RCC_CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
emilmont	77:869cf507173a	163
emilmont	77:869cf507173a	164	/* --- BDCR Register ---*/
emilmont	77:869cf507173a	165	/* Alias word address of RTCEN bit */
emilmont	77:869cf507173a	166	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70)
emilmont	77:869cf507173a	167	#define RTCEN_BitNumber 0x0F
emilmont	77:869cf507173a	168	#define BDCR_RTCEN_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
emilmont	77:869cf507173a	169	/* Alias word address of BDRST bit */
emilmont	77:869cf507173a	170	#define BDRST_BitNumber 0x10
emilmont	77:869cf507173a	171	#define BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
emilmont	77:869cf507173a	172
emilmont	77:869cf507173a	173	/* --- CSR Register ---*/
emilmont	77:869cf507173a	174	/* Alias word address of LSION bit */
emilmont	77:869cf507173a	175	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74)
emilmont	77:869cf507173a	176	#define LSION_BitNumber 0x00
emilmont	77:869cf507173a	177	#define CSR_LSION_BB (PERIPH_BB_BASE + (RCC_CSR_OFFSET * 32) + (LSION_BitNumber * 4))
emilmont	77:869cf507173a	178
emilmont	77:869cf507173a	179	/* CR register byte 3 (Bits[23:16]) base address */
emilmont	77:869cf507173a	180	#define CR_BYTE2_ADDRESS ((uint32_t)0x40023802)
emilmont	77:869cf507173a	181
emilmont	77:869cf507173a	182	/* CIR register byte 2 (Bits[15:8]) base address */
emilmont	77:869cf507173a	183	#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x01))
emilmont	77:869cf507173a	184
emilmont	77:869cf507173a	185	/* CIR register byte 3 (Bits[23:16]) base address */
emilmont	77:869cf507173a	186	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + 0x0C + 0x02))
emilmont	77:869cf507173a	187
emilmont	77:869cf507173a	188	/* BDCR register base address */
bogdanm	81:7d30d6019079	189	#define BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
bogdanm	81:7d30d6019079	190
emilmont	77:869cf507173a	191
bogdanm	81:7d30d6019079	192	#define DBP_TIMEOUT_VALUE ((uint32_t)100)
bogdanm	81:7d30d6019079	193	#define LSE_TIMEOUT_VALUE ((uint32_t)5000)
emilmont	77:869cf507173a	194	/**
emilmont	77:869cf507173a	195	* @}
emilmont	77:869cf507173a	196	*/
emilmont	77:869cf507173a	197
emilmont	77:869cf507173a	198	/** @defgroup RCC_Oscillator_Type
emilmont	77:869cf507173a	199	* @{
emilmont	77:869cf507173a	200	*/
bogdanm	81:7d30d6019079	201	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
emilmont	77:869cf507173a	202	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
emilmont	77:869cf507173a	203	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
emilmont	77:869cf507173a	204	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
emilmont	77:869cf507173a	205	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
emilmont	77:869cf507173a	206
emilmont	77:869cf507173a	207	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15)
emilmont	77:869cf507173a	208	/**
emilmont	77:869cf507173a	209	* @}
emilmont	77:869cf507173a	210	*/
emilmont	77:869cf507173a	211
emilmont	77:869cf507173a	212	/** @defgroup RCC_HSE_Config
emilmont	77:869cf507173a	213	* @{
emilmont	77:869cf507173a	214	*/
emilmont	77:869cf507173a	215	#define RCC_HSE_OFF ((uint8_t)0x00)
emilmont	77:869cf507173a	216	#define RCC_HSE_ON ((uint8_t)0x01)
emilmont	77:869cf507173a	217	#define RCC_HSE_BYPASS ((uint8_t)0x05)
emilmont	77:869cf507173a	218
emilmont	77:869cf507173a	219	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
emilmont	77:869cf507173a	220	((HSE) == RCC_HSE_BYPASS))
emilmont	77:869cf507173a	221	/**
emilmont	77:869cf507173a	222	* @}
emilmont	77:869cf507173a	223	*/
emilmont	77:869cf507173a	224
emilmont	77:869cf507173a	225	/** @defgroup RCC_LSE_Config
emilmont	77:869cf507173a	226	* @{
emilmont	77:869cf507173a	227	*/
emilmont	77:869cf507173a	228	#define RCC_LSE_OFF ((uint8_t)0x00)
emilmont	77:869cf507173a	229	#define RCC_LSE_ON ((uint8_t)0x01)
emilmont	77:869cf507173a	230	#define RCC_LSE_BYPASS ((uint8_t)0x05)
emilmont	77:869cf507173a	231
emilmont	77:869cf507173a	232	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
emilmont	77:869cf507173a	233	((LSE) == RCC_LSE_BYPASS))
emilmont	77:869cf507173a	234	/**
emilmont	77:869cf507173a	235	* @}
emilmont	77:869cf507173a	236	*/
emilmont	77:869cf507173a	237
emilmont	77:869cf507173a	238	/** @defgroup RCC_HSI_Config
emilmont	77:869cf507173a	239	* @{
emilmont	77:869cf507173a	240	*/
emilmont	77:869cf507173a	241	#define RCC_HSI_OFF ((uint8_t)0x00)
emilmont	77:869cf507173a	242	#define RCC_HSI_ON ((uint8_t)0x01)
emilmont	77:869cf507173a	243
emilmont	77:869cf507173a	244	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
emilmont	77:869cf507173a	245	/**
emilmont	77:869cf507173a	246	* @}
emilmont	77:869cf507173a	247	*/
emilmont	77:869cf507173a	248
emilmont	77:869cf507173a	249	/** @defgroup RCC_LSI_Config
emilmont	77:869cf507173a	250	* @{
emilmont	77:869cf507173a	251	*/
emilmont	77:869cf507173a	252	#define RCC_LSI_OFF ((uint8_t)0x00)
emilmont	77:869cf507173a	253	#define RCC_LSI_ON ((uint8_t)0x01)
emilmont	77:869cf507173a	254
emilmont	77:869cf507173a	255	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
emilmont	77:869cf507173a	256	/**
emilmont	77:869cf507173a	257	* @}
emilmont	77:869cf507173a	258	*/
emilmont	77:869cf507173a	259
emilmont	77:869cf507173a	260	/** @defgroup RCC_PLL_Config
emilmont	77:869cf507173a	261	* @{
emilmont	77:869cf507173a	262	*/
emilmont	77:869cf507173a	263	#define RCC_PLL_NONE ((uint8_t)0x00)
emilmont	77:869cf507173a	264	#define RCC_PLL_OFF ((uint8_t)0x01)
emilmont	77:869cf507173a	265	#define RCC_PLL_ON ((uint8_t)0x02)
emilmont	77:869cf507173a	266
emilmont	77:869cf507173a	267	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
emilmont	77:869cf507173a	268	/**
emilmont	77:869cf507173a	269	* @}
emilmont	77:869cf507173a	270	*/
emilmont	77:869cf507173a	271
emilmont	77:869cf507173a	272	/** @defgroup RCC_PLLP_Clock_Divider
emilmont	77:869cf507173a	273	* @{
emilmont	77:869cf507173a	274	*/
emilmont	77:869cf507173a	275	#define RCC_PLLP_DIV2 ((uint32_t)0x00000002)
emilmont	77:869cf507173a	276	#define RCC_PLLP_DIV4 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	277	#define RCC_PLLP_DIV6 ((uint32_t)0x00000006)
emilmont	77:869cf507173a	278	#define RCC_PLLP_DIV8 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	279	/**
emilmont	77:869cf507173a	280	* @}
emilmont	77:869cf507173a	281	*/
emilmont	77:869cf507173a	282
emilmont	77:869cf507173a	283	/** @defgroup RCC_PLL_Clock_Source
emilmont	77:869cf507173a	284	* @{
emilmont	77:869cf507173a	285	*/
emilmont	77:869cf507173a	286	#define RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI
emilmont	77:869cf507173a	287	#define RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE
emilmont	77:869cf507173a	288
emilmont	77:869cf507173a	289	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
emilmont	77:869cf507173a	290	((SOURCE) == RCC_PLLSOURCE_HSE))
emilmont	77:869cf507173a	291	#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
emilmont	77:869cf507173a	292	#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
emilmont	77:869cf507173a	293	#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) \|\| ((VALUE) == 4) \|\| ((VALUE) == 6) \|\| ((VALUE) == 8))
emilmont	77:869cf507173a	294	#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
emilmont	77:869cf507173a	295
emilmont	77:869cf507173a	296	#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
emilmont	77:869cf507173a	297	#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))
emilmont	77:869cf507173a	298
emilmont	77:869cf507173a	299	/**
emilmont	77:869cf507173a	300	* @}
emilmont	77:869cf507173a	301	*/
emilmont	77:869cf507173a	302
emilmont	77:869cf507173a	303	/** @defgroup RCC_System_Clock_Type
emilmont	77:869cf507173a	304	* @{
emilmont	77:869cf507173a	305	*/
emilmont	77:869cf507173a	306	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
emilmont	77:869cf507173a	307	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
emilmont	77:869cf507173a	308	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
emilmont	77:869cf507173a	309	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
emilmont	77:869cf507173a	310
emilmont	77:869cf507173a	311	#define IS_RCC_CLOCKTYPE(CLK) ((1 <= (CLK)) && ((CLK) <= 15))
emilmont	77:869cf507173a	312	/**
emilmont	77:869cf507173a	313	* @}
emilmont	77:869cf507173a	314	*/
emilmont	77:869cf507173a	315
emilmont	77:869cf507173a	316	/** @defgroup RCC_System_Clock_Source
emilmont	77:869cf507173a	317	* @{
emilmont	77:869cf507173a	318	*/
emilmont	77:869cf507173a	319	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
emilmont	77:869cf507173a	320	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
emilmont	77:869cf507173a	321	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
emilmont	77:869cf507173a	322
emilmont	77:869cf507173a	323	#define IS_RCC_SYSCLKSOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSOURCE_HSI) \|\| \
emilmont	77:869cf507173a	324	((SOURCE) == RCC_SYSCLKSOURCE_HSE) \|\| \
emilmont	77:869cf507173a	325	((SOURCE) == RCC_SYSCLKSOURCE_PLLCLK))
emilmont	77:869cf507173a	326	/**
emilmont	77:869cf507173a	327	* @}
emilmont	77:869cf507173a	328	*/
emilmont	77:869cf507173a	329
emilmont	77:869cf507173a	330	/** @defgroup RCC_AHB_Clock_Source
emilmont	77:869cf507173a	331	* @{
emilmont	77:869cf507173a	332	*/
emilmont	77:869cf507173a	333	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
emilmont	77:869cf507173a	334	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
emilmont	77:869cf507173a	335	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
emilmont	77:869cf507173a	336	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
emilmont	77:869cf507173a	337	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
emilmont	77:869cf507173a	338	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
emilmont	77:869cf507173a	339	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
emilmont	77:869cf507173a	340	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
emilmont	77:869cf507173a	341	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
emilmont	77:869cf507173a	342
emilmont	77:869cf507173a	343	#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_DIV1) \|\| ((HCLK) == RCC_SYSCLK_DIV2) \|\| \
emilmont	77:869cf507173a	344	((HCLK) == RCC_SYSCLK_DIV4) \|\| ((HCLK) == RCC_SYSCLK_DIV8) \|\| \
emilmont	77:869cf507173a	345	((HCLK) == RCC_SYSCLK_DIV16) \|\| ((HCLK) == RCC_SYSCLK_DIV64) \|\| \
emilmont	77:869cf507173a	346	((HCLK) == RCC_SYSCLK_DIV128) \|\| ((HCLK) == RCC_SYSCLK_DIV256) \|\| \
emilmont	77:869cf507173a	347	((HCLK) == RCC_SYSCLK_DIV512))
emilmont	77:869cf507173a	348	/**
emilmont	77:869cf507173a	349	* @}
emilmont	77:869cf507173a	350	*/
emilmont	77:869cf507173a	351
emilmont	77:869cf507173a	352	/** @defgroup RCC_APB1_APB2_Clock_Source
emilmont	77:869cf507173a	353	* @{
emilmont	77:869cf507173a	354	*/
emilmont	77:869cf507173a	355	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1
emilmont	77:869cf507173a	356	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2
emilmont	77:869cf507173a	357	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4
emilmont	77:869cf507173a	358	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8
emilmont	77:869cf507173a	359	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
emilmont	77:869cf507173a	360
emilmont	77:869cf507173a	361	#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_DIV1) \|\| ((PCLK) == RCC_HCLK_DIV2) \|\| \
emilmont	77:869cf507173a	362	((PCLK) == RCC_HCLK_DIV4) \|\| ((PCLK) == RCC_HCLK_DIV8) \|\| \
emilmont	77:869cf507173a	363	((PCLK) == RCC_HCLK_DIV16))
emilmont	77:869cf507173a	364	/**
emilmont	77:869cf507173a	365	* @}
emilmont	77:869cf507173a	366	*/
emilmont	77:869cf507173a	367
emilmont	77:869cf507173a	368	/** @defgroup RCC_RTC_Clock_Source
emilmont	77:869cf507173a	369	* @{
emilmont	77:869cf507173a	370	*/
emilmont	77:869cf507173a	371	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100)
emilmont	77:869cf507173a	372	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200)
emilmont	77:869cf507173a	373	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300)
emilmont	77:869cf507173a	374	#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300)
emilmont	77:869cf507173a	375	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300)
emilmont	77:869cf507173a	376	#define RCC_RTCCLKSOURCE_HSE_DIV5 ((uint32_t)0x00050300)
emilmont	77:869cf507173a	377	#define RCC_RTCCLKSOURCE_HSE_DIV6 ((uint32_t)0x00060300)
emilmont	77:869cf507173a	378	#define RCC_RTCCLKSOURCE_HSE_DIV7 ((uint32_t)0x00070300)
emilmont	77:869cf507173a	379	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)0x00080300)
emilmont	77:869cf507173a	380	#define RCC_RTCCLKSOURCE_HSE_DIV9 ((uint32_t)0x00090300)
emilmont	77:869cf507173a	381	#define RCC_RTCCLKSOURCE_HSE_DIV10 ((uint32_t)0x000A0300)
emilmont	77:869cf507173a	382	#define RCC_RTCCLKSOURCE_HSE_DIV11 ((uint32_t)0x000B0300)
emilmont	77:869cf507173a	383	#define RCC_RTCCLKSOURCE_HSE_DIV12 ((uint32_t)0x000C0300)
emilmont	77:869cf507173a	384	#define RCC_RTCCLKSOURCE_HSE_DIV13 ((uint32_t)0x000D0300)
emilmont	77:869cf507173a	385	#define RCC_RTCCLKSOURCE_HSE_DIV14 ((uint32_t)0x000E0300)
emilmont	77:869cf507173a	386	#define RCC_RTCCLKSOURCE_HSE_DIV15 ((uint32_t)0x000F0300)
emilmont	77:869cf507173a	387	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)0x00100300)
emilmont	77:869cf507173a	388	#define RCC_RTCCLKSOURCE_HSE_DIV17 ((uint32_t)0x00110300)
emilmont	77:869cf507173a	389	#define RCC_RTCCLKSOURCE_HSE_DIV18 ((uint32_t)0x00120300)
emilmont	77:869cf507173a	390	#define RCC_RTCCLKSOURCE_HSE_DIV19 ((uint32_t)0x00130300)
emilmont	77:869cf507173a	391	#define RCC_RTCCLKSOURCE_HSE_DIV20 ((uint32_t)0x00140300)
emilmont	77:869cf507173a	392	#define RCC_RTCCLKSOURCE_HSE_DIV21 ((uint32_t)0x00150300)
emilmont	77:869cf507173a	393	#define RCC_RTCCLKSOURCE_HSE_DIV22 ((uint32_t)0x00160300)
emilmont	77:869cf507173a	394	#define RCC_RTCCLKSOURCE_HSE_DIV23 ((uint32_t)0x00170300)
emilmont	77:869cf507173a	395	#define RCC_RTCCLKSOURCE_HSE_DIV24 ((uint32_t)0x00180300)
emilmont	77:869cf507173a	396	#define RCC_RTCCLKSOURCE_HSE_DIV25 ((uint32_t)0x00190300)
emilmont	77:869cf507173a	397	#define RCC_RTCCLKSOURCE_HSE_DIV26 ((uint32_t)0x001A0300)
emilmont	77:869cf507173a	398	#define RCC_RTCCLKSOURCE_HSE_DIV27 ((uint32_t)0x001B0300)
emilmont	77:869cf507173a	399	#define RCC_RTCCLKSOURCE_HSE_DIV28 ((uint32_t)0x001C0300)
emilmont	77:869cf507173a	400	#define RCC_RTCCLKSOURCE_HSE_DIV29 ((uint32_t)0x001D0300)
emilmont	77:869cf507173a	401	#define RCC_RTCCLKSOURCE_HSE_DIV30 ((uint32_t)0x001E0300)
emilmont	77:869cf507173a	402	#define RCC_RTCCLKSOURCE_HSE_DIV31 ((uint32_t)0x001F0300)
emilmont	77:869cf507173a	403	/**
emilmont	77:869cf507173a	404	* @}
emilmont	77:869cf507173a	405	*/
emilmont	77:869cf507173a	406
emilmont	77:869cf507173a	407	/** @defgroup RCC_I2S_Clock_Source
emilmont	77:869cf507173a	408	* @{
emilmont	77:869cf507173a	409	*/
emilmont	77:869cf507173a	410	#define RCC_I2SCLKSOURCE_PLLI2S ((uint32_t)0x00000000)
emilmont	77:869cf507173a	411	#define RCC_I2SCLKSOURCE_EXT ((uint32_t)0x00000001)
emilmont	77:869cf507173a	412	/**
emilmont	77:869cf507173a	413	* @}
emilmont	77:869cf507173a	414	*/
emilmont	77:869cf507173a	415
emilmont	77:869cf507173a	416	/** @defgroup RCC_MCO_Index
emilmont	77:869cf507173a	417	* @{
emilmont	77:869cf507173a	418	*/
emilmont	77:869cf507173a	419	#define RCC_MCO1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	420	#define RCC_MCO2 ((uint32_t)0x00000001)
emilmont	77:869cf507173a	421
emilmont	77:869cf507173a	422	#define IS_RCC_MCO(MCOx) (((MCOx) == RCC_MCO1) \|\| ((MCOx) == RCC_MCO2))
emilmont	77:869cf507173a	423	/**
emilmont	77:869cf507173a	424	* @}
emilmont	77:869cf507173a	425	*/
emilmont	77:869cf507173a	426
emilmont	77:869cf507173a	427	/** @defgroup RCC_MCO1_Clock_Source
emilmont	77:869cf507173a	428	* @{
emilmont	77:869cf507173a	429	*/
emilmont	77:869cf507173a	430	#define RCC_MCO1SOURCE_HSI ((uint32_t)0x00000000)
emilmont	77:869cf507173a	431	#define RCC_MCO1SOURCE_LSE RCC_CFGR_MCO1_0
emilmont	77:869cf507173a	432	#define RCC_MCO1SOURCE_HSE RCC_CFGR_MCO1_1
emilmont	77:869cf507173a	433	#define RCC_MCO1SOURCE_PLLCLK RCC_CFGR_MCO1
emilmont	77:869cf507173a	434
emilmont	77:869cf507173a	435	#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1SOURCE_HSI) \|\| ((SOURCE) == RCC_MCO1SOURCE_LSE) \|\| \
emilmont	77:869cf507173a	436	((SOURCE) == RCC_MCO1SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO1SOURCE_PLLCLK))
emilmont	77:869cf507173a	437	/**
emilmont	77:869cf507173a	438	* @}
emilmont	77:869cf507173a	439	*/
emilmont	77:869cf507173a	440
emilmont	77:869cf507173a	441	/** @defgroup RCC_MCO2_Clock_Source
emilmont	77:869cf507173a	442	* @{
emilmont	77:869cf507173a	443	*/
emilmont	77:869cf507173a	444	#define RCC_MCO2SOURCE_SYSCLK ((uint32_t)0x00000000)
emilmont	77:869cf507173a	445	#define RCC_MCO2SOURCE_PLLI2SCLK RCC_CFGR_MCO2_0
emilmont	77:869cf507173a	446	#define RCC_MCO2SOURCE_HSE RCC_CFGR_MCO2_1
emilmont	77:869cf507173a	447	#define RCC_MCO2SOURCE_PLLCLK RCC_CFGR_MCO2
emilmont	77:869cf507173a	448
emilmont	77:869cf507173a	449	#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2SOURCE_SYSCLK) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLI2SCLK)\|\| \
emilmont	77:869cf507173a	450	((SOURCE) == RCC_MCO2SOURCE_HSE) \|\| ((SOURCE) == RCC_MCO2SOURCE_PLLCLK))
emilmont	77:869cf507173a	451	/**
emilmont	77:869cf507173a	452	* @}
emilmont	77:869cf507173a	453	*/
emilmont	77:869cf507173a	454
emilmont	77:869cf507173a	455	/** @defgroup RCC_MCOx_Clock_Prescaler
emilmont	77:869cf507173a	456	* @{
emilmont	77:869cf507173a	457	*/
emilmont	77:869cf507173a	458	#define RCC_MCODIV_1 ((uint32_t)0x00000000)
emilmont	77:869cf507173a	459	#define RCC_MCODIV_2 RCC_CFGR_MCO1PRE_2
emilmont	77:869cf507173a	460	#define RCC_MCODIV_3 ((uint32_t)RCC_CFGR_MCO1PRE_0 \| RCC_CFGR_MCO1PRE_2)
emilmont	77:869cf507173a	461	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO1PRE_1 \| RCC_CFGR_MCO1PRE_2)
emilmont	77:869cf507173a	462	#define RCC_MCODIV_5 RCC_CFGR_MCO1PRE
emilmont	77:869cf507173a	463
emilmont	77:869cf507173a	464	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) \|\| ((DIV) == RCC_MCODIV_2) \|\| \
emilmont	77:869cf507173a	465	((DIV) == RCC_MCODIV_3) \|\| ((DIV) == RCC_MCODIV_4) \|\| \
emilmont	77:869cf507173a	466	((DIV) == RCC_MCODIV_5))
emilmont	77:869cf507173a	467	/**
emilmont	77:869cf507173a	468	* @}
emilmont	77:869cf507173a	469	*/
emilmont	77:869cf507173a	470
emilmont	77:869cf507173a	471	/** @defgroup RCC_Interrupt
emilmont	77:869cf507173a	472	* @{
emilmont	77:869cf507173a	473	*/
emilmont	77:869cf507173a	474	#define RCC_IT_LSIRDY ((uint8_t)0x01)
emilmont	77:869cf507173a	475	#define RCC_IT_LSERDY ((uint8_t)0x02)
emilmont	77:869cf507173a	476	#define RCC_IT_HSIRDY ((uint8_t)0x04)
emilmont	77:869cf507173a	477	#define RCC_IT_HSERDY ((uint8_t)0x08)
emilmont	77:869cf507173a	478	#define RCC_IT_PLLRDY ((uint8_t)0x10)
emilmont	77:869cf507173a	479	#define RCC_IT_PLLI2SRDY ((uint8_t)0x20)
emilmont	77:869cf507173a	480	#define RCC_IT_CSS ((uint8_t)0x80)
emilmont	77:869cf507173a	481	/**
emilmont	77:869cf507173a	482	* @}
emilmont	77:869cf507173a	483	*/
emilmont	77:869cf507173a	484
emilmont	77:869cf507173a	485	/** @defgroup RCC_Flag
emilmont	77:869cf507173a	486	* Elements values convention: 0XXYYYYYb
emilmont	77:869cf507173a	487	* - YYYYY : Flag position in the register
emilmont	77:869cf507173a	488	* - 0XX : Register index
emilmont	77:869cf507173a	489	* - 01: CR register
emilmont	77:869cf507173a	490	* - 10: BDCR register
emilmont	77:869cf507173a	491	* - 11: CSR register
emilmont	77:869cf507173a	492	* @{
emilmont	77:869cf507173a	493	*/
emilmont	77:869cf507173a	494	/* Flags in the CR register */
emilmont	77:869cf507173a	495	#define RCC_FLAG_HSIRDY ((uint8_t)0x21)
emilmont	77:869cf507173a	496	#define RCC_FLAG_HSERDY ((uint8_t)0x31)
emilmont	77:869cf507173a	497	#define RCC_FLAG_PLLRDY ((uint8_t)0x39)
emilmont	77:869cf507173a	498	#define RCC_FLAG_PLLI2SRDY ((uint8_t)0x3B)
emilmont	77:869cf507173a	499
emilmont	77:869cf507173a	500	/* Flags in the BDCR register */
emilmont	77:869cf507173a	501	#define RCC_FLAG_LSERDY ((uint8_t)0x41)
emilmont	77:869cf507173a	502
emilmont	77:869cf507173a	503	/* Flags in the CSR register */
emilmont	77:869cf507173a	504	#define RCC_FLAG_LSIRDY ((uint8_t)0x61)
emilmont	77:869cf507173a	505	#define RCC_FLAG_BORRST ((uint8_t)0x79)
emilmont	77:869cf507173a	506	#define RCC_FLAG_PINRST ((uint8_t)0x7A)
emilmont	77:869cf507173a	507	#define RCC_FLAG_PORRST ((uint8_t)0x7B)
emilmont	77:869cf507173a	508	#define RCC_FLAG_SFTRST ((uint8_t)0x7C)
emilmont	77:869cf507173a	509	#define RCC_FLAG_IWDGRST ((uint8_t)0x7D)
emilmont	77:869cf507173a	510	#define RCC_FLAG_WWDGRST ((uint8_t)0x7E)
emilmont	77:869cf507173a	511	#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
emilmont	77:869cf507173a	512
emilmont	77:869cf507173a	513	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
emilmont	77:869cf507173a	514	/**
emilmont	77:869cf507173a	515	* @}
emilmont	77:869cf507173a	516	*/
emilmont	77:869cf507173a	517
emilmont	77:869cf507173a	518	/**
emilmont	77:869cf507173a	519	* @}
emilmont	77:869cf507173a	520	*/
emilmont	77:869cf507173a	521	/* Exported macro ------------------------------------------------------------*/
emilmont	77:869cf507173a	522
emilmont	77:869cf507173a	523	/** @brief Enable or disable the AHB1 peripheral clock.
emilmont	77:869cf507173a	524	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	525	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	526	* using it.
emilmont	77:869cf507173a	527	*/
emilmont	77:869cf507173a	528	#define __GPIOA_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOAEN))
emilmont	77:869cf507173a	529	#define __GPIOB_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOBEN))
emilmont	77:869cf507173a	530	#define __GPIOC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOCEN))
emilmont	77:869cf507173a	531	#define __GPIOD_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIODEN))
emilmont	77:869cf507173a	532	#define __GPIOE_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOEEN))
emilmont	77:869cf507173a	533	#define __GPIOH_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_GPIOHEN))
emilmont	77:869cf507173a	534	#define __CRC_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CRCEN))
emilmont	77:869cf507173a	535	#define __BKPSRAM_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_BKPSRAMEN))
emilmont	77:869cf507173a	536	#define __CCMDATARAMEN_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_CCMDATARAMEN))
emilmont	77:869cf507173a	537	#define __DMA1_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA1EN))
emilmont	77:869cf507173a	538	#define __DMA2_CLK_ENABLE() (RCC->AHB1ENR \|= (RCC_AHB1ENR_DMA2EN))
emilmont	77:869cf507173a	539
emilmont	77:869cf507173a	540	#define __GPIOA_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOAEN))
emilmont	77:869cf507173a	541	#define __GPIOB_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOBEN))
emilmont	77:869cf507173a	542	#define __GPIOC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOCEN))
emilmont	77:869cf507173a	543	#define __GPIOD_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIODEN))
emilmont	77:869cf507173a	544	#define __GPIOE_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOEEN))
emilmont	77:869cf507173a	545	#define __GPIOH_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_GPIOHEN))
emilmont	77:869cf507173a	546	#define __CRC_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CRCEN))
emilmont	77:869cf507173a	547	#define __BKPSRAM_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_BKPSRAMEN))
emilmont	77:869cf507173a	548	#define __CCMDATARAMEN_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_CCMDATARAMEN))
emilmont	77:869cf507173a	549	#define __DMA1_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA1EN))
emilmont	77:869cf507173a	550	#define __DMA2_CLK_DISABLE() (RCC->AHB1ENR &= ~(RCC_AHB1ENR_DMA2EN))
emilmont	77:869cf507173a	551
emilmont	77:869cf507173a	552	/** @brief Enable or disable the AHB2 peripheral clock.
emilmont	77:869cf507173a	553	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	554	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	555	* using it.
emilmont	77:869cf507173a	556	*/
emilmont	77:869cf507173a	557	#define __USB_OTG_FS_CLK_ENABLE() do {(RCC->AHB2ENR \|= (RCC_AHB2ENR_OTGFSEN));\
emilmont	77:869cf507173a	558	__SYSCFG_CLK_ENABLE();\
emilmont	77:869cf507173a	559	}while(0)
emilmont	77:869cf507173a	560
emilmont	77:869cf507173a	561
emilmont	77:869cf507173a	562	#define __USB_OTG_FS_CLK_DISABLE() do { (RCC->AHB2ENR &= ~(RCC_AHB2ENR_OTGFSEN));\
emilmont	77:869cf507173a	563	__SYSCFG_CLK_DISABLE();\
emilmont	77:869cf507173a	564	}while(0)
emilmont	77:869cf507173a	565
emilmont	77:869cf507173a	566	#define __RNG_CLK_ENABLE() (RCC->AHB2ENR \|= (RCC_AHB2ENR_RNGEN))
emilmont	77:869cf507173a	567	#define __RNG_CLK_DISABLE() (RCC->AHB2ENR &= ~(RCC_AHB2ENR_RNGEN))
emilmont	77:869cf507173a	568	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
emilmont	77:869cf507173a	569	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	570	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	571	* using it.
emilmont	77:869cf507173a	572	*/
emilmont	77:869cf507173a	573	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
emilmont	77:869cf507173a	574	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
emilmont	77:869cf507173a	575	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
emilmont	77:869cf507173a	576	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
emilmont	77:869cf507173a	577	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
emilmont	77:869cf507173a	578	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
emilmont	77:869cf507173a	579	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
emilmont	77:869cf507173a	580	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
emilmont	77:869cf507173a	581	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
emilmont	77:869cf507173a	582	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
emilmont	77:869cf507173a	583	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
emilmont	77:869cf507173a	584	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
emilmont	77:869cf507173a	585
emilmont	77:869cf507173a	586	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
emilmont	77:869cf507173a	587	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
emilmont	77:869cf507173a	588	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
emilmont	77:869cf507173a	589	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
emilmont	77:869cf507173a	590	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
emilmont	77:869cf507173a	591	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
emilmont	77:869cf507173a	592	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
emilmont	77:869cf507173a	593	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
emilmont	77:869cf507173a	594	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
emilmont	77:869cf507173a	595	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
emilmont	77:869cf507173a	596	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
emilmont	77:869cf507173a	597	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
emilmont	77:869cf507173a	598
emilmont	77:869cf507173a	599	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
emilmont	77:869cf507173a	600	* @note After reset, the peripheral clock (used for registers read/write access)
emilmont	77:869cf507173a	601	* is disabled and the application software has to enable this clock before
emilmont	77:869cf507173a	602	* using it.
emilmont	77:869cf507173a	603	*/
emilmont	77:869cf507173a	604	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
emilmont	77:869cf507173a	605	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
emilmont	77:869cf507173a	606	#define __USART6_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART6EN))
emilmont	77:869cf507173a	607	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
emilmont	77:869cf507173a	608	#define __SDIO_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDIOEN))
emilmont	77:869cf507173a	609	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
emilmont	77:869cf507173a	610	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
emilmont	77:869cf507173a	611	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
emilmont	77:869cf507173a	612	#define __TIM9_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM9EN))
emilmont	77:869cf507173a	613	#define __TIM10_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM10EN))
emilmont	77:869cf507173a	614	#define __TIM11_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM11EN))
emilmont	77:869cf507173a	615
emilmont	77:869cf507173a	616	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
emilmont	77:869cf507173a	617	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
emilmont	77:869cf507173a	618	#define __USART6_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART6EN))
emilmont	77:869cf507173a	619	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
emilmont	77:869cf507173a	620	#define __SDIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDIOEN))
emilmont	77:869cf507173a	621	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
emilmont	77:869cf507173a	622	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
emilmont	77:869cf507173a	623	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
emilmont	77:869cf507173a	624	#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
emilmont	77:869cf507173a	625	#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
emilmont	77:869cf507173a	626	#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
emilmont	77:869cf507173a	627
emilmont	77:869cf507173a	628	/** @brief Force or release AHB1 peripheral reset.
emilmont	77:869cf507173a	629	*/
emilmont	77:869cf507173a	630	#define __AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFF)
emilmont	77:869cf507173a	631	#define __GPIOA_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOARST))
emilmont	77:869cf507173a	632	#define __GPIOB_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOBRST))
emilmont	77:869cf507173a	633	#define __GPIOC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOCRST))
emilmont	77:869cf507173a	634	#define __GPIOD_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIODRST))
emilmont	77:869cf507173a	635	#define __GPIOE_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOERST))
emilmont	77:869cf507173a	636	#define __GPIOH_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_GPIOHRST))
emilmont	77:869cf507173a	637	#define __CRC_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_CRCRST))
emilmont	77:869cf507173a	638	#define __DMA1_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA1RST))
emilmont	77:869cf507173a	639	#define __DMA2_FORCE_RESET() (RCC->AHB1RSTR \|= (RCC_AHB1RSTR_DMA2RST))
emilmont	77:869cf507173a	640
emilmont	77:869cf507173a	641	#define __AHB1_RELEASE_RESET() (RCC->AHB1RSTR = 0x00)
emilmont	77:869cf507173a	642	#define __GPIOA_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOARST))
emilmont	77:869cf507173a	643	#define __GPIOB_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOBRST))
emilmont	77:869cf507173a	644	#define __GPIOC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOCRST))
emilmont	77:869cf507173a	645	#define __GPIOD_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIODRST))
emilmont	77:869cf507173a	646	#define __GPIOE_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOERST))
emilmont	77:869cf507173a	647	#define __GPIOF_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOFRST))
emilmont	77:869cf507173a	648	#define __GPIOG_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOGRST))
emilmont	77:869cf507173a	649	#define __GPIOH_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOHRST))
emilmont	77:869cf507173a	650	#define __GPIOI_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_GPIOIRST))
emilmont	77:869cf507173a	651	#define __CRC_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_CRCRST))
emilmont	77:869cf507173a	652	#define __DMA1_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA1RST))
emilmont	77:869cf507173a	653	#define __DMA2_RELEASE_RESET() (RCC->AHB1RSTR &= ~(RCC_AHB1RSTR_DMA2RST))
emilmont	77:869cf507173a	654
emilmont	77:869cf507173a	655	/** @brief Force or release AHB2 peripheral reset.
emilmont	77:869cf507173a	656	*/
emilmont	77:869cf507173a	657	#define __AHB2_FORCE_RESET() (RCC->AHB2RSTR = 0xFFFFFFFF)
emilmont	77:869cf507173a	658	#define __OTGFS_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_OTGFSRST))
emilmont	77:869cf507173a	659
emilmont	77:869cf507173a	660	#define __AHB2_RELEASE_RESET() (RCC->AHB2RSTR = 0x00)
emilmont	77:869cf507173a	661	#define __OTGFS_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_OTGFSRST))
emilmont	77:869cf507173a	662
emilmont	77:869cf507173a	663	#define __RNG_FORCE_RESET() (RCC->AHB2RSTR \|= (RCC_AHB2RSTR_RNGRST))
emilmont	77:869cf507173a	664	#define __RNG_RELEASE_RESET() (RCC->AHB2RSTR &= ~(RCC_AHB2RSTR_RNGRST))
emilmont	77:869cf507173a	665
emilmont	77:869cf507173a	666	/** @brief Force or release APB1 peripheral reset.
emilmont	77:869cf507173a	667	*/
emilmont	77:869cf507173a	668	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
emilmont	77:869cf507173a	669	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
emilmont	77:869cf507173a	670	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
emilmont	77:869cf507173a	671	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
emilmont	77:869cf507173a	672	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
emilmont	77:869cf507173a	673	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
emilmont	77:869cf507173a	674	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
emilmont	77:869cf507173a	675	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
emilmont	77:869cf507173a	676	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
emilmont	77:869cf507173a	677	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
emilmont	77:869cf507173a	678	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
emilmont	77:869cf507173a	679	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
emilmont	77:869cf507173a	680	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
emilmont	77:869cf507173a	681
emilmont	77:869cf507173a	682	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
emilmont	77:869cf507173a	683	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
emilmont	77:869cf507173a	684	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
emilmont	77:869cf507173a	685	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
emilmont	77:869cf507173a	686	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
emilmont	77:869cf507173a	687	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
emilmont	77:869cf507173a	688	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
emilmont	77:869cf507173a	689	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
emilmont	77:869cf507173a	690	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
emilmont	77:869cf507173a	691	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
emilmont	77:869cf507173a	692	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
emilmont	77:869cf507173a	693	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
emilmont	77:869cf507173a	694	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
emilmont	77:869cf507173a	695
emilmont	77:869cf507173a	696	/** @brief Force or release APB2 peripheral reset.
emilmont	77:869cf507173a	697	*/
emilmont	77:869cf507173a	698	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
emilmont	77:869cf507173a	699	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
emilmont	77:869cf507173a	700	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
emilmont	77:869cf507173a	701	#define __USART6_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART6RST))
emilmont	77:869cf507173a	702	#define __ADC_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADCRST))
emilmont	77:869cf507173a	703	#define __SDIO_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDIORST))
emilmont	77:869cf507173a	704	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
emilmont	77:869cf507173a	705	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
emilmont	77:869cf507173a	706	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
emilmont	77:869cf507173a	707	#define __TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
emilmont	77:869cf507173a	708	#define __TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
emilmont	77:869cf507173a	709	#define __TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
emilmont	77:869cf507173a	710
emilmont	77:869cf507173a	711	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
emilmont	77:869cf507173a	712	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
emilmont	77:869cf507173a	713	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
emilmont	77:869cf507173a	714	#define __USART6_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART6RST))
emilmont	77:869cf507173a	715	#define __ADC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADCRST))
emilmont	77:869cf507173a	716	#define __SDIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDIORST))
emilmont	77:869cf507173a	717	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
emilmont	77:869cf507173a	718	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
emilmont	77:869cf507173a	719	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
emilmont	77:869cf507173a	720	#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
emilmont	77:869cf507173a	721	#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
emilmont	77:869cf507173a	722	#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
emilmont	77:869cf507173a	723
emilmont	77:869cf507173a	724	/** @brief Force or release AHB3 peripheral reset.
emilmont	77:869cf507173a	725	*/
emilmont	77:869cf507173a	726	#define __AHB3_FORCE_RESET() (RCC->AHB3RSTR = 0xFFFFFFFF)
emilmont	77:869cf507173a	727	#define __AHB3_RELEASE_RESET() (RCC->AHB3RSTR = 0x00)
emilmont	77:869cf507173a	728
emilmont	77:869cf507173a	729	/** @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	730	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	731	* power consumption.
emilmont	77:869cf507173a	732	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	733	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	734	*/
emilmont	77:869cf507173a	735	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOALPEN))
emilmont	77:869cf507173a	736	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOBLPEN))
emilmont	77:869cf507173a	737	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOCLPEN))
emilmont	77:869cf507173a	738	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIODLPEN))
emilmont	77:869cf507173a	739	#define __GPIOE_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOELPEN))
emilmont	77:869cf507173a	740	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_GPIOHLPEN))
emilmont	77:869cf507173a	741	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_CRCLPEN))
emilmont	77:869cf507173a	742	#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_FLITFLPEN))
emilmont	77:869cf507173a	743	#define __SRAM1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_SRAM1LPEN))
emilmont	77:869cf507173a	744	#define __BKPSRAM_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_BKPSRAMLPEN))
emilmont	77:869cf507173a	745	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA1LPEN))
emilmont	77:869cf507173a	746	#define __DMA2_CLK_SLEEP_ENABLE() (RCC->AHB1LPENR \|= (RCC_AHB1LPENR_DMA2LPEN))
emilmont	77:869cf507173a	747
emilmont	77:869cf507173a	748	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOALPEN))
emilmont	77:869cf507173a	749	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOBLPEN))
emilmont	77:869cf507173a	750	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOCLPEN))
emilmont	77:869cf507173a	751	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIODLPEN))
emilmont	77:869cf507173a	752	#define __GPIOE_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOELPEN))
emilmont	77:869cf507173a	753	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_GPIOHLPEN))
emilmont	77:869cf507173a	754	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_CRCLPEN))
emilmont	77:869cf507173a	755	#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_FLITFLPEN))
emilmont	77:869cf507173a	756	#define __SRAM1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_SRAM1LPEN))
emilmont	77:869cf507173a	757	#define __BKPSRAM_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_BKPSRAMLPEN))
emilmont	77:869cf507173a	758	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA1LPEN))
emilmont	77:869cf507173a	759	#define __DMA2_CLK_SLEEP_DISABLE() (RCC->AHB1LPENR &= ~(RCC_AHB1LPENR_DMA2LPEN))
emilmont	77:869cf507173a	760
emilmont	77:869cf507173a	761	/** @brief Enable or disable the AHB2 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	762	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	763	* power consumption.
emilmont	77:869cf507173a	764	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	765	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	766	*/
emilmont	77:869cf507173a	767	#define __OTGFS_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_OTGFSLPEN))
emilmont	77:869cf507173a	768
emilmont	77:869cf507173a	769	#define __OTGFS_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_OTGFSLPEN))
emilmont	77:869cf507173a	770
emilmont	77:869cf507173a	771	#define __RNG_CLK_SLEEP_ENABLE() (RCC->AHB2LPENR \|= (RCC_AHB2LPENR_RNGLPEN))
emilmont	77:869cf507173a	772	#define __RNG_CLK_SLEEP_DISABLE() (RCC->AHB2LPENR &= ~(RCC_AHB2LPENR_RNGLPEN))
emilmont	77:869cf507173a	773
emilmont	77:869cf507173a	774	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	775	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	776	* power consumption.
emilmont	77:869cf507173a	777	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	778	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	779	*/
emilmont	77:869cf507173a	780	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
emilmont	77:869cf507173a	781	#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
emilmont	77:869cf507173a	782	#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
emilmont	77:869cf507173a	783	#define __TIM5_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM5LPEN))
emilmont	77:869cf507173a	784	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
emilmont	77:869cf507173a	785	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
emilmont	77:869cf507173a	786	#define __SPI3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI3LPEN))
emilmont	77:869cf507173a	787	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
emilmont	77:869cf507173a	788	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
emilmont	77:869cf507173a	789	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
emilmont	77:869cf507173a	790	#define __I2C3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C3LPEN))
emilmont	77:869cf507173a	791	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
emilmont	77:869cf507173a	792
emilmont	77:869cf507173a	793	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
emilmont	77:869cf507173a	794	#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
emilmont	77:869cf507173a	795	#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
emilmont	77:869cf507173a	796	#define __TIM5_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM5LPEN))
emilmont	77:869cf507173a	797	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
emilmont	77:869cf507173a	798	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
emilmont	77:869cf507173a	799	#define __SPI3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI3LPEN))
emilmont	77:869cf507173a	800	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
emilmont	77:869cf507173a	801	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
emilmont	77:869cf507173a	802	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
emilmont	77:869cf507173a	803	#define __I2C3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C3LPEN))
emilmont	77:869cf507173a	804	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
emilmont	77:869cf507173a	805
emilmont	77:869cf507173a	806	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
emilmont	77:869cf507173a	807	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
emilmont	77:869cf507173a	808	* power consumption.
emilmont	77:869cf507173a	809	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
emilmont	77:869cf507173a	810	* @note By default, all peripheral clocks are enabled during SLEEP mode.
emilmont	77:869cf507173a	811	*/
emilmont	77:869cf507173a	812	#define __TIM1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM1LPEN))
emilmont	77:869cf507173a	813	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
emilmont	77:869cf507173a	814	#define __USART6_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART6LPEN))
emilmont	77:869cf507173a	815	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
emilmont	77:869cf507173a	816	#define __SDIO_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SDIOLPEN))
emilmont	77:869cf507173a	817	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
emilmont	77:869cf507173a	818	#define __SPI4_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI4LPEN))
emilmont	77:869cf507173a	819	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
emilmont	77:869cf507173a	820	#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
emilmont	77:869cf507173a	821	#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
emilmont	77:869cf507173a	822	#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
emilmont	77:869cf507173a	823
emilmont	77:869cf507173a	824	#define __TIM1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM1LPEN))
emilmont	77:869cf507173a	825	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
emilmont	77:869cf507173a	826	#define __USART6_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART6LPEN))
emilmont	77:869cf507173a	827	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
emilmont	77:869cf507173a	828	#define __SDIO_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SDIOLPEN))
emilmont	77:869cf507173a	829	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
emilmont	77:869cf507173a	830	#define __SPI4_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI4LPEN))
emilmont	77:869cf507173a	831	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
emilmont	77:869cf507173a	832	#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
emilmont	77:869cf507173a	833	#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
emilmont	77:869cf507173a	834	#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
emilmont	77:869cf507173a	835
emilmont	77:869cf507173a	836	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
emilmont	77:869cf507173a	837	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
emilmont	77:869cf507173a	838	* It is used (enabled by hardware) as system clock source after startup
emilmont	77:869cf507173a	839	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
emilmont	77:869cf507173a	840	* of the HSE used directly or indirectly as system clock (if the Clock
emilmont	77:869cf507173a	841	* Security System CSS is enabled).
emilmont	77:869cf507173a	842	* @note HSI can not be stopped if it is used as system clock source. In this case,
emilmont	77:869cf507173a	843	* you have to select another source of the system clock then stop the HSI.
emilmont	77:869cf507173a	844	* @note After enabling the HSI, the application software should wait on HSIRDY
emilmont	77:869cf507173a	845	* flag to be set indicating that HSI clock is stable and can be used as
emilmont	77:869cf507173a	846	* system clock source.
emilmont	77:869cf507173a	847	* This parameter can be: ENABLE or DISABLE.
emilmont	77:869cf507173a	848	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
emilmont	77:869cf507173a	849	* clock cycles.
emilmont	77:869cf507173a	850	*/
emilmont	77:869cf507173a	851	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) CR_HSION_BB = ENABLE)
emilmont	77:869cf507173a	852	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) CR_HSION_BB = DISABLE)
emilmont	77:869cf507173a	853
emilmont	77:869cf507173a	854	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
emilmont	77:869cf507173a	855	* @note The calibration is used to compensate for the variations in voltage
emilmont	77:869cf507173a	856	* and temperature that influence the frequency of the internal HSI RC.
emilmont	77:869cf507173a	857	* @param __HSICalibrationValue__: specifies the calibration trimming value.
emilmont	77:869cf507173a	858	* This parameter must be a number between 0 and 0x1F.
emilmont	77:869cf507173a	859	*/
emilmont	77:869cf507173a	860	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
emilmont	77:869cf507173a	861	RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
emilmont	77:869cf507173a	862
emilmont	77:869cf507173a	863	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
emilmont	77:869cf507173a	864	* @note After enabling the LSI, the application software should wait on
emilmont	77:869cf507173a	865	* LSIRDY flag to be set indicating that LSI clock is stable and can
emilmont	77:869cf507173a	866	* be used to clock the IWDG and/or the RTC.
emilmont	77:869cf507173a	867	* @note LSI can not be disabled if the IWDG is running.
emilmont	77:869cf507173a	868	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
emilmont	77:869cf507173a	869	* clock cycles.
emilmont	77:869cf507173a	870	*/
emilmont	77:869cf507173a	871	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) CSR_LSION_BB = ENABLE)
emilmont	77:869cf507173a	872	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) CSR_LSION_BB = DISABLE)
emilmont	77:869cf507173a	873
emilmont	77:869cf507173a	874	/**
emilmont	77:869cf507173a	875	* @brief Macro to configure the External High Speed oscillator (HSE).
emilmont	77:869cf507173a	876	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
emilmont	77:869cf507173a	877	* software should wait on HSERDY flag to be set indicating that HSE clock
emilmont	77:869cf507173a	878	* is stable and can be used to clock the PLL and/or system clock.
emilmont	77:869cf507173a	879	* @note HSE state can not be changed if it is used directly or through the
emilmont	77:869cf507173a	880	* PLL as system clock. In this case, you have to select another source
emilmont	77:869cf507173a	881	* of the system clock then change the HSE state (ex. disable it).
emilmont	77:869cf507173a	882	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
emilmont	77:869cf507173a	883	* @note This function reset the CSSON bit, so if the clock security system(CSS)
emilmont	77:869cf507173a	884	* was previously enabled you have to enable it again after calling this
emilmont	77:869cf507173a	885	* function.
emilmont	77:869cf507173a	886	* @param __STATE__: specifies the new state of the HSE.
emilmont	77:869cf507173a	887	* This parameter can be one of the following values:
emilmont	77:869cf507173a	888	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
emilmont	77:869cf507173a	889	* 6 HSE oscillator clock cycles.
emilmont	77:869cf507173a	890	* @arg RCC_HSE_ON: turn ON the HSE oscillator.
emilmont	77:869cf507173a	891	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock.
emilmont	77:869cf507173a	892	*/
emilmont	77:869cf507173a	893	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t ) CR_BYTE2_ADDRESS = (__STATE__))
emilmont	77:869cf507173a	894
emilmont	77:869cf507173a	895	/**
emilmont	77:869cf507173a	896	* @brief Macro to configure the External Low Speed oscillator (LSE).
emilmont	77:869cf507173a	897	* @note As the LSE is in the Backup domain and write access is denied to
emilmont	77:869cf507173a	898	* this domain after reset, you have to enable write access using
emilmont	77:869cf507173a	899	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
emilmont	77:869cf507173a	900	* (to be done once after reset).
emilmont	77:869cf507173a	901	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
emilmont	77:869cf507173a	902	* software should wait on LSERDY flag to be set indicating that LSE clock
emilmont	77:869cf507173a	903	* is stable and can be used to clock the RTC.
emilmont	77:869cf507173a	904	* @param __STATE__: specifies the new state of the LSE.
emilmont	77:869cf507173a	905	* This parameter can be one of the following values:
emilmont	77:869cf507173a	906	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
emilmont	77:869cf507173a	907	* 6 LSE oscillator clock cycles.
emilmont	77:869cf507173a	908	* @arg RCC_LSE_ON: turn ON the LSE oscillator.
emilmont	77:869cf507173a	909	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock.
emilmont	77:869cf507173a	910	*/
emilmont	77:869cf507173a	911	#define __HAL_RCC_LSE_CONFIG(__STATE__) ((__IO uint8_t ) BDCR_BYTE0_ADDRESS = (__STATE__))
emilmont	77:869cf507173a	912
emilmont	77:869cf507173a	913	/** @brief Macros to enable or disable the the RTC clock.
emilmont	77:869cf507173a	914	* @note These macros must be used only after the RTC clock source was selected.
emilmont	77:869cf507173a	915	*/
emilmont	77:869cf507173a	916	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = ENABLE)
emilmont	77:869cf507173a	917	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) BDCR_RTCEN_BB = DISABLE)
emilmont	77:869cf507173a	918
emilmont	77:869cf507173a	919	/** @brief Macros to configure the RTC clock (RTCCLK).
emilmont	77:869cf507173a	920	* @note As the RTC clock configuration bits are in the Backup domain and write
emilmont	77:869cf507173a	921	* access is denied to this domain after reset, you have to enable write
emilmont	77:869cf507173a	922	* access using the Power Backup Access macro before to configure
emilmont	77:869cf507173a	923	* the RTC clock source (to be done once after reset).
emilmont	77:869cf507173a	924	* @note Once the RTC clock is configured it can't be changed unless the
emilmont	77:869cf507173a	925	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
emilmont	77:869cf507173a	926	* a Power On Reset (POR).
emilmont	77:869cf507173a	927	* @param __RTCCLKSource__: specifies the RTC clock source.
emilmont	77:869cf507173a	928	* This parameter can be one of the following values:
emilmont	77:869cf507173a	929	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
emilmont	77:869cf507173a	930	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
emilmont	77:869cf507173a	931	* @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
emilmont	77:869cf507173a	932	* as RTC clock, where x:[2,31]
emilmont	77:869cf507173a	933	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
emilmont	77:869cf507173a	934	* work in STOP and STANDBY modes, and can be used as wakeup source.
emilmont	77:869cf507173a	935	* However, when the HSE clock is used as RTC clock source, the RTC
emilmont	77:869cf507173a	936	* cannot be used in STOP and STANDBY modes.
emilmont	77:869cf507173a	937	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
emilmont	77:869cf507173a	938	* RTC clock source).
emilmont	77:869cf507173a	939	*/
emilmont	77:869cf507173a	940	#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
bogdanm	81:7d30d6019079	941	MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
bogdanm	81:7d30d6019079	942
emilmont	77:869cf507173a	943	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
emilmont	77:869cf507173a	944	RCC->BDCR \|= ((__RTCCLKSource__) & 0x00000FFF); \
emilmont	77:869cf507173a	945	} while (0)
emilmont	77:869cf507173a	946
emilmont	77:869cf507173a	947	/** @brief Macros to force or release the Backup domain reset.
emilmont	77:869cf507173a	948	* @note This function resets the RTC peripheral (including the backup registers)
emilmont	77:869cf507173a	949	* and the RTC clock source selection in RCC_CSR register.
emilmont	77:869cf507173a	950	* @note The BKPSRAM is not affected by this reset.
emilmont	77:869cf507173a	951	*/
emilmont	77:869cf507173a	952	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) BDCR_BDRST_BB = ENABLE)
emilmont	77:869cf507173a	953	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) BDCR_BDRST_BB = DISABLE)
emilmont	77:869cf507173a	954
emilmont	77:869cf507173a	955	/** @brief Macros to enable or disable the main PLL.
emilmont	77:869cf507173a	956	* @note After enabling the main PLL, the application software should wait on
emilmont	77:869cf507173a	957	* PLLRDY flag to be set indicating that PLL clock is stable and can
emilmont	77:869cf507173a	958	* be used as system clock source.
emilmont	77:869cf507173a	959	* @note The main PLL can not be disabled if it is used as system clock source
emilmont	77:869cf507173a	960	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
emilmont	77:869cf507173a	961	*/
emilmont	77:869cf507173a	962	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) CR_PLLON_BB = ENABLE)
emilmont	77:869cf507173a	963	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) CR_PLLON_BB = DISABLE)
emilmont	77:869cf507173a	964
emilmont	77:869cf507173a	965	/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
emilmont	77:869cf507173a	966	* @note This function must be used only when the main PLL is disabled.
emilmont	77:869cf507173a	967	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
emilmont	77:869cf507173a	968	* This parameter can be one of the following values:
emilmont	77:869cf507173a	969	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
emilmont	77:869cf507173a	970	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
emilmont	77:869cf507173a	971	* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
emilmont	77:869cf507173a	972	* @param __PLLM__: specifies the division factor for PLL VCO input clock
emilmont	77:869cf507173a	973	* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
emilmont	77:869cf507173a	974	* @note You have to set the PLLM parameter correctly to ensure that the VCO input
emilmont	77:869cf507173a	975	* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
emilmont	77:869cf507173a	976	* of 2 MHz to limit PLL jitter.
emilmont	77:869cf507173a	977	* @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
emilmont	77:869cf507173a	978	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont	77:869cf507173a	979	* @note You have to set the PLLN parameter correctly to ensure that the VCO
emilmont	77:869cf507173a	980	* output frequency is between 192 and 432 MHz.
emilmont	77:869cf507173a	981	* @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
emilmont	77:869cf507173a	982	* This parameter must be a number in the range {2, 4, 6, or 8}.
emilmont	77:869cf507173a	983	* @note You have to set the PLLP parameter correctly to not exceed 168 MHz on
emilmont	77:869cf507173a	984	* the System clock frequency.
emilmont	77:869cf507173a	985	* @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
emilmont	77:869cf507173a	986	* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
emilmont	77:869cf507173a	987	* @note If the USB OTG FS is used in your application, you have to set the
emilmont	77:869cf507173a	988	* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
emilmont	77:869cf507173a	989	* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
emilmont	77:869cf507173a	990	* correctly.
emilmont	77:869cf507173a	991	*/
emilmont	77:869cf507173a	992	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__)\
emilmont	77:869cf507173a	993	(RCC->PLLCFGR = (0x20000000 \| (__PLLM__) \| ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) \| \
emilmont	77:869cf507173a	994	((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) \| (__RCC_PLLSource__) \| \
emilmont	77:869cf507173a	995	((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
emilmont	77:869cf507173a	996
emilmont	77:869cf507173a	997	/** @brief Macro to configure the I2S clock source (I2SCLK).
emilmont	77:869cf507173a	998	* @note This function must be called before enabling the I2S APB clock.
emilmont	77:869cf507173a	999	* @param __SOURCE__: specifies the I2S clock source.
emilmont	77:869cf507173a	1000	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1001	* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
emilmont	77:869cf507173a	1002	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
emilmont	77:869cf507173a	1003	* used as I2S clock source.
emilmont	77:869cf507173a	1004	*/
emilmont	77:869cf507173a	1005	#define __HAL_RCC_I2SCLK(__SOURCE__) ((__IO uint32_t ) CFGR_I2SSRC_BB = (__SOURCE__))
emilmont	77:869cf507173a	1006
emilmont	77:869cf507173a	1007	/** @brief Macros to enable or disable the PLLI2S.
emilmont	77:869cf507173a	1008	* @note The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.
emilmont	77:869cf507173a	1009	*/
emilmont	77:869cf507173a	1010	#define __HAL_RCC_PLLI2S_ENABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = ENABLE)
emilmont	77:869cf507173a	1011	#define __HAL_RCC_PLLI2S_DISABLE() ((__IO uint32_t ) CR_PLLI2SON_BB = DISABLE)
emilmont	77:869cf507173a	1012
emilmont	77:869cf507173a	1013	/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
emilmont	77:869cf507173a	1014	* @note This macro must be used only when the PLLI2S is disabled.
emilmont	77:869cf507173a	1015	* @note PLLI2S clock source is common with the main PLL (configured in
emilmont	77:869cf507173a	1016	* HAL_RCC_ClockConfig() API).
emilmont	77:869cf507173a	1017	* @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
emilmont	77:869cf507173a	1018	* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
emilmont	77:869cf507173a	1019	* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
emilmont	77:869cf507173a	1020	* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
emilmont	77:869cf507173a	1021	* @param __PLLI2SR__: specifies the division factor for I2S clock
emilmont	77:869cf507173a	1022	* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
emilmont	77:869cf507173a	1023	* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
emilmont	77:869cf507173a	1024	* on the I2S clock frequency.
emilmont	77:869cf507173a	1025	*/
emilmont	77:869cf507173a	1026	#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) \| ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
emilmont	77:869cf507173a	1027
emilmont	77:869cf507173a	1028	/** @brief Macro to get the clock source used as system clock.
emilmont	77:869cf507173a	1029	* @retval The clock source used as system clock. The returned value can be one
emilmont	77:869cf507173a	1030	* of the following:
emilmont	77:869cf507173a	1031	* - RCC_CFGR_SWS_HSI: HSI used as system clock.
emilmont	77:869cf507173a	1032	* - RCC_CFGR_SWS_HSE: HSE used as system clock.
emilmont	77:869cf507173a	1033	* - RCC_CFGR_SWS_PLL: PLL used as system clock.
emilmont	77:869cf507173a	1034	*/
emilmont	77:869cf507173a	1035	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
emilmont	77:869cf507173a	1036
emilmont	77:869cf507173a	1037	/** @brief Macro to get the oscillator used as PLL clock source.
emilmont	77:869cf507173a	1038	* @retval The oscillator used as PLL clock source. The returned value can be one
emilmont	77:869cf507173a	1039	* of the following:
emilmont	77:869cf507173a	1040	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
emilmont	77:869cf507173a	1041	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
emilmont	77:869cf507173a	1042	*/
emilmont	77:869cf507173a	1043	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC))
emilmont	77:869cf507173a	1044
emilmont	77:869cf507173a	1045	/** @defgroup RCC_Flags_Interrupts_Management
emilmont	77:869cf507173a	1046	* @brief macros to manage the specified RCC Flags and interrupts.
emilmont	77:869cf507173a	1047	* @{
emilmont	77:869cf507173a	1048	*/
emilmont	77:869cf507173a	1049
emilmont	77:869cf507173a	1050	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
emilmont	77:869cf507173a	1051	* the selected interrupts).
emilmont	77:869cf507173a	1052	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
emilmont	77:869cf507173a	1053	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1054	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont	77:869cf507173a	1055	* @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont	77:869cf507173a	1056	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont	77:869cf507173a	1057	* @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont	77:869cf507173a	1058	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont	77:869cf507173a	1059	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont	77:869cf507173a	1060	*/
emilmont	77:869cf507173a	1061	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1062
emilmont	77:869cf507173a	1063	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
emilmont	77:869cf507173a	1064	* the selected interrupts).
emilmont	77:869cf507173a	1065	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
emilmont	77:869cf507173a	1066	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1067	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont	77:869cf507173a	1068	* @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont	77:869cf507173a	1069	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont	77:869cf507173a	1070	* @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont	77:869cf507173a	1071	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont	77:869cf507173a	1072	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont	77:869cf507173a	1073	*/
emilmont	77:869cf507173a	1074	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1075
emilmont	77:869cf507173a	1076	/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
emilmont	77:869cf507173a	1077	* bits to clear the selected interrupt pending bits.
emilmont	77:869cf507173a	1078	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
emilmont	77:869cf507173a	1079	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1080	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont	77:869cf507173a	1081	* @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont	77:869cf507173a	1082	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont	77:869cf507173a	1083	* @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont	77:869cf507173a	1084	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont	77:869cf507173a	1085	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont	77:869cf507173a	1086	* @arg RCC_IT_CSS: Clock Security System interrupt
emilmont	77:869cf507173a	1087	*/
emilmont	77:869cf507173a	1088	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
emilmont	77:869cf507173a	1089
emilmont	77:869cf507173a	1090	/** @brief Check the RCC's interrupt has occurred or not.
emilmont	77:869cf507173a	1091	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
emilmont	77:869cf507173a	1092	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1093	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
emilmont	77:869cf507173a	1094	* @arg RCC_IT_LSERDY: LSE ready interrupt.
emilmont	77:869cf507173a	1095	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
emilmont	77:869cf507173a	1096	* @arg RCC_IT_HSERDY: HSE ready interrupt.
emilmont	77:869cf507173a	1097	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
emilmont	77:869cf507173a	1098	* @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
emilmont	77:869cf507173a	1099	* @arg RCC_IT_CSS: Clock Security System interrupt
emilmont	77:869cf507173a	1100	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
emilmont	77:869cf507173a	1101	*/
emilmont	77:869cf507173a	1102	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
emilmont	77:869cf507173a	1103
emilmont	77:869cf507173a	1104	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
emilmont	77:869cf507173a	1105	* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
emilmont	77:869cf507173a	1106	*/
bogdanm	81:7d30d6019079	1107	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
emilmont	77:869cf507173a	1108
emilmont	77:869cf507173a	1109	/** @brief Check RCC flag is set or not.
emilmont	77:869cf507173a	1110	* @param __FLAG__: specifies the flag to check.
emilmont	77:869cf507173a	1111	* This parameter can be one of the following values:
emilmont	77:869cf507173a	1112	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
emilmont	77:869cf507173a	1113	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
emilmont	77:869cf507173a	1114	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
emilmont	77:869cf507173a	1115	* @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready.
emilmont	77:869cf507173a	1116	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
emilmont	77:869cf507173a	1117	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
emilmont	77:869cf507173a	1118	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
emilmont	77:869cf507173a	1119	* @arg RCC_FLAG_PINRST: Pin reset.
emilmont	77:869cf507173a	1120	* @arg RCC_FLAG_PORRST: POR/PDR reset.
emilmont	77:869cf507173a	1121	* @arg RCC_FLAG_SFTRST: Software reset.
emilmont	77:869cf507173a	1122	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
emilmont	77:869cf507173a	1123	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
emilmont	77:869cf507173a	1124	* @arg RCC_FLAG_LPWRRST: Low Power reset.
emilmont	77:869cf507173a	1125	* @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont	77:869cf507173a	1126	*/
emilmont	77:869cf507173a	1127	#define RCC_FLAG_MASK ((uint8_t)0x1F)
emilmont	77:869cf507173a	1128	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((((__FLAG__) >> 5) == 1)? RCC->CR :((((__FLAG__) >> 5) == 2) ? RCC->BDCR :((((__FLAG__) >> 5) == 3)? RCC->CSR :RCC->CIR))) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))!= 0)? 1 : 0)
emilmont	77:869cf507173a	1129	/**
emilmont	77:869cf507173a	1130	* @}
emilmont	77:869cf507173a	1131	*/
emilmont	77:869cf507173a	1132
emilmont	77:869cf507173a	1133	#define __RCC_PLLSRC() ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> POSITION_VAL(RCC_PLLCFGR_PLLSRC))
emilmont	77:869cf507173a	1134
emilmont	77:869cf507173a	1135
emilmont	77:869cf507173a	1136	/* Include RCC HAL Extension module */
emilmont	77:869cf507173a	1137	#include "stm32f4xx_hal_rcc_ex.h"
emilmont	77:869cf507173a	1138
emilmont	77:869cf507173a	1139	/* Exported functions --------------------------------------------------------*/
emilmont	77:869cf507173a	1140
emilmont	77:869cf507173a	1141	/* Initialization and de-initialization functions ******************************/
emilmont	77:869cf507173a	1142	void HAL_RCC_DeInit(void);
emilmont	77:869cf507173a	1143	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
emilmont	77:869cf507173a	1144	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
emilmont	77:869cf507173a	1145
emilmont	77:869cf507173a	1146	/* Peripheral Control functions ************************************************/
emilmont	77:869cf507173a	1147	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
emilmont	77:869cf507173a	1148	void HAL_RCC_EnableCSS(void);
emilmont	77:869cf507173a	1149	void HAL_RCC_DisableCSS(void);
emilmont	77:869cf507173a	1150	uint32_t HAL_RCC_GetSysClockFreq(void);
emilmont	77:869cf507173a	1151	uint32_t HAL_RCC_GetHCLKFreq(void);
emilmont	77:869cf507173a	1152	uint32_t HAL_RCC_GetPCLK1Freq(void);
emilmont	77:869cf507173a	1153	uint32_t HAL_RCC_GetPCLK2Freq(void);
emilmont	77:869cf507173a	1154	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
emilmont	77:869cf507173a	1155	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
emilmont	77:869cf507173a	1156
emilmont	77:869cf507173a	1157	/* CSS NMI IRQ handler */
emilmont	77:869cf507173a	1158	void HAL_RCC_NMI_IRQHandler(void);
emilmont	77:869cf507173a	1159
emilmont	77:869cf507173a	1160	/* User Callbacks in non blocking mode (IT mode) */
bogdanm	81:7d30d6019079	1161	void HAL_RCC_CCSCallback(void);
emilmont	77:869cf507173a	1162
emilmont	77:869cf507173a	1163	/**
emilmont	77:869cf507173a	1164	* @}
emilmont	77:869cf507173a	1165	*/
emilmont	77:869cf507173a	1166
emilmont	77:869cf507173a	1167	/**
emilmont	77:869cf507173a	1168	* @}
emilmont	77:869cf507173a	1169	*/
emilmont	77:869cf507173a	1170
emilmont	77:869cf507173a	1171	#ifdef __cplusplus
emilmont	77:869cf507173a	1172	}
emilmont	77:869cf507173a	1173	#endif
emilmont	77:869cf507173a	1174
emilmont	77:869cf507173a	1175	#endif /* __STM32F4xx_HAL_RCC_H */
emilmont	77:869cf507173a	1176
emilmont	77:869cf507173a	1177	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F401RE/stm32f4xx_hal_rcc.h@81:7d30d6019079, 2014-03-19 (annotated)

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