Filippo Casamassima / mbed

my fork

Dependents:   Nucleo_blueNRG

Fork of mbed by mbed official

TARGET_LPC2368/core_arm7.h@65:5798e58a58b1, 2013-08-12 (annotated)

Committer:
bogdanm
Date:
Mon Aug 12 13:17:46 2013 +0300
Revision:
65:5798e58a58b1
Parent:
64:e3affc9e7238
Child:
66:9c8f0e3462fb
New target (LPC4088), new features (interrupt chaining), bug fixes (KL25Z I2C).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 65:5798e58a58b1 1 /* mbed Microcontroller Library
bogdanm 65:5798e58a58b1 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
bogdanm 65:5798e58a58b1 3 *
bogdanm 65:5798e58a58b1 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
bogdanm 65:5798e58a58b1 5 * based on core_cm3.h, V1.20
bogdanm 65:5798e58a58b1 6 */
bogdanm 65:5798e58a58b1 7
bogdanm 65:5798e58a58b1 8 #ifndef __ARM7_CORE_H__
bogdanm 65:5798e58a58b1 9 #define __ARM7_CORE_H__
bogdanm 65:5798e58a58b1 10
bogdanm 65:5798e58a58b1 11 #include "vector_defns.h"
bogdanm 65:5798e58a58b1 12
bogdanm 65:5798e58a58b1 13 #ifdef __cplusplus
bogdanm 65:5798e58a58b1 14 extern "C" {
bogdanm 65:5798e58a58b1 15 #endif
bogdanm 65:5798e58a58b1 16
bogdanm 65:5798e58a58b1 17 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
bogdanm 65:5798e58a58b1 18 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 65:5798e58a58b1 19 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 65:5798e58a58b1 20
bogdanm 65:5798e58a58b1 21 #define __CORTEX_M (0x03) /*!< Cortex core */
bogdanm 65:5798e58a58b1 22
bogdanm 65:5798e58a58b1 23 /**
bogdanm 65:5798e58a58b1 24 * Lint configuration \n
bogdanm 65:5798e58a58b1 25 * ----------------------- \n
bogdanm 65:5798e58a58b1 26 *
bogdanm 65:5798e58a58b1 27 * The following Lint messages will be suppressed and not shown: \n
bogdanm 65:5798e58a58b1 28 * \n
bogdanm 65:5798e58a58b1 29 * --- Error 10: --- \n
bogdanm 65:5798e58a58b1 30 * register uint32_t __regBasePri __asm("basepri"); \n
bogdanm 65:5798e58a58b1 31 * Error 10: Expecting ';' \n
bogdanm 65:5798e58a58b1 32 * \n
bogdanm 65:5798e58a58b1 33 * --- Error 530: --- \n
bogdanm 65:5798e58a58b1 34 * return(__regBasePri); \n
bogdanm 65:5798e58a58b1 35 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
bogdanm 65:5798e58a58b1 36 * \n
bogdanm 65:5798e58a58b1 37 * --- Error 550: --- \n
bogdanm 65:5798e58a58b1 38 * __regBasePri = (basePri & 0x1ff); \n
bogdanm 65:5798e58a58b1 39 * } \n
bogdanm 65:5798e58a58b1 40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
bogdanm 65:5798e58a58b1 41 * \n
bogdanm 65:5798e58a58b1 42 * --- Error 754: --- \n
bogdanm 65:5798e58a58b1 43 * uint32_t RESERVED0[24]; \n
bogdanm 65:5798e58a58b1 44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
bogdanm 65:5798e58a58b1 45 * \n
bogdanm 65:5798e58a58b1 46 * --- Error 750: --- \n
bogdanm 65:5798e58a58b1 47 * #define __CM3_CORE_H__ \n
bogdanm 65:5798e58a58b1 48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
bogdanm 65:5798e58a58b1 49 * \n
bogdanm 65:5798e58a58b1 50 * --- Error 528: --- \n
bogdanm 65:5798e58a58b1 51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
bogdanm 65:5798e58a58b1 52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
bogdanm 65:5798e58a58b1 53 * \n
bogdanm 65:5798e58a58b1 54 * --- Error 751: --- \n
bogdanm 65:5798e58a58b1 55 * } InterruptType_Type; \n
bogdanm 65:5798e58a58b1 56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
bogdanm 65:5798e58a58b1 57 * \n
bogdanm 65:5798e58a58b1 58 * \n
bogdanm 65:5798e58a58b1 59 * Note: To re-enable a Message, insert a space before 'lint' * \n
bogdanm 65:5798e58a58b1 60 *
bogdanm 65:5798e58a58b1 61 */
bogdanm 65:5798e58a58b1 62
bogdanm 65:5798e58a58b1 63 /*lint -save */
bogdanm 65:5798e58a58b1 64 /*lint -e10 */
bogdanm 65:5798e58a58b1 65 /*lint -e530 */
bogdanm 65:5798e58a58b1 66 /*lint -e550 */
bogdanm 65:5798e58a58b1 67 /*lint -e754 */
bogdanm 65:5798e58a58b1 68 /*lint -e750 */
bogdanm 65:5798e58a58b1 69 /*lint -e528 */
bogdanm 65:5798e58a58b1 70 /*lint -e751 */
bogdanm 65:5798e58a58b1 71
bogdanm 65:5798e58a58b1 72 #include <stdint.h> /* Include standard types */
bogdanm 65:5798e58a58b1 73
bogdanm 65:5798e58a58b1 74 #if defined ( __CC_ARM )
bogdanm 65:5798e58a58b1 75 /**
bogdanm 65:5798e58a58b1 76 * @brief Return the Main Stack Pointer (current ARM7 stack)
bogdanm 65:5798e58a58b1 77 *
bogdanm 65:5798e58a58b1 78 * @param none
bogdanm 65:5798e58a58b1 79 * @return uint32_t Main Stack Pointer
bogdanm 65:5798e58a58b1 80 *
bogdanm 65:5798e58a58b1 81 * Return the current value of the MSP (main stack pointer)
bogdanm 65:5798e58a58b1 82 * Cortex processor register
bogdanm 65:5798e58a58b1 83 */
bogdanm 65:5798e58a58b1 84 extern uint32_t __get_MSP(void);
bogdanm 65:5798e58a58b1 85 #endif
bogdanm 65:5798e58a58b1 86
bogdanm 65:5798e58a58b1 87
bogdanm 65:5798e58a58b1 88 #if defined (__ICCARM__)
bogdanm 65:5798e58a58b1 89 #include <intrinsics.h> /* IAR Intrinsics */
bogdanm 65:5798e58a58b1 90 #endif
bogdanm 65:5798e58a58b1 91
bogdanm 65:5798e58a58b1 92
bogdanm 65:5798e58a58b1 93 #ifndef __NVIC_PRIO_BITS
bogdanm 65:5798e58a58b1 94 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
bogdanm 65:5798e58a58b1 95 #endif
bogdanm 65:5798e58a58b1 96
bogdanm 65:5798e58a58b1 97 typedef struct
bogdanm 65:5798e58a58b1 98 {
bogdanm 65:5798e58a58b1 99 uint32_t IRQStatus;
bogdanm 65:5798e58a58b1 100 uint32_t FIQStatus;
bogdanm 65:5798e58a58b1 101 uint32_t RawIntr;
bogdanm 65:5798e58a58b1 102 uint32_t IntSelect;
bogdanm 65:5798e58a58b1 103 uint32_t IntEnable;
bogdanm 65:5798e58a58b1 104 uint32_t IntEnClr;
bogdanm 65:5798e58a58b1 105 uint32_t SoftInt;
bogdanm 65:5798e58a58b1 106 uint32_t SoftIntClr;
bogdanm 65:5798e58a58b1 107 uint32_t Protection;
bogdanm 65:5798e58a58b1 108 uint32_t SWPriorityMask;
bogdanm 65:5798e58a58b1 109 uint32_t RESERVED0[54];
bogdanm 65:5798e58a58b1 110 uint32_t VectAddr[32];
bogdanm 65:5798e58a58b1 111 uint32_t RESERVED1[32];
bogdanm 65:5798e58a58b1 112 uint32_t VectPriority[32];
bogdanm 65:5798e58a58b1 113 uint32_t RESERVED2[800];
bogdanm 65:5798e58a58b1 114 uint32_t Address;
bogdanm 65:5798e58a58b1 115 } NVIC_TypeDef;
bogdanm 65:5798e58a58b1 116
bogdanm 65:5798e58a58b1 117 #define NVIC_BASE (0xFFFFF000)
bogdanm 65:5798e58a58b1 118 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
bogdanm 65:5798e58a58b1 119
bogdanm 65:5798e58a58b1 120
bogdanm 65:5798e58a58b1 121
bogdanm 65:5798e58a58b1 122 /**
bogdanm 65:5798e58a58b1 123 * IO definitions
bogdanm 65:5798e58a58b1 124 *
bogdanm 65:5798e58a58b1 125 * define access restrictions to peripheral registers
bogdanm 65:5798e58a58b1 126 */
bogdanm 65:5798e58a58b1 127
bogdanm 65:5798e58a58b1 128 #ifdef __cplusplus
bogdanm 65:5798e58a58b1 129 #define __I volatile /*!< defines 'read only' permissions */
bogdanm 65:5798e58a58b1 130 #else
bogdanm 65:5798e58a58b1 131 #define __I volatile const /*!< defines 'read only' permissions */
bogdanm 65:5798e58a58b1 132 #endif
bogdanm 65:5798e58a58b1 133 #define __O volatile /*!< defines 'write only' permissions */
bogdanm 65:5798e58a58b1 134 #define __IO volatile /*!< defines 'read / write' permissions */
bogdanm 65:5798e58a58b1 135
bogdanm 65:5798e58a58b1 136
bogdanm 65:5798e58a58b1 137
bogdanm 65:5798e58a58b1 138
bogdanm 65:5798e58a58b1 139
bogdanm 65:5798e58a58b1 140 #if defined ( __CC_ARM )
bogdanm 65:5798e58a58b1 141 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 65:5798e58a58b1 142 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 65:5798e58a58b1 143
bogdanm 65:5798e58a58b1 144 #elif defined ( __ICCARM__ )
bogdanm 65:5798e58a58b1 145 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 65:5798e58a58b1 146 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
bogdanm 65:5798e58a58b1 147
bogdanm 65:5798e58a58b1 148 #elif defined ( __GNUC__ )
bogdanm 65:5798e58a58b1 149 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 65:5798e58a58b1 150 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 65:5798e58a58b1 151
bogdanm 65:5798e58a58b1 152 #elif defined ( __TASKING__ )
bogdanm 65:5798e58a58b1 153 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 65:5798e58a58b1 154 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 65:5798e58a58b1 155
bogdanm 65:5798e58a58b1 156 #endif
bogdanm 65:5798e58a58b1 157
bogdanm 65:5798e58a58b1 158
bogdanm 65:5798e58a58b1 159 /* ################### Compiler specific Intrinsics ########################### */
bogdanm 65:5798e58a58b1 160
bogdanm 65:5798e58a58b1 161 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 65:5798e58a58b1 162 /* ARM armcc specific functions */
bogdanm 65:5798e58a58b1 163
bogdanm 65:5798e58a58b1 164 #define __enable_fault_irq __enable_fiq
bogdanm 65:5798e58a58b1 165 #define __disable_fault_irq __disable_fiq
bogdanm 65:5798e58a58b1 166
bogdanm 65:5798e58a58b1 167 #define __NOP __nop
bogdanm 65:5798e58a58b1 168 //#define __WFI __wfi
bogdanm 65:5798e58a58b1 169 //#define __WFE __wfe
bogdanm 65:5798e58a58b1 170 //#define __SEV __sev
bogdanm 65:5798e58a58b1 171 //#define __ISB() __isb(0)
bogdanm 65:5798e58a58b1 172 //#define __DSB() __dsb(0)
bogdanm 65:5798e58a58b1 173 //#define __DMB() __dmb(0)
bogdanm 65:5798e58a58b1 174 //#define __REV __rev
bogdanm 65:5798e58a58b1 175 //#define __RBIT __rbit
bogdanm 65:5798e58a58b1 176 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
bogdanm 65:5798e58a58b1 177 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
bogdanm 65:5798e58a58b1 178 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
bogdanm 65:5798e58a58b1 179 #define __STREXB(value, ptr) __strex(value, ptr)
bogdanm 65:5798e58a58b1 180 #define __STREXH(value, ptr) __strex(value, ptr)
bogdanm 65:5798e58a58b1 181 #define __STREXW(value, ptr) __strex(value, ptr)
bogdanm 65:5798e58a58b1 182
bogdanm 65:5798e58a58b1 183 #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
bogdanm 65:5798e58a58b1 184 LPC_VIC->IntEnClr = 0xffffffff
bogdanm 65:5798e58a58b1 185
bogdanm 65:5798e58a58b1 186 #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
bogdanm 65:5798e58a58b1 187
bogdanm 65:5798e58a58b1 188 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
bogdanm 65:5798e58a58b1 189
bogdanm 65:5798e58a58b1 190 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
bogdanm 65:5798e58a58b1 191 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
bogdanm 65:5798e58a58b1 192 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
bogdanm 65:5798e58a58b1 193
bogdanm 65:5798e58a58b1 194 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
bogdanm 65:5798e58a58b1 195
bogdanm 65:5798e58a58b1 196 static __INLINE void __enable_irq() {
bogdanm 65:5798e58a58b1 197 unsigned long temp;
bogdanm 65:5798e58a58b1 198 __asm__ __volatile__("mrs %0, cpsr\n"
bogdanm 65:5798e58a58b1 199 "bic %0, %0, #0x80\n"
bogdanm 65:5798e58a58b1 200 "msr cpsr_c, %0"
bogdanm 65:5798e58a58b1 201 : "=r" (temp)
bogdanm 65:5798e58a58b1 202 :
bogdanm 65:5798e58a58b1 203 : "memory");
bogdanm 65:5798e58a58b1 204 }
bogdanm 65:5798e58a58b1 205
bogdanm 65:5798e58a58b1 206 static __INLINE void __disable_irq() {
bogdanm 65:5798e58a58b1 207 unsigned long old,temp;
bogdanm 65:5798e58a58b1 208 __asm__ __volatile__("mrs %0, cpsr\n"
bogdanm 65:5798e58a58b1 209 "orr %1, %0, #0xc0\n"
bogdanm 65:5798e58a58b1 210 "msr cpsr_c, %1"
bogdanm 65:5798e58a58b1 211 : "=r" (old), "=r" (temp)
bogdanm 65:5798e58a58b1 212 :
bogdanm 65:5798e58a58b1 213 : "memory");
bogdanm 65:5798e58a58b1 214 // return (old & 0x80) == 0;
bogdanm 65:5798e58a58b1 215 }
bogdanm 65:5798e58a58b1 216
bogdanm 65:5798e58a58b1 217 static __INLINE void __NOP() { __ASM volatile ("nop"); }
bogdanm 65:5798e58a58b1 218
bogdanm 65:5798e58a58b1 219 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
bogdanm 65:5798e58a58b1 220 /* TASKING carm specific functions */
bogdanm 65:5798e58a58b1 221
bogdanm 65:5798e58a58b1 222 /*
bogdanm 65:5798e58a58b1 223 * The CMSIS functions have been implemented as intrinsics in the compiler.
bogdanm 65:5798e58a58b1 224 * Please use "carm -?i" to get an up to date list of all instrinsics,
bogdanm 65:5798e58a58b1 225 * Including the CMSIS ones.
bogdanm 65:5798e58a58b1 226 */
bogdanm 65:5798e58a58b1 227
bogdanm 65:5798e58a58b1 228 #endif
bogdanm 65:5798e58a58b1 229
bogdanm 65:5798e58a58b1 230
bogdanm 65:5798e58a58b1 231 /**
bogdanm 65:5798e58a58b1 232 * @brief Enable Interrupt in NVIC Interrupt Controller
bogdanm 65:5798e58a58b1 233 *
bogdanm 65:5798e58a58b1 234 * @param IRQn_Type IRQn specifies the interrupt number
bogdanm 65:5798e58a58b1 235 * @return none
bogdanm 65:5798e58a58b1 236 *
bogdanm 65:5798e58a58b1 237 * Enable a device specific interupt in the NVIC interrupt controller.
bogdanm 65:5798e58a58b1 238 * The interrupt number cannot be a negative value.
bogdanm 65:5798e58a58b1 239 */
bogdanm 65:5798e58a58b1 240 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 65:5798e58a58b1 241 {
bogdanm 65:5798e58a58b1 242 NVIC->IntEnable = 1 << (uint32_t)IRQn;
bogdanm 65:5798e58a58b1 243 }
bogdanm 65:5798e58a58b1 244
bogdanm 65:5798e58a58b1 245
bogdanm 65:5798e58a58b1 246 /**
bogdanm 65:5798e58a58b1 247 * @brief Disable the interrupt line for external interrupt specified
bogdanm 65:5798e58a58b1 248 *
bogdanm 65:5798e58a58b1 249 * @param IRQn_Type IRQn is the positive number of the external interrupt
bogdanm 65:5798e58a58b1 250 * @return none
bogdanm 65:5798e58a58b1 251 *
bogdanm 65:5798e58a58b1 252 * Disable a device specific interupt in the NVIC interrupt controller.
bogdanm 65:5798e58a58b1 253 * The interrupt number cannot be a negative value.
bogdanm 65:5798e58a58b1 254 */
bogdanm 65:5798e58a58b1 255 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 65:5798e58a58b1 256 {
bogdanm 65:5798e58a58b1 257 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
bogdanm 65:5798e58a58b1 258 }
bogdanm 65:5798e58a58b1 259
bogdanm 65:5798e58a58b1 260 static __INLINE uint32_t __get_IPSR(void)
bogdanm 65:5798e58a58b1 261 {
bogdanm 65:5798e58a58b1 262 unsigned i;
bogdanm 65:5798e58a58b1 263
bogdanm 65:5798e58a58b1 264 for(i = 0; i < 32; i ++)
bogdanm 65:5798e58a58b1 265 if(NVIC->Address == NVIC->VectAddr[i])
bogdanm 65:5798e58a58b1 266 return i;
bogdanm 65:5798e58a58b1 267 return 1; // 1 is an invalid entry in the interrupt table on LPC2368
bogdanm 65:5798e58a58b1 268 }
bogdanm 65:5798e58a58b1 269
bogdanm 65:5798e58a58b1 270 #ifdef __cplusplus
bogdanm 65:5798e58a58b1 271 }
bogdanm 65:5798e58a58b1 272 #endif
bogdanm 65:5798e58a58b1 273
bogdanm 65:5798e58a58b1 274 #endif /* __ARM7_CORE_H__ */
bogdanm 65:5798e58a58b1 275
bogdanm 65:5798e58a58b1 276 /*lint -restore */