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TARGET_LPC1768/LPC17xx.h@65:5798e58a58b1, 2013-08-12 (annotated)

Committer:
bogdanm
Date:
Mon Aug 12 13:17:46 2013 +0300
Revision:
65:5798e58a58b1
Parent:
64:e3affc9e7238
Child:
66:9c8f0e3462fb
New target (LPC4088), new features (interrupt chaining), bug fixes (KL25Z I2C).

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 65:5798e58a58b1 1 /**************************************************************************//**
bogdanm 65:5798e58a58b1 2 * @file LPC17xx.h
bogdanm 65:5798e58a58b1 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
bogdanm 65:5798e58a58b1 4 * NXP LPC17xx Device Series
bogdanm 65:5798e58a58b1 5 * @version: V1.09
bogdanm 65:5798e58a58b1 6 * @date: 17. March 2010
bogdanm 65:5798e58a58b1 7
bogdanm 65:5798e58a58b1 8 *
bogdanm 65:5798e58a58b1 9 * @note
bogdanm 65:5798e58a58b1 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
bogdanm 65:5798e58a58b1 11 *
bogdanm 65:5798e58a58b1 12 * @par
bogdanm 65:5798e58a58b1 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 65:5798e58a58b1 14 * processor based microcontrollers. This file can be freely distributed
bogdanm 65:5798e58a58b1 15 * within development tools that are supporting such ARM based processors.
bogdanm 65:5798e58a58b1 16 *
bogdanm 65:5798e58a58b1 17 * @par
bogdanm 65:5798e58a58b1 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 65:5798e58a58b1 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 65:5798e58a58b1 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 65:5798e58a58b1 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 65:5798e58a58b1 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 65:5798e58a58b1 23 *
bogdanm 65:5798e58a58b1 24 ******************************************************************************/
bogdanm 65:5798e58a58b1 25
bogdanm 65:5798e58a58b1 26
bogdanm 65:5798e58a58b1 27 #ifndef __LPC17xx_H__
bogdanm 65:5798e58a58b1 28 #define __LPC17xx_H__
bogdanm 65:5798e58a58b1 29
bogdanm 65:5798e58a58b1 30 /*
bogdanm 65:5798e58a58b1 31 * ==========================================================================
bogdanm 65:5798e58a58b1 32 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 65:5798e58a58b1 33 * ==========================================================================
bogdanm 65:5798e58a58b1 34 */
bogdanm 65:5798e58a58b1 35
bogdanm 65:5798e58a58b1 36 typedef enum IRQn
bogdanm 65:5798e58a58b1 37 {
bogdanm 65:5798e58a58b1 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
bogdanm 65:5798e58a58b1 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 65:5798e58a58b1 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
bogdanm 65:5798e58a58b1 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
bogdanm 65:5798e58a58b1 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
bogdanm 65:5798e58a58b1 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
bogdanm 65:5798e58a58b1 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
bogdanm 65:5798e58a58b1 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
bogdanm 65:5798e58a58b1 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
bogdanm 65:5798e58a58b1 47
bogdanm 65:5798e58a58b1 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
bogdanm 65:5798e58a58b1 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
bogdanm 65:5798e58a58b1 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
bogdanm 65:5798e58a58b1 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
bogdanm 65:5798e58a58b1 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
bogdanm 65:5798e58a58b1 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
bogdanm 65:5798e58a58b1 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
bogdanm 65:5798e58a58b1 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
bogdanm 65:5798e58a58b1 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
bogdanm 65:5798e58a58b1 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
bogdanm 65:5798e58a58b1 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
bogdanm 65:5798e58a58b1 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
bogdanm 65:5798e58a58b1 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
bogdanm 65:5798e58a58b1 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
bogdanm 65:5798e58a58b1 62 SPI_IRQn = 13, /*!< SPI Interrupt */
bogdanm 65:5798e58a58b1 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
bogdanm 65:5798e58a58b1 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
bogdanm 65:5798e58a58b1 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
bogdanm 65:5798e58a58b1 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
bogdanm 65:5798e58a58b1 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
bogdanm 65:5798e58a58b1 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
bogdanm 65:5798e58a58b1 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
bogdanm 65:5798e58a58b1 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
bogdanm 65:5798e58a58b1 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
bogdanm 65:5798e58a58b1 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
bogdanm 65:5798e58a58b1 73 USB_IRQn = 24, /*!< USB Interrupt */
bogdanm 65:5798e58a58b1 74 CAN_IRQn = 25, /*!< CAN Interrupt */
bogdanm 65:5798e58a58b1 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
bogdanm 65:5798e58a58b1 76 I2S_IRQn = 27, /*!< I2S Interrupt */
bogdanm 65:5798e58a58b1 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
bogdanm 65:5798e58a58b1 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
bogdanm 65:5798e58a58b1 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
bogdanm 65:5798e58a58b1 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
bogdanm 65:5798e58a58b1 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
bogdanm 65:5798e58a58b1 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
bogdanm 65:5798e58a58b1 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
bogdanm 65:5798e58a58b1 84 } IRQn_Type;
bogdanm 65:5798e58a58b1 85
bogdanm 65:5798e58a58b1 86
bogdanm 65:5798e58a58b1 87 /*
bogdanm 65:5798e58a58b1 88 * ==========================================================================
bogdanm 65:5798e58a58b1 89 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 65:5798e58a58b1 90 * ==========================================================================
bogdanm 65:5798e58a58b1 91 */
bogdanm 65:5798e58a58b1 92
bogdanm 65:5798e58a58b1 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
bogdanm 65:5798e58a58b1 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 65:5798e58a58b1 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 65:5798e58a58b1 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 65:5798e58a58b1 97
bogdanm 65:5798e58a58b1 98
bogdanm 65:5798e58a58b1 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
bogdanm 65:5798e58a58b1 100 #include "system_LPC17xx.h" /* System Header */
bogdanm 65:5798e58a58b1 101
bogdanm 65:5798e58a58b1 102
bogdanm 65:5798e58a58b1 103 /******************************************************************************/
bogdanm 65:5798e58a58b1 104 /* Device Specific Peripheral registers structures */
bogdanm 65:5798e58a58b1 105 /******************************************************************************/
bogdanm 65:5798e58a58b1 106
bogdanm 65:5798e58a58b1 107 #if defined ( __CC_ARM )
bogdanm 65:5798e58a58b1 108 #pragma anon_unions
bogdanm 65:5798e58a58b1 109 #endif
bogdanm 65:5798e58a58b1 110
bogdanm 65:5798e58a58b1 111 /*------------- System Control (SC) ------------------------------------------*/
bogdanm 65:5798e58a58b1 112 typedef struct
bogdanm 65:5798e58a58b1 113 {
bogdanm 65:5798e58a58b1 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
bogdanm 65:5798e58a58b1 115 uint32_t RESERVED0[31];
bogdanm 65:5798e58a58b1 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
bogdanm 65:5798e58a58b1 117 __IO uint32_t PLL0CFG;
bogdanm 65:5798e58a58b1 118 __I uint32_t PLL0STAT;
bogdanm 65:5798e58a58b1 119 __O uint32_t PLL0FEED;
bogdanm 65:5798e58a58b1 120 uint32_t RESERVED1[4];
bogdanm 65:5798e58a58b1 121 __IO uint32_t PLL1CON;
bogdanm 65:5798e58a58b1 122 __IO uint32_t PLL1CFG;
bogdanm 65:5798e58a58b1 123 __I uint32_t PLL1STAT;
bogdanm 65:5798e58a58b1 124 __O uint32_t PLL1FEED;
bogdanm 65:5798e58a58b1 125 uint32_t RESERVED2[4];
bogdanm 65:5798e58a58b1 126 __IO uint32_t PCON;
bogdanm 65:5798e58a58b1 127 __IO uint32_t PCONP;
bogdanm 65:5798e58a58b1 128 uint32_t RESERVED3[15];
bogdanm 65:5798e58a58b1 129 __IO uint32_t CCLKCFG;
bogdanm 65:5798e58a58b1 130 __IO uint32_t USBCLKCFG;
bogdanm 65:5798e58a58b1 131 __IO uint32_t CLKSRCSEL;
bogdanm 65:5798e58a58b1 132 __IO uint32_t CANSLEEPCLR;
bogdanm 65:5798e58a58b1 133 __IO uint32_t CANWAKEFLAGS;
bogdanm 65:5798e58a58b1 134 uint32_t RESERVED4[10];
bogdanm 65:5798e58a58b1 135 __IO uint32_t EXTINT; /* External Interrupts */
bogdanm 65:5798e58a58b1 136 uint32_t RESERVED5;
bogdanm 65:5798e58a58b1 137 __IO uint32_t EXTMODE;
bogdanm 65:5798e58a58b1 138 __IO uint32_t EXTPOLAR;
bogdanm 65:5798e58a58b1 139 uint32_t RESERVED6[12];
bogdanm 65:5798e58a58b1 140 __IO uint32_t RSID; /* Reset */
bogdanm 65:5798e58a58b1 141 uint32_t RESERVED7[7];
bogdanm 65:5798e58a58b1 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
bogdanm 65:5798e58a58b1 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
bogdanm 65:5798e58a58b1 144 __IO uint32_t PCLKSEL0;
bogdanm 65:5798e58a58b1 145 __IO uint32_t PCLKSEL1;
bogdanm 65:5798e58a58b1 146 uint32_t RESERVED8[4];
bogdanm 65:5798e58a58b1 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
bogdanm 65:5798e58a58b1 148 __IO uint32_t DMAREQSEL;
bogdanm 65:5798e58a58b1 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
bogdanm 65:5798e58a58b1 150 } LPC_SC_TypeDef;
bogdanm 65:5798e58a58b1 151
bogdanm 65:5798e58a58b1 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
bogdanm 65:5798e58a58b1 153 typedef struct
bogdanm 65:5798e58a58b1 154 {
bogdanm 65:5798e58a58b1 155 __IO uint32_t PINSEL0;
bogdanm 65:5798e58a58b1 156 __IO uint32_t PINSEL1;
bogdanm 65:5798e58a58b1 157 __IO uint32_t PINSEL2;
bogdanm 65:5798e58a58b1 158 __IO uint32_t PINSEL3;
bogdanm 65:5798e58a58b1 159 __IO uint32_t PINSEL4;
bogdanm 65:5798e58a58b1 160 __IO uint32_t PINSEL5;
bogdanm 65:5798e58a58b1 161 __IO uint32_t PINSEL6;
bogdanm 65:5798e58a58b1 162 __IO uint32_t PINSEL7;
bogdanm 65:5798e58a58b1 163 __IO uint32_t PINSEL8;
bogdanm 65:5798e58a58b1 164 __IO uint32_t PINSEL9;
bogdanm 65:5798e58a58b1 165 __IO uint32_t PINSEL10;
bogdanm 65:5798e58a58b1 166 uint32_t RESERVED0[5];
bogdanm 65:5798e58a58b1 167 __IO uint32_t PINMODE0;
bogdanm 65:5798e58a58b1 168 __IO uint32_t PINMODE1;
bogdanm 65:5798e58a58b1 169 __IO uint32_t PINMODE2;
bogdanm 65:5798e58a58b1 170 __IO uint32_t PINMODE3;
bogdanm 65:5798e58a58b1 171 __IO uint32_t PINMODE4;
bogdanm 65:5798e58a58b1 172 __IO uint32_t PINMODE5;
bogdanm 65:5798e58a58b1 173 __IO uint32_t PINMODE6;
bogdanm 65:5798e58a58b1 174 __IO uint32_t PINMODE7;
bogdanm 65:5798e58a58b1 175 __IO uint32_t PINMODE8;
bogdanm 65:5798e58a58b1 176 __IO uint32_t PINMODE9;
bogdanm 65:5798e58a58b1 177 __IO uint32_t PINMODE_OD0;
bogdanm 65:5798e58a58b1 178 __IO uint32_t PINMODE_OD1;
bogdanm 65:5798e58a58b1 179 __IO uint32_t PINMODE_OD2;
bogdanm 65:5798e58a58b1 180 __IO uint32_t PINMODE_OD3;
bogdanm 65:5798e58a58b1 181 __IO uint32_t PINMODE_OD4;
bogdanm 65:5798e58a58b1 182 __IO uint32_t I2CPADCFG;
bogdanm 65:5798e58a58b1 183 } LPC_PINCON_TypeDef;
bogdanm 65:5798e58a58b1 184
bogdanm 65:5798e58a58b1 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 65:5798e58a58b1 186 typedef struct
bogdanm 65:5798e58a58b1 187 {
bogdanm 65:5798e58a58b1 188 union {
bogdanm 65:5798e58a58b1 189 __IO uint32_t FIODIR;
bogdanm 65:5798e58a58b1 190 struct {
bogdanm 65:5798e58a58b1 191 __IO uint16_t FIODIRL;
bogdanm 65:5798e58a58b1 192 __IO uint16_t FIODIRH;
bogdanm 65:5798e58a58b1 193 };
bogdanm 65:5798e58a58b1 194 struct {
bogdanm 65:5798e58a58b1 195 __IO uint8_t FIODIR0;
bogdanm 65:5798e58a58b1 196 __IO uint8_t FIODIR1;
bogdanm 65:5798e58a58b1 197 __IO uint8_t FIODIR2;
bogdanm 65:5798e58a58b1 198 __IO uint8_t FIODIR3;
bogdanm 65:5798e58a58b1 199 };
bogdanm 65:5798e58a58b1 200 };
bogdanm 65:5798e58a58b1 201 uint32_t RESERVED0[3];
bogdanm 65:5798e58a58b1 202 union {
bogdanm 65:5798e58a58b1 203 __IO uint32_t FIOMASK;
bogdanm 65:5798e58a58b1 204 struct {
bogdanm 65:5798e58a58b1 205 __IO uint16_t FIOMASKL;
bogdanm 65:5798e58a58b1 206 __IO uint16_t FIOMASKH;
bogdanm 65:5798e58a58b1 207 };
bogdanm 65:5798e58a58b1 208 struct {
bogdanm 65:5798e58a58b1 209 __IO uint8_t FIOMASK0;
bogdanm 65:5798e58a58b1 210 __IO uint8_t FIOMASK1;
bogdanm 65:5798e58a58b1 211 __IO uint8_t FIOMASK2;
bogdanm 65:5798e58a58b1 212 __IO uint8_t FIOMASK3;
bogdanm 65:5798e58a58b1 213 };
bogdanm 65:5798e58a58b1 214 };
bogdanm 65:5798e58a58b1 215 union {
bogdanm 65:5798e58a58b1 216 __IO uint32_t FIOPIN;
bogdanm 65:5798e58a58b1 217 struct {
bogdanm 65:5798e58a58b1 218 __IO uint16_t FIOPINL;
bogdanm 65:5798e58a58b1 219 __IO uint16_t FIOPINH;
bogdanm 65:5798e58a58b1 220 };
bogdanm 65:5798e58a58b1 221 struct {
bogdanm 65:5798e58a58b1 222 __IO uint8_t FIOPIN0;
bogdanm 65:5798e58a58b1 223 __IO uint8_t FIOPIN1;
bogdanm 65:5798e58a58b1 224 __IO uint8_t FIOPIN2;
bogdanm 65:5798e58a58b1 225 __IO uint8_t FIOPIN3;
bogdanm 65:5798e58a58b1 226 };
bogdanm 65:5798e58a58b1 227 };
bogdanm 65:5798e58a58b1 228 union {
bogdanm 65:5798e58a58b1 229 __IO uint32_t FIOSET;
bogdanm 65:5798e58a58b1 230 struct {
bogdanm 65:5798e58a58b1 231 __IO uint16_t FIOSETL;
bogdanm 65:5798e58a58b1 232 __IO uint16_t FIOSETH;
bogdanm 65:5798e58a58b1 233 };
bogdanm 65:5798e58a58b1 234 struct {
bogdanm 65:5798e58a58b1 235 __IO uint8_t FIOSET0;
bogdanm 65:5798e58a58b1 236 __IO uint8_t FIOSET1;
bogdanm 65:5798e58a58b1 237 __IO uint8_t FIOSET2;
bogdanm 65:5798e58a58b1 238 __IO uint8_t FIOSET3;
bogdanm 65:5798e58a58b1 239 };
bogdanm 65:5798e58a58b1 240 };
bogdanm 65:5798e58a58b1 241 union {
bogdanm 65:5798e58a58b1 242 __O uint32_t FIOCLR;
bogdanm 65:5798e58a58b1 243 struct {
bogdanm 65:5798e58a58b1 244 __O uint16_t FIOCLRL;
bogdanm 65:5798e58a58b1 245 __O uint16_t FIOCLRH;
bogdanm 65:5798e58a58b1 246 };
bogdanm 65:5798e58a58b1 247 struct {
bogdanm 65:5798e58a58b1 248 __O uint8_t FIOCLR0;
bogdanm 65:5798e58a58b1 249 __O uint8_t FIOCLR1;
bogdanm 65:5798e58a58b1 250 __O uint8_t FIOCLR2;
bogdanm 65:5798e58a58b1 251 __O uint8_t FIOCLR3;
bogdanm 65:5798e58a58b1 252 };
bogdanm 65:5798e58a58b1 253 };
bogdanm 65:5798e58a58b1 254 } LPC_GPIO_TypeDef;
bogdanm 65:5798e58a58b1 255
bogdanm 65:5798e58a58b1 256 typedef struct
bogdanm 65:5798e58a58b1 257 {
bogdanm 65:5798e58a58b1 258 __I uint32_t IntStatus;
bogdanm 65:5798e58a58b1 259 __I uint32_t IO0IntStatR;
bogdanm 65:5798e58a58b1 260 __I uint32_t IO0IntStatF;
bogdanm 65:5798e58a58b1 261 __O uint32_t IO0IntClr;
bogdanm 65:5798e58a58b1 262 __IO uint32_t IO0IntEnR;
bogdanm 65:5798e58a58b1 263 __IO uint32_t IO0IntEnF;
bogdanm 65:5798e58a58b1 264 uint32_t RESERVED0[3];
bogdanm 65:5798e58a58b1 265 __I uint32_t IO2IntStatR;
bogdanm 65:5798e58a58b1 266 __I uint32_t IO2IntStatF;
bogdanm 65:5798e58a58b1 267 __O uint32_t IO2IntClr;
bogdanm 65:5798e58a58b1 268 __IO uint32_t IO2IntEnR;
bogdanm 65:5798e58a58b1 269 __IO uint32_t IO2IntEnF;
bogdanm 65:5798e58a58b1 270 } LPC_GPIOINT_TypeDef;
bogdanm 65:5798e58a58b1 271
bogdanm 65:5798e58a58b1 272 /*------------- Timer (TIM) --------------------------------------------------*/
bogdanm 65:5798e58a58b1 273 typedef struct
bogdanm 65:5798e58a58b1 274 {
bogdanm 65:5798e58a58b1 275 __IO uint32_t IR;
bogdanm 65:5798e58a58b1 276 __IO uint32_t TCR;
bogdanm 65:5798e58a58b1 277 __IO uint32_t TC;
bogdanm 65:5798e58a58b1 278 __IO uint32_t PR;
bogdanm 65:5798e58a58b1 279 __IO uint32_t PC;
bogdanm 65:5798e58a58b1 280 __IO uint32_t MCR;
bogdanm 65:5798e58a58b1 281 __IO uint32_t MR0;
bogdanm 65:5798e58a58b1 282 __IO uint32_t MR1;
bogdanm 65:5798e58a58b1 283 __IO uint32_t MR2;
bogdanm 65:5798e58a58b1 284 __IO uint32_t MR3;
bogdanm 65:5798e58a58b1 285 __IO uint32_t CCR;
bogdanm 65:5798e58a58b1 286 __I uint32_t CR0;
bogdanm 65:5798e58a58b1 287 __I uint32_t CR1;
bogdanm 65:5798e58a58b1 288 uint32_t RESERVED0[2];
bogdanm 65:5798e58a58b1 289 __IO uint32_t EMR;
bogdanm 65:5798e58a58b1 290 uint32_t RESERVED1[12];
bogdanm 65:5798e58a58b1 291 __IO uint32_t CTCR;
bogdanm 65:5798e58a58b1 292 } LPC_TIM_TypeDef;
bogdanm 65:5798e58a58b1 293
bogdanm 65:5798e58a58b1 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
bogdanm 65:5798e58a58b1 295 typedef struct
bogdanm 65:5798e58a58b1 296 {
bogdanm 65:5798e58a58b1 297 __IO uint32_t IR;
bogdanm 65:5798e58a58b1 298 __IO uint32_t TCR;
bogdanm 65:5798e58a58b1 299 __IO uint32_t TC;
bogdanm 65:5798e58a58b1 300 __IO uint32_t PR;
bogdanm 65:5798e58a58b1 301 __IO uint32_t PC;
bogdanm 65:5798e58a58b1 302 __IO uint32_t MCR;
bogdanm 65:5798e58a58b1 303 __IO uint32_t MR0;
bogdanm 65:5798e58a58b1 304 __IO uint32_t MR1;
bogdanm 65:5798e58a58b1 305 __IO uint32_t MR2;
bogdanm 65:5798e58a58b1 306 __IO uint32_t MR3;
bogdanm 65:5798e58a58b1 307 __IO uint32_t CCR;
bogdanm 65:5798e58a58b1 308 __I uint32_t CR0;
bogdanm 65:5798e58a58b1 309 __I uint32_t CR1;
bogdanm 65:5798e58a58b1 310 __I uint32_t CR2;
bogdanm 65:5798e58a58b1 311 __I uint32_t CR3;
bogdanm 65:5798e58a58b1 312 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 313 __IO uint32_t MR4;
bogdanm 65:5798e58a58b1 314 __IO uint32_t MR5;
bogdanm 65:5798e58a58b1 315 __IO uint32_t MR6;
bogdanm 65:5798e58a58b1 316 __IO uint32_t PCR;
bogdanm 65:5798e58a58b1 317 __IO uint32_t LER;
bogdanm 65:5798e58a58b1 318 uint32_t RESERVED1[7];
bogdanm 65:5798e58a58b1 319 __IO uint32_t CTCR;
bogdanm 65:5798e58a58b1 320 } LPC_PWM_TypeDef;
bogdanm 65:5798e58a58b1 321
bogdanm 65:5798e58a58b1 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
bogdanm 65:5798e58a58b1 323 typedef struct
bogdanm 65:5798e58a58b1 324 {
bogdanm 65:5798e58a58b1 325 union {
bogdanm 65:5798e58a58b1 326 __I uint8_t RBR;
bogdanm 65:5798e58a58b1 327 __O uint8_t THR;
bogdanm 65:5798e58a58b1 328 __IO uint8_t DLL;
bogdanm 65:5798e58a58b1 329 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 330 };
bogdanm 65:5798e58a58b1 331 union {
bogdanm 65:5798e58a58b1 332 __IO uint8_t DLM;
bogdanm 65:5798e58a58b1 333 __IO uint32_t IER;
bogdanm 65:5798e58a58b1 334 };
bogdanm 65:5798e58a58b1 335 union {
bogdanm 65:5798e58a58b1 336 __I uint32_t IIR;
bogdanm 65:5798e58a58b1 337 __O uint8_t FCR;
bogdanm 65:5798e58a58b1 338 };
bogdanm 65:5798e58a58b1 339 __IO uint8_t LCR;
bogdanm 65:5798e58a58b1 340 uint8_t RESERVED1[7];
bogdanm 65:5798e58a58b1 341 __I uint8_t LSR;
bogdanm 65:5798e58a58b1 342 uint8_t RESERVED2[7];
bogdanm 65:5798e58a58b1 343 __IO uint8_t SCR;
bogdanm 65:5798e58a58b1 344 uint8_t RESERVED3[3];
bogdanm 65:5798e58a58b1 345 __IO uint32_t ACR;
bogdanm 65:5798e58a58b1 346 __IO uint8_t ICR;
bogdanm 65:5798e58a58b1 347 uint8_t RESERVED4[3];
bogdanm 65:5798e58a58b1 348 __IO uint8_t FDR;
bogdanm 65:5798e58a58b1 349 uint8_t RESERVED5[7];
bogdanm 65:5798e58a58b1 350 __IO uint8_t TER;
bogdanm 65:5798e58a58b1 351 uint8_t RESERVED6[39];
bogdanm 65:5798e58a58b1 352 __IO uint32_t FIFOLVL;
bogdanm 65:5798e58a58b1 353 } LPC_UART_TypeDef;
bogdanm 65:5798e58a58b1 354
bogdanm 65:5798e58a58b1 355 typedef struct
bogdanm 65:5798e58a58b1 356 {
bogdanm 65:5798e58a58b1 357 union {
bogdanm 65:5798e58a58b1 358 __I uint8_t RBR;
bogdanm 65:5798e58a58b1 359 __O uint8_t THR;
bogdanm 65:5798e58a58b1 360 __IO uint8_t DLL;
bogdanm 65:5798e58a58b1 361 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 362 };
bogdanm 65:5798e58a58b1 363 union {
bogdanm 65:5798e58a58b1 364 __IO uint8_t DLM;
bogdanm 65:5798e58a58b1 365 __IO uint32_t IER;
bogdanm 65:5798e58a58b1 366 };
bogdanm 65:5798e58a58b1 367 union {
bogdanm 65:5798e58a58b1 368 __I uint32_t IIR;
bogdanm 65:5798e58a58b1 369 __O uint8_t FCR;
bogdanm 65:5798e58a58b1 370 };
bogdanm 65:5798e58a58b1 371 __IO uint8_t LCR;
bogdanm 65:5798e58a58b1 372 uint8_t RESERVED1[7];
bogdanm 65:5798e58a58b1 373 __I uint8_t LSR;
bogdanm 65:5798e58a58b1 374 uint8_t RESERVED2[7];
bogdanm 65:5798e58a58b1 375 __IO uint8_t SCR;
bogdanm 65:5798e58a58b1 376 uint8_t RESERVED3[3];
bogdanm 65:5798e58a58b1 377 __IO uint32_t ACR;
bogdanm 65:5798e58a58b1 378 __IO uint8_t ICR;
bogdanm 65:5798e58a58b1 379 uint8_t RESERVED4[3];
bogdanm 65:5798e58a58b1 380 __IO uint8_t FDR;
bogdanm 65:5798e58a58b1 381 uint8_t RESERVED5[7];
bogdanm 65:5798e58a58b1 382 __IO uint8_t TER;
bogdanm 65:5798e58a58b1 383 uint8_t RESERVED6[39];
bogdanm 65:5798e58a58b1 384 __IO uint32_t FIFOLVL;
bogdanm 65:5798e58a58b1 385 } LPC_UART0_TypeDef;
bogdanm 65:5798e58a58b1 386
bogdanm 65:5798e58a58b1 387 typedef struct
bogdanm 65:5798e58a58b1 388 {
bogdanm 65:5798e58a58b1 389 union {
bogdanm 65:5798e58a58b1 390 __I uint8_t RBR;
bogdanm 65:5798e58a58b1 391 __O uint8_t THR;
bogdanm 65:5798e58a58b1 392 __IO uint8_t DLL;
bogdanm 65:5798e58a58b1 393 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 394 };
bogdanm 65:5798e58a58b1 395 union {
bogdanm 65:5798e58a58b1 396 __IO uint8_t DLM;
bogdanm 65:5798e58a58b1 397 __IO uint32_t IER;
bogdanm 65:5798e58a58b1 398 };
bogdanm 65:5798e58a58b1 399 union {
bogdanm 65:5798e58a58b1 400 __I uint32_t IIR;
bogdanm 65:5798e58a58b1 401 __O uint8_t FCR;
bogdanm 65:5798e58a58b1 402 };
bogdanm 65:5798e58a58b1 403 __IO uint8_t LCR;
bogdanm 65:5798e58a58b1 404 uint8_t RESERVED1[3];
bogdanm 65:5798e58a58b1 405 __IO uint8_t MCR;
bogdanm 65:5798e58a58b1 406 uint8_t RESERVED2[3];
bogdanm 65:5798e58a58b1 407 __I uint8_t LSR;
bogdanm 65:5798e58a58b1 408 uint8_t RESERVED3[3];
bogdanm 65:5798e58a58b1 409 __I uint8_t MSR;
bogdanm 65:5798e58a58b1 410 uint8_t RESERVED4[3];
bogdanm 65:5798e58a58b1 411 __IO uint8_t SCR;
bogdanm 65:5798e58a58b1 412 uint8_t RESERVED5[3];
bogdanm 65:5798e58a58b1 413 __IO uint32_t ACR;
bogdanm 65:5798e58a58b1 414 uint32_t RESERVED6;
bogdanm 65:5798e58a58b1 415 __IO uint32_t FDR;
bogdanm 65:5798e58a58b1 416 uint32_t RESERVED7;
bogdanm 65:5798e58a58b1 417 __IO uint8_t TER;
bogdanm 65:5798e58a58b1 418 uint8_t RESERVED8[27];
bogdanm 65:5798e58a58b1 419 __IO uint8_t RS485CTRL;
bogdanm 65:5798e58a58b1 420 uint8_t RESERVED9[3];
bogdanm 65:5798e58a58b1 421 __IO uint8_t ADRMATCH;
bogdanm 65:5798e58a58b1 422 uint8_t RESERVED10[3];
bogdanm 65:5798e58a58b1 423 __IO uint8_t RS485DLY;
bogdanm 65:5798e58a58b1 424 uint8_t RESERVED11[3];
bogdanm 65:5798e58a58b1 425 __IO uint32_t FIFOLVL;
bogdanm 65:5798e58a58b1 426 } LPC_UART1_TypeDef;
bogdanm 65:5798e58a58b1 427
bogdanm 65:5798e58a58b1 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
bogdanm 65:5798e58a58b1 429 typedef struct
bogdanm 65:5798e58a58b1 430 {
bogdanm 65:5798e58a58b1 431 __IO uint32_t SPCR;
bogdanm 65:5798e58a58b1 432 __I uint32_t SPSR;
bogdanm 65:5798e58a58b1 433 __IO uint32_t SPDR;
bogdanm 65:5798e58a58b1 434 __IO uint32_t SPCCR;
bogdanm 65:5798e58a58b1 435 uint32_t RESERVED0[3];
bogdanm 65:5798e58a58b1 436 __IO uint32_t SPINT;
bogdanm 65:5798e58a58b1 437 } LPC_SPI_TypeDef;
bogdanm 65:5798e58a58b1 438
bogdanm 65:5798e58a58b1 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 65:5798e58a58b1 440 typedef struct
bogdanm 65:5798e58a58b1 441 {
bogdanm 65:5798e58a58b1 442 __IO uint32_t CR0;
bogdanm 65:5798e58a58b1 443 __IO uint32_t CR1;
bogdanm 65:5798e58a58b1 444 __IO uint32_t DR;
bogdanm 65:5798e58a58b1 445 __I uint32_t SR;
bogdanm 65:5798e58a58b1 446 __IO uint32_t CPSR;
bogdanm 65:5798e58a58b1 447 __IO uint32_t IMSC;
bogdanm 65:5798e58a58b1 448 __IO uint32_t RIS;
bogdanm 65:5798e58a58b1 449 __IO uint32_t MIS;
bogdanm 65:5798e58a58b1 450 __IO uint32_t ICR;
bogdanm 65:5798e58a58b1 451 __IO uint32_t DMACR;
bogdanm 65:5798e58a58b1 452 } LPC_SSP_TypeDef;
bogdanm 65:5798e58a58b1 453
bogdanm 65:5798e58a58b1 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 65:5798e58a58b1 455 typedef struct
bogdanm 65:5798e58a58b1 456 {
bogdanm 65:5798e58a58b1 457 __IO uint32_t I2CONSET;
bogdanm 65:5798e58a58b1 458 __I uint32_t I2STAT;
bogdanm 65:5798e58a58b1 459 __IO uint32_t I2DAT;
bogdanm 65:5798e58a58b1 460 __IO uint32_t I2ADR0;
bogdanm 65:5798e58a58b1 461 __IO uint32_t I2SCLH;
bogdanm 65:5798e58a58b1 462 __IO uint32_t I2SCLL;
bogdanm 65:5798e58a58b1 463 __O uint32_t I2CONCLR;
bogdanm 65:5798e58a58b1 464 __IO uint32_t MMCTRL;
bogdanm 65:5798e58a58b1 465 __IO uint32_t I2ADR1;
bogdanm 65:5798e58a58b1 466 __IO uint32_t I2ADR2;
bogdanm 65:5798e58a58b1 467 __IO uint32_t I2ADR3;
bogdanm 65:5798e58a58b1 468 __I uint32_t I2DATA_BUFFER;
bogdanm 65:5798e58a58b1 469 __IO uint32_t I2MASK0;
bogdanm 65:5798e58a58b1 470 __IO uint32_t I2MASK1;
bogdanm 65:5798e58a58b1 471 __IO uint32_t I2MASK2;
bogdanm 65:5798e58a58b1 472 __IO uint32_t I2MASK3;
bogdanm 65:5798e58a58b1 473 } LPC_I2C_TypeDef;
bogdanm 65:5798e58a58b1 474
bogdanm 65:5798e58a58b1 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
bogdanm 65:5798e58a58b1 476 typedef struct
bogdanm 65:5798e58a58b1 477 {
bogdanm 65:5798e58a58b1 478 __IO uint32_t I2SDAO;
bogdanm 65:5798e58a58b1 479 __IO uint32_t I2SDAI;
bogdanm 65:5798e58a58b1 480 __O uint32_t I2STXFIFO;
bogdanm 65:5798e58a58b1 481 __I uint32_t I2SRXFIFO;
bogdanm 65:5798e58a58b1 482 __I uint32_t I2SSTATE;
bogdanm 65:5798e58a58b1 483 __IO uint32_t I2SDMA1;
bogdanm 65:5798e58a58b1 484 __IO uint32_t I2SDMA2;
bogdanm 65:5798e58a58b1 485 __IO uint32_t I2SIRQ;
bogdanm 65:5798e58a58b1 486 __IO uint32_t I2STXRATE;
bogdanm 65:5798e58a58b1 487 __IO uint32_t I2SRXRATE;
bogdanm 65:5798e58a58b1 488 __IO uint32_t I2STXBITRATE;
bogdanm 65:5798e58a58b1 489 __IO uint32_t I2SRXBITRATE;
bogdanm 65:5798e58a58b1 490 __IO uint32_t I2STXMODE;
bogdanm 65:5798e58a58b1 491 __IO uint32_t I2SRXMODE;
bogdanm 65:5798e58a58b1 492 } LPC_I2S_TypeDef;
bogdanm 65:5798e58a58b1 493
bogdanm 65:5798e58a58b1 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
bogdanm 65:5798e58a58b1 495 typedef struct
bogdanm 65:5798e58a58b1 496 {
bogdanm 65:5798e58a58b1 497 __IO uint32_t RICOMPVAL;
bogdanm 65:5798e58a58b1 498 __IO uint32_t RIMASK;
bogdanm 65:5798e58a58b1 499 __IO uint8_t RICTRL;
bogdanm 65:5798e58a58b1 500 uint8_t RESERVED0[3];
bogdanm 65:5798e58a58b1 501 __IO uint32_t RICOUNTER;
bogdanm 65:5798e58a58b1 502 } LPC_RIT_TypeDef;
bogdanm 65:5798e58a58b1 503
bogdanm 65:5798e58a58b1 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
bogdanm 65:5798e58a58b1 505 typedef struct
bogdanm 65:5798e58a58b1 506 {
bogdanm 65:5798e58a58b1 507 __IO uint8_t ILR;
bogdanm 65:5798e58a58b1 508 uint8_t RESERVED0[7];
bogdanm 65:5798e58a58b1 509 __IO uint8_t CCR;
bogdanm 65:5798e58a58b1 510 uint8_t RESERVED1[3];
bogdanm 65:5798e58a58b1 511 __IO uint8_t CIIR;
bogdanm 65:5798e58a58b1 512 uint8_t RESERVED2[3];
bogdanm 65:5798e58a58b1 513 __IO uint8_t AMR;
bogdanm 65:5798e58a58b1 514 uint8_t RESERVED3[3];
bogdanm 65:5798e58a58b1 515 __I uint32_t CTIME0;
bogdanm 65:5798e58a58b1 516 __I uint32_t CTIME1;
bogdanm 65:5798e58a58b1 517 __I uint32_t CTIME2;
bogdanm 65:5798e58a58b1 518 __IO uint8_t SEC;
bogdanm 65:5798e58a58b1 519 uint8_t RESERVED4[3];
bogdanm 65:5798e58a58b1 520 __IO uint8_t MIN;
bogdanm 65:5798e58a58b1 521 uint8_t RESERVED5[3];
bogdanm 65:5798e58a58b1 522 __IO uint8_t HOUR;
bogdanm 65:5798e58a58b1 523 uint8_t RESERVED6[3];
bogdanm 65:5798e58a58b1 524 __IO uint8_t DOM;
bogdanm 65:5798e58a58b1 525 uint8_t RESERVED7[3];
bogdanm 65:5798e58a58b1 526 __IO uint8_t DOW;
bogdanm 65:5798e58a58b1 527 uint8_t RESERVED8[3];
bogdanm 65:5798e58a58b1 528 __IO uint16_t DOY;
bogdanm 65:5798e58a58b1 529 uint16_t RESERVED9;
bogdanm 65:5798e58a58b1 530 __IO uint8_t MONTH;
bogdanm 65:5798e58a58b1 531 uint8_t RESERVED10[3];
bogdanm 65:5798e58a58b1 532 __IO uint16_t YEAR;
bogdanm 65:5798e58a58b1 533 uint16_t RESERVED11;
bogdanm 65:5798e58a58b1 534 __IO uint32_t CALIBRATION;
bogdanm 65:5798e58a58b1 535 __IO uint32_t GPREG0;
bogdanm 65:5798e58a58b1 536 __IO uint32_t GPREG1;
bogdanm 65:5798e58a58b1 537 __IO uint32_t GPREG2;
bogdanm 65:5798e58a58b1 538 __IO uint32_t GPREG3;
bogdanm 65:5798e58a58b1 539 __IO uint32_t GPREG4;
bogdanm 65:5798e58a58b1 540 __IO uint8_t RTC_AUXEN;
bogdanm 65:5798e58a58b1 541 uint8_t RESERVED12[3];
bogdanm 65:5798e58a58b1 542 __IO uint8_t RTC_AUX;
bogdanm 65:5798e58a58b1 543 uint8_t RESERVED13[3];
bogdanm 65:5798e58a58b1 544 __IO uint8_t ALSEC;
bogdanm 65:5798e58a58b1 545 uint8_t RESERVED14[3];
bogdanm 65:5798e58a58b1 546 __IO uint8_t ALMIN;
bogdanm 65:5798e58a58b1 547 uint8_t RESERVED15[3];
bogdanm 65:5798e58a58b1 548 __IO uint8_t ALHOUR;
bogdanm 65:5798e58a58b1 549 uint8_t RESERVED16[3];
bogdanm 65:5798e58a58b1 550 __IO uint8_t ALDOM;
bogdanm 65:5798e58a58b1 551 uint8_t RESERVED17[3];
bogdanm 65:5798e58a58b1 552 __IO uint8_t ALDOW;
bogdanm 65:5798e58a58b1 553 uint8_t RESERVED18[3];
bogdanm 65:5798e58a58b1 554 __IO uint16_t ALDOY;
bogdanm 65:5798e58a58b1 555 uint16_t RESERVED19;
bogdanm 65:5798e58a58b1 556 __IO uint8_t ALMON;
bogdanm 65:5798e58a58b1 557 uint8_t RESERVED20[3];
bogdanm 65:5798e58a58b1 558 __IO uint16_t ALYEAR;
bogdanm 65:5798e58a58b1 559 uint16_t RESERVED21;
bogdanm 65:5798e58a58b1 560 } LPC_RTC_TypeDef;
bogdanm 65:5798e58a58b1 561
bogdanm 65:5798e58a58b1 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 65:5798e58a58b1 563 typedef struct
bogdanm 65:5798e58a58b1 564 {
bogdanm 65:5798e58a58b1 565 __IO uint8_t WDMOD;
bogdanm 65:5798e58a58b1 566 uint8_t RESERVED0[3];
bogdanm 65:5798e58a58b1 567 __IO uint32_t WDTC;
bogdanm 65:5798e58a58b1 568 __O uint8_t WDFEED;
bogdanm 65:5798e58a58b1 569 uint8_t RESERVED1[3];
bogdanm 65:5798e58a58b1 570 __I uint32_t WDTV;
bogdanm 65:5798e58a58b1 571 __IO uint32_t WDCLKSEL;
bogdanm 65:5798e58a58b1 572 } LPC_WDT_TypeDef;
bogdanm 65:5798e58a58b1 573
bogdanm 65:5798e58a58b1 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 65:5798e58a58b1 575 typedef struct
bogdanm 65:5798e58a58b1 576 {
bogdanm 65:5798e58a58b1 577 __IO uint32_t ADCR;
bogdanm 65:5798e58a58b1 578 __IO uint32_t ADGDR;
bogdanm 65:5798e58a58b1 579 uint32_t RESERVED0;
bogdanm 65:5798e58a58b1 580 __IO uint32_t ADINTEN;
bogdanm 65:5798e58a58b1 581 __I uint32_t ADDR0;
bogdanm 65:5798e58a58b1 582 __I uint32_t ADDR1;
bogdanm 65:5798e58a58b1 583 __I uint32_t ADDR2;
bogdanm 65:5798e58a58b1 584 __I uint32_t ADDR3;
bogdanm 65:5798e58a58b1 585 __I uint32_t ADDR4;
bogdanm 65:5798e58a58b1 586 __I uint32_t ADDR5;
bogdanm 65:5798e58a58b1 587 __I uint32_t ADDR6;
bogdanm 65:5798e58a58b1 588 __I uint32_t ADDR7;
bogdanm 65:5798e58a58b1 589 __I uint32_t ADSTAT;
bogdanm 65:5798e58a58b1 590 __IO uint32_t ADTRM;
bogdanm 65:5798e58a58b1 591 } LPC_ADC_TypeDef;
bogdanm 65:5798e58a58b1 592
bogdanm 65:5798e58a58b1 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
bogdanm 65:5798e58a58b1 594 typedef struct
bogdanm 65:5798e58a58b1 595 {
bogdanm 65:5798e58a58b1 596 __IO uint32_t DACR;
bogdanm 65:5798e58a58b1 597 __IO uint32_t DACCTRL;
bogdanm 65:5798e58a58b1 598 __IO uint16_t DACCNTVAL;
bogdanm 65:5798e58a58b1 599 } LPC_DAC_TypeDef;
bogdanm 65:5798e58a58b1 600
bogdanm 65:5798e58a58b1 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
bogdanm 65:5798e58a58b1 602 typedef struct
bogdanm 65:5798e58a58b1 603 {
bogdanm 65:5798e58a58b1 604 __I uint32_t MCCON;
bogdanm 65:5798e58a58b1 605 __O uint32_t MCCON_SET;
bogdanm 65:5798e58a58b1 606 __O uint32_t MCCON_CLR;
bogdanm 65:5798e58a58b1 607 __I uint32_t MCCAPCON;
bogdanm 65:5798e58a58b1 608 __O uint32_t MCCAPCON_SET;
bogdanm 65:5798e58a58b1 609 __O uint32_t MCCAPCON_CLR;
bogdanm 65:5798e58a58b1 610 __IO uint32_t MCTIM0;
bogdanm 65:5798e58a58b1 611 __IO uint32_t MCTIM1;
bogdanm 65:5798e58a58b1 612 __IO uint32_t MCTIM2;
bogdanm 65:5798e58a58b1 613 __IO uint32_t MCPER0;
bogdanm 65:5798e58a58b1 614 __IO uint32_t MCPER1;
bogdanm 65:5798e58a58b1 615 __IO uint32_t MCPER2;
bogdanm 65:5798e58a58b1 616 __IO uint32_t MCPW0;
bogdanm 65:5798e58a58b1 617 __IO uint32_t MCPW1;
bogdanm 65:5798e58a58b1 618 __IO uint32_t MCPW2;
bogdanm 65:5798e58a58b1 619 __IO uint32_t MCDEADTIME;
bogdanm 65:5798e58a58b1 620 __IO uint32_t MCCCP;
bogdanm 65:5798e58a58b1 621 __IO uint32_t MCCR0;
bogdanm 65:5798e58a58b1 622 __IO uint32_t MCCR1;
bogdanm 65:5798e58a58b1 623 __IO uint32_t MCCR2;
bogdanm 65:5798e58a58b1 624 __I uint32_t MCINTEN;
bogdanm 65:5798e58a58b1 625 __O uint32_t MCINTEN_SET;
bogdanm 65:5798e58a58b1 626 __O uint32_t MCINTEN_CLR;
bogdanm 65:5798e58a58b1 627 __I uint32_t MCCNTCON;
bogdanm 65:5798e58a58b1 628 __O uint32_t MCCNTCON_SET;
bogdanm 65:5798e58a58b1 629 __O uint32_t MCCNTCON_CLR;
bogdanm 65:5798e58a58b1 630 __I uint32_t MCINTFLAG;
bogdanm 65:5798e58a58b1 631 __O uint32_t MCINTFLAG_SET;
bogdanm 65:5798e58a58b1 632 __O uint32_t MCINTFLAG_CLR;
bogdanm 65:5798e58a58b1 633 __O uint32_t MCCAP_CLR;
bogdanm 65:5798e58a58b1 634 } LPC_MCPWM_TypeDef;
bogdanm 65:5798e58a58b1 635
bogdanm 65:5798e58a58b1 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
bogdanm 65:5798e58a58b1 637 typedef struct
bogdanm 65:5798e58a58b1 638 {
bogdanm 65:5798e58a58b1 639 __O uint32_t QEICON;
bogdanm 65:5798e58a58b1 640 __I uint32_t QEISTAT;
bogdanm 65:5798e58a58b1 641 __IO uint32_t QEICONF;
bogdanm 65:5798e58a58b1 642 __I uint32_t QEIPOS;
bogdanm 65:5798e58a58b1 643 __IO uint32_t QEIMAXPOS;
bogdanm 65:5798e58a58b1 644 __IO uint32_t CMPOS0;
bogdanm 65:5798e58a58b1 645 __IO uint32_t CMPOS1;
bogdanm 65:5798e58a58b1 646 __IO uint32_t CMPOS2;
bogdanm 65:5798e58a58b1 647 __I uint32_t INXCNT;
bogdanm 65:5798e58a58b1 648 __IO uint32_t INXCMP;
bogdanm 65:5798e58a58b1 649 __IO uint32_t QEILOAD;
bogdanm 65:5798e58a58b1 650 __I uint32_t QEITIME;
bogdanm 65:5798e58a58b1 651 __I uint32_t QEIVEL;
bogdanm 65:5798e58a58b1 652 __I uint32_t QEICAP;
bogdanm 65:5798e58a58b1 653 __IO uint32_t VELCOMP;
bogdanm 65:5798e58a58b1 654 __IO uint32_t FILTER;
bogdanm 65:5798e58a58b1 655 uint32_t RESERVED0[998];
bogdanm 65:5798e58a58b1 656 __O uint32_t QEIIEC;
bogdanm 65:5798e58a58b1 657 __O uint32_t QEIIES;
bogdanm 65:5798e58a58b1 658 __I uint32_t QEIINTSTAT;
bogdanm 65:5798e58a58b1 659 __I uint32_t QEIIE;
bogdanm 65:5798e58a58b1 660 __O uint32_t QEICLR;
bogdanm 65:5798e58a58b1 661 __O uint32_t QEISET;
bogdanm 65:5798e58a58b1 662 } LPC_QEI_TypeDef;
bogdanm 65:5798e58a58b1 663
bogdanm 65:5798e58a58b1 664 /*------------- Controller Area Network (CAN) --------------------------------*/
bogdanm 65:5798e58a58b1 665 typedef struct
bogdanm 65:5798e58a58b1 666 {
bogdanm 65:5798e58a58b1 667 __IO uint32_t mask[512]; /* ID Masks */
bogdanm 65:5798e58a58b1 668 } LPC_CANAF_RAM_TypeDef;
bogdanm 65:5798e58a58b1 669
bogdanm 65:5798e58a58b1 670 typedef struct /* Acceptance Filter Registers */
bogdanm 65:5798e58a58b1 671 {
bogdanm 65:5798e58a58b1 672 __IO uint32_t AFMR;
bogdanm 65:5798e58a58b1 673 __IO uint32_t SFF_sa;
bogdanm 65:5798e58a58b1 674 __IO uint32_t SFF_GRP_sa;
bogdanm 65:5798e58a58b1 675 __IO uint32_t EFF_sa;
bogdanm 65:5798e58a58b1 676 __IO uint32_t EFF_GRP_sa;
bogdanm 65:5798e58a58b1 677 __IO uint32_t ENDofTable;
bogdanm 65:5798e58a58b1 678 __I uint32_t LUTerrAd;
bogdanm 65:5798e58a58b1 679 __I uint32_t LUTerr;
bogdanm 65:5798e58a58b1 680 __IO uint32_t FCANIE;
bogdanm 65:5798e58a58b1 681 __IO uint32_t FCANIC0;
bogdanm 65:5798e58a58b1 682 __IO uint32_t FCANIC1;
bogdanm 65:5798e58a58b1 683 } LPC_CANAF_TypeDef;
bogdanm 65:5798e58a58b1 684
bogdanm 65:5798e58a58b1 685 typedef struct /* Central Registers */
bogdanm 65:5798e58a58b1 686 {
bogdanm 65:5798e58a58b1 687 __I uint32_t CANTxSR;
bogdanm 65:5798e58a58b1 688 __I uint32_t CANRxSR;
bogdanm 65:5798e58a58b1 689 __I uint32_t CANMSR;
bogdanm 65:5798e58a58b1 690 } LPC_CANCR_TypeDef;
bogdanm 65:5798e58a58b1 691
bogdanm 65:5798e58a58b1 692 typedef struct /* Controller Registers */
bogdanm 65:5798e58a58b1 693 {
bogdanm 65:5798e58a58b1 694 __IO uint32_t MOD;
bogdanm 65:5798e58a58b1 695 __O uint32_t CMR;
bogdanm 65:5798e58a58b1 696 __IO uint32_t GSR;
bogdanm 65:5798e58a58b1 697 __I uint32_t ICR;
bogdanm 65:5798e58a58b1 698 __IO uint32_t IER;
bogdanm 65:5798e58a58b1 699 __IO uint32_t BTR;
bogdanm 65:5798e58a58b1 700 __IO uint32_t EWL;
bogdanm 65:5798e58a58b1 701 __I uint32_t SR;
bogdanm 65:5798e58a58b1 702 __IO uint32_t RFS;
bogdanm 65:5798e58a58b1 703 __IO uint32_t RID;
bogdanm 65:5798e58a58b1 704 __IO uint32_t RDA;
bogdanm 65:5798e58a58b1 705 __IO uint32_t RDB;
bogdanm 65:5798e58a58b1 706 __IO uint32_t TFI1;
bogdanm 65:5798e58a58b1 707 __IO uint32_t TID1;
bogdanm 65:5798e58a58b1 708 __IO uint32_t TDA1;
bogdanm 65:5798e58a58b1 709 __IO uint32_t TDB1;
bogdanm 65:5798e58a58b1 710 __IO uint32_t TFI2;
bogdanm 65:5798e58a58b1 711 __IO uint32_t TID2;
bogdanm 65:5798e58a58b1 712 __IO uint32_t TDA2;
bogdanm 65:5798e58a58b1 713 __IO uint32_t TDB2;
bogdanm 65:5798e58a58b1 714 __IO uint32_t TFI3;
bogdanm 65:5798e58a58b1 715 __IO uint32_t TID3;
bogdanm 65:5798e58a58b1 716 __IO uint32_t TDA3;
bogdanm 65:5798e58a58b1 717 __IO uint32_t TDB3;
bogdanm 65:5798e58a58b1 718 } LPC_CAN_TypeDef;
bogdanm 65:5798e58a58b1 719
bogdanm 65:5798e58a58b1 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
bogdanm 65:5798e58a58b1 721 typedef struct /* Common Registers */
bogdanm 65:5798e58a58b1 722 {
bogdanm 65:5798e58a58b1 723 __I uint32_t DMACIntStat;
bogdanm 65:5798e58a58b1 724 __I uint32_t DMACIntTCStat;
bogdanm 65:5798e58a58b1 725 __O uint32_t DMACIntTCClear;
bogdanm 65:5798e58a58b1 726 __I uint32_t DMACIntErrStat;
bogdanm 65:5798e58a58b1 727 __O uint32_t DMACIntErrClr;
bogdanm 65:5798e58a58b1 728 __I uint32_t DMACRawIntTCStat;
bogdanm 65:5798e58a58b1 729 __I uint32_t DMACRawIntErrStat;
bogdanm 65:5798e58a58b1 730 __I uint32_t DMACEnbldChns;
bogdanm 65:5798e58a58b1 731 __IO uint32_t DMACSoftBReq;
bogdanm 65:5798e58a58b1 732 __IO uint32_t DMACSoftSReq;
bogdanm 65:5798e58a58b1 733 __IO uint32_t DMACSoftLBReq;
bogdanm 65:5798e58a58b1 734 __IO uint32_t DMACSoftLSReq;
bogdanm 65:5798e58a58b1 735 __IO uint32_t DMACConfig;
bogdanm 65:5798e58a58b1 736 __IO uint32_t DMACSync;
bogdanm 65:5798e58a58b1 737 } LPC_GPDMA_TypeDef;
bogdanm 65:5798e58a58b1 738
bogdanm 65:5798e58a58b1 739 typedef struct /* Channel Registers */
bogdanm 65:5798e58a58b1 740 {
bogdanm 65:5798e58a58b1 741 __IO uint32_t DMACCSrcAddr;
bogdanm 65:5798e58a58b1 742 __IO uint32_t DMACCDestAddr;
bogdanm 65:5798e58a58b1 743 __IO uint32_t DMACCLLI;
bogdanm 65:5798e58a58b1 744 __IO uint32_t DMACCControl;
bogdanm 65:5798e58a58b1 745 __IO uint32_t DMACCConfig;
bogdanm 65:5798e58a58b1 746 } LPC_GPDMACH_TypeDef;
bogdanm 65:5798e58a58b1 747
bogdanm 65:5798e58a58b1 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
bogdanm 65:5798e58a58b1 749 typedef struct
bogdanm 65:5798e58a58b1 750 {
bogdanm 65:5798e58a58b1 751 __I uint32_t HcRevision; /* USB Host Registers */
bogdanm 65:5798e58a58b1 752 __IO uint32_t HcControl;
bogdanm 65:5798e58a58b1 753 __IO uint32_t HcCommandStatus;
bogdanm 65:5798e58a58b1 754 __IO uint32_t HcInterruptStatus;
bogdanm 65:5798e58a58b1 755 __IO uint32_t HcInterruptEnable;
bogdanm 65:5798e58a58b1 756 __IO uint32_t HcInterruptDisable;
bogdanm 65:5798e58a58b1 757 __IO uint32_t HcHCCA;
bogdanm 65:5798e58a58b1 758 __I uint32_t HcPeriodCurrentED;
bogdanm 65:5798e58a58b1 759 __IO uint32_t HcControlHeadED;
bogdanm 65:5798e58a58b1 760 __IO uint32_t HcControlCurrentED;
bogdanm 65:5798e58a58b1 761 __IO uint32_t HcBulkHeadED;
bogdanm 65:5798e58a58b1 762 __IO uint32_t HcBulkCurrentED;
bogdanm 65:5798e58a58b1 763 __I uint32_t HcDoneHead;
bogdanm 65:5798e58a58b1 764 __IO uint32_t HcFmInterval;
bogdanm 65:5798e58a58b1 765 __I uint32_t HcFmRemaining;
bogdanm 65:5798e58a58b1 766 __I uint32_t HcFmNumber;
bogdanm 65:5798e58a58b1 767 __IO uint32_t HcPeriodicStart;
bogdanm 65:5798e58a58b1 768 __IO uint32_t HcLSTreshold;
bogdanm 65:5798e58a58b1 769 __IO uint32_t HcRhDescriptorA;
bogdanm 65:5798e58a58b1 770 __IO uint32_t HcRhDescriptorB;
bogdanm 65:5798e58a58b1 771 __IO uint32_t HcRhStatus;
bogdanm 65:5798e58a58b1 772 __IO uint32_t HcRhPortStatus1;
bogdanm 65:5798e58a58b1 773 __IO uint32_t HcRhPortStatus2;
bogdanm 65:5798e58a58b1 774 uint32_t RESERVED0[40];
bogdanm 65:5798e58a58b1 775 __I uint32_t Module_ID;
bogdanm 65:5798e58a58b1 776
bogdanm 65:5798e58a58b1 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
bogdanm 65:5798e58a58b1 778 __IO uint32_t OTGIntEn;
bogdanm 65:5798e58a58b1 779 __O uint32_t OTGIntSet;
bogdanm 65:5798e58a58b1 780 __O uint32_t OTGIntClr;
bogdanm 65:5798e58a58b1 781 __IO uint32_t OTGStCtrl;
bogdanm 65:5798e58a58b1 782 __IO uint32_t OTGTmr;
bogdanm 65:5798e58a58b1 783 uint32_t RESERVED1[58];
bogdanm 65:5798e58a58b1 784
bogdanm 65:5798e58a58b1 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
bogdanm 65:5798e58a58b1 786 __IO uint32_t USBDevIntEn;
bogdanm 65:5798e58a58b1 787 __O uint32_t USBDevIntClr;
bogdanm 65:5798e58a58b1 788 __O uint32_t USBDevIntSet;
bogdanm 65:5798e58a58b1 789
bogdanm 65:5798e58a58b1 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
bogdanm 65:5798e58a58b1 791 __I uint32_t USBCmdData;
bogdanm 65:5798e58a58b1 792
bogdanm 65:5798e58a58b1 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
bogdanm 65:5798e58a58b1 794 __O uint32_t USBTxData;
bogdanm 65:5798e58a58b1 795 __I uint32_t USBRxPLen;
bogdanm 65:5798e58a58b1 796 __O uint32_t USBTxPLen;
bogdanm 65:5798e58a58b1 797 __IO uint32_t USBCtrl;
bogdanm 65:5798e58a58b1 798 __O uint32_t USBDevIntPri;
bogdanm 65:5798e58a58b1 799
bogdanm 65:5798e58a58b1 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
bogdanm 65:5798e58a58b1 801 __IO uint32_t USBEpIntEn;
bogdanm 65:5798e58a58b1 802 __O uint32_t USBEpIntClr;
bogdanm 65:5798e58a58b1 803 __O uint32_t USBEpIntSet;
bogdanm 65:5798e58a58b1 804 __O uint32_t USBEpIntPri;
bogdanm 65:5798e58a58b1 805
bogdanm 65:5798e58a58b1 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
bogdanm 65:5798e58a58b1 807 __O uint32_t USBEpInd;
bogdanm 65:5798e58a58b1 808 __IO uint32_t USBMaxPSize;
bogdanm 65:5798e58a58b1 809
bogdanm 65:5798e58a58b1 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
bogdanm 65:5798e58a58b1 811 __O uint32_t USBDMARClr;
bogdanm 65:5798e58a58b1 812 __O uint32_t USBDMARSet;
bogdanm 65:5798e58a58b1 813 uint32_t RESERVED2[9];
bogdanm 65:5798e58a58b1 814 __IO uint32_t USBUDCAH;
bogdanm 65:5798e58a58b1 815 __I uint32_t USBEpDMASt;
bogdanm 65:5798e58a58b1 816 __O uint32_t USBEpDMAEn;
bogdanm 65:5798e58a58b1 817 __O uint32_t USBEpDMADis;
bogdanm 65:5798e58a58b1 818 __I uint32_t USBDMAIntSt;
bogdanm 65:5798e58a58b1 819 __IO uint32_t USBDMAIntEn;
bogdanm 65:5798e58a58b1 820 uint32_t RESERVED3[2];
bogdanm 65:5798e58a58b1 821 __I uint32_t USBEoTIntSt;
bogdanm 65:5798e58a58b1 822 __O uint32_t USBEoTIntClr;
bogdanm 65:5798e58a58b1 823 __O uint32_t USBEoTIntSet;
bogdanm 65:5798e58a58b1 824 __I uint32_t USBNDDRIntSt;
bogdanm 65:5798e58a58b1 825 __O uint32_t USBNDDRIntClr;
bogdanm 65:5798e58a58b1 826 __O uint32_t USBNDDRIntSet;
bogdanm 65:5798e58a58b1 827 __I uint32_t USBSysErrIntSt;
bogdanm 65:5798e58a58b1 828 __O uint32_t USBSysErrIntClr;
bogdanm 65:5798e58a58b1 829 __O uint32_t USBSysErrIntSet;
bogdanm 65:5798e58a58b1 830 uint32_t RESERVED4[15];
bogdanm 65:5798e58a58b1 831
bogdanm 65:5798e58a58b1 832 union {
bogdanm 65:5798e58a58b1 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
bogdanm 65:5798e58a58b1 834 __O uint32_t I2C_TX;
bogdanm 65:5798e58a58b1 835 };
bogdanm 65:5798e58a58b1 836 __I uint32_t I2C_STS;
bogdanm 65:5798e58a58b1 837 __IO uint32_t I2C_CTL;
bogdanm 65:5798e58a58b1 838 __IO uint32_t I2C_CLKHI;
bogdanm 65:5798e58a58b1 839 __O uint32_t I2C_CLKLO;
bogdanm 65:5798e58a58b1 840 uint32_t RESERVED5[824];
bogdanm 65:5798e58a58b1 841
bogdanm 65:5798e58a58b1 842 union {
bogdanm 65:5798e58a58b1 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
bogdanm 65:5798e58a58b1 844 __IO uint32_t OTGClkCtrl;
bogdanm 65:5798e58a58b1 845 };
bogdanm 65:5798e58a58b1 846 union {
bogdanm 65:5798e58a58b1 847 __I uint32_t USBClkSt;
bogdanm 65:5798e58a58b1 848 __I uint32_t OTGClkSt;
bogdanm 65:5798e58a58b1 849 };
bogdanm 65:5798e58a58b1 850 } LPC_USB_TypeDef;
bogdanm 65:5798e58a58b1 851
bogdanm 65:5798e58a58b1 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
bogdanm 65:5798e58a58b1 853 typedef struct
bogdanm 65:5798e58a58b1 854 {
bogdanm 65:5798e58a58b1 855 __IO uint32_t MAC1; /* MAC Registers */
bogdanm 65:5798e58a58b1 856 __IO uint32_t MAC2;
bogdanm 65:5798e58a58b1 857 __IO uint32_t IPGT;
bogdanm 65:5798e58a58b1 858 __IO uint32_t IPGR;
bogdanm 65:5798e58a58b1 859 __IO uint32_t CLRT;
bogdanm 65:5798e58a58b1 860 __IO uint32_t MAXF;
bogdanm 65:5798e58a58b1 861 __IO uint32_t SUPP;
bogdanm 65:5798e58a58b1 862 __IO uint32_t TEST;
bogdanm 65:5798e58a58b1 863 __IO uint32_t MCFG;
bogdanm 65:5798e58a58b1 864 __IO uint32_t MCMD;
bogdanm 65:5798e58a58b1 865 __IO uint32_t MADR;
bogdanm 65:5798e58a58b1 866 __O uint32_t MWTD;
bogdanm 65:5798e58a58b1 867 __I uint32_t MRDD;
bogdanm 65:5798e58a58b1 868 __I uint32_t MIND;
bogdanm 65:5798e58a58b1 869 uint32_t RESERVED0[2];
bogdanm 65:5798e58a58b1 870 __IO uint32_t SA0;
bogdanm 65:5798e58a58b1 871 __IO uint32_t SA1;
bogdanm 65:5798e58a58b1 872 __IO uint32_t SA2;
bogdanm 65:5798e58a58b1 873 uint32_t RESERVED1[45];
bogdanm 65:5798e58a58b1 874 __IO uint32_t Command; /* Control Registers */
bogdanm 65:5798e58a58b1 875 __I uint32_t Status;
bogdanm 65:5798e58a58b1 876 __IO uint32_t RxDescriptor;
bogdanm 65:5798e58a58b1 877 __IO uint32_t RxStatus;
bogdanm 65:5798e58a58b1 878 __IO uint32_t RxDescriptorNumber;
bogdanm 65:5798e58a58b1 879 __I uint32_t RxProduceIndex;
bogdanm 65:5798e58a58b1 880 __IO uint32_t RxConsumeIndex;
bogdanm 65:5798e58a58b1 881 __IO uint32_t TxDescriptor;
bogdanm 65:5798e58a58b1 882 __IO uint32_t TxStatus;
bogdanm 65:5798e58a58b1 883 __IO uint32_t TxDescriptorNumber;
bogdanm 65:5798e58a58b1 884 __IO uint32_t TxProduceIndex;
bogdanm 65:5798e58a58b1 885 __I uint32_t TxConsumeIndex;
bogdanm 65:5798e58a58b1 886 uint32_t RESERVED2[10];
bogdanm 65:5798e58a58b1 887 __I uint32_t TSV0;
bogdanm 65:5798e58a58b1 888 __I uint32_t TSV1;
bogdanm 65:5798e58a58b1 889 __I uint32_t RSV;
bogdanm 65:5798e58a58b1 890 uint32_t RESERVED3[3];
bogdanm 65:5798e58a58b1 891 __IO uint32_t FlowControlCounter;
bogdanm 65:5798e58a58b1 892 __I uint32_t FlowControlStatus;
bogdanm 65:5798e58a58b1 893 uint32_t RESERVED4[34];
bogdanm 65:5798e58a58b1 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
bogdanm 65:5798e58a58b1 895 __IO uint32_t RxFilterWoLStatus;
bogdanm 65:5798e58a58b1 896 __IO uint32_t RxFilterWoLClear;
bogdanm 65:5798e58a58b1 897 uint32_t RESERVED5;
bogdanm 65:5798e58a58b1 898 __IO uint32_t HashFilterL;
bogdanm 65:5798e58a58b1 899 __IO uint32_t HashFilterH;
bogdanm 65:5798e58a58b1 900 uint32_t RESERVED6[882];
bogdanm 65:5798e58a58b1 901 __I uint32_t IntStatus; /* Module Control Registers */
bogdanm 65:5798e58a58b1 902 __IO uint32_t IntEnable;
bogdanm 65:5798e58a58b1 903 __O uint32_t IntClear;
bogdanm 65:5798e58a58b1 904 __O uint32_t IntSet;
bogdanm 65:5798e58a58b1 905 uint32_t RESERVED7;
bogdanm 65:5798e58a58b1 906 __IO uint32_t PowerDown;
bogdanm 65:5798e58a58b1 907 uint32_t RESERVED8;
bogdanm 65:5798e58a58b1 908 __IO uint32_t Module_ID;
bogdanm 65:5798e58a58b1 909 } LPC_EMAC_TypeDef;
bogdanm 65:5798e58a58b1 910
bogdanm 65:5798e58a58b1 911 #if defined ( __CC_ARM )
bogdanm 65:5798e58a58b1 912 #pragma no_anon_unions
bogdanm 65:5798e58a58b1 913 #endif
bogdanm 65:5798e58a58b1 914
bogdanm 65:5798e58a58b1 915
bogdanm 65:5798e58a58b1 916 /******************************************************************************/
bogdanm 65:5798e58a58b1 917 /* Peripheral memory map */
bogdanm 65:5798e58a58b1 918 /******************************************************************************/
bogdanm 65:5798e58a58b1 919 /* Base addresses */
bogdanm 65:5798e58a58b1 920 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 65:5798e58a58b1 921 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 65:5798e58a58b1 922 #define LPC_GPIO_BASE (0x2009C000UL)
bogdanm 65:5798e58a58b1 923 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 65:5798e58a58b1 924 #define LPC_APB1_BASE (0x40080000UL)
bogdanm 65:5798e58a58b1 925 #define LPC_AHB_BASE (0x50000000UL)
bogdanm 65:5798e58a58b1 926 #define LPC_CM3_BASE (0xE0000000UL)
bogdanm 65:5798e58a58b1 927
bogdanm 65:5798e58a58b1 928 /* APB0 peripherals */
bogdanm 65:5798e58a58b1 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 65:5798e58a58b1 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 65:5798e58a58b1 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 65:5798e58a58b1 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 65:5798e58a58b1 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
bogdanm 65:5798e58a58b1 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
bogdanm 65:5798e58a58b1 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
bogdanm 65:5798e58a58b1 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
bogdanm 65:5798e58a58b1 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
bogdanm 65:5798e58a58b1 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
bogdanm 65:5798e58a58b1 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
bogdanm 65:5798e58a58b1 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
bogdanm 65:5798e58a58b1 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
bogdanm 65:5798e58a58b1 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
bogdanm 65:5798e58a58b1 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
bogdanm 65:5798e58a58b1 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 65:5798e58a58b1 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 65:5798e58a58b1 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 65:5798e58a58b1 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
bogdanm 65:5798e58a58b1 948
bogdanm 65:5798e58a58b1 949 /* APB1 peripherals */
bogdanm 65:5798e58a58b1 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
bogdanm 65:5798e58a58b1 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
bogdanm 65:5798e58a58b1 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
bogdanm 65:5798e58a58b1 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
bogdanm 65:5798e58a58b1 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
bogdanm 65:5798e58a58b1 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
bogdanm 65:5798e58a58b1 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
bogdanm 65:5798e58a58b1 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
bogdanm 65:5798e58a58b1 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
bogdanm 65:5798e58a58b1 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
bogdanm 65:5798e58a58b1 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
bogdanm 65:5798e58a58b1 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
bogdanm 65:5798e58a58b1 962
bogdanm 65:5798e58a58b1 963 /* AHB peripherals */
bogdanm 65:5798e58a58b1 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 65:5798e58a58b1 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
bogdanm 65:5798e58a58b1 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
bogdanm 65:5798e58a58b1 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
bogdanm 65:5798e58a58b1 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
bogdanm 65:5798e58a58b1 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
bogdanm 65:5798e58a58b1 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
bogdanm 65:5798e58a58b1 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
bogdanm 65:5798e58a58b1 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
bogdanm 65:5798e58a58b1 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
bogdanm 65:5798e58a58b1 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
bogdanm 65:5798e58a58b1 975
bogdanm 65:5798e58a58b1 976 /* GPIOs */
bogdanm 65:5798e58a58b1 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
bogdanm 65:5798e58a58b1 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
bogdanm 65:5798e58a58b1 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
bogdanm 65:5798e58a58b1 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
bogdanm 65:5798e58a58b1 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
bogdanm 65:5798e58a58b1 982
bogdanm 65:5798e58a58b1 983
bogdanm 65:5798e58a58b1 984 /******************************************************************************/
bogdanm 65:5798e58a58b1 985 /* Peripheral declaration */
bogdanm 65:5798e58a58b1 986 /******************************************************************************/
bogdanm 65:5798e58a58b1 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
bogdanm 65:5798e58a58b1 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
bogdanm 65:5798e58a58b1 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
bogdanm 65:5798e58a58b1 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
bogdanm 65:5798e58a58b1 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
bogdanm 65:5798e58a58b1 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
bogdanm 65:5798e58a58b1 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
bogdanm 65:5798e58a58b1 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
bogdanm 65:5798e58a58b1 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
bogdanm 65:5798e58a58b1 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
bogdanm 65:5798e58a58b1 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
bogdanm 65:5798e58a58b1 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
bogdanm 65:5798e58a58b1 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
bogdanm 65:5798e58a58b1 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
bogdanm 65:5798e58a58b1 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
bogdanm 65:5798e58a58b1 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
bogdanm 65:5798e58a58b1 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
bogdanm 65:5798e58a58b1 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
bogdanm 65:5798e58a58b1 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
bogdanm 65:5798e58a58b1 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
bogdanm 65:5798e58a58b1 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
bogdanm 65:5798e58a58b1 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
bogdanm 65:5798e58a58b1 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
bogdanm 65:5798e58a58b1 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
bogdanm 65:5798e58a58b1 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
bogdanm 65:5798e58a58b1 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
bogdanm 65:5798e58a58b1 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
bogdanm 65:5798e58a58b1 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
bogdanm 65:5798e58a58b1 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
bogdanm 65:5798e58a58b1 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
bogdanm 65:5798e58a58b1 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
bogdanm 65:5798e58a58b1 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
bogdanm 65:5798e58a58b1 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
bogdanm 65:5798e58a58b1 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
bogdanm 65:5798e58a58b1 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
bogdanm 65:5798e58a58b1 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
bogdanm 65:5798e58a58b1 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
bogdanm 65:5798e58a58b1 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
bogdanm 65:5798e58a58b1 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
bogdanm 65:5798e58a58b1 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
bogdanm 65:5798e58a58b1 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
bogdanm 65:5798e58a58b1 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
bogdanm 65:5798e58a58b1 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
bogdanm 65:5798e58a58b1 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
bogdanm 65:5798e58a58b1 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
bogdanm 65:5798e58a58b1 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
bogdanm 65:5798e58a58b1 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
bogdanm 65:5798e58a58b1 1034
bogdanm 65:5798e58a58b1 1035 #endif // __LPC17xx_H__