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TARGET_LPC11U24/cmsis_nvic.h@65:5798e58a58b1, 2013-08-12 (annotated)
- Committer:
- bogdanm
- Date:
- Mon Aug 12 13:17:46 2013 +0300
- Revision:
- 65:5798e58a58b1
- Parent:
- 64:e3affc9e7238
- Child:
- 66:9c8f0e3462fb
New target (LPC4088), new features (interrupt chaining), bug fixes (KL25Z I2C).
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
emilmont | 40:976df7c37ad5 | 1 | /* mbed Microcontroller Library - cmsis_nvic |
emilmont | 40:976df7c37ad5 | 2 | * Copyright (c) 2009-2011 ARM Limited. All rights reserved. |
emilmont | 40:976df7c37ad5 | 3 | * |
emilmont | 40:976df7c37ad5 | 4 | * CMSIS-style functionality to support dynamic vectors |
emilmont | 40:976df7c37ad5 | 5 | */ |
emilmont | 40:976df7c37ad5 | 6 | |
emilmont | 40:976df7c37ad5 | 7 | #ifndef MBED_CMSIS_NVIC_H |
emilmont | 40:976df7c37ad5 | 8 | #define MBED_CMSIS_NVIC_H |
emilmont | 40:976df7c37ad5 | 9 | |
emilmont | 40:976df7c37ad5 | 10 | #include "cmsis.h" |
emilmont | 40:976df7c37ad5 | 11 | |
bogdanm | 65:5798e58a58b1 | 12 | #define NVIC_NUM_VECTORS (16 + 32) // CORE + MCU Peripherals |
bogdanm | 65:5798e58a58b1 | 13 | #define NVIC_USER_IRQ_OFFSET 16 |
bogdanm | 65:5798e58a58b1 | 14 | |
emilmont | 40:976df7c37ad5 | 15 | #ifdef __cplusplus |
emilmont | 40:976df7c37ad5 | 16 | extern "C" { |
emilmont | 40:976df7c37ad5 | 17 | #endif |
emilmont | 40:976df7c37ad5 | 18 | |
emilmont | 40:976df7c37ad5 | 19 | void NVIC_SetVector(IRQn_Type IRQn, uint32_t vector); |
emilmont | 40:976df7c37ad5 | 20 | uint32_t NVIC_GetVector(IRQn_Type IRQn); |
emilmont | 40:976df7c37ad5 | 21 | |
emilmont | 40:976df7c37ad5 | 22 | #ifdef __cplusplus |
emilmont | 40:976df7c37ad5 | 23 | } |
emilmont | 40:976df7c37ad5 | 24 | #endif |
emilmont | 40:976df7c37ad5 | 25 | |
emilmont | 40:976df7c37ad5 | 26 | #endif |