mbed - my fork

Users » filartrix » Code » mbed

my fork

TARGET_NUCLEO_L053R8/stm32l0xx_hal_tim.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Committer:: bogdanm
Date:: Thu Nov 27 13:33:22 2014 +0000
Revision:: 92:4fc01daae5a5
Parent:: 84:0b3ab51c8877
Child:: 96:487b796308b0

Release 92 of the mbed libray



Main changes:



- nRF51822: fixed pin assignment issues

- ST targets moving to the STM32Cube driver

- LPC1439: fixed serial interrupt issue

- first Cortex-A platform supported in mbed (RZ_A1H)

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	84:0b3ab51c8877	1	/**
bogdanm	84:0b3ab51c8877	2	******************************************************************************
bogdanm	84:0b3ab51c8877	3	* @file stm32l0xx_hal_tim.h
bogdanm	84:0b3ab51c8877	4	* @author MCD Application Team
bogdanm	92:4fc01daae5a5	5	* @version V1.1.0
bogdanm	92:4fc01daae5a5	6	* @date 18-June-2014
bogdanm	84:0b3ab51c8877	7	* @brief Header file of TIM HAL module.
bogdanm	84:0b3ab51c8877	8	******************************************************************************
bogdanm	84:0b3ab51c8877	9	* @attention
bogdanm	84:0b3ab51c8877	10	*
bogdanm	84:0b3ab51c8877	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	84:0b3ab51c8877	12	*
bogdanm	84:0b3ab51c8877	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	84:0b3ab51c8877	14	* are permitted provided that the following conditions are met:
bogdanm	84:0b3ab51c8877	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	84:0b3ab51c8877	16	* this list of conditions and the following disclaimer.
bogdanm	84:0b3ab51c8877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	84:0b3ab51c8877	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	84:0b3ab51c8877	19	* and/or other materials provided with the distribution.
bogdanm	84:0b3ab51c8877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	84:0b3ab51c8877	21	* may be used to endorse or promote products derived from this software
bogdanm	84:0b3ab51c8877	22	* without specific prior written permission.
bogdanm	84:0b3ab51c8877	23	*
bogdanm	84:0b3ab51c8877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	84:0b3ab51c8877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	84:0b3ab51c8877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	84:0b3ab51c8877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	84:0b3ab51c8877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	84:0b3ab51c8877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	84:0b3ab51c8877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	84:0b3ab51c8877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	84:0b3ab51c8877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	84:0b3ab51c8877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	84:0b3ab51c8877	34	*
bogdanm	84:0b3ab51c8877	35	******************************************************************************
bogdanm	84:0b3ab51c8877	36	*/
bogdanm	84:0b3ab51c8877	37
bogdanm	84:0b3ab51c8877	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	84:0b3ab51c8877	39	#ifndef __STM32L0xx_HAL_TIM_H
bogdanm	84:0b3ab51c8877	40	#define __STM32L0xx_HAL_TIM_H
bogdanm	84:0b3ab51c8877	41
bogdanm	84:0b3ab51c8877	42	#ifdef __cplusplus
bogdanm	84:0b3ab51c8877	43	extern "C" {
bogdanm	84:0b3ab51c8877	44	#endif
bogdanm	84:0b3ab51c8877	45
bogdanm	84:0b3ab51c8877	46	/* Includes ------------------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	47	#include "stm32l0xx_hal_def.h"
bogdanm	84:0b3ab51c8877	48
bogdanm	84:0b3ab51c8877	49	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	84:0b3ab51c8877	50	* @{
bogdanm	84:0b3ab51c8877	51	*/
bogdanm	84:0b3ab51c8877	52
bogdanm	84:0b3ab51c8877	53	/** @addtogroup TIM
bogdanm	84:0b3ab51c8877	54	* @{
bogdanm	84:0b3ab51c8877	55	*/
bogdanm	84:0b3ab51c8877	56
bogdanm	84:0b3ab51c8877	57	/* Exported types ------------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	58
bogdanm	84:0b3ab51c8877	59	/**
bogdanm	84:0b3ab51c8877	60	* @brief TIM Time base Configuration Structure definition
bogdanm	84:0b3ab51c8877	61	*/
bogdanm	84:0b3ab51c8877	62	typedef struct
bogdanm	84:0b3ab51c8877	63	{
bogdanm	84:0b3ab51c8877	64	uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
bogdanm	84:0b3ab51c8877	65	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	84:0b3ab51c8877	66
bogdanm	84:0b3ab51c8877	67	uint32_t CounterMode; /*!< Specifies the counter mode.
bogdanm	84:0b3ab51c8877	68	This parameter can be a value of @ref TIM_Counter_Mode */
bogdanm	84:0b3ab51c8877	69
bogdanm	84:0b3ab51c8877	70	uint32_t Period; /*!< Specifies the period value to be loaded into the active
bogdanm	84:0b3ab51c8877	71	Auto-Reload Register at the next update event.
bogdanm	84:0b3ab51c8877	72	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
bogdanm	84:0b3ab51c8877	73
bogdanm	84:0b3ab51c8877	74	uint32_t ClockDivision; /*!< Specifies the clock division.
bogdanm	84:0b3ab51c8877	75	This parameter can be a value of @ref TIM_ClockDivision */
bogdanm	84:0b3ab51c8877	76	} TIM_Base_InitTypeDef;
bogdanm	84:0b3ab51c8877	77
bogdanm	84:0b3ab51c8877	78	/**
bogdanm	84:0b3ab51c8877	79	* @brief TIM Output Compare Configuration Structure definition
bogdanm	84:0b3ab51c8877	80	*/
bogdanm	84:0b3ab51c8877	81
bogdanm	84:0b3ab51c8877	82	typedef struct
bogdanm	84:0b3ab51c8877	83	{
bogdanm	84:0b3ab51c8877	84	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	84:0b3ab51c8877	85	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	84:0b3ab51c8877	86
bogdanm	84:0b3ab51c8877	87	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	84:0b3ab51c8877	88	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	84:0b3ab51c8877	89
bogdanm	84:0b3ab51c8877	90	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	84:0b3ab51c8877	91	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	84:0b3ab51c8877	92
bogdanm	84:0b3ab51c8877	93	uint32_t OCFastMode; /*!< Specifies the Fast mode state.
bogdanm	84:0b3ab51c8877	94	This parameter can be a value of @ref TIM_Output_Fast_State
bogdanm	84:0b3ab51c8877	95	@note This parameter is valid only in PWM1 and PWM2 mode. */
bogdanm	84:0b3ab51c8877	96
bogdanm	84:0b3ab51c8877	97	} TIM_OC_InitTypeDef;
bogdanm	84:0b3ab51c8877	98
bogdanm	84:0b3ab51c8877	99	/**
bogdanm	84:0b3ab51c8877	100	* @brief TIM One Pulse Mode Configuration Structure definition
bogdanm	84:0b3ab51c8877	101	*/
bogdanm	84:0b3ab51c8877	102	typedef struct
bogdanm	84:0b3ab51c8877	103	{
bogdanm	84:0b3ab51c8877	104	uint32_t OCMode; /*!< Specifies the TIM mode.
bogdanm	84:0b3ab51c8877	105	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
bogdanm	84:0b3ab51c8877	106
bogdanm	84:0b3ab51c8877	107	uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
bogdanm	84:0b3ab51c8877	108	This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
bogdanm	84:0b3ab51c8877	109
bogdanm	84:0b3ab51c8877	110	uint32_t OCPolarity; /*!< Specifies the output polarity.
bogdanm	84:0b3ab51c8877	111	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
bogdanm	84:0b3ab51c8877	112
bogdanm	84:0b3ab51c8877	113
bogdanm	84:0b3ab51c8877	114	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	84:0b3ab51c8877	115	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	84:0b3ab51c8877	116
bogdanm	84:0b3ab51c8877	117	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	84:0b3ab51c8877	118	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	84:0b3ab51c8877	119
bogdanm	84:0b3ab51c8877	120	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	84:0b3ab51c8877	121	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	84:0b3ab51c8877	122	} TIM_OnePulse_InitTypeDef;
bogdanm	84:0b3ab51c8877	123
bogdanm	84:0b3ab51c8877	124
bogdanm	84:0b3ab51c8877	125	/**
bogdanm	84:0b3ab51c8877	126	* @brief TIM Input Capture Configuration Structure definition
bogdanm	84:0b3ab51c8877	127	*/
bogdanm	84:0b3ab51c8877	128
bogdanm	84:0b3ab51c8877	129	typedef struct
bogdanm	84:0b3ab51c8877	130	{
bogdanm	84:0b3ab51c8877	131	uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
bogdanm	84:0b3ab51c8877	132	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	84:0b3ab51c8877	133
bogdanm	84:0b3ab51c8877	134	uint32_t ICSelection; /*!< Specifies the input.
bogdanm	84:0b3ab51c8877	135	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	84:0b3ab51c8877	136
bogdanm	84:0b3ab51c8877	137	uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	84:0b3ab51c8877	138	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	84:0b3ab51c8877	139
bogdanm	84:0b3ab51c8877	140	uint32_t ICFilter; /*!< Specifies the input capture filter.
bogdanm	84:0b3ab51c8877	141	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	84:0b3ab51c8877	142	} TIM_IC_InitTypeDef;
bogdanm	84:0b3ab51c8877	143
bogdanm	84:0b3ab51c8877	144	/**
bogdanm	84:0b3ab51c8877	145	* @brief TIM Encoder Configuration Structure definition
bogdanm	84:0b3ab51c8877	146	*/
bogdanm	84:0b3ab51c8877	147
bogdanm	84:0b3ab51c8877	148	typedef struct
bogdanm	84:0b3ab51c8877	149	{
bogdanm	84:0b3ab51c8877	150	uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
bogdanm	84:0b3ab51c8877	151	This parameter can be a value of @ref TIM_Encoder_Mode */
bogdanm	84:0b3ab51c8877	152
bogdanm	84:0b3ab51c8877	153	uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	84:0b3ab51c8877	154	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	84:0b3ab51c8877	155
bogdanm	84:0b3ab51c8877	156	uint32_t IC1Selection; /*!< Specifies the input.
bogdanm	84:0b3ab51c8877	157	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	84:0b3ab51c8877	158
bogdanm	84:0b3ab51c8877	159	uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	84:0b3ab51c8877	160	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	84:0b3ab51c8877	161
bogdanm	84:0b3ab51c8877	162	uint32_t IC1Filter; /*!< Specifies the input capture filter.
bogdanm	84:0b3ab51c8877	163	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	84:0b3ab51c8877	164
bogdanm	84:0b3ab51c8877	165	uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
bogdanm	84:0b3ab51c8877	166	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
bogdanm	84:0b3ab51c8877	167
bogdanm	84:0b3ab51c8877	168	uint32_t IC2Selection; /*!< Specifies the input.
bogdanm	84:0b3ab51c8877	169	This parameter can be a value of @ref TIM_Input_Capture_Selection */
bogdanm	84:0b3ab51c8877	170
bogdanm	84:0b3ab51c8877	171	uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
bogdanm	84:0b3ab51c8877	172	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
bogdanm	84:0b3ab51c8877	173
bogdanm	84:0b3ab51c8877	174	uint32_t IC2Filter; /*!< Specifies the input capture filter.
bogdanm	84:0b3ab51c8877	175	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	84:0b3ab51c8877	176	} TIM_Encoder_InitTypeDef;
bogdanm	84:0b3ab51c8877	177
bogdanm	84:0b3ab51c8877	178	/**
bogdanm	84:0b3ab51c8877	179	* @brief Clock Configuration Handle Structure definition
bogdanm	84:0b3ab51c8877	180	*/
bogdanm	84:0b3ab51c8877	181	typedef struct
bogdanm	84:0b3ab51c8877	182	{
bogdanm	92:4fc01daae5a5	183	uint32_t ClockSource; /*!< TIM clock sources.
bogdanm	84:0b3ab51c8877	184	This parameter can be a value of @ref TIM_Clock_Source */
bogdanm	92:4fc01daae5a5	185	uint32_t ClockPolarity; /*!< TIM clock polarity.
bogdanm	84:0b3ab51c8877	186	This parameter can be a value of @ref TIM_Clock_Polarity */
bogdanm	92:4fc01daae5a5	187	uint32_t ClockPrescaler; /*!< TIM clock prescaler.
bogdanm	84:0b3ab51c8877	188	This parameter can be a value of @ref TIM_Clock_Prescaler */
bogdanm	92:4fc01daae5a5	189	uint32_t ClockFilter; /*!< TIM clock filter.
bogdanm	92:4fc01daae5a5	190	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	84:0b3ab51c8877	191	}TIM_ClockConfigTypeDef;
bogdanm	84:0b3ab51c8877	192
bogdanm	84:0b3ab51c8877	193	/**
bogdanm	84:0b3ab51c8877	194	* @brief Clear Input Configuration Handle Structure definition
bogdanm	84:0b3ab51c8877	195	*/
bogdanm	84:0b3ab51c8877	196	typedef struct
bogdanm	84:0b3ab51c8877	197	{
bogdanm	92:4fc01daae5a5	198	uint32_t ClearInputState; /*!< TIM clear Input state.
bogdanm	84:0b3ab51c8877	199	This parameter can be ENABLE or DISABLE */
bogdanm	92:4fc01daae5a5	200	uint32_t ClearInputSource; /*!< TIM clear Input sources.
bogdanm	84:0b3ab51c8877	201	This parameter can be a value of @ref TIM_ClearInput_Source */
bogdanm	92:4fc01daae5a5	202	uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
bogdanm	84:0b3ab51c8877	203	This parameter can be a value of @ref TIM_ClearInput_Polarity */
bogdanm	92:4fc01daae5a5	204	uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
bogdanm	84:0b3ab51c8877	205	This parameter can be a value of @ref TIM_ClearInput_Prescaler */
bogdanm	92:4fc01daae5a5	206	uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
bogdanm	92:4fc01daae5a5	207	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	84:0b3ab51c8877	208	}TIM_ClearInputConfigTypeDef;
bogdanm	84:0b3ab51c8877	209
bogdanm	84:0b3ab51c8877	210	/**
bogdanm	84:0b3ab51c8877	211	* @brief TIM Slave configuration Structure definition
bogdanm	84:0b3ab51c8877	212	*/
bogdanm	84:0b3ab51c8877	213	typedef struct {
bogdanm	92:4fc01daae5a5	214	uint32_t SlaveMode; /*!< Slave mode selection.
bogdanm	84:0b3ab51c8877	215	This parameter can be a value of @ref TIM_Slave_Mode */
bogdanm	92:4fc01daae5a5	216	uint32_t InputTrigger; /*!< Input Trigger source.
bogdanm	84:0b3ab51c8877	217	This parameter can be a value of @ref TIM_Trigger_Selection */
bogdanm	92:4fc01daae5a5	218	uint32_t TriggerPolarity; /*!< Input Trigger polarity.
bogdanm	84:0b3ab51c8877	219	This parameter can be a value of @ref TIM_Trigger_Polarity */
bogdanm	92:4fc01daae5a5	220	uint32_t TriggerPrescaler; /*!< Input trigger prescaler.
bogdanm	84:0b3ab51c8877	221	This parameter can be a value of @ref TIM_Trigger_Prescaler */
bogdanm	92:4fc01daae5a5	222	uint32_t TriggerFilter; /*!< Input trigger filter.
bogdanm	92:4fc01daae5a5	223	This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
bogdanm	84:0b3ab51c8877	224
bogdanm	84:0b3ab51c8877	225	}TIM_SlaveConfigTypeDef;
bogdanm	84:0b3ab51c8877	226
bogdanm	84:0b3ab51c8877	227	/**
bogdanm	84:0b3ab51c8877	228	* @brief HAL State structures definition
bogdanm	84:0b3ab51c8877	229	*/
bogdanm	84:0b3ab51c8877	230	typedef enum
bogdanm	84:0b3ab51c8877	231	{
bogdanm	84:0b3ab51c8877	232	HAL_TIM_STATE_RESET = 0x00, /!< Peripheral not yet initialized or disabled /
bogdanm	84:0b3ab51c8877	233	HAL_TIM_STATE_READY = 0x01, /!< Peripheral Initialized and ready for use /
bogdanm	84:0b3ab51c8877	234	HAL_TIM_STATE_BUSY = 0x02, /!< An internal process is ongoing /
bogdanm	84:0b3ab51c8877	235	HAL_TIM_STATE_TIMEOUT = 0x03, /!< Timeout state /
bogdanm	84:0b3ab51c8877	236	HAL_TIM_STATE_ERROR = 0x04 /!< Reception process is ongoing /
bogdanm	84:0b3ab51c8877	237	}HAL_TIM_StateTypeDef;
bogdanm	84:0b3ab51c8877	238
bogdanm	84:0b3ab51c8877	239	/**
bogdanm	84:0b3ab51c8877	240	* @brief HAL Active channel structures definition
bogdanm	84:0b3ab51c8877	241	*/
bogdanm	84:0b3ab51c8877	242	typedef enum
bogdanm	84:0b3ab51c8877	243	{
bogdanm	84:0b3ab51c8877	244	HAL_TIM_ACTIVE_CHANNEL_1 = 0x01, /!< The active channel is 1 /
bogdanm	84:0b3ab51c8877	245	HAL_TIM_ACTIVE_CHANNEL_2 = 0x02, /!< The active channel is 2 /
bogdanm	84:0b3ab51c8877	246	HAL_TIM_ACTIVE_CHANNEL_3 = 0x04, /!< The active channel is 3 /
bogdanm	84:0b3ab51c8877	247	HAL_TIM_ACTIVE_CHANNEL_4 = 0x08, /!< The active channel is 4 /
bogdanm	84:0b3ab51c8877	248	HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00 /!< All active channels cleared /
bogdanm	84:0b3ab51c8877	249	}HAL_TIM_ActiveChannel;
bogdanm	84:0b3ab51c8877	250
bogdanm	84:0b3ab51c8877	251	/**
bogdanm	84:0b3ab51c8877	252	* @brief TIM Time Base Handle Structure definition
bogdanm	84:0b3ab51c8877	253	*/
bogdanm	84:0b3ab51c8877	254	typedef struct
bogdanm	84:0b3ab51c8877	255	{
bogdanm	84:0b3ab51c8877	256	TIM_TypeDef Instance; /!< Register base address */
bogdanm	84:0b3ab51c8877	257	TIM_Base_InitTypeDef Init; /!< TIM Time Base required parameters /
bogdanm	84:0b3ab51c8877	258	HAL_TIM_ActiveChannel Channel; /!< Active channel /
bogdanm	84:0b3ab51c8877	259	DMA_HandleTypeDef hdma[7]; /!< DMA Handlers array
bogdanm	84:0b3ab51c8877	260	This array is accessed by a @ref DMA_Handle_index */
bogdanm	84:0b3ab51c8877	261	HAL_LockTypeDef Lock; /!< Locking object /
bogdanm	84:0b3ab51c8877	262	__IO HAL_TIM_StateTypeDef State; /!< TIM operation state /
bogdanm	84:0b3ab51c8877	263	}TIM_HandleTypeDef;
bogdanm	84:0b3ab51c8877	264
bogdanm	84:0b3ab51c8877	265	/* Exported constants --------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	266	/** @defgroup TIM_Exported_Constants
bogdanm	84:0b3ab51c8877	267	* @{
bogdanm	84:0b3ab51c8877	268	*/
bogdanm	84:0b3ab51c8877	269
bogdanm	92:4fc01daae5a5	270	/** @defgroup TIM_Input_Channel_Polarity
bogdanm	84:0b3ab51c8877	271	* @{
bogdanm	84:0b3ab51c8877	272	*/
bogdanm	84:0b3ab51c8877	273	#define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000) /!< Polarity for TIx source /
bogdanm	84:0b3ab51c8877	274	#define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /!< Polarity for TIx source /
bogdanm	84:0b3ab51c8877	275	#define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P \| TIM_CCER_CC1NP) /!< Polarity for TIx source /
bogdanm	84:0b3ab51c8877	276	/**
bogdanm	84:0b3ab51c8877	277	* @}
bogdanm	84:0b3ab51c8877	278	*/
bogdanm	84:0b3ab51c8877	279
bogdanm	92:4fc01daae5a5	280	/** @defgroup TIM_ETR_Polarity
bogdanm	84:0b3ab51c8877	281	* @{
bogdanm	84:0b3ab51c8877	282	*/
bogdanm	84:0b3ab51c8877	283	#define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /!< Polarity for ETR source /
bogdanm	84:0b3ab51c8877	284	#define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000) /!< Polarity for ETR source /
bogdanm	84:0b3ab51c8877	285	/**
bogdanm	84:0b3ab51c8877	286	* @}
bogdanm	84:0b3ab51c8877	287	*/
bogdanm	84:0b3ab51c8877	288
bogdanm	92:4fc01daae5a5	289	/** @defgroup TIM_ETR_Prescaler
bogdanm	84:0b3ab51c8877	290	* @{
bogdanm	84:0b3ab51c8877	291	*/
bogdanm	84:0b3ab51c8877	292	#define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000) /!< No prescaler is used /
bogdanm	84:0b3ab51c8877	293	#define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /!< ETR input source is divided by 2 /
bogdanm	84:0b3ab51c8877	294	#define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /!< ETR input source is divided by 4 /
bogdanm	84:0b3ab51c8877	295	#define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /!< ETR input source is divided by 8 /
bogdanm	84:0b3ab51c8877	296	/**
bogdanm	84:0b3ab51c8877	297	* @}
bogdanm	84:0b3ab51c8877	298	*/
bogdanm	84:0b3ab51c8877	299
bogdanm	92:4fc01daae5a5	300	/** @defgroup TIM_Counter_Mode
bogdanm	84:0b3ab51c8877	301	* @{
bogdanm	84:0b3ab51c8877	302	*/
bogdanm	84:0b3ab51c8877	303	#define TIM_COUNTERMODE_UP ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	304	#define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
bogdanm	84:0b3ab51c8877	305	#define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
bogdanm	84:0b3ab51c8877	306	#define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
bogdanm	84:0b3ab51c8877	307	#define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
bogdanm	84:0b3ab51c8877	308
bogdanm	84:0b3ab51c8877	309	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_COUNTERMODE_UP) \|\| \
bogdanm	84:0b3ab51c8877	310	((MODE) == TIM_COUNTERMODE_DOWN) \|\| \
bogdanm	84:0b3ab51c8877	311	((MODE) == TIM_COUNTERMODE_CENTERALIGNED1) \|\| \
bogdanm	84:0b3ab51c8877	312	((MODE) == TIM_COUNTERMODE_CENTERALIGNED2) \|\| \
bogdanm	84:0b3ab51c8877	313	((MODE) == TIM_COUNTERMODE_CENTERALIGNED3))
bogdanm	84:0b3ab51c8877	314	/**
bogdanm	84:0b3ab51c8877	315	* @}
bogdanm	84:0b3ab51c8877	316	*/
bogdanm	84:0b3ab51c8877	317
bogdanm	92:4fc01daae5a5	318	/** @defgroup TIM_ClockDivision
bogdanm	84:0b3ab51c8877	319	* @{
bogdanm	84:0b3ab51c8877	320	*/
bogdanm	84:0b3ab51c8877	321	#define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	322	#define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
bogdanm	84:0b3ab51c8877	323	#define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
bogdanm	84:0b3ab51c8877	324
bogdanm	84:0b3ab51c8877	325	#define IS_TIM_CLOCKDIVISION_DIV(DIV) (((DIV) == TIM_CLOCKDIVISION_DIV1) \|\| \
bogdanm	84:0b3ab51c8877	326	((DIV) == TIM_CLOCKDIVISION_DIV2) \|\| \
bogdanm	84:0b3ab51c8877	327	((DIV) == TIM_CLOCKDIVISION_DIV4))
bogdanm	84:0b3ab51c8877	328	/**
bogdanm	84:0b3ab51c8877	329	* @}
bogdanm	84:0b3ab51c8877	330	*/
bogdanm	84:0b3ab51c8877	331
bogdanm	92:4fc01daae5a5	332	/** @defgroup TIM_Output_Compare_and_PWM_modes
bogdanm	84:0b3ab51c8877	333	* @{
bogdanm	84:0b3ab51c8877	334	*/
bogdanm	84:0b3ab51c8877	335	#define TIM_OCMODE_TIMING ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	336	#define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0)
bogdanm	84:0b3ab51c8877	337	#define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1)
bogdanm	84:0b3ab51c8877	338	#define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_1)
bogdanm	84:0b3ab51c8877	339	#define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 \| TIM_CCMR1_OC1M_2)
bogdanm	84:0b3ab51c8877	340	#define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M)
bogdanm	84:0b3ab51c8877	341	#define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 \| TIM_CCMR1_OC1M_2)
bogdanm	84:0b3ab51c8877	342	#define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2)
bogdanm	84:0b3ab51c8877	343
bogdanm	84:0b3ab51c8877	344	#define IS_TIM_PWM_MODE(MODE) (((MODE) == TIM_OCMODE_PWM1) \|\| \
bogdanm	84:0b3ab51c8877	345	((MODE) == TIM_OCMODE_PWM2))
bogdanm	84:0b3ab51c8877	346
bogdanm	84:0b3ab51c8877	347	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMODE_TIMING) \|\| \
bogdanm	84:0b3ab51c8877	348	((MODE) == TIM_OCMODE_ACTIVE) \|\| \
bogdanm	84:0b3ab51c8877	349	((MODE) == TIM_OCMODE_INACTIVE) \|\| \
bogdanm	84:0b3ab51c8877	350	((MODE) == TIM_OCMODE_TOGGLE) \|\| \
bogdanm	84:0b3ab51c8877	351	((MODE) == TIM_OCMODE_FORCED_ACTIVE) \|\| \
bogdanm	84:0b3ab51c8877	352	((MODE) == TIM_OCMODE_FORCED_INACTIVE))
bogdanm	84:0b3ab51c8877	353	/**
bogdanm	84:0b3ab51c8877	354	* @}
bogdanm	84:0b3ab51c8877	355	*/
bogdanm	84:0b3ab51c8877	356
bogdanm	92:4fc01daae5a5	357	/** @defgroup TIM_Output_Compare_State
bogdanm	84:0b3ab51c8877	358	* @{
bogdanm	84:0b3ab51c8877	359	*/
bogdanm	84:0b3ab51c8877	360	#define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	361	#define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
bogdanm	84:0b3ab51c8877	362
bogdanm	84:0b3ab51c8877	363	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) \|\| \
bogdanm	84:0b3ab51c8877	364	((STATE) == TIM_OUTPUTSTATE_ENABLE))
bogdanm	84:0b3ab51c8877	365	/**
bogdanm	84:0b3ab51c8877	366	* @}
bogdanm	84:0b3ab51c8877	367	*/
bogdanm	92:4fc01daae5a5	368	/** @defgroup TIM_Output_Fast_State
bogdanm	84:0b3ab51c8877	369	* @{
bogdanm	84:0b3ab51c8877	370	*/
bogdanm	84:0b3ab51c8877	371	#define TIM_OCFAST_DISABLE ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	372	#define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
bogdanm	84:0b3ab51c8877	373
bogdanm	84:0b3ab51c8877	374	#define IS_TIM_FAST_STATE(STATE) (((STATE) == TIM_OCFAST_DISABLE) \|\| \
bogdanm	84:0b3ab51c8877	375	((STATE) == TIM_OCFAST_ENABLE))
bogdanm	84:0b3ab51c8877	376	/**
bogdanm	84:0b3ab51c8877	377	* @}
bogdanm	84:0b3ab51c8877	378	*/
bogdanm	84:0b3ab51c8877	379	/** @defgroup TIM_Output_Compare_N_State
bogdanm	84:0b3ab51c8877	380	* @{
bogdanm	84:0b3ab51c8877	381	*/
bogdanm	84:0b3ab51c8877	382	#define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	383	#define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
bogdanm	84:0b3ab51c8877	384
bogdanm	84:0b3ab51c8877	385	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) \|\| \
bogdanm	84:0b3ab51c8877	386	((STATE) == TIM_OUTPUTNSTATE_ENABLE))
bogdanm	84:0b3ab51c8877	387	/**
bogdanm	84:0b3ab51c8877	388	* @}
bogdanm	84:0b3ab51c8877	389	*/
bogdanm	84:0b3ab51c8877	390
bogdanm	92:4fc01daae5a5	391	/** @defgroup TIM_Output_Compare_Polarity
bogdanm	84:0b3ab51c8877	392	* @{
bogdanm	84:0b3ab51c8877	393	*/
bogdanm	84:0b3ab51c8877	394	#define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	395	#define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
bogdanm	84:0b3ab51c8877	396
bogdanm	84:0b3ab51c8877	397	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPOLARITY_HIGH) \|\| \
bogdanm	84:0b3ab51c8877	398	((POLARITY) == TIM_OCPOLARITY_LOW))
bogdanm	84:0b3ab51c8877	399	/**
bogdanm	84:0b3ab51c8877	400	* @}
bogdanm	84:0b3ab51c8877	401	*/
bogdanm	84:0b3ab51c8877	402
bogdanm	92:4fc01daae5a5	403	/** @defgroup TIM_Channel
bogdanm	84:0b3ab51c8877	404	* @{
bogdanm	84:0b3ab51c8877	405	*/
bogdanm	84:0b3ab51c8877	406
bogdanm	84:0b3ab51c8877	407	#define TIM_CHANNEL_1 ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	408	#define TIM_CHANNEL_2 ((uint32_t)0x0004)
bogdanm	84:0b3ab51c8877	409	#define TIM_CHANNEL_3 ((uint32_t)0x0008)
bogdanm	84:0b3ab51c8877	410	#define TIM_CHANNEL_4 ((uint32_t)0x000C)
bogdanm	84:0b3ab51c8877	411	#define TIM_CHANNEL_ALL ((uint32_t)0x0018)
bogdanm	84:0b3ab51c8877	412
bogdanm	84:0b3ab51c8877	413	#define IS_TIM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	84:0b3ab51c8877	414	((CHANNEL) == TIM_CHANNEL_2) \|\| \
bogdanm	84:0b3ab51c8877	415	((CHANNEL) == TIM_CHANNEL_3) \|\| \
bogdanm	84:0b3ab51c8877	416	((CHANNEL) == TIM_CHANNEL_4) \|\| \
bogdanm	84:0b3ab51c8877	417	((CHANNEL) == TIM_CHANNEL_ALL))
bogdanm	84:0b3ab51c8877	418
bogdanm	84:0b3ab51c8877	419	#define IS_TIM_PWMI_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	84:0b3ab51c8877	420	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	84:0b3ab51c8877	421
bogdanm	84:0b3ab51c8877	422	#define IS_TIM_OPM_CHANNELS(CHANNEL) (((CHANNEL) == TIM_CHANNEL_1) \|\| \
bogdanm	84:0b3ab51c8877	423	((CHANNEL) == TIM_CHANNEL_2))
bogdanm	84:0b3ab51c8877	424	/**
bogdanm	84:0b3ab51c8877	425	* @}
bogdanm	84:0b3ab51c8877	426	*/
bogdanm	84:0b3ab51c8877	427
bogdanm	92:4fc01daae5a5	428	/** @defgroup TIM_Input_Capture_Polarity
bogdanm	84:0b3ab51c8877	429	* @{
bogdanm	84:0b3ab51c8877	430	*/
bogdanm	84:0b3ab51c8877	431	#define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
bogdanm	84:0b3ab51c8877	432	#define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
bogdanm	84:0b3ab51c8877	433	#define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
bogdanm	84:0b3ab51c8877	434
bogdanm	84:0b3ab51c8877	435	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPOLARITY_RISING) \|\| \
bogdanm	84:0b3ab51c8877	436	((POLARITY) == TIM_ICPOLARITY_FALLING) \|\| \
bogdanm	84:0b3ab51c8877	437	((POLARITY) == TIM_ICPOLARITY_BOTHEDGE))
bogdanm	84:0b3ab51c8877	438	/**
bogdanm	84:0b3ab51c8877	439	* @}
bogdanm	84:0b3ab51c8877	440	*/
bogdanm	84:0b3ab51c8877	441
bogdanm	92:4fc01daae5a5	442	/** @defgroup TIM_Input_Capture_Selection
bogdanm	84:0b3ab51c8877	443	* @{
bogdanm	84:0b3ab51c8877	444	*/
bogdanm	84:0b3ab51c8877	445	#define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	84:0b3ab51c8877	446	connected to IC1, IC2, IC3 or IC4, respectively */
bogdanm	84:0b3ab51c8877	447	#define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
bogdanm	84:0b3ab51c8877	448	connected to IC2, IC1, IC4 or IC3, respectively */
bogdanm	84:0b3ab51c8877	449	#define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC /
bogdanm	84:0b3ab51c8877	450
bogdanm	84:0b3ab51c8877	451	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSELECTION_DIRECTTI) \|\| \
bogdanm	84:0b3ab51c8877	452	((SELECTION) == TIM_ICSELECTION_INDIRECTTI) \|\| \
bogdanm	84:0b3ab51c8877	453	((SELECTION) == TIM_ICSELECTION_TRC))
bogdanm	84:0b3ab51c8877	454	/**
bogdanm	84:0b3ab51c8877	455	* @}
bogdanm	84:0b3ab51c8877	456	*/
bogdanm	84:0b3ab51c8877	457
bogdanm	92:4fc01daae5a5	458	/** @defgroup TIM_Input_Capture_Prescaler
bogdanm	84:0b3ab51c8877	459	* @{
bogdanm	84:0b3ab51c8877	460	*/
bogdanm	84:0b3ab51c8877	461	#define TIM_ICPSC_DIV1 ((uint32_t)0x0000) /!< Capture performed each time an edge is detected on the capture input /
bogdanm	84:0b3ab51c8877	462	#define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /!< Capture performed once every 2 events /
bogdanm	84:0b3ab51c8877	463	#define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /!< Capture performed once every 4 events /
bogdanm	84:0b3ab51c8877	464	#define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /!< Capture performed once every 8 events /
bogdanm	84:0b3ab51c8877	465
bogdanm	84:0b3ab51c8877	466	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
bogdanm	84:0b3ab51c8877	467	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
bogdanm	84:0b3ab51c8877	468	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
bogdanm	84:0b3ab51c8877	469	((PRESCALER) == TIM_ICPSC_DIV8))
bogdanm	84:0b3ab51c8877	470	/**
bogdanm	84:0b3ab51c8877	471	* @}
bogdanm	84:0b3ab51c8877	472	*/
bogdanm	84:0b3ab51c8877	473
bogdanm	92:4fc01daae5a5	474	/** @defgroup TIM_One_Pulse_Mode
bogdanm	84:0b3ab51c8877	475	* @{
bogdanm	84:0b3ab51c8877	476	*/
bogdanm	84:0b3ab51c8877	477	#define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
bogdanm	84:0b3ab51c8877	478	#define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	479	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMODE_SINGLE) \|\| \
bogdanm	84:0b3ab51c8877	480	((MODE) == TIM_OPMODE_REPETITIVE))
bogdanm	84:0b3ab51c8877	481	/**
bogdanm	84:0b3ab51c8877	482	* @}
bogdanm	84:0b3ab51c8877	483	*/
bogdanm	92:4fc01daae5a5	484	/** @defgroup TIM_Encoder_Mode
bogdanm	84:0b3ab51c8877	485	* @{
bogdanm	84:0b3ab51c8877	486	*/
bogdanm	84:0b3ab51c8877	487	#define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
bogdanm	84:0b3ab51c8877	488	#define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
bogdanm	84:0b3ab51c8877	489	#define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 \| TIM_SMCR_SMS_0)
bogdanm	84:0b3ab51c8877	490	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_ENCODERMODE_TI1) \|\| \
bogdanm	84:0b3ab51c8877	491	((MODE) == TIM_ENCODERMODE_TI2) \|\| \
bogdanm	84:0b3ab51c8877	492	((MODE) == TIM_ENCODERMODE_TI12))
bogdanm	84:0b3ab51c8877	493	/**
bogdanm	84:0b3ab51c8877	494	* @}
bogdanm	84:0b3ab51c8877	495	*/
bogdanm	92:4fc01daae5a5	496	/** @defgroup TIM_Interrupt_definition
bogdanm	84:0b3ab51c8877	497	* @{
bogdanm	84:0b3ab51c8877	498	*/
bogdanm	84:0b3ab51c8877	499	#define TIM_IT_UPDATE (TIM_DIER_UIE)
bogdanm	84:0b3ab51c8877	500	#define TIM_IT_CC1 (TIM_DIER_CC1IE)
bogdanm	84:0b3ab51c8877	501	#define TIM_IT_CC2 (TIM_DIER_CC2IE)
bogdanm	84:0b3ab51c8877	502	#define TIM_IT_CC3 (TIM_DIER_CC3IE)
bogdanm	84:0b3ab51c8877	503	#define TIM_IT_CC4 (TIM_DIER_CC4IE)
bogdanm	84:0b3ab51c8877	504	#define TIM_IT_TRIGGER (TIM_DIER_TIE)
bogdanm	84:0b3ab51c8877	505
bogdanm	84:0b3ab51c8877	506	#define IS_TIM_IT(IT) ((((IT) & 0xFFFFFFA0) == 0x00000000) && ((IT) != 0x00000000))
bogdanm	84:0b3ab51c8877	507
bogdanm	84:0b3ab51c8877	508	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_UPDATE) \|\| \
bogdanm	84:0b3ab51c8877	509	((IT) == TIM_IT_CC1) \|\| \
bogdanm	84:0b3ab51c8877	510	((IT) == TIM_IT_CC2) \|\| \
bogdanm	84:0b3ab51c8877	511	((IT) == TIM_IT_CC3) \|\| \
bogdanm	84:0b3ab51c8877	512	((IT) == TIM_IT_CC4) \|\| \
bogdanm	92:4fc01daae5a5	513	((IT) == TIM_IT_TRIGGER))
bogdanm	84:0b3ab51c8877	514	/**
bogdanm	84:0b3ab51c8877	515	* @}
bogdanm	84:0b3ab51c8877	516	*/
bogdanm	84:0b3ab51c8877	517
bogdanm	92:4fc01daae5a5	518	/** @defgroup TIM_DMA_sources
bogdanm	84:0b3ab51c8877	519	* @{
bogdanm	84:0b3ab51c8877	520	*/
bogdanm	84:0b3ab51c8877	521	#define TIM_DMA_UPDATE (TIM_DIER_UDE)
bogdanm	84:0b3ab51c8877	522	#define TIM_DMA_CC1 (TIM_DIER_CC1DE)
bogdanm	84:0b3ab51c8877	523	#define TIM_DMA_CC2 (TIM_DIER_CC2DE)
bogdanm	84:0b3ab51c8877	524	#define TIM_DMA_CC3 (TIM_DIER_CC3DE)
bogdanm	84:0b3ab51c8877	525	#define TIM_DMA_CC4 (TIM_DIER_CC4DE)
bogdanm	84:0b3ab51c8877	526	#define TIM_DMA_TRIGGER (TIM_DIER_TDE)
bogdanm	84:0b3ab51c8877	527	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFA0FF) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	84:0b3ab51c8877	528
bogdanm	84:0b3ab51c8877	529	/**
bogdanm	84:0b3ab51c8877	530	* @}
bogdanm	84:0b3ab51c8877	531	*/
bogdanm	84:0b3ab51c8877	532
bogdanm	92:4fc01daae5a5	533	/** @defgroup TIM_Event_Source
bogdanm	84:0b3ab51c8877	534	* @{
bogdanm	84:0b3ab51c8877	535	*/
bogdanm	84:0b3ab51c8877	536	#define TIM_EventSource_Update TIM_EGR_UG
bogdanm	84:0b3ab51c8877	537	#define TIM_EventSource_CC1 TIM_EGR_CC1G
bogdanm	84:0b3ab51c8877	538	#define TIM_EventSource_CC2 TIM_EGR_CC2G
bogdanm	84:0b3ab51c8877	539	#define TIM_EventSource_CC3 TIM_EGR_CC3G
bogdanm	84:0b3ab51c8877	540	#define TIM_EventSource_CC4 TIM_EGR_CC4G
bogdanm	84:0b3ab51c8877	541	#define TIM_EventSource_Trigger TIM_EGR_TG
bogdanm	84:0b3ab51c8877	542	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & 0xFFFFFFA0) == 0x00000000) && ((SOURCE) != 0x00000000))
bogdanm	84:0b3ab51c8877	543
bogdanm	84:0b3ab51c8877	544	/**
bogdanm	84:0b3ab51c8877	545	* @}
bogdanm	84:0b3ab51c8877	546	*/
bogdanm	84:0b3ab51c8877	547
bogdanm	92:4fc01daae5a5	548	/** @defgroup TIM_Flag_definition
bogdanm	84:0b3ab51c8877	549	* @{
bogdanm	84:0b3ab51c8877	550	*/
bogdanm	84:0b3ab51c8877	551	#define TIM_FLAG_UPDATE (TIM_SR_UIF)
bogdanm	84:0b3ab51c8877	552	#define TIM_FLAG_CC1 (TIM_SR_CC1IF)
bogdanm	84:0b3ab51c8877	553	#define TIM_FLAG_CC2 (TIM_SR_CC2IF)
bogdanm	84:0b3ab51c8877	554	#define TIM_FLAG_CC3 (TIM_SR_CC3IF)
bogdanm	84:0b3ab51c8877	555	#define TIM_FLAG_CC4 (TIM_SR_CC4IF)
bogdanm	84:0b3ab51c8877	556	#define TIM_FLAG_TRIGGER (TIM_SR_TIF)
bogdanm	84:0b3ab51c8877	557	#define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
bogdanm	84:0b3ab51c8877	558	#define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
bogdanm	84:0b3ab51c8877	559	#define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
bogdanm	84:0b3ab51c8877	560	#define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
bogdanm	84:0b3ab51c8877	561
bogdanm	84:0b3ab51c8877	562	#define IS_TIM_FLAG(FLAG) (((FLAG) == TIM_FLAG_UPDATE) \|\| \
bogdanm	84:0b3ab51c8877	563	((FLAG) == TIM_FLAG_CC1) \|\| \
bogdanm	84:0b3ab51c8877	564	((FLAG) == TIM_FLAG_CC2) \|\| \
bogdanm	84:0b3ab51c8877	565	((FLAG) == TIM_FLAG_CC3) \|\| \
bogdanm	84:0b3ab51c8877	566	((FLAG) == TIM_FLAG_CC4) \|\| \
bogdanm	84:0b3ab51c8877	567	((FLAG) == TIM_FLAG_TRIGGER) \|\| \
bogdanm	84:0b3ab51c8877	568	((FLAG) == TIM_FLAG_CC1OF) \|\| \
bogdanm	84:0b3ab51c8877	569	((FLAG) == TIM_FLAG_CC2OF) \|\| \
bogdanm	84:0b3ab51c8877	570	((FLAG) == TIM_FLAG_CC3OF) \|\| \
bogdanm	92:4fc01daae5a5	571	((FLAG) == TIM_FLAG_CC4OF))
bogdanm	84:0b3ab51c8877	572	/**
bogdanm	84:0b3ab51c8877	573	* @}
bogdanm	84:0b3ab51c8877	574	*/
bogdanm	84:0b3ab51c8877	575
bogdanm	92:4fc01daae5a5	576	/** @defgroup TIM_Clock_Source
bogdanm	84:0b3ab51c8877	577	* @{
bogdanm	84:0b3ab51c8877	578	*/
bogdanm	84:0b3ab51c8877	579	#define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
bogdanm	84:0b3ab51c8877	580	#define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
bogdanm	84:0b3ab51c8877	581	#define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	582	#define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
bogdanm	84:0b3ab51c8877	583	#define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
bogdanm	84:0b3ab51c8877	584	#define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_1)
bogdanm	84:0b3ab51c8877	585	#define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
bogdanm	84:0b3ab51c8877	586	#define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 \| TIM_SMCR_TS_2)
bogdanm	84:0b3ab51c8877	587	#define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 \| TIM_SMCR_TS_2)
bogdanm	84:0b3ab51c8877	588	#define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
bogdanm	84:0b3ab51c8877	589
bogdanm	84:0b3ab51c8877	590	#define IS_TIM_CLOCKSOURCE(CLOCK) (((CLOCK) == TIM_CLOCKSOURCE_INTERNAL) \|\| \
bogdanm	84:0b3ab51c8877	591	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE2) \|\| \
bogdanm	84:0b3ab51c8877	592	((CLOCK) == TIM_CLOCKSOURCE_ITR0) \|\| \
bogdanm	84:0b3ab51c8877	593	((CLOCK) == TIM_CLOCKSOURCE_ITR1) \|\| \
bogdanm	84:0b3ab51c8877	594	((CLOCK) == TIM_CLOCKSOURCE_ITR2) \|\| \
bogdanm	84:0b3ab51c8877	595	((CLOCK) == TIM_CLOCKSOURCE_ITR3) \|\| \
bogdanm	84:0b3ab51c8877	596	((CLOCK) == TIM_CLOCKSOURCE_TI1ED) \|\| \
bogdanm	84:0b3ab51c8877	597	((CLOCK) == TIM_CLOCKSOURCE_TI1) \|\| \
bogdanm	84:0b3ab51c8877	598	((CLOCK) == TIM_CLOCKSOURCE_TI2) \|\| \
bogdanm	84:0b3ab51c8877	599	((CLOCK) == TIM_CLOCKSOURCE_ETRMODE1))
bogdanm	84:0b3ab51c8877	600	/**
bogdanm	84:0b3ab51c8877	601	* @}
bogdanm	84:0b3ab51c8877	602	*/
bogdanm	84:0b3ab51c8877	603
bogdanm	92:4fc01daae5a5	604	/** @defgroup TIM_Clock_Polarity
bogdanm	84:0b3ab51c8877	605	* @{
bogdanm	84:0b3ab51c8877	606	*/
bogdanm	84:0b3ab51c8877	607	#define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx clock sources /
bogdanm	84:0b3ab51c8877	608	#define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx clock sources /
bogdanm	84:0b3ab51c8877	609	#define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIx clock sources /
bogdanm	84:0b3ab51c8877	610	#define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIx clock sources /
bogdanm	84:0b3ab51c8877	611	#define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIx clock sources /
bogdanm	84:0b3ab51c8877	612
bogdanm	84:0b3ab51c8877	613	#define IS_TIM_CLOCKPOLARITY(POLARITY) (((POLARITY) == TIM_CLOCKPOLARITY_INVERTED) \|\| \
bogdanm	84:0b3ab51c8877	614	((POLARITY) == TIM_CLOCKPOLARITY_NONINVERTED) \|\| \
bogdanm	84:0b3ab51c8877	615	((POLARITY) == TIM_CLOCKPOLARITY_RISING) \|\| \
bogdanm	84:0b3ab51c8877	616	((POLARITY) == TIM_CLOCKPOLARITY_FALLING) \|\| \
bogdanm	84:0b3ab51c8877	617	((POLARITY) == TIM_CLOCKPOLARITY_BOTHEDGE))
bogdanm	84:0b3ab51c8877	618	/**
bogdanm	84:0b3ab51c8877	619	* @}
bogdanm	84:0b3ab51c8877	620	*/
bogdanm	92:4fc01daae5a5	621	/** @defgroup TIM_Clock_Prescaler
bogdanm	84:0b3ab51c8877	622	* @{
bogdanm	84:0b3ab51c8877	623	*/
bogdanm	84:0b3ab51c8877	624	#define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	84:0b3ab51c8877	625	#define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Clock: Capture performed once every 2 events. /
bogdanm	84:0b3ab51c8877	626	#define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Clock: Capture performed once every 4 events. /
bogdanm	84:0b3ab51c8877	627	#define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Clock: Capture performed once every 8 events. /
bogdanm	84:0b3ab51c8877	628
bogdanm	84:0b3ab51c8877	629	#define IS_TIM_CLOCKPRESCALER(PRESCALER) (((PRESCALER) == TIM_CLOCKPRESCALER_DIV1) \|\| \
bogdanm	84:0b3ab51c8877	630	((PRESCALER) == TIM_CLOCKPRESCALER_DIV2) \|\| \
bogdanm	84:0b3ab51c8877	631	((PRESCALER) == TIM_CLOCKPRESCALER_DIV4) \|\| \
bogdanm	84:0b3ab51c8877	632	((PRESCALER) == TIM_CLOCKPRESCALER_DIV8))
bogdanm	84:0b3ab51c8877	633	/**
bogdanm	84:0b3ab51c8877	634	* @}
bogdanm	84:0b3ab51c8877	635	*/
bogdanm	92:4fc01daae5a5	636
bogdanm	84:0b3ab51c8877	637	/** @defgroup TIM_Clock_Filter
bogdanm	84:0b3ab51c8877	638	* @{
bogdanm	84:0b3ab51c8877	639	*/
bogdanm	92:4fc01daae5a5	640	#define IS_TIM_CLOCKFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	84:0b3ab51c8877	641	/**
bogdanm	84:0b3ab51c8877	642	* @}
bogdanm	92:4fc01daae5a5	643	*/
bogdanm	84:0b3ab51c8877	644
bogdanm	84:0b3ab51c8877	645	/** @defgroup TIM_ClearInput_Source
bogdanm	84:0b3ab51c8877	646	* @{
bogdanm	84:0b3ab51c8877	647	*/
bogdanm	84:0b3ab51c8877	648	#define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001)
bogdanm	84:0b3ab51c8877	649	#define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	650
bogdanm	84:0b3ab51c8877	651	#define IS_TIM_CLEARINPUT_SOURCE(SOURCE) (((SOURCE) == TIM_CLEARINPUTSOURCE_NONE) \|\| \
bogdanm	84:0b3ab51c8877	652	((SOURCE) == TIM_CLEARINPUTSOURCE_ETR))
bogdanm	84:0b3ab51c8877	653	/**
bogdanm	84:0b3ab51c8877	654	* @}
bogdanm	84:0b3ab51c8877	655	*/
bogdanm	84:0b3ab51c8877	656
bogdanm	84:0b3ab51c8877	657	/** @defgroup TIM_ClearInput_Polarity
bogdanm	84:0b3ab51c8877	658	* @{
bogdanm	84:0b3ab51c8877	659	*/
bogdanm	84:0b3ab51c8877	660	#define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx pin /
bogdanm	84:0b3ab51c8877	661	#define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx pin /
bogdanm	84:0b3ab51c8877	662	#define IS_TIM_CLEARINPUT_POLARITY(POLARITY) (((POLARITY) == TIM_CLEARINPUTPOLARITY_INVERTED) \|\| \
bogdanm	84:0b3ab51c8877	663	((POLARITY) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
bogdanm	84:0b3ab51c8877	664	/**
bogdanm	84:0b3ab51c8877	665	* @}
bogdanm	84:0b3ab51c8877	666	*/
bogdanm	84:0b3ab51c8877	667
bogdanm	84:0b3ab51c8877	668	/** @defgroup TIM_ClearInput_Prescaler
bogdanm	84:0b3ab51c8877	669	* @{
bogdanm	84:0b3ab51c8877	670	*/
bogdanm	84:0b3ab51c8877	671	#define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	84:0b3ab51c8877	672	#define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR pin: Capture performed once every 2 events. /
bogdanm	84:0b3ab51c8877	673	#define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR pin: Capture performed once every 4 events. /
bogdanm	84:0b3ab51c8877	674	#define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR pin: Capture performed once every 8 events. /
bogdanm	84:0b3ab51c8877	675	#define IS_TIM_CLEARINPUT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV1) \|\| \
bogdanm	84:0b3ab51c8877	676	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV2) \|\| \
bogdanm	84:0b3ab51c8877	677	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV4) \|\| \
bogdanm	84:0b3ab51c8877	678	((PRESCALER) == TIM_CLEARINPUTPRESCALER_DIV8))
bogdanm	84:0b3ab51c8877	679	/**
bogdanm	84:0b3ab51c8877	680	* @}
bogdanm	84:0b3ab51c8877	681	*/
bogdanm	84:0b3ab51c8877	682
bogdanm	84:0b3ab51c8877	683	/** @defgroup TIM_ClearInput_Filter
bogdanm	84:0b3ab51c8877	684	* @{
bogdanm	84:0b3ab51c8877	685	*/
bogdanm	84:0b3ab51c8877	686	#define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	84:0b3ab51c8877	687	/**
bogdanm	84:0b3ab51c8877	688	* @}
bogdanm	84:0b3ab51c8877	689	*/
bogdanm	84:0b3ab51c8877	690
bogdanm	84:0b3ab51c8877	691
bogdanm	84:0b3ab51c8877	692	/** @defgroup TIM_Master_Mode_Selection
bogdanm	84:0b3ab51c8877	693	* @{
bogdanm	84:0b3ab51c8877	694	*/
bogdanm	84:0b3ab51c8877	695	#define TIM_TRGO_RESET ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	696	#define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
bogdanm	84:0b3ab51c8877	697	#define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
bogdanm	84:0b3ab51c8877	698	#define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	84:0b3ab51c8877	699	#define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
bogdanm	84:0b3ab51c8877	700	#define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_0))
bogdanm	84:0b3ab51c8877	701	#define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1))
bogdanm	84:0b3ab51c8877	702	#define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 \| TIM_CR2_MMS_1 \| TIM_CR2_MMS_0))
bogdanm	84:0b3ab51c8877	703
bogdanm	84:0b3ab51c8877	704	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO_RESET) \|\| \
bogdanm	84:0b3ab51c8877	705	((SOURCE) == TIM_TRGO_ENABLE) \|\| \
bogdanm	84:0b3ab51c8877	706	((SOURCE) == TIM_TRGO_UPDATE) \|\| \
bogdanm	84:0b3ab51c8877	707	((SOURCE) == TIM_TRGO_OC1) \|\| \
bogdanm	84:0b3ab51c8877	708	((SOURCE) == TIM_TRGO_OC1REF) \|\| \
bogdanm	84:0b3ab51c8877	709	((SOURCE) == TIM_TRGO_OC2REF) \|\| \
bogdanm	84:0b3ab51c8877	710	((SOURCE) == TIM_TRGO_OC3REF) \|\| \
bogdanm	84:0b3ab51c8877	711	((SOURCE) == TIM_TRGO_OC4REF))
bogdanm	84:0b3ab51c8877	712
bogdanm	84:0b3ab51c8877	713
bogdanm	84:0b3ab51c8877	714	/**
bogdanm	84:0b3ab51c8877	715	* @}
bogdanm	84:0b3ab51c8877	716	*/
bogdanm	92:4fc01daae5a5	717	/** @defgroup TIM_Slave_Mode
bogdanm	84:0b3ab51c8877	718	* @{
bogdanm	84:0b3ab51c8877	719	*/
bogdanm	84:0b3ab51c8877	720	#define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	721	#define TIM_SLAVEMODE_RESET ((uint32_t)0x0004)
bogdanm	84:0b3ab51c8877	722	#define TIM_SLAVEMODE_GATED ((uint32_t)0x0005)
bogdanm	84:0b3ab51c8877	723	#define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006)
bogdanm	84:0b3ab51c8877	724	#define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007)
bogdanm	84:0b3ab51c8877	725
bogdanm	84:0b3ab51c8877	726	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SLAVEMODE_DISABLE) \|\| \
bogdanm	84:0b3ab51c8877	727	((MODE) == TIM_SLAVEMODE_GATED) \|\| \
bogdanm	84:0b3ab51c8877	728	((MODE) == TIM_SLAVEMODE_RESET) \|\| \
bogdanm	84:0b3ab51c8877	729	((MODE) == TIM_SLAVEMODE_TRIGGER) \|\| \
bogdanm	84:0b3ab51c8877	730	((MODE) == TIM_SLAVEMODE_EXTERNAL1))
bogdanm	84:0b3ab51c8877	731	/**
bogdanm	84:0b3ab51c8877	732	* @}
bogdanm	84:0b3ab51c8877	733	*/
bogdanm	84:0b3ab51c8877	734
bogdanm	92:4fc01daae5a5	735	/** @defgroup TIM_Master_Slave_Mode
bogdanm	84:0b3ab51c8877	736	* @{
bogdanm	84:0b3ab51c8877	737	*/
bogdanm	84:0b3ab51c8877	738
bogdanm	84:0b3ab51c8877	739	#define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
bogdanm	84:0b3ab51c8877	740	#define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	741	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MASTERSLAVEMODE_ENABLE) \|\| \
bogdanm	84:0b3ab51c8877	742	((STATE) == TIM_MASTERSLAVEMODE_DISABLE))
bogdanm	84:0b3ab51c8877	743	/**
bogdanm	84:0b3ab51c8877	744	* @}
bogdanm	84:0b3ab51c8877	745	*/
bogdanm	92:4fc01daae5a5	746	/** @defgroup TIM_Trigger_Selection
bogdanm	84:0b3ab51c8877	747	* @{
bogdanm	84:0b3ab51c8877	748	*/
bogdanm	84:0b3ab51c8877	749	#define TIM_TS_ITR0 ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	750	#define TIM_TS_ITR1 ((uint32_t)0x0010)
bogdanm	84:0b3ab51c8877	751	#define TIM_TS_ITR2 ((uint32_t)0x0020)
bogdanm	84:0b3ab51c8877	752	#define TIM_TS_ITR3 ((uint32_t)0x0030)
bogdanm	84:0b3ab51c8877	753	#define TIM_TS_TI1F_ED ((uint32_t)0x0040)
bogdanm	84:0b3ab51c8877	754	#define TIM_TS_TI1FP1 ((uint32_t)0x0050)
bogdanm	84:0b3ab51c8877	755	#define TIM_TS_TI2FP2 ((uint32_t)0x0060)
bogdanm	84:0b3ab51c8877	756	#define TIM_TS_ETRF ((uint32_t)0x0070)
bogdanm	84:0b3ab51c8877	757	#define TIM_TS_NONE ((uint32_t)0xFFFF)
bogdanm	84:0b3ab51c8877	758	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	84:0b3ab51c8877	759	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	84:0b3ab51c8877	760	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	84:0b3ab51c8877	761	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	84:0b3ab51c8877	762	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
bogdanm	84:0b3ab51c8877	763	((SELECTION) == TIM_TS_TI1FP1) \|\| \
bogdanm	84:0b3ab51c8877	764	((SELECTION) == TIM_TS_TI2FP2) \|\| \
bogdanm	84:0b3ab51c8877	765	((SELECTION) == TIM_TS_ETRF))
bogdanm	84:0b3ab51c8877	766	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	84:0b3ab51c8877	767	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	84:0b3ab51c8877	768	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	84:0b3ab51c8877	769	((SELECTION) == TIM_TS_ITR3))
bogdanm	84:0b3ab51c8877	770	#define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
bogdanm	84:0b3ab51c8877	771	((SELECTION) == TIM_TS_ITR1) \|\| \
bogdanm	84:0b3ab51c8877	772	((SELECTION) == TIM_TS_ITR2) \|\| \
bogdanm	84:0b3ab51c8877	773	((SELECTION) == TIM_TS_ITR3) \|\| \
bogdanm	84:0b3ab51c8877	774	((SELECTION) == TIM_TS_NONE))
bogdanm	84:0b3ab51c8877	775	/**
bogdanm	84:0b3ab51c8877	776	* @}
bogdanm	84:0b3ab51c8877	777	*/
bogdanm	84:0b3ab51c8877	778
bogdanm	92:4fc01daae5a5	779	/** @defgroup TIM_Trigger_Polarity
bogdanm	84:0b3ab51c8877	780	* @{
bogdanm	84:0b3ab51c8877	781	*/
bogdanm	84:0b3ab51c8877	782	#define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /!< Polarity for ETRx trigger sources /
bogdanm	84:0b3ab51c8877	783	#define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /!< Polarity for ETRx trigger sources /
bogdanm	84:0b3ab51c8877	784	#define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	84:0b3ab51c8877	785	#define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	84:0b3ab51c8877	786	#define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /!< Polarity for TIxFPx or TI1_ED trigger sources /
bogdanm	84:0b3ab51c8877	787
bogdanm	84:0b3ab51c8877	788	#define IS_TIM_TRIGGERPOLARITY(POLARITY) (((POLARITY) == TIM_TRIGGERPOLARITY_INVERTED ) \|\| \
bogdanm	84:0b3ab51c8877	789	((POLARITY) == TIM_TRIGGERPOLARITY_NONINVERTED) \|\| \
bogdanm	84:0b3ab51c8877	790	((POLARITY) == TIM_TRIGGERPOLARITY_RISING ) \|\| \
bogdanm	84:0b3ab51c8877	791	((POLARITY) == TIM_TRIGGERPOLARITY_FALLING ) \|\| \
bogdanm	84:0b3ab51c8877	792	((POLARITY) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
bogdanm	84:0b3ab51c8877	793	/**
bogdanm	84:0b3ab51c8877	794	* @}
bogdanm	84:0b3ab51c8877	795	*/
bogdanm	84:0b3ab51c8877	796
bogdanm	92:4fc01daae5a5	797	/** @defgroup TIM_Trigger_Prescaler
bogdanm	84:0b3ab51c8877	798	* @{
bogdanm	84:0b3ab51c8877	799	*/
bogdanm	84:0b3ab51c8877	800	#define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /!< No prescaler is used /
bogdanm	84:0b3ab51c8877	801	#define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /!< Prescaler for External ETR Trigger: Capture performed once every 2 events. /
bogdanm	84:0b3ab51c8877	802	#define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /!< Prescaler for External ETR Trigger: Capture performed once every 4 events. /
bogdanm	84:0b3ab51c8877	803	#define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /!< Prescaler for External ETR Trigger: Capture performed once every 8 events. /
bogdanm	84:0b3ab51c8877	804
bogdanm	84:0b3ab51c8877	805	#define IS_TIM_TRIGGERPRESCALER(PRESCALER) (((PRESCALER) == TIM_TRIGGERPRESCALER_DIV1) \|\| \
bogdanm	84:0b3ab51c8877	806	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV2) \|\| \
bogdanm	84:0b3ab51c8877	807	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV4) \|\| \
bogdanm	84:0b3ab51c8877	808	((PRESCALER) == TIM_TRIGGERPRESCALER_DIV8))
bogdanm	84:0b3ab51c8877	809	/**
bogdanm	84:0b3ab51c8877	810	* @}
bogdanm	84:0b3ab51c8877	811	*/
bogdanm	84:0b3ab51c8877	812
bogdanm	84:0b3ab51c8877	813	/** @defgroup TIM_Trigger_Filter
bogdanm	84:0b3ab51c8877	814	* @{
bogdanm	84:0b3ab51c8877	815	*/
bogdanm	84:0b3ab51c8877	816	#define IS_TIM_TRIGGERFILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	84:0b3ab51c8877	817	/**
bogdanm	84:0b3ab51c8877	818	* @}
bogdanm	84:0b3ab51c8877	819	*/
bogdanm	84:0b3ab51c8877	820
bogdanm	84:0b3ab51c8877	821	/** @defgroup TIM_TI1_Selection
bogdanm	84:0b3ab51c8877	822	* @{
bogdanm	84:0b3ab51c8877	823	*/
bogdanm	84:0b3ab51c8877	824	#define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	825	#define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
bogdanm	84:0b3ab51c8877	826
bogdanm	84:0b3ab51c8877	827	#define IS_TIM_TI1SELECTION(TI1SELECTION) (((TI1SELECTION) == TIM_TI1SELECTION_CH1) \|\| \
bogdanm	84:0b3ab51c8877	828	((TI1SELECTION) == TIM_TI1SELECTION_XORCOMBINATION))
bogdanm	84:0b3ab51c8877	829	/**
bogdanm	84:0b3ab51c8877	830	* @}
bogdanm	84:0b3ab51c8877	831	*/
bogdanm	84:0b3ab51c8877	832
bogdanm	92:4fc01daae5a5	833	/** @defgroup TIM_DMA_Base_address
bogdanm	84:0b3ab51c8877	834	* @{
bogdanm	84:0b3ab51c8877	835	*/
bogdanm	84:0b3ab51c8877	836	#define TIM_DMABase_CR1 (0x00000000)
bogdanm	84:0b3ab51c8877	837	#define TIM_DMABase_CR2 (0x00000001)
bogdanm	84:0b3ab51c8877	838	#define TIM_DMABase_SMCR (0x00000002)
bogdanm	84:0b3ab51c8877	839	#define TIM_DMABase_DIER (0x00000003)
bogdanm	84:0b3ab51c8877	840	#define TIM_DMABase_SR (0x00000004)
bogdanm	84:0b3ab51c8877	841	#define TIM_DMABase_EGR (0x00000005)
bogdanm	84:0b3ab51c8877	842	#define TIM_DMABase_CCMR1 (0x00000006)
bogdanm	84:0b3ab51c8877	843	#define TIM_DMABase_CCMR2 (0x00000007)
bogdanm	84:0b3ab51c8877	844	#define TIM_DMABase_CCER (0x00000008)
bogdanm	84:0b3ab51c8877	845	#define TIM_DMABase_CNT (0x00000009)
bogdanm	84:0b3ab51c8877	846	#define TIM_DMABase_PSC (0x0000000A)
bogdanm	84:0b3ab51c8877	847	#define TIM_DMABase_ARR (0x0000000B)
bogdanm	84:0b3ab51c8877	848	#define TIM_DMABase_CCR1 (0x0000000D)
bogdanm	84:0b3ab51c8877	849	#define TIM_DMABase_CCR2 (0x0000000E)
bogdanm	84:0b3ab51c8877	850	#define TIM_DMABase_CCR3 (0x0000000F)
bogdanm	84:0b3ab51c8877	851	#define TIM_DMABase_CCR4 (0x00000010)
bogdanm	84:0b3ab51c8877	852	#define TIM_DMABase_DCR (0x00000012)
bogdanm	84:0b3ab51c8877	853	#define TIM_DMABase_OR (0x00000013)
bogdanm	84:0b3ab51c8877	854	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
bogdanm	84:0b3ab51c8877	855	((BASE) == TIM_DMABase_CR2) \|\| \
bogdanm	84:0b3ab51c8877	856	((BASE) == TIM_DMABase_SMCR) \|\| \
bogdanm	84:0b3ab51c8877	857	((BASE) == TIM_DMABase_DIER) \|\| \
bogdanm	84:0b3ab51c8877	858	((BASE) == TIM_DMABase_SR) \|\| \
bogdanm	84:0b3ab51c8877	859	((BASE) == TIM_DMABase_EGR) \|\| \
bogdanm	84:0b3ab51c8877	860	((BASE) == TIM_DMABase_CCMR1) \|\| \
bogdanm	84:0b3ab51c8877	861	((BASE) == TIM_DMABase_CCMR2) \|\| \
bogdanm	84:0b3ab51c8877	862	((BASE) == TIM_DMABase_CCER) \|\| \
bogdanm	84:0b3ab51c8877	863	((BASE) == TIM_DMABase_CNT) \|\| \
bogdanm	84:0b3ab51c8877	864	((BASE) == TIM_DMABase_PSC) \|\| \
bogdanm	84:0b3ab51c8877	865	((BASE) == TIM_DMABase_ARR) \|\| \
bogdanm	84:0b3ab51c8877	866	((BASE) == TIM_DMABase_CCR1) \|\| \
bogdanm	84:0b3ab51c8877	867	((BASE) == TIM_DMABase_CCR2) \|\| \
bogdanm	84:0b3ab51c8877	868	((BASE) == TIM_DMABase_CCR3) \|\| \
bogdanm	84:0b3ab51c8877	869	((BASE) == TIM_DMABase_CCR4) \|\| \
bogdanm	84:0b3ab51c8877	870	((BASE) == TIM_DMABase_DCR) \|\| \
bogdanm	84:0b3ab51c8877	871	((BASE) == TIM_DMABase_OR))
bogdanm	84:0b3ab51c8877	872	/**
bogdanm	84:0b3ab51c8877	873	* @}
bogdanm	84:0b3ab51c8877	874	*/
bogdanm	84:0b3ab51c8877	875
bogdanm	92:4fc01daae5a5	876	/** @defgroup TIM_DMA_Burst_Length
bogdanm	84:0b3ab51c8877	877	* @{
bogdanm	84:0b3ab51c8877	878	*/
bogdanm	84:0b3ab51c8877	879	#define TIM_DMABurstLength_1Transfer (0x00000000)
bogdanm	84:0b3ab51c8877	880	#define TIM_DMABurstLength_2Transfers (0x00000100)
bogdanm	84:0b3ab51c8877	881	#define TIM_DMABurstLength_3Transfers (0x00000200)
bogdanm	84:0b3ab51c8877	882	#define TIM_DMABurstLength_4Transfers (0x00000300)
bogdanm	84:0b3ab51c8877	883	#define TIM_DMABurstLength_5Transfers (0x00000400)
bogdanm	84:0b3ab51c8877	884	#define TIM_DMABurstLength_6Transfers (0x00000500)
bogdanm	84:0b3ab51c8877	885	#define TIM_DMABurstLength_7Transfers (0x00000600)
bogdanm	84:0b3ab51c8877	886	#define TIM_DMABurstLength_8Transfers (0x00000700)
bogdanm	84:0b3ab51c8877	887	#define TIM_DMABurstLength_9Transfers (0x00000800)
bogdanm	84:0b3ab51c8877	888	#define TIM_DMABurstLength_10Transfers (0x00000900)
bogdanm	84:0b3ab51c8877	889	#define TIM_DMABurstLength_11Transfers (0x00000A00)
bogdanm	84:0b3ab51c8877	890	#define TIM_DMABurstLength_12Transfers (0x00000B00)
bogdanm	84:0b3ab51c8877	891	#define TIM_DMABurstLength_13Transfers (0x00000C00)
bogdanm	84:0b3ab51c8877	892	#define TIM_DMABurstLength_14Transfers (0x00000D00)
bogdanm	84:0b3ab51c8877	893	#define TIM_DMABurstLength_15Transfers (0x00000E00)
bogdanm	84:0b3ab51c8877	894	#define TIM_DMABurstLength_16Transfers (0x00000F00)
bogdanm	84:0b3ab51c8877	895	#define TIM_DMABurstLength_17Transfers (0x00001000)
bogdanm	84:0b3ab51c8877	896	#define TIM_DMABurstLength_18Transfers (0x00001100)
bogdanm	84:0b3ab51c8877	897	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
bogdanm	84:0b3ab51c8877	898	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
bogdanm	84:0b3ab51c8877	899	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
bogdanm	84:0b3ab51c8877	900	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
bogdanm	84:0b3ab51c8877	901	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
bogdanm	84:0b3ab51c8877	902	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
bogdanm	84:0b3ab51c8877	903	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
bogdanm	84:0b3ab51c8877	904	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
bogdanm	84:0b3ab51c8877	905	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
bogdanm	84:0b3ab51c8877	906	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
bogdanm	84:0b3ab51c8877	907	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
bogdanm	84:0b3ab51c8877	908	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
bogdanm	84:0b3ab51c8877	909	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
bogdanm	84:0b3ab51c8877	910	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
bogdanm	84:0b3ab51c8877	911	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
bogdanm	84:0b3ab51c8877	912	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
bogdanm	84:0b3ab51c8877	913	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
bogdanm	84:0b3ab51c8877	914	((LENGTH) == TIM_DMABurstLength_18Transfers))
bogdanm	84:0b3ab51c8877	915	/**
bogdanm	84:0b3ab51c8877	916	* @}
bogdanm	84:0b3ab51c8877	917	*/
bogdanm	84:0b3ab51c8877	918
bogdanm	92:4fc01daae5a5	919	/** @defgroup TIM_Input_Capture_Filer_Value
bogdanm	84:0b3ab51c8877	920	* @{
bogdanm	84:0b3ab51c8877	921	*/
bogdanm	84:0b3ab51c8877	922	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
bogdanm	84:0b3ab51c8877	923	/**
bogdanm	84:0b3ab51c8877	924	* @}
bogdanm	84:0b3ab51c8877	925	*/
bogdanm	84:0b3ab51c8877	926
bogdanm	92:4fc01daae5a5	927	/** @defgroup DMA_Handle_index
bogdanm	84:0b3ab51c8877	928	* @{
bogdanm	84:0b3ab51c8877	929	*/
bogdanm	84:0b3ab51c8877	930	#define TIM_DMA_ID_UPDATE ((uint16_t) 0x0) /!< Index of the DMA handle used for Update DMA requests /
bogdanm	84:0b3ab51c8877	931	#define TIM_DMA_ID_CC1 ((uint16_t) 0x1) /!< Index of the DMA handle used for Capture/Compare 1 DMA requests /
bogdanm	84:0b3ab51c8877	932	#define TIM_DMA_ID_CC2 ((uint16_t) 0x2) /!< Index of the DMA handle used for Capture/Compare 2 DMA requests /
bogdanm	84:0b3ab51c8877	933	#define TIM_DMA_ID_CC3 ((uint16_t) 0x3) /!< Index of the DMA handle used for Capture/Compare 3 DMA requests /
bogdanm	84:0b3ab51c8877	934	#define TIM_DMA_ID_CC4 ((uint16_t) 0x4) /!< Index of the DMA handle used for Capture/Compare 4 DMA requests /
bogdanm	84:0b3ab51c8877	935	#define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5) /!< Index of the DMA handle used for Trigger DMA requests /
bogdanm	84:0b3ab51c8877	936	/**
bogdanm	84:0b3ab51c8877	937	* @}
bogdanm	84:0b3ab51c8877	938	*/
bogdanm	84:0b3ab51c8877	939
bogdanm	92:4fc01daae5a5	940	/** @defgroup Channel_CC_State
bogdanm	84:0b3ab51c8877	941	* @{
bogdanm	84:0b3ab51c8877	942	*/
bogdanm	84:0b3ab51c8877	943	#define TIM_CCx_ENABLE ((uint32_t)0x0001)
bogdanm	84:0b3ab51c8877	944	#define TIM_CCx_DISABLE ((uint32_t)0x0000)
bogdanm	84:0b3ab51c8877	945	/**
bogdanm	84:0b3ab51c8877	946	* @}
bogdanm	84:0b3ab51c8877	947	*/
bogdanm	84:0b3ab51c8877	948
bogdanm	84:0b3ab51c8877	949	/**
bogdanm	84:0b3ab51c8877	950	* @}
bogdanm	84:0b3ab51c8877	951	*/
bogdanm	84:0b3ab51c8877	952
bogdanm	84:0b3ab51c8877	953	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	954	/** @defgroup TIM_Exported_Macro
bogdanm	92:4fc01daae5a5	955	* @{
bogdanm	92:4fc01daae5a5	956	*/
bogdanm	84:0b3ab51c8877	957
bogdanm	84:0b3ab51c8877	958	/** @brief Reset UART handle state
bogdanm	84:0b3ab51c8877	959	* @param __HANDLE__: TIM handle
bogdanm	84:0b3ab51c8877	960	* @retval None
bogdanm	84:0b3ab51c8877	961	*/
bogdanm	84:0b3ab51c8877	962	#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
bogdanm	84:0b3ab51c8877	963
bogdanm	84:0b3ab51c8877	964	/**
bogdanm	84:0b3ab51c8877	965	* @brief Enable the TIM peripheral.
bogdanm	84:0b3ab51c8877	966	* @param __HANDLE__: TIM handle
bogdanm	84:0b3ab51c8877	967	* @retval None
bogdanm	84:0b3ab51c8877	968	*/
bogdanm	84:0b3ab51c8877	969	#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1\|=(TIM_CR1_CEN))
bogdanm	84:0b3ab51c8877	970
bogdanm	84:0b3ab51c8877	971	/* The counter of a timer instance is disabled only if all the CCx channels have
bogdanm	84:0b3ab51c8877	972	been disabled */
bogdanm	84:0b3ab51c8877	973	#define CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E \| TIM_CCER_CC2E \| TIM_CCER_CC3E \| TIM_CCER_CC4E))
bogdanm	84:0b3ab51c8877	974
bogdanm	84:0b3ab51c8877	975	/**
bogdanm	84:0b3ab51c8877	976	* @brief Disable the TIM peripheral.
bogdanm	84:0b3ab51c8877	977	* @param __HANDLE__: TIM handle
bogdanm	84:0b3ab51c8877	978	* @retval None
bogdanm	84:0b3ab51c8877	979	*/
bogdanm	84:0b3ab51c8877	980	#define __HAL_TIM_DISABLE(__HANDLE__) \
bogdanm	84:0b3ab51c8877	981	do { \
bogdanm	84:0b3ab51c8877	982	if (((__HANDLE__)->Instance->CCER & CCER_CCxE_MASK) == 0) \
bogdanm	84:0b3ab51c8877	983	{ \
bogdanm	84:0b3ab51c8877	984	(__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
bogdanm	84:0b3ab51c8877	985	} \
bogdanm	84:0b3ab51c8877	986	} while(0)
bogdanm	84:0b3ab51c8877	987
bogdanm	84:0b3ab51c8877	988	#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER \|= (__INTERRUPT__))
bogdanm	84:0b3ab51c8877	989	#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER \|= (__DMA__))
bogdanm	84:0b3ab51c8877	990	#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
bogdanm	84:0b3ab51c8877	991	#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
bogdanm	84:0b3ab51c8877	992	#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
bogdanm	92:4fc01daae5a5	993	#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
bogdanm	84:0b3ab51c8877	994
bogdanm	84:0b3ab51c8877	995	#define __HAL_TIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm	92:4fc01daae5a5	996	#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
bogdanm	84:0b3ab51c8877	997
bogdanm	84:0b3ab51c8877	998	#define __HAL_TIM_DIRECTION_STATUS(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
bogdanm	92:4fc01daae5a5	999	#define __HAL_TIM_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
bogdanm	84:0b3ab51c8877	1000
bogdanm	84:0b3ab51c8877	1001	#define __HAL_TIM_SetICPrescalerValue(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	84:0b3ab51c8877	1002	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 \|= (__ICPSC__)) :\
bogdanm	84:0b3ab51c8877	1003	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 \|= ((__ICPSC__) << 8)) :\
bogdanm	84:0b3ab51c8877	1004	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 \|= (__ICPSC__)) :\
bogdanm	84:0b3ab51c8877	1005	((__HANDLE__)->Instance->CCMR2 \|= ((__ICPSC__) << 8)))
bogdanm	84:0b3ab51c8877	1006
bogdanm	84:0b3ab51c8877	1007	#define __HAL_TIM_ResetICPrescalerValue(__HANDLE__, __CHANNEL__) \
bogdanm	84:0b3ab51c8877	1008	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
bogdanm	84:0b3ab51c8877	1009	((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
bogdanm	84:0b3ab51c8877	1010	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
bogdanm	84:0b3ab51c8877	1011	((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
bogdanm	84:0b3ab51c8877	1012
bogdanm	84:0b3ab51c8877	1013	/**
bogdanm	84:0b3ab51c8877	1014	* @brief Sets the TIM Capture Compare Register value on runtime without
bogdanm	84:0b3ab51c8877	1015	* calling another time ConfigChannel function.
bogdanm	84:0b3ab51c8877	1016	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1017	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	84:0b3ab51c8877	1018	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1019	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	84:0b3ab51c8877	1020	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	84:0b3ab51c8877	1021	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	84:0b3ab51c8877	1022	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	84:0b3ab51c8877	1023	* @param __COMPARE__: specifies the Capture Compare register new value.
bogdanm	84:0b3ab51c8877	1024	* @retval None
bogdanm	84:0b3ab51c8877	1025	*/
bogdanm	84:0b3ab51c8877	1026	#define __HAL_TIM_SetCompare(__HANDLE__, __CHANNEL__, __COMPARE__) \
bogdanm	84:0b3ab51c8877	1027	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)) = (__COMPARE__))
bogdanm	84:0b3ab51c8877	1028
bogdanm	84:0b3ab51c8877	1029	/**
bogdanm	84:0b3ab51c8877	1030	* @brief Gets the TIM Capture Compare Register value on runtime
bogdanm	84:0b3ab51c8877	1031	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1032	* @param __CHANNEL__ : TIM Channel associated with the capture compare register
bogdanm	84:0b3ab51c8877	1033	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1034	* @arg TIM_CHANNEL_1: get capture/compare 1 register value
bogdanm	84:0b3ab51c8877	1035	* @arg TIM_CHANNEL_2: get capture/compare 2 register value
bogdanm	84:0b3ab51c8877	1036	* @arg TIM_CHANNEL_3: get capture/compare 3 register value
bogdanm	84:0b3ab51c8877	1037	* @arg TIM_CHANNEL_4: get capture/compare 4 register value
bogdanm	84:0b3ab51c8877	1038	* @retval None
bogdanm	84:0b3ab51c8877	1039	*/
bogdanm	84:0b3ab51c8877	1040	#define __HAL_TIM_GetCompare(__HANDLE__, __CHANNEL__) \
bogdanm	84:0b3ab51c8877	1041	((__IO uint32_t )(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2)))
bogdanm	84:0b3ab51c8877	1042
bogdanm	84:0b3ab51c8877	1043	/**
bogdanm	84:0b3ab51c8877	1044	* @brief Sets the TIM Counter Register value on runtime.
bogdanm	84:0b3ab51c8877	1045	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1046	* @param __COUNTER__: specifies the Counter register new value.
bogdanm	84:0b3ab51c8877	1047	* @retval None
bogdanm	84:0b3ab51c8877	1048	*/
bogdanm	84:0b3ab51c8877	1049	#define __HAL_TIM_SetCounter(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
bogdanm	84:0b3ab51c8877	1050
bogdanm	84:0b3ab51c8877	1051	/**
bogdanm	84:0b3ab51c8877	1052	* @brief Gets the TIM Counter Register value on runtime.
bogdanm	84:0b3ab51c8877	1053	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1054	* @retval None
bogdanm	84:0b3ab51c8877	1055	*/
bogdanm	84:0b3ab51c8877	1056	#define __HAL_TIM_GetCounter(__HANDLE__) ((__HANDLE__)->Instance->CNT)
bogdanm	84:0b3ab51c8877	1057
bogdanm	84:0b3ab51c8877	1058	/**
bogdanm	84:0b3ab51c8877	1059	* @brief Sets the TIM Autoreload Register value on runtime without calling
bogdanm	84:0b3ab51c8877	1060	* another time any Init function.
bogdanm	84:0b3ab51c8877	1061	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1062	* @param __AUTORELOAD__: specifies the Counter register new value.
bogdanm	84:0b3ab51c8877	1063	* @retval None
bogdanm	84:0b3ab51c8877	1064	*/
bogdanm	84:0b3ab51c8877	1065	#define __HAL_TIM_SetAutoreload(__HANDLE__, __AUTORELOAD__) \
bogdanm	84:0b3ab51c8877	1066	do{ \
bogdanm	84:0b3ab51c8877	1067	(__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
bogdanm	84:0b3ab51c8877	1068	(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
bogdanm	84:0b3ab51c8877	1069	} while(0)
bogdanm	84:0b3ab51c8877	1070	/**
bogdanm	84:0b3ab51c8877	1071	* @brief Gets the TIM Autoreload Register value on runtime
bogdanm	84:0b3ab51c8877	1072	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1073	* @retval None
bogdanm	84:0b3ab51c8877	1074	*/
bogdanm	84:0b3ab51c8877	1075	#define __HAL_TIM_GetAutoreload(__HANDLE__) ((__HANDLE__)->Instance->ARR)
bogdanm	84:0b3ab51c8877	1076
bogdanm	84:0b3ab51c8877	1077	/**
bogdanm	84:0b3ab51c8877	1078	* @brief Sets the TIM Clock Division value on runtime without calling
bogdanm	84:0b3ab51c8877	1079	* another time any Init function.
bogdanm	84:0b3ab51c8877	1080	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1081	* @param __CKD__: specifies the clock division value.
bogdanm	84:0b3ab51c8877	1082	* This parameter can be one of the following value:
bogdanm	84:0b3ab51c8877	1083	* @arg TIM_CLOCKDIVISION_DIV1
bogdanm	84:0b3ab51c8877	1084	* @arg TIM_CLOCKDIVISION_DIV2
bogdanm	84:0b3ab51c8877	1085	* @arg TIM_CLOCKDIVISION_DIV4
bogdanm	84:0b3ab51c8877	1086	* @retval None
bogdanm	84:0b3ab51c8877	1087	*/
bogdanm	84:0b3ab51c8877	1088	#define __HAL_TIM_SetClockDivision(__HANDLE__, __CKD__) \
bogdanm	84:0b3ab51c8877	1089	do{ \
bogdanm	84:0b3ab51c8877	1090	(__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
bogdanm	84:0b3ab51c8877	1091	(__HANDLE__)->Instance->CR1 \|= (__CKD__); \
bogdanm	84:0b3ab51c8877	1092	(__HANDLE__)->Init.ClockDivision = (__CKD__); \
bogdanm	84:0b3ab51c8877	1093	} while(0)
bogdanm	84:0b3ab51c8877	1094	/**
bogdanm	84:0b3ab51c8877	1095	* @brief Gets the TIM Clock Division value on runtime
bogdanm	84:0b3ab51c8877	1096	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1097	* @retval None
bogdanm	84:0b3ab51c8877	1098	*/
bogdanm	84:0b3ab51c8877	1099	#define __HAL_TIM_GetClockDivision(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
bogdanm	84:0b3ab51c8877	1100
bogdanm	84:0b3ab51c8877	1101	/**
bogdanm	84:0b3ab51c8877	1102	* @brief Sets the TIM Input Capture prescaler on runtime without calling
bogdanm	84:0b3ab51c8877	1103	* another time HAL_TIM_IC_ConfigChannel() function.
bogdanm	84:0b3ab51c8877	1104	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1105	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	84:0b3ab51c8877	1106	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1107	* @arg TIM_CHANNEL_1: TIM Channel 1 selected
bogdanm	84:0b3ab51c8877	1108	* @arg TIM_CHANNEL_2: TIM Channel 2 selected
bogdanm	84:0b3ab51c8877	1109	* @arg TIM_CHANNEL_3: TIM Channel 3 selected
bogdanm	84:0b3ab51c8877	1110	* @arg TIM_CHANNEL_4: TIM Channel 4 selected
bogdanm	84:0b3ab51c8877	1111	* @param __ICPSC__: specifies the Input Capture4 prescaler new value.
bogdanm	84:0b3ab51c8877	1112	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1113	* @arg TIM_ICPSC_DIV1: no prescaler
bogdanm	84:0b3ab51c8877	1114	* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
bogdanm	84:0b3ab51c8877	1115	* @arg TIM_ICPSC_DIV4: capture is done once every 4 events
bogdanm	84:0b3ab51c8877	1116	* @arg TIM_ICPSC_DIV8: capture is done once every 8 events
bogdanm	84:0b3ab51c8877	1117	* @retval None
bogdanm	84:0b3ab51c8877	1118	*/
bogdanm	84:0b3ab51c8877	1119	#define __HAL_TIM_SetICPrescaler(__HANDLE__, __CHANNEL__, __ICPSC__) \
bogdanm	84:0b3ab51c8877	1120	do{ \
bogdanm	84:0b3ab51c8877	1121	__HAL_TIM_ResetICPrescalerValue((__HANDLE__), (__CHANNEL__)); \
bogdanm	84:0b3ab51c8877	1122	__HAL_TIM_SetICPrescalerValue((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
bogdanm	84:0b3ab51c8877	1123	} while(0)
bogdanm	84:0b3ab51c8877	1124
bogdanm	84:0b3ab51c8877	1125	/**
bogdanm	84:0b3ab51c8877	1126	* @brief Gets the TIM Input Capture prescaler on runtime
bogdanm	84:0b3ab51c8877	1127	* @param __HANDLE__: TIM handle.
bogdanm	84:0b3ab51c8877	1128	* @param __CHANNEL__ : TIM Channels to be configured.
bogdanm	84:0b3ab51c8877	1129	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1130	* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
bogdanm	84:0b3ab51c8877	1131	* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
bogdanm	84:0b3ab51c8877	1132	* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
bogdanm	84:0b3ab51c8877	1133	* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
bogdanm	84:0b3ab51c8877	1134	* @retval None
bogdanm	84:0b3ab51c8877	1135	*/
bogdanm	84:0b3ab51c8877	1136	#define __HAL_TIM_GetICPrescaler(__HANDLE__, __CHANNEL__) \
bogdanm	84:0b3ab51c8877	1137	(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
bogdanm	84:0b3ab51c8877	1138	((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
bogdanm	84:0b3ab51c8877	1139	((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
bogdanm	84:0b3ab51c8877	1140	(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
bogdanm	92:4fc01daae5a5	1141
bogdanm	92:4fc01daae5a5	1142
bogdanm	92:4fc01daae5a5	1143	/**
bogdanm	92:4fc01daae5a5	1144	* @}
bogdanm	92:4fc01daae5a5	1145	*/
bogdanm	92:4fc01daae5a5	1146
bogdanm	84:0b3ab51c8877	1147	/* Include TIM HAL Extension module */
bogdanm	84:0b3ab51c8877	1148	#include "stm32l0xx_hal_tim_ex.h"
bogdanm	84:0b3ab51c8877	1149
bogdanm	84:0b3ab51c8877	1150	/* Exported functions --------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	1151	/* Time Base functions ********************************************************/
bogdanm	84:0b3ab51c8877	1152	HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1153	HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1154	void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1155	void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1156	/* Blocking mode: Polling */
bogdanm	84:0b3ab51c8877	1157	HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1158	HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1159	/* Non-Blocking mode: Interrupt */
bogdanm	84:0b3ab51c8877	1160	HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1161	HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1162	/* Non-Blocking mode: DMA */
bogdanm	84:0b3ab51c8877	1163	HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef htim, uint32_t pData, uint16_t Length);
bogdanm	84:0b3ab51c8877	1164	HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1165
bogdanm	84:0b3ab51c8877	1166	/* Timer Output Compare functions **********************************************/
bogdanm	84:0b3ab51c8877	1167	HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1168	HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1169	void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1170	void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1171	/* Blocking mode: Polling */
bogdanm	84:0b3ab51c8877	1172	HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1173	HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1174	/* Non-Blocking mode: Interrupt */
bogdanm	84:0b3ab51c8877	1175	HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1176	HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1177	/* Non-Blocking mode: DMA */
bogdanm	84:0b3ab51c8877	1178	HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	84:0b3ab51c8877	1179	HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1180
bogdanm	84:0b3ab51c8877	1181	/* Timer PWM functions *********************************************************/
bogdanm	84:0b3ab51c8877	1182	HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1183	HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1184	void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1185	void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1186	/* Blocking mode: Polling */
bogdanm	84:0b3ab51c8877	1187	HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1188	HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1189	/* Non-Blocking mode: Interrupt */
bogdanm	84:0b3ab51c8877	1190	HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1191	HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1192	/* Non-Blocking mode: DMA */
bogdanm	84:0b3ab51c8877	1193	HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	84:0b3ab51c8877	1194	HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1195
bogdanm	84:0b3ab51c8877	1196	/* Timer Input Capture functions ***********************************************/
bogdanm	84:0b3ab51c8877	1197	HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1198	HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1199	void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1200	void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1201	/* Blocking mode: Polling */
bogdanm	84:0b3ab51c8877	1202	HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1203	HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1204	/* Non-Blocking mode: Interrupt */
bogdanm	84:0b3ab51c8877	1205	HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1206	HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1207	/* Non-Blocking mode: DMA */
bogdanm	84:0b3ab51c8877	1208	HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData, uint16_t Length);
bogdanm	84:0b3ab51c8877	1209	HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1210
bogdanm	84:0b3ab51c8877	1211	/* Timer One Pulse functions ***************************************************/
bogdanm	84:0b3ab51c8877	1212	HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
bogdanm	84:0b3ab51c8877	1213	HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1214	void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1215	void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1216	/* Blocking mode: Polling */
bogdanm	84:0b3ab51c8877	1217	HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	84:0b3ab51c8877	1218	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	84:0b3ab51c8877	1219
bogdanm	84:0b3ab51c8877	1220	/* Non-Blocking mode: Interrupt */
bogdanm	84:0b3ab51c8877	1221	HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	84:0b3ab51c8877	1222	HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
bogdanm	84:0b3ab51c8877	1223
bogdanm	84:0b3ab51c8877	1224	/* Timer Encoder functions *****************************************************/
bogdanm	84:0b3ab51c8877	1225	HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef htim, TIM_Encoder_InitTypeDef sConfig);
bogdanm	84:0b3ab51c8877	1226	HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1227	void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1228	void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1229	/* Blocking mode: Polling */
bogdanm	84:0b3ab51c8877	1230	HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1231	HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1232	/* Non-Blocking mode: Interrupt */
bogdanm	84:0b3ab51c8877	1233	HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1234	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1235	/* Non-Blocking mode: DMA */
bogdanm	84:0b3ab51c8877	1236	HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef htim, uint32_t Channel, uint32_t pData1, uint32_t *pData2, uint16_t Length);
bogdanm	84:0b3ab51c8877	1237	HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1238
bogdanm	84:0b3ab51c8877	1239	/* Interrupt Handler functions **********************************************/
bogdanm	84:0b3ab51c8877	1240	void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1241
bogdanm	84:0b3ab51c8877	1242	/* Control functions *********************************************************/
bogdanm	84:0b3ab51c8877	1243	HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1244	HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef htim, TIM_OC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1245	HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef htim, TIM_IC_InitTypeDef sConfig, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1246	HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef htim, TIM_OnePulse_InitTypeDef sConfig, uint32_t OutputChannel, uint32_t InputChannel);
bogdanm	84:0b3ab51c8877	1247	HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef htim, TIM_ClearInputConfigTypeDef sClearInputConfig, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1248	HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef htim, TIM_ClockConfigTypeDef sClockSourceConfig);
bogdanm	84:0b3ab51c8877	1249	HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
bogdanm	84:0b3ab51c8877	1250	HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef htim, TIM_SlaveConfigTypeDef sSlaveConfig);
bogdanm	84:0b3ab51c8877	1251	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	84:0b3ab51c8877	1252	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	84:0b3ab51c8877	1253	HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	84:0b3ab51c8877	1254	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
bogdanm	84:0b3ab51c8877	1255	uint32_t *BurstBuffer, uint32_t BurstLength);
bogdanm	84:0b3ab51c8877	1256	HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
bogdanm	84:0b3ab51c8877	1257	HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
bogdanm	84:0b3ab51c8877	1258	uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
bogdanm	84:0b3ab51c8877	1259
bogdanm	84:0b3ab51c8877	1260	/* Callback in non blocking modes (Interrupt and DMA) *************************/
bogdanm	84:0b3ab51c8877	1261	void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1262	void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1263	void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1264	void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1265	void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1266	void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1267
bogdanm	84:0b3ab51c8877	1268	/* Peripheral State functions **************************************************/
bogdanm	84:0b3ab51c8877	1269	HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1270	HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1271	HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1272	HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1273	HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1274	HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
bogdanm	84:0b3ab51c8877	1275	void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
bogdanm	84:0b3ab51c8877	1276	void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
bogdanm	84:0b3ab51c8877	1277	void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
bogdanm	84:0b3ab51c8877	1278
bogdanm	84:0b3ab51c8877	1279	/**
bogdanm	84:0b3ab51c8877	1280	* @}
bogdanm	84:0b3ab51c8877	1281	*/
bogdanm	84:0b3ab51c8877	1282
bogdanm	84:0b3ab51c8877	1283	/**
bogdanm	84:0b3ab51c8877	1284	* @}
bogdanm	84:0b3ab51c8877	1285	*/
bogdanm	84:0b3ab51c8877	1286
bogdanm	84:0b3ab51c8877	1287	#ifdef __cplusplus
bogdanm	84:0b3ab51c8877	1288	}
bogdanm	84:0b3ab51c8877	1289	#endif
bogdanm	84:0b3ab51c8877	1290
bogdanm	84:0b3ab51c8877	1291	#endif /* __STM32L0xx_HAL_TIM_H */
bogdanm	84:0b3ab51c8877	1292
bogdanm	84:0b3ab51c8877	1293	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

Repository toolbox

Export to desktop IDE

Repository details

Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_NUCLEO_L053R8/stm32l0xx_hal_tim.h@92:4fc01daae5a5, 2014-11-27 (annotated)

Who changed what in which revision?

Repository toolbox

Repository details

Important Information for this Arm website

Access Warning