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TARGET_NUCLEO_L152RE/stm32l1xx_hal_rcc.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:: filartrix
Date:: Wed Apr 08 14:12:53 2015 +0000
Revision:: 97:4298809c7c9e
Parent:: 90:cb3d968589d8

First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/**
Kojto	90:cb3d968589d8	2	******************************************************************************
Kojto	90:cb3d968589d8	3	* @file stm32l1xx_hal_rcc.h
Kojto	90:cb3d968589d8	4	* @author MCD Application Team
Kojto	90:cb3d968589d8	5	* @version V1.0.0
Kojto	90:cb3d968589d8	6	* @date 5-September-2014
Kojto	90:cb3d968589d8	7	* @brief Header file of RCC HAL module.
Kojto	90:cb3d968589d8	8	******************************************************************************
Kojto	90:cb3d968589d8	9	* @attention
Kojto	90:cb3d968589d8	10	*
Kojto	90:cb3d968589d8	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	90:cb3d968589d8	12	*
Kojto	90:cb3d968589d8	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	14	* are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	90:cb3d968589d8	16	* this list of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	90:cb3d968589d8	18	* this list of conditions and the following disclaimer in the documentation
Kojto	90:cb3d968589d8	19	* and/or other materials provided with the distribution.
Kojto	90:cb3d968589d8	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	90:cb3d968589d8	21	* may be used to endorse or promote products derived from this software
Kojto	90:cb3d968589d8	22	* without specific prior written permission.
Kojto	90:cb3d968589d8	23	*
Kojto	90:cb3d968589d8	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	90:cb3d968589d8	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	90:cb3d968589d8	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	90:cb3d968589d8	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	90:cb3d968589d8	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	90:cb3d968589d8	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	90:cb3d968589d8	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	90:cb3d968589d8	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	90:cb3d968589d8	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	34	*
Kojto	90:cb3d968589d8	35	******************************************************************************
Kojto	90:cb3d968589d8	36	*/
Kojto	90:cb3d968589d8	37
Kojto	90:cb3d968589d8	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	90:cb3d968589d8	39	#ifndef __STM32L1xx_HAL_RCC_H
Kojto	90:cb3d968589d8	40	#define __STM32L1xx_HAL_RCC_H
Kojto	90:cb3d968589d8	41
Kojto	90:cb3d968589d8	42	#ifdef __cplusplus
Kojto	90:cb3d968589d8	43	extern "C" {
Kojto	90:cb3d968589d8	44	#endif
Kojto	90:cb3d968589d8	45
Kojto	90:cb3d968589d8	46	/* Includes ------------------------------------------------------------------*/
Kojto	90:cb3d968589d8	47	#include "stm32l1xx_hal_def.h"
Kojto	90:cb3d968589d8	48
Kojto	90:cb3d968589d8	49	/** @addtogroup STM32L1xx_HAL_Driver
Kojto	90:cb3d968589d8	50	* @{
Kojto	90:cb3d968589d8	51	*/
Kojto	90:cb3d968589d8	52
Kojto	90:cb3d968589d8	53	/** @addtogroup RCC
Kojto	90:cb3d968589d8	54	* @{
Kojto	90:cb3d968589d8	55	*/
Kojto	90:cb3d968589d8	56
Kojto	90:cb3d968589d8	57	/* Exported types ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	58
Kojto	90:cb3d968589d8	59	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	90:cb3d968589d8	60	* @{
Kojto	90:cb3d968589d8	61	*/
Kojto	90:cb3d968589d8	62
Kojto	90:cb3d968589d8	63	/**
Kojto	90:cb3d968589d8	64	* @brief RCC PLL configuration structure definition
Kojto	90:cb3d968589d8	65	*/
Kojto	90:cb3d968589d8	66	typedef struct
Kojto	90:cb3d968589d8	67	{
Kojto	90:cb3d968589d8	68	uint32_t PLLState; /*!< The new state of the PLL.
Kojto	90:cb3d968589d8	69	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	90:cb3d968589d8	70
Kojto	90:cb3d968589d8	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	90:cb3d968589d8	72	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	90:cb3d968589d8	73
Kojto	90:cb3d968589d8	74	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	90:cb3d968589d8	75	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
Kojto	90:cb3d968589d8	76
Kojto	90:cb3d968589d8	77	uint32_t PLLDIV; /*!< PLLDIV: Division factor for PLL VCO input clock
Kojto	90:cb3d968589d8	78	This parameter must be a value of @ref RCC_PLL_Division_Factor*/
Kojto	90:cb3d968589d8	79	} RCC_PLLInitTypeDef;
Kojto	90:cb3d968589d8	80
Kojto	90:cb3d968589d8	81	/**
Kojto	90:cb3d968589d8	82	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	90:cb3d968589d8	83	*/
Kojto	90:cb3d968589d8	84	typedef struct
Kojto	90:cb3d968589d8	85	{
Kojto	90:cb3d968589d8	86	uint32_t OscillatorType; /*!< The oscillators to be configured.
Kojto	90:cb3d968589d8	87	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	90:cb3d968589d8	88
Kojto	90:cb3d968589d8	89	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	90:cb3d968589d8	90	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	90:cb3d968589d8	91
Kojto	90:cb3d968589d8	92	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	90:cb3d968589d8	93	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	90:cb3d968589d8	94
Kojto	90:cb3d968589d8	95	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	90:cb3d968589d8	96	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	90:cb3d968589d8	97
Kojto	90:cb3d968589d8	98	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	90:cb3d968589d8	99	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	90:cb3d968589d8	100
Kojto	90:cb3d968589d8	101	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	90:cb3d968589d8	102	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	90:cb3d968589d8	103
Kojto	90:cb3d968589d8	104	uint32_t MSIState; /*!< The new state of the MSI.
Kojto	90:cb3d968589d8	105	This parameter can be a value of @ref RCC_MSI_Config */
Kojto	90:cb3d968589d8	106
Kojto	90:cb3d968589d8	107	uint32_t MSICalibrationValue; /*!< The MSI calibration trimming value. (default is RCC_MSICALIBRATION_DEFAULT).
Kojto	90:cb3d968589d8	108	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF */
Kojto	90:cb3d968589d8	109
Kojto	90:cb3d968589d8	110	uint32_t MSIClockRange; /*!< The MSI frequency range.
Kojto	90:cb3d968589d8	111	This parameter can be a value of @ref RCC_MSI_Clock_Range */
Kojto	90:cb3d968589d8	112
Kojto	90:cb3d968589d8	113	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	90:cb3d968589d8	114
Kojto	90:cb3d968589d8	115	} RCC_OscInitTypeDef;
Kojto	90:cb3d968589d8	116
Kojto	90:cb3d968589d8	117	/**
Kojto	90:cb3d968589d8	118	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	90:cb3d968589d8	119	*/
Kojto	90:cb3d968589d8	120	typedef struct
Kojto	90:cb3d968589d8	121	{
Kojto	90:cb3d968589d8	122	uint32_t ClockType; /*!< The clock to be configured.
Kojto	90:cb3d968589d8	123	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	90:cb3d968589d8	124
Kojto	90:cb3d968589d8	125	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	90:cb3d968589d8	126	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	90:cb3d968589d8	127
Kojto	90:cb3d968589d8	128	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	90:cb3d968589d8	129	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	90:cb3d968589d8	130
Kojto	90:cb3d968589d8	131	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	90:cb3d968589d8	132	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	90:cb3d968589d8	133
Kojto	90:cb3d968589d8	134	uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
Kojto	90:cb3d968589d8	135	This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
Kojto	90:cb3d968589d8	136
Kojto	90:cb3d968589d8	137	} RCC_ClkInitTypeDef;
Kojto	90:cb3d968589d8	138
Kojto	90:cb3d968589d8	139	/**
Kojto	90:cb3d968589d8	140	* @}
Kojto	90:cb3d968589d8	141	*/
Kojto	90:cb3d968589d8	142
Kojto	90:cb3d968589d8	143	/* Exported constants --------------------------------------------------------*/
Kojto	90:cb3d968589d8	144	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	90:cb3d968589d8	145	* @{
Kojto	90:cb3d968589d8	146	*/
Kojto	90:cb3d968589d8	147	#define DBP_TIMEOUT_VALUE ((uint32_t)100)
Kojto	90:cb3d968589d8	148	#define LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
Kojto	90:cb3d968589d8	149
Kojto	90:cb3d968589d8	150	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	90:cb3d968589d8	151	* @brief RCC registers bit address in the alias region
Kojto	90:cb3d968589d8	152	* @{
Kojto	90:cb3d968589d8	153	*/
Kojto	90:cb3d968589d8	154	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	90:cb3d968589d8	155	#define RCC_CR_OFFSET 0x00
Kojto	90:cb3d968589d8	156	#define RCC_CFGR_OFFSET 0x08
Kojto	90:cb3d968589d8	157	#define RCC_CIR_OFFSET 0x0C
Kojto	90:cb3d968589d8	158	#define RCC_CSR_OFFSET 0x34
Kojto	90:cb3d968589d8	159	#define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
Kojto	90:cb3d968589d8	160	#define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
Kojto	90:cb3d968589d8	161	#define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
Kojto	90:cb3d968589d8	162	#define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
Kojto	90:cb3d968589d8	163
Kojto	90:cb3d968589d8	164	/* --- CR Register ---*/
Kojto	90:cb3d968589d8	165	/* Alias word address of HSION bit */
Kojto	90:cb3d968589d8	166	#define HSION_BITNUMBER POSITION_VAL(RCC_CR_HSION)
Kojto	90:cb3d968589d8	167	#define CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSION_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	168	/* Alias word address of MSION bit */
Kojto	90:cb3d968589d8	169	#define MSION_BITNUMBER POSITION_VAL(RCC_CR_MSION)
Kojto	90:cb3d968589d8	170	#define CR_MSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (MSION_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	171	/* Alias word address of HSEON bit */
Kojto	90:cb3d968589d8	172	#define HSEON_BITNUMBER POSITION_VAL(RCC_CR_HSEON)
Kojto	90:cb3d968589d8	173	#define CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (HSEON_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	174	/* Alias word address of CSSON bit */
Kojto	90:cb3d968589d8	175	#define CSSON_BITNUMBER POSITION_VAL(RCC_CR_CSSON)
Kojto	90:cb3d968589d8	176	#define CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (CSSON_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	177	/* Alias word address of PLLON bit */
Kojto	90:cb3d968589d8	178	#define PLLON_BITNUMBER POSITION_VAL(RCC_CR_PLLON)
Kojto	90:cb3d968589d8	179	#define CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32) + (PLLON_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	180
Kojto	90:cb3d968589d8	181	/* --- CSR Register ---*/
Kojto	90:cb3d968589d8	182	/* Alias word address of LSION bit */
Kojto	90:cb3d968589d8	183	#define LSION_BITNUMBER POSITION_VAL(RCC_CSR_LSION)
Kojto	90:cb3d968589d8	184	#define CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSION_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	185
Kojto	90:cb3d968589d8	186	/* Alias word address of LSEON bit */
Kojto	90:cb3d968589d8	187	#define LSEON_BITNUMBER POSITION_VAL(RCC_CSR_LSEON)
Kojto	90:cb3d968589d8	188	#define CSR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEON_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	189
Kojto	90:cb3d968589d8	190	/* Alias word address of LSEON bit */
Kojto	90:cb3d968589d8	191	#define LSEBYP_BITNUMBER POSITION_VAL(RCC_CSR_LSEBYP)
Kojto	90:cb3d968589d8	192	#define CSR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (LSEBYP_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	193
Kojto	90:cb3d968589d8	194	/* Alias word address of RTCEN bit */
Kojto	90:cb3d968589d8	195	#define RTCEN_BITNUMBER POSITION_VAL(RCC_CSR_RTCEN)
Kojto	90:cb3d968589d8	196	#define CSR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCEN_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	197
Kojto	90:cb3d968589d8	198	/* Alias word address of RTCRST bit */
Kojto	90:cb3d968589d8	199	#define RTCRST_BITNUMBER POSITION_VAL(RCC_CSR_RTCRST)
Kojto	90:cb3d968589d8	200	#define CSR_RTCRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32) + (RTCRST_BITNUMBER * 4)))
Kojto	90:cb3d968589d8	201
Kojto	90:cb3d968589d8	202	/* CR register byte 2 (Bits[23:16]) base address */
Kojto	90:cb3d968589d8	203	#define CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02))
Kojto	90:cb3d968589d8	204
Kojto	90:cb3d968589d8	205	/* CIR register byte 1 (Bits[15:8]) base address */
Kojto	90:cb3d968589d8	206	#define CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01))
Kojto	90:cb3d968589d8	207
Kojto	90:cb3d968589d8	208	/* CIR register byte 2 (Bits[23:16]) base address */
Kojto	90:cb3d968589d8	209	#define CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02))
Kojto	90:cb3d968589d8	210
Kojto	90:cb3d968589d8	211	/**
Kojto	90:cb3d968589d8	212	* @}
Kojto	90:cb3d968589d8	213	*/
Kojto	90:cb3d968589d8	214
Kojto	90:cb3d968589d8	215	/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
Kojto	90:cb3d968589d8	216	* @{
Kojto	90:cb3d968589d8	217	*/
Kojto	90:cb3d968589d8	218
Kojto	90:cb3d968589d8	219	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI
Kojto	90:cb3d968589d8	220	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE
Kojto	90:cb3d968589d8	221
Kojto	90:cb3d968589d8	222	#define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	223	((__SOURCE__) == RCC_PLLSOURCE_HSE))
Kojto	90:cb3d968589d8	224	/**
Kojto	90:cb3d968589d8	225	* @}
Kojto	90:cb3d968589d8	226	*/
Kojto	90:cb3d968589d8	227
Kojto	90:cb3d968589d8	228	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
Kojto	90:cb3d968589d8	229	* @{
Kojto	90:cb3d968589d8	230	*/
Kojto	90:cb3d968589d8	231	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	232	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	233	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	234	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	235	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	236	#define RCC_OSCILLATORTYPE_MSI ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	237
Kojto	90:cb3d968589d8	238	#define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	90:cb3d968589d8	239	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	90:cb3d968589d8	240	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	90:cb3d968589d8	241	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	90:cb3d968589d8	242	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	90:cb3d968589d8	243	(((__OSCILLATOR__) & RCC_OSCILLATORTYPE_MSI) == RCC_OSCILLATORTYPE_MSI))
Kojto	90:cb3d968589d8	244	/**
Kojto	90:cb3d968589d8	245	* @}
Kojto	90:cb3d968589d8	246	*/
Kojto	90:cb3d968589d8	247
Kojto	90:cb3d968589d8	248	/** @defgroup RCC_HSE_Config RCC HSE Config
Kojto	90:cb3d968589d8	249	* @{
Kojto	90:cb3d968589d8	250	*/
Kojto	90:cb3d968589d8	251	#define RCC_HSE_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	252	#define RCC_HSE_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	253	#define RCC_HSE_BYPASS ((uint32_t)0x00000005)
Kojto	90:cb3d968589d8	254
Kojto	90:cb3d968589d8	255	#define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) \|\| ((__HSE__) == RCC_HSE_ON) \|\| \
Kojto	90:cb3d968589d8	256	((__HSE__) == RCC_HSE_BYPASS))
Kojto	90:cb3d968589d8	257	/**
Kojto	90:cb3d968589d8	258	* @}
Kojto	90:cb3d968589d8	259	*/
Kojto	90:cb3d968589d8	260
Kojto	90:cb3d968589d8	261	/** @defgroup RCC_LSE_Config RCC LSE Config
Kojto	90:cb3d968589d8	262	* @{
Kojto	90:cb3d968589d8	263	*/
Kojto	90:cb3d968589d8	264	#define RCC_LSE_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	265	#define RCC_LSE_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	266	#define RCC_LSE_BYPASS ((uint32_t)0x00000005)
Kojto	90:cb3d968589d8	267
Kojto	90:cb3d968589d8	268	#define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) \|\| ((__LSE__) == RCC_LSE_ON) \|\| \
Kojto	90:cb3d968589d8	269	((__LSE__) == RCC_LSE_BYPASS))
Kojto	90:cb3d968589d8	270	/**
Kojto	90:cb3d968589d8	271	* @}
Kojto	90:cb3d968589d8	272	*/
Kojto	90:cb3d968589d8	273
Kojto	90:cb3d968589d8	274	/** @defgroup RCC_HSI_Config RCC HSI Config
Kojto	90:cb3d968589d8	275	* @{
Kojto	90:cb3d968589d8	276	*/
Kojto	90:cb3d968589d8	277	#define RCC_HSI_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	278	#define RCC_HSI_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	279
Kojto	90:cb3d968589d8	280	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON))
Kojto	90:cb3d968589d8	281
Kojto	90:cb3d968589d8	282	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto	90:cb3d968589d8	283
Kojto	90:cb3d968589d8	284	#define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1F)
Kojto	90:cb3d968589d8	285	/**
Kojto	90:cb3d968589d8	286	* @}
Kojto	90:cb3d968589d8	287	*/
Kojto	90:cb3d968589d8	288
Kojto	90:cb3d968589d8	289	/** @defgroup RCC_MSI_Clock_Range RCC MSI Clock Range
Kojto	90:cb3d968589d8	290	* @{
Kojto	90:cb3d968589d8	291	*/
Kojto	90:cb3d968589d8	292
Kojto	90:cb3d968589d8	293	#define RCC_MSIRANGE_0 ((uint32_t)RCC_ICSCR_MSIRANGE_0) /!< MSI = 65.536 KHz /
Kojto	90:cb3d968589d8	294	#define RCC_MSIRANGE_1 ((uint32_t)RCC_ICSCR_MSIRANGE_1) /!< MSI = 131.072 KHz /
Kojto	90:cb3d968589d8	295	#define RCC_MSIRANGE_2 ((uint32_t)RCC_ICSCR_MSIRANGE_2) /!< MSI = 262.144 KHz /
Kojto	90:cb3d968589d8	296	#define RCC_MSIRANGE_3 ((uint32_t)RCC_ICSCR_MSIRANGE_3) /!< MSI = 524.288 KHz /
Kojto	90:cb3d968589d8	297	#define RCC_MSIRANGE_4 ((uint32_t)RCC_ICSCR_MSIRANGE_4) /!< MSI = 1.048 MHz /
Kojto	90:cb3d968589d8	298	#define RCC_MSIRANGE_5 ((uint32_t)RCC_ICSCR_MSIRANGE_5) /!< MSI = 2.097 MHz /
Kojto	90:cb3d968589d8	299	#define RCC_MSIRANGE_6 ((uint32_t)RCC_ICSCR_MSIRANGE_6) /!< MSI = 4.194 MHz /
Kojto	90:cb3d968589d8	300
Kojto	90:cb3d968589d8	301	#define IS_RCC_MSIRANGE(__RANGE__) (((__RANGE__) == RCC_MSIRANGE_0) \|\| \
Kojto	90:cb3d968589d8	302	((__RANGE__) == RCC_MSIRANGE_1) \|\| \
Kojto	90:cb3d968589d8	303	((__RANGE__) == RCC_MSIRANGE_2) \|\| \
Kojto	90:cb3d968589d8	304	((__RANGE__) == RCC_MSIRANGE_3) \|\| \
Kojto	90:cb3d968589d8	305	((__RANGE__) == RCC_MSIRANGE_4) \|\| \
Kojto	90:cb3d968589d8	306	((__RANGE__) == RCC_MSIRANGE_5) \|\| \
Kojto	90:cb3d968589d8	307	((__RANGE__) == RCC_MSIRANGE_6))
Kojto	90:cb3d968589d8	308	/**
Kojto	90:cb3d968589d8	309	* @}
Kojto	90:cb3d968589d8	310	*/
Kojto	90:cb3d968589d8	311
Kojto	90:cb3d968589d8	312	/** @defgroup RCC_LSI_Config RCC LSI Config
Kojto	90:cb3d968589d8	313	* @{
Kojto	90:cb3d968589d8	314	*/
Kojto	90:cb3d968589d8	315	#define RCC_LSI_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	316	#define RCC_LSI_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	317
Kojto	90:cb3d968589d8	318	#define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) \|\| ((__LSI__) == RCC_LSI_ON))
Kojto	90:cb3d968589d8	319	/**
Kojto	90:cb3d968589d8	320	* @}
Kojto	90:cb3d968589d8	321	*/
Kojto	90:cb3d968589d8	322
Kojto	90:cb3d968589d8	323
Kojto	90:cb3d968589d8	324	/** @defgroup RCC_MSI_Config RCC MSI Config
Kojto	90:cb3d968589d8	325	* @{
Kojto	90:cb3d968589d8	326	*/
Kojto	90:cb3d968589d8	327	#define RCC_MSI_OFF ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	328	#define RCC_MSI_ON ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	329
Kojto	90:cb3d968589d8	330	#define IS_RCC_MSI(__MSI__) (((__MSI__) == RCC_MSI_OFF) \|\| ((__MSI__) == RCC_MSI_ON))
Kojto	90:cb3d968589d8	331
Kojto	90:cb3d968589d8	332	#define RCC_MSICALIBRATION_DEFAULT ((uint32_t)0x00) /* Default MSI calibration trimming value */
Kojto	90:cb3d968589d8	333
Kojto	90:cb3d968589d8	334	/**
Kojto	90:cb3d968589d8	335	* @}
Kojto	90:cb3d968589d8	336	*/
Kojto	90:cb3d968589d8	337
Kojto	90:cb3d968589d8	338	/** @defgroup RCC_PLL_Config RCC PLL Config
Kojto	90:cb3d968589d8	339	* @{
Kojto	90:cb3d968589d8	340	*/
Kojto	90:cb3d968589d8	341	#define RCC_PLL_NONE ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	342	#define RCC_PLL_OFF ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	343	#define RCC_PLL_ON ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	344
Kojto	90:cb3d968589d8	345	#define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) \|\| ((__PLL__) == RCC_PLL_OFF) \|\| \
Kojto	90:cb3d968589d8	346	((__PLL__) == RCC_PLL_ON))
Kojto	90:cb3d968589d8	347	/**
Kojto	90:cb3d968589d8	348	* @}
Kojto	90:cb3d968589d8	349	*/
Kojto	90:cb3d968589d8	350
Kojto	90:cb3d968589d8	351	/** @defgroup RCC_PLL_Division_Factor RCC PLL Division Factor
Kojto	90:cb3d968589d8	352	* @{
Kojto	90:cb3d968589d8	353	*/
Kojto	90:cb3d968589d8	354
Kojto	90:cb3d968589d8	355	#define RCC_PLL_DIV2 RCC_CFGR_PLLDIV2
Kojto	90:cb3d968589d8	356	#define RCC_PLL_DIV3 RCC_CFGR_PLLDIV3
Kojto	90:cb3d968589d8	357	#define RCC_PLL_DIV4 RCC_CFGR_PLLDIV4
Kojto	90:cb3d968589d8	358
Kojto	90:cb3d968589d8	359	#define IS_RCC_PLL_DIV(__DIV__) (((__DIV__) == RCC_PLL_DIV2) \|\| \
Kojto	90:cb3d968589d8	360	((__DIV__) == RCC_PLL_DIV3) \|\| ((__DIV__) == RCC_PLL_DIV4))
Kojto	90:cb3d968589d8	361
Kojto	90:cb3d968589d8	362	/**
Kojto	90:cb3d968589d8	363	* @}
Kojto	90:cb3d968589d8	364	*/
Kojto	90:cb3d968589d8	365
Kojto	90:cb3d968589d8	366	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
Kojto	90:cb3d968589d8	367	* @{
Kojto	90:cb3d968589d8	368	*/
Kojto	90:cb3d968589d8	369
Kojto	90:cb3d968589d8	370	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
Kojto	90:cb3d968589d8	371	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
Kojto	90:cb3d968589d8	372	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
Kojto	90:cb3d968589d8	373	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
Kojto	90:cb3d968589d8	374	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
Kojto	90:cb3d968589d8	375	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
Kojto	90:cb3d968589d8	376	#define RCC_PLL_MUL24 RCC_CFGR_PLLMUL24
Kojto	90:cb3d968589d8	377	#define RCC_PLL_MUL32 RCC_CFGR_PLLMUL32
Kojto	90:cb3d968589d8	378	#define RCC_PLL_MUL48 RCC_CFGR_PLLMUL48
Kojto	90:cb3d968589d8	379
Kojto	90:cb3d968589d8	380	#define IS_RCC_PLL_MUL(__MUL__) (((__MUL__) == RCC_PLL_MUL3) \|\| ((__MUL__) == RCC_PLL_MUL4) \|\| \
Kojto	90:cb3d968589d8	381	((__MUL__) == RCC_PLL_MUL6) \|\| ((__MUL__) == RCC_PLL_MUL8) \|\| \
Kojto	90:cb3d968589d8	382	((__MUL__) == RCC_PLL_MUL12) \|\| ((__MUL__) == RCC_PLL_MUL16) \|\| \
Kojto	90:cb3d968589d8	383	((__MUL__) == RCC_PLL_MUL24) \|\| ((__MUL__) == RCC_PLL_MUL32) \|\| \
Kojto	90:cb3d968589d8	384	((__MUL__) == RCC_PLL_MUL48))
Kojto	90:cb3d968589d8	385	/**
Kojto	90:cb3d968589d8	386	* @}
Kojto	90:cb3d968589d8	387	*/
Kojto	90:cb3d968589d8	388
Kojto	90:cb3d968589d8	389	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto	90:cb3d968589d8	390	* @{
Kojto	90:cb3d968589d8	391	*/
Kojto	90:cb3d968589d8	392	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	393	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	394	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	395	#define RCC_CLOCKTYPE_PCLK2 ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	396
Kojto	90:cb3d968589d8	397	#define IS_RCC_CLOCKTYPE(__CLK__) ((1 <= (__CLK__)) && ((__CLK__) <= 15))
Kojto	90:cb3d968589d8	398	/**
Kojto	90:cb3d968589d8	399	* @}
Kojto	90:cb3d968589d8	400	*/
Kojto	90:cb3d968589d8	401
Kojto	90:cb3d968589d8	402	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto	90:cb3d968589d8	403	* @{
Kojto	90:cb3d968589d8	404	*/
Kojto	90:cb3d968589d8	405	#define RCC_SYSCLKSOURCE_MSI ((uint32_t)RCC_CFGR_SW_MSI)
Kojto	90:cb3d968589d8	406	#define RCC_SYSCLKSOURCE_HSI ((uint32_t)RCC_CFGR_SW_HSI)
Kojto	90:cb3d968589d8	407	#define RCC_SYSCLKSOURCE_HSE ((uint32_t)RCC_CFGR_SW_HSE)
Kojto	90:cb3d968589d8	408	#define RCC_SYSCLKSOURCE_PLLCLK ((uint32_t)RCC_CFGR_SW_PLL)
Kojto	90:cb3d968589d8	409
Kojto	90:cb3d968589d8	410	#define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_MSI) \|\| \
Kojto	90:cb3d968589d8	411	((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	412	((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) \|\| \
Kojto	90:cb3d968589d8	413	((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
Kojto	90:cb3d968589d8	414	/**
Kojto	90:cb3d968589d8	415	* @}
Kojto	90:cb3d968589d8	416	*/
Kojto	90:cb3d968589d8	417
Kojto	90:cb3d968589d8	418	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
Kojto	90:cb3d968589d8	419	* @{
Kojto	90:cb3d968589d8	420	*/
Kojto	90:cb3d968589d8	421	#define RCC_SYSCLK_DIV1 ((uint32_t)RCC_CFGR_HPRE_DIV1)
Kojto	90:cb3d968589d8	422	#define RCC_SYSCLK_DIV2 ((uint32_t)RCC_CFGR_HPRE_DIV2)
Kojto	90:cb3d968589d8	423	#define RCC_SYSCLK_DIV4 ((uint32_t)RCC_CFGR_HPRE_DIV4)
Kojto	90:cb3d968589d8	424	#define RCC_SYSCLK_DIV8 ((uint32_t)RCC_CFGR_HPRE_DIV8)
Kojto	90:cb3d968589d8	425	#define RCC_SYSCLK_DIV16 ((uint32_t)RCC_CFGR_HPRE_DIV16)
Kojto	90:cb3d968589d8	426	#define RCC_SYSCLK_DIV64 ((uint32_t)RCC_CFGR_HPRE_DIV64)
Kojto	90:cb3d968589d8	427	#define RCC_SYSCLK_DIV128 ((uint32_t)RCC_CFGR_HPRE_DIV128)
Kojto	90:cb3d968589d8	428	#define RCC_SYSCLK_DIV256 ((uint32_t)RCC_CFGR_HPRE_DIV256)
Kojto	90:cb3d968589d8	429	#define RCC_SYSCLK_DIV512 ((uint32_t)RCC_CFGR_HPRE_DIV512)
Kojto	90:cb3d968589d8	430
Kojto	90:cb3d968589d8	431	#define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) \|\| ((__HCLK__) == RCC_SYSCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	432	((__HCLK__) == RCC_SYSCLK_DIV4) \|\| ((__HCLK__) == RCC_SYSCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	433	((__HCLK__) == RCC_SYSCLK_DIV16) \|\| ((__HCLK__) == RCC_SYSCLK_DIV64) \|\| \
Kojto	90:cb3d968589d8	434	((__HCLK__) == RCC_SYSCLK_DIV128) \|\| ((__HCLK__) == RCC_SYSCLK_DIV256) \|\| \
Kojto	90:cb3d968589d8	435	((__HCLK__) == RCC_SYSCLK_DIV512))
Kojto	90:cb3d968589d8	436	/**
Kojto	90:cb3d968589d8	437	* @}
Kojto	90:cb3d968589d8	438	*/
Kojto	90:cb3d968589d8	439
Kojto	90:cb3d968589d8	440	/** @defgroup RCC_APB1_APB2_Clock_Source RCC APB1 APB2 Clock Source
Kojto	90:cb3d968589d8	441	* @{
Kojto	90:cb3d968589d8	442	*/
Kojto	90:cb3d968589d8	443	#define RCC_HCLK_DIV1 ((uint32_t)RCC_CFGR_PPRE1_DIV1)
Kojto	90:cb3d968589d8	444	#define RCC_HCLK_DIV2 ((uint32_t)RCC_CFGR_PPRE1_DIV2)
Kojto	90:cb3d968589d8	445	#define RCC_HCLK_DIV4 ((uint32_t)RCC_CFGR_PPRE1_DIV4)
Kojto	90:cb3d968589d8	446	#define RCC_HCLK_DIV8 ((uint32_t)RCC_CFGR_PPRE1_DIV8)
Kojto	90:cb3d968589d8	447	#define RCC_HCLK_DIV16 ((uint32_t)RCC_CFGR_PPRE1_DIV16)
Kojto	90:cb3d968589d8	448
Kojto	90:cb3d968589d8	449	#define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) \|\| ((__PCLK__) == RCC_HCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	450	((__PCLK__) == RCC_HCLK_DIV4) \|\| ((__PCLK__) == RCC_HCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	451	((__PCLK__) == RCC_HCLK_DIV16))
Kojto	90:cb3d968589d8	452	/**
Kojto	90:cb3d968589d8	453	* @}
Kojto	90:cb3d968589d8	454	*/
Kojto	90:cb3d968589d8	455
Kojto	90:cb3d968589d8	456	/** @defgroup RCC_RTC_LCD_Clock_Source RCC RTC LCD Clock Source
Kojto	90:cb3d968589d8	457	* @{
Kojto	90:cb3d968589d8	458	*/
Kojto	90:cb3d968589d8	459	#define RCC_RTCCLKSOURCE_LSE ((uint32_t)RCC_CSR_RTCSEL_LSE)
Kojto	90:cb3d968589d8	460	#define RCC_RTCCLKSOURCE_LSI ((uint32_t)RCC_CSR_RTCSEL_LSI)
Kojto	90:cb3d968589d8	461	#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)RCC_CSR_RTCSEL_HSE)
Kojto	90:cb3d968589d8	462	#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)(RCC_CR_RTCPRE_0 \| RCC_CSR_RTCSEL_HSE))
Kojto	90:cb3d968589d8	463	#define RCC_RTCCLKSOURCE_HSE_DIV8 ((uint32_t)(RCC_CR_RTCPRE_1 \| RCC_CSR_RTCSEL_HSE))
Kojto	90:cb3d968589d8	464	#define RCC_RTCCLKSOURCE_HSE_DIV16 ((uint32_t)(RCC_CR_RTCPRE \| RCC_CSR_RTCSEL_HSE))
Kojto	90:cb3d968589d8	465	/**
Kojto	90:cb3d968589d8	466	* @}
Kojto	90:cb3d968589d8	467	*/
Kojto	90:cb3d968589d8	468
Kojto	90:cb3d968589d8	469	/** @defgroup RCC_MCO_Index RCC MCO Index
Kojto	90:cb3d968589d8	470	* @{
Kojto	90:cb3d968589d8	471	*/
Kojto	90:cb3d968589d8	472	#define RCC_MCO1 ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	473	#define RCC_MCO RCC_MCO1
Kojto	90:cb3d968589d8	474
Kojto	90:cb3d968589d8	475	#define IS_RCC_MCO(__MCO__) (((__MCO__) == RCC_MCO))
Kojto	90:cb3d968589d8	476	/**
Kojto	90:cb3d968589d8	477	* @}
Kojto	90:cb3d968589d8	478	*/
Kojto	90:cb3d968589d8	479
Kojto	90:cb3d968589d8	480	/** @defgroup RCC_MCOx_Clock_Prescaler RCC MCO1 Clock Prescaler
Kojto	90:cb3d968589d8	481	* @{
Kojto	90:cb3d968589d8	482	*/
Kojto	90:cb3d968589d8	483	#define RCC_MCODIV_1 ((uint32_t)RCC_CFGR_MCO_DIV1)
Kojto	90:cb3d968589d8	484	#define RCC_MCODIV_2 ((uint32_t)RCC_CFGR_MCO_DIV2)
Kojto	90:cb3d968589d8	485	#define RCC_MCODIV_4 ((uint32_t)RCC_CFGR_MCO_DIV4)
Kojto	90:cb3d968589d8	486	#define RCC_MCODIV_8 ((uint32_t)RCC_CFGR_MCO_DIV8)
Kojto	90:cb3d968589d8	487	#define RCC_MCODIV_16 ((uint32_t)RCC_CFGR_MCO_DIV16)
Kojto	90:cb3d968589d8	488
Kojto	90:cb3d968589d8	489	#define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1) \|\| ((__DIV__) == RCC_MCODIV_2) \|\| \
Kojto	90:cb3d968589d8	490	((__DIV__) == RCC_MCODIV_4) \|\| ((__DIV__) == RCC_MCODIV_8) \|\| \
Kojto	90:cb3d968589d8	491	((__DIV__) == RCC_MCODIV_16))
Kojto	90:cb3d968589d8	492	/**
Kojto	90:cb3d968589d8	493	* @}
Kojto	90:cb3d968589d8	494	*/
Kojto	90:cb3d968589d8	495
Kojto	90:cb3d968589d8	496	/** @defgroup RCC_MCO1_Clock_Source RCC MCO1 Clock Source
Kojto	90:cb3d968589d8	497	* @{
Kojto	90:cb3d968589d8	498	*/
Kojto	90:cb3d968589d8	499	#define RCC_MCO1SOURCE_NOCLOCK ((uint32_t)RCC_CFGR_MCO_NOCLOCK)
Kojto	90:cb3d968589d8	500	#define RCC_MCO1SOURCE_SYSCLK ((uint32_t)RCC_CFGR_MCO_SYSCLK)
Kojto	90:cb3d968589d8	501	#define RCC_MCO1SOURCE_MSI ((uint32_t)RCC_CFGR_MCO_MSI)
Kojto	90:cb3d968589d8	502	#define RCC_MCO1SOURCE_HSI ((uint32_t)RCC_CFGR_MCO_HSI)
Kojto	90:cb3d968589d8	503	#define RCC_MCO1SOURCE_LSE ((uint32_t)RCC_CFGR_MCO_LSE)
Kojto	90:cb3d968589d8	504	#define RCC_MCO1SOURCE_LSI ((uint32_t)RCC_CFGR_MCO_LSI)
Kojto	90:cb3d968589d8	505	#define RCC_MCO1SOURCE_HSE ((uint32_t)RCC_CFGR_MCO_HSE)
Kojto	90:cb3d968589d8	506	#define RCC_MCO1SOURCE_PLLCLK ((uint32_t)RCC_CFGR_MCO_PLL)
Kojto	90:cb3d968589d8	507
Kojto	90:cb3d968589d8	508	#define IS_RCC_MCO1SOURCE(__SOURCE__) (((__SOURCE__) == RCC_MCO1SOURCE_SYSCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_MSI) \
Kojto	90:cb3d968589d8	509	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSE) \
Kojto	90:cb3d968589d8	510	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_LSI) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_HSE) \
Kojto	90:cb3d968589d8	511	\|\| ((__SOURCE__) == RCC_MCO1SOURCE_PLLCLK) \|\| ((__SOURCE__) == RCC_MCO1SOURCE_NOCLOCK))
Kojto	90:cb3d968589d8	512	/**
Kojto	90:cb3d968589d8	513	* @}
Kojto	90:cb3d968589d8	514	*/
Kojto	90:cb3d968589d8	515
Kojto	90:cb3d968589d8	516	/** @defgroup RCC_Interrupt RCC Interrupt
Kojto	90:cb3d968589d8	517	* @{
Kojto	90:cb3d968589d8	518	*/
Kojto	90:cb3d968589d8	519	#define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF)
Kojto	90:cb3d968589d8	520	#define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF)
Kojto	90:cb3d968589d8	521	#define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF)
Kojto	90:cb3d968589d8	522	#define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF)
Kojto	90:cb3d968589d8	523	#define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF)
Kojto	90:cb3d968589d8	524	#define RCC_IT_MSIRDY ((uint8_t)RCC_CIR_MSIRDYF)
Kojto	90:cb3d968589d8	525	#define RCC_IT_LSECSS ((uint8_t)RCC_CIR_LSECSS)
Kojto	90:cb3d968589d8	526	#define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF)
Kojto	90:cb3d968589d8	527	/**
Kojto	90:cb3d968589d8	528	* @}
Kojto	90:cb3d968589d8	529	*/
Kojto	90:cb3d968589d8	530
Kojto	90:cb3d968589d8	531	/** @defgroup RCC_Flag RCC Flag
Kojto	90:cb3d968589d8	532	* Elements values convention: 0XXYYYYYb
Kojto	90:cb3d968589d8	533	* - YYYYY : Flag position in the register
Kojto	90:cb3d968589d8	534	* - XX : Register index
Kojto	90:cb3d968589d8	535	* - 01: CR register
Kojto	90:cb3d968589d8	536	* - 11: CSR register
Kojto	90:cb3d968589d8	537	* @{
Kojto	90:cb3d968589d8	538	*/
Kojto	90:cb3d968589d8	539	#define CR_REG_INDEX ((uint8_t)1)
Kojto	90:cb3d968589d8	540	#define CSR_REG_INDEX ((uint8_t)3)
Kojto	90:cb3d968589d8	541
Kojto	90:cb3d968589d8	542	/* Flags in the CR register */
Kojto	90:cb3d968589d8	543	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSIRDY)))
Kojto	90:cb3d968589d8	544	#define RCC_FLAG_MSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_MSIRDY)))
Kojto	90:cb3d968589d8	545	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_HSERDY)))
Kojto	90:cb3d968589d8	546	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| POSITION_VAL(RCC_CR_PLLRDY)))
Kojto	90:cb3d968589d8	547
Kojto	90:cb3d968589d8	548	/* Flags in the CSR register */
Kojto	90:cb3d968589d8	549	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSIRDY)))
Kojto	90:cb3d968589d8	550	#define RCC_FLAG_LSERDY ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSERDY)))
Kojto	90:cb3d968589d8	551	#define RCC_FLAG_LSECSS ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LSECSSD)))
Kojto	90:cb3d968589d8	552	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_RMVF)))
Kojto	90:cb3d968589d8	553	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_OBLRSTF)))
Kojto	90:cb3d968589d8	554	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PINRSTF)))
Kojto	90:cb3d968589d8	555	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_PORRSTF)))
Kojto	90:cb3d968589d8	556	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_SFTRSTF)))
Kojto	90:cb3d968589d8	557	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_IWDGRSTF)))
Kojto	90:cb3d968589d8	558	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_WWDGRSTF)))
Kojto	90:cb3d968589d8	559	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| POSITION_VAL(RCC_CSR_LPWRRSTF)))
Kojto	90:cb3d968589d8	560
Kojto	90:cb3d968589d8	561	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	90:cb3d968589d8	562
Kojto	90:cb3d968589d8	563	/**
Kojto	90:cb3d968589d8	564	* @}
Kojto	90:cb3d968589d8	565	*/
Kojto	90:cb3d968589d8	566
Kojto	90:cb3d968589d8	567	/**
Kojto	90:cb3d968589d8	568	* @}
Kojto	90:cb3d968589d8	569	*/
Kojto	90:cb3d968589d8	570
Kojto	90:cb3d968589d8	571	/* Exported macro ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	572
Kojto	90:cb3d968589d8	573	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	90:cb3d968589d8	574	* @{
Kojto	90:cb3d968589d8	575	*/
Kojto	90:cb3d968589d8	576
Kojto	90:cb3d968589d8	577	/** @defgroup RCC_Peripheral_Clock_Enable_Disable RCC Peripheral Clock Enable Disable
Kojto	90:cb3d968589d8	578	* @brief Enable or disable the AHB1 peripheral clock.
Kojto	90:cb3d968589d8	579	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	580	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	581	* using it.
Kojto	90:cb3d968589d8	582	* @{
Kojto	90:cb3d968589d8	583	*/
Kojto	90:cb3d968589d8	584	#define __GPIOA_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOAEN))
Kojto	90:cb3d968589d8	585	#define __GPIOB_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOBEN))
Kojto	90:cb3d968589d8	586	#define __GPIOC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOCEN))
Kojto	90:cb3d968589d8	587	#define __GPIOD_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIODEN))
Kojto	90:cb3d968589d8	588	#define __GPIOH_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOHEN))
Kojto	90:cb3d968589d8	589
Kojto	90:cb3d968589d8	590	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
Kojto	90:cb3d968589d8	591	#define __FLITF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FLITFEN))
Kojto	90:cb3d968589d8	592	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
Kojto	90:cb3d968589d8	593
Kojto	90:cb3d968589d8	594	#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto	90:cb3d968589d8	595	#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto	90:cb3d968589d8	596	#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto	90:cb3d968589d8	597	#define __GPIOD_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIODEN))
Kojto	90:cb3d968589d8	598	#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
Kojto	90:cb3d968589d8	599
Kojto	90:cb3d968589d8	600	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto	90:cb3d968589d8	601	#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto	90:cb3d968589d8	602	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto	90:cb3d968589d8	603
Kojto	90:cb3d968589d8	604	/** @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	90:cb3d968589d8	605	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	606	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	607	* using it.
Kojto	90:cb3d968589d8	608	*/
Kojto	90:cb3d968589d8	609	#define __TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
Kojto	90:cb3d968589d8	610	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	611	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
Kojto	90:cb3d968589d8	612	#define __TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
Kojto	90:cb3d968589d8	613	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
Kojto	90:cb3d968589d8	614	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
Kojto	90:cb3d968589d8	615	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	616	#define __USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
Kojto	90:cb3d968589d8	617	#define __USART3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART3EN))
Kojto	90:cb3d968589d8	618	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
Kojto	90:cb3d968589d8	619	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	620	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
Kojto	90:cb3d968589d8	621	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
Kojto	90:cb3d968589d8	622	#define __DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
Kojto	90:cb3d968589d8	623	#define __COMP_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_COMPEN))
Kojto	90:cb3d968589d8	624
Kojto	90:cb3d968589d8	625	#define __TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
Kojto	90:cb3d968589d8	626	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	627	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
Kojto	90:cb3d968589d8	628	#define __TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM6EN))
Kojto	90:cb3d968589d8	629	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
Kojto	90:cb3d968589d8	630	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	90:cb3d968589d8	631	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
Kojto	90:cb3d968589d8	632	#define __USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
Kojto	90:cb3d968589d8	633	#define __USART3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART3EN))
Kojto	90:cb3d968589d8	634	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	90:cb3d968589d8	635	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
Kojto	90:cb3d968589d8	636	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
Kojto	90:cb3d968589d8	637	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	90:cb3d968589d8	638	#define __DAC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DACEN))
Kojto	90:cb3d968589d8	639	#define __COMP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_COMPEN))
Kojto	90:cb3d968589d8	640
Kojto	90:cb3d968589d8	641	/** @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	90:cb3d968589d8	642	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	643	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	644	* using it.
Kojto	90:cb3d968589d8	645	*/
Kojto	90:cb3d968589d8	646	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
Kojto	90:cb3d968589d8	647	#define __TIM9_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM9EN))
Kojto	90:cb3d968589d8	648	#define __TIM10_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM10EN))
Kojto	90:cb3d968589d8	649	#define __TIM11_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM11EN))
Kojto	90:cb3d968589d8	650	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
Kojto	90:cb3d968589d8	651	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	652	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
Kojto	90:cb3d968589d8	653
Kojto	90:cb3d968589d8	654	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	90:cb3d968589d8	655	#define __TIM9_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM9EN))
Kojto	90:cb3d968589d8	656	#define __TIM10_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM10EN))
Kojto	90:cb3d968589d8	657	#define __TIM11_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM11EN))
Kojto	90:cb3d968589d8	658	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	90:cb3d968589d8	659	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	660	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	90:cb3d968589d8	661
Kojto	90:cb3d968589d8	662	/**
Kojto	90:cb3d968589d8	663	* @}
Kojto	90:cb3d968589d8	664	*/
Kojto	90:cb3d968589d8	665
Kojto	90:cb3d968589d8	666	/** @defgroup RCC_Peripheral_Clock_Force_Release RCC Peripheral Clock Force Release
Kojto	90:cb3d968589d8	667	* @brief Force or release AHB peripheral reset.
Kojto	90:cb3d968589d8	668	* @{
Kojto	90:cb3d968589d8	669	*/
Kojto	90:cb3d968589d8	670	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	671	#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
Kojto	90:cb3d968589d8	672	#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
Kojto	90:cb3d968589d8	673	#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
Kojto	90:cb3d968589d8	674	#define __GPIOD_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIODRST))
Kojto	90:cb3d968589d8	675	#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
Kojto	90:cb3d968589d8	676
Kojto	90:cb3d968589d8	677	#define __CRC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRCRST))
Kojto	90:cb3d968589d8	678	#define __FLITF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FLITFRST))
Kojto	90:cb3d968589d8	679	#define __DMA1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_DMA1RST))
Kojto	90:cb3d968589d8	680
Kojto	90:cb3d968589d8	681	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto	90:cb3d968589d8	682	#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto	90:cb3d968589d8	683	#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto	90:cb3d968589d8	684	#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto	90:cb3d968589d8	685	#define __GPIOD_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIODRST))
Kojto	90:cb3d968589d8	686	#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
Kojto	90:cb3d968589d8	687
Kojto	90:cb3d968589d8	688	#define __CRC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_CRCRST))
Kojto	90:cb3d968589d8	689	#define __FLITF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FLITFRST))
Kojto	90:cb3d968589d8	690	#define __DMA1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_DMA1RST))
Kojto	90:cb3d968589d8	691
Kojto	90:cb3d968589d8	692	/** @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	693	*/
Kojto	90:cb3d968589d8	694	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	695	#define __TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	90:cb3d968589d8	696	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	697	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
Kojto	90:cb3d968589d8	698	#define __TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	90:cb3d968589d8	699	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	90:cb3d968589d8	700	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	90:cb3d968589d8	701	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	702	#define __USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	90:cb3d968589d8	703	#define __USART3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART3RST))
Kojto	90:cb3d968589d8	704	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	90:cb3d968589d8	705	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	706	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
Kojto	90:cb3d968589d8	707	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	90:cb3d968589d8	708	#define __DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
Kojto	90:cb3d968589d8	709	#define __COMP_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_COMPRST))
Kojto	90:cb3d968589d8	710
Kojto	90:cb3d968589d8	711	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	90:cb3d968589d8	712	#define __TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
Kojto	90:cb3d968589d8	713	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	714	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
Kojto	90:cb3d968589d8	715	#define __TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM6RST))
Kojto	90:cb3d968589d8	716	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
Kojto	90:cb3d968589d8	717	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	90:cb3d968589d8	718	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
Kojto	90:cb3d968589d8	719	#define __USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
Kojto	90:cb3d968589d8	720	#define __USART3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART3RST))
Kojto	90:cb3d968589d8	721	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	90:cb3d968589d8	722	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
Kojto	90:cb3d968589d8	723	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
Kojto	90:cb3d968589d8	724	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	90:cb3d968589d8	725	#define __DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DACRST))
Kojto	90:cb3d968589d8	726	#define __COMP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_COMPRST))
Kojto	90:cb3d968589d8	727
Kojto	90:cb3d968589d8	728	/** @brief Force or release APB2 peripheral reset.
Kojto	90:cb3d968589d8	729	*/
Kojto	90:cb3d968589d8	730	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	731	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	90:cb3d968589d8	732	#define __TIM9_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM9RST))
Kojto	90:cb3d968589d8	733	#define __TIM10_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM10RST))
Kojto	90:cb3d968589d8	734	#define __TIM11_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM11RST))
Kojto	90:cb3d968589d8	735	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
Kojto	90:cb3d968589d8	736	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	737	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	90:cb3d968589d8	738
Kojto	90:cb3d968589d8	739	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	90:cb3d968589d8	740	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	90:cb3d968589d8	741	#define __TIM9_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM9RST))
Kojto	90:cb3d968589d8	742	#define __TIM10_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM10RST))
Kojto	90:cb3d968589d8	743	#define __TIM11_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM11RST))
Kojto	90:cb3d968589d8	744	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto	90:cb3d968589d8	745	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	746	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	90:cb3d968589d8	747
Kojto	90:cb3d968589d8	748	/**
Kojto	90:cb3d968589d8	749	* @}
Kojto	90:cb3d968589d8	750	*/
Kojto	90:cb3d968589d8	751
Kojto	90:cb3d968589d8	752	/** @defgroup RCC_Peripheral_Clock_Sleep_Enable_Disable RCC Peripheral Clock Sleep Enable Disable
Kojto	90:cb3d968589d8	753	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	754	* power consumption.
Kojto	90:cb3d968589d8	755	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	756	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	757	* @{
Kojto	90:cb3d968589d8	758	*/
Kojto	90:cb3d968589d8	759	#define __GPIOA_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOALPEN))
Kojto	90:cb3d968589d8	760	#define __GPIOB_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOBLPEN))
Kojto	90:cb3d968589d8	761	#define __GPIOC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOCLPEN))
Kojto	90:cb3d968589d8	762	#define __GPIOD_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIODLPEN))
Kojto	90:cb3d968589d8	763	#define __GPIOH_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_GPIOHLPEN))
Kojto	90:cb3d968589d8	764
Kojto	90:cb3d968589d8	765	#define __CRC_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_CRCLPEN))
Kojto	90:cb3d968589d8	766	#define __FLITF_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_FLITFLPEN))
Kojto	90:cb3d968589d8	767	#define __DMA1_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBLPENR_DMA1LPEN))
Kojto	90:cb3d968589d8	768
Kojto	90:cb3d968589d8	769	#define __GPIOA_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOALPEN))
Kojto	90:cb3d968589d8	770	#define __GPIOB_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOBLPEN))
Kojto	90:cb3d968589d8	771	#define __GPIOC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOCLPEN))
Kojto	90:cb3d968589d8	772	#define __GPIOD_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIODLPEN))
Kojto	90:cb3d968589d8	773	#define __GPIOH_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_GPIOHLPEN))
Kojto	90:cb3d968589d8	774
Kojto	90:cb3d968589d8	775	#define __CRC_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_CRCLPEN))
Kojto	90:cb3d968589d8	776	#define __FLITF_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_FLITFLPEN))
Kojto	90:cb3d968589d8	777	#define __DMA1_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~(RCC_AHBLPENR_DMA1LPEN))
Kojto	90:cb3d968589d8	778
Kojto	90:cb3d968589d8	779	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	780	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	781	* power consumption.
Kojto	90:cb3d968589d8	782	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	783	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	784	*/
Kojto	90:cb3d968589d8	785	#define __TIM2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM2LPEN))
Kojto	90:cb3d968589d8	786	#define __TIM3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM3LPEN))
Kojto	90:cb3d968589d8	787	#define __TIM4_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM4LPEN))
Kojto	90:cb3d968589d8	788	#define __TIM6_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM6LPEN))
Kojto	90:cb3d968589d8	789	#define __TIM7_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_TIM7LPEN))
Kojto	90:cb3d968589d8	790	#define __WWDG_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_WWDGLPEN))
Kojto	90:cb3d968589d8	791	#define __SPI2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_SPI2LPEN))
Kojto	90:cb3d968589d8	792	#define __USART2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART2LPEN))
Kojto	90:cb3d968589d8	793	#define __USART3_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USART3LPEN))
Kojto	90:cb3d968589d8	794	#define __I2C1_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C1LPEN))
Kojto	90:cb3d968589d8	795	#define __I2C2_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_I2C2LPEN))
Kojto	90:cb3d968589d8	796	#define __USB_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_USBLPEN))
Kojto	90:cb3d968589d8	797	#define __PWR_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_PWRLPEN))
Kojto	90:cb3d968589d8	798	#define __DAC_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_DACLPEN))
Kojto	90:cb3d968589d8	799	#define __COMP_CLK_SLEEP_ENABLE() (RCC->APB1LPENR \|= (RCC_APB1LPENR_COMPLPEN))
Kojto	90:cb3d968589d8	800
Kojto	90:cb3d968589d8	801	#define __TIM2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM2LPEN))
Kojto	90:cb3d968589d8	802	#define __TIM3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM3LPEN))
Kojto	90:cb3d968589d8	803	#define __TIM4_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM4LPEN))
Kojto	90:cb3d968589d8	804	#define __TIM6_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM6LPEN))
Kojto	90:cb3d968589d8	805	#define __TIM7_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_TIM7LPEN))
Kojto	90:cb3d968589d8	806	#define __WWDG_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_WWDGLPEN))
Kojto	90:cb3d968589d8	807	#define __SPI2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_SPI2LPEN))
Kojto	90:cb3d968589d8	808	#define __USART2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART2LPEN))
Kojto	90:cb3d968589d8	809	#define __USART3_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USART3LPEN))
Kojto	90:cb3d968589d8	810	#define __I2C1_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C1LPEN))
Kojto	90:cb3d968589d8	811	#define __I2C2_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_I2C2LPEN))
Kojto	90:cb3d968589d8	812	#define __USB_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_USBLPEN))
Kojto	90:cb3d968589d8	813	#define __PWR_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_PWRLPEN))
Kojto	90:cb3d968589d8	814	#define __DAC_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_DACLPEN))
Kojto	90:cb3d968589d8	815	#define __COMP_CLK_SLEEP_DISABLE() (RCC->APB1LPENR &= ~(RCC_APB1LPENR_COMPLPEN))
Kojto	90:cb3d968589d8	816
Kojto	90:cb3d968589d8	817	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
Kojto	90:cb3d968589d8	818	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	90:cb3d968589d8	819	* power consumption.
Kojto	90:cb3d968589d8	820	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	90:cb3d968589d8	821	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	90:cb3d968589d8	822	*/
Kojto	90:cb3d968589d8	823	#define __SYSCFG_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SYSCFGLPEN))
Kojto	90:cb3d968589d8	824	#define __TIM9_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM9LPEN))
Kojto	90:cb3d968589d8	825	#define __TIM10_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM10LPEN))
Kojto	90:cb3d968589d8	826	#define __TIM11_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_TIM11LPEN))
Kojto	90:cb3d968589d8	827	#define __ADC1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_ADC1LPEN))
Kojto	90:cb3d968589d8	828	#define __SPI1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_SPI1LPEN))
Kojto	90:cb3d968589d8	829	#define __USART1_CLK_SLEEP_ENABLE() (RCC->APB2LPENR \|= (RCC_APB2LPENR_USART1LPEN))
Kojto	90:cb3d968589d8	830
Kojto	90:cb3d968589d8	831	#define __SYSCFG_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SYSCFGLPEN))
Kojto	90:cb3d968589d8	832	#define __TIM9_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM9LPEN))
Kojto	90:cb3d968589d8	833	#define __TIM10_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM10LPEN))
Kojto	90:cb3d968589d8	834	#define __TIM11_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_TIM11LPEN))
Kojto	90:cb3d968589d8	835	#define __ADC1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_ADC1LPEN))
Kojto	90:cb3d968589d8	836	#define __SPI1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_SPI1LPEN))
Kojto	90:cb3d968589d8	837	#define __USART1_CLK_SLEEP_DISABLE() (RCC->APB2LPENR &= ~(RCC_APB2LPENR_USART1LPEN))
Kojto	90:cb3d968589d8	838
Kojto	90:cb3d968589d8	839	/**
Kojto	90:cb3d968589d8	840	* @}
Kojto	90:cb3d968589d8	841	*/
Kojto	90:cb3d968589d8	842
Kojto	90:cb3d968589d8	843	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	90:cb3d968589d8	844	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	845	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	90:cb3d968589d8	846	* you have to select another source of the system clock then stop the HSI.
Kojto	90:cb3d968589d8	847	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	90:cb3d968589d8	848	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	90:cb3d968589d8	849	* system clock source.
Kojto	90:cb3d968589d8	850	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	90:cb3d968589d8	851	* clock cycles.
Kojto	90:cb3d968589d8	852	*/
Kojto	90:cb3d968589d8	853	#define __HAL_RCC_HSI_ENABLE() ((__IO uint32_t ) CR_HSION_BB = ENABLE)
Kojto	90:cb3d968589d8	854	#define __HAL_RCC_HSI_DISABLE() ((__IO uint32_t ) CR_HSION_BB = DISABLE)
Kojto	90:cb3d968589d8	855
Kojto	90:cb3d968589d8	856	/** @brief Macros to enable or disable the External High Speed oscillator (HSE).
Kojto	90:cb3d968589d8	857	* @param __HSE_STATE__: specifies the new state of the HSE.
Kojto	90:cb3d968589d8	858	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	859	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	90:cb3d968589d8	860	* 6 HSE oscillator clock cycles.
Kojto	90:cb3d968589d8	861	* @arg RCC_HSE_ON: turn ON the HSE oscillator
Kojto	90:cb3d968589d8	862	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
Kojto	90:cb3d968589d8	863	*/
Kojto	90:cb3d968589d8	864	#define __HAL_RCC_HSE_CONFIG(__HSE_STATE__) ((__IO uint8_t ) CR_BYTE2_ADDRESS = (__HSE_STATE__))
Kojto	90:cb3d968589d8	865
Kojto	90:cb3d968589d8	866	/** @brief Macros to enable or disable the Internal Multi Speed oscillator (MSI).
Kojto	90:cb3d968589d8	867	* @note The MSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	868	* It is used (enabled by hardware) as system clock source after startup
Kojto	90:cb3d968589d8	869	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto	90:cb3d968589d8	870	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	90:cb3d968589d8	871	* Security System CSS is enabled).
Kojto	90:cb3d968589d8	872	* @note MSI can not be stopped if it is used as system clock source. In this case,
Kojto	90:cb3d968589d8	873	* you have to select another source of the system clock then stop the MSI.
Kojto	90:cb3d968589d8	874	* @note After enabling the MSI, the application software should wait on MSIRDY
Kojto	90:cb3d968589d8	875	* flag to be set indicating that MSI clock is stable and can be used as
Kojto	90:cb3d968589d8	876	* system clock source.
Kojto	90:cb3d968589d8	877	* @note When the MSI is stopped, MSIRDY flag goes low after 6 MSI oscillator
Kojto	90:cb3d968589d8	878	* clock cycles.
Kojto	90:cb3d968589d8	879	*/
Kojto	90:cb3d968589d8	880	#define __HAL_RCC_MSI_ENABLE() ((__IO uint32_t ) CR_MSION_BB = ENABLE)
Kojto	90:cb3d968589d8	881	#define __HAL_RCC_MSI_DISABLE() ((__IO uint32_t ) CR_MSION_BB = DISABLE)
Kojto	90:cb3d968589d8	882
Kojto	90:cb3d968589d8	883	/** @brief macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	90:cb3d968589d8	884	* @note The calibration is used to compensate for the variations in voltage
Kojto	90:cb3d968589d8	885	* and temperature that influence the frequency of the internal HSI RC.
Kojto	90:cb3d968589d8	886	* @param _HSICALIBRATIONVALUE_: specifies the calibration trimming value.
Kojto	90:cb3d968589d8	887	* (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	90:cb3d968589d8	888	* This parameter must be a number between 0 and 0x1F.
Kojto	90:cb3d968589d8	889	*/
Kojto	90:cb3d968589d8	890	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
Kojto	90:cb3d968589d8	891	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_HSITRIM)))
Kojto	90:cb3d968589d8	892
Kojto	90:cb3d968589d8	893	/** @brief macro to adjust the Internal Multi Speed oscillator (MSI) calibration value.
Kojto	90:cb3d968589d8	894	* @note The calibration is used to compensate for the variations in voltage
Kojto	90:cb3d968589d8	895	* and temperature that influence the frequency of the internal MSI RC.
Kojto	90:cb3d968589d8	896	* @param _MSICALIBRATIONVALUE_: specifies the calibration trimming value.
Kojto	90:cb3d968589d8	897	* (default is RCC_MSICALIBRATION_DEFAULT).
Kojto	90:cb3d968589d8	898	* This parameter must be a number between 0 and 0x1F.
Kojto	90:cb3d968589d8	899	*/
Kojto	90:cb3d968589d8	900	#define __HAL_RCC_MSI_CALIBRATIONVALUE_ADJUST(_MSICALIBRATIONVALUE_) \
Kojto	90:cb3d968589d8	901	(MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSITRIM, (uint32_t)(_MSICALIBRATIONVALUE_) << POSITION_VAL(RCC_ICSCR_MSITRIM)))
Kojto	90:cb3d968589d8	902
Kojto	90:cb3d968589d8	903	/* @brief Macro to configures the Internal Multi Speed oscillator (MSI) clock range.
Kojto	90:cb3d968589d8	904	* @note After restart from Reset or wakeup from STANDBY, the MSI clock is
Kojto	90:cb3d968589d8	905	* around 2.097 MHz. The MSI clock does not change after wake-up from
Kojto	90:cb3d968589d8	906	* STOP mode.
Kojto	90:cb3d968589d8	907	* @note The MSI clock range can be modified on the fly.
Kojto	90:cb3d968589d8	908	* @param _MSIRANGEVALUE_: specifies the MSI Clock range.
Kojto	90:cb3d968589d8	909	* This parameter must be one of the following values:
Kojto	90:cb3d968589d8	910	* @arg RCC_MSIRANGE_0: MSI clock is around 65.536 KHz
Kojto	90:cb3d968589d8	911	* @arg RCC_MSIRANGE_1: MSI clock is around 131.072 KHz
Kojto	90:cb3d968589d8	912	* @arg RCC_MSIRANGE_2: MSI clock is around 262.144 KHz
Kojto	90:cb3d968589d8	913	* @arg RCC_MSIRANGE_3: MSI clock is around 524.288 KHz
Kojto	90:cb3d968589d8	914	* @arg RCC_MSIRANGE_4: MSI clock is around 1.048 MHz
Kojto	90:cb3d968589d8	915	* @arg RCC_MSIRANGE_5: MSI clock is around 2.097 MHz (default after Reset or wake-up from STANDBY)
Kojto	90:cb3d968589d8	916	* @arg RCC_MSIRANGE_6: MSI clock is around 4.194 MHz
Kojto	90:cb3d968589d8	917	*/
Kojto	90:cb3d968589d8	918	#define __HAL_RCC_MSI_RANGE_CONFIG(_MSIRANGEVALUE_) (MODIFY_REG(RCC->ICSCR, RCC_ICSCR_MSIRANGE, (uint32_t)(_MSIRANGEVALUE_)))
Kojto	90:cb3d968589d8	919
Kojto	90:cb3d968589d8	920
Kojto	90:cb3d968589d8	921	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	90:cb3d968589d8	922	* @note After enabling the LSI, the application software should wait on
Kojto	90:cb3d968589d8	923	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	90:cb3d968589d8	924	* be used to clock the IWDG and/or the RTC.
Kojto	90:cb3d968589d8	925	* @note LSI can not be disabled if the IWDG is running.
Kojto	90:cb3d968589d8	926	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	90:cb3d968589d8	927	* clock cycles.
Kojto	90:cb3d968589d8	928	*/
Kojto	90:cb3d968589d8	929	#define __HAL_RCC_LSI_ENABLE() ((__IO uint32_t ) CSR_LSION_BB = ENABLE)
Kojto	90:cb3d968589d8	930	#define __HAL_RCC_LSI_DISABLE() ((__IO uint32_t ) CSR_LSION_BB = DISABLE)
Kojto	90:cb3d968589d8	931
Kojto	90:cb3d968589d8	932	/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSE).
Kojto	90:cb3d968589d8	933	*/
Kojto	90:cb3d968589d8	934	#define __HAL_RCC_LSE_CONFIG(__LSE_STATE__) \
Kojto	90:cb3d968589d8	935	do{ \
Kojto	90:cb3d968589d8	936	if ((__LSE_STATE__) == RCC_LSE_OFF) \
Kojto	90:cb3d968589d8	937	{ \
Kojto	90:cb3d968589d8	938	(__IO uint32_t ) CSR_LSEON_BB = DISABLE; \
Kojto	90:cb3d968589d8	939	(__IO uint32_t ) CSR_LSEBYP_BB = DISABLE; \
Kojto	90:cb3d968589d8	940	} \
Kojto	90:cb3d968589d8	941	else if ((__LSE_STATE__) == RCC_LSE_ON) \
Kojto	90:cb3d968589d8	942	{ \
Kojto	90:cb3d968589d8	943	(__IO uint32_t ) CSR_LSEBYP_BB = DISABLE; \
Kojto	90:cb3d968589d8	944	(__IO uint32_t ) CSR_LSEON_BB = ENABLE; \
Kojto	90:cb3d968589d8	945	} \
Kojto	90:cb3d968589d8	946	else \
Kojto	90:cb3d968589d8	947	{ \
Kojto	90:cb3d968589d8	948	(__IO uint32_t ) CSR_LSEON_BB = DISABLE; \
Kojto	90:cb3d968589d8	949	(__IO uint32_t ) CSR_LSEBYP_BB = ENABLE; \
Kojto	90:cb3d968589d8	950	} \
Kojto	90:cb3d968589d8	951	}while(0)
Kojto	90:cb3d968589d8	952
Kojto	90:cb3d968589d8	953	/** @brief Macros to enable or disable the the RTC clock.
Kojto	90:cb3d968589d8	954	* @note These macros must be used only after the RTC clock source was selected.
Kojto	90:cb3d968589d8	955	*/
Kojto	90:cb3d968589d8	956	#define __HAL_RCC_RTC_ENABLE() ((__IO uint32_t ) CSR_RTCEN_BB = ENABLE)
Kojto	90:cb3d968589d8	957	#define __HAL_RCC_RTC_DISABLE() ((__IO uint32_t ) CSR_RTCEN_BB = DISABLE)
Kojto	90:cb3d968589d8	958
Kojto	90:cb3d968589d8	959	/** @brief Macros to force or release the Backup domain reset.
Kojto	90:cb3d968589d8	960	* @note This function resets the RTC peripheral (including the backup registers)
Kojto	90:cb3d968589d8	961	* and the RTC clock source selection in RCC_CSR register.
Kojto	90:cb3d968589d8	962	* @note The BKPSRAM is not affected by this reset.
Kojto	90:cb3d968589d8	963	*/
Kojto	90:cb3d968589d8	964	#define __HAL_RCC_BACKUPRESET_FORCE() ((__IO uint32_t ) CSR_RTCRST_BB = ENABLE)
Kojto	90:cb3d968589d8	965	#define __HAL_RCC_BACKUPRESET_RELEASE() ((__IO uint32_t ) CSR_RTCRST_BB = DISABLE)
Kojto	90:cb3d968589d8	966
Kojto	90:cb3d968589d8	967
Kojto	90:cb3d968589d8	968	/** @brief Macro to configures the RTC clock (RTCCLK).
Kojto	90:cb3d968589d8	969	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	90:cb3d968589d8	970	* access is denied to this domain after reset, you have to enable write
Kojto	90:cb3d968589d8	971	* access using the Power Backup Access macro before to configure
Kojto	90:cb3d968589d8	972	* the RTC clock source (to be done once after reset).
Kojto	90:cb3d968589d8	973	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	90:cb3d968589d8	974	* Backup domain is reset using __HAL_RCC_BACKUPRESET_FORCE() macro, or by
Kojto	90:cb3d968589d8	975	* a Power On Reset (POR).
Kojto	90:cb3d968589d8	976	* @note RTC prescaler cannot be modified if HSE is enabled (HSEON = 1).
Kojto	90:cb3d968589d8	977	*
Kojto	90:cb3d968589d8	978	* @param __RTC_CLKSOURCE__: specifies the RTC clock source.
Kojto	90:cb3d968589d8	979	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	980	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	90:cb3d968589d8	981	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	90:cb3d968589d8	982	* @arg RCC_RTCCLKSOURCE_HSE_DIV2: HSE divided by 2 selected as RTC clock
Kojto	90:cb3d968589d8	983	* @arg RCC_RTCCLKSOURCE_HSE_DIV4: HSE divided by 4 selected as RTC clock
Kojto	90:cb3d968589d8	984	* @arg RCC_RTCCLKSOURCE_HSE_DIV8: HSE divided by 8 selected as RTC clock
Kojto	90:cb3d968589d8	985	* @arg RCC_RTCCLKSOURCE_HSE_DIV16: HSE divided by 16 selected as RTC clock
Kojto	90:cb3d968589d8	986	* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
Kojto	90:cb3d968589d8	987	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	90:cb3d968589d8	988	* However, when the HSE clock is used as RTC clock source, the RTC
Kojto	90:cb3d968589d8	989	* cannot be used in STOP and STANDBY modes.
Kojto	90:cb3d968589d8	990	* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
Kojto	90:cb3d968589d8	991	* RTC clock source).
Kojto	90:cb3d968589d8	992	*/
Kojto	90:cb3d968589d8	993	#define __HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__) do { \
Kojto	90:cb3d968589d8	994	if(((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL_HSE) == RCC_CSR_RTCSEL_HSE) \
Kojto	90:cb3d968589d8	995	{ \
Kojto	90:cb3d968589d8	996	MODIFY_REG(RCC->CR, RCC_CR_RTCPRE, ((__RTC_CLKSOURCE__) & RCC_CR_RTCPRE)); \
Kojto	90:cb3d968589d8	997	} \
Kojto	90:cb3d968589d8	998	} while (0)
Kojto	90:cb3d968589d8	999
Kojto	90:cb3d968589d8	1000	#define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) do { \
Kojto	90:cb3d968589d8	1001	__HAL_RCC_RTC_CLKPRESCALER(__RTC_CLKSOURCE__); \
Kojto	90:cb3d968589d8	1002	RCC->CSR \|= ((__RTC_CLKSOURCE__) & RCC_CSR_RTCSEL); \
Kojto	90:cb3d968589d8	1003	} while (0)
Kojto	90:cb3d968589d8	1004
Kojto	90:cb3d968589d8	1005	/** @brief macros to get the RTC clock source.
Kojto	90:cb3d968589d8	1006	*/
Kojto	90:cb3d968589d8	1007	#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->CSR, RCC_CSR_RTCSEL))
Kojto	90:cb3d968589d8	1008
Kojto	90:cb3d968589d8	1009	/** @brief Macros to enable or disable the main PLL.
Kojto	90:cb3d968589d8	1010	* @note After enabling the main PLL, the application software should wait on
Kojto	90:cb3d968589d8	1011	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	90:cb3d968589d8	1012	* be used as system clock source.
Kojto	90:cb3d968589d8	1013	* @note The main PLL can not be disabled if it is used as system clock source
Kojto	90:cb3d968589d8	1014	* @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	1015	*/
Kojto	90:cb3d968589d8	1016	#define __HAL_RCC_PLL_ENABLE() ((__IO uint32_t ) CR_PLLON_BB = ENABLE)
Kojto	90:cb3d968589d8	1017	#define __HAL_RCC_PLL_DISABLE() ((__IO uint32_t ) CR_PLLON_BB = DISABLE)
Kojto	90:cb3d968589d8	1018
Kojto	90:cb3d968589d8	1019	/** @brief macros to configure the main PLL clock source, multiplication and division factors.
Kojto	90:cb3d968589d8	1020	* @note This function must be used only when the main PLL is disabled.
Kojto	90:cb3d968589d8	1021	*
Kojto	90:cb3d968589d8	1022	* @param __RCC_PLLSOURCE__: specifies the PLL entry clock source.
Kojto	90:cb3d968589d8	1023	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1024	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	90:cb3d968589d8	1025	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	90:cb3d968589d8	1026	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO output clock
Kojto	90:cb3d968589d8	1027	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1028	* @arg RCC_PLL_MUL3: PLLVCO = PLL clock entry x 3
Kojto	90:cb3d968589d8	1029	* @arg RCC_PLL_MUL4: PLLVCO = PLL clock entry x 4
Kojto	90:cb3d968589d8	1030	* @arg RCC_PLL_MUL6: PLLVCO = PLL clock entry x 6
Kojto	90:cb3d968589d8	1031	* @arg RCC_PLL_MUL8: PLLVCO = PLL clock entry x 8
Kojto	90:cb3d968589d8	1032	* @arg RCC_PLL_MUL12: PLLVCO = PLL clock entry x 12
Kojto	90:cb3d968589d8	1033	* @arg RCC_PLL_MUL16: PLLVCO = PLL clock entry x 16
Kojto	90:cb3d968589d8	1034	* @arg RCC_PLL_MUL24: PLLVCO = PLL clock entry x 24
Kojto	90:cb3d968589d8	1035	* @arg RCC_PLL_MUL32: PLLVCO = PLL clock entry x 32
Kojto	90:cb3d968589d8	1036	* @arg RCC_PLL_MUL48: PLLVCO = PLL clock entry x 48
Kojto	90:cb3d968589d8	1037	* @note The PLL VCO clock frequency must not exceed 96 MHz when the product is in
Kojto	90:cb3d968589d8	1038	* Range 1, 48 MHz when the product is in Range 2 and 24 MHz when the product is
Kojto	90:cb3d968589d8	1039	* in Range 3.
Kojto	90:cb3d968589d8	1040	*
Kojto	90:cb3d968589d8	1041	* @param __PLLDIV__: specifies the division factor for PLL VCO input clock
Kojto	90:cb3d968589d8	1042	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1043	* @arg RCC_PLL_DIV2: PLL clock output = PLLVCO / 2
Kojto	90:cb3d968589d8	1044	* @arg RCC_PLL_DIV3: PLL clock output = PLLVCO / 3
Kojto	90:cb3d968589d8	1045	* @arg RCC_PLL_DIV4: PLL clock output = PLLVCO / 4
Kojto	90:cb3d968589d8	1046	*
Kojto	90:cb3d968589d8	1047	*/
Kojto	90:cb3d968589d8	1048	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__, __PLLDIV__)\
Kojto	90:cb3d968589d8	1049	MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC\|RCC_CFGR_PLLMUL\|RCC_CFGR_PLLDIV),((__RCC_PLLSOURCE__) \| (__PLLMUL__) \| (__PLLDIV__)))
Kojto	90:cb3d968589d8	1050
Kojto	90:cb3d968589d8	1051	/** @brief Macro to get the clock source used as system clock.
Kojto	90:cb3d968589d8	1052	* @retval The clock source used as system clock. The returned value can be one
Kojto	90:cb3d968589d8	1053	* of the following:
Kojto	90:cb3d968589d8	1054	* @arg RCC_CFGR_SWS_MSI: MSI used as system clock
Kojto	90:cb3d968589d8	1055	* @arg RCC_CFGR_SWS_HSI: HSI used as system clock
Kojto	90:cb3d968589d8	1056	* @arg RCC_CFGR_SWS_HSE: HSE used as system clock
Kojto	90:cb3d968589d8	1057	* @arg RCC_CFGR_SWS_PLL: PLL used as system clock
Kojto	90:cb3d968589d8	1058	*/
Kojto	90:cb3d968589d8	1059	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
Kojto	90:cb3d968589d8	1060
Kojto	90:cb3d968589d8	1061	/** @brief macros to manage the specified RCC Flags and interrupts.
Kojto	90:cb3d968589d8	1062	*/
Kojto	90:cb3d968589d8	1063
Kojto	90:cb3d968589d8	1064	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
Kojto	90:cb3d968589d8	1065	* the selected interrupts.).
Kojto	90:cb3d968589d8	1066	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	90:cb3d968589d8	1067	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1068	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	90:cb3d968589d8	1069	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	90:cb3d968589d8	1070	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	90:cb3d968589d8	1071	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	90:cb3d968589d8	1072	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	90:cb3d968589d8	1073	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	90:cb3d968589d8	1074	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
Kojto	90:cb3d968589d8	1075	*/
Kojto	90:cb3d968589d8	1076	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
Kojto	90:cb3d968589d8	1077
Kojto	90:cb3d968589d8	1078	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
Kojto	90:cb3d968589d8	1079	* the selected interrupts).
Kojto	90:cb3d968589d8	1080	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	90:cb3d968589d8	1081	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1082	* @arg RCC_IT_LSIRDY: LSI ready interrupt
Kojto	90:cb3d968589d8	1083	* @arg RCC_IT_LSERDY: LSE ready interrupt
Kojto	90:cb3d968589d8	1084	* @arg RCC_IT_HSIRDY: HSI ready interrupt
Kojto	90:cb3d968589d8	1085	* @arg RCC_IT_HSERDY: HSE ready interrupt
Kojto	90:cb3d968589d8	1086	* @arg RCC_IT_PLLRDY: main PLL ready interrupt
Kojto	90:cb3d968589d8	1087	* @arg RCC_IT_MSIRDY: MSI ready interrupt
Kojto	90:cb3d968589d8	1088	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
Kojto	90:cb3d968589d8	1089	*/
Kojto	90:cb3d968589d8	1090	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	90:cb3d968589d8	1091
Kojto	90:cb3d968589d8	1092	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
Kojto	90:cb3d968589d8	1093	* bits to clear the selected interrupt pending bits.
Kojto	90:cb3d968589d8	1094	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
Kojto	90:cb3d968589d8	1095	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1096	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	90:cb3d968589d8	1097	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	90:cb3d968589d8	1098	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	90:cb3d968589d8	1099	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	90:cb3d968589d8	1100	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	90:cb3d968589d8	1101	* @arg RCC_IT_MSIRDY: MSI ready interrupt.
Kojto	90:cb3d968589d8	1102	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
Kojto	90:cb3d968589d8	1103	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	90:cb3d968589d8	1104	*/
Kojto	90:cb3d968589d8	1105	#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) ((__IO uint8_t ) CIR_BYTE2_ADDRESS = (__INTERRUPT__))
Kojto	90:cb3d968589d8	1106
Kojto	90:cb3d968589d8	1107	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	90:cb3d968589d8	1108	* @param __INTERRUPT__: specifies the RCC interrupt source to check.
Kojto	90:cb3d968589d8	1109	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1110	* @arg RCC_IT_LSIRDY: LSI ready interrupt.
Kojto	90:cb3d968589d8	1111	* @arg RCC_IT_LSERDY: LSE ready interrupt.
Kojto	90:cb3d968589d8	1112	* @arg RCC_IT_HSIRDY: HSI ready interrupt.
Kojto	90:cb3d968589d8	1113	* @arg RCC_IT_HSERDY: HSE ready interrupt.
Kojto	90:cb3d968589d8	1114	* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
Kojto	90:cb3d968589d8	1115	* @arg RCC_IT_MSIRDY: MSI ready interrupt.
Kojto	90:cb3d968589d8	1116	* @arg RCC_IT_LSECSS: LSE CSS interrupt (not available for STM32L100xB \|\| STM32L151xB \|\| STM32L152xB device)
Kojto	90:cb3d968589d8	1117	* @arg RCC_IT_CSS: Clock Security System interrupt
Kojto	90:cb3d968589d8	1118	* @retval The new state of __INTERRUPT__ (TRUE or FALSE).
Kojto	90:cb3d968589d8	1119	*/
Kojto	90:cb3d968589d8	1120	#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
Kojto	90:cb3d968589d8	1121
Kojto	90:cb3d968589d8	1122	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto	90:cb3d968589d8	1123	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Kojto	90:cb3d968589d8	1124	*/
Kojto	90:cb3d968589d8	1125	#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR \|= RCC_CSR_RMVF)
Kojto	90:cb3d968589d8	1126
Kojto	90:cb3d968589d8	1127	/** @brief Check RCC flag is set or not.
Kojto	90:cb3d968589d8	1128	* @param __FLAG__: specifies the flag to check.
Kojto	90:cb3d968589d8	1129	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1130	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
Kojto	90:cb3d968589d8	1131	* @arg RCC_FLAG_MSIRDY: MSI oscillator clock ready.
Kojto	90:cb3d968589d8	1132	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
Kojto	90:cb3d968589d8	1133	* @arg RCC_FLAG_PLLRDY: Main PLL clock ready.
Kojto	90:cb3d968589d8	1134	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready.
Kojto	90:cb3d968589d8	1135	* @arg RCC_FLAG_LSECSS: CSS on LSE failure Detection (*)
Kojto	90:cb3d968589d8	1136	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready.
Kojto	90:cb3d968589d8	1137	* @arg RCC_FLAG_BORRST: POR/PDR or BOR reset.
Kojto	90:cb3d968589d8	1138	* @arg RCC_FLAG_PINRST: Pin reset.
Kojto	90:cb3d968589d8	1139	* @arg RCC_FLAG_PORRST: POR/PDR reset.
Kojto	90:cb3d968589d8	1140	* @arg RCC_FLAG_SFTRST: Software reset.
Kojto	90:cb3d968589d8	1141	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset.
Kojto	90:cb3d968589d8	1142	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset.
Kojto	90:cb3d968589d8	1143	* @arg RCC_FLAG_LPWRRST: Low Power reset.
Kojto	90:cb3d968589d8	1144	* @note (*) This bit is available in high and medium+ density devices only.
Kojto	90:cb3d968589d8	1145	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	90:cb3d968589d8	1146	*/
Kojto	90:cb3d968589d8	1147	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR :RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
Kojto	90:cb3d968589d8	1148
Kojto	90:cb3d968589d8	1149
Kojto	90:cb3d968589d8	1150	/** @brief Get oscillator clock selected as PLL input clock
Kojto	90:cb3d968589d8	1151	* @retval The clock source used for PLL entry. The returned value can be one
Kojto	90:cb3d968589d8	1152	* of the following:
Kojto	90:cb3d968589d8	1153	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL input clock
Kojto	90:cb3d968589d8	1154	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL input clock
Kojto	90:cb3d968589d8	1155	*/
Kojto	90:cb3d968589d8	1156	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((RCC->CFGR & RCC_CFGR_PLLSRC))
Kojto	90:cb3d968589d8	1157
Kojto	90:cb3d968589d8	1158	/**
Kojto	90:cb3d968589d8	1159	* @}
Kojto	90:cb3d968589d8	1160	*/
Kojto	90:cb3d968589d8	1161
Kojto	90:cb3d968589d8	1162	/* Include RCC HAL Extension module */
Kojto	90:cb3d968589d8	1163	#include "stm32l1xx_hal_rcc_ex.h"
Kojto	90:cb3d968589d8	1164
Kojto	90:cb3d968589d8	1165	/* Exported functions --------------------------------------------------------*/
Kojto	90:cb3d968589d8	1166	/** @addtogroup RCC_Private_Functions
Kojto	90:cb3d968589d8	1167	* @{
Kojto	90:cb3d968589d8	1168	*/
Kojto	90:cb3d968589d8	1169
Kojto	90:cb3d968589d8	1170	/** @addtogroup RCC_Exported_Functions_Group1
Kojto	90:cb3d968589d8	1171	* @{
Kojto	90:cb3d968589d8	1172	*/
Kojto	90:cb3d968589d8	1173
Kojto	90:cb3d968589d8	1174	/* Initialization and de-initialization functions ******************************/
Kojto	90:cb3d968589d8	1175	void HAL_RCC_DeInit(void);
Kojto	90:cb3d968589d8	1176	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	90:cb3d968589d8	1177	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	90:cb3d968589d8	1178
Kojto	90:cb3d968589d8	1179	/**
Kojto	90:cb3d968589d8	1180	* @}
Kojto	90:cb3d968589d8	1181	*/
Kojto	90:cb3d968589d8	1182
Kojto	90:cb3d968589d8	1183	/** @addtogroup RCC_Exported_Functions_Group2
Kojto	90:cb3d968589d8	1184	* @{
Kojto	90:cb3d968589d8	1185	*/
Kojto	90:cb3d968589d8	1186
Kojto	90:cb3d968589d8	1187	/* Peripheral Control functions ************************************************/
Kojto	90:cb3d968589d8	1188	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	90:cb3d968589d8	1189	void HAL_RCC_EnableCSS(void);
Kojto	90:cb3d968589d8	1190	void HAL_RCC_DisableCSS(void);
Kojto	90:cb3d968589d8	1191	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	90:cb3d968589d8	1192	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	90:cb3d968589d8	1193	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	90:cb3d968589d8	1194	uint32_t HAL_RCC_GetPCLK2Freq(void);
Kojto	90:cb3d968589d8	1195	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	90:cb3d968589d8	1196	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	90:cb3d968589d8	1197
Kojto	90:cb3d968589d8	1198	/* CSS NMI IRQ handler */
Kojto	90:cb3d968589d8	1199	void HAL_RCC_NMI_IRQHandler(void);
Kojto	90:cb3d968589d8	1200
Kojto	90:cb3d968589d8	1201	/* User Callbacks in non blocking mode (IT mode) */
Kojto	90:cb3d968589d8	1202	void HAL_RCC_CCSCallback(void);
Kojto	90:cb3d968589d8	1203
Kojto	90:cb3d968589d8	1204	/**
Kojto	90:cb3d968589d8	1205	* @}
Kojto	90:cb3d968589d8	1206	*/
Kojto	90:cb3d968589d8	1207
Kojto	90:cb3d968589d8	1208	/**
Kojto	90:cb3d968589d8	1209	* @}
Kojto	90:cb3d968589d8	1210	*/
Kojto	90:cb3d968589d8	1211
Kojto	90:cb3d968589d8	1212	/**
Kojto	90:cb3d968589d8	1213	* @}
Kojto	90:cb3d968589d8	1214	*/
Kojto	90:cb3d968589d8	1215
Kojto	90:cb3d968589d8	1216	/**
Kojto	90:cb3d968589d8	1217	* @}
Kojto	90:cb3d968589d8	1218	*/
Kojto	90:cb3d968589d8	1219
Kojto	90:cb3d968589d8	1220	#ifdef __cplusplus
Kojto	90:cb3d968589d8	1221	}
Kojto	90:cb3d968589d8	1222	#endif
Kojto	90:cb3d968589d8	1223
Kojto	90:cb3d968589d8	1224	#endif /* __STM32L1xx_HAL_RCC_H */
Kojto	90:cb3d968589d8	1225
Kojto	90:cb3d968589d8	1226	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	90:cb3d968589d8	1227

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
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Followers:	1

TARGET_NUCLEO_L152RE/stm32l1xx_hal_rcc.h@97:4298809c7c9e, 2015-04-08 (annotated)

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