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TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc_ex.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:: filartrix
Date:: Wed Apr 08 14:12:53 2015 +0000
Revision:: 97:4298809c7c9e
Parent:: 96:487b796308b0

First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	84:0b3ab51c8877	1	/**
bogdanm	84:0b3ab51c8877	2	******************************************************************************
bogdanm	84:0b3ab51c8877	3	* @file stm32l0xx_hal_rcc_ex.h
bogdanm	84:0b3ab51c8877	4	* @author MCD Application Team
Kojto	96:487b796308b0	5	* @version V1.2.0
Kojto	96:487b796308b0	6	* @date 06-February-2015
bogdanm	84:0b3ab51c8877	7	* @brief Header file of RCC HAL Extension module.
bogdanm	84:0b3ab51c8877	8	******************************************************************************
bogdanm	84:0b3ab51c8877	9	* @attention
bogdanm	84:0b3ab51c8877	10	*
Kojto	96:487b796308b0	11	* <h2><center>© COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm	84:0b3ab51c8877	12	*
bogdanm	84:0b3ab51c8877	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	84:0b3ab51c8877	14	* are permitted provided that the following conditions are met:
bogdanm	84:0b3ab51c8877	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	84:0b3ab51c8877	16	* this list of conditions and the following disclaimer.
bogdanm	84:0b3ab51c8877	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	84:0b3ab51c8877	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	84:0b3ab51c8877	19	* and/or other materials provided with the distribution.
bogdanm	84:0b3ab51c8877	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	84:0b3ab51c8877	21	* may be used to endorse or promote products derived from this software
bogdanm	84:0b3ab51c8877	22	* without specific prior written permission.
bogdanm	84:0b3ab51c8877	23	*
bogdanm	84:0b3ab51c8877	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	84:0b3ab51c8877	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	84:0b3ab51c8877	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	84:0b3ab51c8877	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	84:0b3ab51c8877	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	84:0b3ab51c8877	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	84:0b3ab51c8877	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	84:0b3ab51c8877	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	84:0b3ab51c8877	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	84:0b3ab51c8877	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	84:0b3ab51c8877	34	*
bogdanm	84:0b3ab51c8877	35	******************************************************************************
bogdanm	84:0b3ab51c8877	36	*/
bogdanm	84:0b3ab51c8877	37
bogdanm	84:0b3ab51c8877	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	84:0b3ab51c8877	39	#ifndef __STM32L0xx_HAL_RCC_EX_H
bogdanm	84:0b3ab51c8877	40	#define __STM32L0xx_HAL_RCC_EX_H
bogdanm	84:0b3ab51c8877	41
bogdanm	84:0b3ab51c8877	42	#ifdef __cplusplus
bogdanm	84:0b3ab51c8877	43	extern "C" {
bogdanm	84:0b3ab51c8877	44	#endif
bogdanm	84:0b3ab51c8877	45
bogdanm	84:0b3ab51c8877	46	/* Includes ------------------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	47	#include "stm32l0xx_hal_def.h"
bogdanm	84:0b3ab51c8877	48
bogdanm	84:0b3ab51c8877	49	/** @addtogroup STM32L0xx_HAL_Driver
bogdanm	84:0b3ab51c8877	50	* @{
bogdanm	84:0b3ab51c8877	51	*/
bogdanm	84:0b3ab51c8877	52
Kojto	96:487b796308b0	53	/** @defgroup RCCEx
bogdanm	84:0b3ab51c8877	54	* @{
bogdanm	84:0b3ab51c8877	55	*/
bogdanm	84:0b3ab51c8877	56
bogdanm	84:0b3ab51c8877	57	/* Exported types ------------------------------------------------------------*/
bogdanm	84:0b3ab51c8877	58	/**
bogdanm	84:0b3ab51c8877	59	* @brief RCC extended clocks structure definition
bogdanm	84:0b3ab51c8877	60	*/
Kojto	96:487b796308b0	61	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	84:0b3ab51c8877	62	typedef struct
bogdanm	84:0b3ab51c8877	63	{
bogdanm	84:0b3ab51c8877	64	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	84:0b3ab51c8877	65	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	84:0b3ab51c8877	66	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	84:0b3ab51c8877	67	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	84:0b3ab51c8877	68
bogdanm	84:0b3ab51c8877	69	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	84:0b3ab51c8877	70	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	84:0b3ab51c8877	71
bogdanm	84:0b3ab51c8877	72	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
bogdanm	92:4fc01daae5a5	73	This parameter can be a value of @ref RCCEx_LPUART_Clock_Source */
bogdanm	84:0b3ab51c8877	74
bogdanm	84:0b3ab51c8877	75	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	84:0b3ab51c8877	76	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
Kojto	96:487b796308b0	77	#if defined (STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	78	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	96:487b796308b0	79	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	96:487b796308b0	80	#endif
bogdanm	84:0b3ab51c8877	81
bogdanm	84:0b3ab51c8877	82	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	96:487b796308b0	83	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	96:487b796308b0	84	#if defined (STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	85	uint32_t LCDClockSelection; /*!< specifies the LCD clock source.
Kojto	96:487b796308b0	86	This parameter can be a value of @ref RCC_RTC_Clock_Source */
Kojto	96:487b796308b0	87	#endif
bogdanm	84:0b3ab51c8877	88
bogdanm	84:0b3ab51c8877	89	uint32_t UsbClockSelection; /*!< Specifies USB and RNG Clock Selection
bogdanm	92:4fc01daae5a5	90	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	84:0b3ab51c8877	91
bogdanm	84:0b3ab51c8877	92	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
bogdanm	84:0b3ab51c8877	93	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	84:0b3ab51c8877	94
bogdanm	84:0b3ab51c8877	95	}RCC_PeriphCLKInitTypeDef;
Kojto	96:487b796308b0	96
bogdanm	84:0b3ab51c8877	97
Kojto	96:487b796308b0	98	#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto	96:487b796308b0	99
bogdanm	84:0b3ab51c8877	100	typedef struct
bogdanm	84:0b3ab51c8877	101	{
bogdanm	84:0b3ab51c8877	102	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	84:0b3ab51c8877	103	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
Kojto	96:487b796308b0	104	#if !defined (STM32L031xx) && !defined (STM32L041xx)
bogdanm	84:0b3ab51c8877	105	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	84:0b3ab51c8877	106	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
Kojto	96:487b796308b0	107	#endif
bogdanm	84:0b3ab51c8877	108	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	84:0b3ab51c8877	109	This parameter can be a value of @ref RCCEx_USART2_Clock_Source */
bogdanm	84:0b3ab51c8877	110
bogdanm	84:0b3ab51c8877	111	uint32_t Lpuart1ClockSelection; /*!< LPUART1 clock source
bogdanm	84:0b3ab51c8877	112	This parameter can be a value of @ref RCCEx_LPUART1_Clock_Source */
bogdanm	84:0b3ab51c8877	113
bogdanm	84:0b3ab51c8877	114	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	84:0b3ab51c8877	115	This parameter can be a value of @ref RCCEx_I2C1_Clock_Source */
bogdanm	84:0b3ab51c8877	116
Kojto	96:487b796308b0	117	#if defined (STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	118	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
Kojto	96:487b796308b0	119	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
Kojto	96:487b796308b0	120	#endif
Kojto	96:487b796308b0	121
bogdanm	84:0b3ab51c8877	122	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
Kojto	96:487b796308b0	123	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	84:0b3ab51c8877	124
bogdanm	84:0b3ab51c8877	125	uint32_t LptimClockSelection; /*!< LPTIM1 clock source
bogdanm	84:0b3ab51c8877	126	This parameter can be a value of @ref RCCEx_LPTIM1_Clock_Source */
bogdanm	84:0b3ab51c8877	127
bogdanm	84:0b3ab51c8877	128	}RCC_PeriphCLKInitTypeDef;
Kojto	96:487b796308b0	129
Kojto	96:487b796308b0	130	#endif /* STM32L0x1xx */
Kojto	96:487b796308b0	131
bogdanm	84:0b3ab51c8877	132
Kojto	96:487b796308b0	133	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	96:487b796308b0	134	/** @defgroup RCCEx_Exported_Constants
Kojto	96:487b796308b0	135	* @{
Kojto	96:487b796308b0	136	*/
bogdanm	84:0b3ab51c8877	137	/**
Kojto	96:487b796308b0	138	* @brief RCC CRS Status definition
bogdanm	84:0b3ab51c8877	139	*/
bogdanm	84:0b3ab51c8877	140
Kojto	96:487b796308b0	141	#define RCC_CRS_NONE ((uint32_t) 0x00000000)
Kojto	96:487b796308b0	142	#define RCC_CRS_TIMEOUT ((uint32_t) 0x00000001)
Kojto	96:487b796308b0	143	#define RCC_CRS_SYNCOK ((uint32_t) 0x00000002)
Kojto	96:487b796308b0	144	#define RCC_CRS_SYNCWARM ((uint32_t) 0x00000004)
Kojto	96:487b796308b0	145	#define RCC_CRS_SYNCERR ((uint32_t) 0x00000008)
Kojto	96:487b796308b0	146	#define RCC_CRS_SYNCMISS ((uint32_t) 0x00000010)
Kojto	96:487b796308b0	147	#define RCC_CRS_TRIMOV ((uint32_t) 0x00000020)
Kojto	96:487b796308b0	148
Kojto	96:487b796308b0	149	/**
Kojto	96:487b796308b0	150	* @}
Kojto	96:487b796308b0	151	*/
bogdanm	84:0b3ab51c8877	152	/**
bogdanm	84:0b3ab51c8877	153	* @brief RCC_CRS Init structure definition
bogdanm	84:0b3ab51c8877	154	*/
bogdanm	84:0b3ab51c8877	155	typedef struct
bogdanm	84:0b3ab51c8877	156	{
bogdanm	84:0b3ab51c8877	157	uint32_t Prescaler; /*!< Specifies the division factor of the SYNC signal.
bogdanm	84:0b3ab51c8877	158	This parameter can be a value of @ref RCCEx_CRS_SynchroDivider */
bogdanm	84:0b3ab51c8877	159
bogdanm	84:0b3ab51c8877	160	uint32_t Source; /*!< Specifies the SYNC signal source.
bogdanm	84:0b3ab51c8877	161	This parameter can be a value of @ref RCCEx_CRS_SynchroSource */
bogdanm	84:0b3ab51c8877	162
bogdanm	84:0b3ab51c8877	163	uint32_t Polarity; /*!< Specifies the input polarity for the SYNC signal source.
bogdanm	84:0b3ab51c8877	164	This parameter can be a value of @ref RCCEx_CRS_SynchroPolarity */
bogdanm	84:0b3ab51c8877	165
bogdanm	84:0b3ab51c8877	166	uint32_t ReloadValue; /*!< Specifies the value to be loaded in the frequency error counter with each SYNC event.
bogdanm	84:0b3ab51c8877	167	It can be calculated in using macro __HAL_RCC_CRS_CALCULATE_RELOADVALUE(_FTARGET_, _FSYNC_)
bogdanm	84:0b3ab51c8877	168	This parameter must be a number between 0 and 0xFFFF or a value of @ref RCCEx_CRS_ReloadValueDefault .*/
bogdanm	84:0b3ab51c8877	169
bogdanm	84:0b3ab51c8877	170	uint32_t ErrorLimitValue; /*!< Specifies the value to be used to evaluate the captured frequency error value.
bogdanm	84:0b3ab51c8877	171	This parameter must be a number between 0 and 0xFF or a value of @ref RCCEx_CRS_ErrorLimitDefault */
bogdanm	84:0b3ab51c8877	172
bogdanm	84:0b3ab51c8877	173	uint32_t HSI48CalibrationValue; /*!< Specifies a user-programmable trimming value to the HSI48 oscillator.
bogdanm	84:0b3ab51c8877	174	This parameter must be a number between 0 and 0x3F or a value of @ref RCCEx_CRS_HSI48CalibrationDefault */
bogdanm	84:0b3ab51c8877	175
bogdanm	84:0b3ab51c8877	176	}RCC_CRSInitTypeDef;
bogdanm	84:0b3ab51c8877	177
bogdanm	84:0b3ab51c8877	178	/**
bogdanm	84:0b3ab51c8877	179	* @brief RCC_CRS Synchronization structure definition
bogdanm	84:0b3ab51c8877	180	*/
bogdanm	84:0b3ab51c8877	181	typedef struct
bogdanm	84:0b3ab51c8877	182	{
bogdanm	84:0b3ab51c8877	183	uint32_t ReloadValue; /*!< Specifies the value loaded in the Counter reload value.
bogdanm	84:0b3ab51c8877	184	This parameter must be a number between 0 and 0xFFFF*/
bogdanm	84:0b3ab51c8877	185
bogdanm	84:0b3ab51c8877	186	uint32_t HSI48CalibrationValue; /*!< Specifies value loaded in HSI48 oscillator smooth trimming.
bogdanm	84:0b3ab51c8877	187	This parameter must be a number between 0 and 0x3F */
bogdanm	84:0b3ab51c8877	188
bogdanm	84:0b3ab51c8877	189	uint32_t FreqErrorCapture; /*!< Specifies the value loaded in the .FECAP, the frequency error counter
bogdanm	84:0b3ab51c8877	190	value latched in the time of the last SYNC event.
bogdanm	84:0b3ab51c8877	191	This parameter must be a number between 0 and 0xFFFF */
bogdanm	84:0b3ab51c8877	192
bogdanm	84:0b3ab51c8877	193	uint32_t FreqErrorDirection; /*!< Specifies the value loaded in the .FEDIR, the counting direction of the
bogdanm	84:0b3ab51c8877	194	frequency error counter latched in the time of the last SYNC event.
bogdanm	84:0b3ab51c8877	195	It shows whether the actual frequency is below or above the target.
bogdanm	84:0b3ab51c8877	196	This parameter must be a value of @ref RCCEx_CRS_FreqErrorDirection*/
bogdanm	84:0b3ab51c8877	197
bogdanm	84:0b3ab51c8877	198	}RCC_CRSSynchroInfoTypeDef;
Kojto	96:487b796308b0	199	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	84:0b3ab51c8877	200
bogdanm	84:0b3ab51c8877	201	/* Exported constants --------------------------------------------------------*/
Kojto	96:487b796308b0	202	/** @addtogroup RCCEx_Exported_Constants
bogdanm	84:0b3ab51c8877	203	* @{
bogdanm	84:0b3ab51c8877	204	*/
bogdanm	84:0b3ab51c8877	205
bogdanm	84:0b3ab51c8877	206	/** @defgroup RCCEx_Periph_Clock_Selection
bogdanm	84:0b3ab51c8877	207	* @{
bogdanm	84:0b3ab51c8877	208	*/
Kojto	96:487b796308b0	209	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	96:487b796308b0	210
bogdanm	84:0b3ab51c8877	211	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	84:0b3ab51c8877	212	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	84:0b3ab51c8877	213	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
bogdanm	84:0b3ab51c8877	214	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
bogdanm	84:0b3ab51c8877	215	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
bogdanm	84:0b3ab51c8877	216	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	84:0b3ab51c8877	217	#define RCC_PERIPHCLK_USB ((uint32_t)0x00000040)
bogdanm	84:0b3ab51c8877	218	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
Kojto	96:487b796308b0	219	#if defined (STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	220	#define RCC_PERIPHCLK_LCD ((uint32_t)0x00000800)
Kojto	96:487b796308b0	221	#endif
Kojto	96:487b796308b0	222	#if defined (STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	223	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
Kojto	96:487b796308b0	224	#endif
bogdanm	84:0b3ab51c8877	225
Kojto	96:487b796308b0	226	#if defined (STM32L052xx) \|\| defined(STM32L062xx)
Kojto	96:487b796308b0	227	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Kojto	96:487b796308b0	228	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Kojto	96:487b796308b0	229	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1))
Kojto	96:487b796308b0	230	#elif defined (STM32L053xx) \|\| defined(STM32L063xx)
Kojto	96:487b796308b0	231	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Kojto	96:487b796308b0	232	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Kojto	96:487b796308b0	233	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_LCD))
Kojto	96:487b796308b0	234	#elif defined (STM32L072xx) \|\| defined(STM32L082xx)
Kojto	96:487b796308b0	235	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Kojto	96:487b796308b0	236	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Kojto	96:487b796308b0	237	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 ))
Kojto	96:487b796308b0	238	#elif defined (STM32L073xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	239	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Kojto	96:487b796308b0	240	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Kojto	96:487b796308b0	241	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3 \| \
Kojto	96:487b796308b0	242	RCC_PERIPHCLK_LCD))
Kojto	96:487b796308b0	243	#endif
bogdanm	84:0b3ab51c8877	244
Kojto	96:487b796308b0	245	#else /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto	96:487b796308b0	246
Kojto	96:487b796308b0	247	#if !defined(STM32L031xx) && !defined(STM32L041xx)
bogdanm	84:0b3ab51c8877	248	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
Kojto	96:487b796308b0	249	#endif
bogdanm	84:0b3ab51c8877	250	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	84:0b3ab51c8877	251	#define RCC_PERIPHCLK_LPUART1 ((uint32_t)0x00000004)
bogdanm	84:0b3ab51c8877	252	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000008)
Kojto	96:487b796308b0	253	#if !defined(STM32L031xx) && !defined(STM32L041xx)
bogdanm	84:0b3ab51c8877	254	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000010)
Kojto	96:487b796308b0	255	#endif
bogdanm	84:0b3ab51c8877	256	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00000020)
bogdanm	84:0b3ab51c8877	257	#define RCC_PERIPHCLK_LPTIM1 ((uint32_t)0x00000080)
Kojto	96:487b796308b0	258	#if defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	259	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00000100)
Kojto	96:487b796308b0	260	#endif
bogdanm	84:0b3ab51c8877	261
Kojto	96:487b796308b0	262	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
Kojto	96:487b796308b0	263	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= ( RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Kojto	96:487b796308b0	264	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_RTC ))
Kojto	96:487b796308b0	265	#elif defined(STM32L051xx) \|\| defined(STM32L061xx)
Kojto	96:487b796308b0	266	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Kojto	96:487b796308b0	267	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Kojto	96:487b796308b0	268	RCC_PERIPHCLK_LPTIM1))
Kojto	96:487b796308b0	269	#elif defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	270	#define IS_RCC_PERIPHCLK(__CLK__) ((__CLK__) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_LPUART1 \| \
Kojto	96:487b796308b0	271	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| RCC_PERIPHCLK_RTC \| \
Kojto	96:487b796308b0	272	RCC_PERIPHCLK_LPTIM1 \| RCC_PERIPHCLK_I2C3))
Kojto	96:487b796308b0	273	#endif
Kojto	96:487b796308b0	274
Kojto	96:487b796308b0	275	#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
bogdanm	84:0b3ab51c8877	276	/**
bogdanm	84:0b3ab51c8877	277	* @}
bogdanm	84:0b3ab51c8877	278	*/
Kojto	96:487b796308b0	279
bogdanm	84:0b3ab51c8877	280	/** @defgroup RCCEx_USART1_Clock_Source
bogdanm	84:0b3ab51c8877	281	* @{
bogdanm	84:0b3ab51c8877	282	*/
bogdanm	84:0b3ab51c8877	283	#define RCC_USART1CLKSOURCE_PCLK2 ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	284	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CCIPR_USART1SEL_0
bogdanm	84:0b3ab51c8877	285	#define RCC_USART1CLKSOURCE_HSI RCC_CCIPR_USART1SEL_1
bogdanm	84:0b3ab51c8877	286	#define RCC_USART1CLKSOURCE_LSE (RCC_CCIPR_USART1SEL_0 \| RCC_CCIPR_USART1SEL_1)
Kojto	96:487b796308b0	287	#define IS_RCC_USART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
Kojto	96:487b796308b0	288	((__SOURCE__) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	96:487b796308b0	289	((__SOURCE__) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	96:487b796308b0	290	((__SOURCE__) == RCC_USART1CLKSOURCE_HSI))
bogdanm	84:0b3ab51c8877	291	/**
bogdanm	84:0b3ab51c8877	292	* @}
bogdanm	84:0b3ab51c8877	293	*/
bogdanm	84:0b3ab51c8877	294
bogdanm	84:0b3ab51c8877	295	/** @defgroup RCCEx_USART2_Clock_Source
bogdanm	84:0b3ab51c8877	296	* @{
bogdanm	84:0b3ab51c8877	297	*/
bogdanm	84:0b3ab51c8877	298	#define RCC_USART2CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	299	#define RCC_USART2CLKSOURCE_SYSCLK RCC_CCIPR_USART2SEL_0
bogdanm	84:0b3ab51c8877	300	#define RCC_USART2CLKSOURCE_HSI RCC_CCIPR_USART2SEL_1
bogdanm	84:0b3ab51c8877	301	#define RCC_USART2CLKSOURCE_LSE (RCC_CCIPR_USART2SEL_0 \| RCC_CCIPR_USART2SEL_1)
Kojto	96:487b796308b0	302	#define IS_RCC_USART2CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USART2CLKSOURCE_PCLK1) \|\| \
Kojto	96:487b796308b0	303	((__SOURCE__) == RCC_USART2CLKSOURCE_SYSCLK) \|\| \
Kojto	96:487b796308b0	304	((__SOURCE__) == RCC_USART2CLKSOURCE_LSE) \|\| \
Kojto	96:487b796308b0	305	((__SOURCE__) == RCC_USART2CLKSOURCE_HSI))
bogdanm	84:0b3ab51c8877	306	/**
bogdanm	84:0b3ab51c8877	307	* @}
bogdanm	84:0b3ab51c8877	308	*/
bogdanm	84:0b3ab51c8877	309
bogdanm	84:0b3ab51c8877	310	/** @defgroup RCCEx_LPUART_Clock_Source
bogdanm	84:0b3ab51c8877	311	* @{
bogdanm	84:0b3ab51c8877	312	*/
bogdanm	84:0b3ab51c8877	313	#define RCC_LPUART1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	314	#define RCC_LPUART1CLKSOURCE_SYSCLK RCC_CCIPR_LPUART1SEL_0
bogdanm	84:0b3ab51c8877	315	#define RCC_LPUART1CLKSOURCE_HSI RCC_CCIPR_LPUART1SEL_1
bogdanm	84:0b3ab51c8877	316	#define RCC_LPUART1CLKSOURCE_LSE (RCC_CCIPR_LPUART1SEL_0 \| RCC_CCIPR_LPUART1SEL_1)
Kojto	96:487b796308b0	317	#define IS_RCC_LPUART1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_LPUART1CLKSOURCE_PCLK1) \|\| \
Kojto	96:487b796308b0	318	((__SOURCE__) == RCC_LPUART1CLKSOURCE_SYSCLK) \|\| \
Kojto	96:487b796308b0	319	((__SOURCE__) == RCC_LPUART1CLKSOURCE_LSE) \|\| \
Kojto	96:487b796308b0	320	((__SOURCE__) == RCC_LPUART1CLKSOURCE_HSI))
bogdanm	84:0b3ab51c8877	321	/**
bogdanm	84:0b3ab51c8877	322	* @}
bogdanm	84:0b3ab51c8877	323	*/
bogdanm	84:0b3ab51c8877	324
bogdanm	84:0b3ab51c8877	325	/** @defgroup RCCEx_I2C1_Clock_Source
bogdanm	84:0b3ab51c8877	326	* @{
bogdanm	84:0b3ab51c8877	327	*/
bogdanm	84:0b3ab51c8877	328	#define RCC_I2C1CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	329	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CCIPR_I2C1SEL_0
bogdanm	84:0b3ab51c8877	330	#define RCC_I2C1CLKSOURCE_HSI RCC_CCIPR_I2C1SEL_1
Kojto	96:487b796308b0	331	#define IS_RCC_I2C1CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C1CLKSOURCE_PCLK1) \|\| \
Kojto	96:487b796308b0	332	((__SOURCE__) == RCC_I2C1CLKSOURCE_SYSCLK)\|\| \
Kojto	96:487b796308b0	333	((__SOURCE__) == RCC_I2C1CLKSOURCE_HSI))
Kojto	96:487b796308b0	334	/**
Kojto	96:487b796308b0	335	* @}
Kojto	96:487b796308b0	336	*/
Kojto	96:487b796308b0	337
Kojto	96:487b796308b0	338	#if defined(STM32L071xx) \|\| defined(STM32L072xx) \|\| defined(STM32L073xx)\|\| defined(STM32L081xx) \|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	339
Kojto	96:487b796308b0	340	/** @defgroup RCCEx_I2C3_Clock_Source
Kojto	96:487b796308b0	341	* @{
Kojto	96:487b796308b0	342	*/
Kojto	96:487b796308b0	343	#define RCC_I2C3CLKSOURCE_PCLK1 ((uint32_t)0x00000000)
Kojto	96:487b796308b0	344	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CCIPR_I2C3SEL_0
Kojto	96:487b796308b0	345	#define RCC_I2C3CLKSOURCE_HSI RCC_CCIPR_I2C3SEL_1
Kojto	96:487b796308b0	346	#define IS_RCC_I2C3CLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_I2C3CLKSOURCE_PCLK1) \|\| \
Kojto	96:487b796308b0	347	((__SOURCE__) == RCC_I2C3CLKSOURCE_SYSCLK)\|\| \
Kojto	96:487b796308b0	348	((__SOURCE__) == RCC_I2C3CLKSOURCE_HSI))
Kojto	96:487b796308b0	349	#endif /* defined(STM32L071xx) \|\| defined(STM32L072xx) \|\| defined(STM32L073xx) \|\| defined(STM32L081xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx) */
Kojto	96:487b796308b0	350
bogdanm	84:0b3ab51c8877	351	/**
bogdanm	84:0b3ab51c8877	352	* @}
bogdanm	84:0b3ab51c8877	353	*/
bogdanm	84:0b3ab51c8877	354
bogdanm	84:0b3ab51c8877	355	/** @defgroup RCCEx_TIM_PRescaler_Selection
bogdanm	84:0b3ab51c8877	356	* @{
bogdanm	84:0b3ab51c8877	357	*/
bogdanm	84:0b3ab51c8877	358	#define RCC_TIMPRES_DESACTIVATED ((uint8_t)0x00)
bogdanm	84:0b3ab51c8877	359	#define RCC_TIMPRES_ACTIVATED ((uint8_t)0x01)
bogdanm	84:0b3ab51c8877	360	/**
bogdanm	84:0b3ab51c8877	361	* @}
bogdanm	84:0b3ab51c8877	362	*/
bogdanm	84:0b3ab51c8877	363
Kojto	96:487b796308b0	364	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	84:0b3ab51c8877	365	/** @defgroup RCCEx_USB_Clock_Source
bogdanm	84:0b3ab51c8877	366	* @{
bogdanm	84:0b3ab51c8877	367	*/
bogdanm	84:0b3ab51c8877	368	#define RCC_USBCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	84:0b3ab51c8877	369	#define RCC_USBCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	370
Kojto	96:487b796308b0	371	#define IS_RCC_USBCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_USBCLKSOURCE_HSI48) \|\| \
Kojto	96:487b796308b0	372	((__SOURCE__) == RCC_USBCLKSOURCE_PLLCLK))
bogdanm	84:0b3ab51c8877	373	/**
bogdanm	84:0b3ab51c8877	374	* @}
bogdanm	84:0b3ab51c8877	375	*/
bogdanm	84:0b3ab51c8877	376
bogdanm	84:0b3ab51c8877	377	/** @defgroup RCCEx_RNG_Clock_Source
bogdanm	84:0b3ab51c8877	378	* @{
bogdanm	84:0b3ab51c8877	379	*/
bogdanm	84:0b3ab51c8877	380	#define RCC_RNGCLKSOURCE_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	84:0b3ab51c8877	381	#define RCC_RNGCLKSOURCE_PLLCLK ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	382
Kojto	96:487b796308b0	383	#define IS_RCC_RNGCLKSOURCE(_SOURCE_) (((_SOURCE_) == RCC_RNGCLKSOURCE_HSI48) \|\| \
Kojto	96:487b796308b0	384	((_SOURCE_) == RCC_RNGCLKSOURCE_PLLCLK))
bogdanm	84:0b3ab51c8877	385	/**
bogdanm	84:0b3ab51c8877	386	* @}
bogdanm	84:0b3ab51c8877	387	*/
bogdanm	84:0b3ab51c8877	388
bogdanm	84:0b3ab51c8877	389	/** @defgroup RCCEx_HSI48M_Clock_Source
bogdanm	84:0b3ab51c8877	390	* @{
bogdanm	84:0b3ab51c8877	391	*/
Kojto	96:487b796308b0	392	#define RCC_FLAG_HSI48 SYSCFG_CFGR3_REF_HSI48_RDYF
bogdanm	84:0b3ab51c8877	393
bogdanm	84:0b3ab51c8877	394	#define RCC_HSI48M_PLL ((uint32_t)0x00000000)
Kojto	96:487b796308b0	395	#define RCC_HSI48M_HSI48 RCC_CCIPR_HSI48SEL
bogdanm	84:0b3ab51c8877	396
Kojto	96:487b796308b0	397	#define IS_RCC_HSI48MCLKSOURCE(__HSI48MCLK__) (((__HSI48MCLK__) == RCC_HSI48M_PLL) \|\| ((__HSI48MCLK__) == RCC_HSI48M_HSI48))
bogdanm	84:0b3ab51c8877	398
bogdanm	84:0b3ab51c8877	399	/**
bogdanm	84:0b3ab51c8877	400	* @}
bogdanm	84:0b3ab51c8877	401	*/
Kojto	96:487b796308b0	402	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto	96:487b796308b0	403
Kojto	96:487b796308b0	404	/** @defgroup RCC_HSI_Config
Kojto	96:487b796308b0	405	* @{
Kojto	96:487b796308b0	406	*/
Kojto	96:487b796308b0	407	#define RCC_HSI_OFF ((uint8_t)0x00)
Kojto	96:487b796308b0	408	#define RCC_HSI_ON RCC_CR_HSION
Kojto	96:487b796308b0	409	#define RCC_HSI_DIV4 (RCC_CR_HSIDIVEN \| RCC_CR_HSION)
Kojto	96:487b796308b0	410	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	411	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	412	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	413	#define RCC_HSI_OUTEN RCC_CR_HSIOUTEN
Kojto	96:487b796308b0	414
Kojto	96:487b796308b0	415	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
Kojto	96:487b796308b0	416	((__HSI__) == RCC_HSI_DIV4) \|\| ((__HSI__) == RCC_HSI_OUTEN ))
Kojto	96:487b796308b0	417	#else
Kojto	96:487b796308b0	418	#define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) \|\| ((__HSI__) == RCC_HSI_ON) \|\| \
Kojto	96:487b796308b0	419	((__HSI__) == RCC_HSI_DIV4))
Kojto	96:487b796308b0	420	#endif
Kojto	96:487b796308b0	421
Kojto	96:487b796308b0	422	/**
Kojto	96:487b796308b0	423	* @}
Kojto	96:487b796308b0	424	*/
bogdanm	84:0b3ab51c8877	425
bogdanm	84:0b3ab51c8877	426	/** @defgroup RCCEx_LPTIM1_Clock_Source
bogdanm	84:0b3ab51c8877	427	* @{
bogdanm	84:0b3ab51c8877	428	*/
bogdanm	84:0b3ab51c8877	429	#define RCC_LPTIM1CLKSOURCE_PCLK ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	430	#define RCC_LPTIM1CLKSOURCE_LSI RCC_CCIPR_LPTIM1SEL_0
bogdanm	84:0b3ab51c8877	431	#define RCC_LPTIM1CLKSOURCE_HSI RCC_CCIPR_LPTIM1SEL_1
bogdanm	84:0b3ab51c8877	432	#define RCC_LPTIM1CLKSOURCE_LSE RCC_CCIPR_LPTIM1SEL
bogdanm	84:0b3ab51c8877	433
Kojto	96:487b796308b0	434	#define IS_RCC_LPTIMCLK(__LPTIMCLK_) (((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_PCLK) \|\| \
Kojto	96:487b796308b0	435	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSI) \|\| \
Kojto	96:487b796308b0	436	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_HSI) \|\| \
Kojto	96:487b796308b0	437	((__LPTIMCLK_) == RCC_LPTIM1CLKSOURCE_LSE))
bogdanm	84:0b3ab51c8877	438	/**
bogdanm	84:0b3ab51c8877	439	* @}
bogdanm	84:0b3ab51c8877	440	*/
bogdanm	84:0b3ab51c8877	441
bogdanm	92:4fc01daae5a5	442	/** @defgroup RCCEx_StopWakeUp_Clock
bogdanm	84:0b3ab51c8877	443	* @{
bogdanm	84:0b3ab51c8877	444	*/
bogdanm	84:0b3ab51c8877	445
Kojto	96:487b796308b0	446	#define RCC_STOP_WAKEUPCLOCK_MSI ((uint32_t)0x00)
Kojto	96:487b796308b0	447	#define RCC_STOP_WAKEUPCLOCK_HSI RCC_CFGR_STOPWUCK
bogdanm	84:0b3ab51c8877	448
Kojto	96:487b796308b0	449	#define IS_RCC_STOPWAKEUP_CLOCK(__SOURCE__) (((__SOURCE__) == RCC_StopWakeUpClock_MSI) \|\| \
Kojto	96:487b796308b0	450	((__SOURCE__) == RCC_StopWakeUpClock_HSI))
bogdanm	84:0b3ab51c8877	451	/**
bogdanm	84:0b3ab51c8877	452	* @}
bogdanm	84:0b3ab51c8877	453	*/
bogdanm	84:0b3ab51c8877	454
bogdanm	92:4fc01daae5a5	455	/** @defgroup RCCEx_LSEDrive_Configuration
bogdanm	84:0b3ab51c8877	456	* @{
bogdanm	84:0b3ab51c8877	457	*/
bogdanm	84:0b3ab51c8877	458
bogdanm	84:0b3ab51c8877	459	#define RCC_LSEDRIVE_LOW ((uint32_t)0x00000000)
bogdanm	84:0b3ab51c8877	460	#define RCC_LSEDRIVE_MEDIUMLOW RCC_CSR_LSEDRV_0
bogdanm	84:0b3ab51c8877	461	#define RCC_LSEDRIVE_MEDIUMHIGH RCC_CSR_LSEDRV_1
bogdanm	84:0b3ab51c8877	462	#define RCC_LSEDRIVE_HIGH RCC_CSR_LSEDRV
Kojto	96:487b796308b0	463	#define IS_RCC_LSE_DRIVE(__DRIVE__) (((__DRIVE__) == RCC_LSEDRIVE_LOW) \|\| ((__SOURCE__) == RCC_LSEDRIVE_MEDIUMLOW) \|\| \
Kojto	96:487b796308b0	464	((__DRIVE__) == RCC_LSEDRIVE_MEDIUMHIGH) \|\| ((__SOURCE__) == RCC_LSEDRIVE_HIGH))
bogdanm	84:0b3ab51c8877	465	/**
bogdanm	84:0b3ab51c8877	466	* @}
bogdanm	84:0b3ab51c8877	467	*/
bogdanm	84:0b3ab51c8877	468
Kojto	96:487b796308b0	469	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	84:0b3ab51c8877	470	/** @defgroup RCCEx_CRS_SynchroSource
bogdanm	84:0b3ab51c8877	471	* @{
bogdanm	84:0b3ab51c8877	472	*/
bogdanm	84:0b3ab51c8877	473	#define RCC_CRS_SYNC_SOURCE_GPIO ((uint32_t)0x00) /!< Synchro Signal source GPIO /
bogdanm	84:0b3ab51c8877	474	#define RCC_CRS_SYNC_SOURCE_LSE CRS_CFGR_SYNCSRC_0 /!< Synchro Signal source LSE /
bogdanm	84:0b3ab51c8877	475	#define RCC_CRS_SYNC_SOURCE_USB CRS_CFGR_SYNCSRC_1 /!< Synchro Signal source USB SOF (default)/
bogdanm	84:0b3ab51c8877	476
Kojto	96:487b796308b0	477	#define IS_RCC_CRS_SYNC_SOURCE(__SOURCE__) (((__SOURCE__) == RCC_CRS_SYNC_SOURCE_GPIO) \|\| \
Kojto	96:487b796308b0	478	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_LSE) \|\|\
Kojto	96:487b796308b0	479	((__SOURCE__) == RCC_CRS_SYNC_SOURCE_USB))
bogdanm	84:0b3ab51c8877	480	/**
bogdanm	84:0b3ab51c8877	481	* @}
bogdanm	84:0b3ab51c8877	482	*/
bogdanm	84:0b3ab51c8877	483
bogdanm	84:0b3ab51c8877	484	/** @defgroup RCCEx_CRS_SynchroDivider
bogdanm	84:0b3ab51c8877	485	* @{
bogdanm	84:0b3ab51c8877	486	*/
bogdanm	84:0b3ab51c8877	487	#define RCC_CRS_SYNC_DIV1 ((uint32_t)0x00) /!< Synchro Signal not divided (default) /
bogdanm	84:0b3ab51c8877	488	#define RCC_CRS_SYNC_DIV2 CRS_CFGR_SYNCDIV_0 /!< Synchro Signal divided by 2 /
bogdanm	84:0b3ab51c8877	489	#define RCC_CRS_SYNC_DIV4 CRS_CFGR_SYNCDIV_1 /!< Synchro Signal divided by 4 /
bogdanm	84:0b3ab51c8877	490	#define RCC_CRS_SYNC_DIV8 (CRS_CFGR_SYNCDIV_1 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 8 /
bogdanm	84:0b3ab51c8877	491	#define RCC_CRS_SYNC_DIV16 CRS_CFGR_SYNCDIV_2 /!< Synchro Signal divided by 16 /
bogdanm	84:0b3ab51c8877	492	#define RCC_CRS_SYNC_DIV32 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_0) /!< Synchro Signal divided by 32 /
bogdanm	84:0b3ab51c8877	493	#define RCC_CRS_SYNC_DIV64 (CRS_CFGR_SYNCDIV_2 \| CRS_CFGR_SYNCDIV_1) /!< Synchro Signal divided by 64 /
bogdanm	84:0b3ab51c8877	494	#define RCC_CRS_SYNC_DIV128 CRS_CFGR_SYNCDIV /!< Synchro Signal divided by 128 /
bogdanm	84:0b3ab51c8877	495
Kojto	96:487b796308b0	496	#define IS_RCC_CRS_SYNC_DIV(__DIV__) (((__DIV__) == RCC_CRS_SYNC_DIV1) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV2) \|\|\
Kojto	96:487b796308b0	497	((__DIV__) == RCC_CRS_SYNC_DIV4) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV8) \|\| \
Kojto	96:487b796308b0	498	((__DIV__) == RCC_CRS_SYNC_DIV16) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV32) \|\| \
Kojto	96:487b796308b0	499	((__DIV__) == RCC_CRS_SYNC_DIV64) \|\| ((__DIV__) == RCC_CRS_SYNC_DIV128))
bogdanm	84:0b3ab51c8877	500	/**
bogdanm	84:0b3ab51c8877	501	* @}
bogdanm	84:0b3ab51c8877	502	*/
bogdanm	84:0b3ab51c8877	503
bogdanm	84:0b3ab51c8877	504	/** @defgroup RCCEx_CRS_SynchroPolarity
bogdanm	84:0b3ab51c8877	505	* @{
bogdanm	84:0b3ab51c8877	506	*/
bogdanm	84:0b3ab51c8877	507	#define RCC_CRS_SYNC_POLARITY_RISING ((uint32_t)0x00) /!< Synchro Active on rising edge (default) /
bogdanm	84:0b3ab51c8877	508	#define RCC_CRS_SYNC_POLARITY_FALLING CRS_CFGR_SYNCPOL /!< Synchro Active on falling edge /
bogdanm	84:0b3ab51c8877	509
Kojto	96:487b796308b0	510	#define IS_RCC_CRS_SYNC_POLARITY(__POLARITY__) (((__POLARITY__) == RCC_CRS_SYNC_POLARITY_RISING) \|\| \
Kojto	96:487b796308b0	511	((__POLARITY__) == RCC_CRS_SYNC_POLARITY_FALLING))
bogdanm	84:0b3ab51c8877	512	/**
bogdanm	84:0b3ab51c8877	513	* @}
bogdanm	84:0b3ab51c8877	514	*/
bogdanm	84:0b3ab51c8877	515
bogdanm	84:0b3ab51c8877	516	/** @defgroup RCCEx_CRS_ReloadValueDefault
bogdanm	84:0b3ab51c8877	517	* @{
bogdanm	84:0b3ab51c8877	518	*/
bogdanm	84:0b3ab51c8877	519	#define RCC_CRS_RELOADVALUE_DEFAULT ((uint32_t)0xBB7F) /*!< The reset value of the RELOAD field corresponds
bogdanm	84:0b3ab51c8877	520	to a target frequency of 48 MHz and a synchronization signal frequency of 1 kHz (SOF signal from USB). */
bogdanm	84:0b3ab51c8877	521
Kojto	96:487b796308b0	522	#define IS_RCC_CRS_RELOADVALUE(__VALUE__) (((__VALUE__) <= 0xFFFF))
bogdanm	84:0b3ab51c8877	523	/**
bogdanm	84:0b3ab51c8877	524	* @}
bogdanm	84:0b3ab51c8877	525	*/
bogdanm	84:0b3ab51c8877	526
bogdanm	84:0b3ab51c8877	527	/** @defgroup RCCEx_CRS_ErrorLimitDefault
bogdanm	84:0b3ab51c8877	528	* @{
bogdanm	84:0b3ab51c8877	529	*/
bogdanm	84:0b3ab51c8877	530	#define RCC_CRS_ERRORLIMIT_DEFAULT ((uint32_t)0x22) /!< Default Frequency error limit /
bogdanm	84:0b3ab51c8877	531
Kojto	96:487b796308b0	532	#define IS_RCC_CRS_ERRORLIMIT(__VALUE__) (((__VALUE__) <= 0xFF))
bogdanm	84:0b3ab51c8877	533	/**
bogdanm	84:0b3ab51c8877	534	* @}
bogdanm	84:0b3ab51c8877	535	*/
bogdanm	84:0b3ab51c8877	536
bogdanm	84:0b3ab51c8877	537	/** @defgroup RCCEx_CRS_HSI48CalibrationDefault
bogdanm	84:0b3ab51c8877	538	* @{
bogdanm	84:0b3ab51c8877	539	*/
bogdanm	84:0b3ab51c8877	540	#define RCC_CRS_HSI48CALIBRATION_DEFAULT ((uint32_t)0x20) /*!< The default value is 32, which corresponds to the middle of the trimming interval.
bogdanm	84:0b3ab51c8877	541	The trimming step is around 67 kHz between two consecutive TRIM steps. A higher TRIM value
bogdanm	84:0b3ab51c8877	542	corresponds to a higher output frequency */
bogdanm	84:0b3ab51c8877	543
Kojto	96:487b796308b0	544	#define IS_RCC_CRS_HSI48CALIBRATION(__VALUE__) (((__VALUE__) <= 0x3F))
bogdanm	84:0b3ab51c8877	545	/**
bogdanm	84:0b3ab51c8877	546	* @}
bogdanm	84:0b3ab51c8877	547	*/
bogdanm	84:0b3ab51c8877	548
bogdanm	84:0b3ab51c8877	549	/** @defgroup RCCEx_CRS_FreqErrorDirection
bogdanm	84:0b3ab51c8877	550	* @{
bogdanm	84:0b3ab51c8877	551	*/
bogdanm	84:0b3ab51c8877	552	#define RCC_CRS_FREQERRORDIR_UP ((uint32_t)0x00) /!< Upcounting direction, the actual frequency is above the target /
bogdanm	84:0b3ab51c8877	553	#define RCC_CRS_FREQERRORDIR_DOWN ((uint32_t)CRS_ISR_FEDIR) /!< Downcounting direction, the actual frequency is below the target /
bogdanm	84:0b3ab51c8877	554
Kojto	96:487b796308b0	555	#define IS_RCC_CRS_FREQERRORDIR(__DIR__) (((__DIR__) == RCC_CRS_FREQERRORDIR_UP) \|\| \
Kojto	96:487b796308b0	556	((__DIR__) == RCC_CRS_FREQERRORDIR_DOWN))
bogdanm	84:0b3ab51c8877	557	/**
bogdanm	84:0b3ab51c8877	558	* @}
bogdanm	84:0b3ab51c8877	559	*/
bogdanm	84:0b3ab51c8877	560
bogdanm	84:0b3ab51c8877	561	/** @defgroup RCCEx_CRS_Interrupt_Sources
bogdanm	84:0b3ab51c8877	562	* @{
bogdanm	84:0b3ab51c8877	563	*/
bogdanm	84:0b3ab51c8877	564	#define RCC_CRS_IT_SYNCOK CRS_ISR_SYNCOKF /!< SYNC event OK /
bogdanm	84:0b3ab51c8877	565	#define RCC_CRS_IT_SYNCWARN CRS_ISR_SYNCWARNF /!< SYNC warning /
bogdanm	84:0b3ab51c8877	566	#define RCC_CRS_IT_ERR CRS_ISR_ERRF /!< error /
bogdanm	84:0b3ab51c8877	567	#define RCC_CRS_IT_ESYNC CRS_ISR_ESYNCF /!< Expected SYNC /
bogdanm	84:0b3ab51c8877	568	#define RCC_CRS_IT_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	84:0b3ab51c8877	569	#define RCC_CRS_IT_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	84:0b3ab51c8877	570	#define RCC_CRS_IT_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	84:0b3ab51c8877	571
bogdanm	84:0b3ab51c8877	572	/**
bogdanm	84:0b3ab51c8877	573	* @}
bogdanm	84:0b3ab51c8877	574	*/
bogdanm	84:0b3ab51c8877	575
bogdanm	84:0b3ab51c8877	576	/** @defgroup RCCEx_CRS_Flags
bogdanm	84:0b3ab51c8877	577	* @{
bogdanm	84:0b3ab51c8877	578	*/
bogdanm	84:0b3ab51c8877	579	#define RCC_CRS_FLAG_SYNCOK CRS_ISR_SYNCOKF /* SYNC event OK flag */
bogdanm	84:0b3ab51c8877	580	#define RCC_CRS_FLAG_SYNCWARN CRS_ISR_SYNCWARNF /* SYNC warning flag */
bogdanm	84:0b3ab51c8877	581	#define RCC_CRS_FLAG_ERR CRS_ISR_ERRF /* Error flag */
bogdanm	84:0b3ab51c8877	582	#define RCC_CRS_FLAG_ESYNC CRS_ISR_ESYNCF /* Expected SYNC flag */
bogdanm	84:0b3ab51c8877	583	#define RCC_CRS_FLAG_TRIMOVF CRS_ISR_TRIMOVF /!< Trimming overflow or underflow /
bogdanm	84:0b3ab51c8877	584	#define RCC_CRS_FLAG_SYNCERR CRS_ISR_SYNCERR /!< SYNC error /
bogdanm	84:0b3ab51c8877	585	#define RCC_CRS_FLAG_SYNCMISS CRS_ISR_SYNCMISS /!< SYNC missed/
bogdanm	84:0b3ab51c8877	586
bogdanm	84:0b3ab51c8877	587	/**
bogdanm	84:0b3ab51c8877	588	* @}
bogdanm	84:0b3ab51c8877	589	*/
bogdanm	84:0b3ab51c8877	590
Kojto	96:487b796308b0	591	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	84:0b3ab51c8877	592	/**
bogdanm	84:0b3ab51c8877	593	* @}
bogdanm	84:0b3ab51c8877	594	*/
bogdanm	84:0b3ab51c8877	595
bogdanm	84:0b3ab51c8877	596	/* Exported macro ------------------------------------------------------------*/
Kojto	96:487b796308b0	597	/** @defgroup RCCEx_Exported_Macros RCC Ex Exported Macros
bogdanm	84:0b3ab51c8877	598	* @{
bogdanm	84:0b3ab51c8877	599	*/
bogdanm	84:0b3ab51c8877	600
bogdanm	84:0b3ab51c8877	601	/** @brief Enable or disable the AHB peripheral clock.
bogdanm	84:0b3ab51c8877	602	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	84:0b3ab51c8877	603	* is disabled and the application software has to enable this clock before
bogdanm	84:0b3ab51c8877	604	* using it.
bogdanm	84:0b3ab51c8877	605	*/
bogdanm	84:0b3ab51c8877	606
Kojto	96:487b796308b0	607	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	608	#define __HAL_RCC_AES_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRYPEN))
Kojto	96:487b796308b0	609	#define __HAL_RCC_AES_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_CRYPEN))
Kojto	96:487b796308b0	610	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
Kojto	96:487b796308b0	611
Kojto	96:487b796308b0	612	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	96:487b796308b0	613	#define __HAL_RCC_TSC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_TSCEN))
Kojto	96:487b796308b0	614	#define __HAL_RCC_TSC_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_TSCEN))
Kojto	96:487b796308b0	615
Kojto	96:487b796308b0	616	#define __HAL_RCC_RNG_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_RNGEN))
Kojto	96:487b796308b0	617	#define __HAL_RCC_RNG_CLK_DISABLE() (RCC->AHBENR &= ~ (RCC_AHBENR_RNGEN))
Kojto	96:487b796308b0	618	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto	96:487b796308b0	619
bogdanm	84:0b3ab51c8877	620
Kojto	96:487b796308b0	621	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	622	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	623	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	624	/** @brief Enable or disable the IOPORT peripheral clock.
Kojto	96:487b796308b0	625	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	96:487b796308b0	626	* is disabled and the application software has to enable this clock before
Kojto	96:487b796308b0	627	* using it.
Kojto	96:487b796308b0	628	*/
Kojto	96:487b796308b0	629	#define __HAL_RCC_GPIOE_CLK_ENABLE() do { \
Kojto	96:487b796308b0	630	__IO uint32_t tmpreg; \
Kojto	96:487b796308b0	631	SET_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
Kojto	96:487b796308b0	632	/* Delay after an RCC peripheral clock enabling */ \
Kojto	96:487b796308b0	633	tmpreg = READ_BIT(RCC->IOPENR, RCC_IOPENR_GPIOEEN);\
Kojto	96:487b796308b0	634	UNUSED(tmpreg); \
Kojto	96:487b796308b0	635	} while(0)
bogdanm	84:0b3ab51c8877	636
Kojto	96:487b796308b0	637	#define __HAL_RCC_GPIOE_CLK_DISABLE() (RCC->IOPENR &= ~(RCC_IOPENR_GPIOEEN))
Kojto	96:487b796308b0	638
Kojto	96:487b796308b0	639	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	640	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	641	/* STM32L073xx \|\| STM32L083xx */
bogdanm	84:0b3ab51c8877	642
bogdanm	84:0b3ab51c8877	643	/** @brief Enable or disable the APB1 peripheral clock.
bogdanm	84:0b3ab51c8877	644	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	84:0b3ab51c8877	645	* is disabled and the application software has to enable this clock before
bogdanm	84:0b3ab51c8877	646	* using it.
bogdanm	84:0b3ab51c8877	647	*/
bogdanm	84:0b3ab51c8877	648
Kojto	96:487b796308b0	649	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	96:487b796308b0	650	#define __HAL_RCC_USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
Kojto	96:487b796308b0	651	#define __HAL_RCC_USB_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USBEN))
bogdanm	84:0b3ab51c8877	652
Kojto	96:487b796308b0	653	#define __HAL_RCC_CRS_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CRSEN))
Kojto	96:487b796308b0	654	#define __HAL_RCC_CRS_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CRSEN))
Kojto	96:487b796308b0	655	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	84:0b3ab51c8877	656
bogdanm	84:0b3ab51c8877	657
Kojto	96:487b796308b0	658	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	659	#define __HAL_RCC_LCD_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LCDEN))
Kojto	96:487b796308b0	660	#define __HAL_RCC_LCD_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LCDEN))
Kojto	96:487b796308b0	661	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	84:0b3ab51c8877	662
bogdanm	84:0b3ab51c8877	663	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	664	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
bogdanm	84:0b3ab51c8877	665	defined(STM32L051xx) \|\| defined(STM32L061xx)
Kojto	96:487b796308b0	666	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
Kojto	96:487b796308b0	667	#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
Kojto	96:487b796308b0	668	#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	96:487b796308b0	669	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
Kojto	96:487b796308b0	670	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
Kojto	96:487b796308b0	671	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
Kojto	96:487b796308b0	672	#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	96:487b796308b0	673	#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
Kojto	96:487b796308b0	674	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
Kojto	96:487b796308b0	675
Kojto	96:487b796308b0	676	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
Kojto	96:487b796308b0	677	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
Kojto	96:487b796308b0	678	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
Kojto	96:487b796308b0	679	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
Kojto	96:487b796308b0	680	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
Kojto	96:487b796308b0	681	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
Kojto	96:487b796308b0	682	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
Kojto	96:487b796308b0	683	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
Kojto	96:487b796308b0	684	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
Kojto	96:487b796308b0	685	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
Kojto	96:487b796308b0	686	/* STM32L052xx \|\| STM32L062xx \|\| */
Kojto	96:487b796308b0	687	/* STM32L053xx \|\| STM32L063xx \|\| */
Kojto	96:487b796308b0	688
Kojto	96:487b796308b0	689	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
Kojto	96:487b796308b0	690	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
Kojto	96:487b796308b0	691	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
Kojto	96:487b796308b0	692	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
Kojto	96:487b796308b0	693	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
Kojto	96:487b796308b0	694	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
Kojto	96:487b796308b0	695
Kojto	96:487b796308b0	696	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
Kojto	96:487b796308b0	697	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
Kojto	96:487b796308b0	698	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
Kojto	96:487b796308b0	699	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
Kojto	96:487b796308b0	700	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
Kojto	96:487b796308b0	701	#endif /* STM32L031xx \|\| STM32L041xx \|\| */
Kojto	96:487b796308b0	702
bogdanm	84:0b3ab51c8877	703
Kojto	96:487b796308b0	704	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	705	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	706	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	707	#define __HAL_RCC_TIM2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM2EN))
Kojto	96:487b796308b0	708	#define __HAL_RCC_TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	96:487b796308b0	709	#define __HAL_RCC_TIM6_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM6EN))
Kojto	96:487b796308b0	710	#define __HAL_RCC_TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
Kojto	96:487b796308b0	711	#define __HAL_RCC_SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
Kojto	96:487b796308b0	712	#define __HAL_RCC_USART2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART2EN))
Kojto	96:487b796308b0	713	#define __HAL_RCC_USART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART4EN))
Kojto	96:487b796308b0	714	#define __HAL_RCC_USART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USART5EN))
Kojto	96:487b796308b0	715	#define __HAL_RCC_LPUART1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPUART1EN))
Kojto	96:487b796308b0	716	#define __HAL_RCC_I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
Kojto	96:487b796308b0	717	#define __HAL_RCC_I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
Kojto	96:487b796308b0	718	#define __HAL_RCC_I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
Kojto	96:487b796308b0	719	#define __HAL_RCC_DAC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DACEN))
Kojto	96:487b796308b0	720	#define __HAL_RCC_LPTIM1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_LPTIM1EN))
Kojto	96:487b796308b0	721
Kojto	96:487b796308b0	722	#define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM2EN))
Kojto	96:487b796308b0	723	#define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM3EN))
Kojto	96:487b796308b0	724	#define __HAL_RCC_TIM6_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM6EN))
Kojto	96:487b796308b0	725	#define __HAL_RCC_TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_TIM7EN))
Kojto	96:487b796308b0	726	#define __HAL_RCC_SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_SPI2EN))
Kojto	96:487b796308b0	727	#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART2EN))
Kojto	96:487b796308b0	728	#define __HAL_RCC_USART4_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART4EN))
Kojto	96:487b796308b0	729	#define __HAL_RCC_USART5_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_USART5EN))
Kojto	96:487b796308b0	730	#define __HAL_RCC_LPUART1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPUART1EN))
Kojto	96:487b796308b0	731	#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C1EN))
Kojto	96:487b796308b0	732	#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C2EN))
Kojto	96:487b796308b0	733	#define __HAL_RCC_I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_I2C3EN))
Kojto	96:487b796308b0	734	#define __HAL_RCC_DAC_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_DACEN))
Kojto	96:487b796308b0	735	#define __HAL_RCC_LPTIM1_CLK_DISABLE() (RCC->APB1ENR &= ~ (RCC_APB1ENR_LPTIM1EN))
Kojto	96:487b796308b0	736	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	737	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	738	/* STM32L073xx \|\| STM32L083xx */
Kojto	96:487b796308b0	739
Kojto	96:487b796308b0	740	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	741	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	742	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx) \|\| \
Kojto	96:487b796308b0	743	defined(STM32L031xx) \|\| defined(STM32L041xx)
Kojto	96:487b796308b0	744
bogdanm	84:0b3ab51c8877	745	/** @brief Enable or disable the APB2 peripheral clock.
bogdanm	84:0b3ab51c8877	746	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	84:0b3ab51c8877	747	* is disabled and the application software has to enable this clock before
bogdanm	84:0b3ab51c8877	748	* using it.
bogdanm	84:0b3ab51c8877	749	*/
Kojto	96:487b796308b0	750	#define __HAL_RCC_TIM21_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM21EN))
Kojto	96:487b796308b0	751	#define __HAL_RCC_TIM22_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM22EN))
Kojto	96:487b796308b0	752	#define __HAL_RCC_FIREWALL_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_MIFIEN))
Kojto	96:487b796308b0	753	#define __HAL_RCC_ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
Kojto	96:487b796308b0	754	#define __HAL_RCC_SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	96:487b796308b0	755	#define __HAL_RCC_USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
bogdanm	84:0b3ab51c8877	756
Kojto	96:487b796308b0	757	#define __HAL_RCC_TIM21_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM21EN))
Kojto	96:487b796308b0	758	#define __HAL_RCC_TIM22_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_TIM22EN))
Kojto	96:487b796308b0	759	#define __HAL_RCC_FIREWALL_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_MIFIEN))
Kojto	96:487b796308b0	760	#define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_ADC1EN))
Kojto	96:487b796308b0	761	#define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_SPI1EN))
Kojto	96:487b796308b0	762	#define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~ (RCC_APB2ENR_USART1EN))
Kojto	96:487b796308b0	763	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	764	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	765	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	84:0b3ab51c8877	766
bogdanm	84:0b3ab51c8877	767	/** @brief Force or release AHB peripheral reset.
bogdanm	84:0b3ab51c8877	768	*/
Kojto	96:487b796308b0	769	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	770	#define __HAL_RCC_AES_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_CRYPRST))
Kojto	96:487b796308b0	771	#define __HAL_RCC_AES_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_CRYPRST))
Kojto	96:487b796308b0	772	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
Kojto	96:487b796308b0	773
Kojto	96:487b796308b0	774	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	96:487b796308b0	775	#define __HAL_RCC_TSC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_TSCRST))
Kojto	96:487b796308b0	776	#define __HAL_RCC_TSC_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_TSCRST))
Kojto	96:487b796308b0	777	#define __HAL_RCC_RNG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_RNGRST))
Kojto	96:487b796308b0	778	#define __HAL_RCC_RNG_RELEASE_RESET() (RCC->AHBRSTR &= ~ (RCC_AHBRSTR_RNGRST))
Kojto	96:487b796308b0	779	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	84:0b3ab51c8877	780
Kojto	96:487b796308b0	781	/** @brief Force or release IOPORT peripheral reset.
Kojto	96:487b796308b0	782	*/
Kojto	96:487b796308b0	783	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	784	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	785	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	786	#define __HAL_RCC_GPIOE_FORCE_RESET() (RCC->IOPRSTR \|= (RCC_IOPRSTR_GPIOERST))
bogdanm	84:0b3ab51c8877	787
Kojto	96:487b796308b0	788	#define __HAL_RCC_GPIOE_RELEASE_RESET() (RCC->IOPRSTR &= ~(RCC_IOPRSTR_GPIOERST))
Kojto	96:487b796308b0	789
Kojto	96:487b796308b0	790	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	791	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	792	/* STM32L073xx \|\| STM32L083xx */
Kojto	96:487b796308b0	793
bogdanm	84:0b3ab51c8877	794	/** @brief Force or release APB1 peripheral reset.
bogdanm	84:0b3ab51c8877	795	*/
Kojto	96:487b796308b0	796
bogdanm	84:0b3ab51c8877	797	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	798	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
Kojto	96:487b796308b0	799	defined(STM32L051xx) \|\| defined(STM32L061xx)
Kojto	96:487b796308b0	800	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	96:487b796308b0	801	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	96:487b796308b0	802	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
Kojto	96:487b796308b0	803	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	96:487b796308b0	804	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	96:487b796308b0	805	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	96:487b796308b0	806	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
Kojto	96:487b796308b0	807	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	96:487b796308b0	808	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	84:0b3ab51c8877	809
Kojto	96:487b796308b0	810	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
Kojto	96:487b796308b0	811	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
Kojto	96:487b796308b0	812	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
Kojto	96:487b796308b0	813	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
Kojto	96:487b796308b0	814	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
Kojto	96:487b796308b0	815	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
Kojto	96:487b796308b0	816	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
Kojto	96:487b796308b0	817	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
Kojto	96:487b796308b0	818	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
bogdanm	84:0b3ab51c8877	819	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	84:0b3ab51c8877	820	/* STM32L052xx \|\| STM32L062xx \|\| */
Kojto	96:487b796308b0	821	/* STM32L053xx \|\| STM32L063xx */
Kojto	96:487b796308b0	822	#if defined(STM32L031xx) \|\| defined(STM32L041xx)
Kojto	96:487b796308b0	823	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	96:487b796308b0	824	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
Kojto	96:487b796308b0	825	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	96:487b796308b0	826	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	96:487b796308b0	827	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
Kojto	96:487b796308b0	828
Kojto	96:487b796308b0	829	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
Kojto	96:487b796308b0	830	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
Kojto	96:487b796308b0	831	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
Kojto	96:487b796308b0	832	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
Kojto	96:487b796308b0	833	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
Kojto	96:487b796308b0	834	#endif /* STM32L031xx \|\| STM32L041xx \|\| */
bogdanm	84:0b3ab51c8877	835
Kojto	96:487b796308b0	836	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	837	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	838	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	839	#define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM2RST))
Kojto	96:487b796308b0	840	#define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	96:487b796308b0	841	#define __HAL_RCC_TIM6_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM6RST))
Kojto	96:487b796308b0	842	#define __HAL_RCC_TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
Kojto	96:487b796308b0	843	#define __HAL_RCC_LPTIM1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPTIM1RST))
Kojto	96:487b796308b0	844	#define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	96:487b796308b0	845	#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
Kojto	96:487b796308b0	846	#define __HAL_RCC_I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
Kojto	96:487b796308b0	847	#define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART2RST))
Kojto	96:487b796308b0	848	#define __HAL_RCC_USART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART4RST))
Kojto	96:487b796308b0	849	#define __HAL_RCC_USART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USART5RST))
Kojto	96:487b796308b0	850	#define __HAL_RCC_LPUART1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LPUART1RST))
Kojto	96:487b796308b0	851	#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
Kojto	96:487b796308b0	852	#define __HAL_RCC_DAC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DACRST))
bogdanm	84:0b3ab51c8877	853
Kojto	96:487b796308b0	854	#define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM2RST))
Kojto	96:487b796308b0	855	#define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM3RST))
Kojto	96:487b796308b0	856	#define __HAL_RCC_TIM6_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM6RST))
Kojto	96:487b796308b0	857	#define __HAL_RCC_TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_TIM7RST))
Kojto	96:487b796308b0	858	#define __HAL_RCC_LPTIM1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPTIM1RST))
Kojto	96:487b796308b0	859	#define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C1RST))
Kojto	96:487b796308b0	860	#define __HAL_RCC_I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C2RST))
Kojto	96:487b796308b0	861	#define __HAL_RCC_I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_I2C3RST))
Kojto	96:487b796308b0	862	#define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART2RST))
Kojto	96:487b796308b0	863	#define __HAL_RCC_USART4_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART4RST))
Kojto	96:487b796308b0	864	#define __HAL_RCC_USART5_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USART5RST))
Kojto	96:487b796308b0	865	#define __HAL_RCC_LPUART1_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LPUART1RST))
Kojto	96:487b796308b0	866	#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_SPI2RST))
Kojto	96:487b796308b0	867	#define __HAL_RCC_DAC_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_DACRST))
Kojto	96:487b796308b0	868	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	869	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	870	/* STM32L073xx \|\| STM32L083xx \|\| */
Kojto	96:487b796308b0	871
Kojto	96:487b796308b0	872	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	96:487b796308b0	873	#define __HAL_RCC_USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
Kojto	96:487b796308b0	874	#define __HAL_RCC_USB_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_USBRST))
Kojto	96:487b796308b0	875	#define __HAL_RCC_CRS_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CRSRST))
Kojto	96:487b796308b0	876	#define __HAL_RCC_CRS_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CRSRST))
Kojto	96:487b796308b0	877	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
Kojto	96:487b796308b0	878
Kojto	96:487b796308b0	879	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	880	#define __HAL_RCC_LCD_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_LCDRST))
Kojto	96:487b796308b0	881	#define __HAL_RCC_LCD_RELEASE_RESET() (RCC->APB1RSTR &= ~ (RCC_APB1RSTR_LCDRST))
Kojto	96:487b796308b0	882	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
Kojto	96:487b796308b0	883
Kojto	96:487b796308b0	884	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	885	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	886	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	887	/** @brief Force or release APB2 peripheral reset.
bogdanm	84:0b3ab51c8877	888	*/
Kojto	96:487b796308b0	889	#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	96:487b796308b0	890	#define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
Kojto	96:487b796308b0	891	#define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	96:487b796308b0	892	#define __HAL_RCC_TIM21_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM21RST))
Kojto	96:487b796308b0	893	#define __HAL_RCC_TIM22_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM22RST))
bogdanm	84:0b3ab51c8877	894
Kojto	96:487b796308b0	895	#define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_USART1RST))
Kojto	96:487b796308b0	896	#define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_ADC1RST))
Kojto	96:487b796308b0	897	#define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_SPI1RST))
Kojto	96:487b796308b0	898	#define __HAL_RCC_TIM21_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM21RST))
Kojto	96:487b796308b0	899	#define __HAL_RCC_TIM22_RELEASE_RESET() (RCC->APB2RSTR &= ~ (RCC_APB2RSTR_TIM22RST))
Kojto	96:487b796308b0	900	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	901	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	902	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	84:0b3ab51c8877	903
bogdanm	84:0b3ab51c8877	904	/** @brief Enable or disable the AHB peripheral clock during Low Power (Sleep) mode.
bogdanm	84:0b3ab51c8877	905	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	84:0b3ab51c8877	906	* power consumption.
bogdanm	84:0b3ab51c8877	907	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	84:0b3ab51c8877	908	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	84:0b3ab51c8877	909	*/
bogdanm	84:0b3ab51c8877	910
Kojto	96:487b796308b0	911	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	96:487b796308b0	912	#define __HAL_RCC_TSC_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_TSCSMEN))
Kojto	96:487b796308b0	913	#define __HAL_RCC_RNG_CLK_SLEEP_ENABLE() (RCC->AHBSMENR \|= (RCC_AHBSMENR_RNGSMEN))
Kojto	96:487b796308b0	914	#define __HAL_RCC_TSC_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_TSCSMEN))
Kojto	96:487b796308b0	915	#define __HAL_RCC_RNG_CLK_SLEEP_DISABLE() (RCC->AHBSMENR &= ~ (RCC_AHBSMENR_RNGSMEN))
Kojto	96:487b796308b0	916	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	84:0b3ab51c8877	917
Kojto	96:487b796308b0	918	#if defined(STM32L062xx) \|\| defined(STM32L063xx)\|\| defined(STM32L082xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	919	#define __HAL_RCC_AES_CLK_SLEEP_ENABLE() (RCC->AHBLPENR \|= (RCC_AHBSMENR_CRYPSMEN))
Kojto	96:487b796308b0	920	#define __HAL_RCC_AES_CLK_SLEEP_DISABLE() (RCC->AHBLPENR &= ~ (RCC_AHBSMENR_CRYPSMEN))
Kojto	96:487b796308b0	921	#endif /* STM32L062xx \|\| STM32L063xx \|\| STM32L072xx \|\| STM32L073xx \|\| STM32L082xx \|\| STM32L083xx */
bogdanm	84:0b3ab51c8877	922
Kojto	96:487b796308b0	923	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	924	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	925	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	926	/** @brief Enable or disable the IOPORT peripheral clock during Low Power (Sleep) mode.
Kojto	96:487b796308b0	927	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
Kojto	96:487b796308b0	928	* power consumption.
Kojto	96:487b796308b0	929	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
Kojto	96:487b796308b0	930	* @note By default, all peripheral clocks are enabled during SLEEP mode.
Kojto	96:487b796308b0	931	*/
Kojto	96:487b796308b0	932
Kojto	96:487b796308b0	933	#define __HAL_RCC_GPIOE_CLK_SLEEP_ENABLE() (RCC->IOPSMENR \|= (RCC_IOPSMENR_GPIOESMEN))
Kojto	96:487b796308b0	934	#define __HAL_RCC_GPIOE_CLK_SLEEP_DISABLE() (RCC->IOPSMENR &= ~(RCC_IOPSMENR_GPIOESMEN))
Kojto	96:487b796308b0	935
Kojto	96:487b796308b0	936	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	937	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	938	/* STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	84:0b3ab51c8877	939
bogdanm	84:0b3ab51c8877	940	/** @brief Enable or disable the APB1 peripheral clock during Low Power (Sleep) mode.
bogdanm	84:0b3ab51c8877	941	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	84:0b3ab51c8877	942	* power consumption.
bogdanm	84:0b3ab51c8877	943	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	84:0b3ab51c8877	944	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	84:0b3ab51c8877	945	*/
bogdanm	84:0b3ab51c8877	946
bogdanm	84:0b3ab51c8877	947	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| \
bogdanm	84:0b3ab51c8877	948	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| \
Kojto	96:487b796308b0	949	defined(STM32L051xx) \|\| defined(STM32L061xx)
Kojto	96:487b796308b0	950	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM2SMEN))
Kojto	96:487b796308b0	951	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM6SMEN))
Kojto	96:487b796308b0	952	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_SPI2SMEN))
Kojto	96:487b796308b0	953	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART2SMEN))
Kojto	96:487b796308b0	954	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPUART1SMEN))
Kojto	96:487b796308b0	955	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C1SMEN))
Kojto	96:487b796308b0	956	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C2SMEN))
Kojto	96:487b796308b0	957	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_DACSMEN))
Kojto	96:487b796308b0	958	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	84:0b3ab51c8877	959
Kojto	96:487b796308b0	960	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
Kojto	96:487b796308b0	961	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
Kojto	96:487b796308b0	962	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
Kojto	96:487b796308b0	963	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
Kojto	96:487b796308b0	964	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
Kojto	96:487b796308b0	965	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
Kojto	96:487b796308b0	966	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
Kojto	96:487b796308b0	967	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
Kojto	96:487b796308b0	968	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	84:0b3ab51c8877	969	#endif /* STM32L051xx \|\| STM32L061xx \|\| */
bogdanm	84:0b3ab51c8877	970	/* STM32L052xx \|\| STM32L062xx \|\| */
Kojto	96:487b796308b0	971	/* STM32L053xx \|\| STM32L063xx */
bogdanm	84:0b3ab51c8877	972
Kojto	96:487b796308b0	973	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	974	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	975	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	976	#define __HAL_RCC_TIM2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM2SMEN))
Kojto	96:487b796308b0	977	#define __HAL_RCC_TIM3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM3SMEN))
Kojto	96:487b796308b0	978	#define __HAL_RCC_TIM6_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM6SMEN))
Kojto	96:487b796308b0	979	#define __HAL_RCC_TIM7_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_TIM7SMEN))
Kojto	96:487b796308b0	980	#define __HAL_RCC_SPI2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_SPI2SMEN))
Kojto	96:487b796308b0	981	#define __HAL_RCC_USART2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART2SMEN))
Kojto	96:487b796308b0	982	#define __HAL_RCC_USART4_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART4SMEN))
Kojto	96:487b796308b0	983	#define __HAL_RCC_USART5_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USART5SMEN))
Kojto	96:487b796308b0	984	#define __HAL_RCC_LPUART1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPUART1SMEN))
Kojto	96:487b796308b0	985	#define __HAL_RCC_I2C1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C1SMEN))
Kojto	96:487b796308b0	986	#define __HAL_RCC_I2C2_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C2SMEN))
Kojto	96:487b796308b0	987	#define __HAL_RCC_I2C3_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_I2C3SMEN))
Kojto	96:487b796308b0	988	#define __HAL_RCC_DAC_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_DACSMEN))
Kojto	96:487b796308b0	989	#define __HAL_RCC_LPTIM1_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LPTIM1SMEN))
bogdanm	84:0b3ab51c8877	990
Kojto	96:487b796308b0	991	#define __HAL_RCC_TIM2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM2SMEN))
Kojto	96:487b796308b0	992	#define __HAL_RCC_TIM3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM3SMEN))
Kojto	96:487b796308b0	993	#define __HAL_RCC_TIM6_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM6SMEN))
Kojto	96:487b796308b0	994	#define __HAL_RCC_TIM7_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_TIM7SMEN))
Kojto	96:487b796308b0	995	#define __HAL_RCC_SPI2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_SPI2SMEN))
Kojto	96:487b796308b0	996	#define __HAL_RCC_USART2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART2SMEN))
Kojto	96:487b796308b0	997	#define __HAL_RCC_USART4_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART4SMEN))
Kojto	96:487b796308b0	998	#define __HAL_RCC_USART5_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USART5SMEN))
Kojto	96:487b796308b0	999	#define __HAL_RCC_LPUART1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPUART1SMEN))
Kojto	96:487b796308b0	1000	#define __HAL_RCC_I2C1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C1SMEN))
Kojto	96:487b796308b0	1001	#define __HAL_RCC_I2C2_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C2SMEN))
Kojto	96:487b796308b0	1002	#define __HAL_RCC_I2C3_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_I2C3SMEN))
Kojto	96:487b796308b0	1003	#define __HAL_RCC_DAC_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_DACSMEN))
Kojto	96:487b796308b0	1004	#define __HAL_RCC_LPTIM1_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LPTIM1SMEN))
Kojto	96:487b796308b0	1005	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	1006	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	1007	/* STM32L073xx \|\| STM32L083xx \|\| */
Kojto	96:487b796308b0	1008
Kojto	96:487b796308b0	1009	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
Kojto	96:487b796308b0	1010	#define __HAL_RCC_USB_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_USBSMEN))
Kojto	96:487b796308b0	1011	#define __HAL_RCC_USB_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_USBSMEN))
Kojto	96:487b796308b0	1012	#define __HAL_RCC_CRS_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_CRSSMEN))
Kojto	96:487b796308b0	1013	#define __HAL_RCC_CRS_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_CRSSMEN))
Kojto	96:487b796308b0	1014	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	84:0b3ab51c8877	1015
Kojto	96:487b796308b0	1016	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx)
Kojto	96:487b796308b0	1017	#define __HAL_RCC_LCD_CLK_SLEEP_ENABLE() (RCC->APB1SMENR \|= (RCC_APB1SMENR_LCDSMEN))
Kojto	96:487b796308b0	1018	#define __HAL_RCC_LCD_CLK_SLEEP_DISABLE() (RCC->APB1SMENR &= ~ (RCC_APB1SMENR_LCDSMEN))
Kojto	96:487b796308b0	1019	#endif /* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx */
bogdanm	84:0b3ab51c8877	1020
Kojto	96:487b796308b0	1021	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	1022	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	1023	defined(STM32L051xx) \|\| defined(STM32L061xx) \|\| defined(STM32L071xx) \|\| defined(STM32L081xx)
bogdanm	84:0b3ab51c8877	1024	/** @brief Enable or disable the APB2 peripheral clock during Low Power (Sleep) mode.
bogdanm	84:0b3ab51c8877	1025	* @note Peripheral clock gating in SLEEP mode can be used to further reduce
bogdanm	84:0b3ab51c8877	1026	* power consumption.
bogdanm	84:0b3ab51c8877	1027	* @note After wakeup from SLEEP mode, the peripheral clock is enabled again.
bogdanm	84:0b3ab51c8877	1028	* @note By default, all peripheral clocks are enabled during SLEEP mode.
bogdanm	84:0b3ab51c8877	1029	*/
Kojto	96:487b796308b0	1030	#define __HAL_RCC_TIM21_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_TIM21SMEN))
Kojto	96:487b796308b0	1031	#define __HAL_RCC_TIM22_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_TIM22SMEN))
Kojto	96:487b796308b0	1032	#define __HAL_RCC_ADC1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_ADC1SMEN))
Kojto	96:487b796308b0	1033	#define __HAL_RCC_SPI1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_SPI1SMEN))
Kojto	96:487b796308b0	1034	#define __HAL_RCC_USART1_CLK_SLEEP_ENABLE() (RCC->APB2SMENR \|= (RCC_APB2SMENR_USART1SMEN))
bogdanm	84:0b3ab51c8877	1035
Kojto	96:487b796308b0	1036	#define __HAL_RCC_TIM21_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM21SMEN))
Kojto	96:487b796308b0	1037	#define __HAL_RCC_TIM22_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_TIM22SMEN))
Kojto	96:487b796308b0	1038	#define __HAL_RCC_ADC1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_ADC1SMEN))
Kojto	96:487b796308b0	1039	#define __HAL_RCC_SPI1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_SPI1SMEN))
Kojto	96:487b796308b0	1040	#define __HAL_RCC_USART1_CLK_SLEEP_DISABLE() (RCC->APB2SMENR &= ~ (RCC_APB2SMENR_USART1SMEN))
Kojto	96:487b796308b0	1041	#endif /* STM32L051xx \|\| STM32L061xx \|\| STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	1042	/* STM32L052xx \|\| STM32L062xx \|\| STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	1043	/* STM32L053xx \|\| STM32L063xx \|\| STM32L073xx \|\| STM32L083xx \|\| */
bogdanm	84:0b3ab51c8877	1044
bogdanm	84:0b3ab51c8877	1045	/** @brief macro to configure the I2C1 clock (I2C1CLK).
bogdanm	84:0b3ab51c8877	1046	*
bogdanm	84:0b3ab51c8877	1047	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
bogdanm	84:0b3ab51c8877	1048	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1049	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	84:0b3ab51c8877	1050	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	84:0b3ab51c8877	1051	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	84:0b3ab51c8877	1052	*/
bogdanm	84:0b3ab51c8877	1053	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
bogdanm	84:0b3ab51c8877	1054	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C1SEL, (uint32_t)(__I2C1CLKSource__))
bogdanm	84:0b3ab51c8877	1055
bogdanm	84:0b3ab51c8877	1056	/** @brief macro to get the I2C1 clock source.
bogdanm	84:0b3ab51c8877	1057	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	1058	* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
bogdanm	84:0b3ab51c8877	1059	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
bogdanm	84:0b3ab51c8877	1060	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
bogdanm	84:0b3ab51c8877	1061	*/
bogdanm	84:0b3ab51c8877	1062	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C1SEL)))
bogdanm	84:0b3ab51c8877	1063
Kojto	96:487b796308b0	1064	#if defined (STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	1065	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	1066	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	1067	/** @brief macro to configure the I2C3 clock (I2C3CLK).
Kojto	96:487b796308b0	1068	*
Kojto	96:487b796308b0	1069	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
Kojto	96:487b796308b0	1070	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1071	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto	96:487b796308b0	1072	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	96:487b796308b0	1073	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	96:487b796308b0	1074	*/
Kojto	96:487b796308b0	1075	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
Kojto	96:487b796308b0	1076	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_I2C3SEL, (uint32_t)(__I2C3CLKSource__))
Kojto	96:487b796308b0	1077
Kojto	96:487b796308b0	1078	/** @brief macro to get the I2C3 clock source.
Kojto	96:487b796308b0	1079	* @retval The clock source can be one of the following values:
Kojto	96:487b796308b0	1080	* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
Kojto	96:487b796308b0	1081	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
Kojto	96:487b796308b0	1082	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
Kojto	96:487b796308b0	1083	*/
Kojto	96:487b796308b0	1084	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_I2C3SEL)))
Kojto	96:487b796308b0	1085
Kojto	96:487b796308b0	1086	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	1087	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	1088	/* STM32L073xx \|\| STM32L083xx \|\| */
Kojto	96:487b796308b0	1089
bogdanm	84:0b3ab51c8877	1090	/** @brief macro to configure the USART1 clock (USART1CLK).
bogdanm	84:0b3ab51c8877	1091	*
bogdanm	84:0b3ab51c8877	1092	* @param __USART1CLKSource__: specifies the USART1 clock source.
bogdanm	84:0b3ab51c8877	1093	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1094	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	84:0b3ab51c8877	1095	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	84:0b3ab51c8877	1096	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	84:0b3ab51c8877	1097	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	84:0b3ab51c8877	1098	*/
bogdanm	84:0b3ab51c8877	1099	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
bogdanm	84:0b3ab51c8877	1100	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART1SEL, (uint32_t)(__USART1CLKSource__))
bogdanm	84:0b3ab51c8877	1101
bogdanm	84:0b3ab51c8877	1102	/** @brief macro to get the USART1 clock source.
bogdanm	84:0b3ab51c8877	1103	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	1104	* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
bogdanm	84:0b3ab51c8877	1105	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
bogdanm	84:0b3ab51c8877	1106	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
bogdanm	84:0b3ab51c8877	1107	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
bogdanm	84:0b3ab51c8877	1108	*/
bogdanm	84:0b3ab51c8877	1109	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART1SEL)))
bogdanm	84:0b3ab51c8877	1110
bogdanm	84:0b3ab51c8877	1111	/** @brief macro to configure the USART2 clock (USART2CLK).
bogdanm	84:0b3ab51c8877	1112	*
bogdanm	84:0b3ab51c8877	1113	* @param __USART2CLKSource__: specifies the USART2 clock source.
bogdanm	84:0b3ab51c8877	1114	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1115	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	84:0b3ab51c8877	1116	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	84:0b3ab51c8877	1117	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	84:0b3ab51c8877	1118	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	84:0b3ab51c8877	1119	*/
bogdanm	84:0b3ab51c8877	1120	#define __HAL_RCC_USART2_CONFIG(__USART2CLKSource__) \
bogdanm	84:0b3ab51c8877	1121	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_USART2SEL, (uint32_t)(__USART2CLKSource__))
bogdanm	84:0b3ab51c8877	1122
bogdanm	84:0b3ab51c8877	1123	/** @brief macro to get the USART2 clock source.
bogdanm	84:0b3ab51c8877	1124	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	1125	* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
bogdanm	84:0b3ab51c8877	1126	* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
bogdanm	84:0b3ab51c8877	1127	* @arg RCC_USART2CLKSOURCE_SYSCLK: System Clock selected as USART2 clock
bogdanm	84:0b3ab51c8877	1128	* @arg RCC_USART2CLKSOURCE_LSE: LSE selected as USART2 clock
bogdanm	84:0b3ab51c8877	1129	*/
bogdanm	84:0b3ab51c8877	1130	#define __HAL_RCC_GET_USART2_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_USART2SEL)))
bogdanm	84:0b3ab51c8877	1131
bogdanm	84:0b3ab51c8877	1132	/** @brief macro to configure the LPUART1 clock (LPUART1CLK).
bogdanm	84:0b3ab51c8877	1133	*
bogdanm	84:0b3ab51c8877	1134	* @param __LPUART1CLKSource__: specifies the LPUART1 clock source.
bogdanm	84:0b3ab51c8877	1135	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1136	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1137	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1138	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1139	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1140	*/
bogdanm	84:0b3ab51c8877	1141	#define __HAL_RCC_LPUART1_CONFIG(__LPUART1CLKSource__) \
bogdanm	84:0b3ab51c8877	1142	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPUART1SEL, (uint32_t)(__LPUART1CLKSource__))
bogdanm	84:0b3ab51c8877	1143
bogdanm	84:0b3ab51c8877	1144	/** @brief macro to get the LPUART1 clock source.
bogdanm	84:0b3ab51c8877	1145	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	1146	* @arg RCC_LPUART1CLKSOURCE_PCLK1: PCLK1 selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1147	* @arg RCC_LPUART1CLKSOURCE_HSI: HSI selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1148	* @arg RCC_LPUART1CLKSOURCE_SYSCLK: System Clock selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1149	* @arg RCC_LPUART1CLKSOURCE_LSE: LSE selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1150	*/
bogdanm	84:0b3ab51c8877	1151	#define __HAL_RCC_GET_LPUART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPUART1SEL)))
bogdanm	84:0b3ab51c8877	1152
bogdanm	84:0b3ab51c8877	1153	/** @brief macro to configure the LPTIM1 clock (LPTIM1CLK).
bogdanm	84:0b3ab51c8877	1154	*
bogdanm	84:0b3ab51c8877	1155	* @param __LPTIM1CLKSource__: specifies the LPTIM1 clock source.
bogdanm	84:0b3ab51c8877	1156	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1157	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPTIM1 clock
bogdanm	84:0b3ab51c8877	1158	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPTIM1 clock
bogdanm	84:0b3ab51c8877	1159	* @arg RCC_LPTIM1CLKSOURCE_HSI : LSI selected as LPTIM1 clock
bogdanm	84:0b3ab51c8877	1160	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPTIM1 clock
bogdanm	84:0b3ab51c8877	1161	*/
bogdanm	84:0b3ab51c8877	1162	#define __HAL_RCC_LPTIM1_CONFIG(__LPTIM1CLKSource__) \
bogdanm	84:0b3ab51c8877	1163	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL, (uint32_t)(__LPTIM1CLKSource__))
bogdanm	84:0b3ab51c8877	1164
bogdanm	84:0b3ab51c8877	1165	/** @brief macro to get the LPTIM1 clock source.
bogdanm	84:0b3ab51c8877	1166	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	1167	* @arg RCC_LPTIM1CLKSOURCE_PCLK: PCLK selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1168	* @arg RCC_LPTIM1CLKSOURCE_LSI : HSI selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1169	* @arg RCC_LPTIM1CLKSOURCE_HSI : System Clock selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1170	* @arg RCC_LPTIM1CLKSOURCE_LSE : LSE selected as LPUART1 clock
bogdanm	84:0b3ab51c8877	1171	*/
bogdanm	84:0b3ab51c8877	1172	#define __HAL_RCC_GET_LPTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_LPTIM1SEL)))
bogdanm	84:0b3ab51c8877	1173
Kojto	96:487b796308b0	1174	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	84:0b3ab51c8877	1175	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	84:0b3ab51c8877	1176	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	84:0b3ab51c8877	1177	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1178	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	84:0b3ab51c8877	1179	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	84:0b3ab51c8877	1180	*/
bogdanm	84:0b3ab51c8877	1181	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	84:0b3ab51c8877	1182	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__USBCLKSource__))
bogdanm	84:0b3ab51c8877	1183
bogdanm	84:0b3ab51c8877	1184	/** @brief Macro to get the USB clock source.
bogdanm	84:0b3ab51c8877	1185	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	1186	* @arg RCC_USBCLKSOURCE_HSI48: HSI48 selected as USB clock
bogdanm	84:0b3ab51c8877	1187	* @arg RCC_USBCLKSOURCE_PLLCLK: PLL Clock selected as USB clock
bogdanm	84:0b3ab51c8877	1188	*/
bogdanm	84:0b3ab51c8877	1189	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	84:0b3ab51c8877	1190
bogdanm	84:0b3ab51c8877	1191	/** @brief Macro to configure the RNG clock (RNGCLK).
bogdanm	84:0b3ab51c8877	1192	* @param __RNGCLKSource__: specifies the USB clock source.
bogdanm	84:0b3ab51c8877	1193	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1194	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
bogdanm	84:0b3ab51c8877	1195	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
bogdanm	84:0b3ab51c8877	1196	*/
bogdanm	84:0b3ab51c8877	1197	#define __HAL_RCC_RNG_CONFIG(__RNGCLKSource__) \
bogdanm	84:0b3ab51c8877	1198	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__RNGCLKSource__))
bogdanm	84:0b3ab51c8877	1199
bogdanm	84:0b3ab51c8877	1200	/** @brief Macro to get the RNG clock source.
bogdanm	84:0b3ab51c8877	1201	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	1202	* @arg RCC_RNGCLKSOURCE_HSI48: HSI48 selected as RNG clock
bogdanm	84:0b3ab51c8877	1203	* @arg RCC_RNGCLKSOURCE_PLLCLK: PLL Clock selected as RNG clock
bogdanm	84:0b3ab51c8877	1204	*/
bogdanm	84:0b3ab51c8877	1205	#define __HAL_RCC_GET_RNG_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
bogdanm	84:0b3ab51c8877	1206
bogdanm	84:0b3ab51c8877	1207	/** @brief macro to select the HSI48M clock source
bogdanm	84:0b3ab51c8877	1208	* @note This macro can be replaced by either __HAL_RCC_RNG_CONFIG or
bogdanm	84:0b3ab51c8877	1209	* __HAL_RCC_USB_CONFIG to configure respectively RNG or UBS clock sources.
bogdanm	84:0b3ab51c8877	1210	*
bogdanm	84:0b3ab51c8877	1211	* @param __HSI48MCLKSource__: specifies the HSI48M clock source dedicated for
bogdanm	84:0b3ab51c8877	1212	* USB an RNG peripherals.
bogdanm	84:0b3ab51c8877	1213	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1214	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
Kojto	96:487b796308b0	1215	* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
bogdanm	84:0b3ab51c8877	1216	*/
bogdanm	84:0b3ab51c8877	1217	#define __HAL_RCC_HSI48M_CONFIG(__HSI48MCLKSource__) \
bogdanm	84:0b3ab51c8877	1218	MODIFY_REG(RCC->CCIPR, RCC_CCIPR_HSI48SEL, (uint32_t)(__HSI48MCLKSource__))
bogdanm	84:0b3ab51c8877	1219
bogdanm	84:0b3ab51c8877	1220	/** @brief macro to get the HSI48M clock source.
bogdanm	84:0b3ab51c8877	1221	* @note This macro can be replaced by either __HAL_RCC_GET_RNG_SOURCE or
bogdanm	84:0b3ab51c8877	1222	* __HAL_RCC_GET_USB_SOURCE to get respectively RNG or UBS clock sources.
bogdanm	84:0b3ab51c8877	1223	* @retval The clock source can be one of the following values:
bogdanm	84:0b3ab51c8877	1224	* @arg RCC_HSI48M_PLL: A dedicated 48MHZ PLL output.
Kojto	96:487b796308b0	1225	* @arg RCC_HSI48M_HSI48: 48MHZ issued from internal HSI48 oscillator.
bogdanm	84:0b3ab51c8877	1226	*/
bogdanm	84:0b3ab51c8877	1227	#define __HAL_RCC_GET_HSI48M_SOURCE() ((uint32_t)(READ_BIT(RCC->CCIPR, RCC_CCIPR_HSI48SEL)))
Kojto	96:487b796308b0	1228	#endif /* !(STM32L031xx ) && !(STM32L041xx ) && !(STM32L051xx ) && !(STM32L061xx ) && !(STM32L071xx ) && !(STM32L081xx ) */
bogdanm	84:0b3ab51c8877	1229
bogdanm	84:0b3ab51c8877	1230	/**
bogdanm	84:0b3ab51c8877	1231	* @brief Macros to enable or disable the force of the Internal High Speed oscillator (HSI)
bogdanm	84:0b3ab51c8877	1232	* in STOP mode to be quickly available as kernel clock for USART and I2C.
bogdanm	84:0b3ab51c8877	1233	* @note The Enable of this function has not effect on the HSION bit.
bogdanm	84:0b3ab51c8877	1234	* This parameter can be: ENABLE or DISABLE.
bogdanm	84:0b3ab51c8877	1235	* @retval None
bogdanm	84:0b3ab51c8877	1236	*/
bogdanm	84:0b3ab51c8877	1237	#define __HAL_RCC_HSISTOP_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	84:0b3ab51c8877	1238	#define __HAL_RCC_HSISTOP_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON)
bogdanm	84:0b3ab51c8877	1239
bogdanm	84:0b3ab51c8877	1240	/**
bogdanm	84:0b3ab51c8877	1241	* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
bogdanm	84:0b3ab51c8877	1242	* @param RCC_LSEDrive: specifies the new state of the LSE drive capability.
bogdanm	84:0b3ab51c8877	1243	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1244	* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
bogdanm	84:0b3ab51c8877	1245	* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
bogdanm	84:0b3ab51c8877	1246	* @arg RCC_LSEDRIVE_MEDIUMHIGH: LSE oscillator medium high drive capability.
bogdanm	84:0b3ab51c8877	1247	* @arg RCC_LSEDRIVE_HIGH: LSE oscillator high drive capability.
bogdanm	84:0b3ab51c8877	1248	* @retval None
bogdanm	84:0b3ab51c8877	1249	*/
bogdanm	84:0b3ab51c8877	1250	#define __HAL_RCC_LSEDRIVE_CONFIG(__RCC_LSEDrive__) (MODIFY_REG(RCC->CSR,\
bogdanm	84:0b3ab51c8877	1251	RCC_CSR_LSEDRV, (uint32_t)(__RCC_LSEDrive__) ))
bogdanm	84:0b3ab51c8877	1252
bogdanm	84:0b3ab51c8877	1253	/**
bogdanm	84:0b3ab51c8877	1254	* @brief Macro to configures the wake up from stop clock.
bogdanm	84:0b3ab51c8877	1255	* @param RCC_STOPWUCLK: specifies the clock source used after wake up from stop
bogdanm	84:0b3ab51c8877	1256	* This parameter can be one of the following values:
Kojto	96:487b796308b0	1257	* @arg RCC_STOP_WAKEUPCLOCK_MSI: MSI selected as system clock source
Kojto	96:487b796308b0	1258	* @arg RCC_STOP_WAKEUPCLOCK_HSI: HSI selected as system clock source
bogdanm	84:0b3ab51c8877	1259	* @retval None
bogdanm	84:0b3ab51c8877	1260	*/
bogdanm	84:0b3ab51c8877	1261	#define __HAL_RCC_WAKEUPSTOP_CLK_CONFIG(__RCC_STOPWUCLK__) (MODIFY_REG(RCC->CFGR,\
bogdanm	84:0b3ab51c8877	1262	RCC_CFGR_STOPWUCK, (uint32_t)(__RCC_STOPWUCLK__) ))
bogdanm	84:0b3ab51c8877	1263
Kojto	96:487b796308b0	1264	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	84:0b3ab51c8877	1265	/**
bogdanm	84:0b3ab51c8877	1266	* @brief Enables the specified CRS interrupts.
bogdanm	84:0b3ab51c8877	1267	* @param __INTERRUPT__: specifies the CRS interrupt sources to be enabled.
bogdanm	84:0b3ab51c8877	1268	* This parameter can be any combination of the following values:
bogdanm	84:0b3ab51c8877	1269	* @arg RCC_CRS_IT_SYNCOK
bogdanm	84:0b3ab51c8877	1270	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	84:0b3ab51c8877	1271	* @arg RCC_CRS_IT_ERR
bogdanm	84:0b3ab51c8877	1272	* @arg RCC_CRS_IT_ESYNC
bogdanm	84:0b3ab51c8877	1273	* @retval None
bogdanm	84:0b3ab51c8877	1274	*/
bogdanm	84:0b3ab51c8877	1275	#define __HAL_RCC_CRS_ENABLE_IT(__INTERRUPT__) (CRS->CR \|= (__INTERRUPT__))
bogdanm	84:0b3ab51c8877	1276
bogdanm	84:0b3ab51c8877	1277	/**
bogdanm	84:0b3ab51c8877	1278	* @brief Disables the specified CRS interrupts.
bogdanm	84:0b3ab51c8877	1279	* @param __INTERRUPT__: specifies the CRS interrupt sources to be disabled.
bogdanm	84:0b3ab51c8877	1280	* This parameter can be any combination of the following values:
bogdanm	84:0b3ab51c8877	1281	* @arg RCC_CRS_IT_SYNCOK
bogdanm	84:0b3ab51c8877	1282	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	84:0b3ab51c8877	1283	* @arg RCC_CRS_IT_ERR
bogdanm	84:0b3ab51c8877	1284	* @arg RCC_CRS_IT_ESYNC
bogdanm	84:0b3ab51c8877	1285	* @retval None
bogdanm	84:0b3ab51c8877	1286	*/
bogdanm	84:0b3ab51c8877	1287	#define __HAL_RCC_CRS_DISABLE_IT(__INTERRUPT__) (CRS->CR &= ~(__INTERRUPT__))
bogdanm	84:0b3ab51c8877	1288
Kojto	96:487b796308b0	1289	/** @brief Check the CRS interrupt has occurred or not.
bogdanm	84:0b3ab51c8877	1290	* @param __INTERRUPT__: specifies the CRS interrupt source to check.
bogdanm	84:0b3ab51c8877	1291	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1292	* @arg RCC_CRS_IT_SYNCOK
bogdanm	84:0b3ab51c8877	1293	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	84:0b3ab51c8877	1294	* @arg RCC_CRS_IT_ERR
bogdanm	84:0b3ab51c8877	1295	* @arg RCC_CRS_IT_ESYNC
bogdanm	84:0b3ab51c8877	1296	* @retval The new state of __INTERRUPT__ (SET or RESET).
bogdanm	84:0b3ab51c8877	1297	*/
bogdanm	84:0b3ab51c8877	1298	#define __HAL_RCC_CRS_GET_IT_SOURCE(__INTERRUPT__) ((CRS->CR & (__INTERRUPT__))? SET : RESET)
bogdanm	84:0b3ab51c8877	1299
Kojto	96:487b796308b0	1300	/** @brief Clear the CRS interrupt pending bits
bogdanm	84:0b3ab51c8877	1301	* bits to clear the selected interrupt pending bits.
bogdanm	84:0b3ab51c8877	1302	* @param __INTERRUPT__: specifies the interrupt pending bit to clear.
bogdanm	84:0b3ab51c8877	1303	* This parameter can be any combination of the following values:
bogdanm	84:0b3ab51c8877	1304	* @arg RCC_CRS_IT_SYNCOK
bogdanm	84:0b3ab51c8877	1305	* @arg RCC_CRS_IT_SYNCWARN
bogdanm	84:0b3ab51c8877	1306	* @arg RCC_CRS_IT_ERR
bogdanm	84:0b3ab51c8877	1307	* @arg RCC_CRS_IT_ESYNC
bogdanm	84:0b3ab51c8877	1308	* @arg RCC_CRS_IT_TRIMOVF
bogdanm	84:0b3ab51c8877	1309	* @arg RCC_CRS_IT_SYNCERR
bogdanm	84:0b3ab51c8877	1310	* @arg RCC_CRS_IT_SYNCMISS
bogdanm	84:0b3ab51c8877	1311	*/
bogdanm	84:0b3ab51c8877	1312	/* CRS IT Error Mask */
Kojto	96:487b796308b0	1313	#define RCC_CRS_IT_ERROR_MASK ((uint32_t)(RCC_CRS_IT_TRIMOVF \| RCC_CRS_IT_SYNCERR \| RCC_CRS_IT_SYNCMISS))
bogdanm	84:0b3ab51c8877	1314
bogdanm	84:0b3ab51c8877	1315	#define __HAL_RCC_CRS_CLEAR_IT(__INTERRUPT__) ((((__INTERRUPT__) & RCC_CRS_IT_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	92:4fc01daae5a5	1316	(CRS->ICR = (__INTERRUPT__)))
bogdanm	84:0b3ab51c8877	1317
bogdanm	84:0b3ab51c8877	1318	/**
bogdanm	84:0b3ab51c8877	1319	* @brief Checks whether the specified CRS flag is set or not.
bogdanm	84:0b3ab51c8877	1320	* @param _FLAG_: specifies the flag to check.
bogdanm	84:0b3ab51c8877	1321	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1322	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	84:0b3ab51c8877	1323	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	84:0b3ab51c8877	1324	* @arg RCC_CRS_FLAG_ERR
bogdanm	84:0b3ab51c8877	1325	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	84:0b3ab51c8877	1326	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	84:0b3ab51c8877	1327	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	84:0b3ab51c8877	1328	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	84:0b3ab51c8877	1329	* @retval The new state of _FLAG_ (TRUE or FALSE).
bogdanm	84:0b3ab51c8877	1330	*/
Kojto	96:487b796308b0	1331	#define __HAL_RCC_CRS_GET_FLAG(__FLAG__) ((CRS->ISR & (__FLAG__)) == (__FLAG__))
bogdanm	84:0b3ab51c8877	1332
bogdanm	84:0b3ab51c8877	1333	/**
bogdanm	84:0b3ab51c8877	1334	* @brief Clears the CRS specified FLAG.
bogdanm	84:0b3ab51c8877	1335	* @param _FLAG_: specifies the flag to clear.
bogdanm	84:0b3ab51c8877	1336	* This parameter can be one of the following values:
bogdanm	84:0b3ab51c8877	1337	* @arg RCC_CRS_FLAG_SYNCOK
bogdanm	84:0b3ab51c8877	1338	* @arg RCC_CRS_FLAG_SYNCWARN
bogdanm	84:0b3ab51c8877	1339	* @arg RCC_CRS_FLAG_ERR
bogdanm	84:0b3ab51c8877	1340	* @arg RCC_CRS_FLAG_ESYNC
bogdanm	84:0b3ab51c8877	1341	* @arg RCC_CRS_FLAG_TRIMOVF
bogdanm	84:0b3ab51c8877	1342	* @arg RCC_CRS_FLAG_SYNCERR
bogdanm	84:0b3ab51c8877	1343	* @arg RCC_CRS_FLAG_SYNCMISS
bogdanm	84:0b3ab51c8877	1344	* @retval None
bogdanm	84:0b3ab51c8877	1345	*/
bogdanm	84:0b3ab51c8877	1346
bogdanm	84:0b3ab51c8877	1347	/* CRS Flag Error Mask */
Kojto	96:487b796308b0	1348	#define RCC_CRS_FLAG_ERROR_MASK ((uint32_t)(RCC_CRS_FLAG_TRIMOVF \| RCC_CRS_FLAG_SYNCERR \| RCC_CRS_FLAG_SYNCMISS))
bogdanm	84:0b3ab51c8877	1349
bogdanm	84:0b3ab51c8877	1350	#define __HAL_RCC_CRS_CLEAR_FLAG(__FLAG__) ((((__FLAG__) & RCC_CRS_FLAG_ERROR_MASK)!= 0) ? (CRS->ICR \|= CRS_ICR_ERRC) : \
bogdanm	92:4fc01daae5a5	1351	(CRS->ICR = (__FLAG__)))
bogdanm	84:0b3ab51c8877	1352
bogdanm	84:0b3ab51c8877	1353
bogdanm	84:0b3ab51c8877	1354	/**
bogdanm	84:0b3ab51c8877	1355	* @brief Enables the oscillator clock for frequency error counter.
bogdanm	84:0b3ab51c8877	1356	* @note when the CEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	84:0b3ab51c8877	1357	* @param None
bogdanm	84:0b3ab51c8877	1358	* @retval None
bogdanm	84:0b3ab51c8877	1359	*/
bogdanm	84:0b3ab51c8877	1360	#define __HAL_RCC_CRS_ENABLE_FREQ_ERROR_COUNTER() (CRS->CR \|= CRS_CR_CEN)
bogdanm	84:0b3ab51c8877	1361
bogdanm	84:0b3ab51c8877	1362	/**
bogdanm	84:0b3ab51c8877	1363	* @brief Disables the oscillator clock for frequency error counter.
bogdanm	84:0b3ab51c8877	1364	* @param None
bogdanm	84:0b3ab51c8877	1365	* @retval None
bogdanm	84:0b3ab51c8877	1366	*/
bogdanm	84:0b3ab51c8877	1367	#define __HAL_RCC_CRS_DISABLE_FREQ_ERROR_COUNTER() (CRS->CR &= ~CRS_CR_CEN)
bogdanm	84:0b3ab51c8877	1368
bogdanm	84:0b3ab51c8877	1369	/**
bogdanm	84:0b3ab51c8877	1370	* @brief Enables the automatic hardware adjustment of TRIM bits.
bogdanm	84:0b3ab51c8877	1371	* @note When the AUTOTRIMEN bit is set the CRS_CFGR register becomes write-protected.
bogdanm	84:0b3ab51c8877	1372	* @param None
bogdanm	84:0b3ab51c8877	1373	* @retval None
bogdanm	84:0b3ab51c8877	1374	*/
bogdanm	84:0b3ab51c8877	1375	#define __HAL_RCC_CRS_ENABLE_AUTOMATIC_CALIB() (CRS->CR \|= CRS_CR_AUTOTRIMEN)
bogdanm	84:0b3ab51c8877	1376
bogdanm	84:0b3ab51c8877	1377	/**
bogdanm	84:0b3ab51c8877	1378	* @brief Enables or disables the automatic hardware adjustment of TRIM bits.
bogdanm	84:0b3ab51c8877	1379	* @param None
bogdanm	84:0b3ab51c8877	1380	* @retval None
bogdanm	84:0b3ab51c8877	1381	*/
bogdanm	84:0b3ab51c8877	1382	#define __HAL_RCC_CRS_DISABLE_AUTOMATIC_CALIB() (CRS->CR &= ~CRS_CR_AUTOTRIMEN)
bogdanm	84:0b3ab51c8877	1383
bogdanm	84:0b3ab51c8877	1384	/**
bogdanm	84:0b3ab51c8877	1385	* @brief Macro to calculate reload value to be set in CRS register according to target and sync frequencies
bogdanm	84:0b3ab51c8877	1386	* @note The RELOAD value should be selected according to the ratio between the target frequency and the frequency
bogdanm	84:0b3ab51c8877	1387	* of the synchronization source after prescaling. It is then decreased by one in order to
bogdanm	84:0b3ab51c8877	1388	* reach the expected synchronization on the zero value. The formula is the following:
bogdanm	84:0b3ab51c8877	1389	* RELOAD = (fTARGET / fSYNC) -1
bogdanm	84:0b3ab51c8877	1390	* @param _FTARGET_ Target frequency (value in Hz)
bogdanm	84:0b3ab51c8877	1391	* @param _FSYNC_ Synchronization signal frequency (value in Hz)
bogdanm	84:0b3ab51c8877	1392	* @retval None
bogdanm	84:0b3ab51c8877	1393	*/
Kojto	96:487b796308b0	1394	#define __HAL_RCC_CRS_CALCULATE_RELOADVALUE(__FTARGET__, __FSYNC__) (((__FTARGET__) / (__FSYNC__)) - 1)
Kojto	96:487b796308b0	1395
Kojto	96:487b796308b0	1396	#endif /* !(STM32L031xx) && !(STM32L041xx) && !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto	96:487b796308b0	1397
Kojto	96:487b796308b0	1398	#if defined(STM32L073xx) \|\| defined(STM32L083xx) \|\| \
Kojto	96:487b796308b0	1399	defined(STM32L072xx) \|\| defined(STM32L082xx) \|\| \
Kojto	96:487b796308b0	1400	defined(STM32L071xx) \|\| defined(STM32L081xx)
Kojto	96:487b796308b0	1401	/** @brief Enable or disable the HSI OUT .
Kojto	96:487b796308b0	1402	* @note After reset, the HSI output is not available
Kojto	96:487b796308b0	1403	*/
Kojto	96:487b796308b0	1404
Kojto	96:487b796308b0	1405	#define __HAL_RCC_HSI_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSIOUTEN)
Kojto	96:487b796308b0	1406	#define __HAL_RCC_HSI_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSIOUTEN)
Kojto	96:487b796308b0	1407
Kojto	96:487b796308b0	1408	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	1409	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	1410	/* STM32L073xx \|\| STM32L083xx */
Kojto	96:487b796308b0	1411
Kojto	96:487b796308b0	1412	#if defined(STM32L053xx) \|\| defined(STM32L063xx) \|\| defined(STM32L073xx) \|\| defined(STM32L083xx) \|\|\
Kojto	96:487b796308b0	1413	defined(STM32L052xx) \|\| defined(STM32L062xx) \|\| defined(STM32L072xx) \|\| defined(STM32L082xx)
bogdanm	84:0b3ab51c8877	1414
Kojto	96:487b796308b0	1415	/**
Kojto	96:487b796308b0	1416	* @brief Macro to enable or disable the Internal High Speed oscillator for USB (HSI48).
Kojto	96:487b796308b0	1417	* @note After enabling the HSI48, the application software should wait on
Kojto	96:487b796308b0	1418	* HSI48RDY flag to be set indicating that HSI48 clock is stable and can
Kojto	96:487b796308b0	1419	* be used to clock the USB.
Kojto	96:487b796308b0	1420	* @note The HSI48 is stopped by hardware when entering STOP and STANDBY modes.
Kojto	96:487b796308b0	1421	*/
Kojto	96:487b796308b0	1422	#define __HAL_RCC_HSI48_ENABLE() do { SET_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
Kojto	96:487b796308b0	1423	RCC->APB2ENR \|= RCC_APB2ENR_SYSCFGEN; \
Kojto	96:487b796308b0	1424	SYSCFG->CFGR3 \|= (SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT); \
Kojto	96:487b796308b0	1425	} while (0)
Kojto	96:487b796308b0	1426	#define __HAL_RCC_HSI48_DISABLE() do { CLEAR_BIT(RCC->CRRCR, RCC_CRRCR_HSI48ON); \
Kojto	96:487b796308b0	1427	SYSCFG->CFGR3 &= (uint32_t)~((uint32_t)(SYSCFG_CFGR3_ENREF_HSI48 \| SYSCFG_CFGR3_EN_VREFINT)); \
Kojto	96:487b796308b0	1428	} while (0)
Kojto	96:487b796308b0	1429	/** @brief Enable or disable the HSI48M DIV6 OUT .
Kojto	96:487b796308b0	1430	* @note After reset, the HSI48Mhz (divided by 6) output is not available
Kojto	96:487b796308b0	1431	*/
bogdanm	84:0b3ab51c8877	1432
Kojto	96:487b796308b0	1433	#define __HAL_RCC_HSI48M_DIV6_OUT_ENABLE() SET_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
Kojto	96:487b796308b0	1434	#define __HAL_RCC_HSI48M_DIV6_OUT_DISABLE() CLEAR_BIT(RCC->CR, RCC_CRRCR_HSI48DIV6OUTEN)
Kojto	96:487b796308b0	1435
Kojto	96:487b796308b0	1436	#endif /* STM32L071xx \|\| STM32L081xx \|\| */
Kojto	96:487b796308b0	1437	/* STM32L072xx \|\| STM32L082xx \|\| */
Kojto	96:487b796308b0	1438	/* STM32L073xx \|\| STM32L083xx */
Kojto	96:487b796308b0	1439
bogdanm	84:0b3ab51c8877	1440	/**
bogdanm	84:0b3ab51c8877	1441	* @}
bogdanm	84:0b3ab51c8877	1442	*/
bogdanm	84:0b3ab51c8877	1443
Kojto	96:487b796308b0	1444	/** @defgroup RCCEx_Exported_Functions RCCEx Exported Functions
Kojto	96:487b796308b0	1445	* @{
Kojto	96:487b796308b0	1446	*/
Kojto	96:487b796308b0	1447
Kojto	96:487b796308b0	1448	/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
Kojto	96:487b796308b0	1449
Kojto	96:487b796308b0	1450	* @{
Kojto	96:487b796308b0	1451	*/
bogdanm	84:0b3ab51c8877	1452	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	96:487b796308b0	1453	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
Kojto	96:487b796308b0	1454	void HAL_RCCEx_EnableLSECSS(void);
Kojto	96:487b796308b0	1455	void HAL_RCCEx_DisableLSECSS(void);
Kojto	96:487b796308b0	1456	#if !defined(STM32L031xx) && !defined(STM32L041xx) && !defined(STM32L051xx) && !defined(STM32L061xx) && !defined(STM32L071xx) && !defined(STM32L081xx)
bogdanm	84:0b3ab51c8877	1457	void HAL_RCCEx_CRSConfig(RCC_CRSInitTypeDef *pInit);
bogdanm	84:0b3ab51c8877	1458	void HAL_RCCEx_CRSSoftwareSynchronizationGenerate(void);
bogdanm	84:0b3ab51c8877	1459	void HAL_RCCEx_CRSGetSynchronizationInfo(RCC_CRSSynchroInfoTypeDef *pSynchroInfo);
Kojto	96:487b796308b0	1460	uint32_t HAL_RCCEx_CRSWaitSynchronization(uint32_t Timeout);
Kojto	96:487b796308b0	1461	void HAL_RCCEx_EnableHSI48_VREFINT(void);
Kojto	96:487b796308b0	1462	void HAL_RCCEx_DisableHSI48_VREFINT(void);
Kojto	96:487b796308b0	1463	#endif /* !(STM32L051xx) && !(STM32L061xx) && !(STM32L071xx) && !(STM32L081xx) */
Kojto	96:487b796308b0	1464
Kojto	96:487b796308b0	1465	/**
Kojto	96:487b796308b0	1466	* @}
Kojto	96:487b796308b0	1467	*/
Kojto	96:487b796308b0	1468	/**
Kojto	96:487b796308b0	1469	* @}
Kojto	96:487b796308b0	1470	*/
Kojto	96:487b796308b0	1471
bogdanm	84:0b3ab51c8877	1472	/**
bogdanm	84:0b3ab51c8877	1473	* @}
bogdanm	84:0b3ab51c8877	1474	*/
bogdanm	84:0b3ab51c8877	1475
bogdanm	84:0b3ab51c8877	1476	/**
bogdanm	84:0b3ab51c8877	1477	* @}
bogdanm	84:0b3ab51c8877	1478	*/
bogdanm	84:0b3ab51c8877	1479
bogdanm	84:0b3ab51c8877	1480	#ifdef __cplusplus
bogdanm	84:0b3ab51c8877	1481	}
bogdanm	84:0b3ab51c8877	1482	#endif
bogdanm	84:0b3ab51c8877	1483
bogdanm	84:0b3ab51c8877	1484	#endif /* __STM32L0xx_HAL_RCC_EX_H */
bogdanm	84:0b3ab51c8877	1485
bogdanm	84:0b3ab51c8877	1486	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	96:487b796308b0	1487

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
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Followers:	1

TARGET_NUCLEO_L053R8/stm32l0xx_hal_rcc_ex.h@97:4298809c7c9e, 2015-04-08 (annotated)

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