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TARGET_NUCLEO_L053R8/stm32l0xx_hal_iwdg.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:
filartrix
Date:
Wed Apr 08 14:12:53 2015 +0000
Revision:
97:4298809c7c9e
Parent:
96:487b796308b0 
First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 84:0b3ab51c8877 1 /**
bogdanm 84:0b3ab51c8877 2 ******************************************************************************
bogdanm 84:0b3ab51c8877 3 * @file stm32l0xx_hal_iwdg.h
bogdanm 84:0b3ab51c8877 4 * @author MCD Application Team
Kojto 96:487b796308b0 5 * @version V1.2.0
Kojto 96:487b796308b0 6 * @date 06-February-2015
bogdanm 84:0b3ab51c8877 7 * @brief Header file of IWDG HAL module.
bogdanm 84:0b3ab51c8877 8 ******************************************************************************
bogdanm 84:0b3ab51c8877 9 * @attention
bogdanm 84:0b3ab51c8877 10 *
Kojto 96:487b796308b0 11 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
bogdanm 84:0b3ab51c8877 12 *
bogdanm 84:0b3ab51c8877 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 84:0b3ab51c8877 14 * are permitted provided that the following conditions are met:
bogdanm 84:0b3ab51c8877 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 84:0b3ab51c8877 16 * this list of conditions and the following disclaimer.
bogdanm 84:0b3ab51c8877 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 84:0b3ab51c8877 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 84:0b3ab51c8877 19 * and/or other materials provided with the distribution.
bogdanm 84:0b3ab51c8877 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 84:0b3ab51c8877 21 * may be used to endorse or promote products derived from this software
bogdanm 84:0b3ab51c8877 22 * without specific prior written permission.
bogdanm 84:0b3ab51c8877 23 *
bogdanm 84:0b3ab51c8877 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 84:0b3ab51c8877 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 84:0b3ab51c8877 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 84:0b3ab51c8877 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 84:0b3ab51c8877 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 84:0b3ab51c8877 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 84:0b3ab51c8877 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 84:0b3ab51c8877 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 84:0b3ab51c8877 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 84:0b3ab51c8877 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 84:0b3ab51c8877 34 *
bogdanm 84:0b3ab51c8877 35 ******************************************************************************
bogdanm 84:0b3ab51c8877 36 */
bogdanm 84:0b3ab51c8877 37
bogdanm 84:0b3ab51c8877 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 84:0b3ab51c8877 39 #ifndef __STM32L0xx_HAL_IWDG_H
bogdanm 84:0b3ab51c8877 40 #define __STM32L0xx_HAL_IWDG_H
bogdanm 84:0b3ab51c8877 41
bogdanm 84:0b3ab51c8877 42 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 43 extern "C" {
bogdanm 84:0b3ab51c8877 44 #endif
bogdanm 84:0b3ab51c8877 45
bogdanm 84:0b3ab51c8877 46 /* Includes ------------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 47 #include "stm32l0xx_hal_def.h"
bogdanm 84:0b3ab51c8877 48
bogdanm 84:0b3ab51c8877 49 /** @addtogroup STM32L0xx_HAL_Driver
bogdanm 84:0b3ab51c8877 50 * @{
bogdanm 84:0b3ab51c8877 51 */
bogdanm 84:0b3ab51c8877 52
Kojto 96:487b796308b0 53 /** @defgroup IWDG
bogdanm 84:0b3ab51c8877 54 * @{
bogdanm 84:0b3ab51c8877 55 */
bogdanm 84:0b3ab51c8877 56
bogdanm 84:0b3ab51c8877 57 /* Exported types ------------------------------------------------------------*/
bogdanm 84:0b3ab51c8877 58
bogdanm 92:4fc01daae5a5 59 /** @defgroup IWDG_Exported_Types IWDG Exported Types
bogdanm 92:4fc01daae5a5 60 * @{
bogdanm 92:4fc01daae5a5 61 */
bogdanm 92:4fc01daae5a5 62
Kojto 96:487b796308b0 63 /** @defgroup IWDG_State IWDG state definition
Kojto 96:487b796308b0 64 * @{
Kojto 96:487b796308b0 65 */
bogdanm 84:0b3ab51c8877 66 /**
bogdanm 84:0b3ab51c8877 67 * @brief IWDG HAL State Structure definition
bogdanm 84:0b3ab51c8877 68 */
bogdanm 84:0b3ab51c8877 69 typedef enum
bogdanm 84:0b3ab51c8877 70 {
bogdanm 84:0b3ab51c8877 71 HAL_IWDG_STATE_RESET = 0x00, /*!< IWDG not yet initialized or disabled */
bogdanm 84:0b3ab51c8877 72 HAL_IWDG_STATE_READY = 0x01, /*!< IWDG initialized and ready for use */
bogdanm 84:0b3ab51c8877 73 HAL_IWDG_STATE_BUSY = 0x02, /*!< IWDG internal process is ongoing */
bogdanm 84:0b3ab51c8877 74 HAL_IWDG_STATE_TIMEOUT = 0x03, /*!< IWDG timeout state */
bogdanm 84:0b3ab51c8877 75 HAL_IWDG_STATE_ERROR = 0x04 /*!< IWDG error state */
bogdanm 84:0b3ab51c8877 76
bogdanm 84:0b3ab51c8877 77 }HAL_IWDG_StateTypeDef;
Kojto 96:487b796308b0 78 /**
Kojto 96:487b796308b0 79 * @}
Kojto 96:487b796308b0 80 */
Kojto 96:487b796308b0 81 /** @defgroup IWDG_Init IWDG init configuration structure
Kojto 96:487b796308b0 82 * @{
Kojto 96:487b796308b0 83 */
bogdanm 84:0b3ab51c8877 84 /**
bogdanm 84:0b3ab51c8877 85 * @brief IWDG Init structure definition
bogdanm 84:0b3ab51c8877 86 */
bogdanm 84:0b3ab51c8877 87 typedef struct
bogdanm 84:0b3ab51c8877 88 {
bogdanm 84:0b3ab51c8877 89 uint32_t Prescaler; /*!< Select the prescaler of the IWDG.
bogdanm 84:0b3ab51c8877 90 This parameter can be a value of @ref IWDG_Prescaler */
bogdanm 84:0b3ab51c8877 91
bogdanm 84:0b3ab51c8877 92 uint32_t Reload; /*!< Specifies the IWDG down-counter reload value.
bogdanm 84:0b3ab51c8877 93 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
bogdanm 84:0b3ab51c8877 94
bogdanm 84:0b3ab51c8877 95 uint32_t Window; /*!< Specifies the window value to be compared to the down-counter.
bogdanm 84:0b3ab51c8877 96 This parameter must be a number between Min_Data = 0 and Max_Data = 0x0FFF */
bogdanm 84:0b3ab51c8877 97
bogdanm 84:0b3ab51c8877 98 } IWDG_InitTypeDef;
Kojto 96:487b796308b0 99 /**
Kojto 96:487b796308b0 100 * @}
Kojto 96:487b796308b0 101 */
bogdanm 84:0b3ab51c8877 102
Kojto 96:487b796308b0 103 /** @defgroup IWDG_handle IWDG handler
Kojto 96:487b796308b0 104 * @{
Kojto 96:487b796308b0 105 */
bogdanm 84:0b3ab51c8877 106 /**
bogdanm 92:4fc01daae5a5 107 * @brief IWDG Handle Structure definition
bogdanm 84:0b3ab51c8877 108 */
bogdanm 84:0b3ab51c8877 109 typedef struct
bogdanm 84:0b3ab51c8877 110 {
bogdanm 84:0b3ab51c8877 111 IWDG_TypeDef *Instance; /*!< Register base address */
bogdanm 84:0b3ab51c8877 112
bogdanm 84:0b3ab51c8877 113 IWDG_InitTypeDef Init; /*!< IWDG required parameters */
bogdanm 84:0b3ab51c8877 114
bogdanm 92:4fc01daae5a5 115 HAL_LockTypeDef Lock; /*!< IWDG Locking object */
bogdanm 84:0b3ab51c8877 116
bogdanm 84:0b3ab51c8877 117 __IO HAL_IWDG_StateTypeDef State; /*!< IWDG communication state */
bogdanm 84:0b3ab51c8877 118
bogdanm 84:0b3ab51c8877 119 }IWDG_HandleTypeDef;
bogdanm 84:0b3ab51c8877 120
bogdanm 92:4fc01daae5a5 121 /**
bogdanm 92:4fc01daae5a5 122 * @}
bogdanm 92:4fc01daae5a5 123 */
bogdanm 92:4fc01daae5a5 124
Kojto 96:487b796308b0 125 /**
Kojto 96:487b796308b0 126 * @}
Kojto 96:487b796308b0 127 */
Kojto 96:487b796308b0 128
bogdanm 84:0b3ab51c8877 129 /* Exported constants --------------------------------------------------------*/
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 /** @defgroup IWDG_Exported_Constants IWDG Exported Constants
bogdanm 84:0b3ab51c8877 132 * @{
bogdanm 84:0b3ab51c8877 133 */
bogdanm 84:0b3ab51c8877 134
Kojto 96:487b796308b0 135 /** @defgroup IWDG_Registers_Key IWDG key
bogdanm 84:0b3ab51c8877 136 * @brief IWDG registers bit mask
bogdanm 84:0b3ab51c8877 137 * @{
bogdanm 84:0b3ab51c8877 138 */
bogdanm 84:0b3ab51c8877 139 /* --- KR Register ---*/
bogdanm 84:0b3ab51c8877 140 /* KR register bit mask */
Kojto 96:487b796308b0 141 #define IWDG_KEY_RELOAD ((uint32_t)0xAAAA) /*!< IWDG Reload Counter Enable */
Kojto 96:487b796308b0 142 #define IWDG_KEY_ENABLE ((uint32_t)0xCCCC) /*!< IWDG Peripheral Enable */
Kojto 96:487b796308b0 143 #define IWDG_KEY_WRITE_ACCESS_ENABLE ((uint32_t)0x5555) /*!< IWDG KR Write Access Enable */
Kojto 96:487b796308b0 144 #define IWDG_KEY_WRITE_ACCESS_DISABLE ((uint32_t)0x0000) /*!< IWDG KR Write Access Disable */
bogdanm 84:0b3ab51c8877 145 /**
bogdanm 84:0b3ab51c8877 146 * @}
bogdanm 84:0b3ab51c8877 147 */
bogdanm 84:0b3ab51c8877 148
Kojto 96:487b796308b0 149 #define IS_IWDG_KR(__KR__) (((__KR__) == IWDG_KEY_RELOAD) || \
Kojto 96:487b796308b0 150 ((__KR__) == IWDG_KEY_ENABLE))|| \
Kojto 96:487b796308b0 151 ((__KR__) == IWDG_KEY_WRITE_ACCESS_ENABLE)) || \
Kojto 96:487b796308b0 152 ((__KR__) == IWDG_KEY_WRITE_ACCESS_DISABLE))
Kojto 96:487b796308b0 153
Kojto 96:487b796308b0 154
Kojto 96:487b796308b0 155 /** @defgroup IWDG_Flag_definition IWDG Flag definition
bogdanm 84:0b3ab51c8877 156 * @{
bogdanm 84:0b3ab51c8877 157 */
bogdanm 92:4fc01daae5a5 158 #define IWDG_FLAG_PVU ((uint32_t)IWDG_SR_PVU) /*!< Watchdog counter prescaler value update flag */
bogdanm 92:4fc01daae5a5 159 #define IWDG_FLAG_RVU ((uint32_t)IWDG_SR_RVU) /*!< Watchdog counter reload value update flag */
bogdanm 92:4fc01daae5a5 160 #define IWDG_FLAG_WVU ((uint32_t)IWDG_SR_WVU) /*!< Watchdog counter window value update Flag */
bogdanm 84:0b3ab51c8877 161 /**
bogdanm 84:0b3ab51c8877 162 * @}
bogdanm 84:0b3ab51c8877 163 */
Kojto 96:487b796308b0 164 #define IS_IWDG_FLAG(__FLAG__) (((__FLAG__) == IWDG_FLAG_PVU) || \
Kojto 96:487b796308b0 165 ((__FLAG__) == IWDG_FLAG_RVU) || \
Kojto 96:487b796308b0 166 ((__FLAG__) == IWDG_FLAG_WVU))
bogdanm 84:0b3ab51c8877 167
Kojto 96:487b796308b0 168
Kojto 96:487b796308b0 169 /** @defgroup IWDG_Prescaler IWDG Prescaler
bogdanm 84:0b3ab51c8877 170 * @{
bogdanm 84:0b3ab51c8877 171 */
bogdanm 84:0b3ab51c8877 172 #define IWDG_PRESCALER_4 ((uint8_t)0x00) /*!< IWDG prescaler set to 4 */
bogdanm 92:4fc01daae5a5 173 #define IWDG_PRESCALER_8 ((uint8_t)(IWDG_PR_PR_0)) /*!< IWDG prescaler set to 8 */
bogdanm 92:4fc01daae5a5 174 #define IWDG_PRESCALER_16 ((uint8_t)(IWDG_PR_PR_1)) /*!< IWDG prescaler set to 16 */
bogdanm 92:4fc01daae5a5 175 #define IWDG_PRESCALER_32 ((uint8_t)(IWDG_PR_PR_1 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 32 */
bogdanm 92:4fc01daae5a5 176 #define IWDG_PRESCALER_64 ((uint8_t)(IWDG_PR_PR_2)) /*!< IWDG prescaler set to 64 */
bogdanm 92:4fc01daae5a5 177 #define IWDG_PRESCALER_128 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_0)) /*!< IWDG prescaler set to 128 */
bogdanm 92:4fc01daae5a5 178 #define IWDG_PRESCALER_256 ((uint8_t)(IWDG_PR_PR_2 | IWDG_PR_PR_1)) /*!< IWDG prescaler set to 256 */
Kojto 96:487b796308b0 179 /**
Kojto 96:487b796308b0 180 * @}
Kojto 96:487b796308b0 181 */
bogdanm 92:4fc01daae5a5 182 #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \
bogdanm 92:4fc01daae5a5 183 ((__PRESCALER__) == IWDG_PRESCALER_8) || \
bogdanm 92:4fc01daae5a5 184 ((__PRESCALER__) == IWDG_PRESCALER_16) || \
bogdanm 92:4fc01daae5a5 185 ((__PRESCALER__) == IWDG_PRESCALER_32) || \
bogdanm 92:4fc01daae5a5 186 ((__PRESCALER__) == IWDG_PRESCALER_64) || \
bogdanm 92:4fc01daae5a5 187 ((__PRESCALER__) == IWDG_PRESCALER_128)|| \
bogdanm 92:4fc01daae5a5 188 ((__PRESCALER__) == IWDG_PRESCALER_256))
bogdanm 84:0b3ab51c8877 189
Kojto 96:487b796308b0 190 /* Check for reload value */
bogdanm 92:4fc01daae5a5 191 #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= 0xFFF)
bogdanm 84:0b3ab51c8877 192
Kojto 96:487b796308b0 193 /* Check for window value */
Kojto 96:487b796308b0 194 #define IS_IWDG_WINDOW(__VALUE__) ((__VALUE__) <= 0xFFF)
bogdanm 84:0b3ab51c8877 195
Kojto 96:487b796308b0 196
Kojto 96:487b796308b0 197 /** @defgroup IWDG_Disable IWDG Disable
bogdanm 84:0b3ab51c8877 198 * @{
bogdanm 84:0b3ab51c8877 199 */
bogdanm 84:0b3ab51c8877 200 #define IWDG_WINDOW_DISABLE 0xFFF
bogdanm 84:0b3ab51c8877 201 /**
bogdanm 84:0b3ab51c8877 202 * @}
bogdanm 84:0b3ab51c8877 203 */
bogdanm 84:0b3ab51c8877 204
bogdanm 84:0b3ab51c8877 205 /**
bogdanm 84:0b3ab51c8877 206 * @}
bogdanm 84:0b3ab51c8877 207 */
bogdanm 84:0b3ab51c8877 208 /* Exported macro ------------------------------------------------------------*/
Kojto 96:487b796308b0 209 /** @defgroup IWDG_Exported_Macro IWDG Exported Macro
bogdanm 84:0b3ab51c8877 210 * @{
bogdanm 84:0b3ab51c8877 211 */
bogdanm 84:0b3ab51c8877 212
bogdanm 84:0b3ab51c8877 213 /** @brief Reset IWDG handle state
Kojto 96:487b796308b0 214 * @param __HANDLE__ : IWDG handle
bogdanm 84:0b3ab51c8877 215 * @retval None
bogdanm 84:0b3ab51c8877 216 */
bogdanm 84:0b3ab51c8877 217 #define __HAL_IWDG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IWDG_STATE_RESET)
bogdanm 84:0b3ab51c8877 218
bogdanm 84:0b3ab51c8877 219 /**
bogdanm 84:0b3ab51c8877 220 * @brief Enables the IWDG peripheral.
Kojto 96:487b796308b0 221 * @param __HANDLE__ : IWDG handle
bogdanm 84:0b3ab51c8877 222 * @retval None
bogdanm 84:0b3ab51c8877 223 */
Kojto 96:487b796308b0 224 #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE)
bogdanm 84:0b3ab51c8877 225
bogdanm 84:0b3ab51c8877 226 /**
bogdanm 84:0b3ab51c8877 227 * @brief Reloads IWDG counter with value defined in the reload register
bogdanm 84:0b3ab51c8877 228 * (write access to IWDG_PR and IWDG_RLR registers disabled).
Kojto 96:487b796308b0 229 * @param __HANDLE__ : IWDG handle
bogdanm 84:0b3ab51c8877 230 * @retval None
bogdanm 84:0b3ab51c8877 231 */
Kojto 96:487b796308b0 232 #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD)
bogdanm 84:0b3ab51c8877 233
bogdanm 84:0b3ab51c8877 234 /**
bogdanm 84:0b3ab51c8877 235 * @brief Enables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
Kojto 96:487b796308b0 236 * @param __HANDLE__ : IWDG handle
bogdanm 84:0b3ab51c8877 237 * @retval None
bogdanm 84:0b3ab51c8877 238 */
Kojto 96:487b796308b0 239 #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE)
bogdanm 84:0b3ab51c8877 240
bogdanm 84:0b3ab51c8877 241 /**
bogdanm 84:0b3ab51c8877 242 * @brief Disables write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers.
Kojto 96:487b796308b0 243 * @param __HANDLE__ : IWDG handle
bogdanm 84:0b3ab51c8877 244 * @retval None
bogdanm 84:0b3ab51c8877 245 */
Kojto 96:487b796308b0 246 #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE)
bogdanm 84:0b3ab51c8877 247
bogdanm 84:0b3ab51c8877 248 /**
bogdanm 84:0b3ab51c8877 249 * @brief Gets the selected IWDG's flag status.
Kojto 96:487b796308b0 250 * @param __HANDLE__ : IWDG handle
Kojto 96:487b796308b0 251 * @param __FLAG__ : specifies the flag to check.
bogdanm 84:0b3ab51c8877 252 * This parameter can be one of the following values:
bogdanm 84:0b3ab51c8877 253 * @arg IWDG_FLAG_PVU: Watchdog counter reload value update flag
bogdanm 84:0b3ab51c8877 254 * @arg IWDG_FLAG_RVU: Watchdog counter prescaler value flag
bogdanm 84:0b3ab51c8877 255 * @arg IWDG_FLAG_WVU: Watchdog counter window value flag
bogdanm 84:0b3ab51c8877 256 * @retval The new state of __FLAG__ (TRUE or FALSE) .
bogdanm 84:0b3ab51c8877 257 */
bogdanm 84:0b3ab51c8877 258 #define __HAL_IWDG_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
bogdanm 84:0b3ab51c8877 259
bogdanm 84:0b3ab51c8877 260 /**
bogdanm 84:0b3ab51c8877 261 * @}
bogdanm 84:0b3ab51c8877 262 */
bogdanm 84:0b3ab51c8877 263
bogdanm 92:4fc01daae5a5 264 /* Exported functions --------------------------------------------------------*/
Kojto 96:487b796308b0 265 /** @defgroup IWDG_Exported_Functions
bogdanm 92:4fc01daae5a5 266 * @{
bogdanm 92:4fc01daae5a5 267 */
bogdanm 84:0b3ab51c8877 268
Kojto 96:487b796308b0 269 /** @defgroup IWDG_Exported_Functions_Group1 Initialization/de-initialization functions
Kojto 96:487b796308b0 270 * @{
Kojto 96:487b796308b0 271 */
bogdanm 84:0b3ab51c8877 272 HAL_StatusTypeDef HAL_IWDG_Init(IWDG_HandleTypeDef *hiwdg);
bogdanm 84:0b3ab51c8877 273 void HAL_IWDG_MspInit(IWDG_HandleTypeDef *hiwdg);
Kojto 96:487b796308b0 274 /**
Kojto 96:487b796308b0 275 * @}
Kojto 96:487b796308b0 276 */
bogdanm 84:0b3ab51c8877 277
Kojto 96:487b796308b0 278 /** @defgroup IWDG_Exported_Functions_Group2 I/O operation functions
Kojto 96:487b796308b0 279 * @{
Kojto 96:487b796308b0 280 */
bogdanm 84:0b3ab51c8877 281 HAL_StatusTypeDef HAL_IWDG_Start(IWDG_HandleTypeDef *hiwdg);
bogdanm 84:0b3ab51c8877 282 HAL_StatusTypeDef HAL_IWDG_Refresh(IWDG_HandleTypeDef *hiwdg);
bogdanm 84:0b3ab51c8877 283 /**
bogdanm 84:0b3ab51c8877 284 * @}
Kojto 96:487b796308b0 285 */
Kojto 96:487b796308b0 286
Kojto 96:487b796308b0 287 /** @defgroup IWDG_Exported_Functions_Group3 Peripheral State functions
Kojto 96:487b796308b0 288 * @{
Kojto 96:487b796308b0 289 */
Kojto 96:487b796308b0 290 HAL_IWDG_StateTypeDef HAL_IWDG_GetState(IWDG_HandleTypeDef *hiwdg);
Kojto 96:487b796308b0 291 /**
Kojto 96:487b796308b0 292 * @}
Kojto 96:487b796308b0 293 */
bogdanm 92:4fc01daae5a5 294
bogdanm 92:4fc01daae5a5 295 /**
bogdanm 92:4fc01daae5a5 296 * @}
bogdanm 84:0b3ab51c8877 297 */
bogdanm 84:0b3ab51c8877 298
bogdanm 84:0b3ab51c8877 299 /**
bogdanm 84:0b3ab51c8877 300 * @}
bogdanm 84:0b3ab51c8877 301 */
Kojto 96:487b796308b0 302
Kojto 96:487b796308b0 303 /**
Kojto 96:487b796308b0 304 * @}
Kojto 96:487b796308b0 305 */
Kojto 96:487b796308b0 306
bogdanm 84:0b3ab51c8877 307 #ifdef __cplusplus
bogdanm 84:0b3ab51c8877 308 }
bogdanm 84:0b3ab51c8877 309 #endif
bogdanm 84:0b3ab51c8877 310
bogdanm 84:0b3ab51c8877 311 #endif /* __STM32L0xx_HAL_IWDG_H */
bogdanm 84:0b3ab51c8877 312
bogdanm 84:0b3ab51c8877 313 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 96:487b796308b0 314