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TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:: filartrix
Date:: Wed Apr 08 14:12:53 2015 +0000
Revision:: 97:4298809c7c9e
Parent:: 92:4fc01daae5a5

First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

User	Revision	Line number	New contents of line
bogdanm	86:04dd9b1680ae	1	/**
bogdanm	86:04dd9b1680ae	2	******************************************************************************
bogdanm	86:04dd9b1680ae	3	* @file stm32f3xx_hal_rcc_ex.h
bogdanm	86:04dd9b1680ae	4	* @author MCD Application Team
bogdanm	92:4fc01daae5a5	5	* @version V1.1.0
bogdanm	92:4fc01daae5a5	6	* @date 12-Sept-2014
bogdanm	92:4fc01daae5a5	7	* @brief Header file of RCC HAL Extended module.
bogdanm	86:04dd9b1680ae	8	******************************************************************************
bogdanm	86:04dd9b1680ae	9	* @attention
bogdanm	86:04dd9b1680ae	10	*
bogdanm	86:04dd9b1680ae	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm	86:04dd9b1680ae	12	*
bogdanm	86:04dd9b1680ae	13	* Redistribution and use in source and binary forms, with or without modification,
bogdanm	86:04dd9b1680ae	14	* are permitted provided that the following conditions are met:
bogdanm	86:04dd9b1680ae	15	* 1. Redistributions of source code must retain the above copyright notice,
bogdanm	86:04dd9b1680ae	16	* this list of conditions and the following disclaimer.
bogdanm	86:04dd9b1680ae	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm	86:04dd9b1680ae	18	* this list of conditions and the following disclaimer in the documentation
bogdanm	86:04dd9b1680ae	19	* and/or other materials provided with the distribution.
bogdanm	86:04dd9b1680ae	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm	86:04dd9b1680ae	21	* may be used to endorse or promote products derived from this software
bogdanm	86:04dd9b1680ae	22	* without specific prior written permission.
bogdanm	86:04dd9b1680ae	23	*
bogdanm	86:04dd9b1680ae	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm	86:04dd9b1680ae	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm	86:04dd9b1680ae	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm	86:04dd9b1680ae	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm	86:04dd9b1680ae	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm	86:04dd9b1680ae	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm	86:04dd9b1680ae	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm	86:04dd9b1680ae	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm	86:04dd9b1680ae	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm	86:04dd9b1680ae	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm	86:04dd9b1680ae	34	*
bogdanm	86:04dd9b1680ae	35	******************************************************************************
bogdanm	86:04dd9b1680ae	36	*/
bogdanm	86:04dd9b1680ae	37
bogdanm	86:04dd9b1680ae	38	/* Define to prevent recursive inclusion -------------------------------------*/
bogdanm	86:04dd9b1680ae	39	#ifndef __STM32F3xx_HAL_RCC_EX_H
bogdanm	86:04dd9b1680ae	40	#define __STM32F3xx_HAL_RCC_EX_H
bogdanm	86:04dd9b1680ae	41
bogdanm	86:04dd9b1680ae	42	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	43	extern "C" {
bogdanm	86:04dd9b1680ae	44	#endif
bogdanm	86:04dd9b1680ae	45
bogdanm	86:04dd9b1680ae	46	/* Includes ------------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	47	#include "stm32f3xx_hal_def.h"
bogdanm	86:04dd9b1680ae	48
bogdanm	86:04dd9b1680ae	49	/** @addtogroup STM32F3xx_HAL_Driver
bogdanm	86:04dd9b1680ae	50	* @{
bogdanm	86:04dd9b1680ae	51	*/
bogdanm	86:04dd9b1680ae	52
bogdanm	92:4fc01daae5a5	53	/** @addtogroup RCCEx
bogdanm	86:04dd9b1680ae	54	* @{
bogdanm	86:04dd9b1680ae	55	*/
bogdanm	86:04dd9b1680ae	56
bogdanm	86:04dd9b1680ae	57	/* Exported types ------------------------------------------------------------*/
bogdanm	86:04dd9b1680ae	58
bogdanm	92:4fc01daae5a5	59	/** @defgroup RCCEx_Exported_Types RCC Extended Exported Types
bogdanm	92:4fc01daae5a5	60	* @{
bogdanm	92:4fc01daae5a5	61	*/
bogdanm	92:4fc01daae5a5	62	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	63	/**
bogdanm	92:4fc01daae5a5	64	* @brief RCC PLL configuration structure definition
bogdanm	92:4fc01daae5a5	65	*/
bogdanm	92:4fc01daae5a5	66	typedef struct
bogdanm	92:4fc01daae5a5	67	{
bogdanm	92:4fc01daae5a5	68	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
bogdanm	92:4fc01daae5a5	69	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	92:4fc01daae5a5	70
bogdanm	92:4fc01daae5a5	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
bogdanm	92:4fc01daae5a5	72	This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
bogdanm	92:4fc01daae5a5	73
bogdanm	92:4fc01daae5a5	74	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
bogdanm	92:4fc01daae5a5	75	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
bogdanm	92:4fc01daae5a5	76
bogdanm	92:4fc01daae5a5	77	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
bogdanm	92:4fc01daae5a5	78	This parameter must be a value of @ref RCCEx_PLL_Prediv_Factor */
bogdanm	92:4fc01daae5a5	79
bogdanm	92:4fc01daae5a5	80	}RCC_PLLInitTypeDef;
bogdanm	92:4fc01daae5a5	81
bogdanm	92:4fc01daae5a5	82	/**
bogdanm	92:4fc01daae5a5	83	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	92:4fc01daae5a5	84	*/
bogdanm	92:4fc01daae5a5	85	typedef struct
bogdanm	92:4fc01daae5a5	86	{
bogdanm	92:4fc01daae5a5	87	uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm	92:4fc01daae5a5	88	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	92:4fc01daae5a5	89
bogdanm	92:4fc01daae5a5	90	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	92:4fc01daae5a5	91	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	92:4fc01daae5a5	92
bogdanm	92:4fc01daae5a5	93	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	92:4fc01daae5a5	94	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	92:4fc01daae5a5	95
bogdanm	92:4fc01daae5a5	96	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	92:4fc01daae5a5	97	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	92:4fc01daae5a5	98
bogdanm	92:4fc01daae5a5	99	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm	92:4fc01daae5a5	100	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	92:4fc01daae5a5	101
bogdanm	92:4fc01daae5a5	102	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	92:4fc01daae5a5	103	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	92:4fc01daae5a5	104
bogdanm	92:4fc01daae5a5	105	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	92:4fc01daae5a5	106
bogdanm	92:4fc01daae5a5	107	}RCC_OscInitTypeDef;
bogdanm	92:4fc01daae5a5	108
bogdanm	92:4fc01daae5a5	109	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	110
bogdanm	92:4fc01daae5a5	111	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	112	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	113	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
bogdanm	92:4fc01daae5a5	114	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	92:4fc01daae5a5	115	/**
bogdanm	92:4fc01daae5a5	116	* @brief RCC PLL configuration structure definition
bogdanm	92:4fc01daae5a5	117	*/
bogdanm	92:4fc01daae5a5	118	typedef struct
bogdanm	92:4fc01daae5a5	119	{
bogdanm	92:4fc01daae5a5	120	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
bogdanm	92:4fc01daae5a5	121	This parameter can be a value of @ref RCC_PLL_Config */
bogdanm	92:4fc01daae5a5	122
bogdanm	92:4fc01daae5a5	123	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
bogdanm	92:4fc01daae5a5	124	This parameter must be a value of @ref RCCEx_PLL_Clock_Source */
bogdanm	92:4fc01daae5a5	125
bogdanm	92:4fc01daae5a5	126	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
bogdanm	92:4fc01daae5a5	127	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor*/
bogdanm	92:4fc01daae5a5	128
bogdanm	92:4fc01daae5a5	129	}RCC_PLLInitTypeDef;
bogdanm	92:4fc01daae5a5	130
bogdanm	92:4fc01daae5a5	131	/**
bogdanm	92:4fc01daae5a5	132	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
bogdanm	92:4fc01daae5a5	133	*/
bogdanm	92:4fc01daae5a5	134	typedef struct
bogdanm	92:4fc01daae5a5	135	{
bogdanm	92:4fc01daae5a5	136	uint32_t OscillatorType; /*!< The oscillators to be configured.
bogdanm	92:4fc01daae5a5	137	This parameter can be a value of @ref RCC_Oscillator_Type */
bogdanm	92:4fc01daae5a5	138
bogdanm	92:4fc01daae5a5	139	uint32_t HSEState; /*!< The new state of the HSE.
bogdanm	92:4fc01daae5a5	140	This parameter can be a value of @ref RCC_HSE_Config */
bogdanm	92:4fc01daae5a5	141
bogdanm	92:4fc01daae5a5	142	uint32_t HSEPredivValue; /*!< The HSE predivision factor value.
bogdanm	92:4fc01daae5a5	143	This parameter can be a value of @ref RCCEx_HSE_Predivision_Factor */
bogdanm	92:4fc01daae5a5	144
bogdanm	92:4fc01daae5a5	145	uint32_t LSEState; /*!< The new state of the LSE.
bogdanm	92:4fc01daae5a5	146	This parameter can be a value of @ref RCC_LSE_Config */
bogdanm	92:4fc01daae5a5	147
bogdanm	92:4fc01daae5a5	148	uint32_t HSIState; /*!< The new state of the HSI.
bogdanm	92:4fc01daae5a5	149	This parameter can be a value of @ref RCC_HSI_Config */
bogdanm	92:4fc01daae5a5	150
bogdanm	92:4fc01daae5a5	151	uint32_t HSICalibrationValue; /*!< The calibration trimming value.
bogdanm	92:4fc01daae5a5	152	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
bogdanm	92:4fc01daae5a5	153
bogdanm	92:4fc01daae5a5	154	uint32_t LSIState; /*!< The new state of the LSI.
bogdanm	92:4fc01daae5a5	155	This parameter can be a value of @ref RCC_LSI_Config */
bogdanm	92:4fc01daae5a5	156
bogdanm	92:4fc01daae5a5	157	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
bogdanm	92:4fc01daae5a5	158
bogdanm	92:4fc01daae5a5	159	}RCC_OscInitTypeDef;
bogdanm	92:4fc01daae5a5	160	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	161	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	162	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	92:4fc01daae5a5	163	/* STM32F373xC \|\| STM32F378xx */
bogdanm	92:4fc01daae5a5	164
bogdanm	86:04dd9b1680ae	165	/**
bogdanm	86:04dd9b1680ae	166	* @brief RCC extended clocks structure definition
bogdanm	86:04dd9b1680ae	167	*/
bogdanm	86:04dd9b1680ae	168	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	169	typedef struct
bogdanm	86:04dd9b1680ae	170	{
bogdanm	86:04dd9b1680ae	171	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	172	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	173
bogdanm	86:04dd9b1680ae	174	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	175	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	176
bogdanm	86:04dd9b1680ae	177	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	178	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	179
bogdanm	86:04dd9b1680ae	180	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	181	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	182
bogdanm	86:04dd9b1680ae	183	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	184	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	185
bogdanm	86:04dd9b1680ae	186	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	187	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	188
bogdanm	86:04dd9b1680ae	189	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	86:04dd9b1680ae	190	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	86:04dd9b1680ae	191
bogdanm	86:04dd9b1680ae	192	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	86:04dd9b1680ae	193	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	86:04dd9b1680ae	194
bogdanm	86:04dd9b1680ae	195	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm	86:04dd9b1680ae	196	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm	86:04dd9b1680ae	197
bogdanm	86:04dd9b1680ae	198	uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm	86:04dd9b1680ae	199	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	86:04dd9b1680ae	200
bogdanm	86:04dd9b1680ae	201	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	86:04dd9b1680ae	202	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	203
bogdanm	86:04dd9b1680ae	204	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm	86:04dd9b1680ae	205	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm	86:04dd9b1680ae	206
bogdanm	86:04dd9b1680ae	207	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm	86:04dd9b1680ae	208	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm	86:04dd9b1680ae	209
bogdanm	86:04dd9b1680ae	210	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm	86:04dd9b1680ae	211	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm	86:04dd9b1680ae	212	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	213	#endif /* STM32F301x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	214
bogdanm	86:04dd9b1680ae	215	#if defined(STM32F302x8)
bogdanm	86:04dd9b1680ae	216	typedef struct
bogdanm	86:04dd9b1680ae	217	{
bogdanm	86:04dd9b1680ae	218	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	219	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	220
bogdanm	86:04dd9b1680ae	221	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	222	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	223
bogdanm	86:04dd9b1680ae	224	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	225	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	226
bogdanm	86:04dd9b1680ae	227	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	228	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	229
bogdanm	86:04dd9b1680ae	230	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	231	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	232
bogdanm	86:04dd9b1680ae	233	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	234	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	235
bogdanm	86:04dd9b1680ae	236	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	86:04dd9b1680ae	237	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	86:04dd9b1680ae	238
bogdanm	86:04dd9b1680ae	239	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	86:04dd9b1680ae	240	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	86:04dd9b1680ae	241
bogdanm	86:04dd9b1680ae	242	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm	86:04dd9b1680ae	243	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm	86:04dd9b1680ae	244
bogdanm	86:04dd9b1680ae	245	uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm	86:04dd9b1680ae	246	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	86:04dd9b1680ae	247
bogdanm	86:04dd9b1680ae	248	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	86:04dd9b1680ae	249	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	250
bogdanm	86:04dd9b1680ae	251	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm	86:04dd9b1680ae	252	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm	86:04dd9b1680ae	253
bogdanm	86:04dd9b1680ae	254	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm	86:04dd9b1680ae	255	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm	86:04dd9b1680ae	256
bogdanm	86:04dd9b1680ae	257	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm	86:04dd9b1680ae	258	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm	86:04dd9b1680ae	259
bogdanm	86:04dd9b1680ae	260	uint32_t USBClockSelection; /*!< USB clock source
bogdanm	86:04dd9b1680ae	261	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	86:04dd9b1680ae	262
bogdanm	86:04dd9b1680ae	263	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	264	#endif /* STM32F302x8 */
bogdanm	86:04dd9b1680ae	265
bogdanm	86:04dd9b1680ae	266	#if defined(STM32F302xC)
bogdanm	86:04dd9b1680ae	267	typedef struct
bogdanm	86:04dd9b1680ae	268	{
bogdanm	86:04dd9b1680ae	269	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	270	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	271
bogdanm	86:04dd9b1680ae	272	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	273	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	274
bogdanm	86:04dd9b1680ae	275	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	276	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	277
bogdanm	86:04dd9b1680ae	278	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	279	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	280
bogdanm	86:04dd9b1680ae	281	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	282	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	283
bogdanm	86:04dd9b1680ae	284	uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm	86:04dd9b1680ae	285	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm	86:04dd9b1680ae	286
bogdanm	86:04dd9b1680ae	287	uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm	86:04dd9b1680ae	288	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm	86:04dd9b1680ae	289
bogdanm	86:04dd9b1680ae	290	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	291	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	292
bogdanm	86:04dd9b1680ae	293	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	86:04dd9b1680ae	294	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	86:04dd9b1680ae	295
bogdanm	86:04dd9b1680ae	296	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	86:04dd9b1680ae	297	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	86:04dd9b1680ae	298
bogdanm	86:04dd9b1680ae	299	uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm	86:04dd9b1680ae	300	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	86:04dd9b1680ae	301
bogdanm	86:04dd9b1680ae	302	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	86:04dd9b1680ae	303	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	304
bogdanm	86:04dd9b1680ae	305	uint32_t USBClockSelection; /*!< USB clock source
bogdanm	86:04dd9b1680ae	306	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	86:04dd9b1680ae	307
bogdanm	86:04dd9b1680ae	308	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	309	#endif /* STM32F302xC */
bogdanm	86:04dd9b1680ae	310
bogdanm	86:04dd9b1680ae	311	#if defined(STM32F303xC)
bogdanm	86:04dd9b1680ae	312	typedef struct
bogdanm	86:04dd9b1680ae	313	{
bogdanm	86:04dd9b1680ae	314	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	315	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	316
bogdanm	86:04dd9b1680ae	317	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	318	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	319
bogdanm	86:04dd9b1680ae	320	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	321	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	322
bogdanm	86:04dd9b1680ae	323	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	324	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	325
bogdanm	86:04dd9b1680ae	326	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	327	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	328
bogdanm	86:04dd9b1680ae	329	uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm	86:04dd9b1680ae	330	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm	86:04dd9b1680ae	331
bogdanm	86:04dd9b1680ae	332	uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm	86:04dd9b1680ae	333	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm	86:04dd9b1680ae	334
bogdanm	86:04dd9b1680ae	335	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	336	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	337
bogdanm	86:04dd9b1680ae	338	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	86:04dd9b1680ae	339	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	86:04dd9b1680ae	340
bogdanm	86:04dd9b1680ae	341	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	86:04dd9b1680ae	342	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	86:04dd9b1680ae	343
bogdanm	86:04dd9b1680ae	344	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm	86:04dd9b1680ae	345	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm	86:04dd9b1680ae	346
bogdanm	86:04dd9b1680ae	347	uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm	86:04dd9b1680ae	348	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	86:04dd9b1680ae	349
bogdanm	86:04dd9b1680ae	350	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	86:04dd9b1680ae	351	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	352
bogdanm	86:04dd9b1680ae	353	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm	86:04dd9b1680ae	354	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm	86:04dd9b1680ae	355
bogdanm	86:04dd9b1680ae	356	uint32_t USBClockSelection; /*!< USB clock source
bogdanm	86:04dd9b1680ae	357	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	86:04dd9b1680ae	358
bogdanm	86:04dd9b1680ae	359	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	360	#endif /* STM32F303xC */
bogdanm	86:04dd9b1680ae	361
bogdanm	92:4fc01daae5a5	362	#if defined(STM32F302xE)
bogdanm	92:4fc01daae5a5	363	typedef struct
bogdanm	92:4fc01daae5a5	364	{
bogdanm	92:4fc01daae5a5	365	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	92:4fc01daae5a5	366	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	92:4fc01daae5a5	367
bogdanm	92:4fc01daae5a5	368	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	92:4fc01daae5a5	369	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	92:4fc01daae5a5	370
bogdanm	92:4fc01daae5a5	371	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	92:4fc01daae5a5	372	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	92:4fc01daae5a5	373
bogdanm	92:4fc01daae5a5	374	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	92:4fc01daae5a5	375	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	92:4fc01daae5a5	376
bogdanm	92:4fc01daae5a5	377	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	92:4fc01daae5a5	378	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	92:4fc01daae5a5	379
bogdanm	92:4fc01daae5a5	380	uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm	92:4fc01daae5a5	381	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm	92:4fc01daae5a5	382
bogdanm	92:4fc01daae5a5	383	uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm	92:4fc01daae5a5	384	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm	92:4fc01daae5a5	385
bogdanm	92:4fc01daae5a5	386	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	92:4fc01daae5a5	387	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	92:4fc01daae5a5	388
bogdanm	92:4fc01daae5a5	389	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	92:4fc01daae5a5	390	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	92:4fc01daae5a5	391
bogdanm	92:4fc01daae5a5	392	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	92:4fc01daae5a5	393	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	92:4fc01daae5a5	394
bogdanm	92:4fc01daae5a5	395	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	92:4fc01daae5a5	396	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	92:4fc01daae5a5	397
bogdanm	92:4fc01daae5a5	398	uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm	92:4fc01daae5a5	399	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	92:4fc01daae5a5	400
bogdanm	92:4fc01daae5a5	401	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	92:4fc01daae5a5	402	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	92:4fc01daae5a5	403
bogdanm	92:4fc01daae5a5	404	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
bogdanm	92:4fc01daae5a5	405	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
bogdanm	92:4fc01daae5a5	406
bogdanm	92:4fc01daae5a5	407	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
bogdanm	92:4fc01daae5a5	408	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
bogdanm	92:4fc01daae5a5	409
bogdanm	92:4fc01daae5a5	410	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm	92:4fc01daae5a5	411	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm	92:4fc01daae5a5	412
bogdanm	92:4fc01daae5a5	413	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm	92:4fc01daae5a5	414	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm	92:4fc01daae5a5	415
bogdanm	92:4fc01daae5a5	416	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm	92:4fc01daae5a5	417	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm	92:4fc01daae5a5	418
bogdanm	92:4fc01daae5a5	419	uint32_t USBClockSelection; /*!< USB clock source
bogdanm	92:4fc01daae5a5	420	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	92:4fc01daae5a5	421
bogdanm	92:4fc01daae5a5	422	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	423	#endif /* STM32F302xE */
bogdanm	92:4fc01daae5a5	424
bogdanm	92:4fc01daae5a5	425	#if defined(STM32F303xE)
bogdanm	92:4fc01daae5a5	426	typedef struct
bogdanm	92:4fc01daae5a5	427	{
bogdanm	92:4fc01daae5a5	428	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	92:4fc01daae5a5	429	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	92:4fc01daae5a5	430
bogdanm	92:4fc01daae5a5	431	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	92:4fc01daae5a5	432	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	92:4fc01daae5a5	433
bogdanm	92:4fc01daae5a5	434	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	92:4fc01daae5a5	435	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	92:4fc01daae5a5	436
bogdanm	92:4fc01daae5a5	437	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	92:4fc01daae5a5	438	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	92:4fc01daae5a5	439
bogdanm	92:4fc01daae5a5	440	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	92:4fc01daae5a5	441	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	92:4fc01daae5a5	442
bogdanm	92:4fc01daae5a5	443	uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm	92:4fc01daae5a5	444	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm	92:4fc01daae5a5	445
bogdanm	92:4fc01daae5a5	446	uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm	92:4fc01daae5a5	447	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm	92:4fc01daae5a5	448
bogdanm	92:4fc01daae5a5	449	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	92:4fc01daae5a5	450	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	92:4fc01daae5a5	451
bogdanm	92:4fc01daae5a5	452	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	92:4fc01daae5a5	453	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	92:4fc01daae5a5	454
bogdanm	92:4fc01daae5a5	455	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	92:4fc01daae5a5	456	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	92:4fc01daae5a5	457
bogdanm	92:4fc01daae5a5	458	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	92:4fc01daae5a5	459	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	92:4fc01daae5a5	460
bogdanm	92:4fc01daae5a5	461	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm	92:4fc01daae5a5	462	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm	92:4fc01daae5a5	463
bogdanm	92:4fc01daae5a5	464	uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm	92:4fc01daae5a5	465	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	92:4fc01daae5a5	466
bogdanm	92:4fc01daae5a5	467	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	92:4fc01daae5a5	468	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	92:4fc01daae5a5	469
bogdanm	92:4fc01daae5a5	470	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
bogdanm	92:4fc01daae5a5	471	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
bogdanm	92:4fc01daae5a5	472
bogdanm	92:4fc01daae5a5	473	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
bogdanm	92:4fc01daae5a5	474	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
bogdanm	92:4fc01daae5a5	475
bogdanm	92:4fc01daae5a5	476	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm	92:4fc01daae5a5	477	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm	92:4fc01daae5a5	478
bogdanm	92:4fc01daae5a5	479	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm	92:4fc01daae5a5	480	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm	92:4fc01daae5a5	481
bogdanm	92:4fc01daae5a5	482	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm	92:4fc01daae5a5	483	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm	92:4fc01daae5a5	484
bogdanm	92:4fc01daae5a5	485	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm	92:4fc01daae5a5	486	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm	92:4fc01daae5a5	487
bogdanm	92:4fc01daae5a5	488	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
bogdanm	92:4fc01daae5a5	489	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
bogdanm	92:4fc01daae5a5	490
bogdanm	92:4fc01daae5a5	491	uint32_t USBClockSelection; /*!< USB clock source
bogdanm	92:4fc01daae5a5	492	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	92:4fc01daae5a5	493
bogdanm	92:4fc01daae5a5	494	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	495	#endif /* STM32F303xE */
bogdanm	92:4fc01daae5a5	496
bogdanm	92:4fc01daae5a5	497	#if defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	498	typedef struct
bogdanm	92:4fc01daae5a5	499	{
bogdanm	92:4fc01daae5a5	500	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	92:4fc01daae5a5	501	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	92:4fc01daae5a5	502
bogdanm	92:4fc01daae5a5	503	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	92:4fc01daae5a5	504	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	92:4fc01daae5a5	505
bogdanm	92:4fc01daae5a5	506	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	92:4fc01daae5a5	507	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	92:4fc01daae5a5	508
bogdanm	92:4fc01daae5a5	509	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	92:4fc01daae5a5	510	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	92:4fc01daae5a5	511
bogdanm	92:4fc01daae5a5	512	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	92:4fc01daae5a5	513	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	92:4fc01daae5a5	514
bogdanm	92:4fc01daae5a5	515	uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm	92:4fc01daae5a5	516	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm	92:4fc01daae5a5	517
bogdanm	92:4fc01daae5a5	518	uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm	92:4fc01daae5a5	519	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm	92:4fc01daae5a5	520
bogdanm	92:4fc01daae5a5	521	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	92:4fc01daae5a5	522	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	92:4fc01daae5a5	523
bogdanm	92:4fc01daae5a5	524	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	92:4fc01daae5a5	525	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	92:4fc01daae5a5	526
bogdanm	92:4fc01daae5a5	527	uint32_t I2c3ClockSelection; /*!< I2C3 clock source
bogdanm	92:4fc01daae5a5	528	This parameter can be a value of @ref RCCEx_I2C3_Clock_Source */
bogdanm	92:4fc01daae5a5	529
bogdanm	92:4fc01daae5a5	530	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	92:4fc01daae5a5	531	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	92:4fc01daae5a5	532
bogdanm	92:4fc01daae5a5	533	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm	92:4fc01daae5a5	534	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm	92:4fc01daae5a5	535
bogdanm	92:4fc01daae5a5	536	uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm	92:4fc01daae5a5	537	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	92:4fc01daae5a5	538
bogdanm	92:4fc01daae5a5	539	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	92:4fc01daae5a5	540	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	92:4fc01daae5a5	541
bogdanm	92:4fc01daae5a5	542	uint32_t Tim2ClockSelection; /*!< TIM2 clock source
bogdanm	92:4fc01daae5a5	543	This parameter can be a value of @ref RCCEx_TIM2_Clock_Source */
bogdanm	92:4fc01daae5a5	544
bogdanm	92:4fc01daae5a5	545	uint32_t Tim34ClockSelection; /*!< TIM3 & TIM4 clock source
bogdanm	92:4fc01daae5a5	546	This parameter can be a value of @ref RCCEx_TIM34_Clock_Source */
bogdanm	92:4fc01daae5a5	547
bogdanm	92:4fc01daae5a5	548	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm	92:4fc01daae5a5	549	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm	92:4fc01daae5a5	550
bogdanm	92:4fc01daae5a5	551	uint32_t Tim15ClockSelection; /*!< TIM15 clock source
bogdanm	92:4fc01daae5a5	552	This parameter can be a value of @ref RCCEx_TIM15_Clock_Source */
bogdanm	92:4fc01daae5a5	553
bogdanm	92:4fc01daae5a5	554	uint32_t Tim16ClockSelection; /*!< TIM16 clock source
bogdanm	92:4fc01daae5a5	555	This parameter can be a value of @ref RCCEx_TIM16_Clock_Source */
bogdanm	92:4fc01daae5a5	556
bogdanm	92:4fc01daae5a5	557	uint32_t Tim17ClockSelection; /*!< TIM17 clock source
bogdanm	92:4fc01daae5a5	558	This parameter can be a value of @ref RCCEx_TIM17_Clock_Source */
bogdanm	92:4fc01daae5a5	559
bogdanm	92:4fc01daae5a5	560	uint32_t Tim20ClockSelection; /*!< TIM20 clock source
bogdanm	92:4fc01daae5a5	561	This parameter can be a value of @ref RCCEx_TIM20_Clock_Source */
bogdanm	92:4fc01daae5a5	562
bogdanm	92:4fc01daae5a5	563	}RCC_PeriphCLKInitTypeDef;
bogdanm	92:4fc01daae5a5	564	#endif /* STM32F398xx */
bogdanm	92:4fc01daae5a5	565
bogdanm	86:04dd9b1680ae	566	#if defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	567	typedef struct
bogdanm	86:04dd9b1680ae	568	{
bogdanm	86:04dd9b1680ae	569	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	570	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	571
bogdanm	86:04dd9b1680ae	572	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	573	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	574
bogdanm	86:04dd9b1680ae	575	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	576	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	577
bogdanm	86:04dd9b1680ae	578	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	579	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	580
bogdanm	86:04dd9b1680ae	581	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	582	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	583
bogdanm	86:04dd9b1680ae	584	uint32_t Uart4ClockSelection; /*!< UART4 clock source
bogdanm	86:04dd9b1680ae	585	This parameter can be a value of @ref RCCEx_UART4_Clock_Source */
bogdanm	86:04dd9b1680ae	586
bogdanm	86:04dd9b1680ae	587	uint32_t Uart5ClockSelection; /*!< UART5 clock source
bogdanm	86:04dd9b1680ae	588	This parameter can be a value of @ref RCCEx_UART5_Clock_Source */
bogdanm	86:04dd9b1680ae	589
bogdanm	86:04dd9b1680ae	590	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	591	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	592
bogdanm	86:04dd9b1680ae	593	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	86:04dd9b1680ae	594	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	86:04dd9b1680ae	595
bogdanm	86:04dd9b1680ae	596	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	86:04dd9b1680ae	597	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	86:04dd9b1680ae	598
bogdanm	86:04dd9b1680ae	599	uint32_t Adc34ClockSelection; /*!< ADC3 & ADC4 clock source
bogdanm	86:04dd9b1680ae	600	This parameter can be a value of @ref RCCEx_ADC34_Clock_Source */
bogdanm	86:04dd9b1680ae	601
bogdanm	86:04dd9b1680ae	602	uint32_t I2sClockSelection; /*!< I2S clock source
bogdanm	86:04dd9b1680ae	603	This parameter can be a value of @ref RCCEx_I2S_Clock_Source */
bogdanm	86:04dd9b1680ae	604
bogdanm	86:04dd9b1680ae	605	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	86:04dd9b1680ae	606	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	607
bogdanm	86:04dd9b1680ae	608	uint32_t Tim8ClockSelection; /*!< TIM8 clock source
bogdanm	86:04dd9b1680ae	609	This parameter can be a value of @ref RCCEx_TIM8_Clock_Source */
bogdanm	86:04dd9b1680ae	610
bogdanm	86:04dd9b1680ae	611	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	612	#endif /* STM32F358xx */
bogdanm	86:04dd9b1680ae	613
bogdanm	86:04dd9b1680ae	614	#if defined(STM32F303x8)
bogdanm	86:04dd9b1680ae	615	typedef struct
bogdanm	86:04dd9b1680ae	616	{
bogdanm	86:04dd9b1680ae	617	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	618	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	619
bogdanm	86:04dd9b1680ae	620	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	621	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	622
bogdanm	92:4fc01daae5a5	623	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	624	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	625
bogdanm	86:04dd9b1680ae	626	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	627	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	628
bogdanm	86:04dd9b1680ae	629	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	630	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	631
bogdanm	86:04dd9b1680ae	632	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	633	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	634
bogdanm	86:04dd9b1680ae	635	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	86:04dd9b1680ae	636	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	86:04dd9b1680ae	637
bogdanm	86:04dd9b1680ae	638	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	86:04dd9b1680ae	639	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	640
bogdanm	86:04dd9b1680ae	641	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	642	#endif /* STM32F303x8 */
bogdanm	86:04dd9b1680ae	643
bogdanm	86:04dd9b1680ae	644	#if defined(STM32F334x8)
bogdanm	86:04dd9b1680ae	645	typedef struct
bogdanm	86:04dd9b1680ae	646	{
bogdanm	86:04dd9b1680ae	647	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	648	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	649
bogdanm	86:04dd9b1680ae	650	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	651	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	652
bogdanm	92:4fc01daae5a5	653	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	654	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	655
bogdanm	86:04dd9b1680ae	656	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	657	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	658
bogdanm	86:04dd9b1680ae	659	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	660	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	661
bogdanm	86:04dd9b1680ae	662	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	663	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	664
bogdanm	86:04dd9b1680ae	665	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	86:04dd9b1680ae	666	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	86:04dd9b1680ae	667
bogdanm	86:04dd9b1680ae	668	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	86:04dd9b1680ae	669	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	670
bogdanm	86:04dd9b1680ae	671	uint32_t Hrtim1ClockSelection; /*!< HRTIM1 clock source
bogdanm	86:04dd9b1680ae	672	This parameter can be a value of @ref RCCEx_HRTIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	673
bogdanm	86:04dd9b1680ae	674	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	675	#endif /* STM32F334x8 */
bogdanm	86:04dd9b1680ae	676
bogdanm	86:04dd9b1680ae	677	#if defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	678	typedef struct
bogdanm	86:04dd9b1680ae	679	{
bogdanm	86:04dd9b1680ae	680	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	681	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	682
bogdanm	86:04dd9b1680ae	683	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	684	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	685
bogdanm	86:04dd9b1680ae	686	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	92:4fc01daae5a5	687	This parameter can be a value of @ref RCC_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	688
bogdanm	86:04dd9b1680ae	689	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	690	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	691
bogdanm	86:04dd9b1680ae	692	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	693	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	694
bogdanm	86:04dd9b1680ae	695	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	696	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	697
bogdanm	86:04dd9b1680ae	698	uint32_t Adc12ClockSelection; /*!< ADC1 & ADC2 clock source
bogdanm	86:04dd9b1680ae	699	This parameter can be a value of @ref RCCEx_ADC12_Clock_Source */
bogdanm	86:04dd9b1680ae	700
bogdanm	86:04dd9b1680ae	701	uint32_t Tim1ClockSelection; /*!< TIM1 clock source
bogdanm	86:04dd9b1680ae	702	This parameter can be a value of @ref RCCEx_TIM1_Clock_Source */
bogdanm	86:04dd9b1680ae	703
bogdanm	86:04dd9b1680ae	704	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	705	#endif /* STM32F328xx */
bogdanm	86:04dd9b1680ae	706
bogdanm	86:04dd9b1680ae	707	#if defined(STM32F373xC)
bogdanm	86:04dd9b1680ae	708	typedef struct
bogdanm	86:04dd9b1680ae	709	{
bogdanm	86:04dd9b1680ae	710	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	711	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	712
bogdanm	86:04dd9b1680ae	713	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	714	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	715
bogdanm	86:04dd9b1680ae	716	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	717	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	718
bogdanm	86:04dd9b1680ae	719	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	720	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	721
bogdanm	86:04dd9b1680ae	722	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	723	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	724
bogdanm	86:04dd9b1680ae	725	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	726	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	727
bogdanm	86:04dd9b1680ae	728	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	86:04dd9b1680ae	729	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	86:04dd9b1680ae	730
bogdanm	86:04dd9b1680ae	731	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm	86:04dd9b1680ae	732	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm	86:04dd9b1680ae	733
bogdanm	86:04dd9b1680ae	734	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
bogdanm	86:04dd9b1680ae	735	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
bogdanm	86:04dd9b1680ae	736
bogdanm	86:04dd9b1680ae	737	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	86:04dd9b1680ae	738	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	86:04dd9b1680ae	739
bogdanm	86:04dd9b1680ae	740	uint32_t USBClockSelection; /*!< USB clock source
bogdanm	86:04dd9b1680ae	741	This parameter can be a value of @ref RCCEx_USB_Clock_Source */
bogdanm	86:04dd9b1680ae	742
bogdanm	86:04dd9b1680ae	743	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	744	#endif /* STM32F373xC */
bogdanm	86:04dd9b1680ae	745
bogdanm	86:04dd9b1680ae	746	#if defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	747	typedef struct
bogdanm	86:04dd9b1680ae	748	{
bogdanm	86:04dd9b1680ae	749	uint32_t PeriphClockSelection; /*!< The Extended Clock to be configured.
bogdanm	86:04dd9b1680ae	750	This parameter can be a value of @ref RCCEx_Periph_Clock_Selection */
bogdanm	86:04dd9b1680ae	751
bogdanm	86:04dd9b1680ae	752	uint32_t RTCClockSelection; /*!< Specifies RTC Clock Prescalers Selection
bogdanm	86:04dd9b1680ae	753	This parameter can be a value of @ref RCC_RTC_Clock_Source */
bogdanm	86:04dd9b1680ae	754
bogdanm	86:04dd9b1680ae	755	uint32_t Usart1ClockSelection; /*!< USART1 clock source
bogdanm	86:04dd9b1680ae	756	This parameter can be a value of @ref RCCEx_USART1_Clock_Source */
bogdanm	86:04dd9b1680ae	757
bogdanm	86:04dd9b1680ae	758	uint32_t Usart2ClockSelection; /*!< USART2 clock source
bogdanm	86:04dd9b1680ae	759	This parameter can be a value of @ref RCC_USART2_Clock_Source */
bogdanm	86:04dd9b1680ae	760
bogdanm	86:04dd9b1680ae	761	uint32_t Usart3ClockSelection; /*!< USART3 clock source
bogdanm	86:04dd9b1680ae	762	This parameter can be a value of @ref RCC_USART3_Clock_Source */
bogdanm	86:04dd9b1680ae	763
bogdanm	86:04dd9b1680ae	764	uint32_t I2c1ClockSelection; /*!< I2C1 clock source
bogdanm	86:04dd9b1680ae	765	This parameter can be a value of @ref RCC_I2C1_Clock_Source */
bogdanm	86:04dd9b1680ae	766
bogdanm	86:04dd9b1680ae	767	uint32_t I2c2ClockSelection; /*!< I2C2 clock source
bogdanm	86:04dd9b1680ae	768	This parameter can be a value of @ref RCCEx_I2C2_Clock_Source */
bogdanm	86:04dd9b1680ae	769
bogdanm	86:04dd9b1680ae	770	uint32_t Adc1ClockSelection; /*!< ADC1 clock source
bogdanm	86:04dd9b1680ae	771	This parameter can be a value of @ref RCCEx_ADC1_Clock_Source */
bogdanm	86:04dd9b1680ae	772
bogdanm	86:04dd9b1680ae	773	uint32_t SdadcClockSelection; /*!< SDADC clock prescaler
bogdanm	86:04dd9b1680ae	774	This parameter can be a value of @ref RCCEx_SDADC_Clock_Prescaler */
bogdanm	86:04dd9b1680ae	775
bogdanm	86:04dd9b1680ae	776	uint32_t CecClockSelection; /*!< HDMI CEC clock source
bogdanm	86:04dd9b1680ae	777	This parameter can be a value of @ref RCCEx_CEC_Clock_Source */
bogdanm	86:04dd9b1680ae	778
bogdanm	86:04dd9b1680ae	779	}RCC_PeriphCLKInitTypeDef;
bogdanm	86:04dd9b1680ae	780	#endif /* STM32F378xx */
bogdanm	86:04dd9b1680ae	781
bogdanm	92:4fc01daae5a5	782	/**
bogdanm	92:4fc01daae5a5	783	* @}
bogdanm	92:4fc01daae5a5	784	*/
bogdanm	92:4fc01daae5a5	785
bogdanm	86:04dd9b1680ae	786	/* Exported constants --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	787	/** @defgroup RCCEx_Exported_Constants RCC Extended Exported Constants
bogdanm	92:4fc01daae5a5	788	* @{
bogdanm	92:4fc01daae5a5	789	*/
bogdanm	92:4fc01daae5a5	790	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	791	defined(STM32F334x8) \|\| \
bogdanm	92:4fc01daae5a5	792	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	92:4fc01daae5a5	793	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
bogdanm	92:4fc01daae5a5	794	* @{
bogdanm	92:4fc01daae5a5	795	*/
bogdanm	92:4fc01daae5a5	796	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
bogdanm	92:4fc01daae5a5	797	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
bogdanm	92:4fc01daae5a5	798	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
bogdanm	92:4fc01daae5a5	799	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
bogdanm	92:4fc01daae5a5	800	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
bogdanm	92:4fc01daae5a5	801	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
bogdanm	92:4fc01daae5a5	802	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
bogdanm	92:4fc01daae5a5	803
bogdanm	92:4fc01daae5a5	804	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	92:4fc01daae5a5	805	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	92:4fc01daae5a5	806	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	92:4fc01daae5a5	807	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	92:4fc01daae5a5	808	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	92:4fc01daae5a5	809	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	92:4fc01daae5a5	810	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
bogdanm	92:4fc01daae5a5	811	/**
bogdanm	92:4fc01daae5a5	812	* @}
bogdanm	92:4fc01daae5a5	813	*/
bogdanm	92:4fc01daae5a5	814	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	815	/* STM32F334x8 */
bogdanm	92:4fc01daae5a5	816	/* STM32F373xC \|\| STM32F378xx */
bogdanm	92:4fc01daae5a5	817
bogdanm	92:4fc01daae5a5	818	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	819	defined(STM32F303x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	820	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	92:4fc01daae5a5	821	/** @defgroup RCCEx_MCO_Clock_Source RCC Extended MCO Clock Source
bogdanm	92:4fc01daae5a5	822	* @{
bogdanm	92:4fc01daae5a5	823	*/
bogdanm	92:4fc01daae5a5	824	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
bogdanm	92:4fc01daae5a5	825	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
bogdanm	92:4fc01daae5a5	826	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
bogdanm	92:4fc01daae5a5	827	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
bogdanm	92:4fc01daae5a5	828	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
bogdanm	92:4fc01daae5a5	829	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
bogdanm	92:4fc01daae5a5	830	#define RCC_MCOSOURCE_PLLCLK_DIV1 (RCC_CFGR_PLLNODIV \| RCC_CFGR_MCO_PLL)
bogdanm	92:4fc01daae5a5	831	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
bogdanm	92:4fc01daae5a5	832
bogdanm	92:4fc01daae5a5	833	#define IS_RCC_MCOSOURCE(SOURCE) (((SOURCE) == RCC_MCOSOURCE_NONE) \|\| \
bogdanm	92:4fc01daae5a5	834	((SOURCE) == RCC_MCOSOURCE_LSI) \|\| \
bogdanm	92:4fc01daae5a5	835	((SOURCE) == RCC_MCOSOURCE_LSE) \|\| \
bogdanm	92:4fc01daae5a5	836	((SOURCE) == RCC_MCOSOURCE_SYSCLK) \|\| \
bogdanm	92:4fc01daae5a5	837	((SOURCE) == RCC_MCOSOURCE_HSI) \|\| \
bogdanm	92:4fc01daae5a5	838	((SOURCE) == RCC_MCOSOURCE_HSE) \|\| \
bogdanm	92:4fc01daae5a5	839	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV1) \|\| \
bogdanm	92:4fc01daae5a5	840	((SOURCE) == RCC_MCOSOURCE_PLLCLK_DIV2))
bogdanm	92:4fc01daae5a5	841	/**
bogdanm	92:4fc01daae5a5	842	* @}
bogdanm	92:4fc01daae5a5	843	*/
bogdanm	92:4fc01daae5a5	844	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	845	/* STM32F303x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	846	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	92:4fc01daae5a5	847
bogdanm	92:4fc01daae5a5	848	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	849	/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
bogdanm	92:4fc01daae5a5	850	* @{
bogdanm	92:4fc01daae5a5	851	*/
bogdanm	92:4fc01daae5a5	852	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_PREDIV
bogdanm	92:4fc01daae5a5	853	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
bogdanm	92:4fc01daae5a5	854
bogdanm	92:4fc01daae5a5	855	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	92:4fc01daae5a5	856	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	92:4fc01daae5a5	857	/**
bogdanm	92:4fc01daae5a5	858	* @}
bogdanm	92:4fc01daae5a5	859	*/
bogdanm	92:4fc01daae5a5	860
bogdanm	92:4fc01daae5a5	861	/** @defgroup RCCEx_PLL_Prediv_Factor RCC Extended PLL Prediv Factor
bogdanm	86:04dd9b1680ae	862	* @{
bogdanm	86:04dd9b1680ae	863	*/
bogdanm	92:4fc01daae5a5	864	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
bogdanm	92:4fc01daae5a5	865	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
bogdanm	92:4fc01daae5a5	866	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
bogdanm	92:4fc01daae5a5	867	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
bogdanm	92:4fc01daae5a5	868	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
bogdanm	92:4fc01daae5a5	869	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
bogdanm	92:4fc01daae5a5	870	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
bogdanm	92:4fc01daae5a5	871	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
bogdanm	92:4fc01daae5a5	872	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
bogdanm	92:4fc01daae5a5	873	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
bogdanm	92:4fc01daae5a5	874	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
bogdanm	92:4fc01daae5a5	875	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
bogdanm	92:4fc01daae5a5	876	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
bogdanm	92:4fc01daae5a5	877	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
bogdanm	92:4fc01daae5a5	878	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
bogdanm	92:4fc01daae5a5	879	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
bogdanm	92:4fc01daae5a5	880
bogdanm	92:4fc01daae5a5	881	#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) \|\| ((PREDIV) == RCC_PREDIV_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	882	((PREDIV) == RCC_PREDIV_DIV3) \|\| ((PREDIV) == RCC_PREDIV_DIV4) \|\| \
bogdanm	92:4fc01daae5a5	883	((PREDIV) == RCC_PREDIV_DIV5) \|\| ((PREDIV) == RCC_PREDIV_DIV6) \|\| \
bogdanm	92:4fc01daae5a5	884	((PREDIV) == RCC_PREDIV_DIV7) \|\| ((PREDIV) == RCC_PREDIV_DIV8) \|\| \
bogdanm	92:4fc01daae5a5	885	((PREDIV) == RCC_PREDIV_DIV9) \|\| ((PREDIV) == RCC_PREDIV_DIV10) \|\| \
bogdanm	92:4fc01daae5a5	886	((PREDIV) == RCC_PREDIV_DIV11) \|\| ((PREDIV) == RCC_PREDIV_DIV12) \|\| \
bogdanm	92:4fc01daae5a5	887	((PREDIV) == RCC_PREDIV_DIV13) \|\| ((PREDIV) == RCC_PREDIV_DIV14) \|\| \
bogdanm	92:4fc01daae5a5	888	((PREDIV) == RCC_PREDIV_DIV15) \|\| ((PREDIV) == RCC_PREDIV_DIV16))
bogdanm	92:4fc01daae5a5	889	/**
bogdanm	92:4fc01daae5a5	890	* @}
bogdanm	92:4fc01daae5a5	891	*/
bogdanm	92:4fc01daae5a5	892	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	893
bogdanm	92:4fc01daae5a5	894	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	895	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	896	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
bogdanm	92:4fc01daae5a5	897	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	92:4fc01daae5a5	898	/** @defgroup RCCEx_PLL_Clock_Source RCC Extended PLL Clock Source
bogdanm	92:4fc01daae5a5	899	* @{
bogdanm	92:4fc01daae5a5	900	*/
bogdanm	92:4fc01daae5a5	901	#define RCC_PLLSOURCE_HSI RCC_CFGR_PLLSRC_HSI_DIV2
bogdanm	92:4fc01daae5a5	902	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
bogdanm	92:4fc01daae5a5	903
bogdanm	92:4fc01daae5a5	904	#define IS_RCC_PLLSOURCE(SOURCE) (((SOURCE) == RCC_PLLSOURCE_HSI) \|\| \
bogdanm	92:4fc01daae5a5	905	((SOURCE) == RCC_PLLSOURCE_HSE))
bogdanm	92:4fc01daae5a5	906	/**
bogdanm	92:4fc01daae5a5	907	* @}
bogdanm	92:4fc01daae5a5	908	*/
bogdanm	92:4fc01daae5a5	909
bogdanm	92:4fc01daae5a5	910	/** @defgroup RCCEx_HSE_Predivision_Factor RCC Extended HSE Predivision Factor
bogdanm	92:4fc01daae5a5	911	* @{
bogdanm	92:4fc01daae5a5	912	*/
bogdanm	92:4fc01daae5a5	913
bogdanm	92:4fc01daae5a5	914	#define RCC_HSE_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
bogdanm	92:4fc01daae5a5	915	#define RCC_HSE_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
bogdanm	92:4fc01daae5a5	916	#define RCC_HSE_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
bogdanm	92:4fc01daae5a5	917	#define RCC_HSE_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
bogdanm	92:4fc01daae5a5	918	#define RCC_HSE_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
bogdanm	92:4fc01daae5a5	919	#define RCC_HSE_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
bogdanm	92:4fc01daae5a5	920	#define RCC_HSE_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
bogdanm	92:4fc01daae5a5	921	#define RCC_HSE_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
bogdanm	92:4fc01daae5a5	922	#define RCC_HSE_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
bogdanm	92:4fc01daae5a5	923	#define RCC_HSE_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
bogdanm	92:4fc01daae5a5	924	#define RCC_HSE_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
bogdanm	92:4fc01daae5a5	925	#define RCC_HSE_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
bogdanm	92:4fc01daae5a5	926	#define RCC_HSE_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
bogdanm	92:4fc01daae5a5	927	#define RCC_HSE_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
bogdanm	92:4fc01daae5a5	928	#define RCC_HSE_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
bogdanm	92:4fc01daae5a5	929	#define RCC_HSE_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
bogdanm	92:4fc01daae5a5	930
bogdanm	92:4fc01daae5a5	931	#define IS_RCC_HSE_PREDIV(DIV) (((DIV) == RCC_HSE_PREDIV_DIV1) \|\| ((DIV) == RCC_HSE_PREDIV_DIV2) \|\| \
bogdanm	92:4fc01daae5a5	932	((DIV) == RCC_HSE_PREDIV_DIV3) \|\| ((DIV) == RCC_HSE_PREDIV_DIV4) \|\| \
bogdanm	92:4fc01daae5a5	933	((DIV) == RCC_HSE_PREDIV_DIV5) \|\| ((DIV) == RCC_HSE_PREDIV_DIV6) \|\| \
bogdanm	92:4fc01daae5a5	934	((DIV) == RCC_HSE_PREDIV_DIV7) \|\| ((DIV) == RCC_HSE_PREDIV_DIV8) \|\| \
bogdanm	92:4fc01daae5a5	935	((DIV) == RCC_HSE_PREDIV_DIV9) \|\| ((DIV) == RCC_HSE_PREDIV_DIV10) \|\| \
bogdanm	92:4fc01daae5a5	936	((DIV) == RCC_HSE_PREDIV_DIV11) \|\| ((DIV) == RCC_HSE_PREDIV_DIV12) \|\| \
bogdanm	92:4fc01daae5a5	937	((DIV) == RCC_HSE_PREDIV_DIV13) \|\| ((DIV) == RCC_HSE_PREDIV_DIV14) \|\| \
bogdanm	92:4fc01daae5a5	938	((DIV) == RCC_HSE_PREDIV_DIV15) \|\| ((DIV) == RCC_HSE_PREDIV_DIV16))
bogdanm	92:4fc01daae5a5	939	/**
bogdanm	92:4fc01daae5a5	940	* @}
bogdanm	92:4fc01daae5a5	941	*/
bogdanm	92:4fc01daae5a5	942	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	943	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	944	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	92:4fc01daae5a5	945	/* STM32F373xC \|\| STM32F378xx */
bogdanm	92:4fc01daae5a5	946
bogdanm	92:4fc01daae5a5	947	/** @defgroup RCCEx_Periph_Clock_Selection RCC Extended Periph Clock Selection
bogdanm	86:04dd9b1680ae	948	* @{
bogdanm	86:04dd9b1680ae	949	*/
bogdanm	86:04dd9b1680ae	950	#if defined(STM32F301x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	951	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	952	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	953	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	954	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	955	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	956	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	957	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm	86:04dd9b1680ae	958	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	959	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
bogdanm	86:04dd9b1680ae	960	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	961	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
bogdanm	86:04dd9b1680ae	962	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
bogdanm	86:04dd9b1680ae	963	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
bogdanm	86:04dd9b1680ae	964
bogdanm	86:04dd9b1680ae	965	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	966	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	86:04dd9b1680ae	967	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
bogdanm	86:04dd9b1680ae	968	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
bogdanm	86:04dd9b1680ae	969	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
bogdanm	86:04dd9b1680ae	970	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_RTC))
bogdanm	86:04dd9b1680ae	971	#endif /* STM32F301x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	972
bogdanm	86:04dd9b1680ae	973	#if defined(STM32F302x8)
bogdanm	86:04dd9b1680ae	974	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	975	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	976	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	977	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	978	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	979	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	980	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm	86:04dd9b1680ae	981	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	982	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00008000)
bogdanm	86:04dd9b1680ae	983	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	984	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	86:04dd9b1680ae	985	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00040000)
bogdanm	86:04dd9b1680ae	986	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00080000)
bogdanm	86:04dd9b1680ae	987	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x00100000)
bogdanm	86:04dd9b1680ae	988
bogdanm	86:04dd9b1680ae	989	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	990	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	86:04dd9b1680ae	991	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_I2S \| \
bogdanm	86:04dd9b1680ae	992	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM1 \| \
bogdanm	86:04dd9b1680ae	993	RCC_PERIPHCLK_RTC \| RCC_PERIPHCLK_USB \| \
bogdanm	86:04dd9b1680ae	994	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
bogdanm	86:04dd9b1680ae	995	RCC_PERIPHCLK_TIM17))
bogdanm	86:04dd9b1680ae	996	#endif /* STM32F302x8 */
bogdanm	86:04dd9b1680ae	997
bogdanm	86:04dd9b1680ae	998	#if defined(STM32F302xC)
bogdanm	86:04dd9b1680ae	999	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	1000	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	1001	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	1002	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	1003	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	1004	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	1005	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	1006	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	1007	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm	86:04dd9b1680ae	1008	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	1009	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	1010	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	86:04dd9b1680ae	1011
bogdanm	86:04dd9b1680ae	1012	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	1013	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
bogdanm	86:04dd9b1680ae	1014	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	86:04dd9b1680ae	1015	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
bogdanm	86:04dd9b1680ae	1016	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
bogdanm	86:04dd9b1680ae	1017	RCC_PERIPHCLK_USB))
bogdanm	86:04dd9b1680ae	1018	#endif /* STM32F302xC */
bogdanm	86:04dd9b1680ae	1019
bogdanm	86:04dd9b1680ae	1020	#if defined(STM32F303xC)
bogdanm	86:04dd9b1680ae	1021	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	1022	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	1023	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	1024	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	1025	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	1026	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	1027	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	1028	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	1029	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm	86:04dd9b1680ae	1030	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm	86:04dd9b1680ae	1031	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	1032	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm	86:04dd9b1680ae	1033	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	1034	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	86:04dd9b1680ae	1035
bogdanm	86:04dd9b1680ae	1036	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	1037	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
bogdanm	86:04dd9b1680ae	1038	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	86:04dd9b1680ae	1039	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
bogdanm	86:04dd9b1680ae	1040	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
bogdanm	86:04dd9b1680ae	1041	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
bogdanm	86:04dd9b1680ae	1042	RCC_PERIPHCLK_USB))
bogdanm	86:04dd9b1680ae	1043	#endif /* STM32F303xC */
bogdanm	86:04dd9b1680ae	1044
bogdanm	92:4fc01daae5a5	1045	#if defined(STM32F302xE)
bogdanm	92:4fc01daae5a5	1046	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	1047	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	1048	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	1049	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	1050	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	1051	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	1052	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	1053	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	1054	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	1055	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	92:4fc01daae5a5	1056	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	1057	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	92:4fc01daae5a5	1058	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
bogdanm	92:4fc01daae5a5	1059	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
bogdanm	92:4fc01daae5a5	1060	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
bogdanm	92:4fc01daae5a5	1061	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
bogdanm	92:4fc01daae5a5	1062	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
bogdanm	92:4fc01daae5a5	1063	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
bogdanm	92:4fc01daae5a5	1064
bogdanm	92:4fc01daae5a5	1065	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	92:4fc01daae5a5	1066	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
bogdanm	92:4fc01daae5a5	1067	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	92:4fc01daae5a5	1068	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_I2S \| \
bogdanm	92:4fc01daae5a5	1069	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC \| \
bogdanm	92:4fc01daae5a5	1070	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
bogdanm	92:4fc01daae5a5	1071	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
bogdanm	92:4fc01daae5a5	1072	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
bogdanm	92:4fc01daae5a5	1073	RCC_PERIPHCLK_TIM17))
bogdanm	92:4fc01daae5a5	1074	#endif /* STM32F302xE */
bogdanm	92:4fc01daae5a5	1075
bogdanm	92:4fc01daae5a5	1076	#if defined(STM32F303xE)
bogdanm	92:4fc01daae5a5	1077	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	1078	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	1079	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	1080	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	1081	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	1082	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	1083	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	1084	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	1085	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	1086	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	1087	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	92:4fc01daae5a5	1088	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm	92:4fc01daae5a5	1089	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	1090	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	92:4fc01daae5a5	1091	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
bogdanm	92:4fc01daae5a5	1092	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
bogdanm	92:4fc01daae5a5	1093	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
bogdanm	92:4fc01daae5a5	1094	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
bogdanm	92:4fc01daae5a5	1095	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
bogdanm	92:4fc01daae5a5	1096	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
bogdanm	92:4fc01daae5a5	1097	#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
bogdanm	92:4fc01daae5a5	1098
bogdanm	92:4fc01daae5a5	1099	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	92:4fc01daae5a5	1100	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
bogdanm	92:4fc01daae5a5	1101	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	92:4fc01daae5a5	1102	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
bogdanm	92:4fc01daae5a5	1103	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
bogdanm	92:4fc01daae5a5	1104	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
bogdanm	92:4fc01daae5a5	1105	RCC_PERIPHCLK_USB \| RCC_PERIPHCLK_I2C3 \| \
bogdanm	92:4fc01daae5a5	1106	RCC_PERIPHCLK_TIM2 \| RCC_PERIPHCLK_TIM34 \| \
bogdanm	92:4fc01daae5a5	1107	RCC_PERIPHCLK_TIM15 \| RCC_PERIPHCLK_TIM16 \| \
bogdanm	92:4fc01daae5a5	1108	RCC_PERIPHCLK_TIM17 \| RCC_PERIPHCLK_TIM20))
bogdanm	92:4fc01daae5a5	1109	#endif /* STM32F303xE */
bogdanm	92:4fc01daae5a5	1110
bogdanm	92:4fc01daae5a5	1111	#if defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	1112	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	92:4fc01daae5a5	1113	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	92:4fc01daae5a5	1114	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	92:4fc01daae5a5	1115	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm	92:4fc01daae5a5	1116	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm	92:4fc01daae5a5	1117	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	92:4fc01daae5a5	1118	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	92:4fc01daae5a5	1119	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	92:4fc01daae5a5	1120	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm	92:4fc01daae5a5	1121	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm	92:4fc01daae5a5	1122	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	92:4fc01daae5a5	1123	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm	92:4fc01daae5a5	1124	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	92:4fc01daae5a5	1125	#define RCC_PERIPHCLK_I2C3 ((uint32_t)0x00040000)
bogdanm	92:4fc01daae5a5	1126	#define RCC_PERIPHCLK_TIM2 ((uint32_t)0x00100000)
bogdanm	92:4fc01daae5a5	1127	#define RCC_PERIPHCLK_TIM34 ((uint32_t)0x00200000)
bogdanm	92:4fc01daae5a5	1128	#define RCC_PERIPHCLK_TIM15 ((uint32_t)0x00400000)
bogdanm	92:4fc01daae5a5	1129	#define RCC_PERIPHCLK_TIM16 ((uint32_t)0x00800000)
bogdanm	92:4fc01daae5a5	1130	#define RCC_PERIPHCLK_TIM17 ((uint32_t)0x01000000)
bogdanm	92:4fc01daae5a5	1131	#define RCC_PERIPHCLK_TIM20 ((uint32_t)0x02000000)
bogdanm	92:4fc01daae5a5	1132
bogdanm	92:4fc01daae5a5	1133	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	92:4fc01daae5a5	1134	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
bogdanm	92:4fc01daae5a5	1135	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	92:4fc01daae5a5	1136	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
bogdanm	92:4fc01daae5a5	1137	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
bogdanm	92:4fc01daae5a5	1138	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC \| \
bogdanm	92:4fc01daae5a5	1139	RCC_PERIPHCLK_I2C3 \| RCC_PERIPHCLK_TIM2 \| \
bogdanm	92:4fc01daae5a5	1140	RCC_PERIPHCLK_TIM34 \| RCC_PERIPHCLK_TIM15 \| \
bogdanm	92:4fc01daae5a5	1141	RCC_PERIPHCLK_TIM16 \| RCC_PERIPHCLK_TIM17 \| \
bogdanm	92:4fc01daae5a5	1142	RCC_PERIPHCLK_TIM20))
bogdanm	92:4fc01daae5a5	1143	#endif /* STM32F398xx */
bogdanm	92:4fc01daae5a5	1144
bogdanm	86:04dd9b1680ae	1145	#if defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	1146	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	1147	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	1148	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	1149	#define RCC_PERIPHCLK_UART4 ((uint32_t)0x00000008)
bogdanm	86:04dd9b1680ae	1150	#define RCC_PERIPHCLK_UART5 ((uint32_t)0x00000010)
bogdanm	86:04dd9b1680ae	1151	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	1152	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	1153	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	1154	#define RCC_PERIPHCLK_ADC34 ((uint32_t)0x00000100)
bogdanm	86:04dd9b1680ae	1155	#define RCC_PERIPHCLK_I2S ((uint32_t)0x00000200)
bogdanm	86:04dd9b1680ae	1156	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	1157	#define RCC_PERIPHCLK_TIM8 ((uint32_t)0x00002000)
bogdanm	86:04dd9b1680ae	1158	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	1159
bogdanm	86:04dd9b1680ae	1160	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	1161	RCC_PERIPHCLK_UART4 \| RCC_PERIPHCLK_UART5 \| \
bogdanm	86:04dd9b1680ae	1162	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	86:04dd9b1680ae	1163	RCC_PERIPHCLK_ADC12 \| RCC_PERIPHCLK_ADC34 \| \
bogdanm	86:04dd9b1680ae	1164	RCC_PERIPHCLK_I2S \| RCC_PERIPHCLK_TIM1 \| \
bogdanm	86:04dd9b1680ae	1165	RCC_PERIPHCLK_TIM8 \| RCC_PERIPHCLK_RTC))
bogdanm	86:04dd9b1680ae	1166	#endif /* STM32F358xx */
bogdanm	86:04dd9b1680ae	1167
bogdanm	86:04dd9b1680ae	1168	#if defined(STM32F303x8)
bogdanm	86:04dd9b1680ae	1169	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	1170	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	1171	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	1172	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	1173	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	1174	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	1175	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	1176
bogdanm	86:04dd9b1680ae	1177	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	1178	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
bogdanm	86:04dd9b1680ae	1179	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
bogdanm	86:04dd9b1680ae	1180	#endif /* STM32F303x8 */
bogdanm	86:04dd9b1680ae	1181
bogdanm	86:04dd9b1680ae	1182	#if defined(STM32F334x8)
bogdanm	86:04dd9b1680ae	1183	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	1184	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	1185	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	1186	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	1187	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	1188	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	1189	#define RCC_PERIPHCLK_HRTIM1 ((uint32_t)0x00004000)
bogdanm	86:04dd9b1680ae	1190	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	1191
bogdanm	86:04dd9b1680ae	1192	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	1193	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
bogdanm	86:04dd9b1680ae	1194	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_HRTIM1 \| \
bogdanm	86:04dd9b1680ae	1195	RCC_PERIPHCLK_RTC))
bogdanm	86:04dd9b1680ae	1196	#endif /* STM32F334x8 */
bogdanm	86:04dd9b1680ae	1197
bogdanm	86:04dd9b1680ae	1198	#if defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	1199	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	1200	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	1201	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	1202	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	1203	#define RCC_PERIPHCLK_ADC12 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	1204	#define RCC_PERIPHCLK_TIM1 ((uint32_t)0x00001000)
bogdanm	86:04dd9b1680ae	1205	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	1206
bogdanm	86:04dd9b1680ae	1207	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	1208	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_ADC12 \| \
bogdanm	86:04dd9b1680ae	1209	RCC_PERIPHCLK_TIM1 \| RCC_PERIPHCLK_RTC))
bogdanm	86:04dd9b1680ae	1210	#endif /* STM32F328xx */
bogdanm	86:04dd9b1680ae	1211
bogdanm	86:04dd9b1680ae	1212	#if defined(STM32F373xC)
bogdanm	86:04dd9b1680ae	1213	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	1214	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	1215	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	1216	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	1217	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	1218	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	1219	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	86:04dd9b1680ae	1220	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
bogdanm	86:04dd9b1680ae	1221	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	1222	#define RCC_PERIPHCLK_USB ((uint32_t)0x00020000)
bogdanm	86:04dd9b1680ae	1223
bogdanm	86:04dd9b1680ae	1224	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	1225	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	86:04dd9b1680ae	1226	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
bogdanm	86:04dd9b1680ae	1227	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC \| \
bogdanm	86:04dd9b1680ae	1228	RCC_PERIPHCLK_USB))
bogdanm	86:04dd9b1680ae	1229	#endif /* STM32F373xC */
bogdanm	86:04dd9b1680ae	1230
bogdanm	86:04dd9b1680ae	1231	#if defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	1232	#define RCC_PERIPHCLK_USART1 ((uint32_t)0x00000001)
bogdanm	86:04dd9b1680ae	1233	#define RCC_PERIPHCLK_USART2 ((uint32_t)0x00000002)
bogdanm	86:04dd9b1680ae	1234	#define RCC_PERIPHCLK_USART3 ((uint32_t)0x00000004)
bogdanm	86:04dd9b1680ae	1235	#define RCC_PERIPHCLK_I2C1 ((uint32_t)0x00000020)
bogdanm	86:04dd9b1680ae	1236	#define RCC_PERIPHCLK_I2C2 ((uint32_t)0x00000040)
bogdanm	86:04dd9b1680ae	1237	#define RCC_PERIPHCLK_ADC1 ((uint32_t)0x00000080)
bogdanm	86:04dd9b1680ae	1238	#define RCC_PERIPHCLK_CEC ((uint32_t)0x00000400)
bogdanm	86:04dd9b1680ae	1239	#define RCC_PERIPHCLK_SDADC ((uint32_t)0x00000800)
bogdanm	86:04dd9b1680ae	1240	#define RCC_PERIPHCLK_RTC ((uint32_t)0x00010000)
bogdanm	86:04dd9b1680ae	1241
bogdanm	86:04dd9b1680ae	1242	#define IS_RCC_PERIPHCLK(SELECTION) ((SELECTION) <= (RCC_PERIPHCLK_USART1 \| RCC_PERIPHCLK_USART2 \| RCC_PERIPHCLK_USART3 \| \
bogdanm	86:04dd9b1680ae	1243	RCC_PERIPHCLK_I2C1 \| RCC_PERIPHCLK_I2C2 \| \
bogdanm	86:04dd9b1680ae	1244	RCC_PERIPHCLK_ADC1 \| RCC_PERIPHCLK_SDADC \| \
bogdanm	86:04dd9b1680ae	1245	RCC_PERIPHCLK_CEC \| RCC_PERIPHCLK_RTC))
bogdanm	86:04dd9b1680ae	1246	#endif /* STM32F378xx */
bogdanm	86:04dd9b1680ae	1247	/**
bogdanm	86:04dd9b1680ae	1248	* @}
bogdanm	86:04dd9b1680ae	1249	*/
bogdanm	86:04dd9b1680ae	1250
bogdanm	86:04dd9b1680ae	1251	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	1252
bogdanm	92:4fc01daae5a5	1253	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm	86:04dd9b1680ae	1254	* @{
bogdanm	86:04dd9b1680ae	1255	*/
bogdanm	86:04dd9b1680ae	1256	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
bogdanm	86:04dd9b1680ae	1257	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm	86:04dd9b1680ae	1258	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm	86:04dd9b1680ae	1259	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm	86:04dd9b1680ae	1260
bogdanm	86:04dd9b1680ae	1261	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
bogdanm	86:04dd9b1680ae	1262	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1263	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	1264	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	1265	/**
bogdanm	86:04dd9b1680ae	1266	* @}
bogdanm	86:04dd9b1680ae	1267	*/
bogdanm	86:04dd9b1680ae	1268
bogdanm	92:4fc01daae5a5	1269	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
bogdanm	86:04dd9b1680ae	1270	* @{
bogdanm	86:04dd9b1680ae	1271	*/
bogdanm	86:04dd9b1680ae	1272	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm	86:04dd9b1680ae	1273	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm	86:04dd9b1680ae	1274
bogdanm	86:04dd9b1680ae	1275	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	1276	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
bogdanm	86:04dd9b1680ae	1277	/**
bogdanm	86:04dd9b1680ae	1278	* @}
bogdanm	86:04dd9b1680ae	1279	*/
bogdanm	86:04dd9b1680ae	1280
bogdanm	92:4fc01daae5a5	1281	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
bogdanm	86:04dd9b1680ae	1282	* @{
bogdanm	86:04dd9b1680ae	1283	*/
bogdanm	86:04dd9b1680ae	1284	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
bogdanm	86:04dd9b1680ae	1285	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
bogdanm	86:04dd9b1680ae	1286
bogdanm	86:04dd9b1680ae	1287	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	1288	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
bogdanm	86:04dd9b1680ae	1289	/**
bogdanm	86:04dd9b1680ae	1290	* @}
bogdanm	86:04dd9b1680ae	1291	*/
bogdanm	86:04dd9b1680ae	1292
bogdanm	92:4fc01daae5a5	1293	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
bogdanm	86:04dd9b1680ae	1294	* @{
bogdanm	86:04dd9b1680ae	1295	*/
bogdanm	86:04dd9b1680ae	1296	#define RCC_ADC1PLLCLK_OFF RCC_CFGR2_ADC1PRES_NO
bogdanm	86:04dd9b1680ae	1297	#define RCC_ADC1PLLCLK_DIV1 RCC_CFGR2_ADC1PRES_DIV1
bogdanm	86:04dd9b1680ae	1298	#define RCC_ADC1PLLCLK_DIV2 RCC_CFGR2_ADC1PRES_DIV2
bogdanm	86:04dd9b1680ae	1299	#define RCC_ADC1PLLCLK_DIV4 RCC_CFGR2_ADC1PRES_DIV4
bogdanm	86:04dd9b1680ae	1300	#define RCC_ADC1PLLCLK_DIV6 RCC_CFGR2_ADC1PRES_DIV6
bogdanm	86:04dd9b1680ae	1301	#define RCC_ADC1PLLCLK_DIV8 RCC_CFGR2_ADC1PRES_DIV8
bogdanm	86:04dd9b1680ae	1302	#define RCC_ADC1PLLCLK_DIV10 RCC_CFGR2_ADC1PRES_DIV10
bogdanm	86:04dd9b1680ae	1303	#define RCC_ADC1PLLCLK_DIV12 RCC_CFGR2_ADC1PRES_DIV12
bogdanm	86:04dd9b1680ae	1304	#define RCC_ADC1PLLCLK_DIV16 RCC_CFGR2_ADC1PRES_DIV16
bogdanm	86:04dd9b1680ae	1305	#define RCC_ADC1PLLCLK_DIV32 RCC_CFGR2_ADC1PRES_DIV32
bogdanm	86:04dd9b1680ae	1306	#define RCC_ADC1PLLCLK_DIV64 RCC_CFGR2_ADC1PRES_DIV64
bogdanm	86:04dd9b1680ae	1307	#define RCC_ADC1PLLCLK_DIV128 RCC_CFGR2_ADC1PRES_DIV128
bogdanm	86:04dd9b1680ae	1308	#define RCC_ADC1PLLCLK_DIV256 RCC_CFGR2_ADC1PRES_DIV256
bogdanm	86:04dd9b1680ae	1309
bogdanm	86:04dd9b1680ae	1310	#define IS_RCC_ADC1PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV1) \|\| \
bogdanm	86:04dd9b1680ae	1311	((ADCCLK) == RCC_ADC1PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV4) \|\| \
bogdanm	86:04dd9b1680ae	1312	((ADCCLK) == RCC_ADC1PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	1313	((ADCCLK) == RCC_ADC1PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV12) \|\| \
bogdanm	86:04dd9b1680ae	1314	((ADCCLK) == RCC_ADC1PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV32) \|\| \
bogdanm	86:04dd9b1680ae	1315	((ADCCLK) == RCC_ADC1PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC1PLLCLK_DIV128) \|\| \
bogdanm	86:04dd9b1680ae	1316	((ADCCLK) == RCC_ADC1PLLCLK_DIV256))
bogdanm	86:04dd9b1680ae	1317	/**
bogdanm	86:04dd9b1680ae	1318	* @}
bogdanm	86:04dd9b1680ae	1319	*/
bogdanm	86:04dd9b1680ae	1320
bogdanm	92:4fc01daae5a5	1321	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
bogdanm	86:04dd9b1680ae	1322	* @{
bogdanm	86:04dd9b1680ae	1323	*/
bogdanm	86:04dd9b1680ae	1324	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
bogdanm	86:04dd9b1680ae	1325	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
bogdanm	86:04dd9b1680ae	1326
bogdanm	86:04dd9b1680ae	1327	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1328	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
bogdanm	86:04dd9b1680ae	1329	/**
bogdanm	86:04dd9b1680ae	1330	* @}
bogdanm	86:04dd9b1680ae	1331	*/
bogdanm	86:04dd9b1680ae	1332
bogdanm	92:4fc01daae5a5	1333	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
bogdanm	86:04dd9b1680ae	1334	* @{
bogdanm	86:04dd9b1680ae	1335	*/
bogdanm	86:04dd9b1680ae	1336	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm	86:04dd9b1680ae	1337	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm	86:04dd9b1680ae	1338
bogdanm	86:04dd9b1680ae	1339	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	1340	((SOURCE) == RCC_TIM1CLK_PLLCLK))
bogdanm	86:04dd9b1680ae	1341	/**
bogdanm	86:04dd9b1680ae	1342	* @}
bogdanm	86:04dd9b1680ae	1343	*/
bogdanm	86:04dd9b1680ae	1344
bogdanm	92:4fc01daae5a5	1345	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
bogdanm	86:04dd9b1680ae	1346	* @{
bogdanm	86:04dd9b1680ae	1347	*/
bogdanm	86:04dd9b1680ae	1348	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
bogdanm	86:04dd9b1680ae	1349	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
bogdanm	86:04dd9b1680ae	1350
bogdanm	86:04dd9b1680ae	1351	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	1352	((SOURCE) == RCC_TIM15CLK_PLLCLK))
bogdanm	86:04dd9b1680ae	1353	/**
bogdanm	86:04dd9b1680ae	1354	* @}
bogdanm	86:04dd9b1680ae	1355	*/
bogdanm	86:04dd9b1680ae	1356
bogdanm	92:4fc01daae5a5	1357	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
bogdanm	86:04dd9b1680ae	1358	* @{
bogdanm	86:04dd9b1680ae	1359	*/
bogdanm	86:04dd9b1680ae	1360	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
bogdanm	86:04dd9b1680ae	1361	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
bogdanm	86:04dd9b1680ae	1362
bogdanm	86:04dd9b1680ae	1363	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	1364	((SOURCE) == RCC_TIM16CLK_PLLCLK))
bogdanm	86:04dd9b1680ae	1365	/**
bogdanm	86:04dd9b1680ae	1366	* @}
bogdanm	86:04dd9b1680ae	1367	*/
bogdanm	86:04dd9b1680ae	1368
bogdanm	92:4fc01daae5a5	1369	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
bogdanm	86:04dd9b1680ae	1370	* @{
bogdanm	86:04dd9b1680ae	1371	*/
bogdanm	86:04dd9b1680ae	1372	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
bogdanm	86:04dd9b1680ae	1373	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
bogdanm	86:04dd9b1680ae	1374
bogdanm	86:04dd9b1680ae	1375	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	1376	((SOURCE) == RCC_TIM17CLK_PLLCLK))
bogdanm	86:04dd9b1680ae	1377	/**
bogdanm	86:04dd9b1680ae	1378	* @}
bogdanm	86:04dd9b1680ae	1379	*/
bogdanm	86:04dd9b1680ae	1380
bogdanm	86:04dd9b1680ae	1381	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	1382
bogdanm	86:04dd9b1680ae	1383	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	1384
bogdanm	92:4fc01daae5a5	1385	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm	86:04dd9b1680ae	1386	* @{
bogdanm	86:04dd9b1680ae	1387	*/
bogdanm	86:04dd9b1680ae	1388	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
bogdanm	86:04dd9b1680ae	1389	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm	86:04dd9b1680ae	1390	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm	86:04dd9b1680ae	1391	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm	86:04dd9b1680ae	1392
bogdanm	86:04dd9b1680ae	1393	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
bogdanm	86:04dd9b1680ae	1394	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1395	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	1396	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	1397	/**
bogdanm	86:04dd9b1680ae	1398	* @}
bogdanm	86:04dd9b1680ae	1399	*/
bogdanm	86:04dd9b1680ae	1400
bogdanm	92:4fc01daae5a5	1401	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
bogdanm	86:04dd9b1680ae	1402	* @{
bogdanm	86:04dd9b1680ae	1403	*/
bogdanm	86:04dd9b1680ae	1404	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm	86:04dd9b1680ae	1405	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm	86:04dd9b1680ae	1406
bogdanm	86:04dd9b1680ae	1407	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	1408	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
bogdanm	86:04dd9b1680ae	1409	/**
bogdanm	86:04dd9b1680ae	1410	* @}
bogdanm	86:04dd9b1680ae	1411	*/
bogdanm	86:04dd9b1680ae	1412
bogdanm	92:4fc01daae5a5	1413	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
bogdanm	86:04dd9b1680ae	1414	* @{
bogdanm	86:04dd9b1680ae	1415	*/
bogdanm	86:04dd9b1680ae	1416
bogdanm	86:04dd9b1680ae	1417	/* ADC1 & ADC2 */
bogdanm	86:04dd9b1680ae	1418	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
bogdanm	86:04dd9b1680ae	1419	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
bogdanm	86:04dd9b1680ae	1420	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
bogdanm	86:04dd9b1680ae	1421	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
bogdanm	86:04dd9b1680ae	1422	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
bogdanm	86:04dd9b1680ae	1423	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
bogdanm	86:04dd9b1680ae	1424	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
bogdanm	86:04dd9b1680ae	1425	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
bogdanm	86:04dd9b1680ae	1426	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
bogdanm	86:04dd9b1680ae	1427	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
bogdanm	86:04dd9b1680ae	1428	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
bogdanm	86:04dd9b1680ae	1429	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
bogdanm	86:04dd9b1680ae	1430	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
bogdanm	86:04dd9b1680ae	1431
bogdanm	86:04dd9b1680ae	1432	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
bogdanm	86:04dd9b1680ae	1433	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
bogdanm	86:04dd9b1680ae	1434	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	1435	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
bogdanm	86:04dd9b1680ae	1436	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
bogdanm	86:04dd9b1680ae	1437	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
bogdanm	86:04dd9b1680ae	1438	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
bogdanm	86:04dd9b1680ae	1439	/**
bogdanm	86:04dd9b1680ae	1440	* @}
bogdanm	86:04dd9b1680ae	1441	*/
bogdanm	86:04dd9b1680ae	1442
bogdanm	92:4fc01daae5a5	1443	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
bogdanm	86:04dd9b1680ae	1444	* @{
bogdanm	86:04dd9b1680ae	1445	*/
bogdanm	86:04dd9b1680ae	1446	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
bogdanm	86:04dd9b1680ae	1447	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
bogdanm	86:04dd9b1680ae	1448
bogdanm	86:04dd9b1680ae	1449	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1450	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
bogdanm	86:04dd9b1680ae	1451	/**
bogdanm	86:04dd9b1680ae	1452	* @}
bogdanm	86:04dd9b1680ae	1453	*/
bogdanm	92:4fc01daae5a5	1454	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
bogdanm	86:04dd9b1680ae	1455	* @{
bogdanm	86:04dd9b1680ae	1456	*/
bogdanm	86:04dd9b1680ae	1457	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm	86:04dd9b1680ae	1458	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm	86:04dd9b1680ae	1459
bogdanm	86:04dd9b1680ae	1460	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	1461	((SOURCE) == RCC_TIM1CLK_PLLCLK))
bogdanm	86:04dd9b1680ae	1462	/**
bogdanm	86:04dd9b1680ae	1463	* @}
bogdanm	86:04dd9b1680ae	1464	*/
bogdanm	86:04dd9b1680ae	1465
bogdanm	92:4fc01daae5a5	1466	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
bogdanm	86:04dd9b1680ae	1467	* @{
bogdanm	86:04dd9b1680ae	1468	*/
bogdanm	86:04dd9b1680ae	1469	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
bogdanm	86:04dd9b1680ae	1470	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
bogdanm	86:04dd9b1680ae	1471	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
bogdanm	86:04dd9b1680ae	1472	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
bogdanm	86:04dd9b1680ae	1473
bogdanm	86:04dd9b1680ae	1474	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
bogdanm	86:04dd9b1680ae	1475	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1476	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	1477	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	1478	/**
bogdanm	86:04dd9b1680ae	1479	* @}
bogdanm	86:04dd9b1680ae	1480	*/
bogdanm	86:04dd9b1680ae	1481
bogdanm	92:4fc01daae5a5	1482	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
bogdanm	86:04dd9b1680ae	1483	* @{
bogdanm	86:04dd9b1680ae	1484	*/
bogdanm	86:04dd9b1680ae	1485	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
bogdanm	86:04dd9b1680ae	1486	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
bogdanm	86:04dd9b1680ae	1487	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
bogdanm	86:04dd9b1680ae	1488	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
bogdanm	86:04dd9b1680ae	1489
bogdanm	86:04dd9b1680ae	1490	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
bogdanm	86:04dd9b1680ae	1491	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1492	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	1493	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	1494	/**
bogdanm	86:04dd9b1680ae	1495	* @}
bogdanm	86:04dd9b1680ae	1496	*/
bogdanm	86:04dd9b1680ae	1497
bogdanm	86:04dd9b1680ae	1498	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	1499
bogdanm	92:4fc01daae5a5	1500	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	1501
bogdanm	92:4fc01daae5a5	1502	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm	86:04dd9b1680ae	1503	* @{
bogdanm	86:04dd9b1680ae	1504	*/
bogdanm	86:04dd9b1680ae	1505	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
bogdanm	86:04dd9b1680ae	1506	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm	86:04dd9b1680ae	1507	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm	86:04dd9b1680ae	1508	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm	86:04dd9b1680ae	1509
bogdanm	86:04dd9b1680ae	1510	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
bogdanm	86:04dd9b1680ae	1511	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1512	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	1513	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	1514	/**
bogdanm	86:04dd9b1680ae	1515	* @}
bogdanm	86:04dd9b1680ae	1516	*/
bogdanm	86:04dd9b1680ae	1517
bogdanm	92:4fc01daae5a5	1518	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
bogdanm	92:4fc01daae5a5	1519	* @{
bogdanm	92:4fc01daae5a5	1520	*/
bogdanm	92:4fc01daae5a5	1521	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm	92:4fc01daae5a5	1522	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm	92:4fc01daae5a5	1523
bogdanm	92:4fc01daae5a5	1524	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
bogdanm	92:4fc01daae5a5	1525	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
bogdanm	92:4fc01daae5a5	1526	/**
bogdanm	92:4fc01daae5a5	1527	* @}
bogdanm	92:4fc01daae5a5	1528	*/
bogdanm	92:4fc01daae5a5	1529
bogdanm	92:4fc01daae5a5	1530	/** @defgroup RCCEx_I2C3_Clock_Source RCC Extended I2C3 Clock Source
bogdanm	92:4fc01daae5a5	1531	* @{
bogdanm	92:4fc01daae5a5	1532	*/
bogdanm	92:4fc01daae5a5	1533	#define RCC_I2C3CLKSOURCE_HSI RCC_CFGR3_I2C3SW_HSI
bogdanm	92:4fc01daae5a5	1534	#define RCC_I2C3CLKSOURCE_SYSCLK RCC_CFGR3_I2C3SW_SYSCLK
bogdanm	92:4fc01daae5a5	1535
bogdanm	92:4fc01daae5a5	1536	#define IS_RCC_I2C3CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C3CLKSOURCE_HSI) \|\| \
bogdanm	92:4fc01daae5a5	1537	((SOURCE) == RCC_I2C3CLKSOURCE_SYSCLK))
bogdanm	92:4fc01daae5a5	1538	/**
bogdanm	92:4fc01daae5a5	1539	* @}
bogdanm	92:4fc01daae5a5	1540	*/
bogdanm	92:4fc01daae5a5	1541
bogdanm	92:4fc01daae5a5	1542	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
bogdanm	92:4fc01daae5a5	1543	* @{
bogdanm	92:4fc01daae5a5	1544	*/
bogdanm	92:4fc01daae5a5	1545
bogdanm	92:4fc01daae5a5	1546	/* ADC1 & ADC2 */
bogdanm	92:4fc01daae5a5	1547	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
bogdanm	92:4fc01daae5a5	1548	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
bogdanm	92:4fc01daae5a5	1549	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
bogdanm	92:4fc01daae5a5	1550	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
bogdanm	92:4fc01daae5a5	1551	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
bogdanm	92:4fc01daae5a5	1552	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
bogdanm	92:4fc01daae5a5	1553	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
bogdanm	92:4fc01daae5a5	1554	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
bogdanm	92:4fc01daae5a5	1555	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
bogdanm	92:4fc01daae5a5	1556	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
bogdanm	92:4fc01daae5a5	1557	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
bogdanm	92:4fc01daae5a5	1558	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
bogdanm	92:4fc01daae5a5	1559	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
bogdanm	92:4fc01daae5a5	1560
bogdanm	92:4fc01daae5a5	1561	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
bogdanm	92:4fc01daae5a5	1562	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
bogdanm	92:4fc01daae5a5	1563	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
bogdanm	92:4fc01daae5a5	1564	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
bogdanm	92:4fc01daae5a5	1565	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
bogdanm	92:4fc01daae5a5	1566	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
bogdanm	92:4fc01daae5a5	1567	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
bogdanm	92:4fc01daae5a5	1568	/**
bogdanm	92:4fc01daae5a5	1569	* @}
bogdanm	92:4fc01daae5a5	1570	*/
bogdanm	92:4fc01daae5a5	1571
bogdanm	92:4fc01daae5a5	1572	/** @defgroup RCCEx_I2S_Clock_Source RCC Extended I2S Clock Source
bogdanm	92:4fc01daae5a5	1573	* @{
bogdanm	92:4fc01daae5a5	1574	*/
bogdanm	92:4fc01daae5a5	1575	#define RCC_I2SCLKSOURCE_SYSCLK RCC_CFGR_I2SSRC_SYSCLK
bogdanm	92:4fc01daae5a5	1576	#define RCC_I2SCLKSOURCE_EXT RCC_CFGR_I2SSRC_EXT
bogdanm	92:4fc01daae5a5	1577
bogdanm	92:4fc01daae5a5	1578	#define IS_RCC_I2SCLKSOURCE(SOURCE) (((SOURCE) == RCC_I2SCLKSOURCE_SYSCLK) \|\| \
bogdanm	92:4fc01daae5a5	1579	((SOURCE) == RCC_I2SCLKSOURCE_EXT))
bogdanm	92:4fc01daae5a5	1580	/**
bogdanm	92:4fc01daae5a5	1581	* @}
bogdanm	92:4fc01daae5a5	1582	*/
bogdanm	92:4fc01daae5a5	1583
bogdanm	92:4fc01daae5a5	1584	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
bogdanm	92:4fc01daae5a5	1585	* @{
bogdanm	92:4fc01daae5a5	1586	*/
bogdanm	92:4fc01daae5a5	1587	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm	92:4fc01daae5a5	1588	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm	92:4fc01daae5a5	1589
bogdanm	92:4fc01daae5a5	1590	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
bogdanm	92:4fc01daae5a5	1591	((SOURCE) == RCC_TIM1CLK_PLLCLK))
bogdanm	92:4fc01daae5a5	1592	/**
bogdanm	92:4fc01daae5a5	1593	* @}
bogdanm	92:4fc01daae5a5	1594	*/
bogdanm	92:4fc01daae5a5	1595
bogdanm	92:4fc01daae5a5	1596	/** @defgroup RCCEx_TIM2_Clock_Source RCC Extended TIM2 Clock Source
bogdanm	92:4fc01daae5a5	1597	* @{
bogdanm	92:4fc01daae5a5	1598	*/
bogdanm	92:4fc01daae5a5	1599	#define RCC_TIM2CLK_HCLK RCC_CFGR3_TIM2SW_HCLK
bogdanm	92:4fc01daae5a5	1600	#define RCC_TIM2CLK_PLLCLK RCC_CFGR3_TIM2SW_PLL
bogdanm	92:4fc01daae5a5	1601
bogdanm	92:4fc01daae5a5	1602	#define IS_RCC_TIM2CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM2CLK_HCLK) \|\| \
bogdanm	92:4fc01daae5a5	1603	((SOURCE) == RCC_TIM2CLK_PLLCLK))
bogdanm	92:4fc01daae5a5	1604	/**
bogdanm	92:4fc01daae5a5	1605	* @}
bogdanm	92:4fc01daae5a5	1606	*/
bogdanm	92:4fc01daae5a5	1607
bogdanm	92:4fc01daae5a5	1608	/** @defgroup RCCEx_TIM34_Clock_Source RCC Extended TIM3 & TIM4 Clock Source
bogdanm	92:4fc01daae5a5	1609	* @{
bogdanm	92:4fc01daae5a5	1610	*/
bogdanm	92:4fc01daae5a5	1611	#define RCC_TIM34CLK_HCLK RCC_CFGR3_TIM34SW_HCLK
bogdanm	92:4fc01daae5a5	1612	#define RCC_TIM34CLK_PLLCLK RCC_CFGR3_TIM34SW_PLL
bogdanm	92:4fc01daae5a5	1613
bogdanm	92:4fc01daae5a5	1614	#define IS_RCC_TIM3CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM34CLK_HCLK) \|\| \
bogdanm	92:4fc01daae5a5	1615	((SOURCE) == RCC_TIM34CLK_PLLCLK))
bogdanm	92:4fc01daae5a5	1616	/**
bogdanm	92:4fc01daae5a5	1617	* @}
bogdanm	92:4fc01daae5a5	1618	*/
bogdanm	92:4fc01daae5a5	1619
bogdanm	92:4fc01daae5a5	1620	/** @defgroup RCCEx_TIM15_Clock_Source RCC Extended TIM15 Clock Source
bogdanm	92:4fc01daae5a5	1621	* @{
bogdanm	92:4fc01daae5a5	1622	*/
bogdanm	92:4fc01daae5a5	1623	#define RCC_TIM15CLK_HCLK RCC_CFGR3_TIM15SW_HCLK
bogdanm	92:4fc01daae5a5	1624	#define RCC_TIM15CLK_PLLCLK RCC_CFGR3_TIM15SW_PLL
bogdanm	92:4fc01daae5a5	1625
bogdanm	92:4fc01daae5a5	1626	#define IS_RCC_TIM15CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM15CLK_HCLK) \|\| \
bogdanm	92:4fc01daae5a5	1627	((SOURCE) == RCC_TIM15CLK_PLLCLK))
bogdanm	92:4fc01daae5a5	1628	/**
bogdanm	92:4fc01daae5a5	1629	* @}
bogdanm	92:4fc01daae5a5	1630	*/
bogdanm	92:4fc01daae5a5	1631
bogdanm	92:4fc01daae5a5	1632	/** @defgroup RCCEx_TIM16_Clock_Source RCC Extended TIM16 Clock Source
bogdanm	92:4fc01daae5a5	1633	* @{
bogdanm	92:4fc01daae5a5	1634	*/
bogdanm	92:4fc01daae5a5	1635	#define RCC_TIM16CLK_HCLK RCC_CFGR3_TIM16SW_HCLK
bogdanm	92:4fc01daae5a5	1636	#define RCC_TIM16CLK_PLLCLK RCC_CFGR3_TIM16SW_PLL
bogdanm	92:4fc01daae5a5	1637
bogdanm	92:4fc01daae5a5	1638	#define IS_RCC_TIM16CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM16CLK_HCLK) \|\| \
bogdanm	92:4fc01daae5a5	1639	((SOURCE) == RCC_TIM16CLK_PLLCLK))
bogdanm	92:4fc01daae5a5	1640	/**
bogdanm	92:4fc01daae5a5	1641	* @}
bogdanm	92:4fc01daae5a5	1642	*/
bogdanm	92:4fc01daae5a5	1643
bogdanm	92:4fc01daae5a5	1644	/** @defgroup RCCEx_TIM17_Clock_Source RCC Extended TIM17 Clock Source
bogdanm	92:4fc01daae5a5	1645	* @{
bogdanm	92:4fc01daae5a5	1646	*/
bogdanm	92:4fc01daae5a5	1647	#define RCC_TIM17CLK_HCLK RCC_CFGR3_TIM17SW_HCLK
bogdanm	92:4fc01daae5a5	1648	#define RCC_TIM17CLK_PLLCLK RCC_CFGR3_TIM17SW_PLL
bogdanm	92:4fc01daae5a5	1649
bogdanm	92:4fc01daae5a5	1650	#define IS_RCC_TIM17CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM17CLK_HCLK) \|\| \
bogdanm	92:4fc01daae5a5	1651	((SOURCE) == RCC_TIM17CLK_PLLCLK))
bogdanm	92:4fc01daae5a5	1652	/**
bogdanm	92:4fc01daae5a5	1653	* @}
bogdanm	92:4fc01daae5a5	1654	*/
bogdanm	92:4fc01daae5a5	1655
bogdanm	92:4fc01daae5a5	1656	/** @defgroup RCCEx_UART4_Clock_Source RCC Extended UART4 Clock Source
bogdanm	92:4fc01daae5a5	1657	* @{
bogdanm	92:4fc01daae5a5	1658	*/
bogdanm	92:4fc01daae5a5	1659	#define RCC_UART4CLKSOURCE_PCLK1 RCC_CFGR3_UART4SW_PCLK
bogdanm	92:4fc01daae5a5	1660	#define RCC_UART4CLKSOURCE_SYSCLK RCC_CFGR3_UART4SW_SYSCLK
bogdanm	92:4fc01daae5a5	1661	#define RCC_UART4CLKSOURCE_LSE RCC_CFGR3_UART4SW_LSE
bogdanm	92:4fc01daae5a5	1662	#define RCC_UART4CLKSOURCE_HSI RCC_CFGR3_UART4SW_HSI
bogdanm	92:4fc01daae5a5	1663
bogdanm	92:4fc01daae5a5	1664	#define IS_RCC_UART4CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART4CLKSOURCE_PCLK1) \|\| \
bogdanm	92:4fc01daae5a5	1665	((SOURCE) == RCC_UART4CLKSOURCE_SYSCLK) \|\| \
bogdanm	92:4fc01daae5a5	1666	((SOURCE) == RCC_UART4CLKSOURCE_LSE) \|\| \
bogdanm	92:4fc01daae5a5	1667	((SOURCE) == RCC_UART4CLKSOURCE_HSI))
bogdanm	92:4fc01daae5a5	1668	/**
bogdanm	92:4fc01daae5a5	1669	* @}
bogdanm	92:4fc01daae5a5	1670	*/
bogdanm	92:4fc01daae5a5	1671
bogdanm	92:4fc01daae5a5	1672	/** @defgroup RCCEx_UART5_Clock_Source RCC Extended UART5 Clock Source
bogdanm	92:4fc01daae5a5	1673	* @{
bogdanm	92:4fc01daae5a5	1674	*/
bogdanm	92:4fc01daae5a5	1675	#define RCC_UART5CLKSOURCE_PCLK1 RCC_CFGR3_UART5SW_PCLK
bogdanm	92:4fc01daae5a5	1676	#define RCC_UART5CLKSOURCE_SYSCLK RCC_CFGR3_UART5SW_SYSCLK
bogdanm	92:4fc01daae5a5	1677	#define RCC_UART5CLKSOURCE_LSE RCC_CFGR3_UART5SW_LSE
bogdanm	92:4fc01daae5a5	1678	#define RCC_UART5CLKSOURCE_HSI RCC_CFGR3_UART5SW_HSI
bogdanm	92:4fc01daae5a5	1679
bogdanm	92:4fc01daae5a5	1680	#define IS_RCC_UART5CLKSOURCE(SOURCE) (((SOURCE) == RCC_UART5CLKSOURCE_PCLK1) \|\| \
bogdanm	92:4fc01daae5a5	1681	((SOURCE) == RCC_UART5CLKSOURCE_SYSCLK) \|\| \
bogdanm	92:4fc01daae5a5	1682	((SOURCE) == RCC_UART5CLKSOURCE_LSE) \|\| \
bogdanm	92:4fc01daae5a5	1683	((SOURCE) == RCC_UART5CLKSOURCE_HSI))
bogdanm	92:4fc01daae5a5	1684	/**
bogdanm	92:4fc01daae5a5	1685	* @}
bogdanm	92:4fc01daae5a5	1686	*/
bogdanm	92:4fc01daae5a5	1687
bogdanm	92:4fc01daae5a5	1688	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	1689
bogdanm	92:4fc01daae5a5	1690	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	1691	/** @defgroup RCCEx_TIM20_Clock_Source RCC Extended TIM20 Clock Source
bogdanm	92:4fc01daae5a5	1692	* @{
bogdanm	92:4fc01daae5a5	1693	*/
bogdanm	92:4fc01daae5a5	1694	#define RCC_TIM20CLK_HCLK RCC_CFGR3_TIM20SW_HCLK
bogdanm	92:4fc01daae5a5	1695	#define RCC_TIM20CLK_PLLCLK RCC_CFGR3_TIM20SW_PLL
bogdanm	92:4fc01daae5a5	1696
bogdanm	92:4fc01daae5a5	1697	#define IS_RCC_TIM20CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM20CLK_HCLK) \|\| \
bogdanm	92:4fc01daae5a5	1698	((SOURCE) == RCC_TIM20CLK_PLLCLK))
bogdanm	92:4fc01daae5a5	1699	/**
bogdanm	92:4fc01daae5a5	1700	* @}
bogdanm	92:4fc01daae5a5	1701	*/
bogdanm	92:4fc01daae5a5	1702	#endif /* STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	1703
bogdanm	92:4fc01daae5a5	1704	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	1705	defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	92:4fc01daae5a5	1706
bogdanm	92:4fc01daae5a5	1707	/** @defgroup RCCEx_ADC34_Clock_Source RCC Extended ADC34 Clock Source
bogdanm	86:04dd9b1680ae	1708	* @{
bogdanm	86:04dd9b1680ae	1709	*/
bogdanm	86:04dd9b1680ae	1710
bogdanm	86:04dd9b1680ae	1711	/* ADC3 & ADC4 */
bogdanm	86:04dd9b1680ae	1712	#define RCC_ADC34PLLCLK_OFF RCC_CFGR2_ADCPRE34_NO
bogdanm	86:04dd9b1680ae	1713	#define RCC_ADC34PLLCLK_DIV1 RCC_CFGR2_ADCPRE34_DIV1
bogdanm	86:04dd9b1680ae	1714	#define RCC_ADC34PLLCLK_DIV2 RCC_CFGR2_ADCPRE34_DIV2
bogdanm	86:04dd9b1680ae	1715	#define RCC_ADC34PLLCLK_DIV4 RCC_CFGR2_ADCPRE34_DIV4
bogdanm	86:04dd9b1680ae	1716	#define RCC_ADC34PLLCLK_DIV6 RCC_CFGR2_ADCPRE34_DIV6
bogdanm	86:04dd9b1680ae	1717	#define RCC_ADC34PLLCLK_DIV8 RCC_CFGR2_ADCPRE34_DIV8
bogdanm	86:04dd9b1680ae	1718	#define RCC_ADC34PLLCLK_DIV10 RCC_CFGR2_ADCPRE34_DIV10
bogdanm	86:04dd9b1680ae	1719	#define RCC_ADC34PLLCLK_DIV12 RCC_CFGR2_ADCPRE34_DIV12
bogdanm	86:04dd9b1680ae	1720	#define RCC_ADC34PLLCLK_DIV16 RCC_CFGR2_ADCPRE34_DIV16
bogdanm	86:04dd9b1680ae	1721	#define RCC_ADC34PLLCLK_DIV32 RCC_CFGR2_ADCPRE34_DIV32
bogdanm	86:04dd9b1680ae	1722	#define RCC_ADC34PLLCLK_DIV64 RCC_CFGR2_ADCPRE34_DIV64
bogdanm	86:04dd9b1680ae	1723	#define RCC_ADC34PLLCLK_DIV128 RCC_CFGR2_ADCPRE34_DIV128
bogdanm	86:04dd9b1680ae	1724	#define RCC_ADC34PLLCLK_DIV256 RCC_CFGR2_ADCPRE34_DIV256
bogdanm	86:04dd9b1680ae	1725
bogdanm	86:04dd9b1680ae	1726	#define IS_RCC_ADC34PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC34PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV1) \|\| \
bogdanm	86:04dd9b1680ae	1727	((ADCCLK) == RCC_ADC34PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV4) \|\| \
bogdanm	86:04dd9b1680ae	1728	((ADCCLK) == RCC_ADC34PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	1729	((ADCCLK) == RCC_ADC34PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV12) \|\| \
bogdanm	86:04dd9b1680ae	1730	((ADCCLK) == RCC_ADC34PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV32) \|\| \
bogdanm	86:04dd9b1680ae	1731	((ADCCLK) == RCC_ADC34PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC34PLLCLK_DIV128) \|\| \
bogdanm	86:04dd9b1680ae	1732	((ADCCLK) == RCC_ADC34PLLCLK_DIV256))
bogdanm	86:04dd9b1680ae	1733	/**
bogdanm	86:04dd9b1680ae	1734	* @}
bogdanm	86:04dd9b1680ae	1735	*/
bogdanm	86:04dd9b1680ae	1736
bogdanm	92:4fc01daae5a5	1737	/** @defgroup RCCEx_TIM8_Clock_Source RCC Extended TIM8 Clock Source
bogdanm	86:04dd9b1680ae	1738	* @{
bogdanm	86:04dd9b1680ae	1739	*/
bogdanm	86:04dd9b1680ae	1740	#define RCC_TIM8CLK_HCLK RCC_CFGR3_TIM8SW_HCLK
bogdanm	86:04dd9b1680ae	1741	#define RCC_TIM8CLK_PLLCLK RCC_CFGR3_TIM8SW_PLL
bogdanm	86:04dd9b1680ae	1742
bogdanm	86:04dd9b1680ae	1743	#define IS_RCC_TIM8CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM8CLK_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	1744	((SOURCE) == RCC_TIM8CLK_PLLCLK))
bogdanm	86:04dd9b1680ae	1745	/**
bogdanm	86:04dd9b1680ae	1746	* @}
bogdanm	86:04dd9b1680ae	1747	*/
bogdanm	86:04dd9b1680ae	1748
bogdanm	92:4fc01daae5a5	1749	#endif /* STM32F303xC \|\| STM32F303xE \|\| STM32F398xx \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	1750
bogdanm	86:04dd9b1680ae	1751	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	1752
bogdanm	92:4fc01daae5a5	1753	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm	86:04dd9b1680ae	1754	* @{
bogdanm	86:04dd9b1680ae	1755	*/
bogdanm	86:04dd9b1680ae	1756	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
bogdanm	86:04dd9b1680ae	1757	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm	86:04dd9b1680ae	1758	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm	86:04dd9b1680ae	1759	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm	86:04dd9b1680ae	1760
bogdanm	86:04dd9b1680ae	1761	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
bogdanm	86:04dd9b1680ae	1762	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1763	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	1764	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	1765	/**
bogdanm	86:04dd9b1680ae	1766	* @}
bogdanm	86:04dd9b1680ae	1767	*/
bogdanm	86:04dd9b1680ae	1768
bogdanm	92:4fc01daae5a5	1769	/** @defgroup RCCEx_ADC12_Clock_Source RCC Extended ADC12 Clock Source
bogdanm	86:04dd9b1680ae	1770	* @{
bogdanm	86:04dd9b1680ae	1771	*/
bogdanm	86:04dd9b1680ae	1772	/* ADC1 & ADC2 */
bogdanm	86:04dd9b1680ae	1773	#define RCC_ADC12PLLCLK_OFF RCC_CFGR2_ADCPRE12_NO
bogdanm	86:04dd9b1680ae	1774	#define RCC_ADC12PLLCLK_DIV1 RCC_CFGR2_ADCPRE12_DIV1
bogdanm	86:04dd9b1680ae	1775	#define RCC_ADC12PLLCLK_DIV2 RCC_CFGR2_ADCPRE12_DIV2
bogdanm	86:04dd9b1680ae	1776	#define RCC_ADC12PLLCLK_DIV4 RCC_CFGR2_ADCPRE12_DIV4
bogdanm	86:04dd9b1680ae	1777	#define RCC_ADC12PLLCLK_DIV6 RCC_CFGR2_ADCPRE12_DIV6
bogdanm	86:04dd9b1680ae	1778	#define RCC_ADC12PLLCLK_DIV8 RCC_CFGR2_ADCPRE12_DIV8
bogdanm	86:04dd9b1680ae	1779	#define RCC_ADC12PLLCLK_DIV10 RCC_CFGR2_ADCPRE12_DIV10
bogdanm	86:04dd9b1680ae	1780	#define RCC_ADC12PLLCLK_DIV12 RCC_CFGR2_ADCPRE12_DIV12
bogdanm	86:04dd9b1680ae	1781	#define RCC_ADC12PLLCLK_DIV16 RCC_CFGR2_ADCPRE12_DIV16
bogdanm	86:04dd9b1680ae	1782	#define RCC_ADC12PLLCLK_DIV32 RCC_CFGR2_ADCPRE12_DIV32
bogdanm	86:04dd9b1680ae	1783	#define RCC_ADC12PLLCLK_DIV64 RCC_CFGR2_ADCPRE12_DIV64
bogdanm	86:04dd9b1680ae	1784	#define RCC_ADC12PLLCLK_DIV128 RCC_CFGR2_ADCPRE12_DIV128
bogdanm	86:04dd9b1680ae	1785	#define RCC_ADC12PLLCLK_DIV256 RCC_CFGR2_ADCPRE12_DIV256
bogdanm	86:04dd9b1680ae	1786
bogdanm	86:04dd9b1680ae	1787	#define IS_RCC_ADC12PLLCLK_DIV(ADCCLK) (((ADCCLK) == RCC_ADC12PLLCLK_OFF) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV1) \|\| \
bogdanm	86:04dd9b1680ae	1788	((ADCCLK) == RCC_ADC12PLLCLK_DIV2) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV4) \|\| \
bogdanm	86:04dd9b1680ae	1789	((ADCCLK) == RCC_ADC12PLLCLK_DIV6) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	1790	((ADCCLK) == RCC_ADC12PLLCLK_DIV10) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV12) \|\| \
bogdanm	86:04dd9b1680ae	1791	((ADCCLK) == RCC_ADC12PLLCLK_DIV16) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV32) \|\| \
bogdanm	86:04dd9b1680ae	1792	((ADCCLK) == RCC_ADC12PLLCLK_DIV64) \|\| ((ADCCLK) == RCC_ADC12PLLCLK_DIV128) \|\| \
bogdanm	86:04dd9b1680ae	1793	((ADCCLK) == RCC_ADC12PLLCLK_DIV256))
bogdanm	86:04dd9b1680ae	1794	/**
bogdanm	86:04dd9b1680ae	1795	* @}
bogdanm	86:04dd9b1680ae	1796	*/
bogdanm	86:04dd9b1680ae	1797
bogdanm	92:4fc01daae5a5	1798	/** @defgroup RCCEx_TIM1_Clock_Source RCC Extended TIM1 Clock Source
bogdanm	86:04dd9b1680ae	1799	* @{
bogdanm	86:04dd9b1680ae	1800	*/
bogdanm	86:04dd9b1680ae	1801	#define RCC_TIM1CLK_HCLK RCC_CFGR3_TIM1SW_HCLK
bogdanm	86:04dd9b1680ae	1802	#define RCC_TIM1CLK_PLLCLK RCC_CFGR3_TIM1SW_PLL
bogdanm	86:04dd9b1680ae	1803
bogdanm	86:04dd9b1680ae	1804	#define IS_RCC_TIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_TIM1CLK_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	1805	((SOURCE) == RCC_TIM1CLK_PLLCLK))
bogdanm	86:04dd9b1680ae	1806	/**
bogdanm	86:04dd9b1680ae	1807	* @}
bogdanm	86:04dd9b1680ae	1808	*/
bogdanm	86:04dd9b1680ae	1809
bogdanm	86:04dd9b1680ae	1810	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
bogdanm	86:04dd9b1680ae	1811
bogdanm	86:04dd9b1680ae	1812	#if defined(STM32F334x8)
bogdanm	86:04dd9b1680ae	1813
bogdanm	92:4fc01daae5a5	1814	/** @defgroup RCCEx_HRTIM1_Clock_Source RCC Extended HRTIM1 Clock Source
bogdanm	86:04dd9b1680ae	1815	* @{
bogdanm	86:04dd9b1680ae	1816	*/
bogdanm	86:04dd9b1680ae	1817	#define RCC_HRTIM1CLK_HCLK RCC_CFGR3_HRTIM1SW_HCLK
bogdanm	86:04dd9b1680ae	1818	#define RCC_HRTIM1CLK_PLLCLK RCC_CFGR3_HRTIM1SW_PLL
bogdanm	86:04dd9b1680ae	1819
bogdanm	86:04dd9b1680ae	1820	#define IS_RCC_HRTIM1CLKSOURCE(SOURCE) (((SOURCE) == RCC_HRTIM1CLK_HCLK) \|\| \
bogdanm	86:04dd9b1680ae	1821	((SOURCE) == RCC_HRTIM1CLK_PLLCLK))
bogdanm	86:04dd9b1680ae	1822	/**
bogdanm	86:04dd9b1680ae	1823	* @}
bogdanm	86:04dd9b1680ae	1824	*/
bogdanm	86:04dd9b1680ae	1825
bogdanm	86:04dd9b1680ae	1826	#endif /* STM32F334x8 */
bogdanm	86:04dd9b1680ae	1827
bogdanm	86:04dd9b1680ae	1828	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	1829
bogdanm	92:4fc01daae5a5	1830	/** @defgroup RCCEx_USART1_Clock_Source RCC Extended USART1 Clock Source
bogdanm	86:04dd9b1680ae	1831	* @{
bogdanm	86:04dd9b1680ae	1832	*/
bogdanm	86:04dd9b1680ae	1833	#define RCC_USART1CLKSOURCE_PCLK2 RCC_CFGR3_USART1SW_PCLK
bogdanm	86:04dd9b1680ae	1834	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
bogdanm	86:04dd9b1680ae	1835	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
bogdanm	86:04dd9b1680ae	1836	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
bogdanm	86:04dd9b1680ae	1837
bogdanm	86:04dd9b1680ae	1838	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK2) \|\| \
bogdanm	86:04dd9b1680ae	1839	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
bogdanm	86:04dd9b1680ae	1840	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
bogdanm	86:04dd9b1680ae	1841	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
bogdanm	86:04dd9b1680ae	1842	/**
bogdanm	86:04dd9b1680ae	1843	* @}
bogdanm	86:04dd9b1680ae	1844	*/
bogdanm	86:04dd9b1680ae	1845
bogdanm	92:4fc01daae5a5	1846	/** @defgroup RCCEx_I2C2_Clock_Source RCC Extended I2C2 Clock Source
bogdanm	86:04dd9b1680ae	1847	* @{
bogdanm	86:04dd9b1680ae	1848	*/
bogdanm	86:04dd9b1680ae	1849	#define RCC_I2C2CLKSOURCE_HSI RCC_CFGR3_I2C2SW_HSI
bogdanm	86:04dd9b1680ae	1850	#define RCC_I2C2CLKSOURCE_SYSCLK RCC_CFGR3_I2C2SW_SYSCLK
bogdanm	86:04dd9b1680ae	1851
bogdanm	86:04dd9b1680ae	1852	#define IS_RCC_I2C2CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C2CLKSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	1853	((SOURCE) == RCC_I2C2CLKSOURCE_SYSCLK))
bogdanm	86:04dd9b1680ae	1854	/**
bogdanm	86:04dd9b1680ae	1855	* @}
bogdanm	86:04dd9b1680ae	1856	*/
bogdanm	86:04dd9b1680ae	1857
bogdanm	92:4fc01daae5a5	1858	/** @defgroup RCCEx_ADC1_Clock_Source RCC Extended ADC1 Clock Source
bogdanm	86:04dd9b1680ae	1859	* @{
bogdanm	86:04dd9b1680ae	1860	*/
bogdanm	86:04dd9b1680ae	1861
bogdanm	86:04dd9b1680ae	1862	/* ADC1 */
bogdanm	86:04dd9b1680ae	1863	#define RCC_ADC1PCLK2_DIV2 RCC_CFGR_ADCPRE_DIV2
bogdanm	86:04dd9b1680ae	1864	#define RCC_ADC1PCLK2_DIV4 RCC_CFGR_ADCPRE_DIV4
bogdanm	86:04dd9b1680ae	1865	#define RCC_ADC1PCLK2_DIV6 RCC_CFGR_ADCPRE_DIV6
bogdanm	86:04dd9b1680ae	1866	#define RCC_ADC1PCLK2_DIV8 RCC_CFGR_ADCPRE_DIV8
bogdanm	86:04dd9b1680ae	1867
bogdanm	86:04dd9b1680ae	1868	#define IS_RCC_ADC1PCLK2_DIV(ADCCLK) (((ADCCLK) == RCC_ADC1PCLK2_DIV2) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV4) \|\| \
bogdanm	86:04dd9b1680ae	1869	((ADCCLK) == RCC_ADC1PCLK2_DIV6) \|\| ((ADCCLK) == RCC_ADC1PCLK2_DIV8))
bogdanm	86:04dd9b1680ae	1870	/**
bogdanm	86:04dd9b1680ae	1871	* @}
bogdanm	86:04dd9b1680ae	1872	*/
bogdanm	86:04dd9b1680ae	1873
bogdanm	92:4fc01daae5a5	1874	/** @defgroup RCCEx_CEC_Clock_Source RCC Extended CEC Clock Source
bogdanm	86:04dd9b1680ae	1875	* @{
bogdanm	86:04dd9b1680ae	1876	*/
bogdanm	86:04dd9b1680ae	1877	#define RCC_CECCLKSOURCE_HSI RCC_CFGR3_CECSW_HSI_DIV244
bogdanm	86:04dd9b1680ae	1878	#define RCC_CECCLKSOURCE_LSE RCC_CFGR3_CECSW_LSE
bogdanm	86:04dd9b1680ae	1879
bogdanm	86:04dd9b1680ae	1880	#define IS_RCC_CECCLKSOURCE(SOURCE) (((SOURCE) == RCC_CECCLKSOURCE_HSI) \|\| \
bogdanm	86:04dd9b1680ae	1881	((SOURCE) == RCC_CECCLKSOURCE_LSE))
bogdanm	86:04dd9b1680ae	1882	/**
bogdanm	86:04dd9b1680ae	1883	* @}
bogdanm	86:04dd9b1680ae	1884	*/
bogdanm	86:04dd9b1680ae	1885
bogdanm	92:4fc01daae5a5	1886	/** @defgroup RCCEx_SDADC_Clock_Prescaler RCC Extended SDADC Clock Prescaler
bogdanm	86:04dd9b1680ae	1887	* @{
bogdanm	86:04dd9b1680ae	1888	*/
bogdanm	86:04dd9b1680ae	1889	#define RCC_SDADCSYSCLK_DIV1 RCC_CFGR_SDADCPRE_DIV1
bogdanm	86:04dd9b1680ae	1890	#define RCC_SDADCSYSCLK_DIV2 RCC_CFGR_SDADCPRE_DIV2
bogdanm	86:04dd9b1680ae	1891	#define RCC_SDADCSYSCLK_DIV4 RCC_CFGR_SDADCPRE_DIV4
bogdanm	86:04dd9b1680ae	1892	#define RCC_SDADCSYSCLK_DIV6 RCC_CFGR_SDADCPRE_DIV6
bogdanm	86:04dd9b1680ae	1893	#define RCC_SDADCSYSCLK_DIV8 RCC_CFGR_SDADCPRE_DIV8
bogdanm	86:04dd9b1680ae	1894	#define RCC_SDADCSYSCLK_DIV10 RCC_CFGR_SDADCPRE_DIV10
bogdanm	86:04dd9b1680ae	1895	#define RCC_SDADCSYSCLK_DIV12 RCC_CFGR_SDADCPRE_DIV12
bogdanm	86:04dd9b1680ae	1896	#define RCC_SDADCSYSCLK_DIV14 RCC_CFGR_SDADCPRE_DIV14
bogdanm	86:04dd9b1680ae	1897	#define RCC_SDADCSYSCLK_DIV16 RCC_CFGR_SDADCPRE_DIV16
bogdanm	86:04dd9b1680ae	1898	#define RCC_SDADCSYSCLK_DIV20 RCC_CFGR_SDADCPRE_DIV20
bogdanm	86:04dd9b1680ae	1899	#define RCC_SDADCSYSCLK_DIV24 RCC_CFGR_SDADCPRE_DIV24
bogdanm	86:04dd9b1680ae	1900	#define RCC_SDADCSYSCLK_DIV28 RCC_CFGR_SDADCPRE_DIV28
bogdanm	86:04dd9b1680ae	1901	#define RCC_SDADCSYSCLK_DIV32 RCC_CFGR_SDADCPRE_DIV32
bogdanm	86:04dd9b1680ae	1902	#define RCC_SDADCSYSCLK_DIV36 RCC_CFGR_SDADCPRE_DIV36
bogdanm	86:04dd9b1680ae	1903	#define RCC_SDADCSYSCLK_DIV40 RCC_CFGR_SDADCPRE_DIV40
bogdanm	86:04dd9b1680ae	1904	#define RCC_SDADCSYSCLK_DIV44 RCC_CFGR_SDADCPRE_DIV44
bogdanm	86:04dd9b1680ae	1905	#define RCC_SDADCSYSCLK_DIV48 RCC_CFGR_SDADCPRE_DIV48
bogdanm	86:04dd9b1680ae	1906
bogdanm	86:04dd9b1680ae	1907	#define IS_RCC_SDADCSYSCLK_DIV(DIV) (((DIV) == RCC_SDADCSYSCLK_DIV1) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV2) \|\| \
bogdanm	86:04dd9b1680ae	1908	((DIV) == RCC_SDADCSYSCLK_DIV4) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV6) \|\| \
bogdanm	86:04dd9b1680ae	1909	((DIV) == RCC_SDADCSYSCLK_DIV8) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV10) \|\| \
bogdanm	86:04dd9b1680ae	1910	((DIV) == RCC_SDADCSYSCLK_DIV12) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV14) \|\| \
bogdanm	86:04dd9b1680ae	1911	((DIV) == RCC_SDADCSYSCLK_DIV16) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV20) \|\| \
bogdanm	86:04dd9b1680ae	1912	((DIV) == RCC_SDADCSYSCLK_DIV24) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV28) \|\| \
bogdanm	86:04dd9b1680ae	1913	((DIV) == RCC_SDADCSYSCLK_DIV32) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV36) \|\| \
bogdanm	86:04dd9b1680ae	1914	((DIV) == RCC_SDADCSYSCLK_DIV40) \|\| ((DIV) == RCC_SDADCSYSCLK_DIV44) \|\| \
bogdanm	86:04dd9b1680ae	1915	((DIV) == RCC_SDADCSYSCLK_DIV48))
bogdanm	86:04dd9b1680ae	1916	/**
bogdanm	86:04dd9b1680ae	1917	* @}
bogdanm	86:04dd9b1680ae	1918	*/
bogdanm	86:04dd9b1680ae	1919
bogdanm	86:04dd9b1680ae	1920	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	1921
bogdanm	92:4fc01daae5a5	1922	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
bogdanm	92:4fc01daae5a5	1923	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
bogdanm	92:4fc01daae5a5	1924	defined(STM32F302x8) \|\| \
bogdanm	92:4fc01daae5a5	1925	defined(STM32F373xC)
bogdanm	92:4fc01daae5a5	1926	/** @defgroup RCCEx_USB_Clock_Source RCC Extended USB Clock Source
bogdanm	86:04dd9b1680ae	1927	* @{
bogdanm	86:04dd9b1680ae	1928	*/
bogdanm	86:04dd9b1680ae	1929	#define RCC_USBPLLCLK_DIV1 RCC_CFGR_USBPRE_DIV1
bogdanm	86:04dd9b1680ae	1930	#define RCC_USBPLLCLK_DIV1_5 RCC_CFGR_USBPRE_DIV1_5
bogdanm	86:04dd9b1680ae	1931
bogdanm	86:04dd9b1680ae	1932	#define IS_RCC_USBCLKSOURCE(SOURCE) (((SOURCE) == RCC_USBPLLCLK_DIV1) \|\| \
bogdanm	86:04dd9b1680ae	1933	((SOURCE) == RCC_USBPLLCLK_DIV1_5))
bogdanm	86:04dd9b1680ae	1934	/**
bogdanm	86:04dd9b1680ae	1935	* @}
bogdanm	86:04dd9b1680ae	1936	*/
bogdanm	86:04dd9b1680ae	1937
bogdanm	92:4fc01daae5a5	1938	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
bogdanm	92:4fc01daae5a5	1939	/* STM32F302xC \|\| STM32F303xC \|\| */
bogdanm	92:4fc01daae5a5	1940	/* STM32F302x8 \|\| */
bogdanm	92:4fc01daae5a5	1941	/* STM32F373xC */
bogdanm	86:04dd9b1680ae	1942
bogdanm	86:04dd9b1680ae	1943	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	86:04dd9b1680ae	1944	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	92:4fc01daae5a5	1945	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
bogdanm	86:04dd9b1680ae	1946	* @{
bogdanm	86:04dd9b1680ae	1947	*/
bogdanm	86:04dd9b1680ae	1948	#define RCC_MCO_NODIV ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	1949
bogdanm	86:04dd9b1680ae	1950	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_NODIV))
bogdanm	86:04dd9b1680ae	1951	/**
bogdanm	86:04dd9b1680ae	1952	* @}
bogdanm	86:04dd9b1680ae	1953	*/
bogdanm	92:4fc01daae5a5	1954	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	1955	/* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	1956
bogdanm	92:4fc01daae5a5	1957	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	1958	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	1959	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	92:4fc01daae5a5	1960
bogdanm	92:4fc01daae5a5	1961	/** @defgroup RCCEx_MCOx_Clock_Prescaler RCC Extended MCOx Clock Prescaler
bogdanm	86:04dd9b1680ae	1962	* @{
bogdanm	86:04dd9b1680ae	1963	*/
bogdanm	86:04dd9b1680ae	1964	#define RCC_MCO_DIV1 ((uint32_t)0x00000000)
bogdanm	86:04dd9b1680ae	1965	#define RCC_MCO_DIV2 ((uint32_t)0x10000000)
bogdanm	86:04dd9b1680ae	1966	#define RCC_MCO_DIV4 ((uint32_t)0x20000000)
bogdanm	86:04dd9b1680ae	1967	#define RCC_MCO_DIV8 ((uint32_t)0x30000000)
bogdanm	86:04dd9b1680ae	1968	#define RCC_MCO_DIV16 ((uint32_t)0x40000000)
bogdanm	86:04dd9b1680ae	1969	#define RCC_MCO_DIV32 ((uint32_t)0x50000000)
bogdanm	86:04dd9b1680ae	1970	#define RCC_MCO_DIV64 ((uint32_t)0x60000000)
bogdanm	86:04dd9b1680ae	1971	#define RCC_MCO_DIV128 ((uint32_t)0x70000000)
bogdanm	86:04dd9b1680ae	1972
bogdanm	86:04dd9b1680ae	1973	#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCO_DIV1) \|\| ((DIV) == RCC_MCO_DIV2) \|\| \
bogdanm	86:04dd9b1680ae	1974	((DIV) == RCC_MCO_DIV4) \|\| ((DIV) == RCC_MCO_DIV8) \|\| \
bogdanm	86:04dd9b1680ae	1975	((DIV) == RCC_MCO_DIV16) \|\| ((DIV) == RCC_MCO_DIV32) \|\| \
bogdanm	86:04dd9b1680ae	1976	((DIV) == RCC_MCO_DIV64) \|\| ((DIV) == RCC_MCO_DIV128))
bogdanm	86:04dd9b1680ae	1977	/**
bogdanm	86:04dd9b1680ae	1978	* @}
bogdanm	86:04dd9b1680ae	1979	*/
bogdanm	86:04dd9b1680ae	1980
bogdanm	92:4fc01daae5a5	1981	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	1982	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	1983	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	1984
bogdanm	86:04dd9b1680ae	1985	/**
bogdanm	86:04dd9b1680ae	1986	* @}
bogdanm	86:04dd9b1680ae	1987	*/
bogdanm	86:04dd9b1680ae	1988
bogdanm	86:04dd9b1680ae	1989	/* Exported macro ------------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	1990	/** @defgroup RCCEx_Exported_Macros RCC Extended Exported Macros
bogdanm	92:4fc01daae5a5	1991	* @{
bogdanm	92:4fc01daae5a5	1992	*/
bogdanm	92:4fc01daae5a5	1993
bogdanm	92:4fc01daae5a5	1994	/** @defgroup RCCEx_PLL_Configuration RCC Extended PLL Configuration
bogdanm	92:4fc01daae5a5	1995	* @{
bogdanm	92:4fc01daae5a5	1996	*/
bogdanm	92:4fc01daae5a5	1997	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	1998	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
bogdanm	92:4fc01daae5a5	1999	* @note This macro must be used only when the PLL is disabled.
bogdanm	92:4fc01daae5a5	2000	*
bogdanm	92:4fc01daae5a5	2001	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm	92:4fc01daae5a5	2002	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	2003	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	92:4fc01daae5a5	2004	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	92:4fc01daae5a5	2005	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
bogdanm	92:4fc01daae5a5	2006	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
bogdanm	92:4fc01daae5a5	2007	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
bogdanm	92:4fc01daae5a5	2008	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
bogdanm	92:4fc01daae5a5	2009	*
bogdanm	92:4fc01daae5a5	2010	*/
bogdanm	92:4fc01daae5a5	2011	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
bogdanm	92:4fc01daae5a5	2012	do { \
bogdanm	92:4fc01daae5a5	2013	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
bogdanm	92:4fc01daae5a5	2014	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__))); \
bogdanm	92:4fc01daae5a5	2015	} while(0)
bogdanm	92:4fc01daae5a5	2016	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2017
bogdanm	92:4fc01daae5a5	2018	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	2019	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	2020	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
bogdanm	92:4fc01daae5a5	2021	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	92:4fc01daae5a5	2022	/** @brief Macro to configure the PLL clock source and multiplication factor.
bogdanm	92:4fc01daae5a5	2023	* @note This macro must be used only when the PLL is disabled.
bogdanm	92:4fc01daae5a5	2024	*
bogdanm	92:4fc01daae5a5	2025	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
bogdanm	92:4fc01daae5a5	2026	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	2027	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
bogdanm	92:4fc01daae5a5	2028	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
bogdanm	92:4fc01daae5a5	2029	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
bogdanm	92:4fc01daae5a5	2030	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
bogdanm	92:4fc01daae5a5	2031	*
bogdanm	92:4fc01daae5a5	2032	*/
bogdanm	92:4fc01daae5a5	2033	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PLLMUL__) \
bogdanm	92:4fc01daae5a5	2034	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__)))
bogdanm	92:4fc01daae5a5	2035	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	2036	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	2037	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	92:4fc01daae5a5	2038	/* STM32F373xC \|\| STM32F378xx */
bogdanm	92:4fc01daae5a5	2039	/**
bogdanm	92:4fc01daae5a5	2040	* @}
bogdanm	92:4fc01daae5a5	2041	*/
bogdanm	92:4fc01daae5a5	2042
bogdanm	92:4fc01daae5a5	2043	#if defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	2044	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	2045	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx) \|\| \
bogdanm	92:4fc01daae5a5	2046	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	92:4fc01daae5a5	2047	/** @defgroup RCCEx_HSE_Configuration RCC Extended HSE Configuration
bogdanm	92:4fc01daae5a5	2048	* @{
bogdanm	92:4fc01daae5a5	2049	*/
bogdanm	92:4fc01daae5a5	2050
bogdanm	92:4fc01daae5a5	2051	/**
bogdanm	92:4fc01daae5a5	2052	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
bogdanm	92:4fc01daae5a5	2053	* @note Predivision factor can not be changed if PLL is used as system clock
bogdanm	92:4fc01daae5a5	2054	* In this case, you have to select another source of the system clock, disable the PLL and
bogdanm	92:4fc01daae5a5	2055	* then change the HSE predivision factor.
bogdanm	92:4fc01daae5a5	2056	* @param __HSEPredivValue__: specifies the division value applied to HSE.
bogdanm	92:4fc01daae5a5	2057	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
bogdanm	92:4fc01daae5a5	2058	*/
bogdanm	92:4fc01daae5a5	2059	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
bogdanm	92:4fc01daae5a5	2060	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
bogdanm	92:4fc01daae5a5	2061	/**
bogdanm	92:4fc01daae5a5	2062	* @}
bogdanm	92:4fc01daae5a5	2063	*/
bogdanm	92:4fc01daae5a5	2064	#endif /* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	2065	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	2066	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	92:4fc01daae5a5	2067	/* STM32F373xC \|\| STM32F378xx */
bogdanm	92:4fc01daae5a5	2068
bogdanm	92:4fc01daae5a5	2069	/** @defgroup RCCEx_AHB_Clock_Enable_Disable RCC Extended AHB Clock Enable Disable
bogdanm	92:4fc01daae5a5	2070	* @brief Enable or disable the AHB peripheral clock.
bogdanm	86:04dd9b1680ae	2071	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	2072	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	2073	* using it.
bogdanm	92:4fc01daae5a5	2074	* @{
bogdanm	86:04dd9b1680ae	2075	*/
bogdanm	86:04dd9b1680ae	2076	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	2077	#define __ADC1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC1EN))
bogdanm	86:04dd9b1680ae	2078
bogdanm	86:04dd9b1680ae	2079	#define __ADC1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC1EN))
bogdanm	86:04dd9b1680ae	2080	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	2081
bogdanm	92:4fc01daae5a5	2082	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2083	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2084	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
bogdanm	86:04dd9b1680ae	2085	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
bogdanm	86:04dd9b1680ae	2086	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
bogdanm	86:04dd9b1680ae	2087	/* Aliases for STM32 F3 compatibility */
bogdanm	86:04dd9b1680ae	2088	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
bogdanm	86:04dd9b1680ae	2089	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
bogdanm	86:04dd9b1680ae	2090
bogdanm	86:04dd9b1680ae	2091	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm	86:04dd9b1680ae	2092	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm	86:04dd9b1680ae	2093	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
bogdanm	86:04dd9b1680ae	2094	/* Aliases for STM32 F3 compatibility */
bogdanm	86:04dd9b1680ae	2095	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
bogdanm	86:04dd9b1680ae	2096	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
bogdanm	92:4fc01daae5a5	2097	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2098	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	92:4fc01daae5a5	2099
bogdanm	92:4fc01daae5a5	2100	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2101	defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2102	#define __ADC34_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC34EN))
bogdanm	86:04dd9b1680ae	2103
bogdanm	86:04dd9b1680ae	2104	#define __ADC34_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC34EN))
bogdanm	92:4fc01daae5a5	2105	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2106	/* STM32F303xC \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	2107
bogdanm	86:04dd9b1680ae	2108	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	2109	#define __ADC12_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_ADC12EN))
bogdanm	86:04dd9b1680ae	2110	/* Aliases for STM32 F3 compatibility */
bogdanm	86:04dd9b1680ae	2111	#define __ADC1_CLK_ENABLE() __ADC12_CLK_ENABLE()
bogdanm	86:04dd9b1680ae	2112	#define __ADC2_CLK_ENABLE() __ADC12_CLK_ENABLE()
bogdanm	86:04dd9b1680ae	2113
bogdanm	86:04dd9b1680ae	2114	#define __ADC12_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_ADC12EN))
bogdanm	86:04dd9b1680ae	2115	/* Aliases for STM32 F3 compatibility */
bogdanm	86:04dd9b1680ae	2116	#define __ADC1_CLK_DISABLE() __ADC12_CLK_DISABLE()
bogdanm	86:04dd9b1680ae	2117	#define __ADC2_CLK_DISABLE() __ADC12_CLK_DISABLE()
bogdanm	86:04dd9b1680ae	2118	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
bogdanm	86:04dd9b1680ae	2119
bogdanm	86:04dd9b1680ae	2120	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	2121	#define __DMA2_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA2EN))
bogdanm	86:04dd9b1680ae	2122	#define __GPIOE_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOEEN))
bogdanm	86:04dd9b1680ae	2123
bogdanm	86:04dd9b1680ae	2124	#define __DMA2_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA2EN))
bogdanm	86:04dd9b1680ae	2125	#define __GPIOE_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOEEN))
bogdanm	86:04dd9b1680ae	2126	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	2127
bogdanm	92:4fc01daae5a5	2128	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	2129	#define __FMC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FMCEN))
bogdanm	92:4fc01daae5a5	2130	#define __GPIOG_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOGEN))
bogdanm	92:4fc01daae5a5	2131	#define __GPIOH_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOHEN))
bogdanm	92:4fc01daae5a5	2132
bogdanm	92:4fc01daae5a5	2133	#define __FMC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FMCEN))
bogdanm	92:4fc01daae5a5	2134	#define __GPIOG_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOGEN))
bogdanm	92:4fc01daae5a5	2135	#define __GPIOH_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOHEN))
bogdanm	92:4fc01daae5a5	2136	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2137	/**
bogdanm	92:4fc01daae5a5	2138	* @}
bogdanm	92:4fc01daae5a5	2139	*/
bogdanm	92:4fc01daae5a5	2140
bogdanm	92:4fc01daae5a5	2141	/** @defgroup RCCEx_APB1_Clock_Enable_Disable RCC Extended APB1 Clock Enable Disable
bogdanm	92:4fc01daae5a5	2142	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
bogdanm	86:04dd9b1680ae	2143	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	2144	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	2145	* using it.
bogdanm	92:4fc01daae5a5	2146	* @{
bogdanm	86:04dd9b1680ae	2147	*/
bogdanm	86:04dd9b1680ae	2148	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	2149	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	86:04dd9b1680ae	2150	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
bogdanm	86:04dd9b1680ae	2151	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	86:04dd9b1680ae	2152	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
bogdanm	86:04dd9b1680ae	2153
bogdanm	86:04dd9b1680ae	2154	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	86:04dd9b1680ae	2155	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm	86:04dd9b1680ae	2156	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	86:04dd9b1680ae	2157	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm	86:04dd9b1680ae	2158	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	2159
bogdanm	92:4fc01daae5a5	2160	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2161	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2162	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
bogdanm	86:04dd9b1680ae	2163	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
bogdanm	86:04dd9b1680ae	2164	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	86:04dd9b1680ae	2165	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
bogdanm	86:04dd9b1680ae	2166	#define __UART4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART4EN))
bogdanm	86:04dd9b1680ae	2167	#define __UART5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_UART5EN))
bogdanm	86:04dd9b1680ae	2168	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	86:04dd9b1680ae	2169
bogdanm	86:04dd9b1680ae	2170	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	86:04dd9b1680ae	2171	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm	86:04dd9b1680ae	2172	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	86:04dd9b1680ae	2173	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm	86:04dd9b1680ae	2174	#define __UART4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART4EN))
bogdanm	86:04dd9b1680ae	2175	#define __UART5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_UART5EN))
bogdanm	86:04dd9b1680ae	2176	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	92:4fc01daae5a5	2177	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2178	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	2179
bogdanm	86:04dd9b1680ae	2180	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	2181	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
bogdanm	86:04dd9b1680ae	2182	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
bogdanm	86:04dd9b1680ae	2183
bogdanm	86:04dd9b1680ae	2184	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	86:04dd9b1680ae	2185	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
bogdanm	86:04dd9b1680ae	2186	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
bogdanm	86:04dd9b1680ae	2187
bogdanm	86:04dd9b1680ae	2188	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	2189	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
bogdanm	86:04dd9b1680ae	2190	#define __TIM4_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM4EN))
bogdanm	86:04dd9b1680ae	2191	#define __TIM5_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM5EN))
bogdanm	86:04dd9b1680ae	2192	#define __TIM12_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM12EN))
bogdanm	86:04dd9b1680ae	2193	#define __TIM13_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM13EN))
bogdanm	86:04dd9b1680ae	2194	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
bogdanm	86:04dd9b1680ae	2195	#define __TIM18_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM18EN))
bogdanm	86:04dd9b1680ae	2196	#define __SPI2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI2EN))
bogdanm	86:04dd9b1680ae	2197	#define __SPI3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_SPI3EN))
bogdanm	86:04dd9b1680ae	2198	#define __I2C2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C2EN))
bogdanm	86:04dd9b1680ae	2199	#define __DAC2_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_DAC2EN))
bogdanm	86:04dd9b1680ae	2200	#define __CEC_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CECEN))
bogdanm	86:04dd9b1680ae	2201
bogdanm	86:04dd9b1680ae	2202	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
bogdanm	86:04dd9b1680ae	2203	#define __TIM4_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM4EN))
bogdanm	86:04dd9b1680ae	2204	#define __TIM5_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM5EN))
bogdanm	86:04dd9b1680ae	2205	#define __TIM12_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM12EN))
bogdanm	86:04dd9b1680ae	2206	#define __TIM13_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM13EN))
bogdanm	86:04dd9b1680ae	2207	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
bogdanm	86:04dd9b1680ae	2208	#define __TIM18_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM18EN))
bogdanm	86:04dd9b1680ae	2209	#define __SPI2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI2EN))
bogdanm	86:04dd9b1680ae	2210	#define __SPI3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_SPI3EN))
bogdanm	86:04dd9b1680ae	2211	#define __I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
bogdanm	86:04dd9b1680ae	2212	#define __DAC2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_DAC2EN))
bogdanm	86:04dd9b1680ae	2213	#define __CEC_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CECEN))
bogdanm	86:04dd9b1680ae	2214	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	2215
bogdanm	92:4fc01daae5a5	2216	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2217	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	2218	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	2219	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	2220	#define __TIM7_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM7EN))
bogdanm	86:04dd9b1680ae	2221
bogdanm	86:04dd9b1680ae	2222	#define __TIM7_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM7EN))
bogdanm	92:4fc01daae5a5	2223	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2224	/* STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	2225	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	2226	/* STM32F373xC \|\| STM32F378xx */
bogdanm	92:4fc01daae5a5	2227
bogdanm	92:4fc01daae5a5	2228	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
bogdanm	92:4fc01daae5a5	2229	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
bogdanm	92:4fc01daae5a5	2230	defined(STM32F302x8) \|\| \
bogdanm	92:4fc01daae5a5	2231	defined(STM32F373xC)
bogdanm	86:04dd9b1680ae	2232	#define __USB_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_USBEN))
bogdanm	86:04dd9b1680ae	2233
bogdanm	86:04dd9b1680ae	2234	#define __USB_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USBEN))
bogdanm	92:4fc01daae5a5	2235	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
bogdanm	92:4fc01daae5a5	2236	/* STM32F302xC \|\| STM32F303xC \|\| */
bogdanm	92:4fc01daae5a5	2237	/* STM32F302x8 \|\| */
bogdanm	92:4fc01daae5a5	2238	/* STM32F373xC */
bogdanm	86:04dd9b1680ae	2239
bogdanm	86:04dd9b1680ae	2240	#if !defined(STM32F301x8)
bogdanm	86:04dd9b1680ae	2241	#define __CAN_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_CANEN))
bogdanm	86:04dd9b1680ae	2242
bogdanm	86:04dd9b1680ae	2243	#define __CAN_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_CANEN))
bogdanm	86:04dd9b1680ae	2244	#endif /* STM32F301x8*/
bogdanm	86:04dd9b1680ae	2245
bogdanm	92:4fc01daae5a5	2246	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	2247	#define __I2C3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C3EN))
bogdanm	92:4fc01daae5a5	2248
bogdanm	92:4fc01daae5a5	2249	#define __I2C3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C3EN))
bogdanm	92:4fc01daae5a5	2250	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2251	/**
bogdanm	92:4fc01daae5a5	2252	* @}
bogdanm	92:4fc01daae5a5	2253	*/
bogdanm	92:4fc01daae5a5	2254
bogdanm	92:4fc01daae5a5	2255	/** @defgroup RCCEx_APB2_Clock_Enable_Disable RCC Extended APB2 Clock Enable Disable
bogdanm	92:4fc01daae5a5	2256	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
bogdanm	86:04dd9b1680ae	2257	* @note After reset, the peripheral clock (used for registers read/write access)
bogdanm	86:04dd9b1680ae	2258	* is disabled and the application software has to enable this clock before
bogdanm	86:04dd9b1680ae	2259	* using it.
bogdanm	92:4fc01daae5a5	2260	* @{
bogdanm	86:04dd9b1680ae	2261	*/
bogdanm	92:4fc01daae5a5	2262	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2263	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2264	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
bogdanm	86:04dd9b1680ae	2265
bogdanm	86:04dd9b1680ae	2266	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	92:4fc01daae5a5	2267	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2268	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	92:4fc01daae5a5	2269
bogdanm	92:4fc01daae5a5	2270	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2271	defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2272	#define __TIM8_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM8EN))
bogdanm	86:04dd9b1680ae	2273
bogdanm	86:04dd9b1680ae	2274	#define __TIM8_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM8EN))
bogdanm	92:4fc01daae5a5	2275	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2276	/* STM32F303xC \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	2277
bogdanm	86:04dd9b1680ae	2278	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	2279	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
bogdanm	86:04dd9b1680ae	2280
bogdanm	86:04dd9b1680ae	2281	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	86:04dd9b1680ae	2282	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
bogdanm	86:04dd9b1680ae	2283
bogdanm	86:04dd9b1680ae	2284	#if defined(STM32F334x8)
bogdanm	86:04dd9b1680ae	2285	#define __HRTIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_HRTIM1EN))
bogdanm	86:04dd9b1680ae	2286
bogdanm	86:04dd9b1680ae	2287	#define __HRTIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_HRTIM1EN))
bogdanm	86:04dd9b1680ae	2288	#endif /* STM32F334x8 */
bogdanm	86:04dd9b1680ae	2289
bogdanm	86:04dd9b1680ae	2290	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	2291	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
bogdanm	86:04dd9b1680ae	2292	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
bogdanm	86:04dd9b1680ae	2293	#define __TIM19_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM19EN))
bogdanm	86:04dd9b1680ae	2294	#define __SDADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC1EN))
bogdanm	86:04dd9b1680ae	2295	#define __SDADC2_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC2EN))
bogdanm	86:04dd9b1680ae	2296	#define __SDADC3_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SDADC3EN))
bogdanm	86:04dd9b1680ae	2297
bogdanm	86:04dd9b1680ae	2298	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
bogdanm	86:04dd9b1680ae	2299	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
bogdanm	86:04dd9b1680ae	2300	#define __TIM19_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM19EN))
bogdanm	86:04dd9b1680ae	2301	#define __SDADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC1EN))
bogdanm	86:04dd9b1680ae	2302	#define __SDADC2_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC2EN))
bogdanm	86:04dd9b1680ae	2303	#define __SDADC3_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SDADC3EN))
bogdanm	86:04dd9b1680ae	2304	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	2305
bogdanm	92:4fc01daae5a5	2306	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	86:04dd9b1680ae	2307	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	2308	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	2309	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	2310	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
bogdanm	86:04dd9b1680ae	2311
bogdanm	86:04dd9b1680ae	2312	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
bogdanm	92:4fc01daae5a5	2313	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	86:04dd9b1680ae	2314	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	2315	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	2316	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	92:4fc01daae5a5	2317
bogdanm	92:4fc01daae5a5	2318	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	2319	#define __SPI4_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI4EN))
bogdanm	92:4fc01daae5a5	2320
bogdanm	92:4fc01daae5a5	2321	#define __SPI4_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI4EN))
bogdanm	92:4fc01daae5a5	2322	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2323
bogdanm	92:4fc01daae5a5	2324	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	2325	#define __TIM20_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM20EN))
bogdanm	92:4fc01daae5a5	2326
bogdanm	92:4fc01daae5a5	2327	#define __TIM20_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM20EN))
bogdanm	92:4fc01daae5a5	2328	#endif /* STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2329
bogdanm	92:4fc01daae5a5	2330	/**
bogdanm	92:4fc01daae5a5	2331	* @}
bogdanm	92:4fc01daae5a5	2332	*/
bogdanm	92:4fc01daae5a5	2333
bogdanm	92:4fc01daae5a5	2334	/** @defgroup RCCEx_AHB_Force_Release_Reset RCC Extended AHB Force Release Reset
bogdanm	92:4fc01daae5a5	2335	* @brief Force or release AHB peripheral reset.
bogdanm	92:4fc01daae5a5	2336	* @{
bogdanm	86:04dd9b1680ae	2337	*/
bogdanm	86:04dd9b1680ae	2338	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	2339	#define __ADC1_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC1RST))
bogdanm	86:04dd9b1680ae	2340
bogdanm	86:04dd9b1680ae	2341	#define __ADC1_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC1RST))
bogdanm	86:04dd9b1680ae	2342	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	2343
bogdanm	92:4fc01daae5a5	2344	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2345	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2346	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
bogdanm	86:04dd9b1680ae	2347	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
bogdanm	86:04dd9b1680ae	2348	/* Aliases for STM32 F3 compatibility */
bogdanm	86:04dd9b1680ae	2349	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
bogdanm	86:04dd9b1680ae	2350	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
bogdanm	86:04dd9b1680ae	2351
bogdanm	86:04dd9b1680ae	2352	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm	86:04dd9b1680ae	2353	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
bogdanm	86:04dd9b1680ae	2354	/* Aliases for STM32 F3 compatibility */
bogdanm	86:04dd9b1680ae	2355	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
bogdanm	86:04dd9b1680ae	2356	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
bogdanm	92:4fc01daae5a5	2357	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2358	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	92:4fc01daae5a5	2359
bogdanm	92:4fc01daae5a5	2360	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2361	defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2362	#define __ADC34_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC34RST))
bogdanm	86:04dd9b1680ae	2363
bogdanm	86:04dd9b1680ae	2364	#define __ADC34_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC34RST))
bogdanm	92:4fc01daae5a5	2365	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2366	/* STM32F303xC \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	2367
bogdanm	86:04dd9b1680ae	2368	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	2369	#define __ADC12_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_ADC12RST))
bogdanm	86:04dd9b1680ae	2370	/* Aliases for STM32 F3 compatibility */
bogdanm	86:04dd9b1680ae	2371	#define __ADC1_FORCE_RESET() __ADC12_FORCE_RESET()
bogdanm	86:04dd9b1680ae	2372	#define __ADC2_FORCE_RESET() __ADC12_FORCE_RESET()
bogdanm	86:04dd9b1680ae	2373
bogdanm	86:04dd9b1680ae	2374	#define __ADC12_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_ADC12RST))
bogdanm	86:04dd9b1680ae	2375	/* Aliases for STM32 F3 compatibility */
bogdanm	86:04dd9b1680ae	2376	#define __ADC1_RELEASE_RESET() __ADC12_RELEASE_RESET()
bogdanm	86:04dd9b1680ae	2377	#define __ADC2_RELEASE_RESET() __ADC12_RELEASE_RESET()
bogdanm	86:04dd9b1680ae	2378	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
bogdanm	86:04dd9b1680ae	2379
bogdanm	86:04dd9b1680ae	2380	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	2381	#define __GPIOE_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOERST))
bogdanm	86:04dd9b1680ae	2382
bogdanm	86:04dd9b1680ae	2383	#define __GPIOE_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOERST))
bogdanm	86:04dd9b1680ae	2384	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	2385
bogdanm	92:4fc01daae5a5	2386	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	2387	#define __FMC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_FMCRST))
bogdanm	92:4fc01daae5a5	2388	#define __GPIOG_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOGRST))
bogdanm	92:4fc01daae5a5	2389	#define __GPIOH_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOHRST))
bogdanm	92:4fc01daae5a5	2390
bogdanm	92:4fc01daae5a5	2391	#define __FMC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_FMCRST))
bogdanm	92:4fc01daae5a5	2392	#define __GPIOG_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOGRST))
bogdanm	92:4fc01daae5a5	2393	#define __GPIOH_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOHRST))
bogdanm	92:4fc01daae5a5	2394	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2395	/**
bogdanm	92:4fc01daae5a5	2396	* @}
bogdanm	92:4fc01daae5a5	2397	*/
bogdanm	92:4fc01daae5a5	2398
bogdanm	92:4fc01daae5a5	2399	/** @defgroup RCCEx_APB1_Force_Release_Reset RCC Extended APB1 Force Release Reset
bogdanm	92:4fc01daae5a5	2400	* @brief Force or release APB1 peripheral reset.
bogdanm	92:4fc01daae5a5	2401	* @{
bogdanm	86:04dd9b1680ae	2402	*/
bogdanm	86:04dd9b1680ae	2403	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	2404	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	86:04dd9b1680ae	2405	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
bogdanm	86:04dd9b1680ae	2406	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	86:04dd9b1680ae	2407	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
bogdanm	86:04dd9b1680ae	2408
bogdanm	86:04dd9b1680ae	2409	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	86:04dd9b1680ae	2410	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm	86:04dd9b1680ae	2411	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	86:04dd9b1680ae	2412	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm	86:04dd9b1680ae	2413	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	2414
bogdanm	92:4fc01daae5a5	2415	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2416	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2417	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	86:04dd9b1680ae	2418	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
bogdanm	86:04dd9b1680ae	2419	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	86:04dd9b1680ae	2420	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
bogdanm	86:04dd9b1680ae	2421	#define __UART4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART4RST))
bogdanm	86:04dd9b1680ae	2422	#define __UART5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_UART5RST))
bogdanm	86:04dd9b1680ae	2423	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	86:04dd9b1680ae	2424
bogdanm	86:04dd9b1680ae	2425	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	86:04dd9b1680ae	2426	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm	86:04dd9b1680ae	2427	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	86:04dd9b1680ae	2428	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm	86:04dd9b1680ae	2429	#define __UART4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART4RST))
bogdanm	86:04dd9b1680ae	2430	#define __UART5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_UART5RST))
bogdanm	86:04dd9b1680ae	2431	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	92:4fc01daae5a5	2432	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2433	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	2434
bogdanm	86:04dd9b1680ae	2435	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	2436	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	86:04dd9b1680ae	2437	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
bogdanm	86:04dd9b1680ae	2438
bogdanm	86:04dd9b1680ae	2439	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	86:04dd9b1680ae	2440	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
bogdanm	86:04dd9b1680ae	2441	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
bogdanm	86:04dd9b1680ae	2442
bogdanm	86:04dd9b1680ae	2443	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	2444	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
bogdanm	86:04dd9b1680ae	2445	#define __TIM4_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM4RST))
bogdanm	86:04dd9b1680ae	2446	#define __TIM5_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM5RST))
bogdanm	86:04dd9b1680ae	2447	#define __TIM12_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM12RST))
bogdanm	86:04dd9b1680ae	2448	#define __TIM13_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM13RST))
bogdanm	86:04dd9b1680ae	2449	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
bogdanm	86:04dd9b1680ae	2450	#define __TIM18_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM18RST))
bogdanm	86:04dd9b1680ae	2451	#define __SPI2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI2RST))
bogdanm	86:04dd9b1680ae	2452	#define __SPI3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_SPI3RST))
bogdanm	86:04dd9b1680ae	2453	#define __I2C2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C2RST))
bogdanm	86:04dd9b1680ae	2454	#define __DAC2_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_DAC2RST))
bogdanm	86:04dd9b1680ae	2455	#define __CEC_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CECRST))
bogdanm	86:04dd9b1680ae	2456
bogdanm	86:04dd9b1680ae	2457	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
bogdanm	86:04dd9b1680ae	2458	#define __TIM4_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM4RST))
bogdanm	86:04dd9b1680ae	2459	#define __TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
bogdanm	86:04dd9b1680ae	2460	#define __TIM12_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM12RST))
bogdanm	86:04dd9b1680ae	2461	#define __TIM13_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM13RST))
bogdanm	86:04dd9b1680ae	2462	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
bogdanm	86:04dd9b1680ae	2463	#define __TIM18_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM18RST))
bogdanm	86:04dd9b1680ae	2464	#define __SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
bogdanm	86:04dd9b1680ae	2465	#define __SPI3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI3RST))
bogdanm	86:04dd9b1680ae	2466	#define __I2C2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C2RST))
bogdanm	86:04dd9b1680ae	2467	#define __DAC2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_DAC2RST))
bogdanm	86:04dd9b1680ae	2468	#define __CEC_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CECRST))
bogdanm	86:04dd9b1680ae	2469	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	2470
bogdanm	92:4fc01daae5a5	2471	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2472	defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	2473	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	86:04dd9b1680ae	2474	defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	2475	#define __TIM7_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM7RST))
bogdanm	86:04dd9b1680ae	2476
bogdanm	86:04dd9b1680ae	2477	#define __TIM7_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM7RST))
bogdanm	92:4fc01daae5a5	2478	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2479	/* STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	2480	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	2481	/* STM32F373xC \|\| STM32F378xx */
bogdanm	92:4fc01daae5a5	2482
bogdanm	92:4fc01daae5a5	2483	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
bogdanm	92:4fc01daae5a5	2484	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
bogdanm	92:4fc01daae5a5	2485	defined(STM32F302x8) \|\| \
bogdanm	92:4fc01daae5a5	2486	defined(STM32F373xC)
bogdanm	86:04dd9b1680ae	2487	#define __USB_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_USBRST))
bogdanm	86:04dd9b1680ae	2488
bogdanm	86:04dd9b1680ae	2489	#define __USB_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USBRST))
bogdanm	92:4fc01daae5a5	2490	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
bogdanm	92:4fc01daae5a5	2491	/* STM32F302xC \|\| STM32F303xC \|\| */
bogdanm	92:4fc01daae5a5	2492	/* STM32F302x8 \|\| */
bogdanm	92:4fc01daae5a5	2493	/* STM32F373xC */
bogdanm	86:04dd9b1680ae	2494
bogdanm	86:04dd9b1680ae	2495	#if !defined(STM32F301x8)
bogdanm	86:04dd9b1680ae	2496	#define __CAN_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_CANRST))
bogdanm	86:04dd9b1680ae	2497
bogdanm	86:04dd9b1680ae	2498	#define __CAN_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_CANRST))
bogdanm	86:04dd9b1680ae	2499	#endif /* STM32F301x8*/
bogdanm	86:04dd9b1680ae	2500
bogdanm	92:4fc01daae5a5	2501	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	2502	#define __I2C3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C3RST))
bogdanm	92:4fc01daae5a5	2503
bogdanm	92:4fc01daae5a5	2504	#define __I2C3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C3RST))
bogdanm	92:4fc01daae5a5	2505	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2506	/**
bogdanm	92:4fc01daae5a5	2507	* @}
bogdanm	86:04dd9b1680ae	2508	*/
bogdanm	92:4fc01daae5a5	2509
bogdanm	92:4fc01daae5a5	2510	/** @defgroup RCCEx_APB2_Force_Release_Reset RCC Extended APB2 Force Release Reset
bogdanm	92:4fc01daae5a5	2511	* @brief Force or release APB2 peripheral reset.
bogdanm	92:4fc01daae5a5	2512	* @{
bogdanm	92:4fc01daae5a5	2513	*/
bogdanm	92:4fc01daae5a5	2514	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2515	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2516	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	86:04dd9b1680ae	2517
bogdanm	86:04dd9b1680ae	2518	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	92:4fc01daae5a5	2519	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2520	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	92:4fc01daae5a5	2521
bogdanm	92:4fc01daae5a5	2522	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2523	defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	86:04dd9b1680ae	2524	#define __TIM8_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM8RST))
bogdanm	86:04dd9b1680ae	2525
bogdanm	86:04dd9b1680ae	2526	#define __TIM8_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM8RST))
bogdanm	92:4fc01daae5a5	2527	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2528	/* STM32F303xC \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	2529
bogdanm	86:04dd9b1680ae	2530	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
bogdanm	86:04dd9b1680ae	2531	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	86:04dd9b1680ae	2532
bogdanm	86:04dd9b1680ae	2533	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	86:04dd9b1680ae	2534	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
bogdanm	86:04dd9b1680ae	2535
bogdanm	86:04dd9b1680ae	2536	#if defined(STM32F334x8)
bogdanm	86:04dd9b1680ae	2537	#define __HRTIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_HRTIM1RST))
bogdanm	86:04dd9b1680ae	2538
bogdanm	86:04dd9b1680ae	2539	#define __HRTIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_HRTIM1RST))
bogdanm	86:04dd9b1680ae	2540	#endif /* STM32F334x8 */
bogdanm	86:04dd9b1680ae	2541
bogdanm	86:04dd9b1680ae	2542	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	86:04dd9b1680ae	2543	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
bogdanm	86:04dd9b1680ae	2544	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
bogdanm	86:04dd9b1680ae	2545	#define __TIM19_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM19RST))
bogdanm	86:04dd9b1680ae	2546	#define __SDADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC1RST))
bogdanm	86:04dd9b1680ae	2547	#define __SDADC2_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC2RST))
bogdanm	86:04dd9b1680ae	2548	#define __SDADC3_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SDADC3RST))
bogdanm	86:04dd9b1680ae	2549
bogdanm	86:04dd9b1680ae	2550	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
bogdanm	86:04dd9b1680ae	2551	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
bogdanm	86:04dd9b1680ae	2552	#define __TIM19_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM19RST))
bogdanm	86:04dd9b1680ae	2553	#define __SDADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC1RST))
bogdanm	86:04dd9b1680ae	2554	#define __SDADC2_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC2RST))
bogdanm	86:04dd9b1680ae	2555	#define __SDADC3_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SDADC3RST))
bogdanm	86:04dd9b1680ae	2556	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	2557
bogdanm	92:4fc01daae5a5	2558	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	86:04dd9b1680ae	2559	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx) \|\| \
bogdanm	92:4fc01daae5a5	2560	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	2561	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	86:04dd9b1680ae	2562	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
bogdanm	86:04dd9b1680ae	2563
bogdanm	86:04dd9b1680ae	2564	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
bogdanm	92:4fc01daae5a5	2565	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	86:04dd9b1680ae	2566	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx \|\| */
bogdanm	92:4fc01daae5a5	2567	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	2568	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	92:4fc01daae5a5	2569
bogdanm	92:4fc01daae5a5	2570	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	2571	#define __SPI4_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI4RST))
bogdanm	92:4fc01daae5a5	2572
bogdanm	92:4fc01daae5a5	2573	#define __SPI4_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI4RST))
bogdanm	92:4fc01daae5a5	2574	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2575
bogdanm	92:4fc01daae5a5	2576	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	2577	#define __TIM20_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM20RST))
bogdanm	92:4fc01daae5a5	2578
bogdanm	92:4fc01daae5a5	2579	#define __TIM20_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM20RST))
bogdanm	92:4fc01daae5a5	2580	#endif /* STM32F303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	2581
bogdanm	92:4fc01daae5a5	2582	/**
bogdanm	92:4fc01daae5a5	2583	* @}
bogdanm	92:4fc01daae5a5	2584	*/
bogdanm	86:04dd9b1680ae	2585
bogdanm	86:04dd9b1680ae	2586	#if defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	92:4fc01daae5a5	2587	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
bogdanm	92:4fc01daae5a5	2588	* @{
bogdanm	92:4fc01daae5a5	2589	*/
bogdanm	86:04dd9b1680ae	2590
bogdanm	86:04dd9b1680ae	2591	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
bogdanm	86:04dd9b1680ae	2592	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
bogdanm	86:04dd9b1680ae	2593	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2594	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm	86:04dd9b1680ae	2595	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm	86:04dd9b1680ae	2596	*/
bogdanm	86:04dd9b1680ae	2597	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm	86:04dd9b1680ae	2598	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm	86:04dd9b1680ae	2599
bogdanm	86:04dd9b1680ae	2600	/** @brief Macro to get the I2C2 clock source.
bogdanm	86:04dd9b1680ae	2601	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2602	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm	86:04dd9b1680ae	2603	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm	86:04dd9b1680ae	2604	*/
bogdanm	86:04dd9b1680ae	2605	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm	86:04dd9b1680ae	2606
bogdanm	86:04dd9b1680ae	2607	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
bogdanm	86:04dd9b1680ae	2608	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
bogdanm	86:04dd9b1680ae	2609	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2610	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	86:04dd9b1680ae	2611	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	86:04dd9b1680ae	2612	*/
bogdanm	86:04dd9b1680ae	2613	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
bogdanm	86:04dd9b1680ae	2614	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
bogdanm	86:04dd9b1680ae	2615
bogdanm	86:04dd9b1680ae	2616	/** @brief Macro to get the I2C3 clock source.
bogdanm	86:04dd9b1680ae	2617	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2618	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	86:04dd9b1680ae	2619	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	86:04dd9b1680ae	2620	*/
bogdanm	86:04dd9b1680ae	2621	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
bogdanm	86:04dd9b1680ae	2622
bogdanm	92:4fc01daae5a5	2623	/**
bogdanm	92:4fc01daae5a5	2624	* @}
bogdanm	92:4fc01daae5a5	2625	*/
bogdanm	92:4fc01daae5a5	2626
bogdanm	92:4fc01daae5a5	2627	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm	92:4fc01daae5a5	2628	* @{
bogdanm	92:4fc01daae5a5	2629	*/
bogdanm	86:04dd9b1680ae	2630	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
bogdanm	86:04dd9b1680ae	2631	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
bogdanm	86:04dd9b1680ae	2632	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2633	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm	86:04dd9b1680ae	2634	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm	86:04dd9b1680ae	2635	*/
bogdanm	86:04dd9b1680ae	2636	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm	86:04dd9b1680ae	2637	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm	86:04dd9b1680ae	2638
bogdanm	86:04dd9b1680ae	2639	/** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm	86:04dd9b1680ae	2640	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2641	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2642	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm	86:04dd9b1680ae	2643	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm	86:04dd9b1680ae	2644	*/
bogdanm	86:04dd9b1680ae	2645	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm	86:04dd9b1680ae	2646
bogdanm	86:04dd9b1680ae	2647	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
bogdanm	86:04dd9b1680ae	2648	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
bogdanm	86:04dd9b1680ae	2649	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2650	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
bogdanm	86:04dd9b1680ae	2651	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
bogdanm	86:04dd9b1680ae	2652	*/
bogdanm	86:04dd9b1680ae	2653	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
bogdanm	86:04dd9b1680ae	2654	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
bogdanm	86:04dd9b1680ae	2655
bogdanm	86:04dd9b1680ae	2656	/** @brief Macro to get the TIM15 clock (TIM15CLK).
bogdanm	86:04dd9b1680ae	2657	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2658	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2659	* @arg RCC_TIM15CLKSOURCE_HCLK: HCLK selected as TIM15 clock
bogdanm	86:04dd9b1680ae	2660	* @arg RCC_TIM15CLKSOURCE_PLL: PLL Clock selected as TIM15 clock
bogdanm	86:04dd9b1680ae	2661	*/
bogdanm	86:04dd9b1680ae	2662	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
bogdanm	86:04dd9b1680ae	2663
bogdanm	86:04dd9b1680ae	2664	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
bogdanm	86:04dd9b1680ae	2665	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
bogdanm	86:04dd9b1680ae	2666	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2667	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
bogdanm	86:04dd9b1680ae	2668	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
bogdanm	86:04dd9b1680ae	2669	*/
bogdanm	86:04dd9b1680ae	2670	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
bogdanm	86:04dd9b1680ae	2671	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
bogdanm	86:04dd9b1680ae	2672
bogdanm	86:04dd9b1680ae	2673	/** @brief Macro to get the TIM16 clock (TIM16CLK).
bogdanm	86:04dd9b1680ae	2674	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2675	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2676	* @arg RCC_TIM16CLKSOURCE_HCLK: HCLK selected as TIM16 clock
bogdanm	86:04dd9b1680ae	2677	* @arg RCC_TIM16CLKSOURCE_PLL: PLL Clock selected as TIM16 clock
bogdanm	86:04dd9b1680ae	2678	*/
bogdanm	86:04dd9b1680ae	2679	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
bogdanm	86:04dd9b1680ae	2680
bogdanm	86:04dd9b1680ae	2681	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
bogdanm	86:04dd9b1680ae	2682	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
bogdanm	86:04dd9b1680ae	2683	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2684	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
bogdanm	86:04dd9b1680ae	2685	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
bogdanm	86:04dd9b1680ae	2686	*/
bogdanm	86:04dd9b1680ae	2687	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
bogdanm	86:04dd9b1680ae	2688	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
bogdanm	86:04dd9b1680ae	2689
bogdanm	86:04dd9b1680ae	2690	/** @brief Macro to get the TIM17 clock (TIM17CLK).
bogdanm	86:04dd9b1680ae	2691	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2692	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2693	* @arg RCC_TIM17CLKSOURCE_HCLK: HCLK selected as TIM17 clock
bogdanm	86:04dd9b1680ae	2694	* @arg RCC_TIM17CLKSOURCE_PLL: PLL Clock selected as TIM17 clock
bogdanm	86:04dd9b1680ae	2695	*/
bogdanm	86:04dd9b1680ae	2696	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
bogdanm	86:04dd9b1680ae	2697
bogdanm	92:4fc01daae5a5	2698	/**
bogdanm	92:4fc01daae5a5	2699	* @}
bogdanm	92:4fc01daae5a5	2700	*/
bogdanm	92:4fc01daae5a5	2701
bogdanm	92:4fc01daae5a5	2702	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
bogdanm	92:4fc01daae5a5	2703	* @{
bogdanm	92:4fc01daae5a5	2704	*/
bogdanm	86:04dd9b1680ae	2705	/** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm	86:04dd9b1680ae	2706	* @note This function must be called before enabling the I2S APB clock.
bogdanm	86:04dd9b1680ae	2707	* @param __I2SCLKSource__: specifies the I2S clock source.
bogdanm	86:04dd9b1680ae	2708	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2709	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
bogdanm	86:04dd9b1680ae	2710	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm	86:04dd9b1680ae	2711	* used as I2S clock source
bogdanm	86:04dd9b1680ae	2712	*/
bogdanm	86:04dd9b1680ae	2713	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
bogdanm	86:04dd9b1680ae	2714	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
bogdanm	86:04dd9b1680ae	2715
bogdanm	86:04dd9b1680ae	2716	/** @brief Macro to get the I2S clock source (I2SCLK).
bogdanm	86:04dd9b1680ae	2717	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2718	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
bogdanm	86:04dd9b1680ae	2719	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm	86:04dd9b1680ae	2720	* used as I2S clock source
bogdanm	86:04dd9b1680ae	2721	*/
bogdanm	86:04dd9b1680ae	2722	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
bogdanm	92:4fc01daae5a5	2723	/**
bogdanm	92:4fc01daae5a5	2724	* @}
bogdanm	92:4fc01daae5a5	2725	*/
bogdanm	92:4fc01daae5a5	2726
bogdanm	92:4fc01daae5a5	2727	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm	92:4fc01daae5a5	2728	* @{
bogdanm	92:4fc01daae5a5	2729	*/
bogdanm	86:04dd9b1680ae	2730
bogdanm	86:04dd9b1680ae	2731	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
bogdanm	86:04dd9b1680ae	2732	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
bogdanm	86:04dd9b1680ae	2733	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2734	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
bogdanm	86:04dd9b1680ae	2735	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2736	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2737	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2738	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2739	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2740	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2741	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2742	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2743	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2744	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2745	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2746	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2747	*/
bogdanm	86:04dd9b1680ae	2748	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
bogdanm	86:04dd9b1680ae	2749	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADC1PRES, (uint32_t)(__ADC1CLKSource__))
bogdanm	86:04dd9b1680ae	2750
bogdanm	86:04dd9b1680ae	2751	/** @brief Macro to get the ADC1 clock
bogdanm	86:04dd9b1680ae	2752	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2753	* @arg RCC_ADC1PLLCLK_OFF: ADC1 PLL clock disabled, ADC1 can use AHB clock
bogdanm	86:04dd9b1680ae	2754	* @arg RCC_ADC1PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2755	* @arg RCC_ADC1PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2756	* @arg RCC_ADC1PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2757	* @arg RCC_ADC1PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2758	* @arg RCC_ADC1PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2759	* @arg RCC_ADC1PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2760	* @arg RCC_ADC1PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2761	* @arg RCC_ADC1PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2762	* @arg RCC_ADC1PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2763	* @arg RCC_ADC1PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2764	* @arg RCC_ADC1PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2765	* @arg RCC_ADC1PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	2766	*/
bogdanm	86:04dd9b1680ae	2767	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADC1PRES)))
bogdanm	92:4fc01daae5a5	2768	/**
bogdanm	92:4fc01daae5a5	2769	* @}
bogdanm	92:4fc01daae5a5	2770	*/
bogdanm	86:04dd9b1680ae	2771
bogdanm	86:04dd9b1680ae	2772	#endif /* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	86:04dd9b1680ae	2773
bogdanm	92:4fc01daae5a5	2774	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2775	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	92:4fc01daae5a5	2776	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
bogdanm	92:4fc01daae5a5	2777	* @{
bogdanm	92:4fc01daae5a5	2778	*/
bogdanm	86:04dd9b1680ae	2779
bogdanm	86:04dd9b1680ae	2780	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
bogdanm	86:04dd9b1680ae	2781	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
bogdanm	86:04dd9b1680ae	2782	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2783	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm	86:04dd9b1680ae	2784	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm	86:04dd9b1680ae	2785	*/
bogdanm	86:04dd9b1680ae	2786	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm	86:04dd9b1680ae	2787	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm	86:04dd9b1680ae	2788
bogdanm	86:04dd9b1680ae	2789	/** @brief Macro to get the I2C2 clock source.
bogdanm	86:04dd9b1680ae	2790	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2791	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm	86:04dd9b1680ae	2792	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm	86:04dd9b1680ae	2793	*/
bogdanm	86:04dd9b1680ae	2794	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm	92:4fc01daae5a5	2795	/**
bogdanm	92:4fc01daae5a5	2796	* @}
bogdanm	92:4fc01daae5a5	2797	*/
bogdanm	92:4fc01daae5a5	2798
bogdanm	92:4fc01daae5a5	2799	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm	92:4fc01daae5a5	2800	* @{
bogdanm	92:4fc01daae5a5	2801	*/
bogdanm	86:04dd9b1680ae	2802
bogdanm	86:04dd9b1680ae	2803	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
bogdanm	86:04dd9b1680ae	2804	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
bogdanm	86:04dd9b1680ae	2805	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2806	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
bogdanm	86:04dd9b1680ae	2807	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2808	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2809	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2810	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2811	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2812	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2813	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2814	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2815	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2816	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2817	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2818	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2819	*/
bogdanm	86:04dd9b1680ae	2820	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
bogdanm	86:04dd9b1680ae	2821	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
bogdanm	86:04dd9b1680ae	2822
bogdanm	86:04dd9b1680ae	2823	/** @brief Macro to get the ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2824	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2825	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
bogdanm	86:04dd9b1680ae	2826	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2827	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2828	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2829	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2830	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2831	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2832	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2833	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2834	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2835	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2836	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2837	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	2838	*/
bogdanm	86:04dd9b1680ae	2839	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
bogdanm	92:4fc01daae5a5	2840	/**
bogdanm	92:4fc01daae5a5	2841	* @}
bogdanm	92:4fc01daae5a5	2842	*/
bogdanm	92:4fc01daae5a5	2843
bogdanm	92:4fc01daae5a5	2844	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm	92:4fc01daae5a5	2845	* @{
bogdanm	92:4fc01daae5a5	2846	*/
bogdanm	86:04dd9b1680ae	2847
bogdanm	86:04dd9b1680ae	2848	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
bogdanm	86:04dd9b1680ae	2849	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
bogdanm	86:04dd9b1680ae	2850	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2851	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm	86:04dd9b1680ae	2852	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm	86:04dd9b1680ae	2853	*/
bogdanm	86:04dd9b1680ae	2854	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm	86:04dd9b1680ae	2855	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm	86:04dd9b1680ae	2856
bogdanm	86:04dd9b1680ae	2857	/** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm	86:04dd9b1680ae	2858	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2859	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2860	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm	86:04dd9b1680ae	2861	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm	86:04dd9b1680ae	2862	*/
bogdanm	86:04dd9b1680ae	2863	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm	92:4fc01daae5a5	2864	/**
bogdanm	92:4fc01daae5a5	2865	* @}
bogdanm	92:4fc01daae5a5	2866	*/
bogdanm	92:4fc01daae5a5	2867
bogdanm	92:4fc01daae5a5	2868	/** @defgroup RCCEx_I2Sx_Clock_Config RCC Extended I2Sx Clock Config
bogdanm	92:4fc01daae5a5	2869	* @{
bogdanm	92:4fc01daae5a5	2870	*/
bogdanm	86:04dd9b1680ae	2871
bogdanm	86:04dd9b1680ae	2872	/** @brief Macro to configure the I2S clock source (I2SCLK).
bogdanm	86:04dd9b1680ae	2873	* @note This function must be called before enabling the I2S APB clock.
bogdanm	86:04dd9b1680ae	2874	* @param __I2SCLKSource__: specifies the I2S clock source.
bogdanm	86:04dd9b1680ae	2875	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2876	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
bogdanm	86:04dd9b1680ae	2877	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm	86:04dd9b1680ae	2878	* used as I2S clock source
bogdanm	86:04dd9b1680ae	2879	*/
bogdanm	86:04dd9b1680ae	2880	#define __HAL_RCC_I2S_CONFIG(__I2SCLKSource__) \
bogdanm	86:04dd9b1680ae	2881	MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, (uint32_t)(__I2SCLKSource__))
bogdanm	86:04dd9b1680ae	2882
bogdanm	86:04dd9b1680ae	2883	/** @brief Macro to get the I2S clock source (I2SCLK).
bogdanm	86:04dd9b1680ae	2884	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2885	* @arg RCC_I2SCLKSOURCE_SYSCLK: SYSCLK clock used as I2S clock source
bogdanm	86:04dd9b1680ae	2886	* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
bogdanm	86:04dd9b1680ae	2887	* used as I2S clock source
bogdanm	86:04dd9b1680ae	2888	*/
bogdanm	86:04dd9b1680ae	2889	#define __HAL_RCC_GET_I2S_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_I2SSRC)))
bogdanm	92:4fc01daae5a5	2890	/**
bogdanm	92:4fc01daae5a5	2891	* @}
bogdanm	92:4fc01daae5a5	2892	*/
bogdanm	92:4fc01daae5a5	2893
bogdanm	92:4fc01daae5a5	2894	/** @defgroup RCCEx_UARTx_Clock_Config RCC Extended UARTx Clock Config
bogdanm	92:4fc01daae5a5	2895	* @{
bogdanm	92:4fc01daae5a5	2896	*/
bogdanm	86:04dd9b1680ae	2897
bogdanm	86:04dd9b1680ae	2898	/** @brief Macro to configure the UART4 clock (UART4CLK).
bogdanm	86:04dd9b1680ae	2899	* @param __UART4CLKSource__: specifies the UART4 clock source.
bogdanm	86:04dd9b1680ae	2900	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2901	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
bogdanm	86:04dd9b1680ae	2902	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
bogdanm	86:04dd9b1680ae	2903	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
bogdanm	86:04dd9b1680ae	2904	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
bogdanm	86:04dd9b1680ae	2905	*/
bogdanm	86:04dd9b1680ae	2906	#define __HAL_RCC_UART4_CONFIG(__UART4CLKSource__) \
bogdanm	86:04dd9b1680ae	2907	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART4SW, (uint32_t)(__UART4CLKSource__))
bogdanm	86:04dd9b1680ae	2908
bogdanm	86:04dd9b1680ae	2909	/** @brief Macro to get the UART4 clock source.
bogdanm	86:04dd9b1680ae	2910	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2911	* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
bogdanm	86:04dd9b1680ae	2912	* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
bogdanm	86:04dd9b1680ae	2913	* @arg RCC_UART4CLKSOURCE_SYSCLK: System Clock selected as UART4 clock
bogdanm	86:04dd9b1680ae	2914	* @arg RCC_UART4CLKSOURCE_LSE: LSE selected as UART4 clock
bogdanm	86:04dd9b1680ae	2915	*/
bogdanm	86:04dd9b1680ae	2916	#define __HAL_RCC_GET_UART4_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART4SW)))
bogdanm	86:04dd9b1680ae	2917
bogdanm	86:04dd9b1680ae	2918	/** @brief Macro to configure the UART5 clock (UART5CLK).
bogdanm	86:04dd9b1680ae	2919	* @param __UART5CLKSource__: specifies the UART5 clock source.
bogdanm	86:04dd9b1680ae	2920	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2921	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
bogdanm	86:04dd9b1680ae	2922	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
bogdanm	86:04dd9b1680ae	2923	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
bogdanm	86:04dd9b1680ae	2924	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
bogdanm	86:04dd9b1680ae	2925	*/
bogdanm	86:04dd9b1680ae	2926	#define __HAL_RCC_UART5_CONFIG(__UART5CLKSource__) \
bogdanm	86:04dd9b1680ae	2927	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_UART5SW, (uint32_t)(__UART5CLKSource__))
bogdanm	86:04dd9b1680ae	2928
bogdanm	86:04dd9b1680ae	2929	/** @brief Macro to get the UART5 clock source.
bogdanm	86:04dd9b1680ae	2930	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2931	* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
bogdanm	86:04dd9b1680ae	2932	* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
bogdanm	86:04dd9b1680ae	2933	* @arg RCC_UART5CLKSOURCE_SYSCLK: System Clock selected as UART5 clock
bogdanm	86:04dd9b1680ae	2934	* @arg RCC_UART5CLKSOURCE_LSE: LSE selected as UART5 clock
bogdanm	86:04dd9b1680ae	2935	*/
bogdanm	86:04dd9b1680ae	2936	#define __HAL_RCC_GET_UART5_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_UART5SW)))
bogdanm	92:4fc01daae5a5	2937	/**
bogdanm	92:4fc01daae5a5	2938	* @}
bogdanm	92:4fc01daae5a5	2939	*/
bogdanm	92:4fc01daae5a5	2940	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	2941	/* STM32F302xC \|\| STM32F303xC \|\| STM32F358xx */
bogdanm	92:4fc01daae5a5	2942
bogdanm	92:4fc01daae5a5	2943	#if defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	2944	defined(STM32F303xC) \|\| defined(STM32F358xx)
bogdanm	92:4fc01daae5a5	2945	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm	92:4fc01daae5a5	2946	* @{
bogdanm	92:4fc01daae5a5	2947	*/
bogdanm	86:04dd9b1680ae	2948
bogdanm	86:04dd9b1680ae	2949	/** @brief Macro to configure the ADC3 & ADC4 clock (ADC34CLK).
bogdanm	86:04dd9b1680ae	2950	* @param __ADC34CLKSource__: specifies the ADC3 & ADC4 clock source.
bogdanm	86:04dd9b1680ae	2951	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2952	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
bogdanm	86:04dd9b1680ae	2953	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2954	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2955	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2956	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2957	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2958	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2959	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2960	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2961	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2962	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2963	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2964	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2965	*/
bogdanm	86:04dd9b1680ae	2966	#define __HAL_RCC_ADC34_CONFIG(__ADC34CLKSource__) \
bogdanm	86:04dd9b1680ae	2967	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE34, (uint32_t)(__ADC34CLKSource__))
bogdanm	86:04dd9b1680ae	2968
bogdanm	86:04dd9b1680ae	2969	/** @brief Macro to get the ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2970	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	2971	* @arg RCC_ADC34PLLCLK_OFF: ADC3 & ADC4 PLL clock disabled, ADC3 & ADC4 can use AHB clock
bogdanm	86:04dd9b1680ae	2972	* @arg RCC_ADC34PLLCLK_DIV1: PLL clock divided by 1 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2973	* @arg RCC_ADC34PLLCLK_DIV2: PLL clock divided by 2 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2974	* @arg RCC_ADC34PLLCLK_DIV4: PLL clock divided by 4 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2975	* @arg RCC_ADC34PLLCLK_DIV6: PLL clock divided by 6 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2976	* @arg RCC_ADC34PLLCLK_DIV8: PLL clock divided by 8 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2977	* @arg RCC_ADC34PLLCLK_DIV10: PLL clock divided by 10 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2978	* @arg RCC_ADC34PLLCLK_DIV12: PLL clock divided by 12 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2979	* @arg RCC_ADC34PLLCLK_DIV16: PLL clock divided by 16 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2980	* @arg RCC_ADC34PLLCLK_DIV32: PLL clock divided by 32 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2981	* @arg RCC_ADC34PLLCLK_DIV64: PLL clock divided by 64 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2982	* @arg RCC_ADC34PLLCLK_DIV128: PLL clock divided by 128 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2983	* @arg RCC_ADC34PLLCLK_DIV256: PLL clock divided by 256 selected as ADC3 & ADC4 clock
bogdanm	86:04dd9b1680ae	2984	*/
bogdanm	86:04dd9b1680ae	2985	#define __HAL_RCC_GET_ADC34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE34)))
bogdanm	92:4fc01daae5a5	2986	/**
bogdanm	92:4fc01daae5a5	2987	* @}
bogdanm	92:4fc01daae5a5	2988	*/
bogdanm	92:4fc01daae5a5	2989
bogdanm	92:4fc01daae5a5	2990	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm	92:4fc01daae5a5	2991	* @{
bogdanm	92:4fc01daae5a5	2992	*/
bogdanm	86:04dd9b1680ae	2993
bogdanm	86:04dd9b1680ae	2994	/** @brief Macro to configure the TIM8 clock (TIM8CLK).
bogdanm	86:04dd9b1680ae	2995	* @param __TIM8CLKSource__: specifies the TIM8 clock source.
bogdanm	86:04dd9b1680ae	2996	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	2997	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
bogdanm	86:04dd9b1680ae	2998	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
bogdanm	86:04dd9b1680ae	2999	*/
bogdanm	86:04dd9b1680ae	3000	#define __HAL_RCC_TIM8_CONFIG(__TIM8CLKSource__) \
bogdanm	86:04dd9b1680ae	3001	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM8SW, (uint32_t)(__TIM8CLKSource__))
bogdanm	86:04dd9b1680ae	3002
bogdanm	86:04dd9b1680ae	3003	/** @brief Macro to get the TIM8 clock (TIM8CLK).
bogdanm	86:04dd9b1680ae	3004	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3005	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3006	* @arg RCC_TIM8CLKSOURCE_HCLK: HCLK selected as TIM8 clock
bogdanm	86:04dd9b1680ae	3007	* @arg RCC_TIM8CLKSOURCE_PLL: PLL Clock selected as TIM8 clock
bogdanm	86:04dd9b1680ae	3008	*/
bogdanm	86:04dd9b1680ae	3009	#define __HAL_RCC_GET_TIM8_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM8SW)))
bogdanm	86:04dd9b1680ae	3010
bogdanm	92:4fc01daae5a5	3011	/**
bogdanm	92:4fc01daae5a5	3012	* @}
bogdanm	92:4fc01daae5a5	3013	*/
bogdanm	92:4fc01daae5a5	3014	#endif /* STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	3015	/* STM32F303xC \|\| STM32F358xx */
bogdanm	86:04dd9b1680ae	3016
bogdanm	86:04dd9b1680ae	3017	#if defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx)
bogdanm	92:4fc01daae5a5	3018	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm	92:4fc01daae5a5	3019	* @{
bogdanm	92:4fc01daae5a5	3020	*/
bogdanm	86:04dd9b1680ae	3021
bogdanm	86:04dd9b1680ae	3022	/** @brief Macro to configure the ADC1 & ADC2 clock (ADC12CLK).
bogdanm	86:04dd9b1680ae	3023	* @param __ADC12CLKSource__: specifies the ADC1 & ADC2 clock source.
bogdanm	86:04dd9b1680ae	3024	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3025	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
bogdanm	86:04dd9b1680ae	3026	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3027	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3028	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3029	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3030	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3031	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3032	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3033	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3034	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3035	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3036	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3037	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3038	*/
bogdanm	86:04dd9b1680ae	3039	#define __HAL_RCC_ADC12_CONFIG(__ADC12CLKSource__) \
bogdanm	86:04dd9b1680ae	3040	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_ADCPRE12, (uint32_t)(__ADC12CLKSource__))
bogdanm	86:04dd9b1680ae	3041
bogdanm	86:04dd9b1680ae	3042	/** @brief Macro to get the ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3043	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3044	* @arg RCC_ADC12PLLCLK_OFF: ADC1 & ADC2 PLL clock disabled, ADC1 & ADC2 can use AHB clock
bogdanm	86:04dd9b1680ae	3045	* @arg RCC_ADC12PLLCLK_DIV1: PLL clock divided by 1 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3046	* @arg RCC_ADC12PLLCLK_DIV2: PLL clock divided by 2 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3047	* @arg RCC_ADC12PLLCLK_DIV4: PLL clock divided by 4 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3048	* @arg RCC_ADC12PLLCLK_DIV6: PLL clock divided by 6 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3049	* @arg RCC_ADC12PLLCLK_DIV8: PLL clock divided by 8 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3050	* @arg RCC_ADC12PLLCLK_DIV10: PLL clock divided by 10 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3051	* @arg RCC_ADC12PLLCLK_DIV12: PLL clock divided by 12 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3052	* @arg RCC_ADC12PLLCLK_DIV16: PLL clock divided by 16 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3053	* @arg RCC_ADC12PLLCLK_DIV32: PLL clock divided by 32 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3054	* @arg RCC_ADC12PLLCLK_DIV64: PLL clock divided by 64 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3055	* @arg RCC_ADC12PLLCLK_DIV128: PLL clock divided by 128 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3056	* @arg RCC_ADC12PLLCLK_DIV256: PLL clock divided by 256 selected as ADC1 & ADC2 clock
bogdanm	86:04dd9b1680ae	3057	*/
bogdanm	86:04dd9b1680ae	3058	#define __HAL_RCC_GET_ADC12_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR2, RCC_CFGR2_ADCPRE12)))
bogdanm	92:4fc01daae5a5	3059	/**
bogdanm	92:4fc01daae5a5	3060	* @}
bogdanm	92:4fc01daae5a5	3061	*/
bogdanm	92:4fc01daae5a5	3062
bogdanm	92:4fc01daae5a5	3063	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm	92:4fc01daae5a5	3064	* @{
bogdanm	92:4fc01daae5a5	3065	*/
bogdanm	86:04dd9b1680ae	3066	/** @brief Macro to configure the TIM1 clock (TIM1CLK).
bogdanm	86:04dd9b1680ae	3067	* @param __TIM1CLKSource__: specifies the TIM1 clock source.
bogdanm	86:04dd9b1680ae	3068	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3069	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm	86:04dd9b1680ae	3070	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm	86:04dd9b1680ae	3071	*/
bogdanm	86:04dd9b1680ae	3072	#define __HAL_RCC_TIM1_CONFIG(__TIM1CLKSource__) \
bogdanm	86:04dd9b1680ae	3073	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM1SW, (uint32_t)(__TIM1CLKSource__))
bogdanm	86:04dd9b1680ae	3074
bogdanm	86:04dd9b1680ae	3075	/** @brief Macro to get the TIM1 clock (TIM1CLK).
bogdanm	86:04dd9b1680ae	3076	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3077	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3078	* @arg RCC_TIM1CLKSOURCE_HCLK: HCLK selected as TIM1 clock
bogdanm	86:04dd9b1680ae	3079	* @arg RCC_TIM1CLKSOURCE_PLL: PLL Clock selected as TIM1 clock
bogdanm	86:04dd9b1680ae	3080	*/
bogdanm	86:04dd9b1680ae	3081	#define __HAL_RCC_GET_TIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM1SW)))
bogdanm	92:4fc01daae5a5	3082	/**
bogdanm	92:4fc01daae5a5	3083	* @}
bogdanm	92:4fc01daae5a5	3084	*/
bogdanm	86:04dd9b1680ae	3085	#endif /* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx */
bogdanm	86:04dd9b1680ae	3086
bogdanm	86:04dd9b1680ae	3087	#if defined(STM32F334x8)
bogdanm	92:4fc01daae5a5	3088	/** @defgroup RCCEx_HRTIMx_Clock_Config RCC Extended HRTIMx Clock Config
bogdanm	92:4fc01daae5a5	3089	* @{
bogdanm	92:4fc01daae5a5	3090	*/
bogdanm	86:04dd9b1680ae	3091	/** @brief Macro to configure the HRTIM1 clock.
bogdanm	86:04dd9b1680ae	3092	* @param __HRTIM1CLKSource__: specifies the HRTIM1 clock source.
bogdanm	86:04dd9b1680ae	3093	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3094	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
bogdanm	86:04dd9b1680ae	3095	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
bogdanm	86:04dd9b1680ae	3096	*/
bogdanm	86:04dd9b1680ae	3097	#define __HAL_RCC_HRTIM1_CONFIG(__HRTIM1CLKSource__) \
bogdanm	86:04dd9b1680ae	3098	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_HRTIM1SW, (uint32_t)(__HRTIM1CLKSource__))
bogdanm	86:04dd9b1680ae	3099
bogdanm	86:04dd9b1680ae	3100	/** @brief Macro to get the HRTIM1 clock source.
bogdanm	86:04dd9b1680ae	3101	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3102	* @arg RCC_HRTIM1CLKSOURCE_HCLK: HCLK selected as HRTIM1 clock
bogdanm	86:04dd9b1680ae	3103	* @arg RCC_HRTIM1CLKSOURCE_PLL: PLL Clock selected as HRTIM1 clock
bogdanm	86:04dd9b1680ae	3104	*/
bogdanm	86:04dd9b1680ae	3105	#define __HAL_RCC_GET_HRTIM1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_HRTIM1SW)))
bogdanm	92:4fc01daae5a5	3106	/**
bogdanm	92:4fc01daae5a5	3107	* @}
bogdanm	92:4fc01daae5a5	3108	*/
bogdanm	86:04dd9b1680ae	3109	#endif /* STM32F334x8 */
bogdanm	86:04dd9b1680ae	3110
bogdanm	86:04dd9b1680ae	3111	#if defined(STM32F373xC) \|\| defined(STM32F378xx)
bogdanm	92:4fc01daae5a5	3112	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
bogdanm	92:4fc01daae5a5	3113	* @{
bogdanm	92:4fc01daae5a5	3114	*/
bogdanm	86:04dd9b1680ae	3115	/** @brief Macro to configure the I2C2 clock (I2C2CLK).
bogdanm	86:04dd9b1680ae	3116	* @param __I2C2CLKSource__: specifies the I2C2 clock source.
bogdanm	86:04dd9b1680ae	3117	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3118	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm	86:04dd9b1680ae	3119	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm	86:04dd9b1680ae	3120	*/
bogdanm	86:04dd9b1680ae	3121	#define __HAL_RCC_I2C2_CONFIG(__I2C2CLKSource__) \
bogdanm	86:04dd9b1680ae	3122	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C2SW, (uint32_t)(__I2C2CLKSource__))
bogdanm	86:04dd9b1680ae	3123
bogdanm	86:04dd9b1680ae	3124	/** @brief Macro to get the I2C2 clock source.
bogdanm	86:04dd9b1680ae	3125	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3126	* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
bogdanm	86:04dd9b1680ae	3127	* @arg RCC_I2C2CLKSOURCE_SYSCLK: System Clock selected as I2C2 clock
bogdanm	86:04dd9b1680ae	3128	*/
bogdanm	86:04dd9b1680ae	3129	#define __HAL_RCC_GET_I2C2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C2SW)))
bogdanm	92:4fc01daae5a5	3130	/**
bogdanm	92:4fc01daae5a5	3131	* @}
bogdanm	92:4fc01daae5a5	3132	*/
bogdanm	92:4fc01daae5a5	3133
bogdanm	92:4fc01daae5a5	3134	/** @defgroup RCCEx_ADCx_Clock_Config RCC Extended ADCx Clock Config
bogdanm	92:4fc01daae5a5	3135	* @{
bogdanm	92:4fc01daae5a5	3136	*/
bogdanm	86:04dd9b1680ae	3137	/** @brief Macro to configure the ADC1 clock (ADC1CLK).
bogdanm	86:04dd9b1680ae	3138	* @param __ADC1CLKSource__: specifies the ADC1 clock source.
bogdanm	86:04dd9b1680ae	3139	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3140	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	3141	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	3142	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	3143	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	3144	*/
bogdanm	86:04dd9b1680ae	3145	#define __HAL_RCC_ADC1_CONFIG(__ADC1CLKSource__) \
bogdanm	86:04dd9b1680ae	3146	MODIFY_REG(RCC->CFGR, RCC_CFGR_ADCPRE, (uint32_t)(__ADC1CLKSource__))
bogdanm	86:04dd9b1680ae	3147
bogdanm	86:04dd9b1680ae	3148	/** @brief Macro to get the ADC1 clock (ADC1CLK).
bogdanm	86:04dd9b1680ae	3149	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3150	* @arg RCC_ADC1PCLK2_DIV2: PCLK2 clock divided by 2 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	3151	* @arg RCC_ADC1PCLK2_DIV4: PCLK2 clock divided by 4 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	3152	* @arg RCC_ADC1PCLK2_DIV6: PCLK2 clock divided by 6 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	3153	* @arg RCC_ADC1PCLK2_DIV8: PCLK2 clock divided by 8 selected as ADC1 clock
bogdanm	86:04dd9b1680ae	3154	*/
bogdanm	86:04dd9b1680ae	3155	#define __HAL_RCC_GET_ADC1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_ADCPRE)))
bogdanm	92:4fc01daae5a5	3156	/**
bogdanm	92:4fc01daae5a5	3157	* @}
bogdanm	92:4fc01daae5a5	3158	*/
bogdanm	92:4fc01daae5a5	3159
bogdanm	92:4fc01daae5a5	3160	/** @defgroup RCCEx_SDADCx_Clock_Config RCC Extended SDADCx Clock Config
bogdanm	92:4fc01daae5a5	3161	* @{
bogdanm	92:4fc01daae5a5	3162	*/
bogdanm	86:04dd9b1680ae	3163	/** @brief Macro to configure the SDADCx clock (SDADCxCLK).
bogdanm	86:04dd9b1680ae	3164	* @param __SDADCPrescaler__: specifies the SDADCx system clock prescaler.
bogdanm	86:04dd9b1680ae	3165	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3166	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3167	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3168	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3169	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3170	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3171	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3172	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3173	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3174	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3175	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3176	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3177	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3178	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3179	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3180	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3181	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3182	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3183	*/
bogdanm	86:04dd9b1680ae	3184	#define __HAL_RCC_SDADC_CONFIG(__SDADCPrescaler__) \
bogdanm	86:04dd9b1680ae	3185	MODIFY_REG(RCC->CFGR, RCC_CFGR_SDADCPRE, (uint32_t)(__SDADCPrescaler__))
bogdanm	86:04dd9b1680ae	3186
bogdanm	86:04dd9b1680ae	3187	/** @brief Macro to get the SDADCx clock prescaler.
bogdanm	86:04dd9b1680ae	3188	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3189	* @arg RCC_SDADCSYSCLK_DIV1: SYSCLK clock selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3190	* @arg RCC_SDADCSYSCLK_DIV2: SYSCLK clock divided by 2 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3191	* @arg RCC_SDADCSYSCLK_DIV4: SYSCLK clock divided by 4 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3192	* @arg RCC_SDADCSYSCLK_DIV6: SYSCLK clock divided by 6 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3193	* @arg RCC_SDADCSYSCLK_DIV8: SYSCLK clock divided by 8 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3194	* @arg RCC_SDADCSYSCLK_DIV10: SYSCLK clock divided by 10 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3195	* @arg RCC_SDADCSYSCLK_DIV12: SYSCLK clock divided by 12 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3196	* @arg RCC_SDADCSYSCLK_DIV14: SYSCLK clock divided by 14 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3197	* @arg RCC_SDADCSYSCLK_DIV16: SYSCLK clock divided by 16 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3198	* @arg RCC_SDADCSYSCLK_DIV20: SYSCLK clock divided by 20 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3199	* @arg RCC_SDADCSYSCLK_DIV24: SYSCLK clock divided by 24 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3200	* @arg RCC_SDADCSYSCLK_DIV28: SYSCLK clock divided by 28 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3201	* @arg RCC_SDADCSYSCLK_DIV32: SYSCLK clock divided by 32 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3202	* @arg RCC_SDADCSYSCLK_DIV36: SYSCLK clock divided by 36 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3203	* @arg RCC_SDADCSYSCLK_DIV40: SYSCLK clock divided by 40 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3204	* @arg RCC_SDADCSYSCLK_DIV44: SYSCLK clock divided by 44 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3205	* @arg RCC_SDADCSYSCLK_DIV48: SYSCLK clock divided by 48 selected as SDADCx clock
bogdanm	86:04dd9b1680ae	3206	*/
bogdanm	86:04dd9b1680ae	3207	#define __HAL_RCC_GET_SDADC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SDADCPRE)))
bogdanm	92:4fc01daae5a5	3208	/**
bogdanm	92:4fc01daae5a5	3209	* @}
bogdanm	92:4fc01daae5a5	3210	*/
bogdanm	92:4fc01daae5a5	3211
bogdanm	92:4fc01daae5a5	3212	/** @defgroup RCCEx_CECx_Clock_Config RCC Extended CECx Clock Config
bogdanm	92:4fc01daae5a5	3213	* @{
bogdanm	92:4fc01daae5a5	3214	*/
bogdanm	86:04dd9b1680ae	3215	/** @brief Macro to configure the CEC clock.
bogdanm	86:04dd9b1680ae	3216	* @param __CECCLKSource__: specifies the CEC clock source.
bogdanm	86:04dd9b1680ae	3217	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3218	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	86:04dd9b1680ae	3219	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	86:04dd9b1680ae	3220	*/
bogdanm	86:04dd9b1680ae	3221	#define __HAL_RCC_CEC_CONFIG(__CECCLKSource__) \
bogdanm	86:04dd9b1680ae	3222	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_CECSW, (uint32_t)(__CECCLKSource__))
bogdanm	86:04dd9b1680ae	3223
bogdanm	86:04dd9b1680ae	3224	/** @brief Macro to get the HDMI CEC clock source.
bogdanm	86:04dd9b1680ae	3225	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3226	* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
bogdanm	86:04dd9b1680ae	3227	* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
bogdanm	86:04dd9b1680ae	3228	*/
bogdanm	86:04dd9b1680ae	3229	#define __HAL_RCC_GET_CEC_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_CECSW)))
bogdanm	92:4fc01daae5a5	3230	/**
bogdanm	92:4fc01daae5a5	3231	* @}
bogdanm	92:4fc01daae5a5	3232	*/
bogdanm	86:04dd9b1680ae	3233
bogdanm	86:04dd9b1680ae	3234	#endif /* STM32F373xC \|\| STM32F378xx */
bogdanm	86:04dd9b1680ae	3235
bogdanm	92:4fc01daae5a5	3236	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| \
bogdanm	92:4fc01daae5a5	3237	defined(STM32F302xC) \|\| defined(STM32F303xC) \|\| \
bogdanm	92:4fc01daae5a5	3238	defined(STM32F302x8) \|\| \
bogdanm	92:4fc01daae5a5	3239	defined(STM32F373xC)
bogdanm	92:4fc01daae5a5	3240
bogdanm	92:4fc01daae5a5	3241	/** @defgroup RCCEx_USBx_Clock_Config RCC Extended USBx Clock Config
bogdanm	92:4fc01daae5a5	3242	* @{
bogdanm	92:4fc01daae5a5	3243	*/
bogdanm	86:04dd9b1680ae	3244	/** @brief Macro to configure the USB clock (USBCLK).
bogdanm	86:04dd9b1680ae	3245	* @param __USBCLKSource__: specifies the USB clock source.
bogdanm	86:04dd9b1680ae	3246	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3247	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
bogdanm	86:04dd9b1680ae	3248	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
bogdanm	86:04dd9b1680ae	3249	*/
bogdanm	86:04dd9b1680ae	3250	#define __HAL_RCC_USB_CONFIG(__USBCLKSource__) \
bogdanm	86:04dd9b1680ae	3251	MODIFY_REG(RCC->CFGR, RCC_CFGR_USBPRE, (uint32_t)(__USBCLKSource__))
bogdanm	86:04dd9b1680ae	3252
bogdanm	86:04dd9b1680ae	3253	/** @brief Macro to get the USB clock source.
bogdanm	86:04dd9b1680ae	3254	* @retval The clock source can be one of the following values:
bogdanm	86:04dd9b1680ae	3255	* @arg RCC_USBPLLCLK_DIV1: PLL Clock divided by 1 selected as USB clock
bogdanm	86:04dd9b1680ae	3256	* @arg RCC_USBPLLCLK_DIV1_5: PLL Clock divided by 1.5 selected as USB clock
bogdanm	86:04dd9b1680ae	3257	*/
bogdanm	86:04dd9b1680ae	3258	#define __HAL_RCC_GET_USB_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_USBPRE)))
bogdanm	92:4fc01daae5a5	3259	/**
bogdanm	92:4fc01daae5a5	3260	* @}
bogdanm	92:4fc01daae5a5	3261	*/
bogdanm	92:4fc01daae5a5	3262
bogdanm	92:4fc01daae5a5	3263	#endif /* STM32F302xE \|\| STM32F303xE \|\| */
bogdanm	92:4fc01daae5a5	3264	/* STM32F302xC \|\| STM32F303xC \|\| */
bogdanm	92:4fc01daae5a5	3265	/* STM32F302x8 \|\| */
bogdanm	92:4fc01daae5a5	3266	/* STM32F373xC */
bogdanm	92:4fc01daae5a5	3267
bogdanm	92:4fc01daae5a5	3268	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx) \|\| \
bogdanm	92:4fc01daae5a5	3269	defined(STM32F303x8) \|\| defined(STM32F334x8) \|\| defined(STM32F328xx) \|\| \
bogdanm	92:4fc01daae5a5	3270	defined(STM32F301x8) \|\| defined(STM32F302x8) \|\| defined(STM32F318xx)
bogdanm	92:4fc01daae5a5	3271
bogdanm	92:4fc01daae5a5	3272	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
bogdanm	92:4fc01daae5a5	3273	* @{
bogdanm	92:4fc01daae5a5	3274	*/
bogdanm	86:04dd9b1680ae	3275	/** @brief macro to configure the MCO clock.
bogdanm	86:04dd9b1680ae	3276	* @param __MCOCLKSource__: specifies the MCO clock source.
bogdanm	86:04dd9b1680ae	3277	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3278	* @arg RCC_MCOSOURCE_HSI: HSI selected as MCO clock
bogdanm	86:04dd9b1680ae	3279	* @arg RCC_MCOSOURCE_HSE: HSE selected as MCO clock
bogdanm	86:04dd9b1680ae	3280	* @arg RCC_MCOSOURCE_LSI: LSI selected as MCO clock
bogdanm	86:04dd9b1680ae	3281	* @arg RCC_MCOSOURCE_LSE: LSE selected as MCO clock
bogdanm	86:04dd9b1680ae	3282	* @arg RCC_MCOSOURCE_PLLCLK_DIV2: PLLCLK Divided by 2 selected as MCO clock
bogdanm	86:04dd9b1680ae	3283	* @arg RCC_MCOSOURCE_SYSCLK: System Clock selected as MCO clock
bogdanm	86:04dd9b1680ae	3284	* @param __MCODiv__: specifies the MCO clock prescaler.
bogdanm	86:04dd9b1680ae	3285	* This parameter can be one of the following values:
bogdanm	86:04dd9b1680ae	3286	* @arg RCC_MCO_NODIV: No division applied on MCO clock source
bogdanm	86:04dd9b1680ae	3287	*/
bogdanm	86:04dd9b1680ae	3288	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	86:04dd9b1680ae	3289	MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO \| RCC_CFGR_MCOPRE), ((__MCOCLKSource__) \| (__MCODiv__)))
bogdanm	92:4fc01daae5a5	3290	/**
bogdanm	92:4fc01daae5a5	3291	* @}
bogdanm	92:4fc01daae5a5	3292	*/
bogdanm	86:04dd9b1680ae	3293	#else
bogdanm	92:4fc01daae5a5	3294	/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
bogdanm	92:4fc01daae5a5	3295	* @{
bogdanm	92:4fc01daae5a5	3296	*/
bogdanm	86:04dd9b1680ae	3297
bogdanm	86:04dd9b1680ae	3298	#define __HAL_RCC_MCO_CONFIG(__MCOCLKSource__, __MCODiv__) \
bogdanm	86:04dd9b1680ae	3299	MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSource__))
bogdanm	92:4fc01daae5a5	3300	/**
bogdanm	92:4fc01daae5a5	3301	* @}
bogdanm	92:4fc01daae5a5	3302	*/
bogdanm	92:4fc01daae5a5	3303
bogdanm	92:4fc01daae5a5	3304	#endif /* STM32F302xE \|\| STM32F303xE \|\| STM32F398xx \|\| */
bogdanm	92:4fc01daae5a5	3305	/* STM32F303x8 \|\| STM32F334x8 \|\| STM32F328xx \|\| */
bogdanm	92:4fc01daae5a5	3306	/* STM32F301x8 \|\| STM32F302x8 \|\| STM32F318xx */
bogdanm	92:4fc01daae5a5	3307
bogdanm	92:4fc01daae5a5	3308	#if defined(STM32F302xE) \|\| defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	3309
bogdanm	92:4fc01daae5a5	3310	/** @defgroup RCCEx_I2Cx_Clock_Config RCC Extended I2Cx Clock Config
bogdanm	92:4fc01daae5a5	3311	* @{
bogdanm	92:4fc01daae5a5	3312	*/
bogdanm	92:4fc01daae5a5	3313	/** @brief Macro to configure the I2C3 clock (I2C3CLK).
bogdanm	92:4fc01daae5a5	3314	* @param __I2C3CLKSource__: specifies the I2C3 clock source.
bogdanm	92:4fc01daae5a5	3315	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3316	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	92:4fc01daae5a5	3317	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	92:4fc01daae5a5	3318	*/
bogdanm	92:4fc01daae5a5	3319	#define __HAL_RCC_I2C3_CONFIG(__I2C3CLKSource__) \
bogdanm	92:4fc01daae5a5	3320	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C3SW, (uint32_t)(__I2C3CLKSource__))
bogdanm	92:4fc01daae5a5	3321
bogdanm	92:4fc01daae5a5	3322	/** @brief Macro to get the I2C3 clock source.
bogdanm	92:4fc01daae5a5	3323	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	3324	* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
bogdanm	92:4fc01daae5a5	3325	* @arg RCC_I2C3CLKSOURCE_SYSCLK: System Clock selected as I2C3 clock
bogdanm	92:4fc01daae5a5	3326	*/
bogdanm	92:4fc01daae5a5	3327	#define __HAL_RCC_GET_I2C3_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C3SW)))
bogdanm	92:4fc01daae5a5	3328	/**
bogdanm	92:4fc01daae5a5	3329	* @}
bogdanm	92:4fc01daae5a5	3330	*/
bogdanm	92:4fc01daae5a5	3331
bogdanm	92:4fc01daae5a5	3332	/** @defgroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm	92:4fc01daae5a5	3333	* @{
bogdanm	92:4fc01daae5a5	3334	*/
bogdanm	92:4fc01daae5a5	3335	/** @brief Macro to configure the TIM2 clock (TIM2CLK).
bogdanm	92:4fc01daae5a5	3336	* @param __TIM2CLKSource__: specifies the TIM2 clock source.
bogdanm	92:4fc01daae5a5	3337	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3338	* @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
bogdanm	92:4fc01daae5a5	3339	* @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
bogdanm	92:4fc01daae5a5	3340	*/
bogdanm	92:4fc01daae5a5	3341	#define __HAL_RCC_TIM2_CONFIG(__TIM2CLKSource__) \
bogdanm	92:4fc01daae5a5	3342	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM2SW, (uint32_t)(__TIM2CLKSource__))
bogdanm	92:4fc01daae5a5	3343
bogdanm	92:4fc01daae5a5	3344	/** @brief Macro to get the TIM2 clock (TIM2CLK).
bogdanm	92:4fc01daae5a5	3345	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	3346	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3347	* @arg RCC_TIM2CLK_HCLK: HCLK selected as TIM2 clock
bogdanm	92:4fc01daae5a5	3348	* @arg RCC_TIM2CLK_PLL: PLL Clock selected as TIM2 clock
bogdanm	92:4fc01daae5a5	3349	*/
bogdanm	92:4fc01daae5a5	3350	#define __HAL_RCC_GET_TIM2_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM2SW)))
bogdanm	92:4fc01daae5a5	3351
bogdanm	92:4fc01daae5a5	3352	/** @brief Macro to configure the TIM3 & TIM4 clock (TIM34CLK).
bogdanm	92:4fc01daae5a5	3353	* @param __TIM3CLKSource__: specifies the TIM3 & TIM4 clock source.
bogdanm	92:4fc01daae5a5	3354	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3355	* @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
bogdanm	92:4fc01daae5a5	3356	* @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
bogdanm	92:4fc01daae5a5	3357	*/
bogdanm	92:4fc01daae5a5	3358	#define __HAL_RCC_TIM34_CONFIG(__TIM34CLKSource__) \
bogdanm	92:4fc01daae5a5	3359	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM34SW, (uint32_t)(__TIM34CLKSource__))
bogdanm	92:4fc01daae5a5	3360
bogdanm	92:4fc01daae5a5	3361	/** @brief Macro to get the TIM3 & TIM4 clock (TIM34CLK).
bogdanm	92:4fc01daae5a5	3362	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	3363	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3364	* @arg RCC_TIM34CLK_HCLK: HCLK selected as TIM3 & TIM4 clock
bogdanm	92:4fc01daae5a5	3365	* @arg RCC_TIM34CLK_PLL: PLL Clock selected as TIM3 & TIM4 clock
bogdanm	92:4fc01daae5a5	3366	*/
bogdanm	92:4fc01daae5a5	3367	#define __HAL_RCC_GET_TIM34_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM34SW)))
bogdanm	92:4fc01daae5a5	3368
bogdanm	92:4fc01daae5a5	3369	/** @brief Macro to configure the TIM15 clock (TIM15CLK).
bogdanm	92:4fc01daae5a5	3370	* @param __TIM15CLKSource__: specifies the TIM15 clock source.
bogdanm	92:4fc01daae5a5	3371	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3372	* @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
bogdanm	92:4fc01daae5a5	3373	* @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
bogdanm	92:4fc01daae5a5	3374	*/
bogdanm	92:4fc01daae5a5	3375	#define __HAL_RCC_TIM15_CONFIG(__TIM15CLKSource__) \
bogdanm	92:4fc01daae5a5	3376	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM15SW, (uint32_t)(__TIM15CLKSource__))
bogdanm	92:4fc01daae5a5	3377
bogdanm	92:4fc01daae5a5	3378	/** @brief Macro to get the TIM15 clock (TIM15CLK).
bogdanm	92:4fc01daae5a5	3379	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	3380	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3381	* @arg RCC_TIM15CLK_HCLK: HCLK selected as TIM15 clock
bogdanm	92:4fc01daae5a5	3382	* @arg RCC_TIM15CLK_PLL: PLL Clock selected as TIM15 clock
bogdanm	92:4fc01daae5a5	3383	*/
bogdanm	92:4fc01daae5a5	3384	#define __HAL_RCC_GET_TIM15_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM15SW)))
bogdanm	92:4fc01daae5a5	3385
bogdanm	92:4fc01daae5a5	3386	/** @brief Macro to configure the TIM16 clock (TIM16CLK).
bogdanm	92:4fc01daae5a5	3387	* @param __TIM16CLKSource__: specifies the TIM16 clock source.
bogdanm	92:4fc01daae5a5	3388	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3389	* @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
bogdanm	92:4fc01daae5a5	3390	* @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
bogdanm	92:4fc01daae5a5	3391	*/
bogdanm	92:4fc01daae5a5	3392	#define __HAL_RCC_TIM16_CONFIG(__TIM16CLKSource__) \
bogdanm	92:4fc01daae5a5	3393	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM16SW, (uint32_t)(__TIM16CLKSource__))
bogdanm	92:4fc01daae5a5	3394
bogdanm	92:4fc01daae5a5	3395	/** @brief Macro to get the TIM16 clock (TIM16CLK).
bogdanm	92:4fc01daae5a5	3396	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	3397	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3398	* @arg RCC_TIM16CLK_HCLK: HCLK selected as TIM16 clock
bogdanm	92:4fc01daae5a5	3399	* @arg RCC_TIM16CLK_PLL: PLL Clock selected as TIM16 clock
bogdanm	92:4fc01daae5a5	3400	*/
bogdanm	92:4fc01daae5a5	3401	#define __HAL_RCC_GET_TIM16_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM16SW)))
bogdanm	92:4fc01daae5a5	3402
bogdanm	92:4fc01daae5a5	3403	/** @brief Macro to configure the TIM17 clock (TIM17CLK).
bogdanm	92:4fc01daae5a5	3404	* @param __TIM17CLKSource__: specifies the TIM17 clock source.
bogdanm	92:4fc01daae5a5	3405	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3406	* @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
bogdanm	92:4fc01daae5a5	3407	* @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
bogdanm	92:4fc01daae5a5	3408	*/
bogdanm	92:4fc01daae5a5	3409	#define __HAL_RCC_TIM17_CONFIG(__TIM17CLKSource__) \
bogdanm	92:4fc01daae5a5	3410	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM17SW, (uint32_t)(__TIM17CLKSource__))
bogdanm	92:4fc01daae5a5	3411
bogdanm	92:4fc01daae5a5	3412	/** @brief Macro to get the TIM17 clock (TIM17CLK).
bogdanm	92:4fc01daae5a5	3413	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	3414	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3415	* @arg RCC_TIM17CLK_HCLK: HCLK selected as TIM17 clock
bogdanm	92:4fc01daae5a5	3416	* @arg RCC_TIM17CLK_PLL: PLL Clock selected as TIM17 clock
bogdanm	92:4fc01daae5a5	3417	*/
bogdanm	92:4fc01daae5a5	3418	#define __HAL_RCC_GET_TIM17_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM17SW)))
bogdanm	92:4fc01daae5a5	3419
bogdanm	92:4fc01daae5a5	3420	/**
bogdanm	92:4fc01daae5a5	3421	* @}
bogdanm	92:4fc01daae5a5	3422	*/
bogdanm	92:4fc01daae5a5	3423
bogdanm	92:4fc01daae5a5	3424	#endif /* STM32f302xE \|\| STM32f303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	3425
bogdanm	92:4fc01daae5a5	3426	#if defined(STM32F303xE) \|\| defined(STM32F398xx)
bogdanm	92:4fc01daae5a5	3427	/** @addtogroup RCCEx_TIMx_Clock_Config RCC Extended TIMx Clock Config
bogdanm	92:4fc01daae5a5	3428	* @{
bogdanm	92:4fc01daae5a5	3429	*/
bogdanm	92:4fc01daae5a5	3430	/** @brief Macro to configure the TIM20 clock (TIM20CLK).
bogdanm	92:4fc01daae5a5	3431	* @param __TIM20CLKSource__: specifies the TIM20 clock source.
bogdanm	92:4fc01daae5a5	3432	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3433	* @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
bogdanm	92:4fc01daae5a5	3434	* @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
bogdanm	92:4fc01daae5a5	3435	*/
bogdanm	92:4fc01daae5a5	3436	#define __HAL_RCC_TIM20_CONFIG(__TIM20CLKSource__) \
bogdanm	92:4fc01daae5a5	3437	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_TIM20SW, (uint32_t)(__TIM20CLKSource__))
bogdanm	92:4fc01daae5a5	3438
bogdanm	92:4fc01daae5a5	3439	/** @brief Macro to get the TIM20 clock (TIM20CLK).
bogdanm	92:4fc01daae5a5	3440	* @retval The clock source can be one of the following values:
bogdanm	92:4fc01daae5a5	3441	* This parameter can be one of the following values:
bogdanm	92:4fc01daae5a5	3442	* @arg RCC_TIM20CLK_HCLK: HCLK selected as TIM20 clock
bogdanm	92:4fc01daae5a5	3443	* @arg RCC_TIM20CLK_PLL: PLL Clock selected as TIM20 clock
bogdanm	92:4fc01daae5a5	3444	*/
bogdanm	92:4fc01daae5a5	3445	#define __HAL_RCC_GET_TIM20_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_TIM20SW)))
bogdanm	92:4fc01daae5a5	3446
bogdanm	92:4fc01daae5a5	3447	/**
bogdanm	92:4fc01daae5a5	3448	* @}
bogdanm	92:4fc01daae5a5	3449	*/
bogdanm	92:4fc01daae5a5	3450	#endif /* STM32f303xE \|\| STM32F398xx */
bogdanm	92:4fc01daae5a5	3451
bogdanm	86:04dd9b1680ae	3452
bogdanm	86:04dd9b1680ae	3453	/**
bogdanm	86:04dd9b1680ae	3454	* @}
bogdanm	86:04dd9b1680ae	3455	*/
bogdanm	86:04dd9b1680ae	3456
bogdanm	86:04dd9b1680ae	3457	/* Exported functions --------------------------------------------------------*/
bogdanm	92:4fc01daae5a5	3458	/** @addtogroup RCCEx_Exported_Functions RCC Extended Exported Functions
bogdanm	92:4fc01daae5a5	3459	* @{
bogdanm	92:4fc01daae5a5	3460	*/
bogdanm	92:4fc01daae5a5	3461
bogdanm	92:4fc01daae5a5	3462	/** @addtogroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
bogdanm	92:4fc01daae5a5	3463	* @{
bogdanm	92:4fc01daae5a5	3464	*/
bogdanm	86:04dd9b1680ae	3465	HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	86:04dd9b1680ae	3466	void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
bogdanm	92:4fc01daae5a5	3467	/**
bogdanm	92:4fc01daae5a5	3468	* @}
bogdanm	92:4fc01daae5a5	3469	*/
bogdanm	86:04dd9b1680ae	3470
bogdanm	86:04dd9b1680ae	3471	/**
bogdanm	86:04dd9b1680ae	3472	* @}
bogdanm	86:04dd9b1680ae	3473	*/
bogdanm	86:04dd9b1680ae	3474
bogdanm	86:04dd9b1680ae	3475	/**
bogdanm	86:04dd9b1680ae	3476	* @}
bogdanm	86:04dd9b1680ae	3477	*/
bogdanm	86:04dd9b1680ae	3478
bogdanm	92:4fc01daae5a5	3479	/**
bogdanm	92:4fc01daae5a5	3480	* @}
bogdanm	92:4fc01daae5a5	3481	*/
bogdanm	86:04dd9b1680ae	3482	#ifdef __cplusplus
bogdanm	86:04dd9b1680ae	3483	}
bogdanm	86:04dd9b1680ae	3484	#endif
bogdanm	86:04dd9b1680ae	3485
bogdanm	86:04dd9b1680ae	3486	#endif /* __STM32F3xx_HAL_RCC_EX_H */
bogdanm	86:04dd9b1680ae	3487
bogdanm	86:04dd9b1680ae	3488	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F334R8/stm32f3xx_hal_rcc_ex.h@97:4298809c7c9e, 2015-04-08 (annotated)

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