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TARGET_NUCLEO_F091RC/stm32f0xx_hal_dma.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:
filartrix
Date:
Wed Apr 08 14:12:53 2015 +0000
Revision:
97:4298809c7c9e
Parent:
93:e188a91d3eaa 
First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 90:cb3d968589d8 1 /**
Kojto 90:cb3d968589d8 2 ******************************************************************************
Kojto 90:cb3d968589d8 3 * @file stm32f0xx_hal_dma.h
Kojto 90:cb3d968589d8 4 * @author MCD Application Team
Kojto 93:e188a91d3eaa 5 * @version V1.2.0
Kojto 93:e188a91d3eaa 6 * @date 11-December-2014
Kojto 90:cb3d968589d8 7 * @brief Header file of DMA HAL module.
Kojto 90:cb3d968589d8 8 ******************************************************************************
Kojto 90:cb3d968589d8 9 * @attention
Kojto 90:cb3d968589d8 10 *
Kojto 90:cb3d968589d8 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto 90:cb3d968589d8 12 *
Kojto 90:cb3d968589d8 13 * Redistribution and use in source and binary forms, with or without modification,
Kojto 90:cb3d968589d8 14 * are permitted provided that the following conditions are met:
Kojto 90:cb3d968589d8 15 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 90:cb3d968589d8 16 * this list of conditions and the following disclaimer.
Kojto 90:cb3d968589d8 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 90:cb3d968589d8 18 * this list of conditions and the following disclaimer in the documentation
Kojto 90:cb3d968589d8 19 * and/or other materials provided with the distribution.
Kojto 90:cb3d968589d8 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 90:cb3d968589d8 21 * may be used to endorse or promote products derived from this software
Kojto 90:cb3d968589d8 22 * without specific prior written permission.
Kojto 90:cb3d968589d8 23 *
Kojto 90:cb3d968589d8 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 90:cb3d968589d8 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 90:cb3d968589d8 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 90:cb3d968589d8 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 90:cb3d968589d8 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 90:cb3d968589d8 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 90:cb3d968589d8 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 90:cb3d968589d8 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 90:cb3d968589d8 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 90:cb3d968589d8 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 90:cb3d968589d8 34 *
Kojto 90:cb3d968589d8 35 ******************************************************************************
Kojto 90:cb3d968589d8 36 */
Kojto 90:cb3d968589d8 37
Kojto 90:cb3d968589d8 38 /* Define to prevent recursive inclusion -------------------------------------*/
Kojto 90:cb3d968589d8 39 #ifndef __STM32F0xx_HAL_DMA_H
Kojto 90:cb3d968589d8 40 #define __STM32F0xx_HAL_DMA_H
Kojto 90:cb3d968589d8 41
Kojto 90:cb3d968589d8 42 #ifdef __cplusplus
Kojto 90:cb3d968589d8 43 extern "C" {
Kojto 90:cb3d968589d8 44 #endif
Kojto 90:cb3d968589d8 45
Kojto 90:cb3d968589d8 46 /* Includes ------------------------------------------------------------------*/
Kojto 90:cb3d968589d8 47 #include "stm32f0xx_hal_def.h"
Kojto 90:cb3d968589d8 48
Kojto 90:cb3d968589d8 49 /** @addtogroup STM32F0xx_HAL_Driver
Kojto 90:cb3d968589d8 50 * @{
Kojto 90:cb3d968589d8 51 */
Kojto 90:cb3d968589d8 52
Kojto 90:cb3d968589d8 53 /** @addtogroup DMA
Kojto 90:cb3d968589d8 54 * @{
Kojto 90:cb3d968589d8 55 */
Kojto 90:cb3d968589d8 56
Kojto 90:cb3d968589d8 57 /* Exported types ------------------------------------------------------------*/
Kojto 90:cb3d968589d8 58 /** @defgroup DMA_Exported_Types DMA Exported Types
Kojto 90:cb3d968589d8 59 * @{
Kojto 90:cb3d968589d8 60 */
Kojto 90:cb3d968589d8 61
Kojto 90:cb3d968589d8 62 /**
Kojto 90:cb3d968589d8 63 * @brief DMA Configuration Structure definition
Kojto 90:cb3d968589d8 64 */
Kojto 90:cb3d968589d8 65 typedef struct
Kojto 90:cb3d968589d8 66 {
Kojto 90:cb3d968589d8 67 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
Kojto 90:cb3d968589d8 68 from memory to memory or from peripheral to memory.
Kojto 90:cb3d968589d8 69 This parameter can be a value of @ref DMA_Data_transfer_direction */
Kojto 90:cb3d968589d8 70
Kojto 90:cb3d968589d8 71 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
Kojto 90:cb3d968589d8 72 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
Kojto 90:cb3d968589d8 73
Kojto 90:cb3d968589d8 74 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
Kojto 90:cb3d968589d8 75 This parameter can be a value of @ref DMA_Memory_incremented_mode */
Kojto 90:cb3d968589d8 76
Kojto 90:cb3d968589d8 77 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
Kojto 90:cb3d968589d8 78 This parameter can be a value of @ref DMA_Peripheral_data_size */
Kojto 90:cb3d968589d8 79
Kojto 90:cb3d968589d8 80 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
Kojto 90:cb3d968589d8 81 This parameter can be a value of @ref DMA_Memory_data_size */
Kojto 90:cb3d968589d8 82
Kojto 90:cb3d968589d8 83 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
Kojto 90:cb3d968589d8 84 This parameter can be a value of @ref DMA_mode
Kojto 90:cb3d968589d8 85 @note The circular buffer mode cannot be used if the memory-to-memory
Kojto 90:cb3d968589d8 86 data transfer is configured on the selected Channel */
Kojto 90:cb3d968589d8 87
Kojto 90:cb3d968589d8 88 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
Kojto 90:cb3d968589d8 89 This parameter can be a value of @ref DMA_Priority_level */
Kojto 90:cb3d968589d8 90
Kojto 90:cb3d968589d8 91 } DMA_InitTypeDef;
Kojto 90:cb3d968589d8 92
Kojto 90:cb3d968589d8 93 /**
Kojto 90:cb3d968589d8 94 * @brief DMA Configuration enumeration values definition
Kojto 90:cb3d968589d8 95 */
Kojto 90:cb3d968589d8 96 typedef enum
Kojto 90:cb3d968589d8 97 {
Kojto 90:cb3d968589d8 98 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
Kojto 90:cb3d968589d8 99 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
Kojto 90:cb3d968589d8 100
Kojto 90:cb3d968589d8 101 } DMA_ControlTypeDef;
Kojto 90:cb3d968589d8 102
Kojto 90:cb3d968589d8 103 /**
Kojto 90:cb3d968589d8 104 * @brief HAL DMA State structures definition
Kojto 90:cb3d968589d8 105 */
Kojto 90:cb3d968589d8 106 typedef enum
Kojto 90:cb3d968589d8 107 {
Kojto 90:cb3d968589d8 108 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
Kojto 90:cb3d968589d8 109 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
Kojto 90:cb3d968589d8 110 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
Kojto 90:cb3d968589d8 111 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
Kojto 90:cb3d968589d8 112 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
Kojto 90:cb3d968589d8 113 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
Kojto 90:cb3d968589d8 114
Kojto 90:cb3d968589d8 115 }HAL_DMA_StateTypeDef;
Kojto 90:cb3d968589d8 116
Kojto 90:cb3d968589d8 117 /**
Kojto 90:cb3d968589d8 118 * @brief HAL DMA Error Code structure definition
Kojto 90:cb3d968589d8 119 */
Kojto 90:cb3d968589d8 120 typedef enum
Kojto 90:cb3d968589d8 121 {
Kojto 90:cb3d968589d8 122 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
Kojto 90:cb3d968589d8 123 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
Kojto 90:cb3d968589d8 124
Kojto 90:cb3d968589d8 125 }HAL_DMA_LevelCompleteTypeDef;
Kojto 90:cb3d968589d8 126
Kojto 90:cb3d968589d8 127
Kojto 90:cb3d968589d8 128 /**
Kojto 90:cb3d968589d8 129 * @brief DMA handle Structure definition
Kojto 90:cb3d968589d8 130 */
Kojto 90:cb3d968589d8 131 typedef struct __DMA_HandleTypeDef
Kojto 90:cb3d968589d8 132 {
Kojto 90:cb3d968589d8 133 DMA_Channel_TypeDef *Instance; /*!< Register base address */
Kojto 90:cb3d968589d8 134
Kojto 90:cb3d968589d8 135 DMA_InitTypeDef Init; /*!< DMA communication parameters */
Kojto 90:cb3d968589d8 136
Kojto 90:cb3d968589d8 137 HAL_LockTypeDef Lock; /*!< DMA locking object */
Kojto 90:cb3d968589d8 138
Kojto 90:cb3d968589d8 139 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
Kojto 90:cb3d968589d8 140
Kojto 90:cb3d968589d8 141 void *Parent; /*!< Parent object state */
Kojto 90:cb3d968589d8 142
Kojto 90:cb3d968589d8 143 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
Kojto 90:cb3d968589d8 144
Kojto 90:cb3d968589d8 145 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
Kojto 90:cb3d968589d8 146
Kojto 90:cb3d968589d8 147 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
Kojto 90:cb3d968589d8 148
Kojto 90:cb3d968589d8 149 __IO uint32_t ErrorCode; /*!< DMA Error code */
Kojto 90:cb3d968589d8 150
Kojto 90:cb3d968589d8 151 } DMA_HandleTypeDef;
Kojto 90:cb3d968589d8 152 /**
Kojto 90:cb3d968589d8 153 * @}
Kojto 90:cb3d968589d8 154 */
Kojto 90:cb3d968589d8 155
Kojto 90:cb3d968589d8 156 /* Exported constants --------------------------------------------------------*/
Kojto 90:cb3d968589d8 157 /** @defgroup DMA_Exported_Constants DMA Exported Constants
Kojto 90:cb3d968589d8 158 * @{
Kojto 90:cb3d968589d8 159 */
Kojto 90:cb3d968589d8 160
Kojto 90:cb3d968589d8 161 /** @defgroup DMA_Error_Code DMA Error Code
Kojto 90:cb3d968589d8 162 * @{
Kojto 90:cb3d968589d8 163 */
Kojto 90:cb3d968589d8 164 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
Kojto 90:cb3d968589d8 165 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
Kojto 90:cb3d968589d8 166 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
Kojto 90:cb3d968589d8 167 /**
Kojto 90:cb3d968589d8 168 * @}
Kojto 90:cb3d968589d8 169 */
Kojto 90:cb3d968589d8 170
Kojto 90:cb3d968589d8 171 /** @defgroup DMA_Data_transfer_direction DMA Data transfer direction
Kojto 90:cb3d968589d8 172 * @{
Kojto 90:cb3d968589d8 173 */
Kojto 90:cb3d968589d8 174 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
Kojto 90:cb3d968589d8 175 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
Kojto 90:cb3d968589d8 176 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
Kojto 90:cb3d968589d8 177
Kojto 90:cb3d968589d8 178 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
Kojto 90:cb3d968589d8 179 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
Kojto 90:cb3d968589d8 180 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
Kojto 90:cb3d968589d8 181 /**
Kojto 90:cb3d968589d8 182 * @}
Kojto 90:cb3d968589d8 183 */
Kojto 90:cb3d968589d8 184
Kojto 90:cb3d968589d8 185 /** @defgroup DMA_Data_buffer_size DMA Data buffer size
Kojto 90:cb3d968589d8 186 * @{
Kojto 90:cb3d968589d8 187 */
Kojto 90:cb3d968589d8 188 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
Kojto 90:cb3d968589d8 189 /**
Kojto 90:cb3d968589d8 190 * @}
Kojto 90:cb3d968589d8 191 */
Kojto 90:cb3d968589d8 192
Kojto 90:cb3d968589d8 193 /** @defgroup DMA_Peripheral_incremented_mode DMA Peripheral incremented mode
Kojto 90:cb3d968589d8 194 * @{
Kojto 90:cb3d968589d8 195 */
Kojto 90:cb3d968589d8 196 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
Kojto 90:cb3d968589d8 197 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
Kojto 90:cb3d968589d8 198
Kojto 90:cb3d968589d8 199 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
Kojto 90:cb3d968589d8 200 ((STATE) == DMA_PINC_DISABLE))
Kojto 90:cb3d968589d8 201 /**
Kojto 90:cb3d968589d8 202 * @}
Kojto 90:cb3d968589d8 203 */
Kojto 90:cb3d968589d8 204
Kojto 90:cb3d968589d8 205 /** @defgroup DMA_Memory_incremented_mode DMA Memory incremented mode
Kojto 90:cb3d968589d8 206 * @{
Kojto 90:cb3d968589d8 207 */
Kojto 90:cb3d968589d8 208 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
Kojto 90:cb3d968589d8 209 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
Kojto 90:cb3d968589d8 210
Kojto 90:cb3d968589d8 211 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
Kojto 90:cb3d968589d8 212 ((STATE) == DMA_MINC_DISABLE))
Kojto 90:cb3d968589d8 213 /**
Kojto 90:cb3d968589d8 214 * @}
Kojto 90:cb3d968589d8 215 */
Kojto 90:cb3d968589d8 216
Kojto 90:cb3d968589d8 217 /** @defgroup DMA_Peripheral_data_size DMA Peripheral data size
Kojto 90:cb3d968589d8 218 * @{
Kojto 90:cb3d968589d8 219 */
Kojto 90:cb3d968589d8 220 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
Kojto 90:cb3d968589d8 221 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
Kojto 90:cb3d968589d8 222 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
Kojto 90:cb3d968589d8 223
Kojto 90:cb3d968589d8 224 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
Kojto 90:cb3d968589d8 225 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
Kojto 90:cb3d968589d8 226 ((SIZE) == DMA_PDATAALIGN_WORD))
Kojto 90:cb3d968589d8 227 /**
Kojto 90:cb3d968589d8 228 * @}
Kojto 90:cb3d968589d8 229 */
Kojto 90:cb3d968589d8 230
Kojto 90:cb3d968589d8 231
Kojto 90:cb3d968589d8 232 /** @defgroup DMA_Memory_data_size DMA Memory data size
Kojto 90:cb3d968589d8 233 * @{
Kojto 90:cb3d968589d8 234 */
Kojto 90:cb3d968589d8 235 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
Kojto 90:cb3d968589d8 236 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
Kojto 90:cb3d968589d8 237 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
Kojto 90:cb3d968589d8 238
Kojto 90:cb3d968589d8 239 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
Kojto 90:cb3d968589d8 240 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
Kojto 90:cb3d968589d8 241 ((SIZE) == DMA_MDATAALIGN_WORD ))
Kojto 90:cb3d968589d8 242 /**
Kojto 90:cb3d968589d8 243 * @}
Kojto 90:cb3d968589d8 244 */
Kojto 90:cb3d968589d8 245
Kojto 90:cb3d968589d8 246 /** @defgroup DMA_mode DMA mode
Kojto 90:cb3d968589d8 247 * @{
Kojto 90:cb3d968589d8 248 */
Kojto 90:cb3d968589d8 249 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
Kojto 90:cb3d968589d8 250 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
Kojto 90:cb3d968589d8 251
Kojto 90:cb3d968589d8 252 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
Kojto 90:cb3d968589d8 253 ((MODE) == DMA_CIRCULAR))
Kojto 90:cb3d968589d8 254 /**
Kojto 90:cb3d968589d8 255 * @}
Kojto 90:cb3d968589d8 256 */
Kojto 90:cb3d968589d8 257
Kojto 90:cb3d968589d8 258 /** @defgroup DMA_Priority_level DMA Priority level
Kojto 90:cb3d968589d8 259 * @{
Kojto 90:cb3d968589d8 260 */
Kojto 90:cb3d968589d8 261 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
Kojto 90:cb3d968589d8 262 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
Kojto 90:cb3d968589d8 263 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
Kojto 90:cb3d968589d8 264 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
Kojto 90:cb3d968589d8 265
Kojto 90:cb3d968589d8 266 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
Kojto 90:cb3d968589d8 267 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
Kojto 90:cb3d968589d8 268 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
Kojto 90:cb3d968589d8 269 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
Kojto 90:cb3d968589d8 270 /**
Kojto 90:cb3d968589d8 271 * @}
Kojto 90:cb3d968589d8 272 */
Kojto 90:cb3d968589d8 273
Kojto 90:cb3d968589d8 274
Kojto 90:cb3d968589d8 275 /** @defgroup DMA_interrupt_enable_definitions DMA interrupt enable definitions
Kojto 90:cb3d968589d8 276 * @{
Kojto 90:cb3d968589d8 277 */
Kojto 90:cb3d968589d8 278
Kojto 90:cb3d968589d8 279 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
Kojto 90:cb3d968589d8 280 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
Kojto 90:cb3d968589d8 281 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
Kojto 90:cb3d968589d8 282
Kojto 90:cb3d968589d8 283 /**
Kojto 90:cb3d968589d8 284 * @}
Kojto 90:cb3d968589d8 285 */
Kojto 90:cb3d968589d8 286
Kojto 90:cb3d968589d8 287 /** @defgroup DMA_flag_definitions DMA flag definitions
Kojto 90:cb3d968589d8 288 * @{
Kojto 90:cb3d968589d8 289 */
Kojto 90:cb3d968589d8 290
Kojto 93:e188a91d3eaa 291 #define DMA_FLAG_GL1 ((uint32_t)0x00000001) /*!< Channel 1 global interrupt flag */
Kojto 93:e188a91d3eaa 292 #define DMA_FLAG_TC1 ((uint32_t)0x00000002) /*!< Channel 1 transfer complete flag */
Kojto 93:e188a91d3eaa 293 #define DMA_FLAG_HT1 ((uint32_t)0x00000004) /*!< Channel 1 half transfer flag */
Kojto 93:e188a91d3eaa 294 #define DMA_FLAG_TE1 ((uint32_t)0x00000008) /*!< Channel 1 transfer error flag */
Kojto 93:e188a91d3eaa 295 #define DMA_FLAG_GL2 ((uint32_t)0x00000010) /*!< Channel 2 global interrupt flag */
Kojto 93:e188a91d3eaa 296 #define DMA_FLAG_TC2 ((uint32_t)0x00000020) /*!< Channel 2 transfer complete flag */
Kojto 93:e188a91d3eaa 297 #define DMA_FLAG_HT2 ((uint32_t)0x00000040) /*!< Channel 2 half transfer flag */
Kojto 93:e188a91d3eaa 298 #define DMA_FLAG_TE2 ((uint32_t)0x00000080) /*!< Channel 2 transfer error flag */
Kojto 93:e188a91d3eaa 299 #define DMA_FLAG_GL3 ((uint32_t)0x00000100) /*!< Channel 3 global interrupt flag */
Kojto 93:e188a91d3eaa 300 #define DMA_FLAG_TC3 ((uint32_t)0x00000200) /*!< Channel 3 transfer complete flag */
Kojto 93:e188a91d3eaa 301 #define DMA_FLAG_HT3 ((uint32_t)0x00000400) /*!< Channel 3 half transfer flag */
Kojto 93:e188a91d3eaa 302 #define DMA_FLAG_TE3 ((uint32_t)0x00000800) /*!< Channel 3 transfer error flag */
Kojto 93:e188a91d3eaa 303 #define DMA_FLAG_GL4 ((uint32_t)0x00001000) /*!< Channel 4 global interrupt flag */
Kojto 93:e188a91d3eaa 304 #define DMA_FLAG_TC4 ((uint32_t)0x00002000) /*!< Channel 4 transfer complete flag */
Kojto 93:e188a91d3eaa 305 #define DMA_FLAG_HT4 ((uint32_t)0x00004000) /*!< Channel 4 half transfer flag */
Kojto 93:e188a91d3eaa 306 #define DMA_FLAG_TE4 ((uint32_t)0x00008000) /*!< Channel 4 transfer error flag */
Kojto 93:e188a91d3eaa 307 #define DMA_FLAG_GL5 ((uint32_t)0x00010000) /*!< Channel 5 global interrupt flag */
Kojto 93:e188a91d3eaa 308 #define DMA_FLAG_TC5 ((uint32_t)0x00020000) /*!< Channel 5 transfer complete flag */
Kojto 93:e188a91d3eaa 309 #define DMA_FLAG_HT5 ((uint32_t)0x00040000) /*!< Channel 5 half transfer flag */
Kojto 93:e188a91d3eaa 310 #define DMA_FLAG_TE5 ((uint32_t)0x00080000) /*!< Channel 5 transfer error flag */
Kojto 93:e188a91d3eaa 311 #define DMA_FLAG_GL6 ((uint32_t)0x00100000) /*!< Channel 6 global interrupt flag */
Kojto 93:e188a91d3eaa 312 #define DMA_FLAG_TC6 ((uint32_t)0x00200000) /*!< Channel 6 transfer complete flag */
Kojto 93:e188a91d3eaa 313 #define DMA_FLAG_HT6 ((uint32_t)0x00400000) /*!< Channel 6 half transfer flag */
Kojto 93:e188a91d3eaa 314 #define DMA_FLAG_TE6 ((uint32_t)0x00800000) /*!< Channel 6 transfer error flag */
Kojto 93:e188a91d3eaa 315 #define DMA_FLAG_GL7 ((uint32_t)0x01000000) /*!< Channel 7 global interrupt flag */
Kojto 93:e188a91d3eaa 316 #define DMA_FLAG_TC7 ((uint32_t)0x02000000) /*!< Channel 7 transfer complete flag */
Kojto 93:e188a91d3eaa 317 #define DMA_FLAG_HT7 ((uint32_t)0x04000000) /*!< Channel 7 half transfer flag */
Kojto 93:e188a91d3eaa 318 #define DMA_FLAG_TE7 ((uint32_t)0x08000000) /*!< Channel 7 transfer error flag */
Kojto 90:cb3d968589d8 319
Kojto 90:cb3d968589d8 320
Kojto 90:cb3d968589d8 321 /**
Kojto 90:cb3d968589d8 322 * @}
Kojto 90:cb3d968589d8 323 */
Kojto 90:cb3d968589d8 324
Kojto 90:cb3d968589d8 325 /**
Kojto 90:cb3d968589d8 326 * @}
Kojto 90:cb3d968589d8 327 */
Kojto 90:cb3d968589d8 328
Kojto 90:cb3d968589d8 329 /* Exported macros -----------------------------------------------------------*/
Kojto 90:cb3d968589d8 330 /** @defgroup DMA_Exported_Macros DMA Exported Macros
Kojto 90:cb3d968589d8 331 * @{
Kojto 90:cb3d968589d8 332 */
Kojto 90:cb3d968589d8 333
Kojto 90:cb3d968589d8 334 /** @brief Reset DMA handle state
Kojto 90:cb3d968589d8 335 * @param __HANDLE__: DMA handle.
Kojto 90:cb3d968589d8 336 * @retval None
Kojto 90:cb3d968589d8 337 */
Kojto 90:cb3d968589d8 338 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
Kojto 90:cb3d968589d8 339
Kojto 90:cb3d968589d8 340 /**
Kojto 90:cb3d968589d8 341 * @brief Enable the specified DMA Channel.
Kojto 90:cb3d968589d8 342 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 343 * @retval None.
Kojto 90:cb3d968589d8 344 */
Kojto 90:cb3d968589d8 345 #define __HAL_DMA_ENABLE(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Kojto 90:cb3d968589d8 346
Kojto 90:cb3d968589d8 347 /**
Kojto 90:cb3d968589d8 348 * @brief Disable the specified DMA Channel.
Kojto 90:cb3d968589d8 349 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 350 * @retval None.
Kojto 90:cb3d968589d8 351 */
Kojto 90:cb3d968589d8 352 #define __HAL_DMA_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CCR, DMA_CCR_EN))
Kojto 90:cb3d968589d8 353
Kojto 90:cb3d968589d8 354
Kojto 90:cb3d968589d8 355 /* Interrupt & Flag management */
Kojto 90:cb3d968589d8 356
Kojto 90:cb3d968589d8 357 /**
Kojto 90:cb3d968589d8 358 * @brief Enables the specified DMA Channel interrupts.
Kojto 90:cb3d968589d8 359 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 360 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 90:cb3d968589d8 361 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 362 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 90:cb3d968589d8 363 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 90:cb3d968589d8 364 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 90:cb3d968589d8 365 * @retval None
Kojto 90:cb3d968589d8 366 */
Kojto 90:cb3d968589d8 367 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) (SET_BIT((__HANDLE__)->Instance->CCR, (__INTERRUPT__)))
Kojto 90:cb3d968589d8 368
Kojto 90:cb3d968589d8 369 /**
Kojto 90:cb3d968589d8 370 * @brief Disables the specified DMA Channel interrupts.
Kojto 90:cb3d968589d8 371 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 372 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
Kojto 90:cb3d968589d8 373 * This parameter can be any combination of the following values:
Kojto 90:cb3d968589d8 374 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 90:cb3d968589d8 375 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 90:cb3d968589d8 376 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 90:cb3d968589d8 377 * @retval None
Kojto 90:cb3d968589d8 378 */
Kojto 90:cb3d968589d8 379 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) (CLEAR_BIT((__HANDLE__)->Instance->CCR , (__INTERRUPT__)))
Kojto 90:cb3d968589d8 380
Kojto 90:cb3d968589d8 381 /**
Kojto 90:cb3d968589d8 382 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
Kojto 90:cb3d968589d8 383 * @param __HANDLE__: DMA handle
Kojto 90:cb3d968589d8 384 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
Kojto 90:cb3d968589d8 385 * This parameter can be one of the following values:
Kojto 90:cb3d968589d8 386 * @arg DMA_IT_TC: Transfer complete interrupt mask
Kojto 90:cb3d968589d8 387 * @arg DMA_IT_HT: Half transfer complete interrupt mask
Kojto 90:cb3d968589d8 388 * @arg DMA_IT_TE: Transfer error interrupt mask
Kojto 90:cb3d968589d8 389 * @retval The state of DMA_IT (SET or RESET).
Kojto 90:cb3d968589d8 390 */
Kojto 90:cb3d968589d8 391 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
Kojto 90:cb3d968589d8 392
Kojto 90:cb3d968589d8 393 /**
Kojto 90:cb3d968589d8 394 * @}
Kojto 90:cb3d968589d8 395 */
Kojto 90:cb3d968589d8 396
Kojto 90:cb3d968589d8 397 /* Include DMA HAL Extension module */
Kojto 90:cb3d968589d8 398 #include "stm32f0xx_hal_dma_ex.h"
Kojto 90:cb3d968589d8 399
Kojto 90:cb3d968589d8 400 /* Exported functions --------------------------------------------------------*/
Kojto 90:cb3d968589d8 401 /** @addtogroup DMA_Exported_Functions DMA Exported Functions
Kojto 90:cb3d968589d8 402 * @{
Kojto 90:cb3d968589d8 403 */
Kojto 90:cb3d968589d8 404 /** @addtogroup DMA_Exported_Functions_Group1
Kojto 90:cb3d968589d8 405 * @brief Initialization and de-initialization functions
Kojto 90:cb3d968589d8 406 * @{
Kojto 90:cb3d968589d8 407 */
Kojto 90:cb3d968589d8 408 /* Initialization and de-initialization functions *****************************/
Kojto 90:cb3d968589d8 409 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
Kojto 90:cb3d968589d8 410 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
Kojto 90:cb3d968589d8 411 /**
Kojto 90:cb3d968589d8 412 * @}
Kojto 90:cb3d968589d8 413 */
Kojto 90:cb3d968589d8 414
Kojto 90:cb3d968589d8 415 /** @addtogroup DMA_Exported_Functions_Group2
Kojto 90:cb3d968589d8 416 * @brief I/O operation functions
Kojto 90:cb3d968589d8 417 * @{
Kojto 90:cb3d968589d8 418 */
Kojto 90:cb3d968589d8 419 /* IO operation functions *****************************************************/
Kojto 90:cb3d968589d8 420 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 90:cb3d968589d8 421 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
Kojto 90:cb3d968589d8 422 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
Kojto 90:cb3d968589d8 423 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
Kojto 90:cb3d968589d8 424 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
Kojto 90:cb3d968589d8 425 /**
Kojto 90:cb3d968589d8 426 * @}
Kojto 90:cb3d968589d8 427 */
Kojto 90:cb3d968589d8 428
Kojto 90:cb3d968589d8 429 /* Peripheral State and Error functions ***************************************/
Kojto 90:cb3d968589d8 430 /** @addtogroup DMA_Exported_Functions_Group3
Kojto 90:cb3d968589d8 431 * @brief Peripheral State functions
Kojto 90:cb3d968589d8 432 * @{
Kojto 90:cb3d968589d8 433 */
Kojto 90:cb3d968589d8 434 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
Kojto 90:cb3d968589d8 435 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
Kojto 90:cb3d968589d8 436 /**
Kojto 90:cb3d968589d8 437 * @}
Kojto 90:cb3d968589d8 438 */
Kojto 90:cb3d968589d8 439
Kojto 90:cb3d968589d8 440 /**
Kojto 90:cb3d968589d8 441 * @}
Kojto 90:cb3d968589d8 442 */
Kojto 90:cb3d968589d8 443
Kojto 90:cb3d968589d8 444 /**
Kojto 90:cb3d968589d8 445 * @}
Kojto 90:cb3d968589d8 446 */
Kojto 90:cb3d968589d8 447
Kojto 90:cb3d968589d8 448 /**
Kojto 90:cb3d968589d8 449 * @}
Kojto 90:cb3d968589d8 450 */
Kojto 90:cb3d968589d8 451
Kojto 90:cb3d968589d8 452 #ifdef __cplusplus
Kojto 90:cb3d968589d8 453 }
Kojto 90:cb3d968589d8 454 #endif
Kojto 90:cb3d968589d8 455
Kojto 90:cb3d968589d8 456 #endif /* __STM32F0xx_HAL_DMA_H */
Kojto 90:cb3d968589d8 457
Kojto 90:cb3d968589d8 458 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
Kojto 90:cb3d968589d8 459