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TARGET_NUCLEO_F030R8/stm32f0xx_hal_rcc.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:: filartrix
Date:: Wed Apr 08 14:12:53 2015 +0000
Revision:: 97:4298809c7c9e
Parent:: 93:e188a91d3eaa

First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	90:cb3d968589d8	1	/**
Kojto	90:cb3d968589d8	2	******************************************************************************
Kojto	90:cb3d968589d8	3	* @file stm32f0xx_hal_rcc.h
Kojto	90:cb3d968589d8	4	* @author MCD Application Team
Kojto	93:e188a91d3eaa	5	* @version V1.2.0
Kojto	93:e188a91d3eaa	6	* @date 11-December-2014
Kojto	90:cb3d968589d8	7	* @brief Header file of RCC HAL module.
Kojto	90:cb3d968589d8	8	******************************************************************************
Kojto	90:cb3d968589d8	9	* @attention
Kojto	90:cb3d968589d8	10	*
Kojto	90:cb3d968589d8	11	* <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Kojto	90:cb3d968589d8	12	*
Kojto	90:cb3d968589d8	13	* Redistribution and use in source and binary forms, with or without modification,
Kojto	90:cb3d968589d8	14	* are permitted provided that the following conditions are met:
Kojto	90:cb3d968589d8	15	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	90:cb3d968589d8	16	* this list of conditions and the following disclaimer.
Kojto	90:cb3d968589d8	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	90:cb3d968589d8	18	* this list of conditions and the following disclaimer in the documentation
Kojto	90:cb3d968589d8	19	* and/or other materials provided with the distribution.
Kojto	90:cb3d968589d8	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	90:cb3d968589d8	21	* may be used to endorse or promote products derived from this software
Kojto	90:cb3d968589d8	22	* without specific prior written permission.
Kojto	90:cb3d968589d8	23	*
Kojto	90:cb3d968589d8	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	90:cb3d968589d8	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	90:cb3d968589d8	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	90:cb3d968589d8	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	90:cb3d968589d8	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	90:cb3d968589d8	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	90:cb3d968589d8	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	90:cb3d968589d8	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	90:cb3d968589d8	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	90:cb3d968589d8	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	90:cb3d968589d8	34	*
Kojto	90:cb3d968589d8	35	******************************************************************************
Kojto	90:cb3d968589d8	36	*/
Kojto	90:cb3d968589d8	37
Kojto	90:cb3d968589d8	38	/* Define to prevent recursive inclusion -------------------------------------*/
Kojto	90:cb3d968589d8	39	#ifndef __STM32F0xx_HAL_RCC_H
Kojto	90:cb3d968589d8	40	#define __STM32F0xx_HAL_RCC_H
Kojto	90:cb3d968589d8	41
Kojto	90:cb3d968589d8	42	#ifdef __cplusplus
Kojto	90:cb3d968589d8	43	extern "C" {
Kojto	90:cb3d968589d8	44	#endif
Kojto	90:cb3d968589d8	45
Kojto	90:cb3d968589d8	46	/* Includes ------------------------------------------------------------------*/
Kojto	90:cb3d968589d8	47	#include "stm32f0xx_hal_def.h"
Kojto	90:cb3d968589d8	48
Kojto	90:cb3d968589d8	49	/** @addtogroup STM32F0xx_HAL_Driver
Kojto	90:cb3d968589d8	50	* @{
Kojto	90:cb3d968589d8	51	*/
Kojto	90:cb3d968589d8	52
Kojto	90:cb3d968589d8	53	/** @addtogroup RCC
Kojto	90:cb3d968589d8	54	* @{
Kojto	90:cb3d968589d8	55	*/
Kojto	90:cb3d968589d8	56
Kojto	90:cb3d968589d8	57	/* Exported types ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	58
Kojto	90:cb3d968589d8	59	/** @defgroup RCC_Exported_Types RCC Exported Types
Kojto	90:cb3d968589d8	60	* @{
Kojto	90:cb3d968589d8	61	*/
Kojto	90:cb3d968589d8	62
Kojto	90:cb3d968589d8	63	/**
Kojto	90:cb3d968589d8	64	* @brief RCC PLL configuration structure definition
Kojto	90:cb3d968589d8	65	*/
Kojto	90:cb3d968589d8	66	typedef struct
Kojto	90:cb3d968589d8	67	{
Kojto	90:cb3d968589d8	68	uint32_t PLLState; /*!< PLLState: The new state of the PLL.
Kojto	90:cb3d968589d8	69	This parameter can be a value of @ref RCC_PLL_Config */
Kojto	90:cb3d968589d8	70
Kojto	90:cb3d968589d8	71	uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
Kojto	90:cb3d968589d8	72	This parameter must be a value of @ref RCC_PLL_Clock_Source */
Kojto	90:cb3d968589d8	73
Kojto	90:cb3d968589d8	74	uint32_t PREDIV; /*!< PREDIV: Predivision factor for PLL VCO input clock
Kojto	90:cb3d968589d8	75	This parameter must be a value of @ref RCC_PLL_Prediv_Factor */
Kojto	90:cb3d968589d8	76
Kojto	90:cb3d968589d8	77	uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
Kojto	90:cb3d968589d8	78	This parameter must be a value of @ref RCC_PLL_Multiplication_Factor */
Kojto	90:cb3d968589d8	79
Kojto	90:cb3d968589d8	80	}RCC_PLLInitTypeDef;
Kojto	90:cb3d968589d8	81
Kojto	90:cb3d968589d8	82	/**
Kojto	90:cb3d968589d8	83	* @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
Kojto	90:cb3d968589d8	84	*/
Kojto	90:cb3d968589d8	85	typedef struct
Kojto	90:cb3d968589d8	86	{
Kojto	90:cb3d968589d8	87	uint32_t OscillatorType; /*!< The Oscillators to be configured.
Kojto	90:cb3d968589d8	88	This parameter can be a value of @ref RCC_Oscillator_Type */
Kojto	90:cb3d968589d8	89
Kojto	90:cb3d968589d8	90	uint32_t HSEState; /*!< The new state of the HSE.
Kojto	90:cb3d968589d8	91	This parameter can be a value of @ref RCC_HSE_Config */
Kojto	90:cb3d968589d8	92
Kojto	90:cb3d968589d8	93	uint32_t LSEState; /*!< The new state of the LSE.
Kojto	90:cb3d968589d8	94	This parameter can be a value of @ref RCC_LSE_Config */
Kojto	90:cb3d968589d8	95
Kojto	90:cb3d968589d8	96	uint32_t HSIState; /*!< The new state of the HSI.
Kojto	90:cb3d968589d8	97	This parameter can be a value of @ref RCC_HSI_Config */
Kojto	90:cb3d968589d8	98
Kojto	90:cb3d968589d8	99	uint32_t HSICalibrationValue; /*!< The HSI calibration trimming value (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	90:cb3d968589d8	100	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	90:cb3d968589d8	101
Kojto	90:cb3d968589d8	102	uint32_t HSI14State; /*!< The new state of the HSI14.
Kojto	90:cb3d968589d8	103	This parameter can be a value of @ref RCC_HSI14_Config */
Kojto	90:cb3d968589d8	104
Kojto	90:cb3d968589d8	105	uint32_t HSI14CalibrationValue; /*!< The HSI14 calibration trimming value (default is RCC_HSI14CALIBRATION_DEFAULT).
Kojto	90:cb3d968589d8	106	This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F */
Kojto	90:cb3d968589d8	107
Kojto	93:e188a91d3eaa	108	uint32_t HSI48State; /*!< The new state of the HSI48 (only applicable to STM32F07x, STM32F0x2 and STM32F09x devices).
Kojto	90:cb3d968589d8	109	This parameter can be a value of @ref RCCEx_HSI48_Config */
Kojto	90:cb3d968589d8	110
Kojto	90:cb3d968589d8	111	uint32_t LSIState; /*!< The new state of the LSI.
Kojto	90:cb3d968589d8	112	This parameter can be a value of @ref RCC_LSI_Config */
Kojto	90:cb3d968589d8	113
Kojto	90:cb3d968589d8	114	RCC_PLLInitTypeDef PLL; /!< PLL structure parameters /
Kojto	90:cb3d968589d8	115
Kojto	90:cb3d968589d8	116	}RCC_OscInitTypeDef;
Kojto	90:cb3d968589d8	117
Kojto	90:cb3d968589d8	118	/**
Kojto	90:cb3d968589d8	119	* @brief RCC System, AHB and APB busses clock configuration structure definition
Kojto	90:cb3d968589d8	120	*/
Kojto	90:cb3d968589d8	121	typedef struct
Kojto	90:cb3d968589d8	122	{
Kojto	90:cb3d968589d8	123	uint32_t ClockType; /*!< The clock to be configured.
Kojto	90:cb3d968589d8	124	This parameter can be a value of @ref RCC_System_Clock_Type */
Kojto	90:cb3d968589d8	125
Kojto	90:cb3d968589d8	126	uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
Kojto	90:cb3d968589d8	127	This parameter can be a value of @ref RCC_System_Clock_Source */
Kojto	90:cb3d968589d8	128
Kojto	90:cb3d968589d8	129	uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
Kojto	90:cb3d968589d8	130	This parameter can be a value of @ref RCC_AHB_Clock_Source */
Kojto	90:cb3d968589d8	131
Kojto	90:cb3d968589d8	132	uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
Kojto	90:cb3d968589d8	133	This parameter can be a value of @ref RCC_APB1_Clock_Source */
Kojto	90:cb3d968589d8	134
Kojto	90:cb3d968589d8	135	}RCC_ClkInitTypeDef;
Kojto	90:cb3d968589d8	136
Kojto	90:cb3d968589d8	137	/**
Kojto	90:cb3d968589d8	138	* @}
Kojto	90:cb3d968589d8	139	*/
Kojto	90:cb3d968589d8	140
Kojto	90:cb3d968589d8	141	/* Exported constants --------------------------------------------------------*/
Kojto	90:cb3d968589d8	142	/** @defgroup RCC_Exported_Constants RCC Exported Constants
Kojto	90:cb3d968589d8	143	* @{
Kojto	90:cb3d968589d8	144	*/
Kojto	90:cb3d968589d8	145
Kojto	90:cb3d968589d8	146	/** @defgroup RCC_BitAddress_AliasRegion RCC BitAddress AliasRegion
Kojto	90:cb3d968589d8	147	* @brief RCC registers bit address in the alias region
Kojto	90:cb3d968589d8	148	* @{
Kojto	90:cb3d968589d8	149	*/
Kojto	90:cb3d968589d8	150	#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
Kojto	90:cb3d968589d8	151	/* --- CR Register ---*/
Kojto	90:cb3d968589d8	152	#define RCC_CR_OFFSET (RCC_OFFSET + 0x00)
Kojto	90:cb3d968589d8	153	/* --- CFGR Register ---*/
Kojto	90:cb3d968589d8	154	#define RCC_CFGR_OFFSET (RCC_OFFSET + 0x04)
Kojto	90:cb3d968589d8	155	/* --- CIR Register ---*/
Kojto	90:cb3d968589d8	156	#define RCC_CIR_OFFSET (RCC_OFFSET + 0x08)
Kojto	90:cb3d968589d8	157	/* --- BDCR Register ---*/
Kojto	90:cb3d968589d8	158	#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x20)
Kojto	90:cb3d968589d8	159	/* --- CSR Register ---*/
Kojto	90:cb3d968589d8	160	#define RCC_CSR_OFFSET (RCC_OFFSET + 0x24)
Kojto	90:cb3d968589d8	161	/* --- CR2 Register ---*/
Kojto	90:cb3d968589d8	162	#define RCC_CR2_OFFSET (RCC_OFFSET + 0x34)
Kojto	90:cb3d968589d8	163
Kojto	90:cb3d968589d8	164	/* CR register byte 2 (Bits[23:16]) base address */
Kojto	90:cb3d968589d8	165	#define RCC_CR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CR_OFFSET + 0x02)
Kojto	90:cb3d968589d8	166
Kojto	90:cb3d968589d8	167	/* CIR register byte 1 (Bits[15:8]) base address */
Kojto	90:cb3d968589d8	168	#define RCC_CIR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x01)
Kojto	90:cb3d968589d8	169
Kojto	90:cb3d968589d8	170	/* CIR register byte 2 (Bits[23:16]) base address */
Kojto	90:cb3d968589d8	171	#define RCC_CIR_BYTE2_ADDRESS (PERIPH_BASE + RCC_CIR_OFFSET + 0x02)
Kojto	90:cb3d968589d8	172
Kojto	90:cb3d968589d8	173	/* CSR register byte 1 (Bits[15:8]) base address */
Kojto	90:cb3d968589d8	174	#define RCC_CSR_BYTE1_ADDRESS (PERIPH_BASE + RCC_CSR_OFFSET + 0x01)
Kojto	90:cb3d968589d8	175
Kojto	90:cb3d968589d8	176	/* BDCR register byte 0 (Bits[7:0] base address */
Kojto	90:cb3d968589d8	177	#define RCC_BDCR_BYTE0_ADDRESS (PERIPH_BASE + RCC_BDCR_OFFSET)
Kojto	90:cb3d968589d8	178
Kojto	90:cb3d968589d8	179	#define RCC_CFGR_PLLMUL_BITNUMBER 18
Kojto	90:cb3d968589d8	180	#define RCC_CFGR2_PREDIV_BITNUMBER 0
Kojto	90:cb3d968589d8	181
Kojto	90:cb3d968589d8	182	/**
Kojto	90:cb3d968589d8	183	* @}
Kojto	90:cb3d968589d8	184	*/
Kojto	90:cb3d968589d8	185
Kojto	90:cb3d968589d8	186	/** @defgroup RCC_Timeout RCC Timeout
Kojto	90:cb3d968589d8	187	* @{
Kojto	90:cb3d968589d8	188	*/
Kojto	90:cb3d968589d8	189	/* LSE state change timeout */
Kojto	90:cb3d968589d8	190	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto	90:cb3d968589d8	191
Kojto	90:cb3d968589d8	192	/* Disable Backup domain write protection state change timeout */
Kojto	90:cb3d968589d8	193	#define DBP_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	90:cb3d968589d8	194	/**
Kojto	90:cb3d968589d8	195	* @}
Kojto	90:cb3d968589d8	196	*/
Kojto	90:cb3d968589d8	197
Kojto	90:cb3d968589d8	198	/** @defgroup RCC_Oscillator_Type RCC Oscillator Type
Kojto	90:cb3d968589d8	199	* @{
Kojto	90:cb3d968589d8	200	*/
Kojto	90:cb3d968589d8	201	#define RCC_OSCILLATORTYPE_NONE ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	202	#define RCC_OSCILLATORTYPE_HSE ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	203	#define RCC_OSCILLATORTYPE_HSI ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	204	#define RCC_OSCILLATORTYPE_LSE ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	205	#define RCC_OSCILLATORTYPE_LSI ((uint32_t)0x00000008)
Kojto	90:cb3d968589d8	206	#define RCC_OSCILLATORTYPE_HSI14 ((uint32_t)0x00000010)
Kojto	90:cb3d968589d8	207	#define RCC_OSCILLATORTYPE_HSI48 ((uint32_t)0x00000020)
Kojto	90:cb3d968589d8	208
Kojto	90:cb3d968589d8	209	#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) (((OSCILLATOR) == RCC_OSCILLATORTYPE_NONE) \|\| \
Kojto	90:cb3d968589d8	210	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) \|\| \
Kojto	90:cb3d968589d8	211	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) \|\| \
Kojto	90:cb3d968589d8	212	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) \|\| \
Kojto	90:cb3d968589d8	213	(((OSCILLATOR) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE) \|\| \
Kojto	90:cb3d968589d8	214	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI14) == RCC_OSCILLATORTYPE_HSI14) \|\| \
Kojto	90:cb3d968589d8	215	(((OSCILLATOR) & RCC_OSCILLATORTYPE_HSI48) == RCC_OSCILLATORTYPE_HSI48))
Kojto	90:cb3d968589d8	216	/**
Kojto	90:cb3d968589d8	217	* @}
Kojto	90:cb3d968589d8	218	*/
Kojto	90:cb3d968589d8	219
Kojto	90:cb3d968589d8	220	/** @defgroup RCC_HSE_Config RCC HSE Config
Kojto	90:cb3d968589d8	221	* @{
Kojto	90:cb3d968589d8	222	*/
Kojto	90:cb3d968589d8	223	#define RCC_HSE_OFF ((uint8_t)0x00)
Kojto	90:cb3d968589d8	224	#define RCC_HSE_ON ((uint8_t)0x01)
Kojto	90:cb3d968589d8	225	#define RCC_HSE_BYPASS ((uint8_t)0x05)
Kojto	90:cb3d968589d8	226
Kojto	90:cb3d968589d8	227	#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) \|\| ((HSE) == RCC_HSE_ON) \|\| \
Kojto	90:cb3d968589d8	228	((HSE) == RCC_HSE_BYPASS))
Kojto	90:cb3d968589d8	229	/**
Kojto	90:cb3d968589d8	230	* @}
Kojto	90:cb3d968589d8	231	*/
Kojto	90:cb3d968589d8	232
Kojto	90:cb3d968589d8	233	/** @defgroup RCC_LSE_Config RCC_LSE_Config
Kojto	90:cb3d968589d8	234	* @{
Kojto	90:cb3d968589d8	235	*/
Kojto	90:cb3d968589d8	236	#define RCC_LSE_OFF ((uint8_t)0x00)
Kojto	90:cb3d968589d8	237	#define RCC_LSE_ON ((uint8_t)0x01)
Kojto	90:cb3d968589d8	238	#define RCC_LSE_BYPASS ((uint8_t)0x05)
Kojto	90:cb3d968589d8	239
Kojto	90:cb3d968589d8	240	#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) \|\| ((LSE) == RCC_LSE_ON) \|\| \
Kojto	90:cb3d968589d8	241	((LSE) == RCC_LSE_BYPASS))
Kojto	90:cb3d968589d8	242	/**
Kojto	90:cb3d968589d8	243	* @}
Kojto	90:cb3d968589d8	244	*/
Kojto	90:cb3d968589d8	245
Kojto	90:cb3d968589d8	246	/** @defgroup RCC_HSI_Config RCC HSI Config
Kojto	90:cb3d968589d8	247	* @{
Kojto	90:cb3d968589d8	248	*/
Kojto	90:cb3d968589d8	249	#define RCC_HSI_OFF ((uint8_t)0x00)
Kojto	90:cb3d968589d8	250	#define RCC_HSI_ON ((uint8_t)0x01)
Kojto	90:cb3d968589d8	251
Kojto	90:cb3d968589d8	252	#define IS_RCC_HSI(HSI) (((HSI) == RCC_HSI_OFF) \|\| ((HSI) == RCC_HSI_ON))
Kojto	90:cb3d968589d8	253
Kojto	90:cb3d968589d8	254	#define RCC_HSICALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI calibration trimming value */
Kojto	90:cb3d968589d8	255	/**
Kojto	90:cb3d968589d8	256	* @}
Kojto	90:cb3d968589d8	257	*/
Kojto	90:cb3d968589d8	258
Kojto	90:cb3d968589d8	259	/** @defgroup RCC_HSI14_Config RCC HSI14 Config
Kojto	90:cb3d968589d8	260	* @{
Kojto	90:cb3d968589d8	261	*/
Kojto	90:cb3d968589d8	262	#define RCC_HSI14_OFF ((uint32_t)0x00)
Kojto	90:cb3d968589d8	263	#define RCC_HSI14_ON RCC_CR2_HSI14ON
Kojto	90:cb3d968589d8	264	#define RCC_HSI14_ADC_CONTROL (~RCC_CR2_HSI14DIS)
Kojto	90:cb3d968589d8	265
Kojto	90:cb3d968589d8	266	#define IS_RCC_HSI14(HSI14) (((HSI14) == RCC_HSI14_OFF) \|\| ((HSI14) == RCC_HSI14_ON) \|\| ((HSI14) == RCC_HSI14_ADC_CONTROL))
Kojto	90:cb3d968589d8	267
Kojto	90:cb3d968589d8	268	#define RCC_HSI14CALIBRATION_DEFAULT ((uint32_t)0x10) /* Default HSI14 calibration trimming value */
Kojto	90:cb3d968589d8	269	/**
Kojto	90:cb3d968589d8	270	* @}
Kojto	90:cb3d968589d8	271	*/
Kojto	90:cb3d968589d8	272
Kojto	90:cb3d968589d8	273	/** @defgroup RCC_LSI_Config RCC LSI Config
Kojto	90:cb3d968589d8	274	* @{
Kojto	90:cb3d968589d8	275	*/
Kojto	90:cb3d968589d8	276	#define RCC_LSI_OFF ((uint8_t)0x00)
Kojto	90:cb3d968589d8	277	#define RCC_LSI_ON ((uint8_t)0x01)
Kojto	90:cb3d968589d8	278
Kojto	90:cb3d968589d8	279	#define IS_RCC_LSI(LSI) (((LSI) == RCC_LSI_OFF) \|\| ((LSI) == RCC_LSI_ON))
Kojto	90:cb3d968589d8	280	/**
Kojto	90:cb3d968589d8	281	* @}
Kojto	90:cb3d968589d8	282	*/
Kojto	90:cb3d968589d8	283
Kojto	90:cb3d968589d8	284	/** @defgroup RCC_PLL_Config RCC PLL Config
Kojto	90:cb3d968589d8	285	* @{
Kojto	90:cb3d968589d8	286	*/
Kojto	90:cb3d968589d8	287	#define RCC_PLL_NONE ((uint8_t)0x00)
Kojto	90:cb3d968589d8	288	#define RCC_PLL_OFF ((uint8_t)0x01)
Kojto	90:cb3d968589d8	289	#define RCC_PLL_ON ((uint8_t)0x02)
Kojto	90:cb3d968589d8	290
Kojto	90:cb3d968589d8	291	#define IS_RCC_PLL(PLL) (((PLL) == RCC_PLL_NONE) \|\|((PLL) == RCC_PLL_OFF) \|\| ((PLL) == RCC_PLL_ON))
Kojto	90:cb3d968589d8	292	/**
Kojto	90:cb3d968589d8	293	* @}
Kojto	90:cb3d968589d8	294	*/
Kojto	90:cb3d968589d8	295
Kojto	90:cb3d968589d8	296	/** @defgroup RCC_PLL_Prediv_Factor RCC PLL Prediv Factor
Kojto	90:cb3d968589d8	297	* @{
Kojto	90:cb3d968589d8	298	*/
Kojto	90:cb3d968589d8	299	#define RCC_PREDIV_DIV1 RCC_CFGR2_PREDIV_DIV1
Kojto	90:cb3d968589d8	300	#define RCC_PREDIV_DIV2 RCC_CFGR2_PREDIV_DIV2
Kojto	90:cb3d968589d8	301	#define RCC_PREDIV_DIV3 RCC_CFGR2_PREDIV_DIV3
Kojto	90:cb3d968589d8	302	#define RCC_PREDIV_DIV4 RCC_CFGR2_PREDIV_DIV4
Kojto	90:cb3d968589d8	303	#define RCC_PREDIV_DIV5 RCC_CFGR2_PREDIV_DIV5
Kojto	90:cb3d968589d8	304	#define RCC_PREDIV_DIV6 RCC_CFGR2_PREDIV_DIV6
Kojto	90:cb3d968589d8	305	#define RCC_PREDIV_DIV7 RCC_CFGR2_PREDIV_DIV7
Kojto	90:cb3d968589d8	306	#define RCC_PREDIV_DIV8 RCC_CFGR2_PREDIV_DIV8
Kojto	90:cb3d968589d8	307	#define RCC_PREDIV_DIV9 RCC_CFGR2_PREDIV_DIV9
Kojto	90:cb3d968589d8	308	#define RCC_PREDIV_DIV10 RCC_CFGR2_PREDIV_DIV10
Kojto	90:cb3d968589d8	309	#define RCC_PREDIV_DIV11 RCC_CFGR2_PREDIV_DIV11
Kojto	90:cb3d968589d8	310	#define RCC_PREDIV_DIV12 RCC_CFGR2_PREDIV_DIV12
Kojto	90:cb3d968589d8	311	#define RCC_PREDIV_DIV13 RCC_CFGR2_PREDIV_DIV13
Kojto	90:cb3d968589d8	312	#define RCC_PREDIV_DIV14 RCC_CFGR2_PREDIV_DIV14
Kojto	90:cb3d968589d8	313	#define RCC_PREDIV_DIV15 RCC_CFGR2_PREDIV_DIV15
Kojto	90:cb3d968589d8	314	#define RCC_PREDIV_DIV16 RCC_CFGR2_PREDIV_DIV16
Kojto	90:cb3d968589d8	315
Kojto	90:cb3d968589d8	316	#define IS_RCC_PREDIV(PREDIV) (((PREDIV) == RCC_PREDIV_DIV1) \|\| ((PREDIV) == RCC_PREDIV_DIV2) \|\| \
Kojto	90:cb3d968589d8	317	((PREDIV) == RCC_PREDIV_DIV3) \|\| ((PREDIV) == RCC_PREDIV_DIV4) \|\| \
Kojto	90:cb3d968589d8	318	((PREDIV) == RCC_PREDIV_DIV5) \|\| ((PREDIV) == RCC_PREDIV_DIV6) \|\| \
Kojto	90:cb3d968589d8	319	((PREDIV) == RCC_PREDIV_DIV7) \|\| ((PREDIV) == RCC_PREDIV_DIV8) \|\| \
Kojto	90:cb3d968589d8	320	((PREDIV) == RCC_PREDIV_DIV9) \|\| ((PREDIV) == RCC_PREDIV_DIV10) \|\| \
Kojto	90:cb3d968589d8	321	((PREDIV) == RCC_PREDIV_DIV11) \|\| ((PREDIV) == RCC_PREDIV_DIV12) \|\| \
Kojto	90:cb3d968589d8	322	((PREDIV) == RCC_PREDIV_DIV13) \|\| ((PREDIV) == RCC_PREDIV_DIV14) \|\| \
Kojto	90:cb3d968589d8	323	((PREDIV) == RCC_PREDIV_DIV15) \|\| ((PREDIV) == RCC_PREDIV_DIV16))
Kojto	90:cb3d968589d8	324	/**
Kojto	90:cb3d968589d8	325	* @}
Kojto	90:cb3d968589d8	326	*/
Kojto	90:cb3d968589d8	327
Kojto	90:cb3d968589d8	328	/** @defgroup RCC_PLL_Multiplication_Factor RCC PLL Multiplication Factor
Kojto	90:cb3d968589d8	329	* @{
Kojto	90:cb3d968589d8	330	*/
Kojto	90:cb3d968589d8	331	#define RCC_PLL_MUL2 RCC_CFGR_PLLMUL2
Kojto	90:cb3d968589d8	332	#define RCC_PLL_MUL3 RCC_CFGR_PLLMUL3
Kojto	90:cb3d968589d8	333	#define RCC_PLL_MUL4 RCC_CFGR_PLLMUL4
Kojto	90:cb3d968589d8	334	#define RCC_PLL_MUL5 RCC_CFGR_PLLMUL5
Kojto	90:cb3d968589d8	335	#define RCC_PLL_MUL6 RCC_CFGR_PLLMUL6
Kojto	90:cb3d968589d8	336	#define RCC_PLL_MUL7 RCC_CFGR_PLLMUL7
Kojto	90:cb3d968589d8	337	#define RCC_PLL_MUL8 RCC_CFGR_PLLMUL8
Kojto	90:cb3d968589d8	338	#define RCC_PLL_MUL9 RCC_CFGR_PLLMUL9
Kojto	90:cb3d968589d8	339	#define RCC_PLL_MUL10 RCC_CFGR_PLLMUL10
Kojto	90:cb3d968589d8	340	#define RCC_PLL_MUL11 RCC_CFGR_PLLMUL11
Kojto	90:cb3d968589d8	341	#define RCC_PLL_MUL12 RCC_CFGR_PLLMUL12
Kojto	90:cb3d968589d8	342	#define RCC_PLL_MUL13 RCC_CFGR_PLLMUL13
Kojto	90:cb3d968589d8	343	#define RCC_PLL_MUL14 RCC_CFGR_PLLMUL14
Kojto	90:cb3d968589d8	344	#define RCC_PLL_MUL15 RCC_CFGR_PLLMUL15
Kojto	90:cb3d968589d8	345	#define RCC_PLL_MUL16 RCC_CFGR_PLLMUL16
Kojto	90:cb3d968589d8	346
Kojto	90:cb3d968589d8	347	#define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLL_MUL2) \|\| ((MUL) == RCC_PLL_MUL3) \|\| \
Kojto	90:cb3d968589d8	348	((MUL) == RCC_PLL_MUL4) \|\| ((MUL) == RCC_PLL_MUL5) \|\| \
Kojto	90:cb3d968589d8	349	((MUL) == RCC_PLL_MUL6) \|\| ((MUL) == RCC_PLL_MUL7) \|\| \
Kojto	90:cb3d968589d8	350	((MUL) == RCC_PLL_MUL8) \|\| ((MUL) == RCC_PLL_MUL9) \|\| \
Kojto	90:cb3d968589d8	351	((MUL) == RCC_PLL_MUL10) \|\| ((MUL) == RCC_PLL_MUL11) \|\| \
Kojto	90:cb3d968589d8	352	((MUL) == RCC_PLL_MUL12) \|\| ((MUL) == RCC_PLL_MUL13) \|\| \
Kojto	90:cb3d968589d8	353	((MUL) == RCC_PLL_MUL14) \|\| ((MUL) == RCC_PLL_MUL15) \|\| \
Kojto	90:cb3d968589d8	354	((MUL) == RCC_PLL_MUL16))
Kojto	90:cb3d968589d8	355	/**
Kojto	90:cb3d968589d8	356	* @}
Kojto	90:cb3d968589d8	357	*/
Kojto	90:cb3d968589d8	358
Kojto	90:cb3d968589d8	359	/** @defgroup RCC_PLL_Clock_Source RCC PLL Clock Source
Kojto	90:cb3d968589d8	360	* @{
Kojto	90:cb3d968589d8	361	*/
Kojto	90:cb3d968589d8	362	#define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC_HSE_PREDIV
Kojto	90:cb3d968589d8	363	/**
Kojto	90:cb3d968589d8	364	* @}
Kojto	90:cb3d968589d8	365	*/
Kojto	90:cb3d968589d8	366
Kojto	90:cb3d968589d8	367	/** @defgroup RCC_System_Clock_Type RCC System Clock Type
Kojto	90:cb3d968589d8	368	* @{
Kojto	90:cb3d968589d8	369	*/
Kojto	90:cb3d968589d8	370	#define RCC_CLOCKTYPE_SYSCLK ((uint32_t)0x00000001)
Kojto	90:cb3d968589d8	371	#define RCC_CLOCKTYPE_HCLK ((uint32_t)0x00000002)
Kojto	90:cb3d968589d8	372	#define RCC_CLOCKTYPE_PCLK1 ((uint32_t)0x00000004)
Kojto	90:cb3d968589d8	373
Kojto	90:cb3d968589d8	374	#define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	375	(((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) \|\| \
Kojto	90:cb3d968589d8	376	(((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1))
Kojto	90:cb3d968589d8	377	/**
Kojto	90:cb3d968589d8	378	* @}
Kojto	90:cb3d968589d8	379	*/
Kojto	90:cb3d968589d8	380
Kojto	90:cb3d968589d8	381	/** @defgroup RCC_System_Clock_Source RCC System Clock Source
Kojto	90:cb3d968589d8	382	* @{
Kojto	90:cb3d968589d8	383	*/
Kojto	90:cb3d968589d8	384	#define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI
Kojto	90:cb3d968589d8	385	#define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE
Kojto	90:cb3d968589d8	386	#define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL
Kojto	90:cb3d968589d8	387	/**
Kojto	90:cb3d968589d8	388	* @}
Kojto	90:cb3d968589d8	389	*/
Kojto	90:cb3d968589d8	390
Kojto	90:cb3d968589d8	391	/** @defgroup RCC_System_Clock_Source_Status RCC System Clock Source Status
Kojto	90:cb3d968589d8	392	* @{
Kojto	90:cb3d968589d8	393	*/
Kojto	90:cb3d968589d8	394	#define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI
Kojto	90:cb3d968589d8	395	#define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE
Kojto	90:cb3d968589d8	396	#define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL
Kojto	90:cb3d968589d8	397	/**
Kojto	90:cb3d968589d8	398	* @}
Kojto	90:cb3d968589d8	399	*/
Kojto	90:cb3d968589d8	400
Kojto	90:cb3d968589d8	401	/** @defgroup RCC_AHB_Clock_Source RCC AHB Clock Source
Kojto	90:cb3d968589d8	402	* @{
Kojto	90:cb3d968589d8	403	*/
Kojto	90:cb3d968589d8	404	#define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1
Kojto	90:cb3d968589d8	405	#define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2
Kojto	90:cb3d968589d8	406	#define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4
Kojto	90:cb3d968589d8	407	#define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8
Kojto	90:cb3d968589d8	408	#define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16
Kojto	90:cb3d968589d8	409	#define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64
Kojto	90:cb3d968589d8	410	#define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128
Kojto	90:cb3d968589d8	411	#define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256
Kojto	90:cb3d968589d8	412	#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
Kojto	90:cb3d968589d8	413
Kojto	90:cb3d968589d8	414	#define IS_RCC_SYSCLK_DIV(DIV) (((DIV) == RCC_SYSCLK_DIV1) \|\| ((DIV) == RCC_SYSCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	415	((DIV) == RCC_SYSCLK_DIV4) \|\| ((DIV) == RCC_SYSCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	416	((DIV) == RCC_SYSCLK_DIV16) \|\| ((DIV) == RCC_SYSCLK_DIV64) \|\| \
Kojto	90:cb3d968589d8	417	((DIV) == RCC_SYSCLK_DIV128) \|\| ((DIV) == RCC_SYSCLK_DIV256) \|\| \
Kojto	90:cb3d968589d8	418	((DIV) == RCC_SYSCLK_DIV512))
Kojto	90:cb3d968589d8	419	/**
Kojto	90:cb3d968589d8	420	* @}
Kojto	90:cb3d968589d8	421	*/
Kojto	90:cb3d968589d8	422
Kojto	90:cb3d968589d8	423	/** @defgroup RCC_APB1_Clock_Source RCC APB1 Clock Source
Kojto	90:cb3d968589d8	424	* @{
Kojto	90:cb3d968589d8	425	*/
Kojto	90:cb3d968589d8	426	#define RCC_HCLK_DIV1 RCC_CFGR_PPRE_DIV1
Kojto	90:cb3d968589d8	427	#define RCC_HCLK_DIV2 RCC_CFGR_PPRE_DIV2
Kojto	90:cb3d968589d8	428	#define RCC_HCLK_DIV4 RCC_CFGR_PPRE_DIV4
Kojto	90:cb3d968589d8	429	#define RCC_HCLK_DIV8 RCC_CFGR_PPRE_DIV8
Kojto	90:cb3d968589d8	430	#define RCC_HCLK_DIV16 RCC_CFGR_PPRE_DIV16
Kojto	90:cb3d968589d8	431
Kojto	90:cb3d968589d8	432	#define IS_RCC_HCLK_DIV(DIV) (((DIV) == RCC_HCLK_DIV1) \|\| ((DIV) == RCC_HCLK_DIV2) \|\| \
Kojto	90:cb3d968589d8	433	((DIV) == RCC_HCLK_DIV4) \|\| ((DIV) == RCC_HCLK_DIV8) \|\| \
Kojto	90:cb3d968589d8	434	((DIV) == RCC_HCLK_DIV16))
Kojto	90:cb3d968589d8	435	/**
Kojto	90:cb3d968589d8	436	* @}
Kojto	90:cb3d968589d8	437	*/
Kojto	90:cb3d968589d8	438
Kojto	90:cb3d968589d8	439	/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
Kojto	90:cb3d968589d8	440	* @{
Kojto	90:cb3d968589d8	441	*/
Kojto	90:cb3d968589d8	442	#define RCC_RTCCLKSOURCE_NONE RCC_BDCR_RTCSEL_NOCLOCK
Kojto	90:cb3d968589d8	443	#define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE
Kojto	90:cb3d968589d8	444	#define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI
Kojto	90:cb3d968589d8	445	#define RCC_RTCCLKSOURCE_HSE_DIV32 RCC_BDCR_RTCSEL_HSE
Kojto	90:cb3d968589d8	446
Kojto	90:cb3d968589d8	447	#define IS_RCC_RTCCLKSOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSOURCE_NONE) \|\| \
Kojto	90:cb3d968589d8	448	((SOURCE) == RCC_RTCCLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	449	((SOURCE) == RCC_RTCCLKSOURCE_LSI) \|\| \
Kojto	90:cb3d968589d8	450	((SOURCE) == RCC_RTCCLKSOURCE_HSE_DIV32))
Kojto	90:cb3d968589d8	451	/**
Kojto	90:cb3d968589d8	452	* @}
Kojto	90:cb3d968589d8	453	*/
Kojto	90:cb3d968589d8	454
Kojto	90:cb3d968589d8	455	/** @defgroup RCC_USART1_Clock_Source RCC USART1 Clock Source
Kojto	90:cb3d968589d8	456	* @{
Kojto	90:cb3d968589d8	457	*/
Kojto	90:cb3d968589d8	458	#define RCC_USART1CLKSOURCE_PCLK1 RCC_CFGR3_USART1SW_PCLK
Kojto	90:cb3d968589d8	459	#define RCC_USART1CLKSOURCE_SYSCLK RCC_CFGR3_USART1SW_SYSCLK
Kojto	90:cb3d968589d8	460	#define RCC_USART1CLKSOURCE_LSE RCC_CFGR3_USART1SW_LSE
Kojto	90:cb3d968589d8	461	#define RCC_USART1CLKSOURCE_HSI RCC_CFGR3_USART1SW_HSI
Kojto	90:cb3d968589d8	462
Kojto	90:cb3d968589d8	463	#define IS_RCC_USART1CLKSOURCE(SOURCE) (((SOURCE) == RCC_USART1CLKSOURCE_PCLK1) \|\| \
Kojto	90:cb3d968589d8	464	((SOURCE) == RCC_USART1CLKSOURCE_SYSCLK) \|\| \
Kojto	90:cb3d968589d8	465	((SOURCE) == RCC_USART1CLKSOURCE_LSE) \|\| \
Kojto	90:cb3d968589d8	466	((SOURCE) == RCC_USART1CLKSOURCE_HSI))
Kojto	90:cb3d968589d8	467	/**
Kojto	90:cb3d968589d8	468	* @}
Kojto	90:cb3d968589d8	469	*/
Kojto	90:cb3d968589d8	470
Kojto	90:cb3d968589d8	471	/** @defgroup RCC_I2C1_Clock_Source RCC I2C1 Clock Source
Kojto	90:cb3d968589d8	472	* @{
Kojto	90:cb3d968589d8	473	*/
Kojto	90:cb3d968589d8	474	#define RCC_I2C1CLKSOURCE_HSI RCC_CFGR3_I2C1SW_HSI
Kojto	90:cb3d968589d8	475	#define RCC_I2C1CLKSOURCE_SYSCLK RCC_CFGR3_I2C1SW_SYSCLK
Kojto	90:cb3d968589d8	476
Kojto	90:cb3d968589d8	477	#define IS_RCC_I2C1CLKSOURCE(SOURCE) (((SOURCE) == RCC_I2C1CLKSOURCE_HSI) \|\| \
Kojto	90:cb3d968589d8	478	((SOURCE) == RCC_I2C1CLKSOURCE_SYSCLK))
Kojto	90:cb3d968589d8	479	/**
Kojto	90:cb3d968589d8	480	* @}
Kojto	90:cb3d968589d8	481	*/
Kojto	90:cb3d968589d8	482
Kojto	90:cb3d968589d8	483	/** @defgroup RCC_MCOx_Index RCC MCOx Index
Kojto	90:cb3d968589d8	484	* @{
Kojto	90:cb3d968589d8	485	*/
Kojto	90:cb3d968589d8	486	#define RCC_MCO ((uint32_t)0x00000000)
Kojto	90:cb3d968589d8	487
Kojto	90:cb3d968589d8	488	#define IS_RCC_MCO(MCOx) ((MCOx) == RCC_MCO)
Kojto	90:cb3d968589d8	489	/**
Kojto	90:cb3d968589d8	490	* @}
Kojto	90:cb3d968589d8	491	*/
Kojto	90:cb3d968589d8	492
Kojto	90:cb3d968589d8	493	/** @defgroup RCC_MCO_Clock_Source RCC MCO Clock Source
Kojto	90:cb3d968589d8	494	* @{
Kojto	90:cb3d968589d8	495	*/
Kojto	90:cb3d968589d8	496	#define RCC_MCOSOURCE_NONE RCC_CFGR_MCO_NOCLOCK
Kojto	90:cb3d968589d8	497	#define RCC_MCOSOURCE_LSI RCC_CFGR_MCO_LSI
Kojto	90:cb3d968589d8	498	#define RCC_MCOSOURCE_LSE RCC_CFGR_MCO_LSE
Kojto	90:cb3d968589d8	499	#define RCC_MCOSOURCE_SYSCLK RCC_CFGR_MCO_SYSCLK
Kojto	90:cb3d968589d8	500	#define RCC_MCOSOURCE_HSI RCC_CFGR_MCO_HSI
Kojto	90:cb3d968589d8	501	#define RCC_MCOSOURCE_HSE RCC_CFGR_MCO_HSE
Kojto	90:cb3d968589d8	502	#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_CFGR_MCO_PLL
Kojto	90:cb3d968589d8	503	#define RCC_MCOSOURCE_HSI14 RCC_CFGR_MCO_HSI14
Kojto	90:cb3d968589d8	504	/**
Kojto	90:cb3d968589d8	505	* @}
Kojto	90:cb3d968589d8	506	*/
Kojto	90:cb3d968589d8	507
Kojto	90:cb3d968589d8	508	/** @defgroup RCC_Interrupt RCC Interrupt
Kojto	90:cb3d968589d8	509	* @{
Kojto	90:cb3d968589d8	510	*/
Kojto	90:cb3d968589d8	511	#define RCC_IT_LSIRDY ((uint8_t)0x01)
Kojto	90:cb3d968589d8	512	#define RCC_IT_LSERDY ((uint8_t)0x02)
Kojto	90:cb3d968589d8	513	#define RCC_IT_HSIRDY ((uint8_t)0x04)
Kojto	90:cb3d968589d8	514	#define RCC_IT_HSERDY ((uint8_t)0x08)
Kojto	90:cb3d968589d8	515	#define RCC_IT_PLLRDY ((uint8_t)0x10)
Kojto	90:cb3d968589d8	516	#define RCC_IT_HSI14 ((uint8_t)0x20)
Kojto	90:cb3d968589d8	517	#define RCC_IT_CSS ((uint8_t)0x80)
Kojto	90:cb3d968589d8	518	/**
Kojto	90:cb3d968589d8	519	* @}
Kojto	90:cb3d968589d8	520	*/
Kojto	90:cb3d968589d8	521
Kojto	90:cb3d968589d8	522	/** @defgroup RCC_Flag RCC Flag
Kojto	90:cb3d968589d8	523	* Elements values convention: 0XXYYYYYb
Kojto	90:cb3d968589d8	524	* - YYYYY : Flag position in the register
Kojto	90:cb3d968589d8	525	* - XX : Register index
Kojto	90:cb3d968589d8	526	* - 00: CR register
Kojto	90:cb3d968589d8	527	* - 01: CR2 register
Kojto	90:cb3d968589d8	528	* - 10: BDCR register
Kojto	90:cb3d968589d8	529	* - 11: CSR register
Kojto	90:cb3d968589d8	530	* @{
Kojto	90:cb3d968589d8	531	*/
Kojto	90:cb3d968589d8	532	#define CR_REG_INDEX 0
Kojto	90:cb3d968589d8	533	#define CR2_REG_INDEX 1
Kojto	90:cb3d968589d8	534	#define BDCR_REG_INDEX 2
Kojto	90:cb3d968589d8	535	#define CSR_REG_INDEX 3
Kojto	90:cb3d968589d8	536
Kojto	90:cb3d968589d8	537	/* Flags in the CR register */
Kojto	90:cb3d968589d8	538	#define RCC_CR_HSIRDY_BitNumber 1
Kojto	90:cb3d968589d8	539	#define RCC_CR_HSERDY_BitNumber 17
Kojto	90:cb3d968589d8	540	#define RCC_CR_PLLRDY_BitNumber 25
Kojto	90:cb3d968589d8	541
Kojto	90:cb3d968589d8	542	#define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSIRDY_BitNumber))
Kojto	90:cb3d968589d8	543	#define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_HSERDY_BitNumber))
Kojto	90:cb3d968589d8	544	#define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5) \| RCC_CR_PLLRDY_BitNumber))
Kojto	90:cb3d968589d8	545
Kojto	90:cb3d968589d8	546	/* Flags in the CR2 register */
Kojto	90:cb3d968589d8	547	#define RCC_CR2_HSI14RDY_BitNumber 1
Kojto	90:cb3d968589d8	548
Kojto	90:cb3d968589d8	549	#define RCC_FLAG_HSI14RDY ((uint8_t)((CR2_REG_INDEX << 5) \| RCC_CR2_HSI14RDY_BitNumber))
Kojto	90:cb3d968589d8	550
Kojto	90:cb3d968589d8	551	/* Flags in the BDCR register */
Kojto	90:cb3d968589d8	552	#define RCC_BDCR_LSERDY_BitNumber 1
Kojto	90:cb3d968589d8	553
Kojto	90:cb3d968589d8	554	#define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5) \| RCC_BDCR_LSERDY_BitNumber))
Kojto	90:cb3d968589d8	555
Kojto	90:cb3d968589d8	556	/* Flags in the CSR register */
Kojto	90:cb3d968589d8	557	#define RCC_CSR_LSIRDY_BitNumber 1
Kojto	90:cb3d968589d8	558	#define RCC_CSR_V18PWRRSTF_BitNumber 23
Kojto	90:cb3d968589d8	559	#define RCC_CSR_RMVF_BitNumber 24
Kojto	90:cb3d968589d8	560	#define RCC_CSR_OBLRSTF_BitNumber 25
Kojto	90:cb3d968589d8	561	#define RCC_CSR_PINRSTF_BitNumber 26
Kojto	90:cb3d968589d8	562	#define RCC_CSR_PORRSTF_BitNumber 27
Kojto	90:cb3d968589d8	563	#define RCC_CSR_SFTRSTF_BitNumber 28
Kojto	90:cb3d968589d8	564	#define RCC_CSR_IWDGRSTF_BitNumber 29
Kojto	90:cb3d968589d8	565	#define RCC_CSR_WWDGRSTF_BitNumber 30
Kojto	90:cb3d968589d8	566	#define RCC_CSR_LPWRRSTF_BitNumber 31
Kojto	90:cb3d968589d8	567
Kojto	90:cb3d968589d8	568	#define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
Kojto	90:cb3d968589d8	569	#define RCC_FLAG_V18PWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LSIRDY_BitNumber))
Kojto	90:cb3d968589d8	570	#define RCC_FLAG_RMV ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_RMVF_BitNumber))
Kojto	90:cb3d968589d8	571	#define RCC_FLAG_OBLRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_OBLRSTF_BitNumber))
Kojto	90:cb3d968589d8	572	#define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PINRSTF_BitNumber))
Kojto	90:cb3d968589d8	573	#define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_PORRSTF_BitNumber))
Kojto	90:cb3d968589d8	574	#define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_SFTRSTF_BitNumber))
Kojto	90:cb3d968589d8	575	#define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_IWDGRSTF_BitNumber))
Kojto	90:cb3d968589d8	576	#define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_WWDGRSTF_BitNumber))
Kojto	90:cb3d968589d8	577	#define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5) \| RCC_CSR_LPWRRSTF_BitNumber))
Kojto	90:cb3d968589d8	578	/**
Kojto	90:cb3d968589d8	579	* @}
Kojto	90:cb3d968589d8	580	*/
Kojto	90:cb3d968589d8	581
Kojto	90:cb3d968589d8	582	/** @defgroup RCC_Calibration_values RCC Calibration values
Kojto	90:cb3d968589d8	583	* @{
Kojto	90:cb3d968589d8	584	*/
Kojto	90:cb3d968589d8	585	#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
Kojto	90:cb3d968589d8	586
Kojto	90:cb3d968589d8	587	/**
Kojto	90:cb3d968589d8	588	* @}
Kojto	90:cb3d968589d8	589	*/
Kojto	90:cb3d968589d8	590
Kojto	90:cb3d968589d8	591	/** @addtogroup RCC_Timeout
Kojto	90:cb3d968589d8	592	* @{
Kojto	90:cb3d968589d8	593	*/
Kojto	90:cb3d968589d8	594
Kojto	90:cb3d968589d8	595	#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
Kojto	90:cb3d968589d8	596	#define HSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	90:cb3d968589d8	597	#define LSI_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	90:cb3d968589d8	598	#define LSE_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto	90:cb3d968589d8	599	#define HSI14_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	90:cb3d968589d8	600	#define HSI48_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	90:cb3d968589d8	601	#define PLL_TIMEOUT_VALUE ((uint32_t)100) /* 100 ms */
Kojto	90:cb3d968589d8	602	#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
Kojto	90:cb3d968589d8	603
Kojto	90:cb3d968589d8	604	/**
Kojto	90:cb3d968589d8	605	* @}
Kojto	90:cb3d968589d8	606	*/
Kojto	90:cb3d968589d8	607
Kojto	90:cb3d968589d8	608	/**
Kojto	90:cb3d968589d8	609	* @}
Kojto	90:cb3d968589d8	610	*/
Kojto	90:cb3d968589d8	611
Kojto	90:cb3d968589d8	612	/* Exported macro ------------------------------------------------------------*/
Kojto	90:cb3d968589d8	613
Kojto	90:cb3d968589d8	614	/** @defgroup RCC_Exported_Macros RCC Exported Macros
Kojto	90:cb3d968589d8	615	* @{
Kojto	90:cb3d968589d8	616	*/
Kojto	90:cb3d968589d8	617
Kojto	90:cb3d968589d8	618	/** @defgroup RCC_AHB_Clock_Enable_Disable RCC AHB Clock Enable Disable
Kojto	90:cb3d968589d8	619	* @brief Enable or disable the AHB peripheral clock.
Kojto	90:cb3d968589d8	620	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	621	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	622	* using it.
Kojto	90:cb3d968589d8	623	* @{
Kojto	90:cb3d968589d8	624	*/
Kojto	90:cb3d968589d8	625	#define __GPIOA_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOAEN))
Kojto	90:cb3d968589d8	626	#define __GPIOB_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOBEN))
Kojto	90:cb3d968589d8	627	#define __GPIOC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOCEN))
Kojto	90:cb3d968589d8	628	#define __GPIOF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_GPIOFEN))
Kojto	90:cb3d968589d8	629	#define __CRC_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_CRCEN))
Kojto	90:cb3d968589d8	630	#define __DMA1_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_DMA1EN))
Kojto	90:cb3d968589d8	631	#define __SRAM_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_SRAMEN))
Kojto	90:cb3d968589d8	632	#define __FLITF_CLK_ENABLE() (RCC->AHBENR \|= (RCC_AHBENR_FLITFEN))
Kojto	90:cb3d968589d8	633
Kojto	90:cb3d968589d8	634	#define __GPIOA_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOAEN))
Kojto	90:cb3d968589d8	635	#define __GPIOB_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOBEN))
Kojto	90:cb3d968589d8	636	#define __GPIOC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOCEN))
Kojto	90:cb3d968589d8	637	#define __GPIOF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_GPIOFEN))
Kojto	90:cb3d968589d8	638	#define __CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
Kojto	90:cb3d968589d8	639	#define __DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
Kojto	90:cb3d968589d8	640	#define __SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
Kojto	90:cb3d968589d8	641	#define __FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
Kojto	90:cb3d968589d8	642	/**
Kojto	90:cb3d968589d8	643	* @}
Kojto	90:cb3d968589d8	644	*/
Kojto	90:cb3d968589d8	645
Kojto	90:cb3d968589d8	646	/** @defgroup RCC_APB1_Clock_Enable_Disable RCC APB1 Clock Enable Disable
Kojto	90:cb3d968589d8	647	* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
Kojto	90:cb3d968589d8	648	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	649	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	650	* using it.
Kojto	90:cb3d968589d8	651	* @{
Kojto	90:cb3d968589d8	652	*/
Kojto	90:cb3d968589d8	653	#define __TIM3_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	654	#define __TIM14_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_TIM14EN))
Kojto	90:cb3d968589d8	655	#define __WWDG_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_WWDGEN))
Kojto	90:cb3d968589d8	656	#define __I2C1_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_I2C1EN))
Kojto	90:cb3d968589d8	657	#define __PWR_CLK_ENABLE() (RCC->APB1ENR \|= (RCC_APB1ENR_PWREN))
Kojto	90:cb3d968589d8	658
Kojto	90:cb3d968589d8	659	#define __TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
Kojto	90:cb3d968589d8	660	#define __TIM14_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM14EN))
Kojto	90:cb3d968589d8	661	#define __WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
Kojto	90:cb3d968589d8	662	#define __I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
Kojto	90:cb3d968589d8	663	#define __PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
Kojto	90:cb3d968589d8	664	/**
Kojto	90:cb3d968589d8	665	* @}
Kojto	90:cb3d968589d8	666	*/
Kojto	90:cb3d968589d8	667
Kojto	90:cb3d968589d8	668	/** @defgroup RCC_APB2_Clock_Enable_Disable RCC APB2 Clock Enable Disable
Kojto	90:cb3d968589d8	669	* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
Kojto	90:cb3d968589d8	670	* @note After reset, the peripheral clock (used for registers read/write access)
Kojto	90:cb3d968589d8	671	* is disabled and the application software has to enable this clock before
Kojto	90:cb3d968589d8	672	* using it.
Kojto	90:cb3d968589d8	673	* @{
Kojto	90:cb3d968589d8	674	*/
Kojto	90:cb3d968589d8	675	#define __SYSCFG_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SYSCFGEN))
Kojto	90:cb3d968589d8	676	#define __ADC1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_ADC1EN))
Kojto	90:cb3d968589d8	677	#define __TIM1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM1EN))
Kojto	90:cb3d968589d8	678	#define __SPI1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	679	#define __TIM16_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM16EN))
Kojto	90:cb3d968589d8	680	#define __TIM17_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_TIM17EN))
Kojto	90:cb3d968589d8	681	#define __USART1_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_USART1EN))
Kojto	90:cb3d968589d8	682	#define __DBGMCU_CLK_ENABLE() (RCC->APB2ENR \|= (RCC_APB2ENR_DBGMCUEN))
Kojto	90:cb3d968589d8	683
Kojto	90:cb3d968589d8	684	#define __SYSCFG_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SYSCFGEN))
Kojto	90:cb3d968589d8	685	#define __ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
Kojto	90:cb3d968589d8	686	#define __TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
Kojto	90:cb3d968589d8	687	#define __SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
Kojto	90:cb3d968589d8	688	#define __TIM16_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM16EN))
Kojto	90:cb3d968589d8	689	#define __TIM17_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM17EN))
Kojto	90:cb3d968589d8	690	#define __USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
Kojto	90:cb3d968589d8	691	#define __DBGMCU_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_DBGMCUEN))
Kojto	90:cb3d968589d8	692	/**
Kojto	90:cb3d968589d8	693	* @}
Kojto	90:cb3d968589d8	694	*/
Kojto	90:cb3d968589d8	695
Kojto	90:cb3d968589d8	696	/** @defgroup RCC_AHB_Force_Release_Reset RCC AHB Force Release Reset
Kojto	90:cb3d968589d8	697	* @brief Force or release AHB peripheral reset.
Kojto	90:cb3d968589d8	698	* @{
Kojto	90:cb3d968589d8	699	*/
Kojto	90:cb3d968589d8	700	#define __AHB_FORCE_RESET() (RCC->AHBRSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	701	#define __GPIOA_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOARST))
Kojto	90:cb3d968589d8	702	#define __GPIOB_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOBRST))
Kojto	90:cb3d968589d8	703	#define __GPIOC_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOCRST))
Kojto	90:cb3d968589d8	704	#define __GPIOF_FORCE_RESET() (RCC->AHBRSTR \|= (RCC_AHBRSTR_GPIOFRST))
Kojto	90:cb3d968589d8	705
Kojto	90:cb3d968589d8	706	#define __AHB_RELEASE_RESET() (RCC->AHBRSTR = 0x00)
Kojto	90:cb3d968589d8	707	#define __GPIOA_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOARST))
Kojto	90:cb3d968589d8	708	#define __GPIOB_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOBRST))
Kojto	90:cb3d968589d8	709	#define __GPIOC_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOCRST))
Kojto	90:cb3d968589d8	710	#define __GPIOF_RELEASE_RESET() (RCC->AHBRSTR &= ~(RCC_AHBRSTR_GPIOFRST))
Kojto	90:cb3d968589d8	711	/**
Kojto	90:cb3d968589d8	712	* @}
Kojto	90:cb3d968589d8	713	*/
Kojto	90:cb3d968589d8	714
Kojto	90:cb3d968589d8	715	/** @defgroup RCC_APB1_Force_Release_Reset RCC APB1 Force Release Reset
Kojto	90:cb3d968589d8	716	* @brief Force or release APB1 peripheral reset.
Kojto	90:cb3d968589d8	717	* @{
Kojto	90:cb3d968589d8	718	*/
Kojto	90:cb3d968589d8	719	#define __APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	720	#define __TIM3_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	721	#define __TIM14_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_TIM14RST))
Kojto	90:cb3d968589d8	722	#define __WWDG_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_WWDGRST))
Kojto	90:cb3d968589d8	723	#define __I2C1_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_I2C1RST))
Kojto	90:cb3d968589d8	724	#define __PWR_FORCE_RESET() (RCC->APB1RSTR \|= (RCC_APB1RSTR_PWRRST))
Kojto	90:cb3d968589d8	725
Kojto	90:cb3d968589d8	726	#define __APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
Kojto	90:cb3d968589d8	727	#define __TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
Kojto	90:cb3d968589d8	728	#define __TIM14_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM14RST))
Kojto	90:cb3d968589d8	729	#define __WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
Kojto	90:cb3d968589d8	730	#define __I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
Kojto	90:cb3d968589d8	731	#define __PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
Kojto	90:cb3d968589d8	732	/**
Kojto	90:cb3d968589d8	733	* @}
Kojto	90:cb3d968589d8	734	*/
Kojto	90:cb3d968589d8	735
Kojto	90:cb3d968589d8	736	/** @defgroup RCC_APB2_Force_Release_Reset RCC APB2 Force Release Reset
Kojto	90:cb3d968589d8	737	* @brief Force or release APB2 peripheral reset.
Kojto	90:cb3d968589d8	738	* @{
Kojto	90:cb3d968589d8	739	*/
Kojto	90:cb3d968589d8	740	#define __APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFF)
Kojto	90:cb3d968589d8	741	#define __SYSCFG_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SYSCFGRST))
Kojto	90:cb3d968589d8	742	#define __ADC1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_ADC1RST))
Kojto	90:cb3d968589d8	743	#define __TIM1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM1RST))
Kojto	90:cb3d968589d8	744	#define __SPI1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	745	#define __USART1_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_USART1RST))
Kojto	90:cb3d968589d8	746	#define __TIM16_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM16RST))
Kojto	90:cb3d968589d8	747	#define __TIM17_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_TIM17RST))
Kojto	90:cb3d968589d8	748	#define __DBGMCU_FORCE_RESET() (RCC->APB2RSTR \|= (RCC_APB2RSTR_DBGMCURST))
Kojto	90:cb3d968589d8	749
Kojto	90:cb3d968589d8	750	#define __APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
Kojto	90:cb3d968589d8	751	#define __SYSCFG_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SYSCFGRST))
Kojto	90:cb3d968589d8	752	#define __ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
Kojto	90:cb3d968589d8	753	#define __TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
Kojto	90:cb3d968589d8	754	#define __SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
Kojto	90:cb3d968589d8	755	#define __USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
Kojto	90:cb3d968589d8	756	#define __TIM16_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM16RST))
Kojto	90:cb3d968589d8	757	#define __TIM17_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM17RST))
Kojto	90:cb3d968589d8	758	#define __DBGMCU_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_DBGMCURST))
Kojto	90:cb3d968589d8	759	/**
Kojto	90:cb3d968589d8	760	* @}
Kojto	90:cb3d968589d8	761	*/
Kojto	90:cb3d968589d8	762
Kojto	90:cb3d968589d8	763	/** @defgroup RCC_HSI_Configuration RCC HSI Configuration
Kojto	90:cb3d968589d8	764	* @{
Kojto	90:cb3d968589d8	765	*/
Kojto	90:cb3d968589d8	766
Kojto	90:cb3d968589d8	767	/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
Kojto	90:cb3d968589d8	768	* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	769	* It is used (enabled by hardware) as system clock source after startup
Kojto	90:cb3d968589d8	770	* from Reset, wakeup from STOP and STANDBY mode, or in case of failure
Kojto	90:cb3d968589d8	771	* of the HSE used directly or indirectly as system clock (if the Clock
Kojto	90:cb3d968589d8	772	* Security System CSS is enabled).
Kojto	90:cb3d968589d8	773	* @note HSI can not be stopped if it is used as system clock source. In this case,
Kojto	90:cb3d968589d8	774	* you have to select another source of the system clock then stop the HSI.
Kojto	90:cb3d968589d8	775	* @note After enabling the HSI, the application software should wait on HSIRDY
Kojto	90:cb3d968589d8	776	* flag to be set indicating that HSI clock is stable and can be used as
Kojto	90:cb3d968589d8	777	* system clock source.
Kojto	90:cb3d968589d8	778	* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
Kojto	90:cb3d968589d8	779	* clock cycles.
Kojto	90:cb3d968589d8	780	*/
Kojto	90:cb3d968589d8	781	#define __HAL_RCC_HSI_ENABLE() SET_BIT(RCC->CR, RCC_CR_HSION)
Kojto	90:cb3d968589d8	782	#define __HAL_RCC_HSI_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_HSION)
Kojto	90:cb3d968589d8	783
Kojto	90:cb3d968589d8	784	/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
Kojto	90:cb3d968589d8	785	* @note The calibration is used to compensate for the variations in voltage
Kojto	90:cb3d968589d8	786	* and temperature that influence the frequency of the internal HSI RC.
Kojto	90:cb3d968589d8	787	* @param __HSICalibrationValue__: specifies the calibration trimming value
Kojto	90:cb3d968589d8	788	* (default is RCC_HSICALIBRATION_DEFAULT).
Kojto	90:cb3d968589d8	789	* This parameter must be a number between 0 and 0x1F.
Kojto	90:cb3d968589d8	790	*/
Kojto	90:cb3d968589d8	791	#define RCC_CR_HSITRIM_BitNumber 3
Kojto	90:cb3d968589d8	792	#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) \
Kojto	90:cb3d968589d8	793	MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_BitNumber)
Kojto	90:cb3d968589d8	794	/**
Kojto	90:cb3d968589d8	795	* @}
Kojto	90:cb3d968589d8	796	*/
Kojto	90:cb3d968589d8	797
Kojto	90:cb3d968589d8	798	/** @defgroup RCC_LSI_Configuration RCC LSI Configuration
Kojto	90:cb3d968589d8	799	* @{
Kojto	90:cb3d968589d8	800	*/
Kojto	90:cb3d968589d8	801
Kojto	90:cb3d968589d8	802	/** @brief Macro to enable or disable the Internal Low Speed oscillator (LSI).
Kojto	90:cb3d968589d8	803	* @note After enabling the LSI, the application software should wait on
Kojto	90:cb3d968589d8	804	* LSIRDY flag to be set indicating that LSI clock is stable and can
Kojto	90:cb3d968589d8	805	* be used to clock the IWDG and/or the RTC.
Kojto	90:cb3d968589d8	806	* @note LSI can not be disabled if the IWDG is running.
Kojto	90:cb3d968589d8	807	* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
Kojto	90:cb3d968589d8	808	* clock cycles.
Kojto	90:cb3d968589d8	809	*/
Kojto	90:cb3d968589d8	810	#define __HAL_RCC_LSI_ENABLE() SET_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	90:cb3d968589d8	811	#define __HAL_RCC_LSI_DISABLE() CLEAR_BIT(RCC->CSR, RCC_CSR_LSION)
Kojto	90:cb3d968589d8	812	/**
Kojto	90:cb3d968589d8	813	* @}
Kojto	90:cb3d968589d8	814	*/
Kojto	90:cb3d968589d8	815
Kojto	90:cb3d968589d8	816	/** @defgroup RCC_HSE_Configuration RCC HSE Configuration
Kojto	90:cb3d968589d8	817	* @{
Kojto	90:cb3d968589d8	818	*/
Kojto	90:cb3d968589d8	819
Kojto	90:cb3d968589d8	820	/**
Kojto	90:cb3d968589d8	821	* @brief Macro to configure the External High Speed oscillator (HSE).
Kojto	90:cb3d968589d8	822	* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
Kojto	90:cb3d968589d8	823	* software should wait on HSERDY flag to be set indicating that HSE clock
Kojto	90:cb3d968589d8	824	* is stable and can be used to clock the PLL and/or system clock.
Kojto	90:cb3d968589d8	825	* @note HSE state can not be changed if it is used directly or through the
Kojto	90:cb3d968589d8	826	* PLL as system clock. In this case, you have to select another source
Kojto	90:cb3d968589d8	827	* of the system clock then change the HSE state (ex. disable it).
Kojto	90:cb3d968589d8	828	* @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	829	* @note This function reset the CSSON bit, so if the Clock security system(CSS)
Kojto	90:cb3d968589d8	830	* was previously enabled you have to enable it again after calling this
Kojto	90:cb3d968589d8	831	* function.
Kojto	90:cb3d968589d8	832	* @param __STATE__: specifies the new state of the HSE.
Kojto	90:cb3d968589d8	833	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	834	* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
Kojto	90:cb3d968589d8	835	* 6 HSE oscillator clock cycles.
Kojto	90:cb3d968589d8	836	* @arg RCC_HSE_ON: turn ON the HSE oscillator
Kojto	90:cb3d968589d8	837	* @arg RCC_HSE_BYPASS: HSE oscillator bypassed with external clock
Kojto	90:cb3d968589d8	838	*/
Kojto	90:cb3d968589d8	839	#define __HAL_RCC_HSE_CONFIG(__STATE__) ((__IO uint8_t )RCC_CR_BYTE2_ADDRESS = (__STATE__))
Kojto	90:cb3d968589d8	840
Kojto	90:cb3d968589d8	841	/**
Kojto	90:cb3d968589d8	842	* @brief Macro to configure the External High Speed oscillator (HSE) Predivision factor for PLL.
Kojto	90:cb3d968589d8	843	* @note Predivision factor can not be changed if PLL is used as system clock
Kojto	90:cb3d968589d8	844	* In this case, you have to select another source of the system clock, disable the PLL and
Kojto	90:cb3d968589d8	845	* then change the HSE predivision factor.
Kojto	90:cb3d968589d8	846	* @param __HSEPredivValue__: specifies the division value applied to HSE.
Kojto	90:cb3d968589d8	847	* This parameter must be a number between RCC_HSE_PREDIV_DIV1 and RCC_HSE_PREDIV_DIV16.
Kojto	90:cb3d968589d8	848	*/
Kojto	90:cb3d968589d8	849	#define __HAL_RCC_HSE_PREDIV_CONFIG(__HSEPredivValue__) \
Kojto	90:cb3d968589d8	850	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (uint32_t)(__HSEPredivValue__))
Kojto	90:cb3d968589d8	851	/**
Kojto	90:cb3d968589d8	852	* @}
Kojto	90:cb3d968589d8	853	*/
Kojto	90:cb3d968589d8	854
Kojto	90:cb3d968589d8	855	/** @defgroup RCC_LSE_Configuration RCC LSE Configuration
Kojto	90:cb3d968589d8	856	* @{
Kojto	90:cb3d968589d8	857	*/
Kojto	90:cb3d968589d8	858	/**
Kojto	90:cb3d968589d8	859	* @brief Macro to configure the External Low Speed oscillator (LSE).
Kojto	90:cb3d968589d8	860	* @note As the LSE is in the Backup domain and write access is denied to
Kojto	90:cb3d968589d8	861	* this domain after reset, you have to enable write access using
Kojto	90:cb3d968589d8	862	* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
Kojto	90:cb3d968589d8	863	* (to be done once after reset).
Kojto	90:cb3d968589d8	864	* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
Kojto	90:cb3d968589d8	865	* software should wait on LSERDY flag to be set indicating that LSE clock
Kojto	90:cb3d968589d8	866	* is stable and can be used to clock the RTC.
Kojto	90:cb3d968589d8	867	* @param __STATE__: specifies the new state of the LSE.
Kojto	90:cb3d968589d8	868	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	869	* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
Kojto	90:cb3d968589d8	870	* 6 LSE oscillator clock cycles.
Kojto	90:cb3d968589d8	871	* @arg RCC_LSE_ON: turn ON the LSE oscillator
Kojto	90:cb3d968589d8	872	* @arg RCC_LSE_BYPASS: LSE oscillator bypassed with external clock
Kojto	90:cb3d968589d8	873	*/
Kojto	90:cb3d968589d8	874	#define __HAL_RCC_LSE_CONFIG(__STATE__) \
Kojto	90:cb3d968589d8	875	MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEON\|RCC_BDCR_LSEBYP, (uint32_t)(__STATE__))
Kojto	90:cb3d968589d8	876	/**
Kojto	90:cb3d968589d8	877	* @}
Kojto	90:cb3d968589d8	878	*/
Kojto	90:cb3d968589d8	879
Kojto	90:cb3d968589d8	880	/** @defgroup RCC_HSI14_Configuration RCC_HSI14_Configuration
Kojto	90:cb3d968589d8	881	* @{
Kojto	90:cb3d968589d8	882	*/
Kojto	90:cb3d968589d8	883
Kojto	90:cb3d968589d8	884	/** @brief Macros to enable or disable the Internal 14Mhz High Speed oscillator (HSI14).
Kojto	90:cb3d968589d8	885	* @note The HSI14 is stopped by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	886	* @note HSI14 can not be stopped if it is used as system clock source. In this case,
Kojto	90:cb3d968589d8	887	* you have to select another source of the system clock then stop the HSI14.
Kojto	90:cb3d968589d8	888	* @note After enabling the HSI14 with __HAL_RCC_HSI14_ENABLE(), the application software
Kojto	90:cb3d968589d8	889	* should wait on HSI14RDY flag to be set indicating that HSI clock is stable and can be
Kojto	90:cb3d968589d8	890	* used as system clock source. This is not necessary if HAL_RCC_OscConfig() is used.
Kojto	90:cb3d968589d8	891	* @note When the HSI14 is stopped, HSI14RDY flag goes low after 6 HSI14 oscillator
Kojto	90:cb3d968589d8	892	* clock cycles.
Kojto	90:cb3d968589d8	893	*/
Kojto	90:cb3d968589d8	894	#define __HAL_RCC_HSI14_ENABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14ON)
Kojto	90:cb3d968589d8	895	#define __HAL_RCC_HSI14_DISABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14ON)
Kojto	90:cb3d968589d8	896
Kojto	90:cb3d968589d8	897	/** @brief macros to Enable or Disable the Internal 14Mhz High Speed oscillator (HSI14) usage by ADC.
Kojto	90:cb3d968589d8	898	*/
Kojto	90:cb3d968589d8	899	#define __HAL_RCC_HSI14ADC_ENABLE() CLEAR_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
Kojto	90:cb3d968589d8	900	#define __HAL_RCC_HSI14ADC_DISABLE() SET_BIT(RCC->CR2, RCC_CR2_HSI14DIS)
Kojto	90:cb3d968589d8	901
Kojto	90:cb3d968589d8	902	/** @brief Macro to adjust the Internal 14Mhz High Speed oscillator (HSI) calibration value.
Kojto	90:cb3d968589d8	903	* @note The calibration is used to compensate for the variations in voltage
Kojto	90:cb3d968589d8	904	* and temperature that influence the frequency of the internal HSI14 RC.
Kojto	90:cb3d968589d8	905	* @param __HSI14CalibrationValue__: specifies the calibration trimming value
Kojto	90:cb3d968589d8	906	* (default is RCC_HSI14CALIBRATION_DEFAULT).
Kojto	90:cb3d968589d8	907	* This parameter must be a number between 0 and 0x1F.
Kojto	90:cb3d968589d8	908	*/
Kojto	90:cb3d968589d8	909	#define RCC_CR2_HSI14TRIM_BitNumber 3
Kojto	90:cb3d968589d8	910	#define __HAL_RCC_HSI14_CALIBRATIONVALUE_ADJUST(__HSI14CalibrationValue__) \
Kojto	90:cb3d968589d8	911	MODIFY_REG(RCC->CR2, RCC_CR2_HSI14TRIM, (uint32_t)(__HSI14CalibrationValue__) << RCC_CR2_HSI14TRIM_BitNumber)
Kojto	90:cb3d968589d8	912	/**
Kojto	90:cb3d968589d8	913	* @}
Kojto	90:cb3d968589d8	914	*/
Kojto	90:cb3d968589d8	915
Kojto	90:cb3d968589d8	916	/** @defgroup RCC_USARTx_Clock_Config RCC USARTx Clock Config
Kojto	90:cb3d968589d8	917	* @{
Kojto	90:cb3d968589d8	918	*/
Kojto	90:cb3d968589d8	919
Kojto	90:cb3d968589d8	920	/** @brief Macro to configure the USART1 clock (USART1CLK).
Kojto	90:cb3d968589d8	921	* @param __USART1CLKSource__: specifies the USART1 clock source.
Kojto	90:cb3d968589d8	922	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	923	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
Kojto	90:cb3d968589d8	924	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto	90:cb3d968589d8	925	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto	90:cb3d968589d8	926	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto	90:cb3d968589d8	927	*/
Kojto	90:cb3d968589d8	928	#define __HAL_RCC_USART1_CONFIG(__USART1CLKSource__) \
Kojto	90:cb3d968589d8	929	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_USART1SW, (uint32_t)(__USART1CLKSource__))
Kojto	90:cb3d968589d8	930
Kojto	90:cb3d968589d8	931	/** @brief Macro to get the USART1 clock source.
Kojto	90:cb3d968589d8	932	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	933	* @arg RCC_USART1CLKSOURCE_PCLK1: PCLK1 selected as USART1 clock
Kojto	90:cb3d968589d8	934	* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
Kojto	90:cb3d968589d8	935	* @arg RCC_USART1CLKSOURCE_SYSCLK: System Clock selected as USART1 clock
Kojto	90:cb3d968589d8	936	* @arg RCC_USART1CLKSOURCE_LSE: LSE selected as USART1 clock
Kojto	90:cb3d968589d8	937	*/
Kojto	90:cb3d968589d8	938	#define __HAL_RCC_GET_USART1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_USART1SW)))
Kojto	90:cb3d968589d8	939	/**
Kojto	90:cb3d968589d8	940	* @}
Kojto	90:cb3d968589d8	941	*/
Kojto	90:cb3d968589d8	942
Kojto	90:cb3d968589d8	943	/** @defgroup RCC_I2Cx_Clock_Config RCC I2Cx Clock Config
Kojto	90:cb3d968589d8	944	* @{
Kojto	90:cb3d968589d8	945	*/
Kojto	90:cb3d968589d8	946
Kojto	90:cb3d968589d8	947	/** @brief Macro to configure the I2C1 clock (I2C1CLK).
Kojto	90:cb3d968589d8	948	* @param __I2C1CLKSource__: specifies the I2C1 clock source.
Kojto	90:cb3d968589d8	949	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	950	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto	90:cb3d968589d8	951	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto	90:cb3d968589d8	952	*/
Kojto	90:cb3d968589d8	953	#define __HAL_RCC_I2C1_CONFIG(__I2C1CLKSource__) \
Kojto	90:cb3d968589d8	954	MODIFY_REG(RCC->CFGR3, RCC_CFGR3_I2C1SW, (uint32_t)(__I2C1CLKSource__))
Kojto	90:cb3d968589d8	955
Kojto	90:cb3d968589d8	956	/** @brief Macro to get the I2C1 clock source.
Kojto	90:cb3d968589d8	957	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	958	* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
Kojto	90:cb3d968589d8	959	* @arg RCC_I2C1CLKSOURCE_SYSCLK: System Clock selected as I2C1 clock
Kojto	90:cb3d968589d8	960	*/
Kojto	90:cb3d968589d8	961	#define __HAL_RCC_GET_I2C1_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR3, RCC_CFGR3_I2C1SW)))
Kojto	90:cb3d968589d8	962	/**
Kojto	90:cb3d968589d8	963	* @}
Kojto	90:cb3d968589d8	964	*/
Kojto	90:cb3d968589d8	965
Kojto	90:cb3d968589d8	966	/** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
Kojto	90:cb3d968589d8	967	* @{
Kojto	90:cb3d968589d8	968	*/
Kojto	90:cb3d968589d8	969	/** @brief Macros to enable or disable the the RTC clock.
Kojto	90:cb3d968589d8	970	* @note These macros must be used only after the RTC clock source was selected.
Kojto	90:cb3d968589d8	971	*/
Kojto	90:cb3d968589d8	972	#define __HAL_RCC_RTC_ENABLE() SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto	90:cb3d968589d8	973	#define __HAL_RCC_RTC_DISABLE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN)
Kojto	90:cb3d968589d8	974
Kojto	90:cb3d968589d8	975	/** @brief Macro to configure the RTC clock (RTCCLK).
Kojto	90:cb3d968589d8	976	* @note As the RTC clock configuration bits are in the Backup domain and write
Kojto	90:cb3d968589d8	977	* access is denied to this domain after reset, you have to enable write
Kojto	90:cb3d968589d8	978	* access using the Power Backup Access macro before to configure
Kojto	90:cb3d968589d8	979	* the RTC clock source (to be done once after reset).
Kojto	90:cb3d968589d8	980	* @note Once the RTC clock is configured it can't be changed unless the
Kojto	90:cb3d968589d8	981	* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
Kojto	90:cb3d968589d8	982	* a Power On Reset (POR).
Kojto	90:cb3d968589d8	983	* @param __RTCCLKSource__: specifies the RTC clock source.
Kojto	90:cb3d968589d8	984	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	985	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
Kojto	90:cb3d968589d8	986	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	90:cb3d968589d8	987	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	90:cb3d968589d8	988	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32
Kojto	90:cb3d968589d8	989	*
Kojto	90:cb3d968589d8	990	* @note If the LSE is used as RTC clock source, the RTC continues to
Kojto	90:cb3d968589d8	991	* work in STOP and STANDBY modes, and can be used as wakeup source.
Kojto	90:cb3d968589d8	992	* However, when the LSI clock and HSE clock divided by 32 is used as RTC clock source,
Kojto	90:cb3d968589d8	993	* the RTC cannot be used in STOP and STANDBY modes.
Kojto	90:cb3d968589d8	994	* @note The system must always be configured so as to get a PCLK frequency greater than or
Kojto	90:cb3d968589d8	995	* equal to the RTCCLK frequency for a proper operation of the RTC.
Kojto	90:cb3d968589d8	996	*/
Kojto	90:cb3d968589d8	997	#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) \
Kojto	90:cb3d968589d8	998	MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (uint32_t)(__RTCCLKSource__))
Kojto	90:cb3d968589d8	999
Kojto	90:cb3d968589d8	1000	/** @brief Macro to get the RTC clock source.
Kojto	90:cb3d968589d8	1001	* @retval The clock source can be one of the following values:
Kojto	90:cb3d968589d8	1002	* @arg RCC_RTCCLKSOURCE_NONE: No clock selected as RTC clock
Kojto	90:cb3d968589d8	1003	* @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock
Kojto	90:cb3d968589d8	1004	* @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock
Kojto	90:cb3d968589d8	1005	* @arg RCC_RTCCLKSOURCE_HSE_DIV32: HSE clock divided by 32 selected as RTC clock
Kojto	90:cb3d968589d8	1006	*/
Kojto	90:cb3d968589d8	1007	#define __HAL_RCC_GET_RTC_SOURCE() ((uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL)))
Kojto	90:cb3d968589d8	1008	/**
Kojto	90:cb3d968589d8	1009	* @}
Kojto	90:cb3d968589d8	1010	*/
Kojto	90:cb3d968589d8	1011
Kojto	90:cb3d968589d8	1012	/** @defgroup RCC_Force_Release_Backup RCC Force Release Backup
Kojto	90:cb3d968589d8	1013	* @{
Kojto	90:cb3d968589d8	1014	*/
Kojto	90:cb3d968589d8	1015
Kojto	90:cb3d968589d8	1016	/** @brief Macro to force or release the Backup domain reset.
Kojto	90:cb3d968589d8	1017	* @note These macros reset the RTC peripheral (including the backup registers)
Kojto	90:cb3d968589d8	1018	* and the RTC clock source selection in RCC_CSR register.
Kojto	90:cb3d968589d8	1019	* @note The BKPSRAM is not affected by this reset.
Kojto	90:cb3d968589d8	1020	*/
Kojto	90:cb3d968589d8	1021	#define __HAL_RCC_BACKUPRESET_FORCE() SET_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto	90:cb3d968589d8	1022	#define __HAL_RCC_BACKUPRESET_RELEASE() CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST)
Kojto	90:cb3d968589d8	1023	/**
Kojto	90:cb3d968589d8	1024	* @}
Kojto	90:cb3d968589d8	1025	*/
Kojto	90:cb3d968589d8	1026
Kojto	90:cb3d968589d8	1027	/** @defgroup RCC_PLL_Configuration RCC PLL Configuration
Kojto	90:cb3d968589d8	1028	* @{
Kojto	90:cb3d968589d8	1029	*/
Kojto	90:cb3d968589d8	1030
Kojto	90:cb3d968589d8	1031	/** @brief Macro to enable or disable the PLL.
Kojto	90:cb3d968589d8	1032	* @note After enabling the PLL, the application software should wait on
Kojto	90:cb3d968589d8	1033	* PLLRDY flag to be set indicating that PLL clock is stable and can
Kojto	90:cb3d968589d8	1034	* be used as system clock source.
Kojto	90:cb3d968589d8	1035	* @note The PLL can not be disabled if it is used as system clock source
Kojto	90:cb3d968589d8	1036	* @note The PLL is disabled by hardware when entering STOP and STANDBY modes.
Kojto	90:cb3d968589d8	1037	*/
Kojto	90:cb3d968589d8	1038	#define __HAL_RCC_PLL_ENABLE() SET_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	90:cb3d968589d8	1039	#define __HAL_RCC_PLL_DISABLE() CLEAR_BIT(RCC->CR, RCC_CR_PLLON)
Kojto	90:cb3d968589d8	1040
Kojto	90:cb3d968589d8	1041	/** @brief Macro to configure the PLL clock source, multiplication and division factors.
Kojto	90:cb3d968589d8	1042	* @note This macro must be used only when the PLL is disabled.
Kojto	90:cb3d968589d8	1043	*
Kojto	90:cb3d968589d8	1044	* @param __RCC_PLLSource__: specifies the PLL entry clock source.
Kojto	90:cb3d968589d8	1045	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1046	* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
Kojto	90:cb3d968589d8	1047	* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
Kojto	90:cb3d968589d8	1048	* @param __PREDIV__: specifies the predivider factor for PLL VCO input clock
Kojto	90:cb3d968589d8	1049	* This parameter must be a number between RCC_PREDIV_DIV1 and RCC_PREDIV_DIV16.
Kojto	90:cb3d968589d8	1050	* @param __PLLMUL__: specifies the multiplication factor for PLL VCO input clock
Kojto	90:cb3d968589d8	1051	* This parameter must be a number between RCC_PLL_MUL2 and RCC_PLL_MUL16.
Kojto	90:cb3d968589d8	1052	*
Kojto	90:cb3d968589d8	1053	*/
Kojto	90:cb3d968589d8	1054	#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__ , __PREDIV__, __PLLMUL__) \
Kojto	90:cb3d968589d8	1055	do { \
Kojto	90:cb3d968589d8	1056	MODIFY_REG(RCC->CFGR2, RCC_CFGR2_PREDIV, (__PREDIV__)); \
Kojto	90:cb3d968589d8	1057	MODIFY_REG(RCC->CFGR, RCC_CFGR_PLLMUL \| RCC_CFGR_PLLSRC, (uint32_t)((__PLLMUL__)\|(__RCC_PLLSource__))); \
Kojto	90:cb3d968589d8	1058	} while(0)
Kojto	90:cb3d968589d8	1059	/**
Kojto	90:cb3d968589d8	1060	* @}
Kojto	90:cb3d968589d8	1061	*/
Kojto	90:cb3d968589d8	1062
Kojto	90:cb3d968589d8	1063	/** @defgroup RCC_Get_Clock_source RCC Get Clock source
Kojto	90:cb3d968589d8	1064	* @{
Kojto	90:cb3d968589d8	1065	*/
Kojto	90:cb3d968589d8	1066
Kojto	90:cb3d968589d8	1067	/** @brief Macro to get the clock source used as system clock.
Kojto	90:cb3d968589d8	1068	* @retval The clock source used as system clock.
Kojto	90:cb3d968589d8	1069	* The returned value can be one of the following value:
Kojto	90:cb3d968589d8	1070	* @arg RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock
Kojto	90:cb3d968589d8	1071	* @arg RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock
Kojto	90:cb3d968589d8	1072	* @arg RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock
Kojto	90:cb3d968589d8	1073	*/
Kojto	90:cb3d968589d8	1074	#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS)))
Kojto	90:cb3d968589d8	1075
Kojto	90:cb3d968589d8	1076	/** @brief Macro to get the oscillator used as PLL clock source.
Kojto	90:cb3d968589d8	1077	* @retval The oscillator used as PLL clock source. The returned value can be one
Kojto	90:cb3d968589d8	1078	* of the following:
Kojto	90:cb3d968589d8	1079	* - RCC_PLLSOURCE_HSI: HSI oscillator is used as PLL clock source.
Kojto	90:cb3d968589d8	1080	* - RCC_PLLSOURCE_HSE: HSE oscillator is used as PLL clock source.
Kojto	90:cb3d968589d8	1081	*/
Kojto	90:cb3d968589d8	1082	#define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
Kojto	90:cb3d968589d8	1083	/**
Kojto	90:cb3d968589d8	1084	* @}
Kojto	90:cb3d968589d8	1085	*/
Kojto	90:cb3d968589d8	1086
Kojto	90:cb3d968589d8	1087	/** @defgroup RCC_Flags_Interrupts_Management RCC Flags Interrupts Management
Kojto	90:cb3d968589d8	1088	* @brief macros to manage the specified RCC Flags and interrupts.
Kojto	90:cb3d968589d8	1089	* @{
Kojto	90:cb3d968589d8	1090	*/
Kojto	90:cb3d968589d8	1091
Kojto	90:cb3d968589d8	1092	/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to enable
Kojto	90:cb3d968589d8	1093	* the selected interrupts.).
Kojto	90:cb3d968589d8	1094	* @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
Kojto	90:cb3d968589d8	1095	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1096	* @arg RCC_IT_LSIRDY: LSI ready interrupt enable
Kojto	90:cb3d968589d8	1097	* @arg RCC_IT_LSERDY: LSE ready interrupt enable
Kojto	90:cb3d968589d8	1098	* @arg RCC_IT_HSIRDY: HSI ready interrupt enable
Kojto	90:cb3d968589d8	1099	* @arg RCC_IT_HSERDY: HSE ready interrupt enable
Kojto	90:cb3d968589d8	1100	* @arg RCC_IT_PLLRDY: PLL ready interrupt enable
Kojto	90:cb3d968589d8	1101	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto	90:cb3d968589d8	1102	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto	90:cb3d968589d8	1103	*/
Kojto	90:cb3d968589d8	1104	#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) ((__IO uint8_t )RCC_CIR_BYTE1_ADDRESS \|= (__INTERRUPT__))
Kojto	90:cb3d968589d8	1105
Kojto	90:cb3d968589d8	1106	/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[12:8] bits to disable
Kojto	90:cb3d968589d8	1107	* the selected interrupts.).
Kojto	90:cb3d968589d8	1108	* @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
Kojto	90:cb3d968589d8	1109	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1110	* @arg RCC_IT_LSIRDY: LSI ready interrupt enable
Kojto	90:cb3d968589d8	1111	* @arg RCC_IT_LSERDY: LSE ready interrupt enable
Kojto	90:cb3d968589d8	1112	* @arg RCC_IT_HSIRDY: HSI ready interrupt enable
Kojto	90:cb3d968589d8	1113	* @arg RCC_IT_HSERDY: HSE ready interrupt enable
Kojto	90:cb3d968589d8	1114	* @arg RCC_IT_PLLRDY: PLL ready interrupt enable
Kojto	90:cb3d968589d8	1115	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt enable
Kojto	90:cb3d968589d8	1116	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt enable (only applicable to STM32F0X2 USB devices)
Kojto	90:cb3d968589d8	1117	*/
Kojto	90:cb3d968589d8	1118	#define __HAL_RCC_DISABLE_IT(__INTERRUPT__) ((__IO uint8_t )RCC_CIR_BYTE1_ADDRESS &= ~(__INTERRUPT__))
Kojto	90:cb3d968589d8	1119
Kojto	90:cb3d968589d8	1120	/** @brief Clear the RCC's interrupt pending bits ( Perform Byte access to RCC_CIR[23:16]
Kojto	90:cb3d968589d8	1121	* bits to clear the selected interrupt pending bits.
Kojto	90:cb3d968589d8	1122	* @param __IT__: specifies the interrupt pending bit to clear.
Kojto	90:cb3d968589d8	1123	* This parameter can be any combination of the following values:
Kojto	90:cb3d968589d8	1124	* @arg RCC_IT_LSIRDY: LSI ready interrupt clear
Kojto	90:cb3d968589d8	1125	* @arg RCC_IT_LSERDY: LSE ready interrupt clear
Kojto	90:cb3d968589d8	1126	* @arg RCC_IT_HSIRDY: HSI ready interrupt clear
Kojto	90:cb3d968589d8	1127	* @arg RCC_IT_HSERDY: HSE ready interrupt clear
Kojto	90:cb3d968589d8	1128	* @arg RCC_IT_PLLRDY: PLL ready interrupt clear
Kojto	90:cb3d968589d8	1129	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt clear
Kojto	90:cb3d968589d8	1130	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt clear (only applicable to STM32F0X2 USB devices)
Kojto	90:cb3d968589d8	1131	* @arg RCC_IT_CSS: Clock Security System interrupt clear
Kojto	90:cb3d968589d8	1132	*/
Kojto	90:cb3d968589d8	1133	#define __HAL_RCC_CLEAR_IT(__IT__) ((__IO uint8_t )RCC_CIR_BYTE2_ADDRESS = (__IT__))
Kojto	90:cb3d968589d8	1134
Kojto	90:cb3d968589d8	1135	/** @brief Check the RCC's interrupt has occurred or not.
Kojto	90:cb3d968589d8	1136	* @param __IT__: specifies the RCC interrupt source to check.
Kojto	90:cb3d968589d8	1137	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1138	* @arg RCC_IT_LSIRDY: LSI ready interrupt flag
Kojto	90:cb3d968589d8	1139	* @arg RCC_IT_LSERDY: LSE ready interrupt flag
Kojto	90:cb3d968589d8	1140	* @arg RCC_IT_HSIRDY: HSI ready interrupt flag
Kojto	90:cb3d968589d8	1141	* @arg RCC_IT_HSERDY: HSE ready interrupt flag
Kojto	90:cb3d968589d8	1142	* @arg RCC_IT_PLLRDY: PLL ready interrupt flag
Kojto	90:cb3d968589d8	1143	* @arg RCC_IT_HSI14RDY: HSI14 ready interrupt flag
Kojto	90:cb3d968589d8	1144	* @arg RCC_IT_HSI48RDY: HSI48 ready interrupt flag (only applicable to STM32F0X2 USB devices)
Kojto	90:cb3d968589d8	1145	* @arg RCC_IT_CSS: Clock Security System interrupt flag
Kojto	90:cb3d968589d8	1146	* @retval The new state of __IT__ (TRUE or FALSE).
Kojto	90:cb3d968589d8	1147	*/
Kojto	90:cb3d968589d8	1148	#define __HAL_RCC_GET_IT(__IT__) ((RCC->CIR & (__IT__)) == (__IT__))
Kojto	90:cb3d968589d8	1149
Kojto	90:cb3d968589d8	1150	/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_OBLRST, RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
Kojto	90:cb3d968589d8	1151	* RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
Kojto	90:cb3d968589d8	1152	*/
Kojto	90:cb3d968589d8	1153	#define __HAL_RCC_CLEAR_RESET_FLAGS() SET_BIT(RCC->CSR, RCC_CSR_RMVF)
Kojto	90:cb3d968589d8	1154
Kojto	90:cb3d968589d8	1155	/** @brief Check RCC flag is set or not.
Kojto	90:cb3d968589d8	1156	* @param __FLAG__: specifies the flag to check.
Kojto	90:cb3d968589d8	1157	* This parameter can be one of the following values:
Kojto	90:cb3d968589d8	1158	* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
Kojto	90:cb3d968589d8	1159	* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
Kojto	90:cb3d968589d8	1160	* @arg RCC_FLAG_PLLRDY: PLL clock ready
Kojto	90:cb3d968589d8	1161	* @arg RCC_FLAG_HSI14RDY: HSI14 oscillator clock ready
Kojto	90:cb3d968589d8	1162	* @arg RCC_FLAG_HSI48RDY: HSI48 oscillator clock ready (only applicable to STM32F0X2 USB devices)
Kojto	90:cb3d968589d8	1163	* @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
Kojto	90:cb3d968589d8	1164	* @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
Kojto	90:cb3d968589d8	1165	* @arg RCC_FLAG_OBLRST: Option Byte Load reset
Kojto	90:cb3d968589d8	1166	* @arg RCC_FLAG_PINRST: Pin reset
Kojto	90:cb3d968589d8	1167	* @arg RCC_FLAG_PORRST: POR/PDR reset
Kojto	90:cb3d968589d8	1168	* @arg RCC_FLAG_SFTRST: Software reset
Kojto	90:cb3d968589d8	1169	* @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
Kojto	90:cb3d968589d8	1170	* @arg RCC_FLAG_WWDGRST: Window Watchdog reset
Kojto	90:cb3d968589d8	1171	* @arg RCC_FLAG_LPWRRST: Low Power reset
Kojto	90:cb3d968589d8	1172	* @retval The new state of __FLAG__ (TRUE or FALSE).
Kojto	90:cb3d968589d8	1173	*/
Kojto	90:cb3d968589d8	1174	#define RCC_FLAG_MASK ((uint8_t)0x1F)
Kojto	90:cb3d968589d8	1175	#define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5) == CR_REG_INDEX)? RCC->CR : \
Kojto	90:cb3d968589d8	1176	(((__FLAG__) >> 5) == CR2_REG_INDEX)? RCC->CR2 : \
Kojto	90:cb3d968589d8	1177	(((__FLAG__) >> 5) == BDCR_REG_INDEX) ? RCC->BDCR : \
Kojto	90:cb3d968589d8	1178	RCC->CSR) & ((uint32_t)1 << ((__FLAG__) & RCC_FLAG_MASK)))
Kojto	90:cb3d968589d8	1179
Kojto	90:cb3d968589d8	1180
Kojto	90:cb3d968589d8	1181
Kojto	90:cb3d968589d8	1182	/**
Kojto	90:cb3d968589d8	1183	* @}
Kojto	90:cb3d968589d8	1184	*/
Kojto	90:cb3d968589d8	1185
Kojto	90:cb3d968589d8	1186	/**
Kojto	90:cb3d968589d8	1187	* @}
Kojto	90:cb3d968589d8	1188	*/
Kojto	90:cb3d968589d8	1189
Kojto	90:cb3d968589d8	1190	/* Include RCC HAL Extension module */
Kojto	90:cb3d968589d8	1191	#include "stm32f0xx_hal_rcc_ex.h"
Kojto	90:cb3d968589d8	1192
Kojto	90:cb3d968589d8	1193	/* Exported functions --------------------------------------------------------*/
Kojto	90:cb3d968589d8	1194
Kojto	90:cb3d968589d8	1195	/** @addtogroup RCC_Exported_Functions
Kojto	90:cb3d968589d8	1196	* @{
Kojto	90:cb3d968589d8	1197	*/
Kojto	90:cb3d968589d8	1198
Kojto	90:cb3d968589d8	1199	/** @addtogroup RCC_Exported_Functions_Group1
Kojto	90:cb3d968589d8	1200	* @{
Kojto	90:cb3d968589d8	1201	*/
Kojto	90:cb3d968589d8	1202
Kojto	90:cb3d968589d8	1203	/* Initialization and de-initialization functions ***************************/
Kojto	90:cb3d968589d8	1204	void HAL_RCC_DeInit(void);
Kojto	90:cb3d968589d8	1205	HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	90:cb3d968589d8	1206	HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
Kojto	90:cb3d968589d8	1207
Kojto	90:cb3d968589d8	1208	/**
Kojto	90:cb3d968589d8	1209	* @}
Kojto	90:cb3d968589d8	1210	*/
Kojto	90:cb3d968589d8	1211
Kojto	90:cb3d968589d8	1212	/** @addtogroup RCC_Exported_Functions_Group2
Kojto	90:cb3d968589d8	1213	* @{
Kojto	90:cb3d968589d8	1214	*/
Kojto	90:cb3d968589d8	1215
Kojto	90:cb3d968589d8	1216	/* Peripheral Control functions *********************************************/
Kojto	90:cb3d968589d8	1217	void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
Kojto	90:cb3d968589d8	1218	void HAL_RCC_EnableCSS(void);
Kojto	90:cb3d968589d8	1219	void HAL_RCC_DisableCSS(void);
Kojto	90:cb3d968589d8	1220	uint32_t HAL_RCC_GetSysClockFreq(void);
Kojto	90:cb3d968589d8	1221	uint32_t HAL_RCC_GetHCLKFreq(void);
Kojto	90:cb3d968589d8	1222	uint32_t HAL_RCC_GetPCLK1Freq(void);
Kojto	90:cb3d968589d8	1223	void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
Kojto	90:cb3d968589d8	1224	void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef RCC_ClkInitStruct, uint32_t pFLatency);
Kojto	90:cb3d968589d8	1225
Kojto	90:cb3d968589d8	1226	/* CSS NMI IRQ handler */
Kojto	90:cb3d968589d8	1227	void HAL_RCC_NMI_IRQHandler(void);
Kojto	90:cb3d968589d8	1228
Kojto	90:cb3d968589d8	1229	/* User Callbacks in non blocking mode (IT mode) */
Kojto	90:cb3d968589d8	1230	void HAL_RCC_CCSCallback(void);
Kojto	90:cb3d968589d8	1231
Kojto	90:cb3d968589d8	1232	/**
Kojto	90:cb3d968589d8	1233	* @}
Kojto	90:cb3d968589d8	1234	*/
Kojto	90:cb3d968589d8	1235
Kojto	90:cb3d968589d8	1236	/**
Kojto	90:cb3d968589d8	1237	* @}
Kojto	90:cb3d968589d8	1238	*/
Kojto	90:cb3d968589d8	1239
Kojto	90:cb3d968589d8	1240	/**
Kojto	90:cb3d968589d8	1241	* @}
Kojto	90:cb3d968589d8	1242	*/
Kojto	90:cb3d968589d8	1243
Kojto	90:cb3d968589d8	1244	/**
Kojto	90:cb3d968589d8	1245	* @}
Kojto	90:cb3d968589d8	1246	*/
Kojto	90:cb3d968589d8	1247
Kojto	90:cb3d968589d8	1248	#ifdef __cplusplus
Kojto	90:cb3d968589d8	1249	}
Kojto	90:cb3d968589d8	1250	#endif
Kojto	90:cb3d968589d8	1251
Kojto	90:cb3d968589d8	1252	#endif /* __STM32F0xx_HAL_RCC_H */
Kojto	90:cb3d968589d8	1253
Kojto	90:cb3d968589d8	1254	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/
Kojto	90:cb3d968589d8	1255

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Type:	Library
Created:	08 Apr 2015
Imports:	2
Forks:	0
Commits:	98
Dependents:	1
Dependencies:	0
Followers:	1

TARGET_NUCLEO_F030R8/stm32f0xx_hal_rcc.h@97:4298809c7c9e, 2015-04-08 (annotated)

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