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TARGET_LPC4337/TARGET_NXP/TARGET_LPC43XX/PeripheralNames.h@97:4298809c7c9e, 2015-04-08 (annotated)
- Committer:
- filartrix
- Date:
- Wed Apr 08 14:12:53 2015 +0000
- Revision:
- 97:4298809c7c9e
- Parent:
- 89:552587b429a1
First reale BlueNRG module for nucleo 401 board
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
bogdanm | 89:552587b429a1 | 1 | /* mbed Microcontroller Library |
bogdanm | 89:552587b429a1 | 2 | * Copyright (c) 2006-2013 ARM Limited |
bogdanm | 89:552587b429a1 | 3 | * |
bogdanm | 89:552587b429a1 | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
bogdanm | 89:552587b429a1 | 5 | * you may not use this file except in compliance with the License. |
bogdanm | 89:552587b429a1 | 6 | * You may obtain a copy of the License at |
bogdanm | 89:552587b429a1 | 7 | * |
bogdanm | 89:552587b429a1 | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
bogdanm | 89:552587b429a1 | 9 | * |
bogdanm | 89:552587b429a1 | 10 | * Unless required by applicable law or agreed to in writing, software |
bogdanm | 89:552587b429a1 | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
bogdanm | 89:552587b429a1 | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
bogdanm | 89:552587b429a1 | 13 | * See the License for the specific language governing permissions and |
bogdanm | 89:552587b429a1 | 14 | * limitations under the License. |
bogdanm | 89:552587b429a1 | 15 | */ |
bogdanm | 89:552587b429a1 | 16 | #ifndef MBED_PERIPHERALNAMES_H |
bogdanm | 89:552587b429a1 | 17 | #define MBED_PERIPHERALNAMES_H |
bogdanm | 89:552587b429a1 | 18 | |
bogdanm | 89:552587b429a1 | 19 | #include "cmsis.h" |
bogdanm | 89:552587b429a1 | 20 | |
bogdanm | 89:552587b429a1 | 21 | #ifdef __cplusplus |
bogdanm | 89:552587b429a1 | 22 | extern "C" { |
bogdanm | 89:552587b429a1 | 23 | #endif |
bogdanm | 89:552587b429a1 | 24 | |
bogdanm | 89:552587b429a1 | 25 | typedef enum { |
bogdanm | 89:552587b429a1 | 26 | UART_0 = (int)LPC_USART0_BASE, |
bogdanm | 89:552587b429a1 | 27 | UART_1 = (int)LPC_UART1_BASE, |
bogdanm | 89:552587b429a1 | 28 | UART_2 = (int)LPC_USART2_BASE, |
bogdanm | 89:552587b429a1 | 29 | UART_3 = (int)LPC_USART3_BASE |
bogdanm | 89:552587b429a1 | 30 | } UARTName; |
bogdanm | 89:552587b429a1 | 31 | |
bogdanm | 89:552587b429a1 | 32 | typedef enum { |
bogdanm | 89:552587b429a1 | 33 | ADC0_0 = 0, |
bogdanm | 89:552587b429a1 | 34 | ADC0_1, |
bogdanm | 89:552587b429a1 | 35 | ADC0_2, |
bogdanm | 89:552587b429a1 | 36 | ADC0_3, |
bogdanm | 89:552587b429a1 | 37 | ADC0_4, |
bogdanm | 89:552587b429a1 | 38 | ADC0_5, |
bogdanm | 89:552587b429a1 | 39 | ADC0_6, |
bogdanm | 89:552587b429a1 | 40 | ADC0_7, |
bogdanm | 89:552587b429a1 | 41 | ADC1_0, |
bogdanm | 89:552587b429a1 | 42 | ADC1_1, |
bogdanm | 89:552587b429a1 | 43 | ADC1_2, |
bogdanm | 89:552587b429a1 | 44 | ADC1_3, |
bogdanm | 89:552587b429a1 | 45 | ADC1_4, |
bogdanm | 89:552587b429a1 | 46 | ADC1_5, |
bogdanm | 89:552587b429a1 | 47 | ADC1_6, |
bogdanm | 89:552587b429a1 | 48 | ADC1_7 |
bogdanm | 89:552587b429a1 | 49 | } ADCName; |
bogdanm | 89:552587b429a1 | 50 | |
bogdanm | 89:552587b429a1 | 51 | typedef enum { |
bogdanm | 89:552587b429a1 | 52 | DAC_0 = 0 |
bogdanm | 89:552587b429a1 | 53 | } DACName; |
bogdanm | 89:552587b429a1 | 54 | |
bogdanm | 89:552587b429a1 | 55 | typedef enum { |
bogdanm | 89:552587b429a1 | 56 | SPI_0 = (int)LPC_SSP0_BASE, |
bogdanm | 89:552587b429a1 | 57 | SPI_1 = (int)LPC_SSP1_BASE |
bogdanm | 89:552587b429a1 | 58 | } SPIName; |
bogdanm | 89:552587b429a1 | 59 | |
bogdanm | 89:552587b429a1 | 60 | typedef enum { |
bogdanm | 89:552587b429a1 | 61 | I2C_0 = (int)LPC_I2C0_BASE, |
bogdanm | 89:552587b429a1 | 62 | I2C_1 = (int)LPC_I2C1_BASE |
bogdanm | 89:552587b429a1 | 63 | } I2CName; |
bogdanm | 89:552587b429a1 | 64 | |
bogdanm | 89:552587b429a1 | 65 | typedef enum { |
bogdanm | 89:552587b429a1 | 66 | PWM_0, |
bogdanm | 89:552587b429a1 | 67 | PWM_1, |
bogdanm | 89:552587b429a1 | 68 | PWM_2, |
bogdanm | 89:552587b429a1 | 69 | PWM_3, |
bogdanm | 89:552587b429a1 | 70 | PWM_4, |
bogdanm | 89:552587b429a1 | 71 | PWM_5, |
bogdanm | 89:552587b429a1 | 72 | PWM_6, |
bogdanm | 89:552587b429a1 | 73 | PWM_7, |
bogdanm | 89:552587b429a1 | 74 | PWM_8, |
bogdanm | 89:552587b429a1 | 75 | PWM_9, |
bogdanm | 89:552587b429a1 | 76 | PWM_10, |
bogdanm | 89:552587b429a1 | 77 | PWM_11, |
bogdanm | 89:552587b429a1 | 78 | PWM_12, |
bogdanm | 89:552587b429a1 | 79 | PWM_13, |
bogdanm | 89:552587b429a1 | 80 | PWM_14, |
bogdanm | 89:552587b429a1 | 81 | PWM_15 |
bogdanm | 89:552587b429a1 | 82 | } PWMName; |
bogdanm | 89:552587b429a1 | 83 | |
bogdanm | 89:552587b429a1 | 84 | typedef enum { |
bogdanm | 89:552587b429a1 | 85 | CAN_0 = (int)LPC_C_CAN0_BASE, |
bogdanm | 89:552587b429a1 | 86 | CAN_1 = (int)LPC_C_CAN1_BASE |
bogdanm | 89:552587b429a1 | 87 | } CANName; |
bogdanm | 89:552587b429a1 | 88 | |
bogdanm | 89:552587b429a1 | 89 | #define STDIO_UART_TX USBTX |
bogdanm | 89:552587b429a1 | 90 | #define STDIO_UART_RX USBRX |
bogdanm | 89:552587b429a1 | 91 | #define STDIO_UART UART_2 |
bogdanm | 89:552587b429a1 | 92 | |
bogdanm | 89:552587b429a1 | 93 | // Default peripherals |
bogdanm | 89:552587b429a1 | 94 | #define MBED_SPI0 SPI0_MOSI, SPI0_MISO, SPI0_SCK, SPI0_SSEL |
bogdanm | 89:552587b429a1 | 95 | #define MBED_SPI1 SPI1_MOSI, SPI1_MISO, SPI1_SCK, SPI1_SSEL |
bogdanm | 89:552587b429a1 | 96 | |
bogdanm | 89:552587b429a1 | 97 | #define MBED_UART0 UART0_TX, UART0_RX |
bogdanm | 89:552587b429a1 | 98 | #define MBED_UART1 UART1_TX, UART1_RX |
bogdanm | 89:552587b429a1 | 99 | #define MBED_UART2 UART2_TX, UART2_RX |
bogdanm | 89:552587b429a1 | 100 | #define MBED_UART3 UART3_TX, UART3_RX |
bogdanm | 89:552587b429a1 | 101 | #define MBED_UARTUSB USBTX, USBRX |
bogdanm | 89:552587b429a1 | 102 | |
bogdanm | 89:552587b429a1 | 103 | #define COM1 MBED_UART0 |
bogdanm | 89:552587b429a1 | 104 | #define COM2 MBED_UART1 |
bogdanm | 89:552587b429a1 | 105 | #define COM3 MBED_UART2 |
bogdanm | 89:552587b429a1 | 106 | #define COM4 MBED_UART3 |
bogdanm | 89:552587b429a1 | 107 | |
bogdanm | 89:552587b429a1 | 108 | #define MBED_I2C0 I2C0_SDA, I2C0_SCL |
bogdanm | 89:552587b429a1 | 109 | #define MBED_I2C1 I2C1_SDA, I2C1_SCL |
bogdanm | 89:552587b429a1 | 110 | |
bogdanm | 89:552587b429a1 | 111 | #define MBED_CAN0 p30, p29 |
bogdanm | 89:552587b429a1 | 112 | |
bogdanm | 89:552587b429a1 | 113 | #define MBED_ANALOGOUT0 DAC0 |
bogdanm | 89:552587b429a1 | 114 | |
bogdanm | 89:552587b429a1 | 115 | #define MBED_ANALOGIN0 ADC0 |
bogdanm | 89:552587b429a1 | 116 | #define MBED_ANALOGIN1 ADC1 |
bogdanm | 89:552587b429a1 | 117 | #define MBED_ANALOGIN2 ADC2 |
bogdanm | 89:552587b429a1 | 118 | #define MBED_ANALOGIN3 ADC3 |
bogdanm | 89:552587b429a1 | 119 | #define MBED_ANALOGIN4 ADC4 |
bogdanm | 89:552587b429a1 | 120 | #define MBED_ANALOGIN5 ADC5 |
bogdanm | 89:552587b429a1 | 121 | #define MBED_ANALOGIN6 ADC6 |
bogdanm | 89:552587b429a1 | 122 | #define MBED_ANALOGIN7 ADC7 |
bogdanm | 89:552587b429a1 | 123 | |
bogdanm | 89:552587b429a1 | 124 | #define MBED_PWMOUT0 p26 |
bogdanm | 89:552587b429a1 | 125 | #define MBED_PWMOUT1 p25 |
bogdanm | 89:552587b429a1 | 126 | #define MBED_PWMOUT2 p24 |
bogdanm | 89:552587b429a1 | 127 | #define MBED_PWMOUT3 p23 |
bogdanm | 89:552587b429a1 | 128 | #define MBED_PWMOUT4 p22 |
bogdanm | 89:552587b429a1 | 129 | #define MBED_PWMOUT5 p21 |
bogdanm | 89:552587b429a1 | 130 | |
bogdanm | 89:552587b429a1 | 131 | #ifdef __cplusplus |
bogdanm | 89:552587b429a1 | 132 | } |
bogdanm | 89:552587b429a1 | 133 | #endif |
bogdanm | 89:552587b429a1 | 134 | |
bogdanm | 89:552587b429a1 | 135 | #endif |