Filippo Casamassima / mbed

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TARGET_LPC2368/core_arm7.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:
filartrix
Date:
Wed Apr 08 14:12:53 2015 +0000
Revision:
97:4298809c7c9e
Parent:
66:9c8f0e3462fb 
First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 66:9c8f0e3462fb 1 /* mbed Microcontroller Library
bogdanm 66:9c8f0e3462fb 2 * Copyright (C) 2008-2009 ARM Limited. All rights reserved.
bogdanm 66:9c8f0e3462fb 3 *
bogdanm 66:9c8f0e3462fb 4 * ARM7 version of CMSIS-like functionality - not advised for use outside mbed!
bogdanm 66:9c8f0e3462fb 5 * based on core_cm3.h, V1.20
bogdanm 66:9c8f0e3462fb 6 */
bogdanm 66:9c8f0e3462fb 7
bogdanm 66:9c8f0e3462fb 8 #ifndef __ARM7_CORE_H__
bogdanm 66:9c8f0e3462fb 9 #define __ARM7_CORE_H__
bogdanm 66:9c8f0e3462fb 10
bogdanm 66:9c8f0e3462fb 11 #include "vector_defns.h"
bogdanm 66:9c8f0e3462fb 12
bogdanm 66:9c8f0e3462fb 13 #ifdef __cplusplus
bogdanm 66:9c8f0e3462fb 14 extern "C" {
bogdanm 66:9c8f0e3462fb 15 #endif
bogdanm 66:9c8f0e3462fb 16
bogdanm 66:9c8f0e3462fb 17 #define __CM3_CMSIS_VERSION_MAIN (0x01) /*!< [31:16] CMSIS HAL main version */
bogdanm 66:9c8f0e3462fb 18 #define __CM3_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
bogdanm 66:9c8f0e3462fb 19 #define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number */
bogdanm 66:9c8f0e3462fb 20
bogdanm 66:9c8f0e3462fb 21 #define __CORTEX_M (0x03) /*!< Cortex core */
bogdanm 66:9c8f0e3462fb 22
bogdanm 66:9c8f0e3462fb 23 /**
bogdanm 66:9c8f0e3462fb 24 * Lint configuration \n
bogdanm 66:9c8f0e3462fb 25 * ----------------------- \n
bogdanm 66:9c8f0e3462fb 26 *
bogdanm 66:9c8f0e3462fb 27 * The following Lint messages will be suppressed and not shown: \n
bogdanm 66:9c8f0e3462fb 28 * \n
bogdanm 66:9c8f0e3462fb 29 * --- Error 10: --- \n
bogdanm 66:9c8f0e3462fb 30 * register uint32_t __regBasePri __asm("basepri"); \n
bogdanm 66:9c8f0e3462fb 31 * Error 10: Expecting ';' \n
bogdanm 66:9c8f0e3462fb 32 * \n
bogdanm 66:9c8f0e3462fb 33 * --- Error 530: --- \n
bogdanm 66:9c8f0e3462fb 34 * return(__regBasePri); \n
bogdanm 66:9c8f0e3462fb 35 * Warning 530: Symbol '__regBasePri' (line 264) not initialized \n
bogdanm 66:9c8f0e3462fb 36 * \n
bogdanm 66:9c8f0e3462fb 37 * --- Error 550: --- \n
bogdanm 66:9c8f0e3462fb 38 * __regBasePri = (basePri & 0x1ff); \n
bogdanm 66:9c8f0e3462fb 39 * } \n
bogdanm 66:9c8f0e3462fb 40 * Warning 550: Symbol '__regBasePri' (line 271) not accessed \n
bogdanm 66:9c8f0e3462fb 41 * \n
bogdanm 66:9c8f0e3462fb 42 * --- Error 754: --- \n
bogdanm 66:9c8f0e3462fb 43 * uint32_t RESERVED0[24]; \n
bogdanm 66:9c8f0e3462fb 44 * Info 754: local structure member '<some, not used in the HAL>' (line 109, file ./cm3_core.h) not referenced \n
bogdanm 66:9c8f0e3462fb 45 * \n
bogdanm 66:9c8f0e3462fb 46 * --- Error 750: --- \n
bogdanm 66:9c8f0e3462fb 47 * #define __CM3_CORE_H__ \n
bogdanm 66:9c8f0e3462fb 48 * Info 750: local macro '__CM3_CORE_H__' (line 43, file./cm3_core.h) not referenced \n
bogdanm 66:9c8f0e3462fb 49 * \n
bogdanm 66:9c8f0e3462fb 50 * --- Error 528: --- \n
bogdanm 66:9c8f0e3462fb 51 * static __INLINE void NVIC_DisableIRQ(uint32_t IRQn) \n
bogdanm 66:9c8f0e3462fb 52 * Warning 528: Symbol 'NVIC_DisableIRQ(unsigned int)' (line 419, file ./cm3_core.h) not referenced \n
bogdanm 66:9c8f0e3462fb 53 * \n
bogdanm 66:9c8f0e3462fb 54 * --- Error 751: --- \n
bogdanm 66:9c8f0e3462fb 55 * } InterruptType_Type; \n
bogdanm 66:9c8f0e3462fb 56 * Info 751: local typedef 'InterruptType_Type' (line 170, file ./cm3_core.h) not referenced \n
bogdanm 66:9c8f0e3462fb 57 * \n
bogdanm 66:9c8f0e3462fb 58 * \n
bogdanm 66:9c8f0e3462fb 59 * Note: To re-enable a Message, insert a space before 'lint' * \n
bogdanm 66:9c8f0e3462fb 60 *
bogdanm 66:9c8f0e3462fb 61 */
bogdanm 66:9c8f0e3462fb 62
bogdanm 66:9c8f0e3462fb 63 /*lint -save */
bogdanm 66:9c8f0e3462fb 64 /*lint -e10 */
bogdanm 66:9c8f0e3462fb 65 /*lint -e530 */
bogdanm 66:9c8f0e3462fb 66 /*lint -e550 */
bogdanm 66:9c8f0e3462fb 67 /*lint -e754 */
bogdanm 66:9c8f0e3462fb 68 /*lint -e750 */
bogdanm 66:9c8f0e3462fb 69 /*lint -e528 */
bogdanm 66:9c8f0e3462fb 70 /*lint -e751 */
bogdanm 66:9c8f0e3462fb 71
bogdanm 66:9c8f0e3462fb 72 #include <stdint.h> /* Include standard types */
bogdanm 66:9c8f0e3462fb 73
bogdanm 66:9c8f0e3462fb 74 #if defined ( __CC_ARM )
bogdanm 66:9c8f0e3462fb 75 /**
bogdanm 66:9c8f0e3462fb 76 * @brief Return the Main Stack Pointer (current ARM7 stack)
bogdanm 66:9c8f0e3462fb 77 *
bogdanm 66:9c8f0e3462fb 78 * @param none
bogdanm 66:9c8f0e3462fb 79 * @return uint32_t Main Stack Pointer
bogdanm 66:9c8f0e3462fb 80 *
bogdanm 66:9c8f0e3462fb 81 * Return the current value of the MSP (main stack pointer)
bogdanm 66:9c8f0e3462fb 82 * Cortex processor register
bogdanm 66:9c8f0e3462fb 83 */
bogdanm 66:9c8f0e3462fb 84 extern uint32_t __get_MSP(void);
bogdanm 66:9c8f0e3462fb 85 #endif
bogdanm 66:9c8f0e3462fb 86
bogdanm 66:9c8f0e3462fb 87
bogdanm 66:9c8f0e3462fb 88 #if defined (__ICCARM__)
bogdanm 66:9c8f0e3462fb 89 #include <intrinsics.h> /* IAR Intrinsics */
bogdanm 66:9c8f0e3462fb 90 #endif
bogdanm 66:9c8f0e3462fb 91
bogdanm 66:9c8f0e3462fb 92
bogdanm 66:9c8f0e3462fb 93 #ifndef __NVIC_PRIO_BITS
bogdanm 66:9c8f0e3462fb 94 #define __NVIC_PRIO_BITS 4 /*!< standard definition for NVIC Priority Bits */
bogdanm 66:9c8f0e3462fb 95 #endif
bogdanm 66:9c8f0e3462fb 96
bogdanm 66:9c8f0e3462fb 97 typedef struct
bogdanm 66:9c8f0e3462fb 98 {
bogdanm 66:9c8f0e3462fb 99 uint32_t IRQStatus;
bogdanm 66:9c8f0e3462fb 100 uint32_t FIQStatus;
bogdanm 66:9c8f0e3462fb 101 uint32_t RawIntr;
bogdanm 66:9c8f0e3462fb 102 uint32_t IntSelect;
bogdanm 66:9c8f0e3462fb 103 uint32_t IntEnable;
bogdanm 66:9c8f0e3462fb 104 uint32_t IntEnClr;
bogdanm 66:9c8f0e3462fb 105 uint32_t SoftInt;
bogdanm 66:9c8f0e3462fb 106 uint32_t SoftIntClr;
bogdanm 66:9c8f0e3462fb 107 uint32_t Protection;
bogdanm 66:9c8f0e3462fb 108 uint32_t SWPriorityMask;
bogdanm 66:9c8f0e3462fb 109 uint32_t RESERVED0[54];
bogdanm 66:9c8f0e3462fb 110 uint32_t VectAddr[32];
bogdanm 66:9c8f0e3462fb 111 uint32_t RESERVED1[32];
bogdanm 66:9c8f0e3462fb 112 uint32_t VectPriority[32];
bogdanm 66:9c8f0e3462fb 113 uint32_t RESERVED2[800];
bogdanm 66:9c8f0e3462fb 114 uint32_t Address;
bogdanm 66:9c8f0e3462fb 115 } NVIC_TypeDef;
bogdanm 66:9c8f0e3462fb 116
bogdanm 66:9c8f0e3462fb 117 #define NVIC_BASE (0xFFFFF000)
bogdanm 66:9c8f0e3462fb 118 #define NVIC (( NVIC_TypeDef *) NVIC_BASE)
bogdanm 66:9c8f0e3462fb 119
bogdanm 66:9c8f0e3462fb 120
bogdanm 66:9c8f0e3462fb 121
bogdanm 66:9c8f0e3462fb 122 /**
bogdanm 66:9c8f0e3462fb 123 * IO definitions
bogdanm 66:9c8f0e3462fb 124 *
bogdanm 66:9c8f0e3462fb 125 * define access restrictions to peripheral registers
bogdanm 66:9c8f0e3462fb 126 */
bogdanm 66:9c8f0e3462fb 127
bogdanm 66:9c8f0e3462fb 128 #ifdef __cplusplus
bogdanm 66:9c8f0e3462fb 129 #define __I volatile /*!< defines 'read only' permissions */
bogdanm 66:9c8f0e3462fb 130 #else
bogdanm 66:9c8f0e3462fb 131 #define __I volatile const /*!< defines 'read only' permissions */
bogdanm 66:9c8f0e3462fb 132 #endif
bogdanm 66:9c8f0e3462fb 133 #define __O volatile /*!< defines 'write only' permissions */
bogdanm 66:9c8f0e3462fb 134 #define __IO volatile /*!< defines 'read / write' permissions */
bogdanm 66:9c8f0e3462fb 135
bogdanm 66:9c8f0e3462fb 136
bogdanm 66:9c8f0e3462fb 137
bogdanm 66:9c8f0e3462fb 138
bogdanm 66:9c8f0e3462fb 139
bogdanm 66:9c8f0e3462fb 140 #if defined ( __CC_ARM )
bogdanm 66:9c8f0e3462fb 141 #define __ASM __asm /*!< asm keyword for ARM Compiler */
bogdanm 66:9c8f0e3462fb 142 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
bogdanm 66:9c8f0e3462fb 143
bogdanm 66:9c8f0e3462fb 144 #elif defined ( __ICCARM__ )
bogdanm 66:9c8f0e3462fb 145 #define __ASM __asm /*!< asm keyword for IAR Compiler */
bogdanm 66:9c8f0e3462fb 146 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only avaiable in High optimization mode! */
bogdanm 66:9c8f0e3462fb 147
bogdanm 66:9c8f0e3462fb 148 #elif defined ( __GNUC__ )
bogdanm 66:9c8f0e3462fb 149 #define __ASM __asm /*!< asm keyword for GNU Compiler */
bogdanm 66:9c8f0e3462fb 150 #define __INLINE inline /*!< inline keyword for GNU Compiler */
bogdanm 66:9c8f0e3462fb 151
bogdanm 66:9c8f0e3462fb 152 #elif defined ( __TASKING__ )
bogdanm 66:9c8f0e3462fb 153 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
bogdanm 66:9c8f0e3462fb 154 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
bogdanm 66:9c8f0e3462fb 155
bogdanm 66:9c8f0e3462fb 156 #endif
bogdanm 66:9c8f0e3462fb 157
bogdanm 66:9c8f0e3462fb 158
bogdanm 66:9c8f0e3462fb 159 /* ################### Compiler specific Intrinsics ########################### */
bogdanm 66:9c8f0e3462fb 160
bogdanm 66:9c8f0e3462fb 161 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
bogdanm 66:9c8f0e3462fb 162 /* ARM armcc specific functions */
bogdanm 66:9c8f0e3462fb 163
bogdanm 66:9c8f0e3462fb 164 #define __enable_fault_irq __enable_fiq
bogdanm 66:9c8f0e3462fb 165 #define __disable_fault_irq __disable_fiq
bogdanm 66:9c8f0e3462fb 166
bogdanm 66:9c8f0e3462fb 167 #define __NOP __nop
bogdanm 66:9c8f0e3462fb 168 //#define __WFI __wfi
bogdanm 66:9c8f0e3462fb 169 //#define __WFE __wfe
bogdanm 66:9c8f0e3462fb 170 //#define __SEV __sev
bogdanm 66:9c8f0e3462fb 171 //#define __ISB() __isb(0)
bogdanm 66:9c8f0e3462fb 172 //#define __DSB() __dsb(0)
bogdanm 66:9c8f0e3462fb 173 //#define __DMB() __dmb(0)
bogdanm 66:9c8f0e3462fb 174 //#define __REV __rev
bogdanm 66:9c8f0e3462fb 175 //#define __RBIT __rbit
bogdanm 66:9c8f0e3462fb 176 #define __LDREXB(ptr) ((unsigned char ) __ldrex(ptr))
bogdanm 66:9c8f0e3462fb 177 #define __LDREXH(ptr) ((unsigned short) __ldrex(ptr))
bogdanm 66:9c8f0e3462fb 178 #define __LDREXW(ptr) ((unsigned int ) __ldrex(ptr))
bogdanm 66:9c8f0e3462fb 179 #define __STREXB(value, ptr) __strex(value, ptr)
bogdanm 66:9c8f0e3462fb 180 #define __STREXH(value, ptr) __strex(value, ptr)
bogdanm 66:9c8f0e3462fb 181 #define __STREXW(value, ptr) __strex(value, ptr)
bogdanm 66:9c8f0e3462fb 182
bogdanm 66:9c8f0e3462fb 183 #define __disable_irq() unsigned tmp_IntEnable = LPC_VIC->IntEnable; \
bogdanm 66:9c8f0e3462fb 184 LPC_VIC->IntEnClr = 0xffffffff
bogdanm 66:9c8f0e3462fb 185
bogdanm 66:9c8f0e3462fb 186 #define __enable_irq() LPC_VIC->IntEnable = tmp_IntEnable
bogdanm 66:9c8f0e3462fb 187
bogdanm 66:9c8f0e3462fb 188 #elif (defined (__ICCARM__)) /*------------------ ICC Compiler -------------------*/
bogdanm 66:9c8f0e3462fb 189
bogdanm 66:9c8f0e3462fb 190 #define __enable_irq __enable_interrupt /*!< global Interrupt enable */
bogdanm 66:9c8f0e3462fb 191 #define __disable_irq __disable_interrupt /*!< global Interrupt disable */
bogdanm 66:9c8f0e3462fb 192 #define __NOP __no_operation() /*!< no operation intrinsic in IAR Compiler */
bogdanm 66:9c8f0e3462fb 193
bogdanm 66:9c8f0e3462fb 194 #elif (defined (__GNUC__)) /*------------------ GNU Compiler ---------------------*/
bogdanm 66:9c8f0e3462fb 195
bogdanm 66:9c8f0e3462fb 196 static __INLINE void __enable_irq() {
bogdanm 66:9c8f0e3462fb 197 unsigned long temp;
bogdanm 66:9c8f0e3462fb 198 __asm__ __volatile__("mrs %0, cpsr\n"
bogdanm 66:9c8f0e3462fb 199 "bic %0, %0, #0x80\n"
bogdanm 66:9c8f0e3462fb 200 "msr cpsr_c, %0"
bogdanm 66:9c8f0e3462fb 201 : "=r" (temp)
bogdanm 66:9c8f0e3462fb 202 :
bogdanm 66:9c8f0e3462fb 203 : "memory");
bogdanm 66:9c8f0e3462fb 204 }
bogdanm 66:9c8f0e3462fb 205
bogdanm 66:9c8f0e3462fb 206 static __INLINE void __disable_irq() {
bogdanm 66:9c8f0e3462fb 207 unsigned long old,temp;
bogdanm 66:9c8f0e3462fb 208 __asm__ __volatile__("mrs %0, cpsr\n"
bogdanm 66:9c8f0e3462fb 209 "orr %1, %0, #0xc0\n"
bogdanm 66:9c8f0e3462fb 210 "msr cpsr_c, %1"
bogdanm 66:9c8f0e3462fb 211 : "=r" (old), "=r" (temp)
bogdanm 66:9c8f0e3462fb 212 :
bogdanm 66:9c8f0e3462fb 213 : "memory");
bogdanm 66:9c8f0e3462fb 214 // return (old & 0x80) == 0;
bogdanm 66:9c8f0e3462fb 215 }
bogdanm 66:9c8f0e3462fb 216
bogdanm 66:9c8f0e3462fb 217 static __INLINE void __NOP() { __ASM volatile ("nop"); }
bogdanm 66:9c8f0e3462fb 218
bogdanm 66:9c8f0e3462fb 219 #elif (defined (__TASKING__)) /*------------------ TASKING Compiler ---------------------*/
bogdanm 66:9c8f0e3462fb 220 /* TASKING carm specific functions */
bogdanm 66:9c8f0e3462fb 221
bogdanm 66:9c8f0e3462fb 222 /*
bogdanm 66:9c8f0e3462fb 223 * The CMSIS functions have been implemented as intrinsics in the compiler.
bogdanm 66:9c8f0e3462fb 224 * Please use "carm -?i" to get an up to date list of all instrinsics,
bogdanm 66:9c8f0e3462fb 225 * Including the CMSIS ones.
bogdanm 66:9c8f0e3462fb 226 */
bogdanm 66:9c8f0e3462fb 227
bogdanm 66:9c8f0e3462fb 228 #endif
bogdanm 66:9c8f0e3462fb 229
bogdanm 66:9c8f0e3462fb 230
bogdanm 66:9c8f0e3462fb 231 /**
bogdanm 66:9c8f0e3462fb 232 * @brief Enable Interrupt in NVIC Interrupt Controller
bogdanm 66:9c8f0e3462fb 233 *
bogdanm 66:9c8f0e3462fb 234 * @param IRQn_Type IRQn specifies the interrupt number
bogdanm 66:9c8f0e3462fb 235 * @return none
bogdanm 66:9c8f0e3462fb 236 *
bogdanm 66:9c8f0e3462fb 237 * Enable a device specific interupt in the NVIC interrupt controller.
bogdanm 66:9c8f0e3462fb 238 * The interrupt number cannot be a negative value.
bogdanm 66:9c8f0e3462fb 239 */
bogdanm 66:9c8f0e3462fb 240 static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
bogdanm 66:9c8f0e3462fb 241 {
bogdanm 66:9c8f0e3462fb 242 NVIC->IntEnable = 1 << (uint32_t)IRQn;
bogdanm 66:9c8f0e3462fb 243 }
bogdanm 66:9c8f0e3462fb 244
bogdanm 66:9c8f0e3462fb 245
bogdanm 66:9c8f0e3462fb 246 /**
bogdanm 66:9c8f0e3462fb 247 * @brief Disable the interrupt line for external interrupt specified
bogdanm 66:9c8f0e3462fb 248 *
bogdanm 66:9c8f0e3462fb 249 * @param IRQn_Type IRQn is the positive number of the external interrupt
bogdanm 66:9c8f0e3462fb 250 * @return none
bogdanm 66:9c8f0e3462fb 251 *
bogdanm 66:9c8f0e3462fb 252 * Disable a device specific interupt in the NVIC interrupt controller.
bogdanm 66:9c8f0e3462fb 253 * The interrupt number cannot be a negative value.
bogdanm 66:9c8f0e3462fb 254 */
bogdanm 66:9c8f0e3462fb 255 static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
bogdanm 66:9c8f0e3462fb 256 {
bogdanm 66:9c8f0e3462fb 257 NVIC->IntEnClr = 1 << (uint32_t)IRQn;
bogdanm 66:9c8f0e3462fb 258 }
bogdanm 66:9c8f0e3462fb 259
bogdanm 66:9c8f0e3462fb 260 static __INLINE uint32_t __get_IPSR(void)
bogdanm 66:9c8f0e3462fb 261 {
bogdanm 66:9c8f0e3462fb 262 unsigned i;
bogdanm 66:9c8f0e3462fb 263
bogdanm 66:9c8f0e3462fb 264 for(i = 0; i < 32; i ++)
bogdanm 66:9c8f0e3462fb 265 if(NVIC->Address == NVIC->VectAddr[i])
bogdanm 66:9c8f0e3462fb 266 return i;
bogdanm 66:9c8f0e3462fb 267 return 1; // 1 is an invalid entry in the interrupt table on LPC2368
bogdanm 66:9c8f0e3462fb 268 }
bogdanm 66:9c8f0e3462fb 269
bogdanm 66:9c8f0e3462fb 270 #ifdef __cplusplus
bogdanm 66:9c8f0e3462fb 271 }
bogdanm 66:9c8f0e3462fb 272 #endif
bogdanm 66:9c8f0e3462fb 273
bogdanm 66:9c8f0e3462fb 274 #endif /* __ARM7_CORE_H__ */
bogdanm 66:9c8f0e3462fb 275
bogdanm 66:9c8f0e3462fb 276 /*lint -restore */