Filippo Casamassima / mbed

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TARGET_LPC1768/LPC17xx.h@97:4298809c7c9e, 2015-04-08 (annotated)

Committer:
filartrix
Date:
Wed Apr 08 14:12:53 2015 +0000
Revision:
97:4298809c7c9e
Parent:
66:9c8f0e3462fb 
First reale BlueNRG module for nucleo 401 board

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 66:9c8f0e3462fb 1 /**************************************************************************//**
bogdanm 66:9c8f0e3462fb 2 * @file LPC17xx.h
bogdanm 66:9c8f0e3462fb 3 * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File for
bogdanm 66:9c8f0e3462fb 4 * NXP LPC17xx Device Series
bogdanm 66:9c8f0e3462fb 5 * @version: V1.09
bogdanm 66:9c8f0e3462fb 6 * @date: 17. March 2010
bogdanm 66:9c8f0e3462fb 7
bogdanm 66:9c8f0e3462fb 8 *
bogdanm 66:9c8f0e3462fb 9 * @note
bogdanm 66:9c8f0e3462fb 10 * Copyright (C) 2009 ARM Limited. All rights reserved.
bogdanm 66:9c8f0e3462fb 11 *
bogdanm 66:9c8f0e3462fb 12 * @par
bogdanm 66:9c8f0e3462fb 13 * ARM Limited (ARM) is supplying this software for use with Cortex-M
bogdanm 66:9c8f0e3462fb 14 * processor based microcontrollers. This file can be freely distributed
bogdanm 66:9c8f0e3462fb 15 * within development tools that are supporting such ARM based processors.
bogdanm 66:9c8f0e3462fb 16 *
bogdanm 66:9c8f0e3462fb 17 * @par
bogdanm 66:9c8f0e3462fb 18 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
bogdanm 66:9c8f0e3462fb 19 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
bogdanm 66:9c8f0e3462fb 20 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
bogdanm 66:9c8f0e3462fb 21 * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
bogdanm 66:9c8f0e3462fb 22 * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
bogdanm 66:9c8f0e3462fb 23 *
bogdanm 66:9c8f0e3462fb 24 ******************************************************************************/
bogdanm 66:9c8f0e3462fb 25
bogdanm 66:9c8f0e3462fb 26
bogdanm 66:9c8f0e3462fb 27 #ifndef __LPC17xx_H__
bogdanm 66:9c8f0e3462fb 28 #define __LPC17xx_H__
bogdanm 66:9c8f0e3462fb 29
bogdanm 66:9c8f0e3462fb 30 /*
bogdanm 66:9c8f0e3462fb 31 * ==========================================================================
bogdanm 66:9c8f0e3462fb 32 * ---------- Interrupt Number Definition -----------------------------------
bogdanm 66:9c8f0e3462fb 33 * ==========================================================================
bogdanm 66:9c8f0e3462fb 34 */
bogdanm 66:9c8f0e3462fb 35
bogdanm 66:9c8f0e3462fb 36 typedef enum IRQn
bogdanm 66:9c8f0e3462fb 37 {
bogdanm 66:9c8f0e3462fb 38 /****** Cortex-M3 Processor Exceptions Numbers ***************************************************/
bogdanm 66:9c8f0e3462fb 39 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
bogdanm 66:9c8f0e3462fb 40 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M3 Memory Management Interrupt */
bogdanm 66:9c8f0e3462fb 41 BusFault_IRQn = -11, /*!< 5 Cortex-M3 Bus Fault Interrupt */
bogdanm 66:9c8f0e3462fb 42 UsageFault_IRQn = -10, /*!< 6 Cortex-M3 Usage Fault Interrupt */
bogdanm 66:9c8f0e3462fb 43 SVCall_IRQn = -5, /*!< 11 Cortex-M3 SV Call Interrupt */
bogdanm 66:9c8f0e3462fb 44 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M3 Debug Monitor Interrupt */
bogdanm 66:9c8f0e3462fb 45 PendSV_IRQn = -2, /*!< 14 Cortex-M3 Pend SV Interrupt */
bogdanm 66:9c8f0e3462fb 46 SysTick_IRQn = -1, /*!< 15 Cortex-M3 System Tick Interrupt */
bogdanm 66:9c8f0e3462fb 47
bogdanm 66:9c8f0e3462fb 48 /****** LPC17xx Specific Interrupt Numbers *******************************************************/
bogdanm 66:9c8f0e3462fb 49 WDT_IRQn = 0, /*!< Watchdog Timer Interrupt */
bogdanm 66:9c8f0e3462fb 50 TIMER0_IRQn = 1, /*!< Timer0 Interrupt */
bogdanm 66:9c8f0e3462fb 51 TIMER1_IRQn = 2, /*!< Timer1 Interrupt */
bogdanm 66:9c8f0e3462fb 52 TIMER2_IRQn = 3, /*!< Timer2 Interrupt */
bogdanm 66:9c8f0e3462fb 53 TIMER3_IRQn = 4, /*!< Timer3 Interrupt */
bogdanm 66:9c8f0e3462fb 54 UART0_IRQn = 5, /*!< UART0 Interrupt */
bogdanm 66:9c8f0e3462fb 55 UART1_IRQn = 6, /*!< UART1 Interrupt */
bogdanm 66:9c8f0e3462fb 56 UART2_IRQn = 7, /*!< UART2 Interrupt */
bogdanm 66:9c8f0e3462fb 57 UART3_IRQn = 8, /*!< UART3 Interrupt */
bogdanm 66:9c8f0e3462fb 58 PWM1_IRQn = 9, /*!< PWM1 Interrupt */
bogdanm 66:9c8f0e3462fb 59 I2C0_IRQn = 10, /*!< I2C0 Interrupt */
bogdanm 66:9c8f0e3462fb 60 I2C1_IRQn = 11, /*!< I2C1 Interrupt */
bogdanm 66:9c8f0e3462fb 61 I2C2_IRQn = 12, /*!< I2C2 Interrupt */
bogdanm 66:9c8f0e3462fb 62 SPI_IRQn = 13, /*!< SPI Interrupt */
bogdanm 66:9c8f0e3462fb 63 SSP0_IRQn = 14, /*!< SSP0 Interrupt */
bogdanm 66:9c8f0e3462fb 64 SSP1_IRQn = 15, /*!< SSP1 Interrupt */
bogdanm 66:9c8f0e3462fb 65 PLL0_IRQn = 16, /*!< PLL0 Lock (Main PLL) Interrupt */
bogdanm 66:9c8f0e3462fb 66 RTC_IRQn = 17, /*!< Real Time Clock Interrupt */
bogdanm 66:9c8f0e3462fb 67 EINT0_IRQn = 18, /*!< External Interrupt 0 Interrupt */
bogdanm 66:9c8f0e3462fb 68 EINT1_IRQn = 19, /*!< External Interrupt 1 Interrupt */
bogdanm 66:9c8f0e3462fb 69 EINT2_IRQn = 20, /*!< External Interrupt 2 Interrupt */
bogdanm 66:9c8f0e3462fb 70 EINT3_IRQn = 21, /*!< External Interrupt 3 Interrupt */
bogdanm 66:9c8f0e3462fb 71 ADC_IRQn = 22, /*!< A/D Converter Interrupt */
bogdanm 66:9c8f0e3462fb 72 BOD_IRQn = 23, /*!< Brown-Out Detect Interrupt */
bogdanm 66:9c8f0e3462fb 73 USB_IRQn = 24, /*!< USB Interrupt */
bogdanm 66:9c8f0e3462fb 74 CAN_IRQn = 25, /*!< CAN Interrupt */
bogdanm 66:9c8f0e3462fb 75 DMA_IRQn = 26, /*!< General Purpose DMA Interrupt */
bogdanm 66:9c8f0e3462fb 76 I2S_IRQn = 27, /*!< I2S Interrupt */
bogdanm 66:9c8f0e3462fb 77 ENET_IRQn = 28, /*!< Ethernet Interrupt */
bogdanm 66:9c8f0e3462fb 78 RIT_IRQn = 29, /*!< Repetitive Interrupt Timer Interrupt */
bogdanm 66:9c8f0e3462fb 79 MCPWM_IRQn = 30, /*!< Motor Control PWM Interrupt */
bogdanm 66:9c8f0e3462fb 80 QEI_IRQn = 31, /*!< Quadrature Encoder Interface Interrupt */
bogdanm 66:9c8f0e3462fb 81 PLL1_IRQn = 32, /*!< PLL1 Lock (USB PLL) Interrupt */
bogdanm 66:9c8f0e3462fb 82 USBActivity_IRQn = 33, /* USB Activity interrupt */
bogdanm 66:9c8f0e3462fb 83 CANActivity_IRQn = 34, /* CAN Activity interrupt */
bogdanm 66:9c8f0e3462fb 84 } IRQn_Type;
bogdanm 66:9c8f0e3462fb 85
bogdanm 66:9c8f0e3462fb 86
bogdanm 66:9c8f0e3462fb 87 /*
bogdanm 66:9c8f0e3462fb 88 * ==========================================================================
bogdanm 66:9c8f0e3462fb 89 * ----------- Processor and Core Peripheral Section ------------------------
bogdanm 66:9c8f0e3462fb 90 * ==========================================================================
bogdanm 66:9c8f0e3462fb 91 */
bogdanm 66:9c8f0e3462fb 92
bogdanm 66:9c8f0e3462fb 93 /* Configuration of the Cortex-M3 Processor and Core Peripherals */
bogdanm 66:9c8f0e3462fb 94 #define __MPU_PRESENT 1 /*!< MPU present or not */
bogdanm 66:9c8f0e3462fb 95 #define __NVIC_PRIO_BITS 5 /*!< Number of Bits used for Priority Levels */
bogdanm 66:9c8f0e3462fb 96 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
bogdanm 66:9c8f0e3462fb 97
bogdanm 66:9c8f0e3462fb 98
bogdanm 66:9c8f0e3462fb 99 #include "core_cm3.h" /* Cortex-M3 processor and core peripherals */
bogdanm 66:9c8f0e3462fb 100 #include "system_LPC17xx.h" /* System Header */
bogdanm 66:9c8f0e3462fb 101
bogdanm 66:9c8f0e3462fb 102
bogdanm 66:9c8f0e3462fb 103 /******************************************************************************/
bogdanm 66:9c8f0e3462fb 104 /* Device Specific Peripheral registers structures */
bogdanm 66:9c8f0e3462fb 105 /******************************************************************************/
bogdanm 66:9c8f0e3462fb 106
bogdanm 66:9c8f0e3462fb 107 #if defined ( __CC_ARM )
bogdanm 66:9c8f0e3462fb 108 #pragma anon_unions
bogdanm 66:9c8f0e3462fb 109 #endif
bogdanm 66:9c8f0e3462fb 110
bogdanm 66:9c8f0e3462fb 111 /*------------- System Control (SC) ------------------------------------------*/
bogdanm 66:9c8f0e3462fb 112 typedef struct
bogdanm 66:9c8f0e3462fb 113 {
bogdanm 66:9c8f0e3462fb 114 __IO uint32_t FLASHCFG; /* Flash Accelerator Module */
bogdanm 66:9c8f0e3462fb 115 uint32_t RESERVED0[31];
bogdanm 66:9c8f0e3462fb 116 __IO uint32_t PLL0CON; /* Clocking and Power Control */
bogdanm 66:9c8f0e3462fb 117 __IO uint32_t PLL0CFG;
bogdanm 66:9c8f0e3462fb 118 __I uint32_t PLL0STAT;
bogdanm 66:9c8f0e3462fb 119 __O uint32_t PLL0FEED;
bogdanm 66:9c8f0e3462fb 120 uint32_t RESERVED1[4];
bogdanm 66:9c8f0e3462fb 121 __IO uint32_t PLL1CON;
bogdanm 66:9c8f0e3462fb 122 __IO uint32_t PLL1CFG;
bogdanm 66:9c8f0e3462fb 123 __I uint32_t PLL1STAT;
bogdanm 66:9c8f0e3462fb 124 __O uint32_t PLL1FEED;
bogdanm 66:9c8f0e3462fb 125 uint32_t RESERVED2[4];
bogdanm 66:9c8f0e3462fb 126 __IO uint32_t PCON;
bogdanm 66:9c8f0e3462fb 127 __IO uint32_t PCONP;
bogdanm 66:9c8f0e3462fb 128 uint32_t RESERVED3[15];
bogdanm 66:9c8f0e3462fb 129 __IO uint32_t CCLKCFG;
bogdanm 66:9c8f0e3462fb 130 __IO uint32_t USBCLKCFG;
bogdanm 66:9c8f0e3462fb 131 __IO uint32_t CLKSRCSEL;
bogdanm 66:9c8f0e3462fb 132 __IO uint32_t CANSLEEPCLR;
bogdanm 66:9c8f0e3462fb 133 __IO uint32_t CANWAKEFLAGS;
bogdanm 66:9c8f0e3462fb 134 uint32_t RESERVED4[10];
bogdanm 66:9c8f0e3462fb 135 __IO uint32_t EXTINT; /* External Interrupts */
bogdanm 66:9c8f0e3462fb 136 uint32_t RESERVED5;
bogdanm 66:9c8f0e3462fb 137 __IO uint32_t EXTMODE;
bogdanm 66:9c8f0e3462fb 138 __IO uint32_t EXTPOLAR;
bogdanm 66:9c8f0e3462fb 139 uint32_t RESERVED6[12];
bogdanm 66:9c8f0e3462fb 140 __IO uint32_t RSID; /* Reset */
bogdanm 66:9c8f0e3462fb 141 uint32_t RESERVED7[7];
bogdanm 66:9c8f0e3462fb 142 __IO uint32_t SCS; /* Syscon Miscellaneous Registers */
bogdanm 66:9c8f0e3462fb 143 __IO uint32_t IRCTRIM; /* Clock Dividers */
bogdanm 66:9c8f0e3462fb 144 __IO uint32_t PCLKSEL0;
bogdanm 66:9c8f0e3462fb 145 __IO uint32_t PCLKSEL1;
bogdanm 66:9c8f0e3462fb 146 uint32_t RESERVED8[4];
bogdanm 66:9c8f0e3462fb 147 __IO uint32_t USBIntSt; /* USB Device/OTG Interrupt Register */
bogdanm 66:9c8f0e3462fb 148 __IO uint32_t DMAREQSEL;
bogdanm 66:9c8f0e3462fb 149 __IO uint32_t CLKOUTCFG; /* Clock Output Configuration */
bogdanm 66:9c8f0e3462fb 150 } LPC_SC_TypeDef;
bogdanm 66:9c8f0e3462fb 151
bogdanm 66:9c8f0e3462fb 152 /*------------- Pin Connect Block (PINCON) -----------------------------------*/
bogdanm 66:9c8f0e3462fb 153 typedef struct
bogdanm 66:9c8f0e3462fb 154 {
bogdanm 66:9c8f0e3462fb 155 __IO uint32_t PINSEL0;
bogdanm 66:9c8f0e3462fb 156 __IO uint32_t PINSEL1;
bogdanm 66:9c8f0e3462fb 157 __IO uint32_t PINSEL2;
bogdanm 66:9c8f0e3462fb 158 __IO uint32_t PINSEL3;
bogdanm 66:9c8f0e3462fb 159 __IO uint32_t PINSEL4;
bogdanm 66:9c8f0e3462fb 160 __IO uint32_t PINSEL5;
bogdanm 66:9c8f0e3462fb 161 __IO uint32_t PINSEL6;
bogdanm 66:9c8f0e3462fb 162 __IO uint32_t PINSEL7;
bogdanm 66:9c8f0e3462fb 163 __IO uint32_t PINSEL8;
bogdanm 66:9c8f0e3462fb 164 __IO uint32_t PINSEL9;
bogdanm 66:9c8f0e3462fb 165 __IO uint32_t PINSEL10;
bogdanm 66:9c8f0e3462fb 166 uint32_t RESERVED0[5];
bogdanm 66:9c8f0e3462fb 167 __IO uint32_t PINMODE0;
bogdanm 66:9c8f0e3462fb 168 __IO uint32_t PINMODE1;
bogdanm 66:9c8f0e3462fb 169 __IO uint32_t PINMODE2;
bogdanm 66:9c8f0e3462fb 170 __IO uint32_t PINMODE3;
bogdanm 66:9c8f0e3462fb 171 __IO uint32_t PINMODE4;
bogdanm 66:9c8f0e3462fb 172 __IO uint32_t PINMODE5;
bogdanm 66:9c8f0e3462fb 173 __IO uint32_t PINMODE6;
bogdanm 66:9c8f0e3462fb 174 __IO uint32_t PINMODE7;
bogdanm 66:9c8f0e3462fb 175 __IO uint32_t PINMODE8;
bogdanm 66:9c8f0e3462fb 176 __IO uint32_t PINMODE9;
bogdanm 66:9c8f0e3462fb 177 __IO uint32_t PINMODE_OD0;
bogdanm 66:9c8f0e3462fb 178 __IO uint32_t PINMODE_OD1;
bogdanm 66:9c8f0e3462fb 179 __IO uint32_t PINMODE_OD2;
bogdanm 66:9c8f0e3462fb 180 __IO uint32_t PINMODE_OD3;
bogdanm 66:9c8f0e3462fb 181 __IO uint32_t PINMODE_OD4;
bogdanm 66:9c8f0e3462fb 182 __IO uint32_t I2CPADCFG;
bogdanm 66:9c8f0e3462fb 183 } LPC_PINCON_TypeDef;
bogdanm 66:9c8f0e3462fb 184
bogdanm 66:9c8f0e3462fb 185 /*------------- General Purpose Input/Output (GPIO) --------------------------*/
bogdanm 66:9c8f0e3462fb 186 typedef struct
bogdanm 66:9c8f0e3462fb 187 {
bogdanm 66:9c8f0e3462fb 188 union {
bogdanm 66:9c8f0e3462fb 189 __IO uint32_t FIODIR;
bogdanm 66:9c8f0e3462fb 190 struct {
bogdanm 66:9c8f0e3462fb 191 __IO uint16_t FIODIRL;
bogdanm 66:9c8f0e3462fb 192 __IO uint16_t FIODIRH;
bogdanm 66:9c8f0e3462fb 193 };
bogdanm 66:9c8f0e3462fb 194 struct {
bogdanm 66:9c8f0e3462fb 195 __IO uint8_t FIODIR0;
bogdanm 66:9c8f0e3462fb 196 __IO uint8_t FIODIR1;
bogdanm 66:9c8f0e3462fb 197 __IO uint8_t FIODIR2;
bogdanm 66:9c8f0e3462fb 198 __IO uint8_t FIODIR3;
bogdanm 66:9c8f0e3462fb 199 };
bogdanm 66:9c8f0e3462fb 200 };
bogdanm 66:9c8f0e3462fb 201 uint32_t RESERVED0[3];
bogdanm 66:9c8f0e3462fb 202 union {
bogdanm 66:9c8f0e3462fb 203 __IO uint32_t FIOMASK;
bogdanm 66:9c8f0e3462fb 204 struct {
bogdanm 66:9c8f0e3462fb 205 __IO uint16_t FIOMASKL;
bogdanm 66:9c8f0e3462fb 206 __IO uint16_t FIOMASKH;
bogdanm 66:9c8f0e3462fb 207 };
bogdanm 66:9c8f0e3462fb 208 struct {
bogdanm 66:9c8f0e3462fb 209 __IO uint8_t FIOMASK0;
bogdanm 66:9c8f0e3462fb 210 __IO uint8_t FIOMASK1;
bogdanm 66:9c8f0e3462fb 211 __IO uint8_t FIOMASK2;
bogdanm 66:9c8f0e3462fb 212 __IO uint8_t FIOMASK3;
bogdanm 66:9c8f0e3462fb 213 };
bogdanm 66:9c8f0e3462fb 214 };
bogdanm 66:9c8f0e3462fb 215 union {
bogdanm 66:9c8f0e3462fb 216 __IO uint32_t FIOPIN;
bogdanm 66:9c8f0e3462fb 217 struct {
bogdanm 66:9c8f0e3462fb 218 __IO uint16_t FIOPINL;
bogdanm 66:9c8f0e3462fb 219 __IO uint16_t FIOPINH;
bogdanm 66:9c8f0e3462fb 220 };
bogdanm 66:9c8f0e3462fb 221 struct {
bogdanm 66:9c8f0e3462fb 222 __IO uint8_t FIOPIN0;
bogdanm 66:9c8f0e3462fb 223 __IO uint8_t FIOPIN1;
bogdanm 66:9c8f0e3462fb 224 __IO uint8_t FIOPIN2;
bogdanm 66:9c8f0e3462fb 225 __IO uint8_t FIOPIN3;
bogdanm 66:9c8f0e3462fb 226 };
bogdanm 66:9c8f0e3462fb 227 };
bogdanm 66:9c8f0e3462fb 228 union {
bogdanm 66:9c8f0e3462fb 229 __IO uint32_t FIOSET;
bogdanm 66:9c8f0e3462fb 230 struct {
bogdanm 66:9c8f0e3462fb 231 __IO uint16_t FIOSETL;
bogdanm 66:9c8f0e3462fb 232 __IO uint16_t FIOSETH;
bogdanm 66:9c8f0e3462fb 233 };
bogdanm 66:9c8f0e3462fb 234 struct {
bogdanm 66:9c8f0e3462fb 235 __IO uint8_t FIOSET0;
bogdanm 66:9c8f0e3462fb 236 __IO uint8_t FIOSET1;
bogdanm 66:9c8f0e3462fb 237 __IO uint8_t FIOSET2;
bogdanm 66:9c8f0e3462fb 238 __IO uint8_t FIOSET3;
bogdanm 66:9c8f0e3462fb 239 };
bogdanm 66:9c8f0e3462fb 240 };
bogdanm 66:9c8f0e3462fb 241 union {
bogdanm 66:9c8f0e3462fb 242 __O uint32_t FIOCLR;
bogdanm 66:9c8f0e3462fb 243 struct {
bogdanm 66:9c8f0e3462fb 244 __O uint16_t FIOCLRL;
bogdanm 66:9c8f0e3462fb 245 __O uint16_t FIOCLRH;
bogdanm 66:9c8f0e3462fb 246 };
bogdanm 66:9c8f0e3462fb 247 struct {
bogdanm 66:9c8f0e3462fb 248 __O uint8_t FIOCLR0;
bogdanm 66:9c8f0e3462fb 249 __O uint8_t FIOCLR1;
bogdanm 66:9c8f0e3462fb 250 __O uint8_t FIOCLR2;
bogdanm 66:9c8f0e3462fb 251 __O uint8_t FIOCLR3;
bogdanm 66:9c8f0e3462fb 252 };
bogdanm 66:9c8f0e3462fb 253 };
bogdanm 66:9c8f0e3462fb 254 } LPC_GPIO_TypeDef;
bogdanm 66:9c8f0e3462fb 255
bogdanm 66:9c8f0e3462fb 256 typedef struct
bogdanm 66:9c8f0e3462fb 257 {
bogdanm 66:9c8f0e3462fb 258 __I uint32_t IntStatus;
bogdanm 66:9c8f0e3462fb 259 __I uint32_t IO0IntStatR;
bogdanm 66:9c8f0e3462fb 260 __I uint32_t IO0IntStatF;
bogdanm 66:9c8f0e3462fb 261 __O uint32_t IO0IntClr;
bogdanm 66:9c8f0e3462fb 262 __IO uint32_t IO0IntEnR;
bogdanm 66:9c8f0e3462fb 263 __IO uint32_t IO0IntEnF;
bogdanm 66:9c8f0e3462fb 264 uint32_t RESERVED0[3];
bogdanm 66:9c8f0e3462fb 265 __I uint32_t IO2IntStatR;
bogdanm 66:9c8f0e3462fb 266 __I uint32_t IO2IntStatF;
bogdanm 66:9c8f0e3462fb 267 __O uint32_t IO2IntClr;
bogdanm 66:9c8f0e3462fb 268 __IO uint32_t IO2IntEnR;
bogdanm 66:9c8f0e3462fb 269 __IO uint32_t IO2IntEnF;
bogdanm 66:9c8f0e3462fb 270 } LPC_GPIOINT_TypeDef;
bogdanm 66:9c8f0e3462fb 271
bogdanm 66:9c8f0e3462fb 272 /*------------- Timer (TIM) --------------------------------------------------*/
bogdanm 66:9c8f0e3462fb 273 typedef struct
bogdanm 66:9c8f0e3462fb 274 {
bogdanm 66:9c8f0e3462fb 275 __IO uint32_t IR;
bogdanm 66:9c8f0e3462fb 276 __IO uint32_t TCR;
bogdanm 66:9c8f0e3462fb 277 __IO uint32_t TC;
bogdanm 66:9c8f0e3462fb 278 __IO uint32_t PR;
bogdanm 66:9c8f0e3462fb 279 __IO uint32_t PC;
bogdanm 66:9c8f0e3462fb 280 __IO uint32_t MCR;
bogdanm 66:9c8f0e3462fb 281 __IO uint32_t MR0;
bogdanm 66:9c8f0e3462fb 282 __IO uint32_t MR1;
bogdanm 66:9c8f0e3462fb 283 __IO uint32_t MR2;
bogdanm 66:9c8f0e3462fb 284 __IO uint32_t MR3;
bogdanm 66:9c8f0e3462fb 285 __IO uint32_t CCR;
bogdanm 66:9c8f0e3462fb 286 __I uint32_t CR0;
bogdanm 66:9c8f0e3462fb 287 __I uint32_t CR1;
bogdanm 66:9c8f0e3462fb 288 uint32_t RESERVED0[2];
bogdanm 66:9c8f0e3462fb 289 __IO uint32_t EMR;
bogdanm 66:9c8f0e3462fb 290 uint32_t RESERVED1[12];
bogdanm 66:9c8f0e3462fb 291 __IO uint32_t CTCR;
bogdanm 66:9c8f0e3462fb 292 } LPC_TIM_TypeDef;
bogdanm 66:9c8f0e3462fb 293
bogdanm 66:9c8f0e3462fb 294 /*------------- Pulse-Width Modulation (PWM) ---------------------------------*/
bogdanm 66:9c8f0e3462fb 295 typedef struct
bogdanm 66:9c8f0e3462fb 296 {
bogdanm 66:9c8f0e3462fb 297 __IO uint32_t IR;
bogdanm 66:9c8f0e3462fb 298 __IO uint32_t TCR;
bogdanm 66:9c8f0e3462fb 299 __IO uint32_t TC;
bogdanm 66:9c8f0e3462fb 300 __IO uint32_t PR;
bogdanm 66:9c8f0e3462fb 301 __IO uint32_t PC;
bogdanm 66:9c8f0e3462fb 302 __IO uint32_t MCR;
bogdanm 66:9c8f0e3462fb 303 __IO uint32_t MR0;
bogdanm 66:9c8f0e3462fb 304 __IO uint32_t MR1;
bogdanm 66:9c8f0e3462fb 305 __IO uint32_t MR2;
bogdanm 66:9c8f0e3462fb 306 __IO uint32_t MR3;
bogdanm 66:9c8f0e3462fb 307 __IO uint32_t CCR;
bogdanm 66:9c8f0e3462fb 308 __I uint32_t CR0;
bogdanm 66:9c8f0e3462fb 309 __I uint32_t CR1;
bogdanm 66:9c8f0e3462fb 310 __I uint32_t CR2;
bogdanm 66:9c8f0e3462fb 311 __I uint32_t CR3;
bogdanm 66:9c8f0e3462fb 312 uint32_t RESERVED0;
bogdanm 66:9c8f0e3462fb 313 __IO uint32_t MR4;
bogdanm 66:9c8f0e3462fb 314 __IO uint32_t MR5;
bogdanm 66:9c8f0e3462fb 315 __IO uint32_t MR6;
bogdanm 66:9c8f0e3462fb 316 __IO uint32_t PCR;
bogdanm 66:9c8f0e3462fb 317 __IO uint32_t LER;
bogdanm 66:9c8f0e3462fb 318 uint32_t RESERVED1[7];
bogdanm 66:9c8f0e3462fb 319 __IO uint32_t CTCR;
bogdanm 66:9c8f0e3462fb 320 } LPC_PWM_TypeDef;
bogdanm 66:9c8f0e3462fb 321
bogdanm 66:9c8f0e3462fb 322 /*------------- Universal Asynchronous Receiver Transmitter (UART) -----------*/
bogdanm 66:9c8f0e3462fb 323 typedef struct
bogdanm 66:9c8f0e3462fb 324 {
bogdanm 66:9c8f0e3462fb 325 union {
bogdanm 66:9c8f0e3462fb 326 __I uint8_t RBR;
bogdanm 66:9c8f0e3462fb 327 __O uint8_t THR;
bogdanm 66:9c8f0e3462fb 328 __IO uint8_t DLL;
bogdanm 66:9c8f0e3462fb 329 uint32_t RESERVED0;
bogdanm 66:9c8f0e3462fb 330 };
bogdanm 66:9c8f0e3462fb 331 union {
bogdanm 66:9c8f0e3462fb 332 __IO uint8_t DLM;
bogdanm 66:9c8f0e3462fb 333 __IO uint32_t IER;
bogdanm 66:9c8f0e3462fb 334 };
bogdanm 66:9c8f0e3462fb 335 union {
bogdanm 66:9c8f0e3462fb 336 __I uint32_t IIR;
bogdanm 66:9c8f0e3462fb 337 __O uint8_t FCR;
bogdanm 66:9c8f0e3462fb 338 };
bogdanm 66:9c8f0e3462fb 339 __IO uint8_t LCR;
bogdanm 66:9c8f0e3462fb 340 uint8_t RESERVED1[7];
bogdanm 66:9c8f0e3462fb 341 __I uint8_t LSR;
bogdanm 66:9c8f0e3462fb 342 uint8_t RESERVED2[7];
bogdanm 66:9c8f0e3462fb 343 __IO uint8_t SCR;
bogdanm 66:9c8f0e3462fb 344 uint8_t RESERVED3[3];
bogdanm 66:9c8f0e3462fb 345 __IO uint32_t ACR;
bogdanm 66:9c8f0e3462fb 346 __IO uint8_t ICR;
bogdanm 66:9c8f0e3462fb 347 uint8_t RESERVED4[3];
bogdanm 66:9c8f0e3462fb 348 __IO uint8_t FDR;
bogdanm 66:9c8f0e3462fb 349 uint8_t RESERVED5[7];
bogdanm 66:9c8f0e3462fb 350 __IO uint8_t TER;
bogdanm 66:9c8f0e3462fb 351 uint8_t RESERVED6[39];
bogdanm 66:9c8f0e3462fb 352 __IO uint32_t FIFOLVL;
bogdanm 66:9c8f0e3462fb 353 } LPC_UART_TypeDef;
bogdanm 66:9c8f0e3462fb 354
bogdanm 66:9c8f0e3462fb 355 typedef struct
bogdanm 66:9c8f0e3462fb 356 {
bogdanm 66:9c8f0e3462fb 357 union {
bogdanm 66:9c8f0e3462fb 358 __I uint8_t RBR;
bogdanm 66:9c8f0e3462fb 359 __O uint8_t THR;
bogdanm 66:9c8f0e3462fb 360 __IO uint8_t DLL;
bogdanm 66:9c8f0e3462fb 361 uint32_t RESERVED0;
bogdanm 66:9c8f0e3462fb 362 };
bogdanm 66:9c8f0e3462fb 363 union {
bogdanm 66:9c8f0e3462fb 364 __IO uint8_t DLM;
bogdanm 66:9c8f0e3462fb 365 __IO uint32_t IER;
bogdanm 66:9c8f0e3462fb 366 };
bogdanm 66:9c8f0e3462fb 367 union {
bogdanm 66:9c8f0e3462fb 368 __I uint32_t IIR;
bogdanm 66:9c8f0e3462fb 369 __O uint8_t FCR;
bogdanm 66:9c8f0e3462fb 370 };
bogdanm 66:9c8f0e3462fb 371 __IO uint8_t LCR;
bogdanm 66:9c8f0e3462fb 372 uint8_t RESERVED1[7];
bogdanm 66:9c8f0e3462fb 373 __I uint8_t LSR;
bogdanm 66:9c8f0e3462fb 374 uint8_t RESERVED2[7];
bogdanm 66:9c8f0e3462fb 375 __IO uint8_t SCR;
bogdanm 66:9c8f0e3462fb 376 uint8_t RESERVED3[3];
bogdanm 66:9c8f0e3462fb 377 __IO uint32_t ACR;
bogdanm 66:9c8f0e3462fb 378 __IO uint8_t ICR;
bogdanm 66:9c8f0e3462fb 379 uint8_t RESERVED4[3];
bogdanm 66:9c8f0e3462fb 380 __IO uint8_t FDR;
bogdanm 66:9c8f0e3462fb 381 uint8_t RESERVED5[7];
bogdanm 66:9c8f0e3462fb 382 __IO uint8_t TER;
bogdanm 66:9c8f0e3462fb 383 uint8_t RESERVED6[39];
bogdanm 66:9c8f0e3462fb 384 __IO uint32_t FIFOLVL;
bogdanm 66:9c8f0e3462fb 385 } LPC_UART0_TypeDef;
bogdanm 66:9c8f0e3462fb 386
bogdanm 66:9c8f0e3462fb 387 typedef struct
bogdanm 66:9c8f0e3462fb 388 {
bogdanm 66:9c8f0e3462fb 389 union {
bogdanm 66:9c8f0e3462fb 390 __I uint8_t RBR;
bogdanm 66:9c8f0e3462fb 391 __O uint8_t THR;
bogdanm 66:9c8f0e3462fb 392 __IO uint8_t DLL;
bogdanm 66:9c8f0e3462fb 393 uint32_t RESERVED0;
bogdanm 66:9c8f0e3462fb 394 };
bogdanm 66:9c8f0e3462fb 395 union {
bogdanm 66:9c8f0e3462fb 396 __IO uint8_t DLM;
bogdanm 66:9c8f0e3462fb 397 __IO uint32_t IER;
bogdanm 66:9c8f0e3462fb 398 };
bogdanm 66:9c8f0e3462fb 399 union {
bogdanm 66:9c8f0e3462fb 400 __I uint32_t IIR;
bogdanm 66:9c8f0e3462fb 401 __O uint8_t FCR;
bogdanm 66:9c8f0e3462fb 402 };
bogdanm 66:9c8f0e3462fb 403 __IO uint8_t LCR;
bogdanm 66:9c8f0e3462fb 404 uint8_t RESERVED1[3];
bogdanm 66:9c8f0e3462fb 405 __IO uint8_t MCR;
bogdanm 66:9c8f0e3462fb 406 uint8_t RESERVED2[3];
bogdanm 66:9c8f0e3462fb 407 __I uint8_t LSR;
bogdanm 66:9c8f0e3462fb 408 uint8_t RESERVED3[3];
bogdanm 66:9c8f0e3462fb 409 __I uint8_t MSR;
bogdanm 66:9c8f0e3462fb 410 uint8_t RESERVED4[3];
bogdanm 66:9c8f0e3462fb 411 __IO uint8_t SCR;
bogdanm 66:9c8f0e3462fb 412 uint8_t RESERVED5[3];
bogdanm 66:9c8f0e3462fb 413 __IO uint32_t ACR;
bogdanm 66:9c8f0e3462fb 414 uint32_t RESERVED6;
bogdanm 66:9c8f0e3462fb 415 __IO uint32_t FDR;
bogdanm 66:9c8f0e3462fb 416 uint32_t RESERVED7;
bogdanm 66:9c8f0e3462fb 417 __IO uint8_t TER;
bogdanm 66:9c8f0e3462fb 418 uint8_t RESERVED8[27];
bogdanm 66:9c8f0e3462fb 419 __IO uint8_t RS485CTRL;
bogdanm 66:9c8f0e3462fb 420 uint8_t RESERVED9[3];
bogdanm 66:9c8f0e3462fb 421 __IO uint8_t ADRMATCH;
bogdanm 66:9c8f0e3462fb 422 uint8_t RESERVED10[3];
bogdanm 66:9c8f0e3462fb 423 __IO uint8_t RS485DLY;
bogdanm 66:9c8f0e3462fb 424 uint8_t RESERVED11[3];
bogdanm 66:9c8f0e3462fb 425 __IO uint32_t FIFOLVL;
bogdanm 66:9c8f0e3462fb 426 } LPC_UART1_TypeDef;
bogdanm 66:9c8f0e3462fb 427
bogdanm 66:9c8f0e3462fb 428 /*------------- Serial Peripheral Interface (SPI) ----------------------------*/
bogdanm 66:9c8f0e3462fb 429 typedef struct
bogdanm 66:9c8f0e3462fb 430 {
bogdanm 66:9c8f0e3462fb 431 __IO uint32_t SPCR;
bogdanm 66:9c8f0e3462fb 432 __I uint32_t SPSR;
bogdanm 66:9c8f0e3462fb 433 __IO uint32_t SPDR;
bogdanm 66:9c8f0e3462fb 434 __IO uint32_t SPCCR;
bogdanm 66:9c8f0e3462fb 435 uint32_t RESERVED0[3];
bogdanm 66:9c8f0e3462fb 436 __IO uint32_t SPINT;
bogdanm 66:9c8f0e3462fb 437 } LPC_SPI_TypeDef;
bogdanm 66:9c8f0e3462fb 438
bogdanm 66:9c8f0e3462fb 439 /*------------- Synchronous Serial Communication (SSP) -----------------------*/
bogdanm 66:9c8f0e3462fb 440 typedef struct
bogdanm 66:9c8f0e3462fb 441 {
bogdanm 66:9c8f0e3462fb 442 __IO uint32_t CR0;
bogdanm 66:9c8f0e3462fb 443 __IO uint32_t CR1;
bogdanm 66:9c8f0e3462fb 444 __IO uint32_t DR;
bogdanm 66:9c8f0e3462fb 445 __I uint32_t SR;
bogdanm 66:9c8f0e3462fb 446 __IO uint32_t CPSR;
bogdanm 66:9c8f0e3462fb 447 __IO uint32_t IMSC;
bogdanm 66:9c8f0e3462fb 448 __IO uint32_t RIS;
bogdanm 66:9c8f0e3462fb 449 __IO uint32_t MIS;
bogdanm 66:9c8f0e3462fb 450 __IO uint32_t ICR;
bogdanm 66:9c8f0e3462fb 451 __IO uint32_t DMACR;
bogdanm 66:9c8f0e3462fb 452 } LPC_SSP_TypeDef;
bogdanm 66:9c8f0e3462fb 453
bogdanm 66:9c8f0e3462fb 454 /*------------- Inter-Integrated Circuit (I2C) -------------------------------*/
bogdanm 66:9c8f0e3462fb 455 typedef struct
bogdanm 66:9c8f0e3462fb 456 {
bogdanm 66:9c8f0e3462fb 457 __IO uint32_t I2CONSET;
bogdanm 66:9c8f0e3462fb 458 __I uint32_t I2STAT;
bogdanm 66:9c8f0e3462fb 459 __IO uint32_t I2DAT;
bogdanm 66:9c8f0e3462fb 460 __IO uint32_t I2ADR0;
bogdanm 66:9c8f0e3462fb 461 __IO uint32_t I2SCLH;
bogdanm 66:9c8f0e3462fb 462 __IO uint32_t I2SCLL;
bogdanm 66:9c8f0e3462fb 463 __O uint32_t I2CONCLR;
bogdanm 66:9c8f0e3462fb 464 __IO uint32_t MMCTRL;
bogdanm 66:9c8f0e3462fb 465 __IO uint32_t I2ADR1;
bogdanm 66:9c8f0e3462fb 466 __IO uint32_t I2ADR2;
bogdanm 66:9c8f0e3462fb 467 __IO uint32_t I2ADR3;
bogdanm 66:9c8f0e3462fb 468 __I uint32_t I2DATA_BUFFER;
bogdanm 66:9c8f0e3462fb 469 __IO uint32_t I2MASK0;
bogdanm 66:9c8f0e3462fb 470 __IO uint32_t I2MASK1;
bogdanm 66:9c8f0e3462fb 471 __IO uint32_t I2MASK2;
bogdanm 66:9c8f0e3462fb 472 __IO uint32_t I2MASK3;
bogdanm 66:9c8f0e3462fb 473 } LPC_I2C_TypeDef;
bogdanm 66:9c8f0e3462fb 474
bogdanm 66:9c8f0e3462fb 475 /*------------- Inter IC Sound (I2S) -----------------------------------------*/
bogdanm 66:9c8f0e3462fb 476 typedef struct
bogdanm 66:9c8f0e3462fb 477 {
bogdanm 66:9c8f0e3462fb 478 __IO uint32_t I2SDAO;
bogdanm 66:9c8f0e3462fb 479 __IO uint32_t I2SDAI;
bogdanm 66:9c8f0e3462fb 480 __O uint32_t I2STXFIFO;
bogdanm 66:9c8f0e3462fb 481 __I uint32_t I2SRXFIFO;
bogdanm 66:9c8f0e3462fb 482 __I uint32_t I2SSTATE;
bogdanm 66:9c8f0e3462fb 483 __IO uint32_t I2SDMA1;
bogdanm 66:9c8f0e3462fb 484 __IO uint32_t I2SDMA2;
bogdanm 66:9c8f0e3462fb 485 __IO uint32_t I2SIRQ;
bogdanm 66:9c8f0e3462fb 486 __IO uint32_t I2STXRATE;
bogdanm 66:9c8f0e3462fb 487 __IO uint32_t I2SRXRATE;
bogdanm 66:9c8f0e3462fb 488 __IO uint32_t I2STXBITRATE;
bogdanm 66:9c8f0e3462fb 489 __IO uint32_t I2SRXBITRATE;
bogdanm 66:9c8f0e3462fb 490 __IO uint32_t I2STXMODE;
bogdanm 66:9c8f0e3462fb 491 __IO uint32_t I2SRXMODE;
bogdanm 66:9c8f0e3462fb 492 } LPC_I2S_TypeDef;
bogdanm 66:9c8f0e3462fb 493
bogdanm 66:9c8f0e3462fb 494 /*------------- Repetitive Interrupt Timer (RIT) -----------------------------*/
bogdanm 66:9c8f0e3462fb 495 typedef struct
bogdanm 66:9c8f0e3462fb 496 {
bogdanm 66:9c8f0e3462fb 497 __IO uint32_t RICOMPVAL;
bogdanm 66:9c8f0e3462fb 498 __IO uint32_t RIMASK;
bogdanm 66:9c8f0e3462fb 499 __IO uint8_t RICTRL;
bogdanm 66:9c8f0e3462fb 500 uint8_t RESERVED0[3];
bogdanm 66:9c8f0e3462fb 501 __IO uint32_t RICOUNTER;
bogdanm 66:9c8f0e3462fb 502 } LPC_RIT_TypeDef;
bogdanm 66:9c8f0e3462fb 503
bogdanm 66:9c8f0e3462fb 504 /*------------- Real-Time Clock (RTC) ----------------------------------------*/
bogdanm 66:9c8f0e3462fb 505 typedef struct
bogdanm 66:9c8f0e3462fb 506 {
bogdanm 66:9c8f0e3462fb 507 __IO uint8_t ILR;
bogdanm 66:9c8f0e3462fb 508 uint8_t RESERVED0[7];
bogdanm 66:9c8f0e3462fb 509 __IO uint8_t CCR;
bogdanm 66:9c8f0e3462fb 510 uint8_t RESERVED1[3];
bogdanm 66:9c8f0e3462fb 511 __IO uint8_t CIIR;
bogdanm 66:9c8f0e3462fb 512 uint8_t RESERVED2[3];
bogdanm 66:9c8f0e3462fb 513 __IO uint8_t AMR;
bogdanm 66:9c8f0e3462fb 514 uint8_t RESERVED3[3];
bogdanm 66:9c8f0e3462fb 515 __I uint32_t CTIME0;
bogdanm 66:9c8f0e3462fb 516 __I uint32_t CTIME1;
bogdanm 66:9c8f0e3462fb 517 __I uint32_t CTIME2;
bogdanm 66:9c8f0e3462fb 518 __IO uint8_t SEC;
bogdanm 66:9c8f0e3462fb 519 uint8_t RESERVED4[3];
bogdanm 66:9c8f0e3462fb 520 __IO uint8_t MIN;
bogdanm 66:9c8f0e3462fb 521 uint8_t RESERVED5[3];
bogdanm 66:9c8f0e3462fb 522 __IO uint8_t HOUR;
bogdanm 66:9c8f0e3462fb 523 uint8_t RESERVED6[3];
bogdanm 66:9c8f0e3462fb 524 __IO uint8_t DOM;
bogdanm 66:9c8f0e3462fb 525 uint8_t RESERVED7[3];
bogdanm 66:9c8f0e3462fb 526 __IO uint8_t DOW;
bogdanm 66:9c8f0e3462fb 527 uint8_t RESERVED8[3];
bogdanm 66:9c8f0e3462fb 528 __IO uint16_t DOY;
bogdanm 66:9c8f0e3462fb 529 uint16_t RESERVED9;
bogdanm 66:9c8f0e3462fb 530 __IO uint8_t MONTH;
bogdanm 66:9c8f0e3462fb 531 uint8_t RESERVED10[3];
bogdanm 66:9c8f0e3462fb 532 __IO uint16_t YEAR;
bogdanm 66:9c8f0e3462fb 533 uint16_t RESERVED11;
bogdanm 66:9c8f0e3462fb 534 __IO uint32_t CALIBRATION;
bogdanm 66:9c8f0e3462fb 535 __IO uint32_t GPREG0;
bogdanm 66:9c8f0e3462fb 536 __IO uint32_t GPREG1;
bogdanm 66:9c8f0e3462fb 537 __IO uint32_t GPREG2;
bogdanm 66:9c8f0e3462fb 538 __IO uint32_t GPREG3;
bogdanm 66:9c8f0e3462fb 539 __IO uint32_t GPREG4;
bogdanm 66:9c8f0e3462fb 540 __IO uint8_t RTC_AUXEN;
bogdanm 66:9c8f0e3462fb 541 uint8_t RESERVED12[3];
bogdanm 66:9c8f0e3462fb 542 __IO uint8_t RTC_AUX;
bogdanm 66:9c8f0e3462fb 543 uint8_t RESERVED13[3];
bogdanm 66:9c8f0e3462fb 544 __IO uint8_t ALSEC;
bogdanm 66:9c8f0e3462fb 545 uint8_t RESERVED14[3];
bogdanm 66:9c8f0e3462fb 546 __IO uint8_t ALMIN;
bogdanm 66:9c8f0e3462fb 547 uint8_t RESERVED15[3];
bogdanm 66:9c8f0e3462fb 548 __IO uint8_t ALHOUR;
bogdanm 66:9c8f0e3462fb 549 uint8_t RESERVED16[3];
bogdanm 66:9c8f0e3462fb 550 __IO uint8_t ALDOM;
bogdanm 66:9c8f0e3462fb 551 uint8_t RESERVED17[3];
bogdanm 66:9c8f0e3462fb 552 __IO uint8_t ALDOW;
bogdanm 66:9c8f0e3462fb 553 uint8_t RESERVED18[3];
bogdanm 66:9c8f0e3462fb 554 __IO uint16_t ALDOY;
bogdanm 66:9c8f0e3462fb 555 uint16_t RESERVED19;
bogdanm 66:9c8f0e3462fb 556 __IO uint8_t ALMON;
bogdanm 66:9c8f0e3462fb 557 uint8_t RESERVED20[3];
bogdanm 66:9c8f0e3462fb 558 __IO uint16_t ALYEAR;
bogdanm 66:9c8f0e3462fb 559 uint16_t RESERVED21;
bogdanm 66:9c8f0e3462fb 560 } LPC_RTC_TypeDef;
bogdanm 66:9c8f0e3462fb 561
bogdanm 66:9c8f0e3462fb 562 /*------------- Watchdog Timer (WDT) -----------------------------------------*/
bogdanm 66:9c8f0e3462fb 563 typedef struct
bogdanm 66:9c8f0e3462fb 564 {
bogdanm 66:9c8f0e3462fb 565 __IO uint8_t WDMOD;
bogdanm 66:9c8f0e3462fb 566 uint8_t RESERVED0[3];
bogdanm 66:9c8f0e3462fb 567 __IO uint32_t WDTC;
bogdanm 66:9c8f0e3462fb 568 __O uint8_t WDFEED;
bogdanm 66:9c8f0e3462fb 569 uint8_t RESERVED1[3];
bogdanm 66:9c8f0e3462fb 570 __I uint32_t WDTV;
bogdanm 66:9c8f0e3462fb 571 __IO uint32_t WDCLKSEL;
bogdanm 66:9c8f0e3462fb 572 } LPC_WDT_TypeDef;
bogdanm 66:9c8f0e3462fb 573
bogdanm 66:9c8f0e3462fb 574 /*------------- Analog-to-Digital Converter (ADC) ----------------------------*/
bogdanm 66:9c8f0e3462fb 575 typedef struct
bogdanm 66:9c8f0e3462fb 576 {
bogdanm 66:9c8f0e3462fb 577 __IO uint32_t ADCR;
bogdanm 66:9c8f0e3462fb 578 __IO uint32_t ADGDR;
bogdanm 66:9c8f0e3462fb 579 uint32_t RESERVED0;
bogdanm 66:9c8f0e3462fb 580 __IO uint32_t ADINTEN;
bogdanm 66:9c8f0e3462fb 581 __I uint32_t ADDR0;
bogdanm 66:9c8f0e3462fb 582 __I uint32_t ADDR1;
bogdanm 66:9c8f0e3462fb 583 __I uint32_t ADDR2;
bogdanm 66:9c8f0e3462fb 584 __I uint32_t ADDR3;
bogdanm 66:9c8f0e3462fb 585 __I uint32_t ADDR4;
bogdanm 66:9c8f0e3462fb 586 __I uint32_t ADDR5;
bogdanm 66:9c8f0e3462fb 587 __I uint32_t ADDR6;
bogdanm 66:9c8f0e3462fb 588 __I uint32_t ADDR7;
bogdanm 66:9c8f0e3462fb 589 __I uint32_t ADSTAT;
bogdanm 66:9c8f0e3462fb 590 __IO uint32_t ADTRM;
bogdanm 66:9c8f0e3462fb 591 } LPC_ADC_TypeDef;
bogdanm 66:9c8f0e3462fb 592
bogdanm 66:9c8f0e3462fb 593 /*------------- Digital-to-Analog Converter (DAC) ----------------------------*/
bogdanm 66:9c8f0e3462fb 594 typedef struct
bogdanm 66:9c8f0e3462fb 595 {
bogdanm 66:9c8f0e3462fb 596 __IO uint32_t DACR;
bogdanm 66:9c8f0e3462fb 597 __IO uint32_t DACCTRL;
bogdanm 66:9c8f0e3462fb 598 __IO uint16_t DACCNTVAL;
bogdanm 66:9c8f0e3462fb 599 } LPC_DAC_TypeDef;
bogdanm 66:9c8f0e3462fb 600
bogdanm 66:9c8f0e3462fb 601 /*------------- Motor Control Pulse-Width Modulation (MCPWM) -----------------*/
bogdanm 66:9c8f0e3462fb 602 typedef struct
bogdanm 66:9c8f0e3462fb 603 {
bogdanm 66:9c8f0e3462fb 604 __I uint32_t MCCON;
bogdanm 66:9c8f0e3462fb 605 __O uint32_t MCCON_SET;
bogdanm 66:9c8f0e3462fb 606 __O uint32_t MCCON_CLR;
bogdanm 66:9c8f0e3462fb 607 __I uint32_t MCCAPCON;
bogdanm 66:9c8f0e3462fb 608 __O uint32_t MCCAPCON_SET;
bogdanm 66:9c8f0e3462fb 609 __O uint32_t MCCAPCON_CLR;
bogdanm 66:9c8f0e3462fb 610 __IO uint32_t MCTIM0;
bogdanm 66:9c8f0e3462fb 611 __IO uint32_t MCTIM1;
bogdanm 66:9c8f0e3462fb 612 __IO uint32_t MCTIM2;
bogdanm 66:9c8f0e3462fb 613 __IO uint32_t MCPER0;
bogdanm 66:9c8f0e3462fb 614 __IO uint32_t MCPER1;
bogdanm 66:9c8f0e3462fb 615 __IO uint32_t MCPER2;
bogdanm 66:9c8f0e3462fb 616 __IO uint32_t MCPW0;
bogdanm 66:9c8f0e3462fb 617 __IO uint32_t MCPW1;
bogdanm 66:9c8f0e3462fb 618 __IO uint32_t MCPW2;
bogdanm 66:9c8f0e3462fb 619 __IO uint32_t MCDEADTIME;
bogdanm 66:9c8f0e3462fb 620 __IO uint32_t MCCCP;
bogdanm 66:9c8f0e3462fb 621 __IO uint32_t MCCR0;
bogdanm 66:9c8f0e3462fb 622 __IO uint32_t MCCR1;
bogdanm 66:9c8f0e3462fb 623 __IO uint32_t MCCR2;
bogdanm 66:9c8f0e3462fb 624 __I uint32_t MCINTEN;
bogdanm 66:9c8f0e3462fb 625 __O uint32_t MCINTEN_SET;
bogdanm 66:9c8f0e3462fb 626 __O uint32_t MCINTEN_CLR;
bogdanm 66:9c8f0e3462fb 627 __I uint32_t MCCNTCON;
bogdanm 66:9c8f0e3462fb 628 __O uint32_t MCCNTCON_SET;
bogdanm 66:9c8f0e3462fb 629 __O uint32_t MCCNTCON_CLR;
bogdanm 66:9c8f0e3462fb 630 __I uint32_t MCINTFLAG;
bogdanm 66:9c8f0e3462fb 631 __O uint32_t MCINTFLAG_SET;
bogdanm 66:9c8f0e3462fb 632 __O uint32_t MCINTFLAG_CLR;
bogdanm 66:9c8f0e3462fb 633 __O uint32_t MCCAP_CLR;
bogdanm 66:9c8f0e3462fb 634 } LPC_MCPWM_TypeDef;
bogdanm 66:9c8f0e3462fb 635
bogdanm 66:9c8f0e3462fb 636 /*------------- Quadrature Encoder Interface (QEI) ---------------------------*/
bogdanm 66:9c8f0e3462fb 637 typedef struct
bogdanm 66:9c8f0e3462fb 638 {
bogdanm 66:9c8f0e3462fb 639 __O uint32_t QEICON;
bogdanm 66:9c8f0e3462fb 640 __I uint32_t QEISTAT;
bogdanm 66:9c8f0e3462fb 641 __IO uint32_t QEICONF;
bogdanm 66:9c8f0e3462fb 642 __I uint32_t QEIPOS;
bogdanm 66:9c8f0e3462fb 643 __IO uint32_t QEIMAXPOS;
bogdanm 66:9c8f0e3462fb 644 __IO uint32_t CMPOS0;
bogdanm 66:9c8f0e3462fb 645 __IO uint32_t CMPOS1;
bogdanm 66:9c8f0e3462fb 646 __IO uint32_t CMPOS2;
bogdanm 66:9c8f0e3462fb 647 __I uint32_t INXCNT;
bogdanm 66:9c8f0e3462fb 648 __IO uint32_t INXCMP;
bogdanm 66:9c8f0e3462fb 649 __IO uint32_t QEILOAD;
bogdanm 66:9c8f0e3462fb 650 __I uint32_t QEITIME;
bogdanm 66:9c8f0e3462fb 651 __I uint32_t QEIVEL;
bogdanm 66:9c8f0e3462fb 652 __I uint32_t QEICAP;
bogdanm 66:9c8f0e3462fb 653 __IO uint32_t VELCOMP;
bogdanm 66:9c8f0e3462fb 654 __IO uint32_t FILTER;
bogdanm 66:9c8f0e3462fb 655 uint32_t RESERVED0[998];
bogdanm 66:9c8f0e3462fb 656 __O uint32_t QEIIEC;
bogdanm 66:9c8f0e3462fb 657 __O uint32_t QEIIES;
bogdanm 66:9c8f0e3462fb 658 __I uint32_t QEIINTSTAT;
bogdanm 66:9c8f0e3462fb 659 __I uint32_t QEIIE;
bogdanm 66:9c8f0e3462fb 660 __O uint32_t QEICLR;
bogdanm 66:9c8f0e3462fb 661 __O uint32_t QEISET;
bogdanm 66:9c8f0e3462fb 662 } LPC_QEI_TypeDef;
bogdanm 66:9c8f0e3462fb 663
bogdanm 66:9c8f0e3462fb 664 /*------------- Controller Area Network (CAN) --------------------------------*/
bogdanm 66:9c8f0e3462fb 665 typedef struct
bogdanm 66:9c8f0e3462fb 666 {
bogdanm 66:9c8f0e3462fb 667 __IO uint32_t mask[512]; /* ID Masks */
bogdanm 66:9c8f0e3462fb 668 } LPC_CANAF_RAM_TypeDef;
bogdanm 66:9c8f0e3462fb 669
bogdanm 66:9c8f0e3462fb 670 typedef struct /* Acceptance Filter Registers */
bogdanm 66:9c8f0e3462fb 671 {
bogdanm 66:9c8f0e3462fb 672 __IO uint32_t AFMR;
bogdanm 66:9c8f0e3462fb 673 __IO uint32_t SFF_sa;
bogdanm 66:9c8f0e3462fb 674 __IO uint32_t SFF_GRP_sa;
bogdanm 66:9c8f0e3462fb 675 __IO uint32_t EFF_sa;
bogdanm 66:9c8f0e3462fb 676 __IO uint32_t EFF_GRP_sa;
bogdanm 66:9c8f0e3462fb 677 __IO uint32_t ENDofTable;
bogdanm 66:9c8f0e3462fb 678 __I uint32_t LUTerrAd;
bogdanm 66:9c8f0e3462fb 679 __I uint32_t LUTerr;
bogdanm 66:9c8f0e3462fb 680 __IO uint32_t FCANIE;
bogdanm 66:9c8f0e3462fb 681 __IO uint32_t FCANIC0;
bogdanm 66:9c8f0e3462fb 682 __IO uint32_t FCANIC1;
bogdanm 66:9c8f0e3462fb 683 } LPC_CANAF_TypeDef;
bogdanm 66:9c8f0e3462fb 684
bogdanm 66:9c8f0e3462fb 685 typedef struct /* Central Registers */
bogdanm 66:9c8f0e3462fb 686 {
bogdanm 66:9c8f0e3462fb 687 __I uint32_t CANTxSR;
bogdanm 66:9c8f0e3462fb 688 __I uint32_t CANRxSR;
bogdanm 66:9c8f0e3462fb 689 __I uint32_t CANMSR;
bogdanm 66:9c8f0e3462fb 690 } LPC_CANCR_TypeDef;
bogdanm 66:9c8f0e3462fb 691
bogdanm 66:9c8f0e3462fb 692 typedef struct /* Controller Registers */
bogdanm 66:9c8f0e3462fb 693 {
bogdanm 66:9c8f0e3462fb 694 __IO uint32_t MOD;
bogdanm 66:9c8f0e3462fb 695 __O uint32_t CMR;
bogdanm 66:9c8f0e3462fb 696 __IO uint32_t GSR;
bogdanm 66:9c8f0e3462fb 697 __I uint32_t ICR;
bogdanm 66:9c8f0e3462fb 698 __IO uint32_t IER;
bogdanm 66:9c8f0e3462fb 699 __IO uint32_t BTR;
bogdanm 66:9c8f0e3462fb 700 __IO uint32_t EWL;
bogdanm 66:9c8f0e3462fb 701 __I uint32_t SR;
bogdanm 66:9c8f0e3462fb 702 __IO uint32_t RFS;
bogdanm 66:9c8f0e3462fb 703 __IO uint32_t RID;
bogdanm 66:9c8f0e3462fb 704 __IO uint32_t RDA;
bogdanm 66:9c8f0e3462fb 705 __IO uint32_t RDB;
bogdanm 66:9c8f0e3462fb 706 __IO uint32_t TFI1;
bogdanm 66:9c8f0e3462fb 707 __IO uint32_t TID1;
bogdanm 66:9c8f0e3462fb 708 __IO uint32_t TDA1;
bogdanm 66:9c8f0e3462fb 709 __IO uint32_t TDB1;
bogdanm 66:9c8f0e3462fb 710 __IO uint32_t TFI2;
bogdanm 66:9c8f0e3462fb 711 __IO uint32_t TID2;
bogdanm 66:9c8f0e3462fb 712 __IO uint32_t TDA2;
bogdanm 66:9c8f0e3462fb 713 __IO uint32_t TDB2;
bogdanm 66:9c8f0e3462fb 714 __IO uint32_t TFI3;
bogdanm 66:9c8f0e3462fb 715 __IO uint32_t TID3;
bogdanm 66:9c8f0e3462fb 716 __IO uint32_t TDA3;
bogdanm 66:9c8f0e3462fb 717 __IO uint32_t TDB3;
bogdanm 66:9c8f0e3462fb 718 } LPC_CAN_TypeDef;
bogdanm 66:9c8f0e3462fb 719
bogdanm 66:9c8f0e3462fb 720 /*------------- General Purpose Direct Memory Access (GPDMA) -----------------*/
bogdanm 66:9c8f0e3462fb 721 typedef struct /* Common Registers */
bogdanm 66:9c8f0e3462fb 722 {
bogdanm 66:9c8f0e3462fb 723 __I uint32_t DMACIntStat;
bogdanm 66:9c8f0e3462fb 724 __I uint32_t DMACIntTCStat;
bogdanm 66:9c8f0e3462fb 725 __O uint32_t DMACIntTCClear;
bogdanm 66:9c8f0e3462fb 726 __I uint32_t DMACIntErrStat;
bogdanm 66:9c8f0e3462fb 727 __O uint32_t DMACIntErrClr;
bogdanm 66:9c8f0e3462fb 728 __I uint32_t DMACRawIntTCStat;
bogdanm 66:9c8f0e3462fb 729 __I uint32_t DMACRawIntErrStat;
bogdanm 66:9c8f0e3462fb 730 __I uint32_t DMACEnbldChns;
bogdanm 66:9c8f0e3462fb 731 __IO uint32_t DMACSoftBReq;
bogdanm 66:9c8f0e3462fb 732 __IO uint32_t DMACSoftSReq;
bogdanm 66:9c8f0e3462fb 733 __IO uint32_t DMACSoftLBReq;
bogdanm 66:9c8f0e3462fb 734 __IO uint32_t DMACSoftLSReq;
bogdanm 66:9c8f0e3462fb 735 __IO uint32_t DMACConfig;
bogdanm 66:9c8f0e3462fb 736 __IO uint32_t DMACSync;
bogdanm 66:9c8f0e3462fb 737 } LPC_GPDMA_TypeDef;
bogdanm 66:9c8f0e3462fb 738
bogdanm 66:9c8f0e3462fb 739 typedef struct /* Channel Registers */
bogdanm 66:9c8f0e3462fb 740 {
bogdanm 66:9c8f0e3462fb 741 __IO uint32_t DMACCSrcAddr;
bogdanm 66:9c8f0e3462fb 742 __IO uint32_t DMACCDestAddr;
bogdanm 66:9c8f0e3462fb 743 __IO uint32_t DMACCLLI;
bogdanm 66:9c8f0e3462fb 744 __IO uint32_t DMACCControl;
bogdanm 66:9c8f0e3462fb 745 __IO uint32_t DMACCConfig;
bogdanm 66:9c8f0e3462fb 746 } LPC_GPDMACH_TypeDef;
bogdanm 66:9c8f0e3462fb 747
bogdanm 66:9c8f0e3462fb 748 /*------------- Universal Serial Bus (USB) -----------------------------------*/
bogdanm 66:9c8f0e3462fb 749 typedef struct
bogdanm 66:9c8f0e3462fb 750 {
bogdanm 66:9c8f0e3462fb 751 __I uint32_t HcRevision; /* USB Host Registers */
bogdanm 66:9c8f0e3462fb 752 __IO uint32_t HcControl;
bogdanm 66:9c8f0e3462fb 753 __IO uint32_t HcCommandStatus;
bogdanm 66:9c8f0e3462fb 754 __IO uint32_t HcInterruptStatus;
bogdanm 66:9c8f0e3462fb 755 __IO uint32_t HcInterruptEnable;
bogdanm 66:9c8f0e3462fb 756 __IO uint32_t HcInterruptDisable;
bogdanm 66:9c8f0e3462fb 757 __IO uint32_t HcHCCA;
bogdanm 66:9c8f0e3462fb 758 __I uint32_t HcPeriodCurrentED;
bogdanm 66:9c8f0e3462fb 759 __IO uint32_t HcControlHeadED;
bogdanm 66:9c8f0e3462fb 760 __IO uint32_t HcControlCurrentED;
bogdanm 66:9c8f0e3462fb 761 __IO uint32_t HcBulkHeadED;
bogdanm 66:9c8f0e3462fb 762 __IO uint32_t HcBulkCurrentED;
bogdanm 66:9c8f0e3462fb 763 __I uint32_t HcDoneHead;
bogdanm 66:9c8f0e3462fb 764 __IO uint32_t HcFmInterval;
bogdanm 66:9c8f0e3462fb 765 __I uint32_t HcFmRemaining;
bogdanm 66:9c8f0e3462fb 766 __I uint32_t HcFmNumber;
bogdanm 66:9c8f0e3462fb 767 __IO uint32_t HcPeriodicStart;
bogdanm 66:9c8f0e3462fb 768 __IO uint32_t HcLSTreshold;
bogdanm 66:9c8f0e3462fb 769 __IO uint32_t HcRhDescriptorA;
bogdanm 66:9c8f0e3462fb 770 __IO uint32_t HcRhDescriptorB;
bogdanm 66:9c8f0e3462fb 771 __IO uint32_t HcRhStatus;
bogdanm 66:9c8f0e3462fb 772 __IO uint32_t HcRhPortStatus1;
bogdanm 66:9c8f0e3462fb 773 __IO uint32_t HcRhPortStatus2;
bogdanm 66:9c8f0e3462fb 774 uint32_t RESERVED0[40];
bogdanm 66:9c8f0e3462fb 775 __I uint32_t Module_ID;
bogdanm 66:9c8f0e3462fb 776
bogdanm 66:9c8f0e3462fb 777 __I uint32_t OTGIntSt; /* USB On-The-Go Registers */
bogdanm 66:9c8f0e3462fb 778 __IO uint32_t OTGIntEn;
bogdanm 66:9c8f0e3462fb 779 __O uint32_t OTGIntSet;
bogdanm 66:9c8f0e3462fb 780 __O uint32_t OTGIntClr;
bogdanm 66:9c8f0e3462fb 781 __IO uint32_t OTGStCtrl;
bogdanm 66:9c8f0e3462fb 782 __IO uint32_t OTGTmr;
bogdanm 66:9c8f0e3462fb 783 uint32_t RESERVED1[58];
bogdanm 66:9c8f0e3462fb 784
bogdanm 66:9c8f0e3462fb 785 __I uint32_t USBDevIntSt; /* USB Device Interrupt Registers */
bogdanm 66:9c8f0e3462fb 786 __IO uint32_t USBDevIntEn;
bogdanm 66:9c8f0e3462fb 787 __O uint32_t USBDevIntClr;
bogdanm 66:9c8f0e3462fb 788 __O uint32_t USBDevIntSet;
bogdanm 66:9c8f0e3462fb 789
bogdanm 66:9c8f0e3462fb 790 __O uint32_t USBCmdCode; /* USB Device SIE Command Registers */
bogdanm 66:9c8f0e3462fb 791 __I uint32_t USBCmdData;
bogdanm 66:9c8f0e3462fb 792
bogdanm 66:9c8f0e3462fb 793 __I uint32_t USBRxData; /* USB Device Transfer Registers */
bogdanm 66:9c8f0e3462fb 794 __O uint32_t USBTxData;
bogdanm 66:9c8f0e3462fb 795 __I uint32_t USBRxPLen;
bogdanm 66:9c8f0e3462fb 796 __O uint32_t USBTxPLen;
bogdanm 66:9c8f0e3462fb 797 __IO uint32_t USBCtrl;
bogdanm 66:9c8f0e3462fb 798 __O uint32_t USBDevIntPri;
bogdanm 66:9c8f0e3462fb 799
bogdanm 66:9c8f0e3462fb 800 __I uint32_t USBEpIntSt; /* USB Device Endpoint Interrupt Regs */
bogdanm 66:9c8f0e3462fb 801 __IO uint32_t USBEpIntEn;
bogdanm 66:9c8f0e3462fb 802 __O uint32_t USBEpIntClr;
bogdanm 66:9c8f0e3462fb 803 __O uint32_t USBEpIntSet;
bogdanm 66:9c8f0e3462fb 804 __O uint32_t USBEpIntPri;
bogdanm 66:9c8f0e3462fb 805
bogdanm 66:9c8f0e3462fb 806 __IO uint32_t USBReEp; /* USB Device Endpoint Realization Reg*/
bogdanm 66:9c8f0e3462fb 807 __O uint32_t USBEpInd;
bogdanm 66:9c8f0e3462fb 808 __IO uint32_t USBMaxPSize;
bogdanm 66:9c8f0e3462fb 809
bogdanm 66:9c8f0e3462fb 810 __I uint32_t USBDMARSt; /* USB Device DMA Registers */
bogdanm 66:9c8f0e3462fb 811 __O uint32_t USBDMARClr;
bogdanm 66:9c8f0e3462fb 812 __O uint32_t USBDMARSet;
bogdanm 66:9c8f0e3462fb 813 uint32_t RESERVED2[9];
bogdanm 66:9c8f0e3462fb 814 __IO uint32_t USBUDCAH;
bogdanm 66:9c8f0e3462fb 815 __I uint32_t USBEpDMASt;
bogdanm 66:9c8f0e3462fb 816 __O uint32_t USBEpDMAEn;
bogdanm 66:9c8f0e3462fb 817 __O uint32_t USBEpDMADis;
bogdanm 66:9c8f0e3462fb 818 __I uint32_t USBDMAIntSt;
bogdanm 66:9c8f0e3462fb 819 __IO uint32_t USBDMAIntEn;
bogdanm 66:9c8f0e3462fb 820 uint32_t RESERVED3[2];
bogdanm 66:9c8f0e3462fb 821 __I uint32_t USBEoTIntSt;
bogdanm 66:9c8f0e3462fb 822 __O uint32_t USBEoTIntClr;
bogdanm 66:9c8f0e3462fb 823 __O uint32_t USBEoTIntSet;
bogdanm 66:9c8f0e3462fb 824 __I uint32_t USBNDDRIntSt;
bogdanm 66:9c8f0e3462fb 825 __O uint32_t USBNDDRIntClr;
bogdanm 66:9c8f0e3462fb 826 __O uint32_t USBNDDRIntSet;
bogdanm 66:9c8f0e3462fb 827 __I uint32_t USBSysErrIntSt;
bogdanm 66:9c8f0e3462fb 828 __O uint32_t USBSysErrIntClr;
bogdanm 66:9c8f0e3462fb 829 __O uint32_t USBSysErrIntSet;
bogdanm 66:9c8f0e3462fb 830 uint32_t RESERVED4[15];
bogdanm 66:9c8f0e3462fb 831
bogdanm 66:9c8f0e3462fb 832 union {
bogdanm 66:9c8f0e3462fb 833 __I uint32_t I2C_RX; /* USB OTG I2C Registers */
bogdanm 66:9c8f0e3462fb 834 __O uint32_t I2C_TX;
bogdanm 66:9c8f0e3462fb 835 };
bogdanm 66:9c8f0e3462fb 836 __I uint32_t I2C_STS;
bogdanm 66:9c8f0e3462fb 837 __IO uint32_t I2C_CTL;
bogdanm 66:9c8f0e3462fb 838 __IO uint32_t I2C_CLKHI;
bogdanm 66:9c8f0e3462fb 839 __O uint32_t I2C_CLKLO;
bogdanm 66:9c8f0e3462fb 840 uint32_t RESERVED5[824];
bogdanm 66:9c8f0e3462fb 841
bogdanm 66:9c8f0e3462fb 842 union {
bogdanm 66:9c8f0e3462fb 843 __IO uint32_t USBClkCtrl; /* USB Clock Control Registers */
bogdanm 66:9c8f0e3462fb 844 __IO uint32_t OTGClkCtrl;
bogdanm 66:9c8f0e3462fb 845 };
bogdanm 66:9c8f0e3462fb 846 union {
bogdanm 66:9c8f0e3462fb 847 __I uint32_t USBClkSt;
bogdanm 66:9c8f0e3462fb 848 __I uint32_t OTGClkSt;
bogdanm 66:9c8f0e3462fb 849 };
bogdanm 66:9c8f0e3462fb 850 } LPC_USB_TypeDef;
bogdanm 66:9c8f0e3462fb 851
bogdanm 66:9c8f0e3462fb 852 /*------------- Ethernet Media Access Controller (EMAC) ----------------------*/
bogdanm 66:9c8f0e3462fb 853 typedef struct
bogdanm 66:9c8f0e3462fb 854 {
bogdanm 66:9c8f0e3462fb 855 __IO uint32_t MAC1; /* MAC Registers */
bogdanm 66:9c8f0e3462fb 856 __IO uint32_t MAC2;
bogdanm 66:9c8f0e3462fb 857 __IO uint32_t IPGT;
bogdanm 66:9c8f0e3462fb 858 __IO uint32_t IPGR;
bogdanm 66:9c8f0e3462fb 859 __IO uint32_t CLRT;
bogdanm 66:9c8f0e3462fb 860 __IO uint32_t MAXF;
bogdanm 66:9c8f0e3462fb 861 __IO uint32_t SUPP;
bogdanm 66:9c8f0e3462fb 862 __IO uint32_t TEST;
bogdanm 66:9c8f0e3462fb 863 __IO uint32_t MCFG;
bogdanm 66:9c8f0e3462fb 864 __IO uint32_t MCMD;
bogdanm 66:9c8f0e3462fb 865 __IO uint32_t MADR;
bogdanm 66:9c8f0e3462fb 866 __O uint32_t MWTD;
bogdanm 66:9c8f0e3462fb 867 __I uint32_t MRDD;
bogdanm 66:9c8f0e3462fb 868 __I uint32_t MIND;
bogdanm 66:9c8f0e3462fb 869 uint32_t RESERVED0[2];
bogdanm 66:9c8f0e3462fb 870 __IO uint32_t SA0;
bogdanm 66:9c8f0e3462fb 871 __IO uint32_t SA1;
bogdanm 66:9c8f0e3462fb 872 __IO uint32_t SA2;
bogdanm 66:9c8f0e3462fb 873 uint32_t RESERVED1[45];
bogdanm 66:9c8f0e3462fb 874 __IO uint32_t Command; /* Control Registers */
bogdanm 66:9c8f0e3462fb 875 __I uint32_t Status;
bogdanm 66:9c8f0e3462fb 876 __IO uint32_t RxDescriptor;
bogdanm 66:9c8f0e3462fb 877 __IO uint32_t RxStatus;
bogdanm 66:9c8f0e3462fb 878 __IO uint32_t RxDescriptorNumber;
bogdanm 66:9c8f0e3462fb 879 __I uint32_t RxProduceIndex;
bogdanm 66:9c8f0e3462fb 880 __IO uint32_t RxConsumeIndex;
bogdanm 66:9c8f0e3462fb 881 __IO uint32_t TxDescriptor;
bogdanm 66:9c8f0e3462fb 882 __IO uint32_t TxStatus;
bogdanm 66:9c8f0e3462fb 883 __IO uint32_t TxDescriptorNumber;
bogdanm 66:9c8f0e3462fb 884 __IO uint32_t TxProduceIndex;
bogdanm 66:9c8f0e3462fb 885 __I uint32_t TxConsumeIndex;
bogdanm 66:9c8f0e3462fb 886 uint32_t RESERVED2[10];
bogdanm 66:9c8f0e3462fb 887 __I uint32_t TSV0;
bogdanm 66:9c8f0e3462fb 888 __I uint32_t TSV1;
bogdanm 66:9c8f0e3462fb 889 __I uint32_t RSV;
bogdanm 66:9c8f0e3462fb 890 uint32_t RESERVED3[3];
bogdanm 66:9c8f0e3462fb 891 __IO uint32_t FlowControlCounter;
bogdanm 66:9c8f0e3462fb 892 __I uint32_t FlowControlStatus;
bogdanm 66:9c8f0e3462fb 893 uint32_t RESERVED4[34];
bogdanm 66:9c8f0e3462fb 894 __IO uint32_t RxFilterCtrl; /* Rx Filter Registers */
bogdanm 66:9c8f0e3462fb 895 __IO uint32_t RxFilterWoLStatus;
bogdanm 66:9c8f0e3462fb 896 __IO uint32_t RxFilterWoLClear;
bogdanm 66:9c8f0e3462fb 897 uint32_t RESERVED5;
bogdanm 66:9c8f0e3462fb 898 __IO uint32_t HashFilterL;
bogdanm 66:9c8f0e3462fb 899 __IO uint32_t HashFilterH;
bogdanm 66:9c8f0e3462fb 900 uint32_t RESERVED6[882];
bogdanm 66:9c8f0e3462fb 901 __I uint32_t IntStatus; /* Module Control Registers */
bogdanm 66:9c8f0e3462fb 902 __IO uint32_t IntEnable;
bogdanm 66:9c8f0e3462fb 903 __O uint32_t IntClear;
bogdanm 66:9c8f0e3462fb 904 __O uint32_t IntSet;
bogdanm 66:9c8f0e3462fb 905 uint32_t RESERVED7;
bogdanm 66:9c8f0e3462fb 906 __IO uint32_t PowerDown;
bogdanm 66:9c8f0e3462fb 907 uint32_t RESERVED8;
bogdanm 66:9c8f0e3462fb 908 __IO uint32_t Module_ID;
bogdanm 66:9c8f0e3462fb 909 } LPC_EMAC_TypeDef;
bogdanm 66:9c8f0e3462fb 910
bogdanm 66:9c8f0e3462fb 911 #if defined ( __CC_ARM )
bogdanm 66:9c8f0e3462fb 912 #pragma no_anon_unions
bogdanm 66:9c8f0e3462fb 913 #endif
bogdanm 66:9c8f0e3462fb 914
bogdanm 66:9c8f0e3462fb 915
bogdanm 66:9c8f0e3462fb 916 /******************************************************************************/
bogdanm 66:9c8f0e3462fb 917 /* Peripheral memory map */
bogdanm 66:9c8f0e3462fb 918 /******************************************************************************/
bogdanm 66:9c8f0e3462fb 919 /* Base addresses */
bogdanm 66:9c8f0e3462fb 920 #define LPC_FLASH_BASE (0x00000000UL)
bogdanm 66:9c8f0e3462fb 921 #define LPC_RAM_BASE (0x10000000UL)
bogdanm 66:9c8f0e3462fb 922 #define LPC_GPIO_BASE (0x2009C000UL)
bogdanm 66:9c8f0e3462fb 923 #define LPC_APB0_BASE (0x40000000UL)
bogdanm 66:9c8f0e3462fb 924 #define LPC_APB1_BASE (0x40080000UL)
bogdanm 66:9c8f0e3462fb 925 #define LPC_AHB_BASE (0x50000000UL)
bogdanm 66:9c8f0e3462fb 926 #define LPC_CM3_BASE (0xE0000000UL)
bogdanm 66:9c8f0e3462fb 927
bogdanm 66:9c8f0e3462fb 928 /* APB0 peripherals */
bogdanm 66:9c8f0e3462fb 929 #define LPC_WDT_BASE (LPC_APB0_BASE + 0x00000)
bogdanm 66:9c8f0e3462fb 930 #define LPC_TIM0_BASE (LPC_APB0_BASE + 0x04000)
bogdanm 66:9c8f0e3462fb 931 #define LPC_TIM1_BASE (LPC_APB0_BASE + 0x08000)
bogdanm 66:9c8f0e3462fb 932 #define LPC_UART0_BASE (LPC_APB0_BASE + 0x0C000)
bogdanm 66:9c8f0e3462fb 933 #define LPC_UART1_BASE (LPC_APB0_BASE + 0x10000)
bogdanm 66:9c8f0e3462fb 934 #define LPC_PWM1_BASE (LPC_APB0_BASE + 0x18000)
bogdanm 66:9c8f0e3462fb 935 #define LPC_I2C0_BASE (LPC_APB0_BASE + 0x1C000)
bogdanm 66:9c8f0e3462fb 936 #define LPC_SPI_BASE (LPC_APB0_BASE + 0x20000)
bogdanm 66:9c8f0e3462fb 937 #define LPC_RTC_BASE (LPC_APB0_BASE + 0x24000)
bogdanm 66:9c8f0e3462fb 938 #define LPC_GPIOINT_BASE (LPC_APB0_BASE + 0x28080)
bogdanm 66:9c8f0e3462fb 939 #define LPC_PINCON_BASE (LPC_APB0_BASE + 0x2C000)
bogdanm 66:9c8f0e3462fb 940 #define LPC_SSP1_BASE (LPC_APB0_BASE + 0x30000)
bogdanm 66:9c8f0e3462fb 941 #define LPC_ADC_BASE (LPC_APB0_BASE + 0x34000)
bogdanm 66:9c8f0e3462fb 942 #define LPC_CANAF_RAM_BASE (LPC_APB0_BASE + 0x38000)
bogdanm 66:9c8f0e3462fb 943 #define LPC_CANAF_BASE (LPC_APB0_BASE + 0x3C000)
bogdanm 66:9c8f0e3462fb 944 #define LPC_CANCR_BASE (LPC_APB0_BASE + 0x40000)
bogdanm 66:9c8f0e3462fb 945 #define LPC_CAN1_BASE (LPC_APB0_BASE + 0x44000)
bogdanm 66:9c8f0e3462fb 946 #define LPC_CAN2_BASE (LPC_APB0_BASE + 0x48000)
bogdanm 66:9c8f0e3462fb 947 #define LPC_I2C1_BASE (LPC_APB0_BASE + 0x5C000)
bogdanm 66:9c8f0e3462fb 948
bogdanm 66:9c8f0e3462fb 949 /* APB1 peripherals */
bogdanm 66:9c8f0e3462fb 950 #define LPC_SSP0_BASE (LPC_APB1_BASE + 0x08000)
bogdanm 66:9c8f0e3462fb 951 #define LPC_DAC_BASE (LPC_APB1_BASE + 0x0C000)
bogdanm 66:9c8f0e3462fb 952 #define LPC_TIM2_BASE (LPC_APB1_BASE + 0x10000)
bogdanm 66:9c8f0e3462fb 953 #define LPC_TIM3_BASE (LPC_APB1_BASE + 0x14000)
bogdanm 66:9c8f0e3462fb 954 #define LPC_UART2_BASE (LPC_APB1_BASE + 0x18000)
bogdanm 66:9c8f0e3462fb 955 #define LPC_UART3_BASE (LPC_APB1_BASE + 0x1C000)
bogdanm 66:9c8f0e3462fb 956 #define LPC_I2C2_BASE (LPC_APB1_BASE + 0x20000)
bogdanm 66:9c8f0e3462fb 957 #define LPC_I2S_BASE (LPC_APB1_BASE + 0x28000)
bogdanm 66:9c8f0e3462fb 958 #define LPC_RIT_BASE (LPC_APB1_BASE + 0x30000)
bogdanm 66:9c8f0e3462fb 959 #define LPC_MCPWM_BASE (LPC_APB1_BASE + 0x38000)
bogdanm 66:9c8f0e3462fb 960 #define LPC_QEI_BASE (LPC_APB1_BASE + 0x3C000)
bogdanm 66:9c8f0e3462fb 961 #define LPC_SC_BASE (LPC_APB1_BASE + 0x7C000)
bogdanm 66:9c8f0e3462fb 962
bogdanm 66:9c8f0e3462fb 963 /* AHB peripherals */
bogdanm 66:9c8f0e3462fb 964 #define LPC_EMAC_BASE (LPC_AHB_BASE + 0x00000)
bogdanm 66:9c8f0e3462fb 965 #define LPC_GPDMA_BASE (LPC_AHB_BASE + 0x04000)
bogdanm 66:9c8f0e3462fb 966 #define LPC_GPDMACH0_BASE (LPC_AHB_BASE + 0x04100)
bogdanm 66:9c8f0e3462fb 967 #define LPC_GPDMACH1_BASE (LPC_AHB_BASE + 0x04120)
bogdanm 66:9c8f0e3462fb 968 #define LPC_GPDMACH2_BASE (LPC_AHB_BASE + 0x04140)
bogdanm 66:9c8f0e3462fb 969 #define LPC_GPDMACH3_BASE (LPC_AHB_BASE + 0x04160)
bogdanm 66:9c8f0e3462fb 970 #define LPC_GPDMACH4_BASE (LPC_AHB_BASE + 0x04180)
bogdanm 66:9c8f0e3462fb 971 #define LPC_GPDMACH5_BASE (LPC_AHB_BASE + 0x041A0)
bogdanm 66:9c8f0e3462fb 972 #define LPC_GPDMACH6_BASE (LPC_AHB_BASE + 0x041C0)
bogdanm 66:9c8f0e3462fb 973 #define LPC_GPDMACH7_BASE (LPC_AHB_BASE + 0x041E0)
bogdanm 66:9c8f0e3462fb 974 #define LPC_USB_BASE (LPC_AHB_BASE + 0x0C000)
bogdanm 66:9c8f0e3462fb 975
bogdanm 66:9c8f0e3462fb 976 /* GPIOs */
bogdanm 66:9c8f0e3462fb 977 #define LPC_GPIO0_BASE (LPC_GPIO_BASE + 0x00000)
bogdanm 66:9c8f0e3462fb 978 #define LPC_GPIO1_BASE (LPC_GPIO_BASE + 0x00020)
bogdanm 66:9c8f0e3462fb 979 #define LPC_GPIO2_BASE (LPC_GPIO_BASE + 0x00040)
bogdanm 66:9c8f0e3462fb 980 #define LPC_GPIO3_BASE (LPC_GPIO_BASE + 0x00060)
bogdanm 66:9c8f0e3462fb 981 #define LPC_GPIO4_BASE (LPC_GPIO_BASE + 0x00080)
bogdanm 66:9c8f0e3462fb 982
bogdanm 66:9c8f0e3462fb 983
bogdanm 66:9c8f0e3462fb 984 /******************************************************************************/
bogdanm 66:9c8f0e3462fb 985 /* Peripheral declaration */
bogdanm 66:9c8f0e3462fb 986 /******************************************************************************/
bogdanm 66:9c8f0e3462fb 987 #define LPC_SC ((LPC_SC_TypeDef *) LPC_SC_BASE )
bogdanm 66:9c8f0e3462fb 988 #define LPC_GPIO0 ((LPC_GPIO_TypeDef *) LPC_GPIO0_BASE )
bogdanm 66:9c8f0e3462fb 989 #define LPC_GPIO1 ((LPC_GPIO_TypeDef *) LPC_GPIO1_BASE )
bogdanm 66:9c8f0e3462fb 990 #define LPC_GPIO2 ((LPC_GPIO_TypeDef *) LPC_GPIO2_BASE )
bogdanm 66:9c8f0e3462fb 991 #define LPC_GPIO3 ((LPC_GPIO_TypeDef *) LPC_GPIO3_BASE )
bogdanm 66:9c8f0e3462fb 992 #define LPC_GPIO4 ((LPC_GPIO_TypeDef *) LPC_GPIO4_BASE )
bogdanm 66:9c8f0e3462fb 993 #define LPC_WDT ((LPC_WDT_TypeDef *) LPC_WDT_BASE )
bogdanm 66:9c8f0e3462fb 994 #define LPC_TIM0 ((LPC_TIM_TypeDef *) LPC_TIM0_BASE )
bogdanm 66:9c8f0e3462fb 995 #define LPC_TIM1 ((LPC_TIM_TypeDef *) LPC_TIM1_BASE )
bogdanm 66:9c8f0e3462fb 996 #define LPC_TIM2 ((LPC_TIM_TypeDef *) LPC_TIM2_BASE )
bogdanm 66:9c8f0e3462fb 997 #define LPC_TIM3 ((LPC_TIM_TypeDef *) LPC_TIM3_BASE )
bogdanm 66:9c8f0e3462fb 998 #define LPC_RIT ((LPC_RIT_TypeDef *) LPC_RIT_BASE )
bogdanm 66:9c8f0e3462fb 999 #define LPC_UART0 ((LPC_UART0_TypeDef *) LPC_UART0_BASE )
bogdanm 66:9c8f0e3462fb 1000 #define LPC_UART1 ((LPC_UART1_TypeDef *) LPC_UART1_BASE )
bogdanm 66:9c8f0e3462fb 1001 #define LPC_UART2 ((LPC_UART_TypeDef *) LPC_UART2_BASE )
bogdanm 66:9c8f0e3462fb 1002 #define LPC_UART3 ((LPC_UART_TypeDef *) LPC_UART3_BASE )
bogdanm 66:9c8f0e3462fb 1003 #define LPC_PWM1 ((LPC_PWM_TypeDef *) LPC_PWM1_BASE )
bogdanm 66:9c8f0e3462fb 1004 #define LPC_I2C0 ((LPC_I2C_TypeDef *) LPC_I2C0_BASE )
bogdanm 66:9c8f0e3462fb 1005 #define LPC_I2C1 ((LPC_I2C_TypeDef *) LPC_I2C1_BASE )
bogdanm 66:9c8f0e3462fb 1006 #define LPC_I2C2 ((LPC_I2C_TypeDef *) LPC_I2C2_BASE )
bogdanm 66:9c8f0e3462fb 1007 #define LPC_I2S ((LPC_I2S_TypeDef *) LPC_I2S_BASE )
bogdanm 66:9c8f0e3462fb 1008 #define LPC_SPI ((LPC_SPI_TypeDef *) LPC_SPI_BASE )
bogdanm 66:9c8f0e3462fb 1009 #define LPC_RTC ((LPC_RTC_TypeDef *) LPC_RTC_BASE )
bogdanm 66:9c8f0e3462fb 1010 #define LPC_GPIOINT ((LPC_GPIOINT_TypeDef *) LPC_GPIOINT_BASE )
bogdanm 66:9c8f0e3462fb 1011 #define LPC_PINCON ((LPC_PINCON_TypeDef *) LPC_PINCON_BASE )
bogdanm 66:9c8f0e3462fb 1012 #define LPC_SSP0 ((LPC_SSP_TypeDef *) LPC_SSP0_BASE )
bogdanm 66:9c8f0e3462fb 1013 #define LPC_SSP1 ((LPC_SSP_TypeDef *) LPC_SSP1_BASE )
bogdanm 66:9c8f0e3462fb 1014 #define LPC_ADC ((LPC_ADC_TypeDef *) LPC_ADC_BASE )
bogdanm 66:9c8f0e3462fb 1015 #define LPC_DAC ((LPC_DAC_TypeDef *) LPC_DAC_BASE )
bogdanm 66:9c8f0e3462fb 1016 #define LPC_CANAF_RAM ((LPC_CANAF_RAM_TypeDef *) LPC_CANAF_RAM_BASE)
bogdanm 66:9c8f0e3462fb 1017 #define LPC_CANAF ((LPC_CANAF_TypeDef *) LPC_CANAF_BASE )
bogdanm 66:9c8f0e3462fb 1018 #define LPC_CANCR ((LPC_CANCR_TypeDef *) LPC_CANCR_BASE )
bogdanm 66:9c8f0e3462fb 1019 #define LPC_CAN1 ((LPC_CAN_TypeDef *) LPC_CAN1_BASE )
bogdanm 66:9c8f0e3462fb 1020 #define LPC_CAN2 ((LPC_CAN_TypeDef *) LPC_CAN2_BASE )
bogdanm 66:9c8f0e3462fb 1021 #define LPC_MCPWM ((LPC_MCPWM_TypeDef *) LPC_MCPWM_BASE )
bogdanm 66:9c8f0e3462fb 1022 #define LPC_QEI ((LPC_QEI_TypeDef *) LPC_QEI_BASE )
bogdanm 66:9c8f0e3462fb 1023 #define LPC_EMAC ((LPC_EMAC_TypeDef *) LPC_EMAC_BASE )
bogdanm 66:9c8f0e3462fb 1024 #define LPC_GPDMA ((LPC_GPDMA_TypeDef *) LPC_GPDMA_BASE )
bogdanm 66:9c8f0e3462fb 1025 #define LPC_GPDMACH0 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH0_BASE )
bogdanm 66:9c8f0e3462fb 1026 #define LPC_GPDMACH1 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH1_BASE )
bogdanm 66:9c8f0e3462fb 1027 #define LPC_GPDMACH2 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH2_BASE )
bogdanm 66:9c8f0e3462fb 1028 #define LPC_GPDMACH3 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH3_BASE )
bogdanm 66:9c8f0e3462fb 1029 #define LPC_GPDMACH4 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH4_BASE )
bogdanm 66:9c8f0e3462fb 1030 #define LPC_GPDMACH5 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH5_BASE )
bogdanm 66:9c8f0e3462fb 1031 #define LPC_GPDMACH6 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH6_BASE )
bogdanm 66:9c8f0e3462fb 1032 #define LPC_GPDMACH7 ((LPC_GPDMACH_TypeDef *) LPC_GPDMACH7_BASE )
bogdanm 66:9c8f0e3462fb 1033 #define LPC_USB ((LPC_USB_TypeDef *) LPC_USB_BASE )
bogdanm 66:9c8f0e3462fb 1034
bogdanm 66:9c8f0e3462fb 1035 #endif // __LPC17xx_H__