Filippo Casamassima / mbed

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TARGET_NUCLEO_F334R8/stm32f3xx_hal_dma.h@86:04dd9b1680ae, 2014-07-02 (annotated)

Committer:
bogdanm
Date:
Wed Jul 02 13:22:23 2014 +0100
Revision:
86:04dd9b1680ae
Child:
92:4fc01daae5a5
Release 86 of the mbed library



Main changes:





- bug fixes in various backends

- mbed "error" replaced by assert logic (mbed_assert)

- new ST Nucleo targets

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 86:04dd9b1680ae 1 /**
bogdanm 86:04dd9b1680ae 2 ******************************************************************************
bogdanm 86:04dd9b1680ae 3 * @file stm32f3xx_hal_dma.h
bogdanm 86:04dd9b1680ae 4 * @author MCD Application Team
bogdanm 86:04dd9b1680ae 5 * @version V1.0.1
bogdanm 86:04dd9b1680ae 6 * @date 18-June-2014
bogdanm 86:04dd9b1680ae 7 * @brief Header file of DMA HAL module.
bogdanm 86:04dd9b1680ae 8 ******************************************************************************
bogdanm 86:04dd9b1680ae 9 * @attention
bogdanm 86:04dd9b1680ae 10 *
bogdanm 86:04dd9b1680ae 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 86:04dd9b1680ae 12 *
bogdanm 86:04dd9b1680ae 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 86:04dd9b1680ae 14 * are permitted provided that the following conditions are met:
bogdanm 86:04dd9b1680ae 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 86:04dd9b1680ae 16 * this list of conditions and the following disclaimer.
bogdanm 86:04dd9b1680ae 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 86:04dd9b1680ae 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 86:04dd9b1680ae 19 * and/or other materials provided with the distribution.
bogdanm 86:04dd9b1680ae 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 86:04dd9b1680ae 21 * may be used to endorse or promote products derived from this software
bogdanm 86:04dd9b1680ae 22 * without specific prior written permission.
bogdanm 86:04dd9b1680ae 23 *
bogdanm 86:04dd9b1680ae 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 86:04dd9b1680ae 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 86:04dd9b1680ae 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 86:04dd9b1680ae 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 86:04dd9b1680ae 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 86:04dd9b1680ae 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 86:04dd9b1680ae 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 86:04dd9b1680ae 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 86:04dd9b1680ae 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 86:04dd9b1680ae 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 86:04dd9b1680ae 34 *
bogdanm 86:04dd9b1680ae 35 ******************************************************************************
bogdanm 86:04dd9b1680ae 36 */
bogdanm 86:04dd9b1680ae 37
bogdanm 86:04dd9b1680ae 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 86:04dd9b1680ae 39 #ifndef __STM32F3xx_HAL_DMA_H
bogdanm 86:04dd9b1680ae 40 #define __STM32F3xx_HAL_DMA_H
bogdanm 86:04dd9b1680ae 41
bogdanm 86:04dd9b1680ae 42 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 43 extern "C" {
bogdanm 86:04dd9b1680ae 44 #endif
bogdanm 86:04dd9b1680ae 45
bogdanm 86:04dd9b1680ae 46 /* Includes ------------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 47 #include "stm32f3xx_hal_def.h"
bogdanm 86:04dd9b1680ae 48
bogdanm 86:04dd9b1680ae 49 /** @addtogroup STM32F3xx_HAL_Driver
bogdanm 86:04dd9b1680ae 50 * @{
bogdanm 86:04dd9b1680ae 51 */
bogdanm 86:04dd9b1680ae 52
bogdanm 86:04dd9b1680ae 53 /** @addtogroup DMA
bogdanm 86:04dd9b1680ae 54 * @{
bogdanm 86:04dd9b1680ae 55 */
bogdanm 86:04dd9b1680ae 56
bogdanm 86:04dd9b1680ae 57 /* Exported types ------------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 58
bogdanm 86:04dd9b1680ae 59 /**
bogdanm 86:04dd9b1680ae 60 * @brief DMA Configuration Structure definition
bogdanm 86:04dd9b1680ae 61 */
bogdanm 86:04dd9b1680ae 62 typedef struct
bogdanm 86:04dd9b1680ae 63 {
bogdanm 86:04dd9b1680ae 64 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
bogdanm 86:04dd9b1680ae 65 from memory to memory or from peripheral to memory.
bogdanm 86:04dd9b1680ae 66 This parameter can be a value of @ref DMA_Data_transfer_direction */
bogdanm 86:04dd9b1680ae 67
bogdanm 86:04dd9b1680ae 68 uint32_t PeriphInc; /*!< Specifies whether the Peripheral address register should be incremented or not.
bogdanm 86:04dd9b1680ae 69 This parameter can be a value of @ref DMA_Peripheral_incremented_mode */
bogdanm 86:04dd9b1680ae 70
bogdanm 86:04dd9b1680ae 71 uint32_t MemInc; /*!< Specifies whether the memory address register should be incremented or not.
bogdanm 86:04dd9b1680ae 72 This parameter can be a value of @ref DMA_Memory_incremented_mode */
bogdanm 86:04dd9b1680ae 73
bogdanm 86:04dd9b1680ae 74 uint32_t PeriphDataAlignment; /*!< Specifies the Peripheral data width.
bogdanm 86:04dd9b1680ae 75 This parameter can be a value of @ref DMA_Peripheral_data_size */
bogdanm 86:04dd9b1680ae 76
bogdanm 86:04dd9b1680ae 77 uint32_t MemDataAlignment; /*!< Specifies the Memory data width.
bogdanm 86:04dd9b1680ae 78 This parameter can be a value of @ref DMA_Memory_data_size */
bogdanm 86:04dd9b1680ae 79
bogdanm 86:04dd9b1680ae 80 uint32_t Mode; /*!< Specifies the operation mode of the DMAy Channelx.
bogdanm 86:04dd9b1680ae 81 This parameter can be a value of @ref DMA_mode
bogdanm 86:04dd9b1680ae 82 @note The circular buffer mode cannot be used if the memory-to-memory
bogdanm 86:04dd9b1680ae 83 data transfer is configured on the selected Channel */
bogdanm 86:04dd9b1680ae 84
bogdanm 86:04dd9b1680ae 85 uint32_t Priority; /*!< Specifies the software priority for the DMAy Channelx.
bogdanm 86:04dd9b1680ae 86 This parameter can be a value of @ref DMA_Priority_level */
bogdanm 86:04dd9b1680ae 87
bogdanm 86:04dd9b1680ae 88 } DMA_InitTypeDef;
bogdanm 86:04dd9b1680ae 89
bogdanm 86:04dd9b1680ae 90 /**
bogdanm 86:04dd9b1680ae 91 * @brief DMA Configuration enumeration values definition
bogdanm 86:04dd9b1680ae 92 */
bogdanm 86:04dd9b1680ae 93 typedef enum
bogdanm 86:04dd9b1680ae 94 {
bogdanm 86:04dd9b1680ae 95 DMA_MODE = 0, /*!< Control related DMA mode Parameter in DMA_InitTypeDef */
bogdanm 86:04dd9b1680ae 96 DMA_PRIORITY = 1, /*!< Control related priority level Parameter in DMA_InitTypeDef */
bogdanm 86:04dd9b1680ae 97
bogdanm 86:04dd9b1680ae 98 } DMA_ControlTypeDef;
bogdanm 86:04dd9b1680ae 99
bogdanm 86:04dd9b1680ae 100 /**
bogdanm 86:04dd9b1680ae 101 * @brief HAL DMA State structures definition
bogdanm 86:04dd9b1680ae 102 */
bogdanm 86:04dd9b1680ae 103 typedef enum
bogdanm 86:04dd9b1680ae 104 {
bogdanm 86:04dd9b1680ae 105 HAL_DMA_STATE_RESET = 0x00, /*!< DMA not yet initialized or disabled */
bogdanm 86:04dd9b1680ae 106 HAL_DMA_STATE_READY = 0x01, /*!< DMA process success and ready for use */
bogdanm 86:04dd9b1680ae 107 HAL_DMA_STATE_READY_HALF = 0x11, /*!< DMA Half process success */
bogdanm 86:04dd9b1680ae 108 HAL_DMA_STATE_BUSY = 0x02, /*!< DMA process is ongoing */
bogdanm 86:04dd9b1680ae 109 HAL_DMA_STATE_TIMEOUT = 0x03, /*!< DMA timeout state */
bogdanm 86:04dd9b1680ae 110 HAL_DMA_STATE_ERROR = 0x04, /*!< DMA error state */
bogdanm 86:04dd9b1680ae 111
bogdanm 86:04dd9b1680ae 112 }HAL_DMA_StateTypeDef;
bogdanm 86:04dd9b1680ae 113
bogdanm 86:04dd9b1680ae 114 /**
bogdanm 86:04dd9b1680ae 115 * @brief HAL DMA Error Code structure definition
bogdanm 86:04dd9b1680ae 116 */
bogdanm 86:04dd9b1680ae 117 typedef enum
bogdanm 86:04dd9b1680ae 118 {
bogdanm 86:04dd9b1680ae 119 HAL_DMA_FULL_TRANSFER = 0x00, /*!< Full transfer */
bogdanm 86:04dd9b1680ae 120 HAL_DMA_HALF_TRANSFER = 0x01, /*!< Half Transfer */
bogdanm 86:04dd9b1680ae 121
bogdanm 86:04dd9b1680ae 122 }HAL_DMA_LevelCompleteTypeDef;
bogdanm 86:04dd9b1680ae 123
bogdanm 86:04dd9b1680ae 124
bogdanm 86:04dd9b1680ae 125 /**
bogdanm 86:04dd9b1680ae 126 * @brief DMA handle Structure definition
bogdanm 86:04dd9b1680ae 127 */
bogdanm 86:04dd9b1680ae 128 typedef struct __DMA_HandleTypeDef
bogdanm 86:04dd9b1680ae 129 {
bogdanm 86:04dd9b1680ae 130 DMA_Channel_TypeDef *Instance; /*!< Register base address */
bogdanm 86:04dd9b1680ae 131
bogdanm 86:04dd9b1680ae 132 DMA_InitTypeDef Init; /*!< DMA communication parameters */
bogdanm 86:04dd9b1680ae 133
bogdanm 86:04dd9b1680ae 134 HAL_LockTypeDef Lock; /*!< DMA locking object */
bogdanm 86:04dd9b1680ae 135
bogdanm 86:04dd9b1680ae 136 HAL_DMA_StateTypeDef State; /*!< DMA transfer state */
bogdanm 86:04dd9b1680ae 137
bogdanm 86:04dd9b1680ae 138 void *Parent; /*!< Parent object state */
bogdanm 86:04dd9b1680ae 139
bogdanm 86:04dd9b1680ae 140 void (* XferCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer complete callback */
bogdanm 86:04dd9b1680ae 141
bogdanm 86:04dd9b1680ae 142 void (* XferHalfCpltCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA Half transfer complete callback */
bogdanm 86:04dd9b1680ae 143
bogdanm 86:04dd9b1680ae 144 void (* XferErrorCallback)( struct __DMA_HandleTypeDef * hdma); /*!< DMA transfer error callback */
bogdanm 86:04dd9b1680ae 145
bogdanm 86:04dd9b1680ae 146 __IO uint32_t ErrorCode; /*!< DMA Error code */
bogdanm 86:04dd9b1680ae 147
bogdanm 86:04dd9b1680ae 148 } DMA_HandleTypeDef;
bogdanm 86:04dd9b1680ae 149
bogdanm 86:04dd9b1680ae 150 /* Exported constants --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 151
bogdanm 86:04dd9b1680ae 152 /** @defgroup DMA_Exported_Constants
bogdanm 86:04dd9b1680ae 153 * @{
bogdanm 86:04dd9b1680ae 154 */
bogdanm 86:04dd9b1680ae 155
bogdanm 86:04dd9b1680ae 156 /** @defgroup DMA_Error_Code
bogdanm 86:04dd9b1680ae 157 * @{
bogdanm 86:04dd9b1680ae 158 */
bogdanm 86:04dd9b1680ae 159 #define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000) /*!< No error */
bogdanm 86:04dd9b1680ae 160 #define HAL_DMA_ERROR_TE ((uint32_t)0x00000001) /*!< Transfer error */
bogdanm 86:04dd9b1680ae 161 #define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020) /*!< Timeout error */
bogdanm 86:04dd9b1680ae 162 /**
bogdanm 86:04dd9b1680ae 163 * @}
bogdanm 86:04dd9b1680ae 164 */
bogdanm 86:04dd9b1680ae 165
bogdanm 86:04dd9b1680ae 166
bogdanm 86:04dd9b1680ae 167 /** @defgroup DMA_Data_transfer_direction
bogdanm 86:04dd9b1680ae 168 * @{
bogdanm 86:04dd9b1680ae 169 */
bogdanm 86:04dd9b1680ae 170 #define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000) /*!< Peripheral to memory direction */
bogdanm 86:04dd9b1680ae 171 #define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_CCR_DIR) /*!< Memory to peripheral direction */
bogdanm 86:04dd9b1680ae 172 #define DMA_MEMORY_TO_MEMORY ((uint32_t)(DMA_CCR_MEM2MEM)) /*!< Memory to memory direction */
bogdanm 86:04dd9b1680ae 173
bogdanm 86:04dd9b1680ae 174 #define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_PERIPH_TO_MEMORY ) || \
bogdanm 86:04dd9b1680ae 175 ((DIRECTION) == DMA_MEMORY_TO_PERIPH) || \
bogdanm 86:04dd9b1680ae 176 ((DIRECTION) == DMA_MEMORY_TO_MEMORY))
bogdanm 86:04dd9b1680ae 177 /**
bogdanm 86:04dd9b1680ae 178 * @}
bogdanm 86:04dd9b1680ae 179 */
bogdanm 86:04dd9b1680ae 180
bogdanm 86:04dd9b1680ae 181 /** @defgroup DMA_Data_buffer_size
bogdanm 86:04dd9b1680ae 182 * @{
bogdanm 86:04dd9b1680ae 183 */
bogdanm 86:04dd9b1680ae 184 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
bogdanm 86:04dd9b1680ae 185 /**
bogdanm 86:04dd9b1680ae 186 * @}
bogdanm 86:04dd9b1680ae 187 */
bogdanm 86:04dd9b1680ae 188
bogdanm 86:04dd9b1680ae 189 /** @defgroup DMA_Peripheral_incremented_mode
bogdanm 86:04dd9b1680ae 190 * @{
bogdanm 86:04dd9b1680ae 191 */
bogdanm 86:04dd9b1680ae 192 #define DMA_PINC_ENABLE ((uint32_t)DMA_CCR_PINC) /*!< Peripheral increment mode Enable */
bogdanm 86:04dd9b1680ae 193 #define DMA_PINC_DISABLE ((uint32_t)0x00000000) /*!< Peripheral increment mode Disable */
bogdanm 86:04dd9b1680ae 194
bogdanm 86:04dd9b1680ae 195 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PINC_ENABLE) || \
bogdanm 86:04dd9b1680ae 196 ((STATE) == DMA_PINC_DISABLE))
bogdanm 86:04dd9b1680ae 197 /**
bogdanm 86:04dd9b1680ae 198 * @}
bogdanm 86:04dd9b1680ae 199 */
bogdanm 86:04dd9b1680ae 200
bogdanm 86:04dd9b1680ae 201 /** @defgroup DMA_Memory_incremented_mode
bogdanm 86:04dd9b1680ae 202 * @{
bogdanm 86:04dd9b1680ae 203 */
bogdanm 86:04dd9b1680ae 204 #define DMA_MINC_ENABLE ((uint32_t)DMA_CCR_MINC) /*!< Memory increment mode Enable */
bogdanm 86:04dd9b1680ae 205 #define DMA_MINC_DISABLE ((uint32_t)0x00000000) /*!< Memory increment mode Disable */
bogdanm 86:04dd9b1680ae 206
bogdanm 86:04dd9b1680ae 207 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MINC_ENABLE) || \
bogdanm 86:04dd9b1680ae 208 ((STATE) == DMA_MINC_DISABLE))
bogdanm 86:04dd9b1680ae 209 /**
bogdanm 86:04dd9b1680ae 210 * @}
bogdanm 86:04dd9b1680ae 211 */
bogdanm 86:04dd9b1680ae 212
bogdanm 86:04dd9b1680ae 213 /** @defgroup DMA_Peripheral_data_size
bogdanm 86:04dd9b1680ae 214 * @{
bogdanm 86:04dd9b1680ae 215 */
bogdanm 86:04dd9b1680ae 216 #define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Peripheral data alignment : Byte */
bogdanm 86:04dd9b1680ae 217 #define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_PSIZE_0) /*!< Peripheral data alignment : HalfWord */
bogdanm 86:04dd9b1680ae 218 #define DMA_PDATAALIGN_WORD ((uint32_t)DMA_CCR_PSIZE_1) /*!< Peripheral data alignment : Word */
bogdanm 86:04dd9b1680ae 219
bogdanm 86:04dd9b1680ae 220 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PDATAALIGN_BYTE) || \
bogdanm 86:04dd9b1680ae 221 ((SIZE) == DMA_PDATAALIGN_HALFWORD) || \
bogdanm 86:04dd9b1680ae 222 ((SIZE) == DMA_PDATAALIGN_WORD))
bogdanm 86:04dd9b1680ae 223 /**
bogdanm 86:04dd9b1680ae 224 * @}
bogdanm 86:04dd9b1680ae 225 */
bogdanm 86:04dd9b1680ae 226
bogdanm 86:04dd9b1680ae 227
bogdanm 86:04dd9b1680ae 228 /** @defgroup DMA_Memory_data_size
bogdanm 86:04dd9b1680ae 229 * @{
bogdanm 86:04dd9b1680ae 230 */
bogdanm 86:04dd9b1680ae 231 #define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000) /*!< Memory data alignment : Byte */
bogdanm 86:04dd9b1680ae 232 #define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_CCR_MSIZE_0) /*!< Memory data alignment : HalfWord */
bogdanm 86:04dd9b1680ae 233 #define DMA_MDATAALIGN_WORD ((uint32_t)DMA_CCR_MSIZE_1) /*!< Memory data alignment : Word */
bogdanm 86:04dd9b1680ae 234
bogdanm 86:04dd9b1680ae 235 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MDATAALIGN_BYTE) || \
bogdanm 86:04dd9b1680ae 236 ((SIZE) == DMA_MDATAALIGN_HALFWORD) || \
bogdanm 86:04dd9b1680ae 237 ((SIZE) == DMA_MDATAALIGN_WORD ))
bogdanm 86:04dd9b1680ae 238 /**
bogdanm 86:04dd9b1680ae 239 * @}
bogdanm 86:04dd9b1680ae 240 */
bogdanm 86:04dd9b1680ae 241
bogdanm 86:04dd9b1680ae 242 /** @defgroup DMA_mode
bogdanm 86:04dd9b1680ae 243 * @{
bogdanm 86:04dd9b1680ae 244 */
bogdanm 86:04dd9b1680ae 245 #define DMA_NORMAL ((uint32_t)0x00000000) /*!< Normal Mode */
bogdanm 86:04dd9b1680ae 246 #define DMA_CIRCULAR ((uint32_t)DMA_CCR_CIRC) /*!< Circular Mode */
bogdanm 86:04dd9b1680ae 247
bogdanm 86:04dd9b1680ae 248 #define IS_DMA_MODE(MODE) (((MODE) == DMA_NORMAL ) || \
bogdanm 86:04dd9b1680ae 249 ((MODE) == DMA_CIRCULAR))
bogdanm 86:04dd9b1680ae 250 /**
bogdanm 86:04dd9b1680ae 251 * @}
bogdanm 86:04dd9b1680ae 252 */
bogdanm 86:04dd9b1680ae 253
bogdanm 86:04dd9b1680ae 254 /** @defgroup DMA_Priority_level
bogdanm 86:04dd9b1680ae 255 * @{
bogdanm 86:04dd9b1680ae 256 */
bogdanm 86:04dd9b1680ae 257 #define DMA_PRIORITY_LOW ((uint32_t)0x00000000) /*!< Priority level : Low */
bogdanm 86:04dd9b1680ae 258 #define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_CCR_PL_0) /*!< Priority level : Medium */
bogdanm 86:04dd9b1680ae 259 #define DMA_PRIORITY_HIGH ((uint32_t)DMA_CCR_PL_1) /*!< Priority level : High */
bogdanm 86:04dd9b1680ae 260 #define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_CCR_PL) /*!< Priority level : Very_High */
bogdanm 86:04dd9b1680ae 261
bogdanm 86:04dd9b1680ae 262 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_PRIORITY_LOW ) || \
bogdanm 86:04dd9b1680ae 263 ((PRIORITY) == DMA_PRIORITY_MEDIUM) || \
bogdanm 86:04dd9b1680ae 264 ((PRIORITY) == DMA_PRIORITY_HIGH) || \
bogdanm 86:04dd9b1680ae 265 ((PRIORITY) == DMA_PRIORITY_VERY_HIGH))
bogdanm 86:04dd9b1680ae 266 /**
bogdanm 86:04dd9b1680ae 267 * @}
bogdanm 86:04dd9b1680ae 268 */
bogdanm 86:04dd9b1680ae 269
bogdanm 86:04dd9b1680ae 270
bogdanm 86:04dd9b1680ae 271 /** @defgroup DMA_interrupt_enable_definitions
bogdanm 86:04dd9b1680ae 272 * @{
bogdanm 86:04dd9b1680ae 273 */
bogdanm 86:04dd9b1680ae 274
bogdanm 86:04dd9b1680ae 275 #define DMA_IT_TC ((uint32_t)DMA_CCR_TCIE)
bogdanm 86:04dd9b1680ae 276 #define DMA_IT_HT ((uint32_t)DMA_CCR_HTIE)
bogdanm 86:04dd9b1680ae 277 #define DMA_IT_TE ((uint32_t)DMA_CCR_TEIE)
bogdanm 86:04dd9b1680ae 278
bogdanm 86:04dd9b1680ae 279 /**
bogdanm 86:04dd9b1680ae 280 * @}
bogdanm 86:04dd9b1680ae 281 */
bogdanm 86:04dd9b1680ae 282
bogdanm 86:04dd9b1680ae 283 /** @defgroup DMA_flag_definitions
bogdanm 86:04dd9b1680ae 284 * @{
bogdanm 86:04dd9b1680ae 285 */
bogdanm 86:04dd9b1680ae 286
bogdanm 86:04dd9b1680ae 287 #define DMA_FLAG_GL1 ((uint32_t)0x00000001)
bogdanm 86:04dd9b1680ae 288 #define DMA_FLAG_TC1 ((uint32_t)0x00000002)
bogdanm 86:04dd9b1680ae 289 #define DMA_FLAG_HT1 ((uint32_t)0x00000004)
bogdanm 86:04dd9b1680ae 290 #define DMA_FLAG_TE1 ((uint32_t)0x00000008)
bogdanm 86:04dd9b1680ae 291 #define DMA_FLAG_GL2 ((uint32_t)0x00000010)
bogdanm 86:04dd9b1680ae 292 #define DMA_FLAG_TC2 ((uint32_t)0x00000020)
bogdanm 86:04dd9b1680ae 293 #define DMA_FLAG_HT2 ((uint32_t)0x00000040)
bogdanm 86:04dd9b1680ae 294 #define DMA_FLAG_TE2 ((uint32_t)0x00000080)
bogdanm 86:04dd9b1680ae 295 #define DMA_FLAG_GL3 ((uint32_t)0x00000100)
bogdanm 86:04dd9b1680ae 296 #define DMA_FLAG_TC3 ((uint32_t)0x00000200)
bogdanm 86:04dd9b1680ae 297 #define DMA_FLAG_HT3 ((uint32_t)0x00000400)
bogdanm 86:04dd9b1680ae 298 #define DMA_FLAG_TE3 ((uint32_t)0x00000800)
bogdanm 86:04dd9b1680ae 299 #define DMA_FLAG_GL4 ((uint32_t)0x00001000)
bogdanm 86:04dd9b1680ae 300 #define DMA_FLAG_TC4 ((uint32_t)0x00002000)
bogdanm 86:04dd9b1680ae 301 #define DMA_FLAG_HT4 ((uint32_t)0x00004000)
bogdanm 86:04dd9b1680ae 302 #define DMA_FLAG_TE4 ((uint32_t)0x00008000)
bogdanm 86:04dd9b1680ae 303 #define DMA_FLAG_GL5 ((uint32_t)0x00010000)
bogdanm 86:04dd9b1680ae 304 #define DMA_FLAG_TC5 ((uint32_t)0x00020000)
bogdanm 86:04dd9b1680ae 305 #define DMA_FLAG_HT5 ((uint32_t)0x00040000)
bogdanm 86:04dd9b1680ae 306 #define DMA_FLAG_TE5 ((uint32_t)0x00080000)
bogdanm 86:04dd9b1680ae 307 #define DMA_FLAG_GL6 ((uint32_t)0x00100000)
bogdanm 86:04dd9b1680ae 308 #define DMA_FLAG_TC6 ((uint32_t)0x00200000)
bogdanm 86:04dd9b1680ae 309 #define DMA_FLAG_HT6 ((uint32_t)0x00400000)
bogdanm 86:04dd9b1680ae 310 #define DMA_FLAG_TE6 ((uint32_t)0x00800000)
bogdanm 86:04dd9b1680ae 311 #define DMA_FLAG_GL7 ((uint32_t)0x01000000)
bogdanm 86:04dd9b1680ae 312 #define DMA_FLAG_TC7 ((uint32_t)0x02000000)
bogdanm 86:04dd9b1680ae 313 #define DMA_FLAG_HT7 ((uint32_t)0x04000000)
bogdanm 86:04dd9b1680ae 314 #define DMA_FLAG_TE7 ((uint32_t)0x08000000)
bogdanm 86:04dd9b1680ae 315
bogdanm 86:04dd9b1680ae 316
bogdanm 86:04dd9b1680ae 317 /**
bogdanm 86:04dd9b1680ae 318 * @}
bogdanm 86:04dd9b1680ae 319 */
bogdanm 86:04dd9b1680ae 320
bogdanm 86:04dd9b1680ae 321 /**
bogdanm 86:04dd9b1680ae 322 * @}
bogdanm 86:04dd9b1680ae 323 */
bogdanm 86:04dd9b1680ae 324
bogdanm 86:04dd9b1680ae 325 /* Exported macros -----------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 326
bogdanm 86:04dd9b1680ae 327 /** @brief Reset DMA handle state
bogdanm 86:04dd9b1680ae 328 * @param __HANDLE__: DMA handle.
bogdanm 86:04dd9b1680ae 329 * @retval None
bogdanm 86:04dd9b1680ae 330 */
bogdanm 86:04dd9b1680ae 331 #define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
bogdanm 86:04dd9b1680ae 332
bogdanm 86:04dd9b1680ae 333 /**
bogdanm 86:04dd9b1680ae 334 * @brief Enable the specified DMA Channel.
bogdanm 86:04dd9b1680ae 335 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 336 * @retval None.
bogdanm 86:04dd9b1680ae 337 */
bogdanm 86:04dd9b1680ae 338 #define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR |= DMA_CCR_EN)
bogdanm 86:04dd9b1680ae 339
bogdanm 86:04dd9b1680ae 340 /**
bogdanm 86:04dd9b1680ae 341 * @brief Disable the specified DMA Channel.
bogdanm 86:04dd9b1680ae 342 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 343 * @retval None.
bogdanm 86:04dd9b1680ae 344 */
bogdanm 86:04dd9b1680ae 345 #define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CCR &= ~DMA_CCR_EN)
bogdanm 86:04dd9b1680ae 346
bogdanm 86:04dd9b1680ae 347
bogdanm 86:04dd9b1680ae 348 /* Interrupt & Flag management */
bogdanm 86:04dd9b1680ae 349
bogdanm 86:04dd9b1680ae 350 /**
bogdanm 86:04dd9b1680ae 351 * @brief Enables the specified DMA Channel interrupts.
bogdanm 86:04dd9b1680ae 352 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 353 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 86:04dd9b1680ae 354 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 355 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 356 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 357 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 358 * @retval None
bogdanm 86:04dd9b1680ae 359 */
bogdanm 86:04dd9b1680ae 360 #define __HAL_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR |= (__INTERRUPT__))
bogdanm 86:04dd9b1680ae 361
bogdanm 86:04dd9b1680ae 362 /**
bogdanm 86:04dd9b1680ae 363 * @brief Disables the specified DMA Channel interrupts.
bogdanm 86:04dd9b1680ae 364 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 365 * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
bogdanm 86:04dd9b1680ae 366 * This parameter can be any combination of the following values:
bogdanm 86:04dd9b1680ae 367 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 368 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 369 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 370 * @retval None
bogdanm 86:04dd9b1680ae 371 */
bogdanm 86:04dd9b1680ae 372 #define __HAL_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CCR &= ~(__INTERRUPT__))
bogdanm 86:04dd9b1680ae 373
bogdanm 86:04dd9b1680ae 374 /**
bogdanm 86:04dd9b1680ae 375 * @brief Checks whether the specified DMA Channel interrupt has occurred or not.
bogdanm 86:04dd9b1680ae 376 * @param __HANDLE__: DMA handle
bogdanm 86:04dd9b1680ae 377 * @param __INTERRUPT__: specifies the DMA interrupt source to check.
bogdanm 86:04dd9b1680ae 378 * This parameter can be one of the following values:
bogdanm 86:04dd9b1680ae 379 * @arg DMA_IT_TC: Transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 380 * @arg DMA_IT_HT: Half transfer complete interrupt mask
bogdanm 86:04dd9b1680ae 381 * @arg DMA_IT_TE: Transfer error interrupt mask
bogdanm 86:04dd9b1680ae 382 * @retval The state of DMA_IT (SET or RESET).
bogdanm 86:04dd9b1680ae 383 */
bogdanm 86:04dd9b1680ae 384 #define __HAL_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CCR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
bogdanm 86:04dd9b1680ae 385
bogdanm 86:04dd9b1680ae 386 /* Include DMA HAL Extension module */
bogdanm 86:04dd9b1680ae 387 #include "stm32f3xx_hal_dma_ex.h"
bogdanm 86:04dd9b1680ae 388
bogdanm 86:04dd9b1680ae 389 /* Exported functions --------------------------------------------------------*/
bogdanm 86:04dd9b1680ae 390
bogdanm 86:04dd9b1680ae 391 /* Initialization and de-initialization functions *****************************/
bogdanm 86:04dd9b1680ae 392 HAL_StatusTypeDef HAL_DMA_Init(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 393 HAL_StatusTypeDef HAL_DMA_DeInit (DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 394
bogdanm 86:04dd9b1680ae 395 /* IO operation functions *****************************************************/
bogdanm 86:04dd9b1680ae 396 HAL_StatusTypeDef HAL_DMA_Start (DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 86:04dd9b1680ae 397 HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength);
bogdanm 86:04dd9b1680ae 398 HAL_StatusTypeDef HAL_DMA_Abort(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 399 HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, uint32_t CompleteLevel, uint32_t Timeout);
bogdanm 86:04dd9b1680ae 400 void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 401
bogdanm 86:04dd9b1680ae 402 /* Peripheral State and Error functions ***************************************/
bogdanm 86:04dd9b1680ae 403 HAL_DMA_StateTypeDef HAL_DMA_GetState(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 404 uint32_t HAL_DMA_GetError(DMA_HandleTypeDef *hdma);
bogdanm 86:04dd9b1680ae 405
bogdanm 86:04dd9b1680ae 406 /**
bogdanm 86:04dd9b1680ae 407 * @}
bogdanm 86:04dd9b1680ae 408 */
bogdanm 86:04dd9b1680ae 409
bogdanm 86:04dd9b1680ae 410 /**
bogdanm 86:04dd9b1680ae 411 * @}
bogdanm 86:04dd9b1680ae 412 */
bogdanm 86:04dd9b1680ae 413
bogdanm 86:04dd9b1680ae 414 #ifdef __cplusplus
bogdanm 86:04dd9b1680ae 415 }
bogdanm 86:04dd9b1680ae 416 #endif
bogdanm 86:04dd9b1680ae 417
bogdanm 86:04dd9b1680ae 418 #endif /* __STM32F3xx_HAL_DMA_H */
bogdanm 86:04dd9b1680ae 419
bogdanm 86:04dd9b1680ae 420 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/