Filippo Casamassima
my fork
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mbed official
TARGET_NUCLEO_F072RB/stm32f0xx_hal.h@85:024bf7f99721, 2014-06-11 (annotated)
- Committer:
- bogdanm
- Date:
- Wed Jun 11 15:14:05 2014 +0100
- Revision:
- 85:024bf7f99721
- Child:
- 92:4fc01daae5a5
Release 85 of the mbed library
Main changes:
- K64F Ethernet fixes
- Updated tests
- Fixes for various mbed targets
- Code cleanup: fixed warnings, more consistent code style
- GCC support for K64F
There is a known issue with the I2C interface on some ST targets. If you
find the I2C interface problematic on your ST board, please log a bug
against this on mbed.org.
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 85:024bf7f99721 | 1 | /** |
| bogdanm | 85:024bf7f99721 | 2 | ****************************************************************************** |
| bogdanm | 85:024bf7f99721 | 3 | * @file stm32f0xx_hal.h |
| bogdanm | 85:024bf7f99721 | 4 | * @author MCD Application Team |
| bogdanm | 85:024bf7f99721 | 5 | * @version V1.0.0 |
| bogdanm | 85:024bf7f99721 | 6 | * @date 28-May-2014 |
| bogdanm | 85:024bf7f99721 | 7 | * @brief This file contains all the functions prototypes for the HAL |
| bogdanm | 85:024bf7f99721 | 8 | * module driver. |
| bogdanm | 85:024bf7f99721 | 9 | ****************************************************************************** |
| bogdanm | 85:024bf7f99721 | 10 | * @attention |
| bogdanm | 85:024bf7f99721 | 11 | * |
| bogdanm | 85:024bf7f99721 | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| bogdanm | 85:024bf7f99721 | 13 | * |
| bogdanm | 85:024bf7f99721 | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| bogdanm | 85:024bf7f99721 | 15 | * are permitted provided that the following conditions are met: |
| bogdanm | 85:024bf7f99721 | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| bogdanm | 85:024bf7f99721 | 17 | * this list of conditions and the following disclaimer. |
| bogdanm | 85:024bf7f99721 | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| bogdanm | 85:024bf7f99721 | 19 | * this list of conditions and the following disclaimer in the documentation |
| bogdanm | 85:024bf7f99721 | 20 | * and/or other materials provided with the distribution. |
| bogdanm | 85:024bf7f99721 | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| bogdanm | 85:024bf7f99721 | 22 | * may be used to endorse or promote products derived from this software |
| bogdanm | 85:024bf7f99721 | 23 | * without specific prior written permission. |
| bogdanm | 85:024bf7f99721 | 24 | * |
| bogdanm | 85:024bf7f99721 | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| bogdanm | 85:024bf7f99721 | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| bogdanm | 85:024bf7f99721 | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| bogdanm | 85:024bf7f99721 | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| bogdanm | 85:024bf7f99721 | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| bogdanm | 85:024bf7f99721 | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| bogdanm | 85:024bf7f99721 | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| bogdanm | 85:024bf7f99721 | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| bogdanm | 85:024bf7f99721 | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| bogdanm | 85:024bf7f99721 | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| bogdanm | 85:024bf7f99721 | 35 | * |
| bogdanm | 85:024bf7f99721 | 36 | ****************************************************************************** |
| bogdanm | 85:024bf7f99721 | 37 | */ |
| bogdanm | 85:024bf7f99721 | 38 | |
| bogdanm | 85:024bf7f99721 | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 40 | #ifndef __STM32F0xx_HAL_H |
| bogdanm | 85:024bf7f99721 | 41 | #define __STM32F0xx_HAL_H |
| bogdanm | 85:024bf7f99721 | 42 | |
| bogdanm | 85:024bf7f99721 | 43 | #ifdef __cplusplus |
| bogdanm | 85:024bf7f99721 | 44 | extern "C" { |
| bogdanm | 85:024bf7f99721 | 45 | #endif |
| bogdanm | 85:024bf7f99721 | 46 | |
| bogdanm | 85:024bf7f99721 | 47 | /* Includes ------------------------------------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 48 | #include "stm32f0xx_hal_conf.h" |
| bogdanm | 85:024bf7f99721 | 49 | |
| bogdanm | 85:024bf7f99721 | 50 | /** @addtogroup STM32F0xx_HAL_Driver |
| bogdanm | 85:024bf7f99721 | 51 | * @{ |
| bogdanm | 85:024bf7f99721 | 52 | */ |
| bogdanm | 85:024bf7f99721 | 53 | |
| bogdanm | 85:024bf7f99721 | 54 | /** @addtogroup HAL |
| bogdanm | 85:024bf7f99721 | 55 | * @{ |
| bogdanm | 85:024bf7f99721 | 56 | */ |
| bogdanm | 85:024bf7f99721 | 57 | |
| bogdanm | 85:024bf7f99721 | 58 | /* Exported types ------------------------------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 59 | /* Exported constants --------------------------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 60 | |
| bogdanm | 85:024bf7f99721 | 61 | /** @defgroup HAL_DMA_Remapping |
| bogdanm | 85:024bf7f99721 | 62 | * Elements values convention: 0xYYYYYYYY |
| bogdanm | 85:024bf7f99721 | 63 | * - YYYYYYYY : Position in the SYSCFG register CFGR1 |
| bogdanm | 85:024bf7f99721 | 64 | * @{ |
| bogdanm | 85:024bf7f99721 | 65 | */ |
| bogdanm | 85:024bf7f99721 | 66 | #define HAL_REMAPDMA_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap |
| bogdanm | 85:024bf7f99721 | 67 | 0: No remap (ADC DMA requests mapped on DMA channel 1 |
| bogdanm | 85:024bf7f99721 | 68 | 1: Remap (ADC DMA requests mapped on DMA channel 2 */ |
| bogdanm | 85:024bf7f99721 | 69 | #define HAL_REMAPDMA_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap |
| bogdanm | 85:024bf7f99721 | 70 | 0: No remap (USART1_TX DMA request mapped on DMA channel 2 |
| bogdanm | 85:024bf7f99721 | 71 | 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ |
| bogdanm | 85:024bf7f99721 | 72 | #define HAL_REMAPDMA_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap |
| bogdanm | 85:024bf7f99721 | 73 | 0: No remap (USART1_RX DMA request mapped on DMA channel 3 |
| bogdanm | 85:024bf7f99721 | 74 | 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ |
| bogdanm | 85:024bf7f99721 | 75 | #define HAL_REMAPDMA_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap |
| bogdanm | 85:024bf7f99721 | 76 | 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) |
| bogdanm | 85:024bf7f99721 | 77 | 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ |
| bogdanm | 85:024bf7f99721 | 78 | #define HAL_REMAPDMA_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap |
| bogdanm | 85:024bf7f99721 | 79 | 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 |
| bogdanm | 85:024bf7f99721 | 80 | 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ |
| bogdanm | 85:024bf7f99721 | 81 | |
| bogdanm | 85:024bf7f99721 | 82 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 83 | #define HAL_REMAPDMA_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only |
| bogdanm | 85:024bf7f99721 | 84 | 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) |
| bogdanm | 85:024bf7f99721 | 85 | 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ |
| bogdanm | 85:024bf7f99721 | 86 | #define HAL_REMAPDMA_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only |
| bogdanm | 85:024bf7f99721 | 87 | 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) |
| bogdanm | 85:024bf7f99721 | 88 | 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ |
| bogdanm | 85:024bf7f99721 | 89 | #define HAL_REMAPDMA_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. |
| bogdanm | 85:024bf7f99721 | 90 | 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) |
| bogdanm | 85:024bf7f99721 | 91 | 1: 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ |
| bogdanm | 85:024bf7f99721 | 92 | #define HAL_REMAPDMA_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. |
| bogdanm | 85:024bf7f99721 | 93 | 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) |
| bogdanm | 85:024bf7f99721 | 94 | 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ |
| bogdanm | 85:024bf7f99721 | 95 | #define HAL_REMAPDMA_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. |
| bogdanm | 85:024bf7f99721 | 96 | 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) |
| bogdanm | 85:024bf7f99721 | 97 | 1: 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ |
| bogdanm | 85:024bf7f99721 | 98 | #define HAL_REMAPDMA_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. |
| bogdanm | 85:024bf7f99721 | 99 | 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) |
| bogdanm | 85:024bf7f99721 | 100 | 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ |
| bogdanm | 85:024bf7f99721 | 101 | #define HAL_REMAPDMA_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. |
| bogdanm | 85:024bf7f99721 | 102 | 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) |
| bogdanm | 85:024bf7f99721 | 103 | 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ |
| bogdanm | 85:024bf7f99721 | 104 | #define HAL_REMAPDMA_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. |
| bogdanm | 85:024bf7f99721 | 105 | 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) |
| bogdanm | 85:024bf7f99721 | 106 | 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ |
| bogdanm | 85:024bf7f99721 | 107 | #define HAL_REMAPDMA_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. |
| bogdanm | 85:024bf7f99721 | 108 | 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) |
| bogdanm | 85:024bf7f99721 | 109 | 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ |
| bogdanm | 85:024bf7f99721 | 110 | #endif |
| bogdanm | 85:024bf7f99721 | 111 | |
| bogdanm | 85:024bf7f99721 | 112 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 113 | #define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \ |
| bogdanm | 85:024bf7f99721 | 114 | ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \ |
| bogdanm | 85:024bf7f99721 | 115 | ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \ |
| bogdanm | 85:024bf7f99721 | 116 | ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \ |
| bogdanm | 85:024bf7f99721 | 117 | ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2) || \ |
| bogdanm | 85:024bf7f99721 | 118 | ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH6) || \ |
| bogdanm | 85:024bf7f99721 | 119 | ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH7) || \ |
| bogdanm | 85:024bf7f99721 | 120 | ((RMP) == HAL_REMAPDMA_SPI2_DMA_CH67) || \ |
| bogdanm | 85:024bf7f99721 | 121 | ((RMP) == HAL_REMAPDMA_USART2_DMA_CH67) || \ |
| bogdanm | 85:024bf7f99721 | 122 | ((RMP) == HAL_REMAPDMA_USART3_DMA_CH32) || \ |
| bogdanm | 85:024bf7f99721 | 123 | ((RMP) == HAL_REMAPDMA_I2C1_DMA_CH76) || \ |
| bogdanm | 85:024bf7f99721 | 124 | ((RMP) == HAL_REMAPDMA_TIM1_DMA_CH6) || \ |
| bogdanm | 85:024bf7f99721 | 125 | ((RMP) == HAL_REMAPDMA_TIM2_DMA_CH7) || \ |
| bogdanm | 85:024bf7f99721 | 126 | ((RMP) == HAL_REMAPDMA_TIM3_DMA_CH6)) |
| bogdanm | 85:024bf7f99721 | 127 | #else |
| bogdanm | 85:024bf7f99721 | 128 | #define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \ |
| bogdanm | 85:024bf7f99721 | 129 | ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \ |
| bogdanm | 85:024bf7f99721 | 130 | ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \ |
| bogdanm | 85:024bf7f99721 | 131 | ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \ |
| bogdanm | 85:024bf7f99721 | 132 | ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2)) |
| bogdanm | 85:024bf7f99721 | 133 | #endif |
| bogdanm | 85:024bf7f99721 | 134 | /** |
| bogdanm | 85:024bf7f99721 | 135 | * @} |
| bogdanm | 85:024bf7f99721 | 136 | */ |
| bogdanm | 85:024bf7f99721 | 137 | |
| bogdanm | 85:024bf7f99721 | 138 | #if defined(STM32F042x6) || defined(STM32F048xx) |
| bogdanm | 85:024bf7f99721 | 139 | /** @defgroup HAL_Pin_Remapping |
| bogdanm | 85:024bf7f99721 | 140 | * @{ |
| bogdanm | 85:024bf7f99721 | 141 | */ |
| bogdanm | 85:024bf7f99721 | 142 | #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). |
| bogdanm | 85:024bf7f99721 | 143 | 0: No remap (pin pair PA9/10 mapped on the pins) |
| bogdanm | 85:024bf7f99721 | 144 | 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ |
| bogdanm | 85:024bf7f99721 | 145 | |
| bogdanm | 85:024bf7f99721 | 146 | #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) |
| bogdanm | 85:024bf7f99721 | 147 | /** |
| bogdanm | 85:024bf7f99721 | 148 | * @} |
| bogdanm | 85:024bf7f99721 | 149 | */ |
| bogdanm | 85:024bf7f99721 | 150 | #endif /* STM32F042x6 || STM32F048xx */ |
| bogdanm | 85:024bf7f99721 | 151 | |
| bogdanm | 85:024bf7f99721 | 152 | /** @defgroup HAL_FastModePlus_I2C |
| bogdanm | 85:024bf7f99721 | 153 | * @{ |
| bogdanm | 85:024bf7f99721 | 154 | */ |
| bogdanm | 85:024bf7f99721 | 155 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 (SYSCFG_CFGR1_I2C_FMP_PB6) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 85:024bf7f99721 | 156 | 0: PB6 pin operates in standard mode |
| bogdanm | 85:024bf7f99721 | 157 | 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */ |
| bogdanm | 85:024bf7f99721 | 158 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 (SYSCFG_CFGR1_I2C_FMP_PB7) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 85:024bf7f99721 | 159 | 0: PB7 pin operates in standard mode |
| bogdanm | 85:024bf7f99721 | 160 | 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */ |
| bogdanm | 85:024bf7f99721 | 161 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 (SYSCFG_CFGR1_I2C_FMP_PB8) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 85:024bf7f99721 | 162 | 0: PB8 pin operates in standard mode |
| bogdanm | 85:024bf7f99721 | 163 | 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */ |
| bogdanm | 85:024bf7f99721 | 164 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 (SYSCFG_CFGR1_I2C_FMP_PB9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 85:024bf7f99721 | 165 | 0: PB9 pin operates in standard mode |
| bogdanm | 85:024bf7f99721 | 166 | 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */ |
| bogdanm | 85:024bf7f99721 | 167 | |
| bogdanm | 85:024bf7f99721 | 168 | #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || \ |
| bogdanm | 85:024bf7f99721 | 169 | defined(STM32F042x6) || defined(STM32F048xx) || \ |
| bogdanm | 85:024bf7f99721 | 170 | defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 171 | #define HAL_SYSCFG_FASTMODEPLUS_I2C1 (SYSCFG_CFGR1_I2C_FMP_I2C1) /*!< I2C1 fast mode Plus driving capability activation |
| bogdanm | 85:024bf7f99721 | 172 | 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits |
| bogdanm | 85:024bf7f99721 | 173 | 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */ |
| bogdanm | 85:024bf7f99721 | 174 | #endif |
| bogdanm | 85:024bf7f99721 | 175 | |
| bogdanm | 85:024bf7f99721 | 176 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 177 | #define HAL_SYSCFG_FASTMODEPLUS_I2C2 (SYSCFG_CFGR1_I2C_FMP_I2C2) /*!< I2C2 fast mode Plus driving capability activation |
| bogdanm | 85:024bf7f99721 | 178 | 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits |
| bogdanm | 85:024bf7f99721 | 179 | 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */ |
| bogdanm | 85:024bf7f99721 | 180 | #endif |
| bogdanm | 85:024bf7f99721 | 181 | |
| bogdanm | 85:024bf7f99721 | 182 | #if defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) |
| bogdanm | 85:024bf7f99721 | 183 | #define HAL_SYSCFG_FASTMODEPLUS_I2C2_PA9 (SYSCFG_CFGR1_I2C_FMP_PA9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 85:024bf7f99721 | 184 | 0: PA9 pin operates in standard mode |
| bogdanm | 85:024bf7f99721 | 185 | 1: FM+ mode is enabled on PA9 pin, and the Speed control is bypassed */ |
| bogdanm | 85:024bf7f99721 | 186 | #define HAL_SYSCFG_FASTMODEPLUS_I2C2_PA10 (SYSCFG_CFGR1_I2C_FMP_PA10) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| bogdanm | 85:024bf7f99721 | 187 | 0: PA10 pin operates in standard mode |
| bogdanm | 85:024bf7f99721 | 188 | 1: FM+ mode is enabled on PA10 pin, and the Speed control is bypassed */ |
| bogdanm | 85:024bf7f99721 | 189 | #endif |
| bogdanm | 85:024bf7f99721 | 190 | |
| bogdanm | 85:024bf7f99721 | 191 | /** |
| bogdanm | 85:024bf7f99721 | 192 | * @} |
| bogdanm | 85:024bf7f99721 | 193 | */ |
| bogdanm | 85:024bf7f99721 | 194 | |
| bogdanm | 85:024bf7f99721 | 195 | |
| bogdanm | 85:024bf7f99721 | 196 | /* Exported macros -----------------------------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 197 | |
| bogdanm | 85:024bf7f99721 | 198 | /** @brief Freeze/Unfreeze Peripherals in Debug mode |
| bogdanm | 85:024bf7f99721 | 199 | */ |
| bogdanm | 85:024bf7f99721 | 200 | #define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| bogdanm | 85:024bf7f99721 | 201 | #define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| bogdanm | 85:024bf7f99721 | 202 | |
| bogdanm | 85:024bf7f99721 | 203 | #define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| bogdanm | 85:024bf7f99721 | 204 | #define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| bogdanm | 85:024bf7f99721 | 205 | |
| bogdanm | 85:024bf7f99721 | 206 | #define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| bogdanm | 85:024bf7f99721 | 207 | #define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| bogdanm | 85:024bf7f99721 | 208 | |
| bogdanm | 85:024bf7f99721 | 209 | #define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| bogdanm | 85:024bf7f99721 | 210 | #define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| bogdanm | 85:024bf7f99721 | 211 | |
| bogdanm | 85:024bf7f99721 | 212 | #define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| bogdanm | 85:024bf7f99721 | 213 | #define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| bogdanm | 85:024bf7f99721 | 214 | |
| bogdanm | 85:024bf7f99721 | 215 | #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| bogdanm | 85:024bf7f99721 | 216 | #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| bogdanm | 85:024bf7f99721 | 217 | |
| bogdanm | 85:024bf7f99721 | 218 | #if defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || \ |
| bogdanm | 85:024bf7f99721 | 219 | defined(STM32F071xB) || defined(STM32F072xB) || \ |
| bogdanm | 85:024bf7f99721 | 220 | defined(STM32F038xx) || defined(STM32F058xx) || defined(STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 221 | #define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| bogdanm | 85:024bf7f99721 | 222 | #define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| bogdanm | 85:024bf7f99721 | 223 | #endif /* STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F051x8 || */ |
| bogdanm | 85:024bf7f99721 | 224 | /* STM32F071xB || STM32F072xB || */ |
| bogdanm | 85:024bf7f99721 | 225 | /* STM32F038xx || STM32F058xx || STM32F078xx */ |
| bogdanm | 85:024bf7f99721 | 226 | |
| bogdanm | 85:024bf7f99721 | 227 | #if defined(STM32F030x8) || defined(STM32F051x8) || \ |
| bogdanm | 85:024bf7f99721 | 228 | defined(STM32F071xB) || defined(STM32F072xB) || \ |
| bogdanm | 85:024bf7f99721 | 229 | defined(STM32F058xx) || defined(STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 230 | #define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| bogdanm | 85:024bf7f99721 | 231 | #define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| bogdanm | 85:024bf7f99721 | 232 | #endif /* STM32F030x8 || STM32F051x8 || */ |
| bogdanm | 85:024bf7f99721 | 233 | /* STM32F071xB || STM32F072xB || */ |
| bogdanm | 85:024bf7f99721 | 234 | /* STM32F058xx || STM32F078xx */ |
| bogdanm | 85:024bf7f99721 | 235 | |
| bogdanm | 85:024bf7f99721 | 236 | #if defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 237 | #define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| bogdanm | 85:024bf7f99721 | 238 | #define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| bogdanm | 85:024bf7f99721 | 239 | #endif /* STM32F071xB || STM32F072xB || STM32F078xx */ |
| bogdanm | 85:024bf7f99721 | 240 | |
| bogdanm | 85:024bf7f99721 | 241 | #if defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F072xB) |
| bogdanm | 85:024bf7f99721 | 242 | #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN1_STOP)) |
| bogdanm | 85:024bf7f99721 | 243 | #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN1_STOP)) |
| bogdanm | 85:024bf7f99721 | 244 | #endif /* STM32F042x6 || STM32F072xB */ |
| bogdanm | 85:024bf7f99721 | 245 | |
| bogdanm | 85:024bf7f99721 | 246 | |
| bogdanm | 85:024bf7f99721 | 247 | #define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| bogdanm | 85:024bf7f99721 | 248 | #define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| bogdanm | 85:024bf7f99721 | 249 | |
| bogdanm | 85:024bf7f99721 | 250 | #if defined(STM32F030x8) || defined(STM32F051x8) || \ |
| bogdanm | 85:024bf7f99721 | 251 | defined(STM32F071xB) || defined(STM32F072xB) || \ |
| bogdanm | 85:024bf7f99721 | 252 | defined(STM32F058xx) || defined(STM32F078xx) |
| bogdanm | 85:024bf7f99721 | 253 | #define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| bogdanm | 85:024bf7f99721 | 254 | #define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| bogdanm | 85:024bf7f99721 | 255 | #endif /* STM32F030x8 || STM32F051x8 || */ |
| bogdanm | 85:024bf7f99721 | 256 | /* STM32F071xB || STM32F072xB || */ |
| bogdanm | 85:024bf7f99721 | 257 | /* STM32F058xx || STM32F078xx */ |
| bogdanm | 85:024bf7f99721 | 258 | |
| bogdanm | 85:024bf7f99721 | 259 | #define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| bogdanm | 85:024bf7f99721 | 260 | #define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| bogdanm | 85:024bf7f99721 | 261 | |
| bogdanm | 85:024bf7f99721 | 262 | #define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| bogdanm | 85:024bf7f99721 | 263 | #define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| bogdanm | 85:024bf7f99721 | 264 | |
| bogdanm | 85:024bf7f99721 | 265 | /** @brief Main Flash memory mapped at 0x00000000 |
| bogdanm | 85:024bf7f99721 | 266 | */ |
| bogdanm | 85:024bf7f99721 | 267 | #define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) |
| bogdanm | 85:024bf7f99721 | 268 | |
| bogdanm | 85:024bf7f99721 | 269 | /** @brief System Flash memory mapped at 0x00000000 |
| bogdanm | 85:024bf7f99721 | 270 | */ |
| bogdanm | 85:024bf7f99721 | 271 | #define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| bogdanm | 85:024bf7f99721 | 272 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ |
| bogdanm | 85:024bf7f99721 | 273 | }while(0) |
| bogdanm | 85:024bf7f99721 | 274 | |
| bogdanm | 85:024bf7f99721 | 275 | /** @brief Embedded SRAM mapped at 0x00000000 |
| bogdanm | 85:024bf7f99721 | 276 | */ |
| bogdanm | 85:024bf7f99721 | 277 | #define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| bogdanm | 85:024bf7f99721 | 278 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ |
| bogdanm | 85:024bf7f99721 | 279 | }while(0) |
| bogdanm | 85:024bf7f99721 | 280 | |
| bogdanm | 85:024bf7f99721 | 281 | /** @brief DMA remapping enable/disable macros |
| bogdanm | 85:024bf7f99721 | 282 | * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_Remapping |
| bogdanm | 85:024bf7f99721 | 283 | */ |
| bogdanm | 85:024bf7f99721 | 284 | #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ |
| bogdanm | 85:024bf7f99721 | 285 | SYSCFG->CFGR1 |= (__DMA_REMAP__); \ |
| bogdanm | 85:024bf7f99721 | 286 | }while(0) |
| bogdanm | 85:024bf7f99721 | 287 | #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ |
| bogdanm | 85:024bf7f99721 | 288 | SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ |
| bogdanm | 85:024bf7f99721 | 289 | }while(0) |
| bogdanm | 85:024bf7f99721 | 290 | |
| bogdanm | 85:024bf7f99721 | 291 | #if defined(STM32F042x6) || defined(STM32F048xx) |
| bogdanm | 85:024bf7f99721 | 292 | /** @brief Pin remapping enable/disable macros |
| bogdanm | 85:024bf7f99721 | 293 | * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_Remapping |
| bogdanm | 85:024bf7f99721 | 294 | */ |
| bogdanm | 85:024bf7f99721 | 295 | #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ |
| bogdanm | 85:024bf7f99721 | 296 | SYSCFG->CFGR1 |= (__PIN_REMAP__); \ |
| bogdanm | 85:024bf7f99721 | 297 | }while(0) |
| bogdanm | 85:024bf7f99721 | 298 | #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__DMA_REMAP__))); \ |
| bogdanm | 85:024bf7f99721 | 299 | SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ |
| bogdanm | 85:024bf7f99721 | 300 | }while(0) |
| bogdanm | 85:024bf7f99721 | 301 | #endif /* STM32F042x6 || STM32F048xx */ |
| bogdanm | 85:024bf7f99721 | 302 | |
| bogdanm | 85:024bf7f99721 | 303 | /** @brief Fast mode Plus driving capability enable/disable macros |
| bogdanm | 85:024bf7f99721 | 304 | * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C |
| bogdanm | 85:024bf7f99721 | 305 | */ |
| bogdanm | 85:024bf7f99721 | 306 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ |
| bogdanm | 85:024bf7f99721 | 307 | SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \ |
| bogdanm | 85:024bf7f99721 | 308 | }while(0) |
| bogdanm | 85:024bf7f99721 | 309 | |
| bogdanm | 85:024bf7f99721 | 310 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ |
| bogdanm | 85:024bf7f99721 | 311 | SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \ |
| bogdanm | 85:024bf7f99721 | 312 | }while(0) |
| bogdanm | 85:024bf7f99721 | 313 | |
| bogdanm | 85:024bf7f99721 | 314 | /** @brief SYSCFG Break Lockup lock |
| bogdanm | 85:024bf7f99721 | 315 | * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input |
| bogdanm | 85:024bf7f99721 | 316 | * @note The selected configuration is locked and can be unlocked by system reset |
| bogdanm | 85:024bf7f99721 | 317 | */ |
| bogdanm | 85:024bf7f99721 | 318 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ |
| bogdanm | 85:024bf7f99721 | 319 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ |
| bogdanm | 85:024bf7f99721 | 320 | }while(0) |
| bogdanm | 85:024bf7f99721 | 321 | |
| bogdanm | 85:024bf7f99721 | 322 | #if defined(STM32F031x6) || defined(STM32F042x6) || defined(STM32F048xx) || defined(STM32F051x8) || \ |
| bogdanm | 85:024bf7f99721 | 323 | defined(STM32F071xB) || defined(STM32F072xB) |
| bogdanm | 85:024bf7f99721 | 324 | /** @brief SYSCFG Break PVD lock |
| bogdanm | 85:024bf7f99721 | 325 | * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register |
| bogdanm | 85:024bf7f99721 | 326 | * @note The selected configuration is locked and can be unlocked by system reset |
| bogdanm | 85:024bf7f99721 | 327 | */ |
| bogdanm | 85:024bf7f99721 | 328 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ |
| bogdanm | 85:024bf7f99721 | 329 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ |
| bogdanm | 85:024bf7f99721 | 330 | }while(0) |
| bogdanm | 85:024bf7f99721 | 331 | #endif /* STM32F031x6 || STM32F042x6 || STM32F048xx || STM32F051x8) || */ |
| bogdanm | 85:024bf7f99721 | 332 | /* STM32F071xB || STM32F072xB */ |
| bogdanm | 85:024bf7f99721 | 333 | |
| bogdanm | 85:024bf7f99721 | 334 | /** @brief SYSCFG Break SRAM PARITY lock |
| bogdanm | 85:024bf7f99721 | 335 | * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 |
| bogdanm | 85:024bf7f99721 | 336 | * @note The selected configuration is locked and can be unlocked by system reset |
| bogdanm | 85:024bf7f99721 | 337 | */ |
| bogdanm | 85:024bf7f99721 | 338 | #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ |
| bogdanm | 85:024bf7f99721 | 339 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ |
| bogdanm | 85:024bf7f99721 | 340 | }while(0) |
| bogdanm | 85:024bf7f99721 | 341 | |
| bogdanm | 85:024bf7f99721 | 342 | /** |
| bogdanm | 85:024bf7f99721 | 343 | * @brief Parity check on RAM disable macro |
| bogdanm | 85:024bf7f99721 | 344 | * @note Disabling the parity check on RAM locks the configuration bit. |
| bogdanm | 85:024bf7f99721 | 345 | * To re-enable the parity check on RAM perform a system reset. |
| bogdanm | 85:024bf7f99721 | 346 | */ |
| bogdanm | 85:024bf7f99721 | 347 | #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) |
| bogdanm | 85:024bf7f99721 | 348 | |
| bogdanm | 85:024bf7f99721 | 349 | |
| bogdanm | 85:024bf7f99721 | 350 | /* Exported functions --------------------------------------------------------*/ |
| bogdanm | 85:024bf7f99721 | 351 | |
| bogdanm | 85:024bf7f99721 | 352 | /* Initialization and de-initialization functions ****************************/ |
| bogdanm | 85:024bf7f99721 | 353 | HAL_StatusTypeDef HAL_Init(void); |
| bogdanm | 85:024bf7f99721 | 354 | HAL_StatusTypeDef HAL_DeInit(void); |
| bogdanm | 85:024bf7f99721 | 355 | void HAL_MspInit(void); |
| bogdanm | 85:024bf7f99721 | 356 | void HAL_MspDeInit(void); |
| bogdanm | 85:024bf7f99721 | 357 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| bogdanm | 85:024bf7f99721 | 358 | |
| bogdanm | 85:024bf7f99721 | 359 | /* Peripheral Control functions **********************************************/ |
| bogdanm | 85:024bf7f99721 | 360 | void HAL_IncTick(void); |
| bogdanm | 85:024bf7f99721 | 361 | void HAL_Delay(__IO uint32_t Delay); |
| bogdanm | 85:024bf7f99721 | 362 | uint32_t HAL_GetTick(void); |
| bogdanm | 85:024bf7f99721 | 363 | void HAL_SuspendTick(void); |
| bogdanm | 85:024bf7f99721 | 364 | void HAL_ResumeTick(void); |
| bogdanm | 85:024bf7f99721 | 365 | uint32_t HAL_GetHalVersion(void); |
| bogdanm | 85:024bf7f99721 | 366 | uint32_t HAL_GetREVID(void); |
| bogdanm | 85:024bf7f99721 | 367 | uint32_t HAL_GetDEVID(void); |
| bogdanm | 85:024bf7f99721 | 368 | |
| bogdanm | 85:024bf7f99721 | 369 | void HAL_EnableDBGStopMode(void); |
| bogdanm | 85:024bf7f99721 | 370 | void HAL_DisableDBGStopMode(void); |
| bogdanm | 85:024bf7f99721 | 371 | void HAL_EnableDBGStandbyMode(void); |
| bogdanm | 85:024bf7f99721 | 372 | void HAL_DisableDBGStandbyMode(void); |
| bogdanm | 85:024bf7f99721 | 373 | |
| bogdanm | 85:024bf7f99721 | 374 | /** |
| bogdanm | 85:024bf7f99721 | 375 | * @} |
| bogdanm | 85:024bf7f99721 | 376 | */ |
| bogdanm | 85:024bf7f99721 | 377 | |
| bogdanm | 85:024bf7f99721 | 378 | /** |
| bogdanm | 85:024bf7f99721 | 379 | * @} |
| bogdanm | 85:024bf7f99721 | 380 | */ |
| bogdanm | 85:024bf7f99721 | 381 | |
| bogdanm | 85:024bf7f99721 | 382 | #ifdef __cplusplus |
| bogdanm | 85:024bf7f99721 | 383 | } |
| bogdanm | 85:024bf7f99721 | 384 | #endif |
| bogdanm | 85:024bf7f99721 | 385 | |
| bogdanm | 85:024bf7f99721 | 386 | #endif /* __STM32F0xx_HAL_H */ |
| bogdanm | 85:024bf7f99721 | 387 | |
| bogdanm | 85:024bf7f99721 | 388 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |