frederic blanc / Mbed 2 deprecated qei_hw_motor

Keil MBC1700 demoboard and L293, QEI ,TFT, MOTOR, UART

Dependencies:   mbed Motor

QEI_hw_m/qeihw.h@0:9555690e7705, 2012-03-02 (annotated)

Committer:
fblanc
Date:
Fri Mar 02 14:18:23 2012 +0000
Revision:
0:9555690e7705
v1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
fblanc 0:9555690e7705 1 /* mbed Library - QEIhw
fblanc 0:9555690e7705 2 * Copyright (c) 2010, hball
fblanc 0:9555690e7705 3 * released under MIT license http://mbed.org/licence/mit
fblanc 0:9555690e7705 4 */
fblanc 0:9555690e7705 5
fblanc 0:9555690e7705 6 /***********************************************************************//**
fblanc 0:9555690e7705 7 * @file qeihw.h
fblanc 0:9555690e7705 8 * @brief Header file for the qeihw driver. Adapted from the CMSIS
fblanc 0:9555690e7705 9 * header, lpc17xx_qei.h, v 2.0
fblanc 0:9555690e7705 10 * @version 0.0
fblanc 0:9555690e7705 11 * @date 10 Dec 2010
fblanc 0:9555690e7705 12 * @author hb
fblanc 0:9555690e7705 13 **************************************************************************/
fblanc 0:9555690e7705 14
fblanc 0:9555690e7705 15
fblanc 0:9555690e7705 16 #ifndef MBED_QEIHW_H
fblanc 0:9555690e7705 17 #define MBED_QEIHW_H
fblanc 0:9555690e7705 18
fblanc 0:9555690e7705 19 /* Includes ------------------------------------------------------------------- */
fblanc 0:9555690e7705 20 #include "mbed.h"
fblanc 0:9555690e7705 21
fblanc 0:9555690e7705 22
fblanc 0:9555690e7705 23 /* Public Types --------------------------------------------------------------- */
fblanc 0:9555690e7705 24
fblanc 0:9555690e7705 25 /* Flag Status type definition */
fblanc 0:9555690e7705 26 typedef enum {RESET = 0, SET = !RESET} FlagStatus, IntStatus, SetState;
fblanc 0:9555690e7705 27
fblanc 0:9555690e7705 28 /* Functional State Definition */
fblanc 0:9555690e7705 29 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
fblanc 0:9555690e7705 30
fblanc 0:9555690e7705 31
fblanc 0:9555690e7705 32 /* Other definitions */
fblanc 0:9555690e7705 33 #define XTAL_FREQ 12000000
fblanc 0:9555690e7705 34
fblanc 0:9555690e7705 35 /* Public Functions ----------------------------------------------------------- */
fblanc 0:9555690e7705 36 /** @defgroup QEI_Public_Functions QEI Public Functions
fblanc 0:9555690e7705 37 */
fblanc 0:9555690e7705 38
fblanc 0:9555690e7705 39 /** QEI hardware interface class
fblanc 0:9555690e7705 40 * Requires mbed hardware modification: connect
fblanc 0:9555690e7705 41 * encoder PhA to p1.20, and PhB to p1.23.
fblanc 0:9555690e7705 42 *
fblanc 0:9555690e7705 43 * Example:
fblanc 0:9555690e7705 44 * @code
fblanc 0:9555690e7705 45 * // Display changes in encoder position and direction
fblanc 0:9555690e7705 46 #include "mbed.h"
fblanc 0:9555690e7705 47 * #include "qeihw.h"
fblanc 0:9555690e7705 48 *
fblanc 0:9555690e7705 49 * DigitalOut led1(LED1);
fblanc 0:9555690e7705 50 * DigitalOut led3(LED3);
fblanc 0:9555690e7705 51 * QEIHW qei(QEI_DIRINV_NONE, QEI_SIGNALMODE_QUAD, QEI_CAPMODE_2X, QEI_INVINX_NONE );
fblanc 0:9555690e7705 52 *
fblanc 0:9555690e7705 53 * int main() {
fblanc 0:9555690e7705 54 * int32_t temp, position = 0;
fblanc 0:9555690e7705 55 * qei.SetDigiFilter(480UL);
fblanc 0:9555690e7705 56 * qei.SetMaxPosition(0xFFFFFFFF);
fblanc 0:9555690e7705 57 *
fblanc 0:9555690e7705 58 * while(1) {
fblanc 0:9555690e7705 59 * while(position == (temp = qei.GetPosition()) );
fblanc 0:9555690e7705 60 * position = temp;
fblanc 0:9555690e7705 61 * printf("New position = %d.\r\n", temp);
fblanc 0:9555690e7705 62 * led1 = qei.Direction() == SET ? 1 : 0;
fblanc 0:9555690e7705 63 * led3 = !led1;
fblanc 0:9555690e7705 64 * wait(0.1);
fblanc 0:9555690e7705 65 * }
fblanc 0:9555690e7705 66 * }
fblanc 0:9555690e7705 67 * @endcode
fblanc 0:9555690e7705 68 */
fblanc 0:9555690e7705 69
fblanc 0:9555690e7705 70 class QEIHW {
fblanc 0:9555690e7705 71 public:
fblanc 0:9555690e7705 72
fblanc 0:9555690e7705 73 /** Create a QEI object and configure it
fblanc 0:9555690e7705 74 *
fblanc 0:9555690e7705 75 * @param _dirinv Direction invert. When = 1, complements the QEICONF register DIR bit
fblanc 0:9555690e7705 76 * @param _sigmode Signal mode. When = 0, PhA and PhB are quadrature inputs. When = 1, PhA is direction and PhB is clock
fblanc 0:9555690e7705 77 * @param _capmode Capture mode. When = 0, count PhA edges only (2X mode). Whe = 1, count PhB edges also (4X mode).
fblanc 0:9555690e7705 78 * @param _invinx Invert index. When = 1, inverts the sense of the index signal
fblanc 0:9555690e7705 79 */
fblanc 0:9555690e7705 80 QEIHW( uint32_t _dirinv, uint32_t _sigmode, uint32_t _capmode, uint32_t _invinx);
fblanc 0:9555690e7705 81
fblanc 0:9555690e7705 82 /** Resets value for each type of QEI value, such as velocity, position, etc.
fblanc 0:9555690e7705 83 *
fblanc 0:9555690e7705 84 * @param[in] ulResetType QEI Reset Type, should be one of the following:
fblanc 0:9555690e7705 85 * - QEI_RESET_POS: Reset Position Counter
fblanc 0:9555690e7705 86 * - QEI_RESET_POSOnIDX: Reset Position Counter on Index signal
fblanc 0:9555690e7705 87 * - QEI_RESET_VEL: Reset Velocity
fblanc 0:9555690e7705 88 * - QEI_RESET_IDX: Reset Index Counter
fblanc 0:9555690e7705 89 */
fblanc 0:9555690e7705 90 void Reset(uint32_t ulResetType);
fblanc 0:9555690e7705 91
fblanc 0:9555690e7705 92 /** Powers down the QEI block, returns pins to GPIO mode
fblanc 0:9555690e7705 93 *
fblanc 0:9555690e7705 94 */
fblanc 0:9555690e7705 95 void DeInit();
fblanc 0:9555690e7705 96
fblanc 0:9555690e7705 97 /** Report direction (QEISTAT bit DIR)
fblanc 0:9555690e7705 98 *
fblanc 0:9555690e7705 99 * @return State of the DIR bit (SET or RESET)
fblanc 0:9555690e7705 100 */
fblanc 0:9555690e7705 101 FlagStatus Direction();
fblanc 0:9555690e7705 102
fblanc 0:9555690e7705 103 /**
fblanc 0:9555690e7705 104 * @brief Get current position value in QEI peripheral
fblanc 0:9555690e7705 105 *
fblanc 0:9555690e7705 106 * @return Current position value of QEI peripheral
fblanc 0:9555690e7705 107 */
fblanc 0:9555690e7705 108 uint32_t GetPosition();
fblanc 0:9555690e7705 109
fblanc 0:9555690e7705 110 /** Set max position value for QEI peripheral
fblanc 0:9555690e7705 111 *
fblanc 0:9555690e7705 112 * @param[in] ulMaxPos Max position value to set
fblanc 0:9555690e7705 113 * @return None
fblanc 0:9555690e7705 114 */
fblanc 0:9555690e7705 115 void SetMaxPosition(uint32_t ulMaxPos);
fblanc 0:9555690e7705 116
fblanc 0:9555690e7705 117 /** Set position compare value for QEI peripheral
fblanc 0:9555690e7705 118 * @param[in] bPosCompCh Compare Position channel, should be:
fblanc 0:9555690e7705 119 * - QEI_COMPPOS_CH_0: QEI compare position channel 0
fblanc 0:9555690e7705 120 * - QEI_COMPPOS_CH_1: QEI compare position channel 1
fblanc 0:9555690e7705 121 * - QEI_COMPPOS_CH_2: QEI compare position channel 2
fblanc 0:9555690e7705 122 * @param[in] ulPosComp Compare Position value to set
fblanc 0:9555690e7705 123 * @return None
fblanc 0:9555690e7705 124 */
fblanc 0:9555690e7705 125 void SetPositionComp( uint8_t bPosCompCh, uint32_t ulPosComp);
fblanc 0:9555690e7705 126
fblanc 0:9555690e7705 127 /** Get current index counter of QEI peripheral
fblanc 0:9555690e7705 128 *
fblanc 0:9555690e7705 129 * @return Current value of QEI index counter
fblanc 0:9555690e7705 130 */
fblanc 0:9555690e7705 131 uint32_t GetIndex();
fblanc 0:9555690e7705 132
fblanc 0:9555690e7705 133 /** Set value for index compare in QEI peripheral
fblanc 0:9555690e7705 134 * @param[in] ulIndexComp Compare Index Value to set
fblanc 0:9555690e7705 135 * @return None
fblanc 0:9555690e7705 136 */
fblanc 0:9555690e7705 137 void SetIndexComp( uint32_t ulIndexComp);
fblanc 0:9555690e7705 138
fblanc 0:9555690e7705 139 /** Set Velocity timer reload value
fblanc 0:9555690e7705 140 *
fblanc 0:9555690e7705 141 * @param[in] ulReloadValue Velocity timer reload count
fblanc 0:9555690e7705 142 * @return None
fblanc 0:9555690e7705 143 */
fblanc 0:9555690e7705 144 void SetVelocityTimerReload( uint32_t ulReloadValue);
fblanc 0:9555690e7705 145
fblanc 0:9555690e7705 146 /** Set Velocity timer reload value in microseconds
fblanc 0:9555690e7705 147 *
fblanc 0:9555690e7705 148 * @param[in] ulReloadValue Velocity timer reload count
fblanc 0:9555690e7705 149 * @return None
fblanc 0:9555690e7705 150 */
fblanc 0:9555690e7705 151 void SetVelocityTimerReload_us( uint32_t ulReloadValue);
fblanc 0:9555690e7705 152
fblanc 0:9555690e7705 153 /** Get current timer counter in QEI peripheral
fblanc 0:9555690e7705 154 *
fblanc 0:9555690e7705 155 * @return Current timer counter in QEI peripheral
fblanc 0:9555690e7705 156 */
fblanc 0:9555690e7705 157 uint32_t GetTimer();
fblanc 0:9555690e7705 158
fblanc 0:9555690e7705 159 /** Get current velocity pulse counter in current time period
fblanc 0:9555690e7705 160 *
fblanc 0:9555690e7705 161 * @return Current velocity pulse counter value
fblanc 0:9555690e7705 162 */
fblanc 0:9555690e7705 163 uint32_t GetVelocity();
fblanc 0:9555690e7705 164
fblanc 0:9555690e7705 165 /** Get the most recently measured velocity of the QEI. When
fblanc 0:9555690e7705 166 * the Velocity timer in QEI is over-flow, the current velocity
fblanc 0:9555690e7705 167 * value will be loaded into Velocity Capture register.
fblanc 0:9555690e7705 168 *
fblanc 0:9555690e7705 169 * @return The most recently measured velocity value
fblanc 0:9555690e7705 170 */
fblanc 0:9555690e7705 171 uint32_t GetVelocityCap();
fblanc 0:9555690e7705 172
fblanc 0:9555690e7705 173 /** Set Velocity Compare value for QEI peripheral
fblanc 0:9555690e7705 174 *
fblanc 0:9555690e7705 175 * @param[in] ulVelComp Compare Velocity value to set
fblanc 0:9555690e7705 176 * @return None
fblanc 0:9555690e7705 177 */
fblanc 0:9555690e7705 178 void SetVelocityComp( uint32_t ulVelComp);
fblanc 0:9555690e7705 179
fblanc 0:9555690e7705 180 /** Set value of sampling count for the digital filter in
fblanc 0:9555690e7705 181 * QEI peripheral
fblanc 0:9555690e7705 182 *
fblanc 0:9555690e7705 183 * @param[in] ulSamplingPulse Value of sampling count to set
fblanc 0:9555690e7705 184 * @return None
fblanc 0:9555690e7705 185 */
fblanc 0:9555690e7705 186 void SetDigiFilter( uint32_t ulSamplingPulse);
fblanc 0:9555690e7705 187
fblanc 0:9555690e7705 188 /** Check whether if specified interrupt flag status in QEI
fblanc 0:9555690e7705 189 * peripheral is set or not
fblanc 0:9555690e7705 190 *
fblanc 0:9555690e7705 191 * @param[in] ulIntType Interrupt Flag Status type, should be:
fblanc 0:9555690e7705 192 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:9555690e7705 193 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:9555690e7705 194 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:9555690e7705 195 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:9555690e7705 196 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:9555690e7705 197 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:9555690e7705 198 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:9555690e7705 199 current position interrupt
fblanc 0:9555690e7705 200 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:9555690e7705 201 current position interrupt
fblanc 0:9555690e7705 202 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:9555690e7705 203 current position interrupt
fblanc 0:9555690e7705 204 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:9555690e7705 205 index count interrupt
fblanc 0:9555690e7705 206 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:9555690e7705 207 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:9555690e7705 208 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:9555690e7705 209 * @return New State of specified interrupt flag status (SET or RESET)
fblanc 0:9555690e7705 210 */
fblanc 0:9555690e7705 211 FlagStatus GetIntStatus( uint32_t ulIntType);
fblanc 0:9555690e7705 212
fblanc 0:9555690e7705 213 /** Enable/Disable specified interrupt in QEI peripheral
fblanc 0:9555690e7705 214 *
fblanc 0:9555690e7705 215 * @param[in] ulIntType Interrupt Flag Status type, should be:
fblanc 0:9555690e7705 216 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:9555690e7705 217 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:9555690e7705 218 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:9555690e7705 219 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:9555690e7705 220 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:9555690e7705 221 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:9555690e7705 222 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:9555690e7705 223 * current position interrupt
fblanc 0:9555690e7705 224 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:9555690e7705 225 * current position interrupt
fblanc 0:9555690e7705 226 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:9555690e7705 227 * current position interrupt
fblanc 0:9555690e7705 228 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:9555690e7705 229 * index count interrupt
fblanc 0:9555690e7705 230 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:9555690e7705 231 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:9555690e7705 232 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:9555690e7705 233 * @param[in] NewState New function state, should be:
fblanc 0:9555690e7705 234 * - DISABLE
fblanc 0:9555690e7705 235 * - ENABLE
fblanc 0:9555690e7705 236 * @return None
fblanc 0:9555690e7705 237 */
fblanc 0:9555690e7705 238 void IntCmd( uint32_t ulIntType, FunctionalState NewState);
fblanc 0:9555690e7705 239
fblanc 0:9555690e7705 240 /** Asserts specified interrupt in QEI peripheral
fblanc 0:9555690e7705 241 *
fblanc 0:9555690e7705 242 * @param[in] ulIntType Interrupt Flag Status type, should be:
fblanc 0:9555690e7705 243 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:9555690e7705 244 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:9555690e7705 245 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:9555690e7705 246 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:9555690e7705 247 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:9555690e7705 248 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:9555690e7705 249 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:9555690e7705 250 current position interrupt
fblanc 0:9555690e7705 251 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:9555690e7705 252 current position interrupt
fblanc 0:9555690e7705 253 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:9555690e7705 254 current position interrupt
fblanc 0:9555690e7705 255 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:9555690e7705 256 index count interrupt
fblanc 0:9555690e7705 257 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:9555690e7705 258 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:9555690e7705 259 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:9555690e7705 260 * @return None
fblanc 0:9555690e7705 261 */
fblanc 0:9555690e7705 262 void IntSet( uint32_t ulIntType);
fblanc 0:9555690e7705 263
fblanc 0:9555690e7705 264 /** De-asserts specified interrupt (pending) in QEI peripheral
fblanc 0:9555690e7705 265 *
fblanc 0:9555690e7705 266 * @param[in] ulIntType Interrupt Flag Status type, should be:
fblanc 0:9555690e7705 267 - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:9555690e7705 268 - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:9555690e7705 269 - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:9555690e7705 270 - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:9555690e7705 271 - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:9555690e7705 272 - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:9555690e7705 273 - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:9555690e7705 274 current position interrupt
fblanc 0:9555690e7705 275 - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:9555690e7705 276 current position interrupt
fblanc 0:9555690e7705 277 - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:9555690e7705 278 current position interrupt
fblanc 0:9555690e7705 279 - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:9555690e7705 280 index count interrupt
fblanc 0:9555690e7705 281 - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:9555690e7705 282 - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:9555690e7705 283 - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:9555690e7705 284 * @return None
fblanc 0:9555690e7705 285 */
fblanc 0:9555690e7705 286 void IntClear( uint32_t ulIntType);
fblanc 0:9555690e7705 287
fblanc 0:9555690e7705 288 /** Append interrupt handler for specific QEI interrupt source
fblanc 0:9555690e7705 289 *
fblanc 0:9555690e7705 290 * @param[in] ulISRType Interrupt Flag Status type, should be:
fblanc 0:9555690e7705 291 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:9555690e7705 292 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:9555690e7705 293 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:9555690e7705 294 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:9555690e7705 295 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:9555690e7705 296 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:9555690e7705 297 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:9555690e7705 298 * current position interrupt
fblanc 0:9555690e7705 299 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:9555690e7705 300 * current position interrupt
fblanc 0:9555690e7705 301 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:9555690e7705 302 * current position interrupt
fblanc 0:9555690e7705 303 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:9555690e7705 304 * index count interrupt
fblanc 0:9555690e7705 305 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:9555690e7705 306 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:9555690e7705 307 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:9555690e7705 308 *
fblanc 0:9555690e7705 309 * @return none
fblanc 0:9555690e7705 310 */
fblanc 0:9555690e7705 311 void AppendISR(uint32_t ulISRType, void(*fptr)(void));
fblanc 0:9555690e7705 312
fblanc 0:9555690e7705 313 /** Unappend interrupt handler for specific QEI interrupt source
fblanc 0:9555690e7705 314 *
fblanc 0:9555690e7705 315 * @param[in] ulISRType Interrupt Flag Status type, should be:
fblanc 0:9555690e7705 316 * - QEI_INTFLAG_INX_Int: index pulse was detected interrupt
fblanc 0:9555690e7705 317 * - QEI_INTFLAG_TIM_Int: Velocity timer over flow interrupt
fblanc 0:9555690e7705 318 * - QEI_INTFLAG_VELC_Int: Capture velocity is less than compare interrupt
fblanc 0:9555690e7705 319 * - QEI_INTFLAG_DIR_Int: Change of direction interrupt
fblanc 0:9555690e7705 320 * - QEI_INTFLAG_ERR_Int: An encoder phase error interrupt
fblanc 0:9555690e7705 321 * - QEI_INTFLAG_ENCLK_Int: An encoder clock pulse was detected interrupt
fblanc 0:9555690e7705 322 * - QEI_INTFLAG_POS0_Int: position 0 compare value is equal to the
fblanc 0:9555690e7705 323 * current position interrupt
fblanc 0:9555690e7705 324 * - QEI_INTFLAG_POS1_Int: position 1 compare value is equal to the
fblanc 0:9555690e7705 325 * current position interrupt
fblanc 0:9555690e7705 326 * - QEI_INTFLAG_POS2_Int: position 2 compare value is equal to the
fblanc 0:9555690e7705 327 * current position interrupt
fblanc 0:9555690e7705 328 * - QEI_INTFLAG_REV_Int: Index compare value is equal to the current
fblanc 0:9555690e7705 329 * index count interrupt
fblanc 0:9555690e7705 330 * - QEI_INTFLAG_POS0REV_Int: Combined position 0 and revolution count interrupt
fblanc 0:9555690e7705 331 * - QEI_INTFLAG_POS1REV_Int: Combined position 1 and revolution count interrupt
fblanc 0:9555690e7705 332 * - QEI_INTFLAG_POS2REV_Int: Combined position 2 and revolution count interrupt
fblanc 0:9555690e7705 333 *
fblanc 0:9555690e7705 334 * @return none
fblanc 0:9555690e7705 335 */
fblanc 0:9555690e7705 336 void UnAppendISR(uint32_t ulISRType);
fblanc 0:9555690e7705 337
fblanc 0:9555690e7705 338
fblanc 0:9555690e7705 339 /**
fblanc 0:9555690e7705 340 * @brief Calculates the actual velocity in RPM passed via velocity
fblanc 0:9555690e7705 341 * capture value and Pulse Per Revolution (of the encoder) value
fblanc 0:9555690e7705 342 * parameter input.
fblanc 0:9555690e7705 343 *
fblanc 0:9555690e7705 344 * @param[in] ulVelCapValue Velocity capture input value that can
fblanc 0:9555690e7705 345 * be got from QEI_GetVelocityCap() function
fblanc 0:9555690e7705 346 * @param[in] ulPPR Pulse per round of encoder
fblanc 0:9555690e7705 347 * @return The actual value of velocity in RPM (Revolutions per minute)
fblanc 0:9555690e7705 348 */
fblanc 0:9555690e7705 349 uint32_t CalculateRPM( uint32_t ulVelCapValue, uint32_t ulPPR);
fblanc 0:9555690e7705 350
fblanc 0:9555690e7705 351
fblanc 0:9555690e7705 352 /* Public Macros -------------------------------------------------------------- */
fblanc 0:9555690e7705 353 /* QEI Reset types */
fblanc 0:9555690e7705 354 #define QEI_RESET_POS QEI_CON_RESP /**< Reset position counter */
fblanc 0:9555690e7705 355 #define QEI_RESET_POSOnIDX QEI_CON_RESPI /**< Reset Posistion Counter on Index */
fblanc 0:9555690e7705 356 #define QEI_RESET_VEL QEI_CON_RESV /**< Reset Velocity */
fblanc 0:9555690e7705 357 #define QEI_RESET_IDX QEI_CON_RESI /**< Reset Index Counter */
fblanc 0:9555690e7705 358
fblanc 0:9555690e7705 359 /* QEI Direction Invert Type Option */
fblanc 0:9555690e7705 360 #define QEI_DIRINV_NONE ((uint32_t)(0)) /**< Direction is not inverted */
fblanc 0:9555690e7705 361 #define QEI_DIRINV_CMPL ((uint32_t)(1)) /**< Direction is complemented */
fblanc 0:9555690e7705 362
fblanc 0:9555690e7705 363 /* QEI Signal Mode Option */
fblanc 0:9555690e7705 364 #define QEI_SIGNALMODE_QUAD ((uint32_t)(0)) /**< Signal operation: Quadrature phase mode */
fblanc 0:9555690e7705 365 #define QEI_SIGNALMODE_CLKDIR ((uint32_t)(1)) /**< Signal operation: Clock/Direction mode */
fblanc 0:9555690e7705 366
fblanc 0:9555690e7705 367 /* QEI Capture Mode Option */
fblanc 0:9555690e7705 368 #define QEI_CAPMODE_2X ((uint32_t)(0)) /**< Capture mode: Only Phase-A edges are counted (2X) */
fblanc 0:9555690e7705 369 #define QEI_CAPMODE_4X ((uint32_t)(1)) /**< Capture mode: BOTH PhA and PhB edges are counted (4X)*/
fblanc 0:9555690e7705 370
fblanc 0:9555690e7705 371 /* QEI Invert Index Signal Option */
fblanc 0:9555690e7705 372 #define QEI_INVINX_NONE ((uint32_t)(0)) /**< Invert Index signal option: None */
fblanc 0:9555690e7705 373 #define QEI_INVINX_EN ((uint32_t)(1)) /**< Invert Index signal option: Enable */
fblanc 0:9555690e7705 374
fblanc 0:9555690e7705 375 /* QEI timer reload option */
fblanc 0:9555690e7705 376 #define QEI_TIMERRELOAD_TICKVAL ((uint8_t)(0)) /**< Reload value in absolute value */
fblanc 0:9555690e7705 377 #define QEI_TIMERRELOAD_USVAL ((uint8_t)(1)) /**< Reload value in microsecond value */
fblanc 0:9555690e7705 378
fblanc 0:9555690e7705 379 /* QEI Flag Status type */
fblanc 0:9555690e7705 380 #define QEI_STATUS_DIR ((uint32_t)(1<<0)) /**< Direction status */
fblanc 0:9555690e7705 381
fblanc 0:9555690e7705 382 /* QEI Compare Position channel option */
fblanc 0:9555690e7705 383 #define QEI_COMPPOS_CH_0 ((uint8_t)(0)) /**< QEI compare position channel 0 */
fblanc 0:9555690e7705 384 #define QEI_COMPPOS_CH_1 ((uint8_t)(1)) /**< QEI compare position channel 1 */
fblanc 0:9555690e7705 385 #define QEI_COMPPOS_CH_2 ((uint8_t)(2)) /**< QEI compare position channel 2 */
fblanc 0:9555690e7705 386
fblanc 0:9555690e7705 387 /* QEI interrupt flag type */
fblanc 0:9555690e7705 388 #define QEI_INTFLAG_INX_Int ((uint32_t)(1<<0)) /**< index pulse was detected interrupt */
fblanc 0:9555690e7705 389 #define QEI_INTFLAG_TIM_Int ((uint32_t)(1<<1)) /**< Velocity timer over flow interrupt */
fblanc 0:9555690e7705 390 #define QEI_INTFLAG_VELC_Int ((uint32_t)(1<<2)) /**< Capture velocity is less than compare interrupt */
fblanc 0:9555690e7705 391 #define QEI_INTFLAG_DIR_Int ((uint32_t)(1<<3)) /**< Change of direction interrupt */
fblanc 0:9555690e7705 392 #define QEI_INTFLAG_ERR_Int ((uint32_t)(1<<4)) /**< An encoder phase error interrupt */
fblanc 0:9555690e7705 393 #define QEI_INTFLAG_ENCLK_Int ((uint32_t)(1<<5)) /**< An encoder clock pulse was detected interrupt */
fblanc 0:9555690e7705 394 #define QEI_INTFLAG_POS0_Int ((uint32_t)(1<<6)) /**< position 0 compare value is equal to the
fblanc 0:9555690e7705 395 current position interrupt */
fblanc 0:9555690e7705 396 #define QEI_INTFLAG_POS1_Int ((uint32_t)(1<<7)) /**< position 1 compare value is equal to the
fblanc 0:9555690e7705 397 current position interrupt */
fblanc 0:9555690e7705 398 #define QEI_INTFLAG_POS2_Int ((uint32_t)(1<<8)) /**< position 2 compare value is equal to the
fblanc 0:9555690e7705 399 current position interrupt */
fblanc 0:9555690e7705 400 #define QEI_INTFLAG_REV_Int ((uint32_t)(1<<9)) /**< Index compare value is equal to the current
fblanc 0:9555690e7705 401 index count interrupt */
fblanc 0:9555690e7705 402 #define QEI_INTFLAG_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt */
fblanc 0:9555690e7705 403 #define QEI_INTFLAG_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt */
fblanc 0:9555690e7705 404 #define QEI_INTFLAG_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt */
fblanc 0:9555690e7705 405
fblanc 0:9555690e7705 406 /* QEI Process position reporting options */
fblanc 0:9555690e7705 407 #define QEI_PROCESS_OPERATE 0;
fblanc 0:9555690e7705 408 #define QEI_PROCESS_RESET 1;
fblanc 0:9555690e7705 409 #define QEI_PROCESS_INCREMENTAL 0;
fblanc 0:9555690e7705 410 #define QEI_PROCESS_ACCUMULATE 1;
fblanc 0:9555690e7705 411 #define QEI_PROCESS_LINEAR 0;
fblanc 0:9555690e7705 412 #define QEI_PROCESS_WEIGHTED 1;
fblanc 0:9555690e7705 413
fblanc 0:9555690e7705 414 private:
fblanc 0:9555690e7705 415 static void _Qeiisr(void);
fblanc 0:9555690e7705 416 void Qeiisr(void);
fblanc 0:9555690e7705 417 static QEIHW *instance;
fblanc 0:9555690e7705 418
fblanc 0:9555690e7705 419 void(*_qei_isr[13])();
fblanc 0:9555690e7705 420
fblanc 0:9555690e7705 421
fblanc 0:9555690e7705 422 /* Private Macros ------------------------------------------------------------- */
fblanc 0:9555690e7705 423 /* --------------------- BIT DEFINITIONS -------------------------------------- */
fblanc 0:9555690e7705 424 /* Quadrature Encoder Interface Control Register Definition --------------------- */
fblanc 0:9555690e7705 425 /*********************************************************************//**
fblanc 0:9555690e7705 426 * Macro defines for QEI Control register
fblanc 0:9555690e7705 427 **********************************************************************/
fblanc 0:9555690e7705 428 #define QEI_CON_RESP ((uint32_t)(1<<0)) /**< Reset position counter */
fblanc 0:9555690e7705 429 #define QEI_CON_RESPI ((uint32_t)(1<<1)) /**< Reset Posistion Counter on Index */
fblanc 0:9555690e7705 430 #define QEI_CON_RESV ((uint32_t)(1<<2)) /**< Reset Velocity */
fblanc 0:9555690e7705 431 #define QEI_CON_RESI ((uint32_t)(1<<3)) /**< Reset Index Counter */
fblanc 0:9555690e7705 432 #define QEI_CON_BITMASK ((uint32_t)(0x0F)) /**< QEI Control register bit-mask */
fblanc 0:9555690e7705 433
fblanc 0:9555690e7705 434 /*********************************************************************//**
fblanc 0:9555690e7705 435 * Macro defines for QEI Configuration register
fblanc 0:9555690e7705 436 **********************************************************************/
fblanc 0:9555690e7705 437 #define QEI_CONF_DIRINV ((uint32_t)(1<<0)) /**< Direction Invert */
fblanc 0:9555690e7705 438 #define QEI_CONF_SIGMODE ((uint32_t)(1<<1)) /**< Signal mode */
fblanc 0:9555690e7705 439 #define QEI_CONF_CAPMODE ((uint32_t)(1<<2)) /**< Capture mode */
fblanc 0:9555690e7705 440 #define QEI_CONF_INVINX ((uint32_t)(1<<3)) /**< Invert index */
fblanc 0:9555690e7705 441 #define QEI_CONF_BITMASK ((uint32_t)(0x0F)) /**< QEI Configuration register bit-mask */
fblanc 0:9555690e7705 442
fblanc 0:9555690e7705 443 /*********************************************************************//**
fblanc 0:9555690e7705 444 * Macro defines for QEI Status register
fblanc 0:9555690e7705 445 **********************************************************************/
fblanc 0:9555690e7705 446 #define QEI_STAT_DIR ((uint32_t)(1<<0)) /**< Direction bit */
fblanc 0:9555690e7705 447 #define QEI_STAT_BITMASK ((uint32_t)(1<<0)) /**< QEI status register bit-mask */
fblanc 0:9555690e7705 448
fblanc 0:9555690e7705 449 /* Quadrature Encoder Interface Interrupt registers definitions --------------------- */
fblanc 0:9555690e7705 450 /*********************************************************************//**
fblanc 0:9555690e7705 451 * Macro defines for QEI Interrupt Status register
fblanc 0:9555690e7705 452 **********************************************************************/
fblanc 0:9555690e7705 453 #define QEI_INTSTAT_INX_Int ((uint32_t)(1<<0)) /**< Indicates that an index pulse was detected */
fblanc 0:9555690e7705 454 #define QEI_INTSTAT_TIM_Int ((uint32_t)(1<<1)) /**< Indicates that a velocity timer overflow occurred */
fblanc 0:9555690e7705 455 #define QEI_INTSTAT_VELC_Int ((uint32_t)(1<<2)) /**< Indicates that capture velocity is less than compare velocity */
fblanc 0:9555690e7705 456 #define QEI_INTSTAT_DIR_Int ((uint32_t)(1<<3)) /**< Indicates that a change of direction was detected */
fblanc 0:9555690e7705 457 #define QEI_INTSTAT_ERR_Int ((uint32_t)(1<<4)) /**< Indicates that an encoder phase error was detected */
fblanc 0:9555690e7705 458 #define QEI_INTSTAT_ENCLK_Int ((uint32_t)(1<<5)) /**< Indicates that and encoder clock pulse was detected */
fblanc 0:9555690e7705 459 #define QEI_INTSTAT_POS0_Int ((uint32_t)(1<<6)) /**< Indicates that the position 0 compare value is equal to the
fblanc 0:9555690e7705 460 current position */
fblanc 0:9555690e7705 461 #define QEI_INTSTAT_POS1_Int ((uint32_t)(1<<7)) /**< Indicates that the position 1compare value is equal to the
fblanc 0:9555690e7705 462 current position */
fblanc 0:9555690e7705 463 #define QEI_INTSTAT_POS2_Int ((uint32_t)(1<<8)) /**< Indicates that the position 2 compare value is equal to the
fblanc 0:9555690e7705 464 current position */
fblanc 0:9555690e7705 465 #define QEI_INTSTAT_REV_Int ((uint32_t)(1<<9)) /**< Indicates that the index compare value is equal to the current
fblanc 0:9555690e7705 466 index count */
fblanc 0:9555690e7705 467 #define QEI_INTSTAT_POS0REV_Int ((uint32_t)(1<<10)) /**< Combined position 0 and revolution count interrupt. Set when
fblanc 0:9555690e7705 468 both the POS0_Int bit is set and the REV_Int is set */
fblanc 0:9555690e7705 469 #define QEI_INTSTAT_POS1REV_Int ((uint32_t)(1<<11)) /**< Combined position 1 and revolution count interrupt. Set when
fblanc 0:9555690e7705 470 both the POS1_Int bit is set and the REV_Int is set */
fblanc 0:9555690e7705 471 #define QEI_INTSTAT_POS2REV_Int ((uint32_t)(1<<12)) /**< Combined position 2 and revolution count interrupt. Set when
fblanc 0:9555690e7705 472 both the POS2_Int bit is set and the REV_Int is set */
fblanc 0:9555690e7705 473 #define QEI_INTSTAT_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Status register bit-mask */
fblanc 0:9555690e7705 474
fblanc 0:9555690e7705 475 /*********************************************************************//**
fblanc 0:9555690e7705 476 * Macro defines for QEI Interrupt Set register
fblanc 0:9555690e7705 477 **********************************************************************/
fblanc 0:9555690e7705 478 #define QEI_INTSET_INX_Int ((uint32_t)(1<<0)) /**< Set Bit Indicates that an index pulse was detected */
fblanc 0:9555690e7705 479 #define QEI_INTSET_TIM_Int ((uint32_t)(1<<1)) /**< Set Bit Indicates that a velocity timer overflow occurred */
fblanc 0:9555690e7705 480 #define QEI_INTSET_VELC_Int ((uint32_t)(1<<2)) /**< Set Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:9555690e7705 481 #define QEI_INTSET_DIR_Int ((uint32_t)(1<<3)) /**< Set Bit Indicates that a change of direction was detected */
fblanc 0:9555690e7705 482 #define QEI_INTSET_ERR_Int ((uint32_t)(1<<4)) /**< Set Bit Indicates that an encoder phase error was detected */
fblanc 0:9555690e7705 483 #define QEI_INTSET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Bit Indicates that and encoder clock pulse was detected */
fblanc 0:9555690e7705 484 #define QEI_INTSET_POS0_Int ((uint32_t)(1<<6)) /**< Set Bit Indicates that the position 0 compare value is equal to the
fblanc 0:9555690e7705 485 current position */
fblanc 0:9555690e7705 486 #define QEI_INTSET_POS1_Int ((uint32_t)(1<<7)) /**< Set Bit Indicates that the position 1compare value is equal to the
fblanc 0:9555690e7705 487 current position */
fblanc 0:9555690e7705 488 #define QEI_INTSET_POS2_Int ((uint32_t)(1<<8)) /**< Set Bit Indicates that the position 2 compare value is equal to the
fblanc 0:9555690e7705 489 current position */
fblanc 0:9555690e7705 490 #define QEI_INTSET_REV_Int ((uint32_t)(1<<9)) /**< Set Bit Indicates that the index compare value is equal to the current
fblanc 0:9555690e7705 491 index count */
fblanc 0:9555690e7705 492 #define QEI_INTSET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Bit that combined position 0 and revolution count interrupt */
fblanc 0:9555690e7705 493 #define QEI_INTSET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Bit that Combined position 1 and revolution count interrupt */
fblanc 0:9555690e7705 494 #define QEI_INTSET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Bit that Combined position 2 and revolution count interrupt */
fblanc 0:9555690e7705 495 #define QEI_INTSET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Set register bit-mask */
fblanc 0:9555690e7705 496
fblanc 0:9555690e7705 497 /*********************************************************************//**
fblanc 0:9555690e7705 498 * Macro defines for QEI Interrupt Clear register
fblanc 0:9555690e7705 499 **********************************************************************/
fblanc 0:9555690e7705 500 #define QEI_INTCLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Bit Indicates that an index pulse was detected */
fblanc 0:9555690e7705 501 #define QEI_INTCLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Bit Indicates that a velocity timer overflow occurred */
fblanc 0:9555690e7705 502 #define QEI_INTCLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:9555690e7705 503 #define QEI_INTCLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Bit Indicates that a change of direction was detected */
fblanc 0:9555690e7705 504 #define QEI_INTCLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Bit Indicates that an encoder phase error was detected */
fblanc 0:9555690e7705 505 #define QEI_INTCLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Bit Indicates that and encoder clock pulse was detected */
fblanc 0:9555690e7705 506 #define QEI_INTCLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Bit Indicates that the position 0 compare value is equal to the
fblanc 0:9555690e7705 507 current position */
fblanc 0:9555690e7705 508 #define QEI_INTCLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Bit Indicates that the position 1compare value is equal to the
fblanc 0:9555690e7705 509 current position */
fblanc 0:9555690e7705 510 #define QEI_INTCLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Bit Indicates that the position 2 compare value is equal to the
fblanc 0:9555690e7705 511 current position */
fblanc 0:9555690e7705 512 #define QEI_INTCLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Bit Indicates that the index compare value is equal to the current
fblanc 0:9555690e7705 513 index count */
fblanc 0:9555690e7705 514 #define QEI_INTCLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Bit that combined position 0 and revolution count interrupt */
fblanc 0:9555690e7705 515 #define QEI_INTCLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Bit that Combined position 1 and revolution count interrupt */
fblanc 0:9555690e7705 516 #define QEI_INTCLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Bit that Combined position 2 and revolution count interrupt */
fblanc 0:9555690e7705 517 #define QEI_INTCLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Clear register bit-mask */
fblanc 0:9555690e7705 518
fblanc 0:9555690e7705 519 /*********************************************************************//**
fblanc 0:9555690e7705 520 * Macro defines for QEI Interrupt Enable register
fblanc 0:9555690e7705 521 **********************************************************************/
fblanc 0:9555690e7705 522 #define QEI_INTEN_INX_Int ((uint32_t)(1<<0)) /**< Enabled Interrupt Bit Indicates that an index pulse was detected */
fblanc 0:9555690e7705 523 #define QEI_INTEN_TIM_Int ((uint32_t)(1<<1)) /**< Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
fblanc 0:9555690e7705 524 #define QEI_INTEN_VELC_Int ((uint32_t)(1<<2)) /**< Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:9555690e7705 525 #define QEI_INTEN_DIR_Int ((uint32_t)(1<<3)) /**< Enabled Interrupt Bit Indicates that a change of direction was detected */
fblanc 0:9555690e7705 526 #define QEI_INTEN_ERR_Int ((uint32_t)(1<<4)) /**< Enabled Interrupt Bit Indicates that an encoder phase error was detected */
fblanc 0:9555690e7705 527 #define QEI_INTEN_ENCLK_Int ((uint32_t)(1<<5)) /**< Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
fblanc 0:9555690e7705 528 #define QEI_INTEN_POS0_Int ((uint32_t)(1<<6)) /**< Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
fblanc 0:9555690e7705 529 current position */
fblanc 0:9555690e7705 530 #define QEI_INTEN_POS1_Int ((uint32_t)(1<<7)) /**< Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
fblanc 0:9555690e7705 531 current position */
fblanc 0:9555690e7705 532 #define QEI_INTEN_POS2_Int ((uint32_t)(1<<8)) /**< Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
fblanc 0:9555690e7705 533 current position */
fblanc 0:9555690e7705 534 #define QEI_INTEN_REV_Int ((uint32_t)(1<<9)) /**< Enabled Interrupt Bit Indicates that the index compare value is equal to the current
fblanc 0:9555690e7705 535 index count */
fblanc 0:9555690e7705 536 #define QEI_INTEN_POS0REV_Int ((uint32_t)(1<<10)) /**< Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
fblanc 0:9555690e7705 537 #define QEI_INTEN_POS1REV_Int ((uint32_t)(1<<11)) /**< Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
fblanc 0:9555690e7705 538 #define QEI_INTEN_POS2REV_Int ((uint32_t)(1<<12)) /**< Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
fblanc 0:9555690e7705 539 #define QEI_INTEN_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable register bit-mask */
fblanc 0:9555690e7705 540
fblanc 0:9555690e7705 541 /*********************************************************************//**
fblanc 0:9555690e7705 542 * Macro defines for QEI Interrupt Enable Set register
fblanc 0:9555690e7705 543 **********************************************************************/
fblanc 0:9555690e7705 544 #define QEI_IESET_INX_Int ((uint32_t)(1<<0)) /**< Set Enable Interrupt Bit Indicates that an index pulse was detected */
fblanc 0:9555690e7705 545 #define QEI_IESET_TIM_Int ((uint32_t)(1<<1)) /**< Set Enable Interrupt Bit Indicates that a velocity timer overflow occurred */
fblanc 0:9555690e7705 546 #define QEI_IESET_VELC_Int ((uint32_t)(1<<2)) /**< Set Enable Interrupt Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:9555690e7705 547 #define QEI_IESET_DIR_Int ((uint32_t)(1<<3)) /**< Set Enable Interrupt Bit Indicates that a change of direction was detected */
fblanc 0:9555690e7705 548 #define QEI_IESET_ERR_Int ((uint32_t)(1<<4)) /**< Set Enable Interrupt Bit Indicates that an encoder phase error was detected */
fblanc 0:9555690e7705 549 #define QEI_IESET_ENCLK_Int ((uint32_t)(1<<5)) /**< Set Enable Interrupt Bit Indicates that and encoder clock pulse was detected */
fblanc 0:9555690e7705 550 #define QEI_IESET_POS0_Int ((uint32_t)(1<<6)) /**< Set Enable Interrupt Bit Indicates that the position 0 compare value is equal to the
fblanc 0:9555690e7705 551 current position */
fblanc 0:9555690e7705 552 #define QEI_IESET_POS1_Int ((uint32_t)(1<<7)) /**< Set Enable Interrupt Bit Indicates that the position 1compare value is equal to the
fblanc 0:9555690e7705 553 current position */
fblanc 0:9555690e7705 554 #define QEI_IESET_POS2_Int ((uint32_t)(1<<8)) /**< Set Enable Interrupt Bit Indicates that the position 2 compare value is equal to the
fblanc 0:9555690e7705 555 current position */
fblanc 0:9555690e7705 556 #define QEI_IESET_REV_Int ((uint32_t)(1<<9)) /**< Set Enable Interrupt Bit Indicates that the index compare value is equal to the current
fblanc 0:9555690e7705 557 index count */
fblanc 0:9555690e7705 558 #define QEI_IESET_POS0REV_Int ((uint32_t)(1<<10)) /**< Set Enable Interrupt Bit that combined position 0 and revolution count interrupt */
fblanc 0:9555690e7705 559 #define QEI_IESET_POS1REV_Int ((uint32_t)(1<<11)) /**< Set Enable Interrupt Bit that Combined position 1 and revolution count interrupt */
fblanc 0:9555690e7705 560 #define QEI_IESET_POS2REV_Int ((uint32_t)(1<<12)) /**< Set Enable Interrupt Bit that Combined position 2 and revolution count interrupt */
fblanc 0:9555690e7705 561 #define QEI_IESET_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Set register bit-mask */
fblanc 0:9555690e7705 562
fblanc 0:9555690e7705 563 /*********************************************************************//**
fblanc 0:9555690e7705 564 * Macro defines for QEI Interrupt Enable Clear register
fblanc 0:9555690e7705 565 **********************************************************************/
fblanc 0:9555690e7705 566 #define QEI_IECLR_INX_Int ((uint32_t)(1<<0)) /**< Clear Enabled Interrupt Bit Indicates that an index pulse was detected */
fblanc 0:9555690e7705 567 #define QEI_IECLR_TIM_Int ((uint32_t)(1<<1)) /**< Clear Enabled Interrupt Bit Indicates that a velocity timer overflow occurred */
fblanc 0:9555690e7705 568 #define QEI_IECLR_VELC_Int ((uint32_t)(1<<2)) /**< Clear Enabled Interrupt Bit Indicates that capture velocity is less than compare velocity */
fblanc 0:9555690e7705 569 #define QEI_IECLR_DIR_Int ((uint32_t)(1<<3)) /**< Clear Enabled Interrupt Bit Indicates that a change of direction was detected */
fblanc 0:9555690e7705 570 #define QEI_IECLR_ERR_Int ((uint32_t)(1<<4)) /**< Clear Enabled Interrupt Bit Indicates that an encoder phase error was detected */
fblanc 0:9555690e7705 571 #define QEI_IECLR_ENCLK_Int ((uint32_t)(1<<5)) /**< Clear Enabled Interrupt Bit Indicates that and encoder clock pulse was detected */
fblanc 0:9555690e7705 572 #define QEI_IECLR_POS0_Int ((uint32_t)(1<<6)) /**< Clear Enabled Interrupt Bit Indicates that the position 0 compare value is equal to the
fblanc 0:9555690e7705 573 current position */
fblanc 0:9555690e7705 574 #define QEI_IECLR_POS1_Int ((uint32_t)(1<<7)) /**< Clear Enabled Interrupt Bit Indicates that the position 1compare value is equal to the
fblanc 0:9555690e7705 575 current position */
fblanc 0:9555690e7705 576 #define QEI_IECLR_POS2_Int ((uint32_t)(1<<8)) /**< Clear Enabled Interrupt Bit Indicates that the position 2 compare value is equal to the
fblanc 0:9555690e7705 577 current position */
fblanc 0:9555690e7705 578 #define QEI_IECLR_REV_Int ((uint32_t)(1<<9)) /**< Clear Enabled Interrupt Bit Indicates that the index compare value is equal to the current
fblanc 0:9555690e7705 579 index count */
fblanc 0:9555690e7705 580 #define QEI_IECLR_POS0REV_Int ((uint32_t)(1<<10)) /**< Clear Enabled Interrupt Bit that combined position 0 and revolution count interrupt */
fblanc 0:9555690e7705 581 #define QEI_IECLR_POS1REV_Int ((uint32_t)(1<<11)) /**< Clear Enabled Interrupt Bit that Combined position 1 and revolution count interrupt */
fblanc 0:9555690e7705 582 #define QEI_IECLR_POS2REV_Int ((uint32_t)(1<<12)) /**< Clear Enabled Interrupt Bit that Combined position 2 and revolution count interrupt */
fblanc 0:9555690e7705 583 #define QEI_IECLR_BITMASK ((uint32_t)(0x1FFF)) /**< QEI Interrupt Enable Clear register bit-mask */
fblanc 0:9555690e7705 584
fblanc 0:9555690e7705 585 /*********************************************************************//**
fblanc 0:9555690e7705 586 * Macro defines for PCONP register QEI-related bits
fblanc 0:9555690e7705 587 **********************************************************************/
fblanc 0:9555690e7705 588 #define PCONP_QEI_ENABLE ((uint32_t)(1<<18)) /**< QEI peripheral power enable bit */
fblanc 0:9555690e7705 589 #define PCONP_QEI_DISABLE ~((uint32_t)(1<<18)) /**< QEI peripheral power disable bit-mask */
fblanc 0:9555690e7705 590
fblanc 0:9555690e7705 591 /*********************************************************************//**
fblanc 0:9555690e7705 592 * Macro defines for PCLKSELx register QEI-related bits
fblanc 0:9555690e7705 593 **********************************************************************/
fblanc 0:9555690e7705 594 #define PCLKSEL_CCLK_DIV_1 1UL /**< Set PCLK to CCLK/1 */
fblanc 0:9555690e7705 595 #define PCLKSEL_CCLK_DIV_2 2UL /**< Set PCLK to CCLK/2 */
fblanc 0:9555690e7705 596 #define PCLKSEL_CCLK_DIV_4 0UL /**< Set PCLK to CCLK/4 */
fblanc 0:9555690e7705 597 #define PCLKSEL_CCLK_DIV_8 3UL /**< Set PCLK to CCLK/8 */
fblanc 0:9555690e7705 598 #define PCLKSEL1_PCLK_QEI_MASK ((uint32_t)(3<<0)) /**< PCLK_QEI PCLK_QEI bit field mask */
fblanc 0:9555690e7705 599 /*********************************************************************//**
fblanc 0:9555690e7705 600 * Macro defines for PINSEL3 register QEI-related bits
fblanc 0:9555690e7705 601 **********************************************************************/
fblanc 0:9555690e7705 602 #define PINSEL3_MCI0 ((uint32_t)(1<<8)) /**< MCIO (PhA) pin select */
fblanc 0:9555690e7705 603 #define PINSEL3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) pin mask */
fblanc 0:9555690e7705 604 #define PINSEL3_MCI1 ((uint32_t)(1<<14)) /**< MCI1 (PhB) pin select */
fblanc 0:9555690e7705 605 #define PINSEL3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI2 (PhB) pin mask */
fblanc 0:9555690e7705 606 #define PINSEL3_MCI2 ((uint32_t)(1<<16)) /**< MCI2 (Index) pin select */
fblanc 0:9555690e7705 607 #define PINSEL3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) pin mask */
fblanc 0:9555690e7705 608
fblanc 0:9555690e7705 609 /*********************************************************************//**
fblanc 0:9555690e7705 610 * Macro defines for PINMODE3 register QEI-related bits
fblanc 0:9555690e7705 611 **********************************************************************/
fblanc 0:9555690e7705 612 #define PIN_PULL_UP 0UL
fblanc 0:9555690e7705 613 #define PIN_REPEATER 1UL
fblanc 0:9555690e7705 614 #define PIN_NORESISTOR 2UL
fblanc 0:9555690e7705 615 #define PIN_PULL_DOWN 3UL
fblanc 0:9555690e7705 616
fblanc 0:9555690e7705 617 #define PINMODE3_MCI0 ((uint32_t)(PIN_NORESISTOR<<8)) /**< MCIO (PhA) resistor selection */
fblanc 0:9555690e7705 618 #define PINMODE3_GPIO1p20 ((uint32_t)(PIN_PULL_DOWN<<8)) /**< GPIO 1.20) resistor selection */
fblanc 0:9555690e7705 619 #define PINMODE3_MCI0_MASK ~((uint32_t)(3<<8)) /**< MCIO (PhA) resistor mask */
fblanc 0:9555690e7705 620
fblanc 0:9555690e7705 621 #define PINMODE3_MCI1 ((uint32_t)(PIN_NORESISTOR<<14)) /**< MCI1 (PhB) resistor selection */
fblanc 0:9555690e7705 622 #define PINMODE3_GPIO1p23 ((uint32_t)(PIN_PULL_DOWN<<14)) /**< GPIO 1.23) resistor selection */
fblanc 0:9555690e7705 623 #define PINMODE3_MCI1_MASK ~((uint32_t)(3<<14)) /**< MCI1 (PhB) resistor mask */
fblanc 0:9555690e7705 624
fblanc 0:9555690e7705 625 #define PINMODE3_MCI2 ((uint32_t)(PIN_PULL_UP<<16)) /**< MCI2 (Index) resistor selection */
fblanc 0:9555690e7705 626 #define PINMODE3_GPIO1p24 ((uint32_t)(PIN_PULL_DOWN<<16)) /**< GPIO 1.24) resistor selection */
fblanc 0:9555690e7705 627 #define PINMODE3_MCI2_MASK ~((uint32_t)(3<<16)) /**< MCI2 (Index) resistor mask */
fblanc 0:9555690e7705 628
fblanc 0:9555690e7705 629 };
fblanc 0:9555690e7705 630
fblanc 0:9555690e7705 631
fblanc 0:9555690e7705 632 #endif /* MBED_QEI_H */
fblanc 0:9555690e7705 633 /* --------------------------------- End Of File ------------------------------ */