frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_NUCLEO_F401RE/stm32f4xx_hal_pwr_ex.h@90:cb3d968589d8, 2014-10-28 (annotated)

Committer:
Kojto
Date:
Tue Oct 28 16:40:41 2014 +0000
Revision:
90:cb3d968589d8
Parent:
85:024bf7f99721 
Release 90 of the mbed library



Changes:



- Freescale KSDK update (v1.0)

- K22 - new target addition

- KL43Z - new target addition

- Nucleo F091RC - new target addition

- Nucleo L152RE - STM32Cube driver

- Nordic - Softdevice v7.1.0

- Nvic files - BSD License

- LPC824 - various HAL fixes

- Nucleo F411RE - CMSIS - IAR files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 77:869cf507173a 1 /**
emilmont 77:869cf507173a 2 ******************************************************************************
emilmont 77:869cf507173a 3 * @file stm32f4xx_hal_pwr_ex.h
emilmont 77:869cf507173a 4 * @author MCD Application Team
Kojto 90:cb3d968589d8 5 * @version V1.1.0
Kojto 90:cb3d968589d8 6 * @date 19-June-2014
emilmont 77:869cf507173a 7 * @brief Header file of PWR HAL Extension module.
emilmont 77:869cf507173a 8 ******************************************************************************
emilmont 77:869cf507173a 9 * @attention
emilmont 77:869cf507173a 10 *
emilmont 77:869cf507173a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
emilmont 77:869cf507173a 12 *
emilmont 77:869cf507173a 13 * Redistribution and use in source and binary forms, with or without modification,
emilmont 77:869cf507173a 14 * are permitted provided that the following conditions are met:
emilmont 77:869cf507173a 15 * 1. Redistributions of source code must retain the above copyright notice,
emilmont 77:869cf507173a 16 * this list of conditions and the following disclaimer.
emilmont 77:869cf507173a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont 77:869cf507173a 18 * this list of conditions and the following disclaimer in the documentation
emilmont 77:869cf507173a 19 * and/or other materials provided with the distribution.
emilmont 77:869cf507173a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont 77:869cf507173a 21 * may be used to endorse or promote products derived from this software
emilmont 77:869cf507173a 22 * without specific prior written permission.
emilmont 77:869cf507173a 23 *
emilmont 77:869cf507173a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont 77:869cf507173a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont 77:869cf507173a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont 77:869cf507173a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont 77:869cf507173a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont 77:869cf507173a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont 77:869cf507173a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont 77:869cf507173a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont 77:869cf507173a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont 77:869cf507173a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont 77:869cf507173a 34 *
emilmont 77:869cf507173a 35 ******************************************************************************
emilmont 77:869cf507173a 36 */
emilmont 77:869cf507173a 37
emilmont 77:869cf507173a 38 /* Define to prevent recursive inclusion -------------------------------------*/
emilmont 77:869cf507173a 39 #ifndef __STM32F4xx_HAL_PWR_EX_H
emilmont 77:869cf507173a 40 #define __STM32F4xx_HAL_PWR_EX_H
emilmont 77:869cf507173a 41
emilmont 77:869cf507173a 42 #ifdef __cplusplus
emilmont 77:869cf507173a 43 extern "C" {
emilmont 77:869cf507173a 44 #endif
emilmont 77:869cf507173a 45
emilmont 77:869cf507173a 46 /* Includes ------------------------------------------------------------------*/
emilmont 77:869cf507173a 47 #include "stm32f4xx_hal_def.h"
emilmont 77:869cf507173a 48
emilmont 77:869cf507173a 49 /** @addtogroup STM32F4xx_HAL_Driver
emilmont 77:869cf507173a 50 * @{
emilmont 77:869cf507173a 51 */
emilmont 77:869cf507173a 52
emilmont 77:869cf507173a 53 /** @addtogroup PWREx
emilmont 77:869cf507173a 54 * @{
emilmont 77:869cf507173a 55 */
emilmont 77:869cf507173a 56
emilmont 77:869cf507173a 57 /* Exported types ------------------------------------------------------------*/
emilmont 77:869cf507173a 58 /* Exported constants --------------------------------------------------------*/
emilmont 77:869cf507173a 59 /* ------------- PWR registers bit address in the alias region ---------------*/
emilmont 77:869cf507173a 60 /* --- CR Register ---*/
Kojto 90:cb3d968589d8 61 /* Alias word address of FPDS bit */
Kojto 90:cb3d968589d8 62 #define FPDS_BitNumber 0x09
Kojto 90:cb3d968589d8 63 #define CR_FPDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
emilmont 77:869cf507173a 64
emilmont 77:869cf507173a 65 /* Alias word address of ODEN bit */
emilmont 77:869cf507173a 66 #define ODEN_BitNumber 0x10
emilmont 77:869cf507173a 67 #define CR_ODEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODEN_BitNumber * 4))
emilmont 77:869cf507173a 68
emilmont 77:869cf507173a 69 /* Alias word address of ODSWEN bit */
emilmont 77:869cf507173a 70 #define ODSWEN_BitNumber 0x11
emilmont 77:869cf507173a 71 #define CR_ODSWEN_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (ODSWEN_BitNumber * 4))
emilmont 77:869cf507173a 72
Kojto 90:cb3d968589d8 73 /* Alias word address of MRLVDS bit */
Kojto 90:cb3d968589d8 74 #define MRLVDS_BitNumber 0x0B
Kojto 90:cb3d968589d8 75 #define CR_MRLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (MRLVDS_BitNumber * 4))
emilmont 77:869cf507173a 76
Kojto 90:cb3d968589d8 77 /* Alias word address of LPLVDS bit */
Kojto 90:cb3d968589d8 78 #define LPLVDS_BitNumber 0x0A
Kojto 90:cb3d968589d8 79 #define CR_LPLVDS_BB (PERIPH_BB_BASE + (CR_OFFSET * 32) + (LPLVDS_BitNumber * 4))
Kojto 90:cb3d968589d8 80
Kojto 90:cb3d968589d8 81 /* --- CSR Register ---*/
Kojto 90:cb3d968589d8 82 /* Alias word address of BRE bit */
Kojto 90:cb3d968589d8 83 #define BRE_BitNumber 0x09
Kojto 90:cb3d968589d8 84 #define CSR_BRE_BB (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
Kojto 90:cb3d968589d8 85
Kojto 90:cb3d968589d8 86 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
Kojto 90:cb3d968589d8 87
Kojto 90:cb3d968589d8 88 /** @defgroup PWREx_Regulator_state_in_UnderDrive_mode
Kojto 90:cb3d968589d8 89 * @{
Kojto 90:cb3d968589d8 90 */
Kojto 90:cb3d968589d8 91 #define PWR_MAINREGULATOR_UNDERDRIVE_ON PWR_CR_MRUDS
Kojto 90:cb3d968589d8 92 #define PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON ((uint32_t)(PWR_CR_LPDS | PWR_CR_LPUDS))
Kojto 90:cb3d968589d8 93
Kojto 90:cb3d968589d8 94 #define IS_PWR_REGULATOR_UNDERDRIVE(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_UNDERDRIVE_ON) || \
Kojto 90:cb3d968589d8 95 ((REGULATOR) == PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON))
Kojto 90:cb3d968589d8 96 /**
Kojto 90:cb3d968589d8 97 * @}
Kojto 90:cb3d968589d8 98 */
Kojto 90:cb3d968589d8 99
emilmont 77:869cf507173a 100 /** @defgroup PWREx_Over_Under_Drive_Flag
emilmont 77:869cf507173a 101 * @{
emilmont 77:869cf507173a 102 */
emilmont 77:869cf507173a 103 #define PWR_FLAG_ODRDY PWR_CSR_ODRDY
emilmont 77:869cf507173a 104 #define PWR_FLAG_ODSWRDY PWR_CSR_ODSWRDY
emilmont 77:869cf507173a 105 #define PWR_FLAG_UDRDY PWR_CSR_UDSWRDY
emilmont 77:869cf507173a 106 /**
emilmont 77:869cf507173a 107 * @}
emilmont 77:869cf507173a 108 */
Kojto 90:cb3d968589d8 109 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 110 /**
emilmont 77:869cf507173a 111 * @}
emilmont 77:869cf507173a 112 */
emilmont 77:869cf507173a 113
emilmont 77:869cf507173a 114 /* Exported macro ------------------------------------------------------------*/
emilmont 77:869cf507173a 115
Kojto 90:cb3d968589d8 116 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
emilmont 77:869cf507173a 117 /** @brief Macros to enable or disable the Over drive mode.
emilmont 77:869cf507173a 118 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
emilmont 77:869cf507173a 119 */
emilmont 77:869cf507173a 120 #define __HAL_PWR_OVERDRIVE_ENABLE() (*(__IO uint32_t *) CR_ODEN_BB = ENABLE)
emilmont 77:869cf507173a 121 #define __HAL_PWR_OVERDRIVE_DISABLE() (*(__IO uint32_t *) CR_ODEN_BB = DISABLE)
emilmont 77:869cf507173a 122
emilmont 77:869cf507173a 123 /** @brief Macros to enable or disable the Over drive switching.
emilmont 77:869cf507173a 124 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
emilmont 77:869cf507173a 125 */
emilmont 77:869cf507173a 126 #define __HAL_PWR_OVERDRIVESWITCHING_ENABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = ENABLE)
emilmont 77:869cf507173a 127 #define __HAL_PWR_OVERDRIVESWITCHING_DISABLE() (*(__IO uint32_t *) CR_ODSWEN_BB = DISABLE)
emilmont 77:869cf507173a 128
emilmont 77:869cf507173a 129 /** @brief Macros to enable or disable the Under drive mode.
emilmont 77:869cf507173a 130 * @note This mode is enabled only with STOP low power mode.
emilmont 77:869cf507173a 131 * In this mode, the 1.2V domain is preserved in reduced leakage mode. This
emilmont 77:869cf507173a 132 * mode is only available when the main regulator or the low power regulator
emilmont 77:869cf507173a 133 * is in low voltage mode.
emilmont 77:869cf507173a 134 * @note If the Under-drive mode was enabled, it is automatically disabled after
emilmont 77:869cf507173a 135 * exiting Stop mode.
emilmont 77:869cf507173a 136 * When the voltage regulator operates in Under-drive mode, an additional
emilmont 77:869cf507173a 137 * startup delay is induced when waking up from Stop mode.
emilmont 77:869cf507173a 138 */
emilmont 77:869cf507173a 139 #define __HAL_PWR_UNDERDRIVE_ENABLE() (PWR->CR |= (uint32_t)PWR_CR_UDEN)
emilmont 77:869cf507173a 140 #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR &= (uint32_t)(~PWR_CR_UDEN))
emilmont 77:869cf507173a 141
emilmont 77:869cf507173a 142 /** @brief Check PWR flag is set or not.
emilmont 77:869cf507173a 143 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
emilmont 77:869cf507173a 144 * @param __FLAG__: specifies the flag to check.
emilmont 77:869cf507173a 145 * This parameter can be one of the following values:
emilmont 77:869cf507173a 146 * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
emilmont 77:869cf507173a 147 * is ready
emilmont 77:869cf507173a 148 * @arg PWR_FLAG_ODSWRDY: This flag indicates that the Over-drive mode
emilmont 77:869cf507173a 149 * switching is ready
emilmont 77:869cf507173a 150 * @arg PWR_FLAG_UDRDY: This flag indicates that the Under-drive mode
emilmont 77:869cf507173a 151 * is enabled in Stop mode
emilmont 77:869cf507173a 152 * @retval The new state of __FLAG__ (TRUE or FALSE).
emilmont 77:869cf507173a 153 */
emilmont 77:869cf507173a 154 #define __HAL_PWR_GET_ODRUDR_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
emilmont 77:869cf507173a 155
emilmont 77:869cf507173a 156 /** @brief Clear the Under-Drive Ready flag.
emilmont 77:869cf507173a 157 * @note These macros can be used only for STM32F42xx/STM3243xx devices.
emilmont 77:869cf507173a 158 */
emilmont 77:869cf507173a 159 #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR |= PWR_FLAG_UDRDY)
emilmont 77:869cf507173a 160
emilmont 77:869cf507173a 161 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 162
emilmont 77:869cf507173a 163 /* Exported functions --------------------------------------------------------*/
emilmont 77:869cf507173a 164 void HAL_PWREx_EnableFlashPowerDown(void);
emilmont 77:869cf507173a 165 void HAL_PWREx_DisableFlashPowerDown(void);
emilmont 77:869cf507173a 166 HAL_StatusTypeDef HAL_PWREx_EnableBkUpReg(void);
emilmont 77:869cf507173a 167 HAL_StatusTypeDef HAL_PWREx_DisableBkUpReg(void);
emilmont 77:869cf507173a 168
Kojto 90:cb3d968589d8 169 #if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE)
Kojto 90:cb3d968589d8 170 void HAL_PWREx_EnableMainRegulatorLowVoltage(void);
Kojto 90:cb3d968589d8 171 void HAL_PWREx_DisableMainRegulatorLowVoltage(void);
Kojto 90:cb3d968589d8 172 void HAL_PWREx_EnableLowRegulatorLowVoltage(void);
Kojto 90:cb3d968589d8 173 void HAL_PWREx_DisableLowRegulatorLowVoltage(void);
Kojto 90:cb3d968589d8 174 #endif /* STM32F401xC || STM32F401xE || STM32F411xE */
Kojto 90:cb3d968589d8 175
emilmont 77:869cf507173a 176 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
emilmont 77:869cf507173a 177 HAL_StatusTypeDef HAL_PWREx_ActivateOverDrive(void);
emilmont 77:869cf507173a 178 HAL_StatusTypeDef HAL_PWREx_DeactivateOverDrive(void);
Kojto 90:cb3d968589d8 179 HAL_StatusTypeDef HAL_PWREx_EnterUnderDriveSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
emilmont 77:869cf507173a 180 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
emilmont 77:869cf507173a 181
emilmont 77:869cf507173a 182 /**
emilmont 77:869cf507173a 183 * @}
emilmont 77:869cf507173a 184 */
emilmont 77:869cf507173a 185
emilmont 77:869cf507173a 186 /**
emilmont 77:869cf507173a 187 * @}
emilmont 77:869cf507173a 188 */
emilmont 77:869cf507173a 189
emilmont 77:869cf507173a 190 #ifdef __cplusplus
emilmont 77:869cf507173a 191 }
emilmont 77:869cf507173a 192 #endif
emilmont 77:869cf507173a 193
emilmont 77:869cf507173a 194
emilmont 77:869cf507173a 195 #endif /* __STM32F4xx_HAL_PWR_EX_H */
emilmont 77:869cf507173a 196
emilmont 77:869cf507173a 197 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/