frederic blanc / mbed

/TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h substitute line 894 extern } by }

Fork of mbed by mbed official

TARGET_RZ_A1H/mtu2_iobitmask.h@93:9dd889aeda0e, 2014-12-05 (annotated)

Committer:
fblanc
Date:
Fri Dec 05 15:42:32 2014 +0000
Revision:
93:9dd889aeda0e
Parent:
92:4fc01daae5a5 
substitute line 894 extern } by }; /TARGET_K64F/TARGET_Freescale/TARGET_KPSDK_MCUS/TARGET_KPSDK_CODE/hal/adc/fsl_adc_hal.h

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 92:4fc01daae5a5 1 /*******************************************************************************
bogdanm 92:4fc01daae5a5 2 * DISCLAIMER
bogdanm 92:4fc01daae5a5 3 * This software is supplied by Renesas Electronics Corporation and is only
bogdanm 92:4fc01daae5a5 4 * intended for use with Renesas products. No other uses are authorized. This
bogdanm 92:4fc01daae5a5 5 * software is owned by Renesas Electronics Corporation and is protected under
bogdanm 92:4fc01daae5a5 6 * all applicable laws, including copyright laws.
bogdanm 92:4fc01daae5a5 7 * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING
bogdanm 92:4fc01daae5a5 8 * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT
bogdanm 92:4fc01daae5a5 9 * LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE
bogdanm 92:4fc01daae5a5 10 * AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED.
bogdanm 92:4fc01daae5a5 11 * TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS
bogdanm 92:4fc01daae5a5 12 * ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE
bogdanm 92:4fc01daae5a5 13 * FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR
bogdanm 92:4fc01daae5a5 14 * ANY REASON RELATED TO THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE
bogdanm 92:4fc01daae5a5 15 * BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
bogdanm 92:4fc01daae5a5 16 * Renesas reserves the right, without notice, to make changes to this software
bogdanm 92:4fc01daae5a5 17 * and to discontinue the availability of this software. By using this software,
bogdanm 92:4fc01daae5a5 18 * you agree to the additional terms and conditions found by accessing the
bogdanm 92:4fc01daae5a5 19 * following link:
bogdanm 92:4fc01daae5a5 20 * http://www.renesas.com/disclaimer
bogdanm 92:4fc01daae5a5 21 * Copyright (C) 2012 - 2014 Renesas Electronics Corporation. All rights reserved.
bogdanm 92:4fc01daae5a5 22 *******************************************************************************/
bogdanm 92:4fc01daae5a5 23 /*******************************************************************************
bogdanm 92:4fc01daae5a5 24 * File Name : mtu2_iobitmask.h
bogdanm 92:4fc01daae5a5 25 * $Rev: 1138 $
bogdanm 92:4fc01daae5a5 26 * $Date:: 2014-08-08 11:03:56 +0900#$
bogdanm 92:4fc01daae5a5 27 * Description : MTU2 register define header
bogdanm 92:4fc01daae5a5 28 *******************************************************************************/
bogdanm 92:4fc01daae5a5 29 #ifndef MTU2_IOBITMASK_H
bogdanm 92:4fc01daae5a5 30 #define MTU2_IOBITMASK_H
bogdanm 92:4fc01daae5a5 31
bogdanm 92:4fc01daae5a5 32
bogdanm 92:4fc01daae5a5 33 /* ==== Mask values for IO registers ==== */
bogdanm 92:4fc01daae5a5 34 #define MTU2_TCR_n_TPSC (0x07u)
bogdanm 92:4fc01daae5a5 35 #define MTU2_TCR_n_CKEG (0x18u)
bogdanm 92:4fc01daae5a5 36 #define MTU2_TCR_n_CCLR (0xE0u)
bogdanm 92:4fc01daae5a5 37
bogdanm 92:4fc01daae5a5 38 #define MTU2_TMDR_n_MD (0x0Fu)
bogdanm 92:4fc01daae5a5 39
bogdanm 92:4fc01daae5a5 40 #define MTU2_TIOR_2_IOA (0x0Fu)
bogdanm 92:4fc01daae5a5 41 #define MTU2_TIOR_2_IOB (0xF0u)
bogdanm 92:4fc01daae5a5 42
bogdanm 92:4fc01daae5a5 43 #define MTU2_TIER_n_TGIEA (0x01u)
bogdanm 92:4fc01daae5a5 44 #define MTU2_TIER_n_TGIEB (0x02u)
bogdanm 92:4fc01daae5a5 45 #define MTU2_TIER_n_TCIEV (0x10u)
bogdanm 92:4fc01daae5a5 46 #define MTU2_TIER_2_TCIEU (0x20u)
bogdanm 92:4fc01daae5a5 47 #define MTU2_TIER_n_TTGE (0x80u)
bogdanm 92:4fc01daae5a5 48
bogdanm 92:4fc01daae5a5 49 #define MTU2_TSR_n_TGFA (0x01u)
bogdanm 92:4fc01daae5a5 50 #define MTU2_TSR_n_TGFB (0x02u)
bogdanm 92:4fc01daae5a5 51 #define MTU2_TSR_n_TCFV (0x10u)
bogdanm 92:4fc01daae5a5 52 #define MTU2_TSR_2_TCFU (0x20u)
bogdanm 92:4fc01daae5a5 53 #define MTU2_TSR_2_TCFD (0x80u)
bogdanm 92:4fc01daae5a5 54
bogdanm 92:4fc01daae5a5 55 #define MTU2_TCNT_n_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 56
bogdanm 92:4fc01daae5a5 57 #define MTU2_TGRA_n_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 58
bogdanm 92:4fc01daae5a5 59 #define MTU2_TGRB_n_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 60
bogdanm 92:4fc01daae5a5 61 #define MTU2_TMDR_3_BFA (0x10u)
bogdanm 92:4fc01daae5a5 62 #define MTU2_TMDR_3_BFB (0x20u)
bogdanm 92:4fc01daae5a5 63
bogdanm 92:4fc01daae5a5 64 #define MTU2_TMDR_4_BFA (0x10u)
bogdanm 92:4fc01daae5a5 65 #define MTU2_TMDR_4_BFB (0x20u)
bogdanm 92:4fc01daae5a5 66
bogdanm 92:4fc01daae5a5 67 #define MTU2_TIORH_3_IOA (0x0Fu)
bogdanm 92:4fc01daae5a5 68 #define MTU2_TIORH_3_IOB (0xF0u)
bogdanm 92:4fc01daae5a5 69
bogdanm 92:4fc01daae5a5 70 #define MTU2_TIORL_3_IOC (0x0Fu)
bogdanm 92:4fc01daae5a5 71 #define MTU2_TIORL_3_IOD (0xF0u)
bogdanm 92:4fc01daae5a5 72
bogdanm 92:4fc01daae5a5 73 #define MTU2_TIORH_4_IOA (0x0Fu)
bogdanm 92:4fc01daae5a5 74 #define MTU2_TIORH_4_IOB (0xF0u)
bogdanm 92:4fc01daae5a5 75
bogdanm 92:4fc01daae5a5 76 #define MTU2_TIORL_4_IOC (0x0Fu)
bogdanm 92:4fc01daae5a5 77 #define MTU2_TIORL_4_IOD (0xF0u)
bogdanm 92:4fc01daae5a5 78
bogdanm 92:4fc01daae5a5 79 #define MTU2_TIER_3_TGIEC (0x04u)
bogdanm 92:4fc01daae5a5 80 #define MTU2_TIER_3_TGIED (0x08u)
bogdanm 92:4fc01daae5a5 81
bogdanm 92:4fc01daae5a5 82 #define MTU2_TIER_4_TGIEC (0x04u)
bogdanm 92:4fc01daae5a5 83 #define MTU2_TIER_4_TGIED (0x08u)
bogdanm 92:4fc01daae5a5 84 #define MTU2_TIER_4_TTGE2 (0x40u)
bogdanm 92:4fc01daae5a5 85
bogdanm 92:4fc01daae5a5 86 #define MTU2_TOER_OE3B (0x01u)
bogdanm 92:4fc01daae5a5 87 #define MTU2_TOER_OE4A (0x02u)
bogdanm 92:4fc01daae5a5 88 #define MTU2_TOER_OE4B (0x04u)
bogdanm 92:4fc01daae5a5 89 #define MTU2_TOER_OE3D (0x08u)
bogdanm 92:4fc01daae5a5 90 #define MTU2_TOER_OE4C (0x10u)
bogdanm 92:4fc01daae5a5 91 #define MTU2_TOER_OE4D (0x20u)
bogdanm 92:4fc01daae5a5 92
bogdanm 92:4fc01daae5a5 93 #define MTU2_TGCR_UF (0x01u)
bogdanm 92:4fc01daae5a5 94 #define MTU2_TGCR_VF (0x02u)
bogdanm 92:4fc01daae5a5 95 #define MTU2_TGCR_WF (0x04u)
bogdanm 92:4fc01daae5a5 96 #define MTU2_TGCR_FB (0x08u)
bogdanm 92:4fc01daae5a5 97 #define MTU2_TGCR_P (0x10u)
bogdanm 92:4fc01daae5a5 98 #define MTU2_TGCR_N (0x20u)
bogdanm 92:4fc01daae5a5 99 #define MTU2_TGCR_BDC (0x40u)
bogdanm 92:4fc01daae5a5 100
bogdanm 92:4fc01daae5a5 101 #define MTU2_TOCR1_OLSP (0x01u)
bogdanm 92:4fc01daae5a5 102 #define MTU2_TOCR1_OLSN (0x02u)
bogdanm 92:4fc01daae5a5 103 #define MTU2_TOCR1_TOCS (0x04u)
bogdanm 92:4fc01daae5a5 104 #define MTU2_TOCR1_TOCL (0x08u)
bogdanm 92:4fc01daae5a5 105 #define MTU2_TOCR1_PSYE (0x40u)
bogdanm 92:4fc01daae5a5 106
bogdanm 92:4fc01daae5a5 107 #define MTU2_TOCR2_OLS1P (0x01u)
bogdanm 92:4fc01daae5a5 108 #define MTU2_TOCR2_OLS1N (0x02u)
bogdanm 92:4fc01daae5a5 109 #define MTU2_TOCR2_OLS2P (0x04u)
bogdanm 92:4fc01daae5a5 110 #define MTU2_TOCR2_OLS2N (0x08u)
bogdanm 92:4fc01daae5a5 111 #define MTU2_TOCR2_OLS3P (0x10u)
bogdanm 92:4fc01daae5a5 112 #define MTU2_TOCR2_OLS3N (0x20u)
bogdanm 92:4fc01daae5a5 113 #define MTU2_TOCR2_BF (0xC0u)
bogdanm 92:4fc01daae5a5 114
bogdanm 92:4fc01daae5a5 115 #define MTU2_TCDR_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 116
bogdanm 92:4fc01daae5a5 117 #define MTU2_TDDR_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 118
bogdanm 92:4fc01daae5a5 119 #define MTU2_TCNTS_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 120
bogdanm 92:4fc01daae5a5 121 #define MTU2_TCBR_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 122
bogdanm 92:4fc01daae5a5 123 #define MTU2_TGRC_3_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 124
bogdanm 92:4fc01daae5a5 125 #define MTU2_TGRD_3_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 126
bogdanm 92:4fc01daae5a5 127 #define MTU2_TGRC_4_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 128
bogdanm 92:4fc01daae5a5 129 #define MTU2_TGRD_4_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 130
bogdanm 92:4fc01daae5a5 131 #define MTU2_TSR_3_TGFC (0x04u)
bogdanm 92:4fc01daae5a5 132 #define MTU2_TSR_3_TGFD (0x08u)
bogdanm 92:4fc01daae5a5 133 #define MTU2_TSR_3_TCFD (0x80u)
bogdanm 92:4fc01daae5a5 134
bogdanm 92:4fc01daae5a5 135 #define MTU2_TSR_4_TGFC (0x04u)
bogdanm 92:4fc01daae5a5 136 #define MTU2_TSR_4_TGFD (0x08u)
bogdanm 92:4fc01daae5a5 137 #define MTU2_TSR_4_TCFD (0x80u)
bogdanm 92:4fc01daae5a5 138
bogdanm 92:4fc01daae5a5 139 #define MTU2_TITCR_4VCOR (0x07u)
bogdanm 92:4fc01daae5a5 140 #define MTU2_TITCR_T4VEN (0x08u)
bogdanm 92:4fc01daae5a5 141 #define MTU2_TITCR_3ACOR (0x70u)
bogdanm 92:4fc01daae5a5 142 #define MTU2_TITCR_T3AEN (0x80u)
bogdanm 92:4fc01daae5a5 143
bogdanm 92:4fc01daae5a5 144 #define MTU2_TITCNT_4VCNT (0x07u)
bogdanm 92:4fc01daae5a5 145 #define MTU2_TITCNT_3ACNT (0x70u)
bogdanm 92:4fc01daae5a5 146
bogdanm 92:4fc01daae5a5 147 #define MTU2_TBTER_BTE (0x03u)
bogdanm 92:4fc01daae5a5 148
bogdanm 92:4fc01daae5a5 149 #define MTU2_TDER_TDER (0x01u)
bogdanm 92:4fc01daae5a5 150
bogdanm 92:4fc01daae5a5 151 #define MTU2_TOLBR_OLS1P (0x01u)
bogdanm 92:4fc01daae5a5 152 #define MTU2_TOLBR_OLS1N (0x02u)
bogdanm 92:4fc01daae5a5 153 #define MTU2_TOLBR_OLS2P (0x04u)
bogdanm 92:4fc01daae5a5 154 #define MTU2_TOLBR_OLS2N (0x08u)
bogdanm 92:4fc01daae5a5 155 #define MTU2_TOLBR_OLS3P (0x10u)
bogdanm 92:4fc01daae5a5 156 #define MTU2_TOLBR_OLS3N (0x20u)
bogdanm 92:4fc01daae5a5 157
bogdanm 92:4fc01daae5a5 158 #define MTU2_TBTM_3_TTSA (0x01u)
bogdanm 92:4fc01daae5a5 159 #define MTU2_TBTM_3_TTSB (0x02u)
bogdanm 92:4fc01daae5a5 160
bogdanm 92:4fc01daae5a5 161 #define MTU2_TBTM_4_TTSA (0x01u)
bogdanm 92:4fc01daae5a5 162 #define MTU2_TBTM_4_TTSB (0x02u)
bogdanm 92:4fc01daae5a5 163
bogdanm 92:4fc01daae5a5 164 #define MTU2_TADCR_ITB4VE (0x0001u)
bogdanm 92:4fc01daae5a5 165 #define MTU2_TADCR_ITB3AE (0x0002u)
bogdanm 92:4fc01daae5a5 166 #define MTU2_TADCR_ITA4VE (0x0004u)
bogdanm 92:4fc01daae5a5 167 #define MTU2_TADCR_ITA3AE (0x0008u)
bogdanm 92:4fc01daae5a5 168 #define MTU2_TADCR_DT4BE (0x0010u)
bogdanm 92:4fc01daae5a5 169 #define MTU2_TADCR_UT4BE (0x0020u)
bogdanm 92:4fc01daae5a5 170 #define MTU2_TADCR_DT4AE (0x0040u)
bogdanm 92:4fc01daae5a5 171 #define MTU2_TADCR_UT4AE (0x0080u)
bogdanm 92:4fc01daae5a5 172 #define MTU2_TADCR_BF (0xC000u)
bogdanm 92:4fc01daae5a5 173
bogdanm 92:4fc01daae5a5 174 #define MTU2_TADCORA_4_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 175
bogdanm 92:4fc01daae5a5 176 #define MTU2_TADCORB_4_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 177
bogdanm 92:4fc01daae5a5 178 #define MTU2_TADCOBRA_4_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 179
bogdanm 92:4fc01daae5a5 180 #define MTU2_TADCOBRB_4_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 181
bogdanm 92:4fc01daae5a5 182 #define MTU2_TWCR_WRE (0x01u)
bogdanm 92:4fc01daae5a5 183 #define MTU2_TWCR_CCE (0x80u)
bogdanm 92:4fc01daae5a5 184
bogdanm 92:4fc01daae5a5 185 #define MTU2_TSTR_CST0 (0x01u)
bogdanm 92:4fc01daae5a5 186 #define MTU2_TSTR_CST1 (0x02u)
bogdanm 92:4fc01daae5a5 187 #define MTU2_TSTR_CST2 (0x04u)
bogdanm 92:4fc01daae5a5 188 #define MTU2_TSTR_CST3 (0x40u)
bogdanm 92:4fc01daae5a5 189 #define MTU2_TSTR_CST4 (0x80u)
bogdanm 92:4fc01daae5a5 190
bogdanm 92:4fc01daae5a5 191 #define MTU2_TSYR_SYNC0 (0x01u)
bogdanm 92:4fc01daae5a5 192 #define MTU2_TSYR_SYNC1 (0x02u)
bogdanm 92:4fc01daae5a5 193 #define MTU2_TSYR_SYNC2 (0x04u)
bogdanm 92:4fc01daae5a5 194 #define MTU2_TSYR_SYNC3 (0x40u)
bogdanm 92:4fc01daae5a5 195 #define MTU2_TSYR_SYNC4 (0x80u)
bogdanm 92:4fc01daae5a5 196
bogdanm 92:4fc01daae5a5 197 #define MTU2_TRWER_RWE (0x01u)
bogdanm 92:4fc01daae5a5 198
bogdanm 92:4fc01daae5a5 199 #define MTU2_TMDR_0_BFA (0x10u)
bogdanm 92:4fc01daae5a5 200 #define MTU2_TMDR_0_BFB (0x20u)
bogdanm 92:4fc01daae5a5 201 #define MTU2_TMDR_0_BFE (0x40u)
bogdanm 92:4fc01daae5a5 202
bogdanm 92:4fc01daae5a5 203 #define MTU2_TIORH_0_IOA (0x0Fu)
bogdanm 92:4fc01daae5a5 204 #define MTU2_TIORH_0_IOB (0xF0u)
bogdanm 92:4fc01daae5a5 205
bogdanm 92:4fc01daae5a5 206 #define MTU2_TIORL_0_IOC (0x0Fu)
bogdanm 92:4fc01daae5a5 207 #define MTU2_TIORL_0_IOD (0xF0u)
bogdanm 92:4fc01daae5a5 208
bogdanm 92:4fc01daae5a5 209 #define MTU2_TIER_0_TGIEC (0x04u)
bogdanm 92:4fc01daae5a5 210 #define MTU2_TIER_0_TGIED (0x08u)
bogdanm 92:4fc01daae5a5 211
bogdanm 92:4fc01daae5a5 212 #define MTU2_TSR_0_TGFC (0x04u)
bogdanm 92:4fc01daae5a5 213 #define MTU2_TSR_0_TGFD (0x08u)
bogdanm 92:4fc01daae5a5 214
bogdanm 92:4fc01daae5a5 215 #define MTU2_TGRC_0_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 216
bogdanm 92:4fc01daae5a5 217 #define MTU2_TGRD_0_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 218
bogdanm 92:4fc01daae5a5 219 #define MTU2_TGRE_0_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 220
bogdanm 92:4fc01daae5a5 221 #define MTU2_TGRF_0_D (0xFFFFu)
bogdanm 92:4fc01daae5a5 222
bogdanm 92:4fc01daae5a5 223 #define MTU2_TIER2_0_TGIEE (0x01u)
bogdanm 92:4fc01daae5a5 224 #define MTU2_TIER2_0_TGIEF (0x02u)
bogdanm 92:4fc01daae5a5 225
bogdanm 92:4fc01daae5a5 226 #define MTU2_TSR2_0_TGFE (0x01u)
bogdanm 92:4fc01daae5a5 227 #define MTU2_TSR2_0_TGFF (0x02u)
bogdanm 92:4fc01daae5a5 228
bogdanm 92:4fc01daae5a5 229 #define MTU2_TBTM_0_TTSA (0x01u)
bogdanm 92:4fc01daae5a5 230 #define MTU2_TBTM_0_TTSB (0x02u)
bogdanm 92:4fc01daae5a5 231 #define MTU2_TBTM_0_TTSE (0x04u)
bogdanm 92:4fc01daae5a5 232
bogdanm 92:4fc01daae5a5 233 #define MTU2_TIOR_1_IOA (0x0Fu)
bogdanm 92:4fc01daae5a5 234 #define MTU2_TIOR_1_IOB (0xF0u)
bogdanm 92:4fc01daae5a5 235
bogdanm 92:4fc01daae5a5 236 #define MTU2_TIER_1_TCIEU (0x20u)
bogdanm 92:4fc01daae5a5 237
bogdanm 92:4fc01daae5a5 238 #define MTU2_TSR_1_TCFU (0x20u)
bogdanm 92:4fc01daae5a5 239 #define MTU2_TSR_1_TCFD (0x80u)
bogdanm 92:4fc01daae5a5 240
bogdanm 92:4fc01daae5a5 241 #define MTU2_TICCR_I1AE (0x01u)
bogdanm 92:4fc01daae5a5 242 #define MTU2_TICCR_I1BE (0x02u)
bogdanm 92:4fc01daae5a5 243 #define MTU2_TICCR_I2AE (0x04u)
bogdanm 92:4fc01daae5a5 244 #define MTU2_TICCR_I2BE (0x08u)
bogdanm 92:4fc01daae5a5 245
bogdanm 92:4fc01daae5a5 246
bogdanm 92:4fc01daae5a5 247 /* ==== Shift values for IO registers ==== */
bogdanm 92:4fc01daae5a5 248 #define MTU2_TCR_n_TPSC_SHIFT (0u)
bogdanm 92:4fc01daae5a5 249 #define MTU2_TCR_n_CKEG_SHIFT (3u)
bogdanm 92:4fc01daae5a5 250 #define MTU2_TCR_n_CCLR_SHIFT (5u)
bogdanm 92:4fc01daae5a5 251
bogdanm 92:4fc01daae5a5 252 #define MTU2_TMDR_n_MD_SHIFT (0u)
bogdanm 92:4fc01daae5a5 253
bogdanm 92:4fc01daae5a5 254 #define MTU2_TIOR_2_IOA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 255 #define MTU2_TIOR_2_IOB_SHIFT (4u)
bogdanm 92:4fc01daae5a5 256
bogdanm 92:4fc01daae5a5 257 #define MTU2_TIER_n_TGIEA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 258 #define MTU2_TIER_n_TGIEB_SHIFT (1u)
bogdanm 92:4fc01daae5a5 259 #define MTU2_TIER_n_TCIEV_SHIFT (4u)
bogdanm 92:4fc01daae5a5 260 #define MTU2_TIER_2_TCIEU_SHIFT (5u)
bogdanm 92:4fc01daae5a5 261 #define MTU2_TIER_n_TTGE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 262
bogdanm 92:4fc01daae5a5 263 #define MTU2_TSR_n_TGFA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 264 #define MTU2_TSR_n_TGFB_SHIFT (1u)
bogdanm 92:4fc01daae5a5 265 #define MTU2_TSR_n_TCFV_SHIFT (4u)
bogdanm 92:4fc01daae5a5 266 #define MTU2_TSR_2_TCFU_SHIFT (5u)
bogdanm 92:4fc01daae5a5 267 #define MTU2_TSR_2_TCFD_SHIFT (7u)
bogdanm 92:4fc01daae5a5 268
bogdanm 92:4fc01daae5a5 269 #define MTU2_TCNT_n_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 270
bogdanm 92:4fc01daae5a5 271 #define MTU2_TGRA_n_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 272
bogdanm 92:4fc01daae5a5 273 #define MTU2_TGRB_n_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 274
bogdanm 92:4fc01daae5a5 275 #define MTU2_TMDR_3_BFA_SHIFT (4u)
bogdanm 92:4fc01daae5a5 276 #define MTU2_TMDR_3_BFB_SHIFT (5u)
bogdanm 92:4fc01daae5a5 277
bogdanm 92:4fc01daae5a5 278 #define MTU2_TMDR_4_BFA_SHIFT (4u)
bogdanm 92:4fc01daae5a5 279 #define MTU2_TMDR_4_BFB_SHIFT (5u)
bogdanm 92:4fc01daae5a5 280
bogdanm 92:4fc01daae5a5 281 #define MTU2_TIORH_3_IOA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 282 #define MTU2_TIORH_3_IOB_SHIFT (4u)
bogdanm 92:4fc01daae5a5 283
bogdanm 92:4fc01daae5a5 284 #define MTU2_TIORL_3_IOC_SHIFT (0u)
bogdanm 92:4fc01daae5a5 285 #define MTU2_TIORL_3_IOD_SHIFT (4u)
bogdanm 92:4fc01daae5a5 286
bogdanm 92:4fc01daae5a5 287 #define MTU2_TIORH_4_IOA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 288 #define MTU2_TIORH_4_IOB_SHIFT (4u)
bogdanm 92:4fc01daae5a5 289
bogdanm 92:4fc01daae5a5 290 #define MTU2_TIORL_4_IOC_SHIFT (0u)
bogdanm 92:4fc01daae5a5 291 #define MTU2_TIORL_4_IOD_SHIFT (4u)
bogdanm 92:4fc01daae5a5 292
bogdanm 92:4fc01daae5a5 293 #define MTU2_TIER_3_TGIEC_SHIFT (2u)
bogdanm 92:4fc01daae5a5 294 #define MTU2_TIER_3_TGIED_SHIFT (3u)
bogdanm 92:4fc01daae5a5 295
bogdanm 92:4fc01daae5a5 296 #define MTU2_TIER_4_TGIEC_SHIFT (2u)
bogdanm 92:4fc01daae5a5 297 #define MTU2_TIER_4_TGIED_SHIFT (3u)
bogdanm 92:4fc01daae5a5 298 #define MTU2_TIER_4_TTGE2_SHIFT (6u)
bogdanm 92:4fc01daae5a5 299
bogdanm 92:4fc01daae5a5 300 #define MTU2_TOER_OE3B_SHIFT (0u)
bogdanm 92:4fc01daae5a5 301 #define MTU2_TOER_OE4A_SHIFT (1u)
bogdanm 92:4fc01daae5a5 302 #define MTU2_TOER_OE4B_SHIFT (2u)
bogdanm 92:4fc01daae5a5 303 #define MTU2_TOER_OE3D_SHIFT (3u)
bogdanm 92:4fc01daae5a5 304 #define MTU2_TOER_OE4C_SHIFT (4u)
bogdanm 92:4fc01daae5a5 305 #define MTU2_TOER_OE4D_SHIFT (5u)
bogdanm 92:4fc01daae5a5 306
bogdanm 92:4fc01daae5a5 307 #define MTU2_TGCR_UF_SHIFT (0u)
bogdanm 92:4fc01daae5a5 308 #define MTU2_TGCR_VF_SHIFT (1u)
bogdanm 92:4fc01daae5a5 309 #define MTU2_TGCR_WF_SHIFT (2u)
bogdanm 92:4fc01daae5a5 310 #define MTU2_TGCR_FB_SHIFT (3u)
bogdanm 92:4fc01daae5a5 311 #define MTU2_TGCR_P_SHIFT (4u)
bogdanm 92:4fc01daae5a5 312 #define MTU2_TGCR_N_SHIFT (5u)
bogdanm 92:4fc01daae5a5 313 #define MTU2_TGCR_BDC_SHIFT (6u)
bogdanm 92:4fc01daae5a5 314
bogdanm 92:4fc01daae5a5 315 #define MTU2_TOCR1_OLSP_SHIFT (0u)
bogdanm 92:4fc01daae5a5 316 #define MTU2_TOCR1_OLSN_SHIFT (1u)
bogdanm 92:4fc01daae5a5 317 #define MTU2_TOCR1_TOCS_SHIFT (2u)
bogdanm 92:4fc01daae5a5 318 #define MTU2_TOCR1_TOCL_SHIFT (3u)
bogdanm 92:4fc01daae5a5 319 #define MTU2_TOCR1_PSYE_SHIFT (6u)
bogdanm 92:4fc01daae5a5 320
bogdanm 92:4fc01daae5a5 321 #define MTU2_TOCR2_OLS1P_SHIFT (0u)
bogdanm 92:4fc01daae5a5 322 #define MTU2_TOCR2_OLS1N_SHIFT (1u)
bogdanm 92:4fc01daae5a5 323 #define MTU2_TOCR2_OLS2P_SHIFT (2u)
bogdanm 92:4fc01daae5a5 324 #define MTU2_TOCR2_OLS2N_SHIFT (3u)
bogdanm 92:4fc01daae5a5 325 #define MTU2_TOCR2_OLS3P_SHIFT (4u)
bogdanm 92:4fc01daae5a5 326 #define MTU2_TOCR2_OLS3N_SHIFT (5u)
bogdanm 92:4fc01daae5a5 327 #define MTU2_TOCR2_BF_SHIFT (6u)
bogdanm 92:4fc01daae5a5 328
bogdanm 92:4fc01daae5a5 329 #define MTU2_TCDR_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 330
bogdanm 92:4fc01daae5a5 331 #define MTU2_TDDR_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 332
bogdanm 92:4fc01daae5a5 333 #define MTU2_TCNTS_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 334
bogdanm 92:4fc01daae5a5 335 #define MTU2_TCBR_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 336
bogdanm 92:4fc01daae5a5 337 #define MTU2_TGRC_3_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 338
bogdanm 92:4fc01daae5a5 339 #define MTU2_TGRD_3_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 340
bogdanm 92:4fc01daae5a5 341 #define MTU2_TGRC_4_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 342
bogdanm 92:4fc01daae5a5 343 #define MTU2_TGRD_4_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 344
bogdanm 92:4fc01daae5a5 345 #define MTU2_TSR_3_TGFC_SHIFT (2u)
bogdanm 92:4fc01daae5a5 346 #define MTU2_TSR_3_TGFD_SHIFT (3u)
bogdanm 92:4fc01daae5a5 347 #define MTU2_TSR_3_TCFD_SHIFT (7u)
bogdanm 92:4fc01daae5a5 348
bogdanm 92:4fc01daae5a5 349 #define MTU2_TSR_4_TGFC_SHIFT (2u)
bogdanm 92:4fc01daae5a5 350 #define MTU2_TSR_4_TGFD_SHIFT (3u)
bogdanm 92:4fc01daae5a5 351 #define MTU2_TSR_4_TCFD_SHIFT (7u)
bogdanm 92:4fc01daae5a5 352
bogdanm 92:4fc01daae5a5 353 #define MTU2_TITCR_4VCOR_SHIFT (0u)
bogdanm 92:4fc01daae5a5 354 #define MTU2_TITCR_T4VEN_SHIFT (3u)
bogdanm 92:4fc01daae5a5 355 #define MTU2_TITCR_3ACOR_SHIFT (4u)
bogdanm 92:4fc01daae5a5 356 #define MTU2_TITCR_T3AEN_SHIFT (7u)
bogdanm 92:4fc01daae5a5 357
bogdanm 92:4fc01daae5a5 358 #define MTU2_TITCNT_4VCNT_SHIFT (0u)
bogdanm 92:4fc01daae5a5 359 #define MTU2_TITCNT_3ACNT_SHIFT (4u)
bogdanm 92:4fc01daae5a5 360
bogdanm 92:4fc01daae5a5 361 #define MTU2_TBTER_BTE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 362
bogdanm 92:4fc01daae5a5 363 #define MTU2_TDER_TDER_SHIFT (0u)
bogdanm 92:4fc01daae5a5 364
bogdanm 92:4fc01daae5a5 365 #define MTU2_TOLBR_OLS1P_SHIFT (0u)
bogdanm 92:4fc01daae5a5 366 #define MTU2_TOLBR_OLS1N_SHIFT (1u)
bogdanm 92:4fc01daae5a5 367 #define MTU2_TOLBR_OLS2P_SHIFT (2u)
bogdanm 92:4fc01daae5a5 368 #define MTU2_TOLBR_OLS2N_SHIFT (3u)
bogdanm 92:4fc01daae5a5 369 #define MTU2_TOLBR_OLS3P_SHIFT (4u)
bogdanm 92:4fc01daae5a5 370 #define MTU2_TOLBR_OLS3N_SHIFT (5u)
bogdanm 92:4fc01daae5a5 371
bogdanm 92:4fc01daae5a5 372 #define MTU2_TBTM_3_TTSA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 373 #define MTU2_TBTM_3_TTSB_SHIFT (1u)
bogdanm 92:4fc01daae5a5 374
bogdanm 92:4fc01daae5a5 375 #define MTU2_TBTM_4_TTSA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 376 #define MTU2_TBTM_4_TTSB_SHIFT (1u)
bogdanm 92:4fc01daae5a5 377
bogdanm 92:4fc01daae5a5 378 #define MTU2_TADCR_ITB4VE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 379 #define MTU2_TADCR_ITB3AE_SHIFT (1u)
bogdanm 92:4fc01daae5a5 380 #define MTU2_TADCR_ITA4VE_SHIFT (2u)
bogdanm 92:4fc01daae5a5 381 #define MTU2_TADCR_ITA3AE_SHIFT (3u)
bogdanm 92:4fc01daae5a5 382 #define MTU2_TADCR_DT4BE_SHIFT (4u)
bogdanm 92:4fc01daae5a5 383 #define MTU2_TADCR_UT4BE_SHIFT (5u)
bogdanm 92:4fc01daae5a5 384 #define MTU2_TADCR_DT4AE_SHIFT (6u)
bogdanm 92:4fc01daae5a5 385 #define MTU2_TADCR_UT4AE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 386 #define MTU2_TADCR_BF_SHIFT (14u)
bogdanm 92:4fc01daae5a5 387
bogdanm 92:4fc01daae5a5 388 #define MTU2_TADCORA_4_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 389
bogdanm 92:4fc01daae5a5 390 #define MTU2_TADCORB_4_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 391
bogdanm 92:4fc01daae5a5 392 #define MTU2_TADCOBRA_4_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 393
bogdanm 92:4fc01daae5a5 394 #define MTU2_TADCOBRB_4_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 395
bogdanm 92:4fc01daae5a5 396 #define MTU2_TWCR_WRE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 397 #define MTU2_TWCR_CCE_SHIFT (7u)
bogdanm 92:4fc01daae5a5 398
bogdanm 92:4fc01daae5a5 399 #define MTU2_TSTR_CST0_SHIFT (0u)
bogdanm 92:4fc01daae5a5 400 #define MTU2_TSTR_CST1_SHIFT (1u)
bogdanm 92:4fc01daae5a5 401 #define MTU2_TSTR_CST2_SHIFT (2u)
bogdanm 92:4fc01daae5a5 402 #define MTU2_TSTR_CST3_SHIFT (6u)
bogdanm 92:4fc01daae5a5 403 #define MTU2_TSTR_CST4_SHIFT (7u)
bogdanm 92:4fc01daae5a5 404
bogdanm 92:4fc01daae5a5 405 #define MTU2_TSYR_SYNC0_SHIFT (0u)
bogdanm 92:4fc01daae5a5 406 #define MTU2_TSYR_SYNC1_SHIFT (1u)
bogdanm 92:4fc01daae5a5 407 #define MTU2_TSYR_SYNC2_SHIFT (2u)
bogdanm 92:4fc01daae5a5 408 #define MTU2_TSYR_SYNC3_SHIFT (6u)
bogdanm 92:4fc01daae5a5 409 #define MTU2_TSYR_SYNC4_SHIFT (7u)
bogdanm 92:4fc01daae5a5 410
bogdanm 92:4fc01daae5a5 411 #define MTU2_TRWER_RWE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 412
bogdanm 92:4fc01daae5a5 413 #define MTU2_TMDR_0_BFA_SHIFT (4u)
bogdanm 92:4fc01daae5a5 414 #define MTU2_TMDR_0_BFB_SHIFT (5u)
bogdanm 92:4fc01daae5a5 415 #define MTU2_TMDR_0_BFE_SHIFT (6u)
bogdanm 92:4fc01daae5a5 416
bogdanm 92:4fc01daae5a5 417 #define MTU2_TIORH_0_IOA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 418 #define MTU2_TIORH_0_IOB_SHIFT (4u)
bogdanm 92:4fc01daae5a5 419
bogdanm 92:4fc01daae5a5 420 #define MTU2_TIORL_0_IOC_SHIFT (0u)
bogdanm 92:4fc01daae5a5 421 #define MTU2_TIORL_0_IOD_SHIFT (4u)
bogdanm 92:4fc01daae5a5 422
bogdanm 92:4fc01daae5a5 423 #define MTU2_TIER_0_TGIEC_SHIFT (2u)
bogdanm 92:4fc01daae5a5 424 #define MTU2_TIER_0_TGIED_SHIFT (3u)
bogdanm 92:4fc01daae5a5 425
bogdanm 92:4fc01daae5a5 426 #define MTU2_TSR_0_TGFC_SHIFT (2u)
bogdanm 92:4fc01daae5a5 427 #define MTU2_TSR_0_TGFD_SHIFT (3u)
bogdanm 92:4fc01daae5a5 428
bogdanm 92:4fc01daae5a5 429 #define MTU2_TGRC_0_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 430
bogdanm 92:4fc01daae5a5 431 #define MTU2_TGRD_0_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 432
bogdanm 92:4fc01daae5a5 433 #define MTU2_TGRE_0_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 434
bogdanm 92:4fc01daae5a5 435 #define MTU2_TGRF_0_D_SHIFT (0u)
bogdanm 92:4fc01daae5a5 436
bogdanm 92:4fc01daae5a5 437 #define MTU2_TIER2_0_TGIEE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 438 #define MTU2_TIER2_0_TGIEF_SHIFT (1u)
bogdanm 92:4fc01daae5a5 439
bogdanm 92:4fc01daae5a5 440 #define MTU2_TSR2_0_TGFE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 441 #define MTU2_TSR2_0_TGFF_SHIFT (1u)
bogdanm 92:4fc01daae5a5 442
bogdanm 92:4fc01daae5a5 443 #define MTU2_TBTM_0_TTSA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 444 #define MTU2_TBTM_0_TTSB_SHIFT (1u)
bogdanm 92:4fc01daae5a5 445 #define MTU2_TBTM_0_TTSE_SHIFT (2u)
bogdanm 92:4fc01daae5a5 446
bogdanm 92:4fc01daae5a5 447 #define MTU2_TIOR_1_IOA_SHIFT (0u)
bogdanm 92:4fc01daae5a5 448 #define MTU2_TIOR_1_IOB_SHIFT (4u)
bogdanm 92:4fc01daae5a5 449
bogdanm 92:4fc01daae5a5 450 #define MTU2_TIER_1_TCIEU_SHIFT (5u)
bogdanm 92:4fc01daae5a5 451
bogdanm 92:4fc01daae5a5 452 #define MTU2_TSR_1_TCFU_SHIFT (5u)
bogdanm 92:4fc01daae5a5 453 #define MTU2_TSR_1_TCFD_SHIFT (7u)
bogdanm 92:4fc01daae5a5 454
bogdanm 92:4fc01daae5a5 455 #define MTU2_TICCR_I1AE_SHIFT (0u)
bogdanm 92:4fc01daae5a5 456 #define MTU2_TICCR_I1BE_SHIFT (1u)
bogdanm 92:4fc01daae5a5 457 #define MTU2_TICCR_I2AE_SHIFT (2u)
bogdanm 92:4fc01daae5a5 458 #define MTU2_TICCR_I2BE_SHIFT (3u)
bogdanm 92:4fc01daae5a5 459
bogdanm 92:4fc01daae5a5 460
bogdanm 92:4fc01daae5a5 461 #endif /* MTU2_IOBITMASK_H */
bogdanm 92:4fc01daae5a5 462 /* End of File */